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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id d16sm3100480pgb.12.2021.02.20.06.48.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Feb 2021 06:48:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xFusbs9cqhSOHLyzRwhjUugqc4UxfzCYlHyTzr24kaY=; b=MNfKSOun6WEuISPPawSXUVcaDsShffjxChhwLZlm3I8unnq0hzJ7pDX8JismPPCJFo QzHcDf1885s3rraWGbABrtOj6DZqZSDL9iTjbNcjVfKyGkHHZG24ax0j5R2cDbOgozLl J+pWsfYQbgEl1vyojQdCVseX5cTFeEr3deWrTfmXO2IffCME56Uwz+T8gr+ernsG2fPf hX1mDcJl0KkCp9fhqB6LNy4ItK8aEmfISWNNLwq8ZeBtxlp5bHLxvOZiAU4bRRZOjLsU scUG+jn1kE8gijv9FPtsep2zkuIQrb81Z+8bwWwiWWS8RX2pVaXBPWH/qFZxRst0trPR Gdig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xFusbs9cqhSOHLyzRwhjUugqc4UxfzCYlHyTzr24kaY=; b=KA5dEG6rJFqtBQHYqnaXsUe1iU7nmphjbVqBCA4VCNyc+/hn65BERf+oAsShlkzM5q i7eUfJbn/rmalqMder3hNwAHD1+ICLqOKywPyGYZ8V2GpM9dMXqlLmWVOJJY43MIys/7 ah2eRece7P4ohA/iegir1830Icx+YoJkcKH1cupWsFblSR2fRHbfbJfedQb8Fm3NpiCL uCxAWEsgfeZaUqVl+nNLMJvPVCgjHOoAUU91BMQMeOu1nbdw4bjXGM+ldVSJErAHMuUW o1rJopAtnbHmoe+YoYaQ3aG0uiVlfWxmI/3qCQ7kEZrCIOJMkcg/ze+aTlUQdYa3EYpe T4kQ== X-Gm-Message-State: AOAM533bAGumhLiS8KZDQhQdYEEL477vrHcsM2/gbWhsdRQPivPYktHw HE6YMdCTUAWUVfU9CykeckAoYcMie2w= X-Google-Smtp-Source: ABdhPJzCiwETQ59wukJIaX5Q4kTfkqspkT4JgsTYw2Mlo2O20fVRJ1XN9E+/eR1CrBgoqyPC16V9uQ== X-Received: by 2002:a17:90a:ab07:: with SMTP id m7mr14266797pjq.74.1613832501137; Sat, 20 Feb 2021 06:48:21 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 1/4] hw/riscv: Drop 'struct MemmapEntry' Date: Sat, 20 Feb 2021 22:48:04 +0800 Message-Id: <20210220144807.819-2-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210220144807.819-1-bmeng.cn@gmail.com> References: <20210220144807.819-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) From: Bin Meng There is already a MemMapEntry type defined in hwaddr.h. Let's drop the RISC-V defined `struct MemmapEntry` and use the existing one. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- (no changes since v1) hw/riscv/microchip_pfsoc.c | 9 +++------ hw/riscv/opentitan.c | 9 +++------ hw/riscv/sifive_e.c | 9 +++------ hw/riscv/sifive_u.c | 11 ++++------- hw/riscv/spike.c | 9 +++------ hw/riscv/virt.c | 9 +++------ 6 files changed, 19 insertions(+), 37 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index e952b49e8c..266f1c3342 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -86,10 +86,7 @@ * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.= htm * describes the complete IOSCB modules memory maps */ -static const struct MemmapEntry { - hwaddr base; - hwaddr size; -} microchip_pfsoc_memmap[] =3D { +static const MemMapEntry microchip_pfsoc_memmap[] =3D { [MICROCHIP_PFSOC_RSVD0] =3D { 0x0, 0x100 }, [MICROCHIP_PFSOC_DEBUG] =3D { 0x100, 0xf00 }, [MICROCHIP_PFSOC_E51_DTIM] =3D { 0x1000000, 0x2000 }, @@ -182,7 +179,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *de= v, Error **errp) { MachineState *ms =3D MACHINE(qdev_get_machine()); MicrochipPFSoCState *s =3D MICROCHIP_PFSOC(dev); - const struct MemmapEntry *memmap =3D microchip_pfsoc_memmap; + const MemMapEntry *memmap =3D microchip_pfsoc_memmap; MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *rsvd0_mem =3D g_new(MemoryRegion, 1); MemoryRegion *e51_dtim_mem =3D g_new(MemoryRegion, 1); @@ -451,7 +448,7 @@ type_init(microchip_pfsoc_soc_register_types) static void microchip_icicle_kit_machine_init(MachineState *machine) { MachineClass *mc =3D MACHINE_GET_CLASS(machine); - const struct MemmapEntry *memmap =3D microchip_pfsoc_memmap; + const MemMapEntry *memmap =3D microchip_pfsoc_memmap; MicrochipIcicleKitState *s =3D MICROCHIP_ICICLE_KIT_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *mem_low =3D g_new(MemoryRegion, 1); diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index af3456932f..e168bffe69 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -28,10 +28,7 @@ #include "qemu/units.h" #include "sysemu/sysemu.h" =20 -static const struct MemmapEntry { - hwaddr base; - hwaddr size; -} ibex_memmap[] =3D { +static const MemMapEntry ibex_memmap[] =3D { [IBEX_DEV_ROM] =3D { 0x00008000, 16 * KiB }, [IBEX_DEV_RAM] =3D { 0x10000000, 0x10000 }, [IBEX_DEV_FLASH] =3D { 0x20000000, 0x80000 }, @@ -66,7 +63,7 @@ static const struct MemmapEntry { =20 static void opentitan_board_init(MachineState *machine) { - const struct MemmapEntry *memmap =3D ibex_memmap; + const MemMapEntry *memmap =3D ibex_memmap; OpenTitanState *s =3D g_new0(OpenTitanState, 1); MemoryRegion *sys_mem =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); @@ -114,7 +111,7 @@ static void lowrisc_ibex_soc_init(Object *obj) =20 static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) { - const struct MemmapEntry *memmap =3D ibex_memmap; + const MemMapEntry *memmap =3D ibex_memmap; MachineState *ms =3D MACHINE(qdev_get_machine()); LowRISCIbexSoCState *s =3D RISCV_IBEX_SOC(dev_soc); MemoryRegion *sys_mem =3D get_system_memory(); diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 59bac4cc9a..f939bcf9ea 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -50,10 +50,7 @@ #include "sysemu/sysemu.h" #include "exec/address-spaces.h" =20 -static const struct MemmapEntry { - hwaddr base; - hwaddr size; -} sifive_e_memmap[] =3D { +static MemMapEntry sifive_e_memmap[] =3D { [SIFIVE_E_DEV_DEBUG] =3D { 0x0, 0x1000 }, [SIFIVE_E_DEV_MROM] =3D { 0x1000, 0x2000 }, [SIFIVE_E_DEV_OTP] =3D { 0x20000, 0x2000 }, @@ -77,7 +74,7 @@ static const struct MemmapEntry { =20 static void sifive_e_machine_init(MachineState *machine) { - const struct MemmapEntry *memmap =3D sifive_e_memmap; + const MemMapEntry *memmap =3D sifive_e_memmap; =20 SiFiveEState *s =3D RISCV_E_MACHINE(machine); MemoryRegion *sys_mem =3D get_system_memory(); @@ -187,7 +184,7 @@ static void sifive_e_soc_init(Object *obj) static void sifive_e_soc_realize(DeviceState *dev, Error **errp) { MachineState *ms =3D MACHINE(qdev_get_machine()); - const struct MemmapEntry *memmap =3D sifive_e_memmap; + const MemMapEntry *memmap =3D sifive_e_memmap; SiFiveESoCState *s =3D RISCV_E_SOC(dev); MemoryRegion *sys_mem =3D get_system_memory(); =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 6c1158a848..7b59942369 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -63,10 +63,7 @@ =20 #include =20 -static const struct MemmapEntry { - hwaddr base; - hwaddr size; -} sifive_u_memmap[] =3D { +static const MemMapEntry sifive_u_memmap[] =3D { [SIFIVE_U_DEV_DEBUG] =3D { 0x0, 0x100 }, [SIFIVE_U_DEV_MROM] =3D { 0x1000, 0xf000 }, [SIFIVE_U_DEV_CLINT] =3D { 0x2000000, 0x10000 }, @@ -91,7 +88,7 @@ static const struct MemmapEntry { #define OTP_SERIAL 1 #define GEM_REVISION 0x10070109 =20 -static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, +static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, uint64_t mem_size, const char *cmdline, bool is_32_= bit) { MachineState *ms =3D MACHINE(qdev_get_machine()); @@ -484,7 +481,7 @@ static void sifive_u_machine_reset(void *opaque, int n,= int level) =20 static void sifive_u_machine_init(MachineState *machine) { - const struct MemmapEntry *memmap =3D sifive_u_memmap; + const MemMapEntry *memmap =3D sifive_u_memmap; SiFiveUState *s =3D RISCV_U_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); @@ -766,7 +763,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Erro= r **errp) { MachineState *ms =3D MACHINE(qdev_get_machine()); SiFiveUSoCState *s =3D RISCV_U_SOC(dev); - const struct MemmapEntry *memmap =3D sifive_u_memmap; + const MemMapEntry *memmap =3D sifive_u_memmap; MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); MemoryRegion *l2lim_mem =3D g_new(MemoryRegion, 1); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 56986ecfe0..ed4ca9808e 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -43,16 +43,13 @@ #include "sysemu/qtest.h" #include "sysemu/sysemu.h" =20 -static const struct MemmapEntry { - hwaddr base; - hwaddr size; -} spike_memmap[] =3D { +static const MemMapEntry spike_memmap[] =3D { [SPIKE_MROM] =3D { 0x1000, 0xf000 }, [SPIKE_CLINT] =3D { 0x2000000, 0x10000 }, [SPIKE_DRAM] =3D { 0x80000000, 0x0 }, }; =20 -static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, +static void create_fdt(SpikeState *s, const MemMapEntry *memmap, uint64_t mem_size, const char *cmdline, bool is_32_= bit) { void *fdt; @@ -179,7 +176,7 @@ static void create_fdt(SpikeState *s, const struct Memm= apEntry *memmap, =20 static void spike_board_init(MachineState *machine) { - const struct MemmapEntry *memmap =3D spike_memmap; + const MemMapEntry *memmap =3D spike_memmap; SpikeState *s =3D SPIKE_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2299b3a6be..cfd52bc59b 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -43,10 +43,7 @@ #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" =20 -static const struct MemmapEntry { - hwaddr base; - hwaddr size; -} virt_memmap[] =3D { +static const MemMapEntry virt_memmap[] =3D { [VIRT_DEBUG] =3D { 0x0, 0x100 }, [VIRT_MROM] =3D { 0x1000, 0xf000 }, [VIRT_TEST] =3D { 0x100000, 0x1000 }, @@ -170,7 +167,7 @@ static void create_pcie_irq_map(void *fdt, char *nodena= me, 0x1800, 0, 0, 0x7); } =20 -static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, +static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, uint64_t mem_size, const char *cmdline, bool is_32_= bit) { void *fdt; @@ -490,7 +487,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion = *sys_mem, =20 static void virt_machine_init(MachineState *machine) { - const struct MemmapEntry *memmap =3D virt_memmap; + const MemMapEntry *memmap =3D virt_memmap; RISCVVirtState *s =3D RISCV_VIRT_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); --=20 2.25.1 From nobody Fri May 10 12:13:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1613832614; cv=none; d=zohomail.com; s=zohoarc; b=ddrg5oGfxUinYa0m7UxNYqvz32QmUN7Pr5qcl48DEqN2k8wxF3qbI7QbiZ+N8sWuWzdSOgEK9lbWQFQsGZQ0YEN/YR49/3ELxBJCk3DtmO0GPnlZmgPwymshHaTOQI0DVOKge6x1+BGt+Ye7DqvJ+v7t702dZ7BGGl4DWu+XUYE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613832614; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id d16sm3100480pgb.12.2021.02.20.06.48.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Feb 2021 06:48:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PZi3soyJQhaWNPEZSj3fBWGFj5Xy0/vFaW0BKIB31GQ=; b=FfW/uD8O8qL+6rgWbprLiqI5t5B/qTajYxMEsV8v2Ls/+dBstGwuYt6lf7tZnNffPL kS8pjRCAT/P0kXXsLTLwq1XhG0VmkinKKOwHp5UktA1kubWrplj3iTxa7P7A6j9MUydF tqDP/R3l7etDtnowiRoyQ7lVLfmsNay0ivKhEuB7DKw/vL5ELYTclwabH2jxJINEFRxv x98+2S1kdIeENZcIuJ6Pot2KueVlGecT7iOYUdQoG6yRzTtVQuGPS95iXY+m/zxc1h0W 3g9+KKdd3MaRsYSQV2aX/FvNAh8mQrSkG2edmwOQQ4htfuVpTrvnMtp8TC4yuyCt2eRu NzUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PZi3soyJQhaWNPEZSj3fBWGFj5Xy0/vFaW0BKIB31GQ=; b=S/AqW00pB9I1jDxZyIGyBOoUOHP8VJ1NFKmGLv7aFV794qdrq5vp2bKJaS02/ef1uw NUS9lRTkoAJ0XRTFB28B6b/ajf96+OyXdWoxV8p1rpeMokURYxlfMesM3GSgyl8b4Ray 8me6MNvGaHASg9g8lTsALGg2fkiucNImpol+iqWu50yPe3mrVt5Ey/bcGpLJXuSsGtr9 9IZTrGKdX6R18w8CJ4muYiNNKI+LHWolrBv7KVqGNDKKclt8CDY/lnTj9VEYPZg8MJ4X vnWTAlFInAUjSAhFon39PQfLJrG9HmYKlDkk2RN+hklFTete4Mmq2qzfOi7hIHv9dwvq Tszw== X-Gm-Message-State: AOAM530idWLJhILNBkK/rEEOirbJsikbmpJp6iPlX4NEvwoWHboocNo0 h2uGWCNroeU9QUOxP3sJ3Q8= X-Google-Smtp-Source: ABdhPJzGZX6sh5PNZmkccLUElhk+3HQwjv8bWjE/pVCgoyQyRkTRmCJPrLMaeuLMRfGTGeVbmrXY/Q== X-Received: by 2002:a65:5643:: with SMTP id m3mr5496157pgs.91.1613832506390; Sat, 20 Feb 2021 06:48:26 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 2/4] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() Date: Sat, 20 Feb 2021 22:48:05 +0800 Message-Id: <20210220144807.819-3-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210220144807.819-1-bmeng.cn@gmail.com> References: <20210220144807.819-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" From: Bin Meng `link_up` is never used in gpex_pcie_init(). Drop it. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) hw/riscv/virt.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index cfd52bc59b..1d05bb3ef9 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -449,7 +449,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion = *sys_mem, hwaddr ecam_base, hwaddr ecam_si= ze, hwaddr mmio_base, hwaddr mmio_si= ze, hwaddr pio_base, - DeviceState *plic, bool link_up) + DeviceState *plic) { DeviceState *dev; MemoryRegion *ecam_alias, *ecam_reg; @@ -669,12 +669,12 @@ static void virt_machine_init(MachineState *machine) } =20 gpex_pcie_init(system_memory, - memmap[VIRT_PCIE_ECAM].base, - memmap[VIRT_PCIE_ECAM].size, - memmap[VIRT_PCIE_MMIO].base, - memmap[VIRT_PCIE_MMIO].size, - memmap[VIRT_PCIE_PIO].base, - DEVICE(pcie_plic), true); + memmap[VIRT_PCIE_ECAM].base, + memmap[VIRT_PCIE_ECAM].size, + memmap[VIRT_PCIE_MMIO].base, + memmap[VIRT_PCIE_MMIO].size, + memmap[VIRT_PCIE_PIO].base, + DEVICE(pcie_plic)); =20 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, --=20 2.25.1 From nobody Fri May 10 12:13:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1613832756; cv=none; d=zohomail.com; s=zohoarc; b=d+DYb59SPwr9X2V+c8azI0ndsKc1tSsud9I2Glk+Wyh6OoE5lovQ/XMVRALbwq+8XISgnKAA6RDcT/imL0ZQWVqLh/fL9CCwK/UI/owkPdqgW+UE7q+tMNDsGzPwAb//VnOe6+8QPfJhvNiHl4mdIWRaArqWT2U4btyi2vtlHsM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613832756; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yl3FmSMqUOceM2edicTwk98MpA8ZTg1Y4GvnyWg9pt8=; b=MPV6IL/eK7+AHAGYB2upp8sJiupHitWGFgYaoiAEylQxgYlenaWkQS7gvWqWzKQQkmANn+fmVop288shVyvArruvRA8lTn4yQKB0EjGq8t5PGSOHJGBQvH6tNHRcf9p5xAt21Trn37FEBSKjzd8plPFu7UPc1PemM5iySmzfxs0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613832755683504.6020809253853; Sat, 20 Feb 2021 06:52:35 -0800 (PST) Received: from localhost ([::1]:54828 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lDTcY-0002UC-KE for importer@patchew.org; Sat, 20 Feb 2021 09:52:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57462) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lDTYi-00078H-Ug; Sat, 20 Feb 2021 09:48:36 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:36446) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lDTYd-0003aP-Mw; Sat, 20 Feb 2021 09:48:36 -0500 Received: by mail-pj1-x1033.google.com with SMTP id s23so2687288pji.1; Sat, 20 Feb 2021 06:48:30 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id d16sm3100480pgb.12.2021.02.20.06.48.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Feb 2021 06:48:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yl3FmSMqUOceM2edicTwk98MpA8ZTg1Y4GvnyWg9pt8=; b=RMDAoKmo5YivtDwabZNy30r4kZBN4j/NYkwBza05RZcJ1hU/uvcaq8j6kZXEiGAoQE t3VSnmVFu+MvCUESdzJdHEUULcehIxzB8EzvOT5EZZhij1YofXKNTG9otZeh1fkZ4akX rFmwfgkq8Nn8q0gaYEGDs4TlFWUJbiNKui3xZF9fzVcMbKbdA/kJdiX5JptgzYs3SEaI UoKvq315ecpZRJAOMKbHtCVqzfhJA08S9+sHNtLkO6L3pH6pKUDVstSj9HTQ8qHFAoJd AuKj5FxLcb4zitCs2RqGjjQYdzKIuS2l1cwZMv4RI20158beTNKzeQNUbbHwj5HYwmzD v5TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yl3FmSMqUOceM2edicTwk98MpA8ZTg1Y4GvnyWg9pt8=; b=WPeCAU7fkV1CRRv4qfXFbdYnqNOz0D5+Dom8REIG54VIlMCOagn2z+rzk6fhAf28It pRnmI8vJkoUChj8p8eg8s3mqXy7fJzHTpXXRqD1SuIJAvcFC2uuo5aTCeJwOmz44eUma i1ejoQUf4UhpvyMa8WaPedrSb0CQ6ImHQ2/Y+NLGHZwMjNlq0ssGjx4+8+LkSA/+ikUb Kv1tst1Bsdgxg5zwPasZkHYKe9eh4uXcUcq/CCNKFO3AB/ONQv/2vHB2P+1b5wKB8s5X PBycMy1KSMr3SEXY5zY4kUSERTrOaWq4epJ9GwVJDAxUv7BLxWNSQnZTiCyNf9eyI4j4 9XoA== X-Gm-Message-State: AOAM531YKpb+BkqwVI8I5EVpE+xNtN3tDUdpSSM/rgic0a324YYOE0S/ JY8c1GkGI6jXMJRwp0U1IvQ= X-Google-Smtp-Source: ABdhPJwrBLDfJVS+sS4La4ay6kgcaE8RMd0J8sDv2zNhwm8DzWaowGJAw0/wmgZWm2LSDWu5NdGs6w== X-Received: by 2002:a17:902:f2d1:b029:e2:86d3:128 with SMTP id h17-20020a170902f2d1b02900e286d30128mr6727350plc.63.1613832510201; Sat, 20 Feb 2021 06:48:30 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 3/4] hw/riscv: virt: Limit RAM size in a 32-bit system Date: Sat, 20 Feb 2021 22:48:06 +0800 Message-Id: <20210220144807.819-4-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210220144807.819-1-bmeng.cn@gmail.com> References: <20210220144807.819-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" From: Bin Meng RV32 supports 34-bit physical address hence the maximum RAM size should be limited. Limit the RAM size to 10 GiB, which leaves some room for PCIe high mmio space. For 32-bit host, this is not needed as machine->ram_size cannot represent a RAM size that big. Use a #if size test to only do the size limitation for the 64-bit host. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v3: - Fix the typo (limit) in the commit message and codes Changes in v2: - Use a #if size test to only do the size limitation for the 64-bit host hw/riscv/virt.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 1d05bb3ef9..c4b8f455f8 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -590,6 +590,16 @@ static void virt_machine_init(MachineState *machine) } } =20 + if (riscv_is_32bit(&s->soc[0])) { +#if HOST_LONG_BITS =3D=3D 64 + /* limit RAM size in a 32-bit system */ + if (machine->ram_size > 10 * GiB) { + machine->ram_size =3D 10 * GiB; + error_report("Limiting RAM size to 10 GiB"); + } +#endif + } + /* register system main memory (actual RAM) */ memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram", machine->ram_size, &error_fatal); --=20 2.25.1 From nobody Fri May 10 12:13:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1613832767; cv=none; d=zohomail.com; s=zohoarc; b=c7FGlM+LXX71xifYxxIRkMb0kPQ5F4MyHE7x8gV5LYijNq2akHEa7fZsFTgBa7l1ecab853Au1++yf3CDXKO6Nk3woTx4ofBuqq6vV1JHUPKyu5eX0DMyNLxOxaIL0RkUi2kPSgqCZW1/lMzwTvf6O8ztldoBVmYqVowDyQ63Ao= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613832767; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PhZTMUwjoq80zLn5T9J9Vyn2H21mn4uZhhWc8FpCttQ=; b=iQKYcV6QITeC+oorLGq0Mq4wtLOFw61CulxYLrRFgfl0zEF0ntHGPJKDgL7ilEDQgoeMvyQoBguYPhGqaz0uXdg85wGotxcCdInl77DMrU+I7kfPecvpKZadwuwdbV9/ZhOEj9RtFbqw9X/uS6qzA16WX9A8H0BJTXguD4JhYQs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613832767149842.9178668049467; Sat, 20 Feb 2021 06:52:47 -0800 (PST) Received: from localhost ([::1]:55774 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lDTck-0002sb-5e for importer@patchew.org; Sat, 20 Feb 2021 09:52:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57484) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lDTYk-0007CO-Sc; Sat, 20 Feb 2021 09:48:38 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:33948) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lDTYj-0003cR-1m; Sat, 20 Feb 2021 09:48:38 -0500 Received: by mail-pj1-x1033.google.com with SMTP id my11so5174810pjb.1; Sat, 20 Feb 2021 06:48:34 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id d16sm3100480pgb.12.2021.02.20.06.48.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Feb 2021 06:48:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PhZTMUwjoq80zLn5T9J9Vyn2H21mn4uZhhWc8FpCttQ=; b=bXf5u/Yzo67BYVbTkuhFAzmRhCXsEN+DshFeeX0q3NEUUm1WesY1ry3ifYAO1uOWI9 CFqWbEuSbELBOUzDMOQ5HCo3Ezqg1Rx2KxTvTAt8W8Trcco6kg1QaQdq1ALkBRtlv5ug sTf01JLjdPPluNSFZOozDV8Lsgwg3jCxzWkS5tMqrWQtDblH77dApqLlj3xlIBzALltK 83qAkmZuO37MNx8pII6aUatxT2PG+KnIdHJDHz8ZESo8upHbTzSlhCEiHCjz1Q7TvjBw 6j6J86cr4ihpe+9sbfgEFp/hLyoU1scR7nb0WNq0KQZdLyu/pV4NyFbg+trkVBikTI28 mTBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PhZTMUwjoq80zLn5T9J9Vyn2H21mn4uZhhWc8FpCttQ=; b=Dd33O1+DX+9k0AZC6nVNBlvUEh8FfTkbPfWzNIe/aO9WVlZ2dZNaKh15jGghlgGhW0 ybipkz9D1PJgrrlwResedRC9PHNqEbxAVmlj/qX7MgUSmmGkUzC4W3vUlWczD+2jMxEJ cpY5XDtl4Lq7uuqLs29C7ZP1+Iwnz2SHLIG9AVJQgzR/IaVGbq/VNAQyhsuD+RxYgUKk H9qZUHx5d1xV3Zmr2kZXkkHDuLVYob3YQITWgNglN/J1WJDSIP1DuJTtz4KqHz1IYsDJ bix8GLkhiIoeR8vlFYLOlKd+lL52YVMBO7W5CXmvukPtvBpJNXcuzpGY3HubbkmkYDCL sRvw== X-Gm-Message-State: AOAM53354dznzStadLygzV1hjVXufc4rKsftZTOgUntKJJgYxdDD1AQ0 uV6JAtVuliQdUG0uNvJa0cM= X-Google-Smtp-Source: ABdhPJwQAgOMlKvOCJoQaBlaUjgxDqdnxj83a3eY2zxIdCgExCPAk8Q1toLza/BNvHhPjsgoC1tyWQ== X-Received: by 2002:a17:90a:420c:: with SMTP id o12mr14512685pjg.193.1613832513368; Sat, 20 Feb 2021 06:48:33 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 4/4] hw/riscv: virt: Map high mmio for PCIe Date: Sat, 20 Feb 2021 22:48:07 +0800 Message-Id: <20210220144807.819-5-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210220144807.819-1-bmeng.cn@gmail.com> References: <20210220144807.819-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" From: Bin Meng Some peripherals require 64-bit PCI address, so let's map the high mmio space for PCIe. For RV32, the address is hardcoded to below 4 GiB from the highest accessible physical address. For RV64, the base address depends on top of RAM and is aligned to its size which is using 16 GiB for now. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) hw/riscv/virt.c | 35 +++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c4b8f455f8..4f0c2fbca0 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -59,6 +59,15 @@ static const MemMapEntry virt_memmap[] =3D { [VIRT_DRAM] =3D { 0x80000000, 0x0 }, }; =20 +/* PCIe high mmio is fixed for RV32 */ +#define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL +#define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) + +/* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ +#define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) + +static MemMapEntry virt_high_pcie_memmap; + #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) =20 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, @@ -371,7 +380,11 @@ static void create_fdt(RISCVVirtState *s, const MemMap= Entry *memmap, 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 1, FDT_PCI_RANGE_MMIO, 2, memmap[VIRT_PCIE_MMIO].base, - 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size); + 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, + 1, FDT_PCI_RANGE_MMIO_64BIT, + 2, virt_high_pcie_memmap.base, + 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); + create_pcie_irq_map(fdt, name, plic_pcie_phandle); g_free(name); =20 @@ -448,12 +461,14 @@ update_bootargs: static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, hwaddr ecam_base, hwaddr ecam_si= ze, hwaddr mmio_base, hwaddr mmio_si= ze, + hwaddr high_mmio_base, + hwaddr high_mmio_size, hwaddr pio_base, DeviceState *plic) { DeviceState *dev; MemoryRegion *ecam_alias, *ecam_reg; - MemoryRegion *mmio_alias, *mmio_reg; + MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; qemu_irq irq; int i; =20 @@ -473,6 +488,13 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion= *sys_mem, mmio_reg, mmio_base, mmio_size); memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias= ); =20 + /* Map high MMIO space */ + high_mmio_alias =3D g_new0(MemoryRegion, 1); + memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high= ", + mmio_reg, high_mmio_base, high_mmio_size); + memory_region_add_subregion(get_system_memory(), high_mmio_base, + high_mmio_alias); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); =20 for (i =3D 0; i < GPEX_NUM_IRQS; i++) { @@ -598,6 +620,13 @@ static void virt_machine_init(MachineState *machine) error_report("Limiting RAM size to 10 GiB"); } #endif + virt_high_pcie_memmap.base =3D VIRT32_HIGH_PCIE_MMIO_BASE; + virt_high_pcie_memmap.size =3D VIRT32_HIGH_PCIE_MMIO_SIZE; + } else { + virt_high_pcie_memmap.size =3D VIRT64_HIGH_PCIE_MMIO_SIZE; + virt_high_pcie_memmap.base =3D memmap[VIRT_DRAM].base + machine->r= am_size; + virt_high_pcie_memmap.base =3D + ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.siz= e); } =20 /* register system main memory (actual RAM) */ @@ -683,6 +712,8 @@ static void virt_machine_init(MachineState *machine) memmap[VIRT_PCIE_ECAM].size, memmap[VIRT_PCIE_MMIO].base, memmap[VIRT_PCIE_MMIO].size, + virt_high_pcie_memmap.base, + virt_high_pcie_memmap.size, memmap[VIRT_PCIE_PIO].base, DEVICE(pcie_plic)); =20 --=20 2.25.1