From nobody Mon Feb 9 20:13:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613747977; cv=none; d=zohomail.com; s=zohoarc; b=iwnpawFwj0uuKvvzazXUHfXE3TezDQy0KI8Ltkvk9SfqWvYLQvzPtWZWk2g5Q8qftzAKUrmFKm5YRX36tTycFdM6FcrkHShM5P50kDevvoL4lvga1tKH0AJ5iWA99VOEaeWmxjQouQjI+ei5UQbicL4aJ24DTQTDfdgUgNtuaKo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613747977; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=y0IkltMwkMmsntCXmla7YgVCExbHqoOzjdETdOI28dg=; b=V/QEpceAZ6ery0kVWTnHQAlb3stqoHUuY1A4nXm0yh0rhITdqx1Pj5oBwkQ2A06+ybDxrbi+DABrmu9cxXqHntyVbIMdRxxwVqf/TI5lck+pPxm/BO9/9re+1GDJETYRxMJBO8lonTiVALKmt416nwLycdxa6WVfvrb5zjwb5zI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613747977140689.6416158898134; Fri, 19 Feb 2021 07:19:37 -0800 (PST) Received: from localhost ([::1]:43446 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7ZA-0003g0-1J for importer@patchew.org; Fri, 19 Feb 2021 10:19:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34306) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73s-0002lk-LI for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:16 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:34487) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73P-0003db-Il for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:16 -0500 Received: by mail-wr1-x42d.google.com with SMTP id n4so8912910wrx.1 for ; Fri, 19 Feb 2021 06:46:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=y0IkltMwkMmsntCXmla7YgVCExbHqoOzjdETdOI28dg=; b=wseSwm5R1EC+ycCHupY24rZDlUnOWnFgK8okczW+Z6g+zgVYmKYu1l2KWd+MK1Lh90 R9QZTwMAe7pRkQCqCfSPW5TPQV6Q4WqH0oVz3m6z1LaNWvJHqOYENoxCjBP6ZoKpbg5C LvCk3ygzlyUDG7ZwnIQcaLbwo3uYkAH6B/pcL4RGlgePf+RLU5few3NPaNLf9Ai3g6Cg q8QSCG9+Jzaxv3zbXFFvMASuh0iOjodPFiZbp9qiyF3ZKwXqS/nryvwDmkrIhPCHCfG1 9jv7K8z55xgOrmrPmldERFhkAXsu2Sc5suiRaAiN8o8W7L+46zSoQ7kkarMVRvSX2zSL uImg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y0IkltMwkMmsntCXmla7YgVCExbHqoOzjdETdOI28dg=; b=HlWNWztOVpCNpWWvLoGotiOMYEsHUTFMHIyH40OhmtYIgwzLFy12tEjlymvDA8lnNT XuLiF92MohJU/HesKUt70c2DjFYKw76u7cKegpbr10Uj6KVT9p4JefrFkfDSgseIz+R/ Ho3eLyBOkMIyckVDXP2Rv29bw3I3xhBpiSMQfHVDbjSOM1y8yFb/x0Ec/XZPO8ZKgotV crhzauHLRW8JEqTe/quamzapCmoQq+2CHD5Upwkf8YsdjJ7l5Y7dkJtV/aO/XwW7sqC2 4m4Oe9DmkLqhgtWOfZR2jDyAOboDRK28KyEsnq0egHkrV/w7cDnPFoWEhudKw+EC+lfA i1yg== X-Gm-Message-State: AOAM532aEaBpJwO/q9zqBYujhkUf3FFfcW7J2XOvGAYKcis2lh7UGigg jvF3pYfzvof9Pn4IET64df5wKg== X-Google-Smtp-Source: ABdhPJxk562T7pjJ74OIbrgk9pUWBpaRW9mqfoU5pbFGB4fPZw3pTvkzc98R9KNO2qwv1K1NpWTNyg== X-Received: by 2002:a05:6000:1546:: with SMTP id 6mr9486027wry.398.1613746006201; Fri, 19 Feb 2021 06:46:46 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 35/44] hw/arm/armsse: Add SSE-300 support Date: Fri, 19 Feb 2021 14:46:08 +0000 Message-Id: <20210219144617.4782-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Now we have sufficiently parameterised the code, we can add SSE-300 support by adding a new entry to the armsse_variants[] array. Note that the main watchdog (unlike the s32k watchdog) in the SSE-300 is a different device from the CMSDK watchdog; we don't have a model of it so we leave it as a TYPE_UNIMPLEMENTED_DEVICE stub. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 1 + hw/arm/armsse.c | 152 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 153 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 21d239c381c..36592be62c5 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -123,6 +123,7 @@ OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass, */ #define TYPE_IOTKIT "iotkit" #define TYPE_SSE200 "sse-200" +#define TYPE_SSE300 "sse-300" =20 /* We have an IRQ splitter and an OR gate input for each external PPC * and the 2 internal PPCs diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 2366c49376d..e5aeb9e485f 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -337,6 +337,128 @@ static const ARMSSEDeviceInfo sse200_devices[] =3D { } }; =20 +static const ARMSSEDeviceInfo sse300_devices[] =3D { + { + .name =3D "timer0", + .type =3D TYPE_SSE_TIMER, + .index =3D 0, + .addr =3D 0x48000000, + .ppc =3D 0, + .ppc_port =3D 0, + .irq =3D 3, + }, + { + .name =3D "timer1", + .type =3D TYPE_SSE_TIMER, + .index =3D 1, + .addr =3D 0x48001000, + .ppc =3D 0, + .ppc_port =3D 1, + .irq =3D 4, + }, + { + .name =3D "timer2", + .type =3D TYPE_SSE_TIMER, + .index =3D 2, + .addr =3D 0x48002000, + .ppc =3D 0, + .ppc_port =3D 2, + .irq =3D 5, + }, + { + .name =3D "timer3", + .type =3D TYPE_SSE_TIMER, + .index =3D 3, + .addr =3D 0x48003000, + .ppc =3D 0, + .ppc_port =3D 5, + .irq =3D 27, + }, + { + .name =3D "s32ktimer", + .type =3D TYPE_CMSDK_APB_TIMER, + .index =3D 0, + .addr =3D 0x4802f000, + .ppc =3D 1, + .ppc_port =3D 0, + .irq =3D 2, + .slowclk =3D true, + }, + { + .name =3D "s32kwatchdog", + .type =3D TYPE_CMSDK_APB_WATCHDOG, + .index =3D 0, + .addr =3D 0x4802e000, + .ppc =3D NO_PPC, + .irq =3D NMI_0, + .slowclk =3D true, + }, + { + .name =3D "watchdog", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 0, + .addr =3D 0x48040000, + .size =3D 0x2000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "armsse-sysinfo", + .type =3D TYPE_IOTKIT_SYSINFO, + .index =3D 0, + .addr =3D 0x48020000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "armsse-sysctl", + .type =3D TYPE_IOTKIT_SYSCTL, + .index =3D 0, + .addr =3D 0x58021000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "SYS_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 1, + .addr =3D 0x58022000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "CPU0CORE_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 2, + .addr =3D 0x50023000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "MGMT_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 3, + .addr =3D 0x50028000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "DEBUG_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 4, + .addr =3D 0x50029000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D NULL, + } +}; + /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ static const bool sse200_irq_is_common[32] =3D { [0 ... 5] =3D true, @@ -352,6 +474,18 @@ static const bool sse200_irq_is_common[32] =3D { /* 30, 31: reserved */ }; =20 +static const bool sse300_irq_is_common[32] =3D { + [0 ... 5] =3D true, + /* 6, 7: per-CPU MHU interrupts */ + [8 ... 12] =3D true, + /* 13: reserved */ + [14 ... 16] =3D true, + /* 17-25: reserved */ + [26 ... 27] =3D true, + /* 28, 29: per-CPU CTI interrupts */ + /* 30, 31: reserved */ +}; + static const ARMSSEInfo armsse_variants[] =3D { { .name =3D TYPE_IOTKIT, @@ -389,6 +523,24 @@ static const ARMSSEInfo armsse_variants[] =3D { .devinfo =3D sse200_devices, .irq_is_common =3D sse200_irq_is_common, }, + { + .name =3D TYPE_SSE300, + .sse_version =3D ARMSSE_SSE300, + .sram_banks =3D 2, + .num_cpus =3D 1, + .sys_version =3D 0x7e00043b, + .iidr =3D 0x74a0043b, + .cpuwait_rst =3D 0, + .has_mhus =3D false, + .has_cachectrl =3D false, + .has_cpusecctrl =3D true, + .has_cpuid =3D true, + .has_cpu_pwrctrl =3D true, + .has_sse_counter =3D true, + .props =3D armsse_properties, + .devinfo =3D sse300_devices, + .irq_is_common =3D sse300_irq_is_common, + }, }; =20 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) --=20 2.20.1