From nobody Mon Feb 9 19:54:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613747709; cv=none; d=zohomail.com; s=zohoarc; b=J/e1+/jMfxFG9+OSDfIkIKR8RuYPEH1mAYHHjwxt1b6mx6X1/olnienoXQ0TTdo0fJZNYqPfm4ew/QgtIAtdDFtOjLXy1wWfzs0t0Par0+EYLrvujLG8amkXADXbDRF5ysIPO2CYSn+vz2XxIUIe0Ne6pdrwfUjAkDHJmEL71EE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613747709; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AbLWZDU49J088c2eS3fP9W433ZG0VZOrayl8b6TQOBc=; b=LUAuYYn4Bt7f+jpgFwiXNTK6zIxOqY73vIf+LwXBGaiGrT9ZyPxhSA/ODEtCXyk2AdDUWKWRecU4SwmmMdBRuzUA5HXzzo+YJGvAv8R0CxnRWA5U9iEiY03i3e8pQ1z1HQkIM3PI52btS118dFlNOw1u3EcEQcEE3/qrpi7qJJQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613747708638606.6888133104491; Fri, 19 Feb 2021 07:15:08 -0800 (PST) Received: from localhost ([::1]:58090 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7Up-0006Ac-8F for importer@patchew.org; Fri, 19 Feb 2021 10:15:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34262) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73q-0002iU-V1 for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:14 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:34484) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73O-0003cs-QZ for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:14 -0500 Received: by mail-wr1-x42a.google.com with SMTP id n4so8912846wrx.1 for ; Fri, 19 Feb 2021 06:46:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=AbLWZDU49J088c2eS3fP9W433ZG0VZOrayl8b6TQOBc=; b=eCQtSIqUDnby2MRJA5kkN6VuIZciSAnwASc/yII6cvWkrMLqaF7q3n/4ScF8JweKej i6iItJ84KqMxa0tTzJnzxTEQ3oj9rhH0Tm/GSsEk+wc0Y9vsTBx46ZJxWzaoLXDeHTSS EG5wqKEOwG2q/6Z4gONbquLfaDQYDkDBK8tLEwJXX89iI2hIMbwTaYV2O9aY7X+AcEKp VbC7zeUZQq+sX4uz9NGzPwLemgL46kuyd09hM7tifBQCq05UdSuDwkGqAKKBhW32hmrL A3NVUqWQgjqJf+/3htDxYt2NA5wEIeoPvYs0hxQTtHAcATmr7h72ZzDmb4KIE0M5HZFC jqEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AbLWZDU49J088c2eS3fP9W433ZG0VZOrayl8b6TQOBc=; b=VBrbMUQrEQ3HJxEpbhVgwvYxCOTl2OkILxds3mniUlSHSKFKRvHK/5uhyfd4Aq3lDo 9lGi+/mYx4FQ8pDDhfMgQTgJP//8GqD0inuzBdGydifRO2Mk5V4zabZsbJK6GvsZoGKH vZDZjweWHJaa+vTtzI1U+XMZOXnjCG6lSG9qtytFiTf6n8eXrNeBs7y13oln588TNMBz fczwJhCrA4HNE62aSIYytd+rzHXadO3FQGiYYgBk6VsLn35+Z++kVnrrd6I7FIMUxBeq XLqKTf0R5YqLgqqOGfCn0FE429FJdDlqKT6eJFwnyCvNLCPfbqanYHoDmpdeU47U0Wrp 1ETA== X-Gm-Message-State: AOAM531ok+2aLZN1kQbE5qycbyVWtA7xNqYicsRzI0QF0mXtgn8hf/xj VB34zbriLn0gysdUz7Th6dj0REmV8MigWg== X-Google-Smtp-Source: ABdhPJxFJRWlrAv73i+PduWiS3Dw0T49dVn2OHTGWwESeO6enljVH2VzRp+VEkaGNUDEgcr18Ilt/g== X-Received: by 2002:a5d:698d:: with SMTP id g13mr9674942wru.30.1613746005401; Fri, 19 Feb 2021 06:46:45 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 34/44] hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL block Date: Fri, 19 Feb 2021 14:46:07 +0000 Message-Id: <20210219144617.4782-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Support SSE variants like the SSE-300 with an ARMSSE_CPU_PWRCTRL register block. Because this block is per-CPU and does not clash with any of the SSE-200 devices, we handle it with a has_cpu_pwrctrl flag like the existing has_cachectrl, has_cpusectrl and has_cpuid, rather than trying to add per-CPU-device support to the devinfo array handling code. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 3 +++ hw/arm/armsse.c | 26 ++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index f4e2b680479..21d239c381c 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -104,6 +104,7 @@ #include "hw/misc/iotkit-sysinfo.h" #include "hw/misc/armsse-cpuid.h" #include "hw/misc/armsse-mhu.h" +#include "hw/misc/armsse-cpu-pwrctrl.h" #include "hw/misc/unimp.h" #include "hw/or-irq.h" #include "hw/clock.h" @@ -179,6 +180,8 @@ struct ARMSSE { =20 ARMSSECPUID cpuid[SSE_MAX_CPUS]; =20 + ARMSSECPUPwrCtrl cpu_pwrctrl[SSE_MAX_CPUS]; + /* * 'container' holds all devices seen by all CPUs. * 'cpu_container[i]' is the view that CPU i has: this has the diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index ec9c30e0996..2366c49376d 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -66,6 +66,7 @@ struct ARMSSEInfo { bool has_cachectrl; bool has_cpusecctrl; bool has_cpuid; + bool has_cpu_pwrctrl; bool has_sse_counter; Property *props; const ARMSSEDeviceInfo *devinfo; @@ -364,6 +365,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cachectrl =3D false, .has_cpusecctrl =3D false, .has_cpuid =3D false, + .has_cpu_pwrctrl =3D false, .has_sse_counter =3D false, .props =3D iotkit_properties, .devinfo =3D iotkit_devices, @@ -381,6 +383,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cachectrl =3D true, .has_cpusecctrl =3D true, .has_cpuid =3D true, + .has_cpu_pwrctrl =3D false, .has_sse_counter =3D false, .props =3D armsse_properties, .devinfo =3D sse200_devices, @@ -660,6 +663,15 @@ static void armsse_init(Object *obj) g_free(name); } } + if (info->has_cpu_pwrctrl) { + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("cpu_pwrctrl%d", i); + + object_initialize_child(obj, name, &s->cpu_pwrctrl[i], + TYPE_ARMSSE_CPU_PWRCTRL); + g_free(name); + } + } if (info->has_sse_counter) { object_initialize_child(obj, "sse-counter", &s->sse_counter, TYPE_SSE_COUNTER); @@ -1255,6 +1267,8 @@ static void armsse_realize(DeviceState *dev, Error **= errp) * 0x50010000: L1 icache control registers * 0x50011000: CPUSECCTRL (CPU local security control registers) * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block + * The SSE-300 has an extra: + * 0x40012000 and 0x50012000: CPU_PWRCTRL register block */ if (info->has_cachectrl) { for (i =3D 0; i < info->num_cpus; i++) { @@ -1301,6 +1315,18 @@ static void armsse_realize(DeviceState *dev, Error *= *errp) memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, = mr); } } + if (info->has_cpu_pwrctrl) { + for (i =3D 0; i < info->num_cpus; i++) { + MemoryRegion *mr; + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu_pwrctrl[i]), errp))= { + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpu_pwrctrl[i= ]), 0); + memory_region_add_subregion(&s->cpu_container[i], 0x40012000, = mr); + } + } =20 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[1]), errp)) { return; --=20 2.20.1