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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=R7MC92E/b1Y+h5JuyGdL6d25h9VANDzCuQIoG8m1Og4=; b=HE9sAzFvoJG21FJ932QOuOYcTNLgG8criSE582bP5EbZwwRJG8DSqrShguHfngS8Vx lC1MleeyKhBmfqzZ6HkU4p0C/qoq0/tu1p4TqXDPOb2NAlxtNkwDQ2UIg4epCG4cpJEb C7Zctcq+MxFnKQnyHdI1is23krrhYGiby3mKbhslw+PhBs5azlATMCQ0K0n0eU5NCP51 kIQ3DsgIO1jcUH9d/tar5QJy3pj8Fzh8AtaL0FhoZ7Ehh/3WuwkSIaWCrvSY1wg+yumC p65sPC8uZ8RNimJ8sY40QsXdj3LxNNCgE72503mO8e2IQ8Dxy8iLgLRDUG9NrA6enEAr sOqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R7MC92E/b1Y+h5JuyGdL6d25h9VANDzCuQIoG8m1Og4=; b=Fv+UXE1nLL0GODAeEBpFQO4uwKidFP6Ftb5zLCP1GNvn9h2R9kbAzq3VxxGLBm/C0h YdX/jTYX68xMazJp2hrjk0b8UiuOaPNDrMkWhN14DpJEqgCbUkMQ7IpTzc06L1nyoEeV izcecy5AdvmoNPD+vnWIYBxoeFEecZHl6qP9Z9MevESzbTY4u6zmAv8JaosE4AS14W4J raPdvovBDI8eIARRV/IV3UAcTLZopSVUHVUIq/ErormCU5rcU8qbt6qlaTQMA4iBRwE9 nHcjvHVgJ5Lg0Y70pHVfthmIo+b5OHRLv5RqNniU+S0gZigVyKgE3kdzhIBn5AhQ0jcG L+UQ== X-Gm-Message-State: AOAM532BIbhZiBDsfCQR51rkWiKPl9crqA0k80RQISsFjUC8jond75dS oP+EXmxcPZ5UfNv7HNOkv8si3Q== X-Google-Smtp-Source: ABdhPJzjLpJaAa5ozEQ0FTKTG4z/Wk147zLBuDWMTh8IZmyH3OjccE0P1XQe89BFq9wHgUsExDGFbg== X-Received: by 2002:a5d:44d2:: with SMTP id z18mr9553101wrr.26.1613745981411; Fri, 19 Feb 2021 06:46:21 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 01/44] clock: Add ClockEvent parameter to callbacks Date: Fri, 19 Feb 2021 14:45:34 +0000 Message-Id: <20210219144617.4782-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The Clock framework allows users to specify a callback which is called after the clock's period has been updated. Some users need to also have a callback which is called before the clock period is updated. As the first step in adding support for notifying Clock users on pre-update events, add an argument to the ClockCallback to specify what event is being notified, and add an argument to the various functions for registering a callback to specify which events are of interest to that callback. Note that the documentation update renders correct the previously incorrect claim in 'Adding a new clock' that callbacks "will be explained in a following section". Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Luc Michel Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- v2->v3: used 'unsigned int' instead of 'int' for parameters and struct fields containing an event mask, as suggested by Philippe; fixed events argument to qdev_init_clock_in() with NULL callback pointer in npcm7xx_adc.c (spotted by Hao) --- docs/devel/clocks.rst | 52 +++++++++++++++++++++++++++----- include/hw/clock.h | 21 +++++++++++-- include/hw/qdev-clock.h | 17 ++++++++--- hw/adc/npcm7xx_adc.c | 2 +- hw/arm/armsse.c | 9 +++--- hw/char/cadence_uart.c | 4 +-- hw/char/ibex_uart.c | 4 +-- hw/char/pl011.c | 5 +-- hw/core/clock.c | 21 ++++++++++--- hw/core/qdev-clock.c | 8 +++-- hw/mips/cps.c | 2 +- hw/misc/bcm2835_cprman.c | 23 ++++++++------ hw/misc/npcm7xx_clk.c | 26 +++++++++++++--- hw/misc/npcm7xx_pwm.c | 2 +- hw/misc/zynq_slcr.c | 5 +-- hw/timer/cmsdk-apb-dualtimer.c | 5 +-- hw/timer/cmsdk-apb-timer.c | 4 +-- hw/timer/npcm7xx_timer.c | 2 +- hw/watchdog/cmsdk-apb-watchdog.c | 5 +-- target/mips/cpu.c | 2 +- 20 files changed, 161 insertions(+), 58 deletions(-) diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst index c54bbb82409..cd344e3fe5d 100644 --- a/docs/devel/clocks.rst +++ b/docs/devel/clocks.rst @@ -80,11 +80,12 @@ Adding clocks to a device must be done during the init = method of the Device instance. =20 To add an input clock to a device, the function ``qdev_init_clock_in()`` -must be used. It takes the name, a callback and an opaque parameter -for the callback (this will be explained in a following section). +must be used. It takes the name, a callback, an opaque parameter +for the callback and a mask of events when the callback should be +called (this will be explained in a following section). Output is simpler; only the name is required. Typically:: =20 - qdev_init_clock_in(DEVICE(dev), "clk_in", clk_in_callback, dev); + qdev_init_clock_in(DEVICE(dev), "clk_in", clk_in_callback, dev, ClockU= pdate); qdev_init_clock_out(DEVICE(dev), "clk_out"); =20 Both functions return the created Clock pointer, which should be saved in = the @@ -113,7 +114,7 @@ output. * callback for the input clock (see "Callback on input clock * change" section below for more information). */ - static void clk_in_callback(void *opaque); + static void clk_in_callback(void *opaque, ClockEvent event); =20 /* * static array describing clocks: @@ -124,7 +125,7 @@ output. * the clk_out field of a MyDeviceState structure. */ static const ClockPortInitArray mydev_clocks =3D { - QDEV_CLOCK_IN(MyDeviceState, clk_in, clk_in_callback), + QDEV_CLOCK_IN(MyDeviceState, clk_in, clk_in_callback, ClockUpdate), QDEV_CLOCK_OUT(MyDeviceState, clk_out), QDEV_CLOCK_END }; @@ -153,6 +154,40 @@ nothing else to do. This value will be propagated to o= ther clocks when connecting the clocks together and devices will fetch the right value duri= ng the first reset. =20 +Clock callbacks +--------------- + +You can give a clock a callback function in several ways: + + * by passing it as an argument to ``qdev_init_clock_in()`` + * as an argument to the ``QDEV_CLOCK_IN()`` macro initializing an + array to be passed to ``qdev_init_clocks()`` + * by directly calling the ``clock_set_callback()`` function + +The callback function must be of this type: + +.. code-block:: c + + typedef void ClockCallback(void *opaque, ClockEvent event); + +The ``opaque`` argument is the pointer passed to ``qdev_init_clock_in()`` +or ``clock_set_callback()``; for ``qdev_init_clocks()`` it is the +``dev`` device pointer. + +The ``event`` argument specifies why the callback has been called. +When you register the callback you specify a mask of ClockEvent values +that you are interested in. The callback will only be called for those +events. + +The events currently supported are: + + * ``ClockUpdate`` : called after the input clock's period has changed + +Note that a clock only has one callback: it is not possible to register +different functions for different events. You must register a single +callback which listens for all of the events you are interested in, +and use the ``event`` argument to identify which event has happened. + Retrieving clocks from a device ------------------------------- =20 @@ -231,7 +266,7 @@ object during device instance init. For example: .. code-block:: c =20 clk =3D qdev_init_clock_in(DEVICE(dev), "clk-in", clk_in_callback, - dev); + dev, ClockUpdate); /* set initial value to 10ns / 100MHz */ clock_set_ns(clk, 10); =20 @@ -267,11 +302,12 @@ next lowest integer. This implies some inaccuracy due= to the rounding, so be cautious about using it in calculations. =20 It is also possible to register a callback on clock frequency changes. -Here is an example: +Here is an example, which assumes that ``clock_callback`` has been +specified as the callback for the ``ClockUpdate`` event: =20 .. code-block:: c =20 - void clock_callback(void *opaque) { + void clock_callback(void *opaque, ClockEvent event) { MyDeviceState *s =3D (MyDeviceState *) opaque; /* * 'opaque' is the argument passed to qdev_init_clock_in(); diff --git a/include/hw/clock.h b/include/hw/clock.h index e5f45e2626d..282a37f7c5a 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -22,7 +22,17 @@ #define TYPE_CLOCK "clock" OBJECT_DECLARE_SIMPLE_TYPE(Clock, CLOCK) =20 -typedef void ClockCallback(void *opaque); +/* + * Argument to ClockCallback functions indicating why the callback + * has been called. A mask of these values logically ORed together + * is used to specify which events are interesting when the callback + * is registered, so these values must all be different bit values. + */ +typedef enum ClockEvent { + ClockUpdate =3D 1, /* Clock period has just updated */ +} ClockEvent; + +typedef void ClockCallback(void *opaque, ClockEvent event); =20 /* * clock store a value representing the clock's period in 2^-32ns unit. @@ -50,6 +60,7 @@ typedef void ClockCallback(void *opaque); * @canonical_path: clock path string cache (used for trace purpose) * @callback: called when clock changes * @callback_opaque: argument for @callback + * @callback_events: mask of events when callback should be called * @source: source (or parent in clock tree) of the clock * @children: list of clocks connected to this one (it is their source) * @sibling: structure used to form a clock list @@ -67,6 +78,7 @@ struct Clock { char *canonical_path; ClockCallback *callback; void *callback_opaque; + unsigned int callback_events; =20 /* Clocks are organized in a clock tree */ Clock *source; @@ -114,10 +126,15 @@ Clock *clock_new(Object *parent, const char *name); * @clk: the clock to register the callback into * @cb: the callback function * @opaque: the argument to the callback + * @events: the events the callback should be called for + * (logical OR of ClockEvent enum values) * * Register a callback called on every clock update. + * Note that a clock has only one callback: you cannot register + * different callback functions for different events. */ -void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque); +void clock_set_callback(Clock *clk, ClockCallback *cb, + void *opaque, unsigned int events); =20 /** * clock_clear_callback: diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h index 64ca4d266f2..ffa0f7ba09e 100644 --- a/include/hw/qdev-clock.h +++ b/include/hw/qdev-clock.h @@ -22,6 +22,8 @@ * @name: the name of the clock (can't be NULL). * @callback: optional callback to be called on update or NULL. * @opaque: argument for the callback + * @events: the events the callback should be called for + * (logical OR of ClockEvent enum values) * @returns: a pointer to the newly added clock * * Add an input clock to device @dev as a clock named @name. @@ -29,7 +31,8 @@ * The callback will be called with @opaque as opaque parameter. */ Clock *qdev_init_clock_in(DeviceState *dev, const char *name, - ClockCallback *callback, void *opaque); + ClockCallback *callback, void *opaque, + unsigned int events); =20 /** * qdev_init_clock_out: @@ -105,6 +108,7 @@ void qdev_finalize_clocklist(DeviceState *dev); * @output: indicates whether the clock is input or output * @callback: for inputs, optional callback to be called on clock's update * with device as opaque + * @callback_events: mask of ClockEvent values for when callback is called * @offset: optional offset to store the ClockIn or ClockOut pointer in de= vice * state structure (0 means unused) */ @@ -112,6 +116,7 @@ struct ClockPortInitElem { const char *name; bool is_output; ClockCallback *callback; + unsigned int callback_events; size_t offset; }; =20 @@ -119,10 +124,11 @@ struct ClockPortInitElem { (offsetof(devstate, field) + \ type_check(Clock *, typeof_field(devstate, field))) =20 -#define QDEV_CLOCK(out_not_in, devstate, field, cb) { \ +#define QDEV_CLOCK(out_not_in, devstate, field, cb, cbevents) { \ .name =3D (stringify(field)), \ .is_output =3D out_not_in, \ .callback =3D cb, \ + .callback_events =3D cbevents, \ .offset =3D clock_offset_value(devstate, field), \ } =20 @@ -133,14 +139,15 @@ struct ClockPortInitElem { * @field: a field in @_devstate (must be Clock*) * @callback: (for input only) callback (or NULL) to be called with the de= vice * state as argument + * @cbevents: (for input only) ClockEvent mask for when callback is called * * The name of the clock will be derived from @field */ -#define QDEV_CLOCK_IN(devstate, field, callback) \ - QDEV_CLOCK(false, devstate, field, callback) +#define QDEV_CLOCK_IN(devstate, field, callback, cbevents) \ + QDEV_CLOCK(false, devstate, field, callback, cbevents) =20 #define QDEV_CLOCK_OUT(devstate, field) \ - QDEV_CLOCK(true, devstate, field, NULL) + QDEV_CLOCK(true, devstate, field, NULL, 0) =20 #define QDEV_CLOCK_END { .name =3D NULL } =20 diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c index 870a6d50c27..0f0a9f63e20 100644 --- a/hw/adc/npcm7xx_adc.c +++ b/hw/adc/npcm7xx_adc.c @@ -238,7 +238,7 @@ static void npcm7xx_adc_init(Object *obj) memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s, TYPE_NPCM7XX_ADC, 4 * KiB); sysbus_init_mmio(sbd, &s->iomem); - s->clock =3D qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL); + s->clock =3D qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL, 0); =20 for (i =3D 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) { object_property_add_uint32_ptr(obj, "adci[*]", diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 26e1a8c95b6..fa155b72022 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -230,9 +230,10 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s) qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); } =20 -static void armsse_mainclk_update(void *opaque) +static void armsse_mainclk_update(void *opaque, ClockEvent event) { ARMSSE *s =3D ARM_SSE(opaque); + /* * Set system_clock_scale from our Clock input; this is what * controls the tick rate of the CPU SysTick timer. @@ -251,8 +252,8 @@ static void armsse_init(Object *obj) assert(info->num_cpus <=3D SSE_MAX_CPUS); =20 s->mainclk =3D qdev_init_clock_in(DEVICE(s), "MAINCLK", - armsse_mainclk_update, s); - s->s32kclk =3D qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL); + armsse_mainclk_update, s, ClockUpdate); + s->s32kclk =3D qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL, 0); =20 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); =20 @@ -1120,7 +1121,7 @@ static void armsse_realize(DeviceState *dev, Error **= errp) sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); =20 /* Set initial system_clock_scale from MAINCLK */ - armsse_mainclk_update(s); + armsse_mainclk_update(s, ClockUpdate); } =20 static void armsse_idau_check(IDAUInterface *ii, uint32_t address, diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index c603e14012a..ceb677bc5a8 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -519,7 +519,7 @@ static void cadence_uart_realize(DeviceState *dev, Erro= r **errp) uart_event, NULL, s, NULL, true); } =20 -static void cadence_uart_refclk_update(void *opaque) +static void cadence_uart_refclk_update(void *opaque, ClockEvent event) { CadenceUARTState *s =3D opaque; =20 @@ -537,7 +537,7 @@ static void cadence_uart_init(Object *obj) sysbus_init_irq(sbd, &s->irq); =20 s->refclk =3D qdev_init_clock_in(DEVICE(obj), "refclk", - cadence_uart_refclk_update, s); + cadence_uart_refclk_update, s, ClockUpd= ate); /* initialize the frequency in case the clock remains unconnected */ clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK); =20 diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c index 89f1182c9bf..edcaa30aded 100644 --- a/hw/char/ibex_uart.c +++ b/hw/char/ibex_uart.c @@ -396,7 +396,7 @@ static void ibex_uart_write(void *opaque, hwaddr addr, } } =20 -static void ibex_uart_clk_update(void *opaque) +static void ibex_uart_clk_update(void *opaque, ClockEvent event) { IbexUartState *s =3D opaque; =20 @@ -466,7 +466,7 @@ static void ibex_uart_init(Object *obj) IbexUartState *s =3D IBEX_UART(obj); =20 s->f_clk =3D qdev_init_clock_in(DEVICE(obj), "f_clock", - ibex_uart_clk_update, s); + ibex_uart_clk_update, s, ClockUpdate); clock_set_hz(s->f_clk, IBEX_UART_CLOCK); =20 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_watermark); diff --git a/hw/char/pl011.c b/hw/char/pl011.c index ea4a4e52356..c5621a195ff 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -309,7 +309,7 @@ static void pl011_event(void *opaque, QEMUChrEvent even= t) pl011_put_fifo(opaque, 0x400); } =20 -static void pl011_clock_update(void *opaque) +static void pl011_clock_update(void *opaque, ClockEvent event) { PL011State *s =3D PL011(opaque); =20 @@ -378,7 +378,8 @@ static void pl011_init(Object *obj) sysbus_init_irq(sbd, &s->irq[i]); } =20 - s->clk =3D qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, = s); + s->clk =3D qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, = s, + ClockUpdate); =20 s->read_trigger =3D 1; s->ifl =3D 0x12; diff --git a/hw/core/clock.c b/hw/core/clock.c index 76b5f468b6e..4479eff145b 100644 --- a/hw/core/clock.c +++ b/hw/core/clock.c @@ -39,15 +39,17 @@ Clock *clock_new(Object *parent, const char *name) return clk; } =20 -void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque) +void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque, + unsigned int events) { clk->callback =3D cb; clk->callback_opaque =3D opaque; + clk->callback_events =3D events; } =20 void clock_clear_callback(Clock *clk) { - clock_set_callback(clk, NULL, NULL); + clock_set_callback(clk, NULL, NULL, 0); } =20 bool clock_set(Clock *clk, uint64_t period) @@ -62,6 +64,17 @@ bool clock_set(Clock *clk, uint64_t period) return true; } =20 +static void clock_call_callback(Clock *clk, ClockEvent event) +{ + /* + * Call the Clock's callback for this event, if it has one and + * is interested in this event. + */ + if (clk->callback && (clk->callback_events & event)) { + clk->callback(clk->callback_opaque, event); + } +} + static void clock_propagate_period(Clock *clk, bool call_callbacks) { Clock *child; @@ -72,8 +85,8 @@ static void clock_propagate_period(Clock *clk, bool call_= callbacks) trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk), CLOCK_PERIOD_TO_HZ(clk->period), call_callbacks); - if (call_callbacks && child->callback) { - child->callback(child->callback_opaque); + if (call_callbacks) { + clock_call_callback(child, ClockUpdate); } clock_propagate_period(child, call_callbacks); } diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c index eb05f2a13ca..117f4c6ea4a 100644 --- a/hw/core/qdev-clock.c +++ b/hw/core/qdev-clock.c @@ -111,7 +111,8 @@ Clock *qdev_init_clock_out(DeviceState *dev, const char= *name) } =20 Clock *qdev_init_clock_in(DeviceState *dev, const char *name, - ClockCallback *callback, void *opaque) + ClockCallback *callback, void *opaque, + unsigned int events) { NamedClockList *ncl; =20 @@ -120,7 +121,7 @@ Clock *qdev_init_clock_in(DeviceState *dev, const char = *name, ncl =3D qdev_init_clocklist(dev, name, false, NULL); =20 if (callback) { - clock_set_callback(ncl->clock, callback, opaque); + clock_set_callback(ncl->clock, callback, opaque, events); } return ncl->clock; } @@ -137,7 +138,8 @@ void qdev_init_clocks(DeviceState *dev, const ClockPort= InitArray clocks) if (elem->is_output) { *clkp =3D qdev_init_clock_out(dev, elem->name); } else { - *clkp =3D qdev_init_clock_in(dev, elem->name, elem->callback, = dev); + *clkp =3D qdev_init_clock_in(dev, elem->name, elem->callback, = dev, + elem->callback_events); } } } diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 7a0d289efaf..2b436700ce6 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -39,7 +39,7 @@ static void mips_cps_init(Object *obj) SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); MIPSCPSState *s =3D MIPS_CPS(obj); =20 - s->clock =3D qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, NULL); + s->clock =3D qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, NULL, 0); /* * Cover entire address space as there do not seem to be any * constraints for the base address of CPC and GIC. diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index 7e415a017c9..75e6c574d46 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -107,7 +107,7 @@ static void pll_update(CprmanPllState *pll) clock_update_hz(pll->out, freq); } =20 -static void pll_xosc_update(void *opaque) +static void pll_xosc_update(void *opaque, ClockEvent event) { pll_update(CPRMAN_PLL(opaque)); } @@ -116,7 +116,8 @@ static void pll_init(Object *obj) { CprmanPllState *s =3D CPRMAN_PLL(obj); =20 - s->xosc_in =3D qdev_init_clock_in(DEVICE(s), "xosc-in", pll_xosc_updat= e, s); + s->xosc_in =3D qdev_init_clock_in(DEVICE(s), "xosc-in", pll_xosc_updat= e, + s, ClockUpdate); s->out =3D qdev_init_clock_out(DEVICE(s), "out"); } =20 @@ -209,7 +210,7 @@ static void pll_update_all_channels(BCM2835CprmanState = *s, } } =20 -static void pll_channel_pll_in_update(void *opaque) +static void pll_channel_pll_in_update(void *opaque, ClockEvent event) { pll_channel_update(CPRMAN_PLL_CHANNEL(opaque)); } @@ -219,7 +220,8 @@ static void pll_channel_init(Object *obj) CprmanPllChannelState *s =3D CPRMAN_PLL_CHANNEL(obj); =20 s->pll_in =3D qdev_init_clock_in(DEVICE(s), "pll-in", - pll_channel_pll_in_update, s); + pll_channel_pll_in_update, s, + ClockUpdate); s->out =3D qdev_init_clock_out(DEVICE(s), "out"); } =20 @@ -303,7 +305,7 @@ static void clock_mux_update(CprmanClockMuxState *mux) clock_update_hz(mux->out, freq); } =20 -static void clock_mux_src_update(void *opaque) +static void clock_mux_src_update(void *opaque, ClockEvent event) { CprmanClockMuxState **backref =3D opaque; CprmanClockMuxState *s =3D *backref; @@ -335,7 +337,8 @@ static void clock_mux_init(Object *obj) s->backref[i] =3D s; s->srcs[i] =3D qdev_init_clock_in(DEVICE(s), name, clock_mux_src_update, - &s->backref[i]); + &s->backref[i], + ClockUpdate); g_free(name); } =20 @@ -380,7 +383,7 @@ static void dsi0hsck_mux_update(CprmanDsi0HsckMuxState = *s) clock_update(s->out, clock_get(src)); } =20 -static void dsi0hsck_mux_in_update(void *opaque) +static void dsi0hsck_mux_in_update(void *opaque, ClockEvent event) { dsi0hsck_mux_update(CPRMAN_DSI0HSCK_MUX(opaque)); } @@ -390,8 +393,10 @@ static void dsi0hsck_mux_init(Object *obj) CprmanDsi0HsckMuxState *s =3D CPRMAN_DSI0HSCK_MUX(obj); DeviceState *dev =3D DEVICE(obj); =20 - s->plla_in =3D qdev_init_clock_in(dev, "plla-in", dsi0hsck_mux_in_upda= te, s); - s->plld_in =3D qdev_init_clock_in(dev, "plld-in", dsi0hsck_mux_in_upda= te, s); + s->plla_in =3D qdev_init_clock_in(dev, "plla-in", dsi0hsck_mux_in_upda= te, + s, ClockUpdate); + s->plld_in =3D qdev_init_clock_in(dev, "plld-in", dsi0hsck_mux_in_upda= te, + s, ClockUpdate); s->out =3D qdev_init_clock_out(DEVICE(s), "out"); } =20 diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c index 0bcae9ce957..a1ee67dc9a1 100644 --- a/hw/misc/npcm7xx_clk.c +++ b/hw/misc/npcm7xx_clk.c @@ -586,15 +586,26 @@ static const DividerInitInfo divider_init_info_list[]= =3D { }, }; =20 +static void npcm7xx_clk_update_pll_cb(void *opaque, ClockEvent event) +{ + npcm7xx_clk_update_pll(opaque); +} + static void npcm7xx_clk_pll_init(Object *obj) { NPCM7xxClockPLLState *pll =3D NPCM7XX_CLOCK_PLL(obj); =20 pll->clock_in =3D qdev_init_clock_in(DEVICE(pll), "clock-in", - npcm7xx_clk_update_pll, pll); + npcm7xx_clk_update_pll_cb, pll, + ClockUpdate); pll->clock_out =3D qdev_init_clock_out(DEVICE(pll), "clock-out"); } =20 +static void npcm7xx_clk_update_sel_cb(void *opaque, ClockEvent event) +{ + npcm7xx_clk_update_sel(opaque); +} + static void npcm7xx_clk_sel_init(Object *obj) { int i; @@ -603,16 +614,23 @@ static void npcm7xx_clk_sel_init(Object *obj) for (i =3D 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) { sel->clock_in[i] =3D qdev_init_clock_in(DEVICE(sel), g_strdup_printf("clock-in[%d]", i), - npcm7xx_clk_update_sel, sel); + npcm7xx_clk_update_sel_cb, sel, ClockUpdate); } sel->clock_out =3D qdev_init_clock_out(DEVICE(sel), "clock-out"); } + +static void npcm7xx_clk_update_divider_cb(void *opaque, ClockEvent event) +{ + npcm7xx_clk_update_divider(opaque); +} + static void npcm7xx_clk_divider_init(Object *obj) { NPCM7xxClockDividerState *div =3D NPCM7XX_CLOCK_DIVIDER(obj); =20 div->clock_in =3D qdev_init_clock_in(DEVICE(div), "clock-in", - npcm7xx_clk_update_divider, div); + npcm7xx_clk_update_divider_cb, + div, ClockUpdate); div->clock_out =3D qdev_init_clock_out(DEVICE(div), "clock-out"); } =20 @@ -875,7 +893,7 @@ static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLK= State *s) { int i; =20 - s->clkref =3D qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL); + s->clkref =3D qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL, 0); =20 /* First pass: init all converter modules */ QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) !=3D NPCM7XX_CLOCK_NR= _PLLS); diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c index dabcb6c0f95..ce192bb2741 100644 --- a/hw/misc/npcm7xx_pwm.c +++ b/hw/misc/npcm7xx_pwm.c @@ -493,7 +493,7 @@ static void npcm7xx_pwm_init(Object *obj) memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s, TYPE_NPCM7XX_PWM, 4 * KiB); sysbus_init_mmio(sbd, &s->iomem); - s->clock =3D qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL); + s->clock =3D qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL, 0); =20 for (i =3D 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { object_property_add_uint32_ptr(obj, "freq[*]", diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 66504a9d3ab..c66d7db177d 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -307,9 +307,10 @@ static void zynq_slcr_propagate_clocks(ZynqSLCRState *= s) clock_propagate(s->uart1_ref_clk); } =20 -static void zynq_slcr_ps_clk_callback(void *opaque) +static void zynq_slcr_ps_clk_callback(void *opaque, ClockEvent event) { ZynqSLCRState *s =3D (ZynqSLCRState *) opaque; + zynq_slcr_compute_clocks(s); zynq_slcr_propagate_clocks(s); } @@ -576,7 +577,7 @@ static const MemoryRegionOps slcr_ops =3D { }; =20 static const ClockPortInitArray zynq_slcr_clocks =3D { - QDEV_CLOCK_IN(ZynqSLCRState, ps_clk, zynq_slcr_ps_clk_callback), + QDEV_CLOCK_IN(ZynqSLCRState, ps_clk, zynq_slcr_ps_clk_callback, ClockU= pdate), QDEV_CLOCK_OUT(ZynqSLCRState, uart0_ref_clk), QDEV_CLOCK_OUT(ZynqSLCRState, uart1_ref_clk), QDEV_CLOCK_END diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c index ef49f5852d3..d4a509c798e 100644 --- a/hw/timer/cmsdk-apb-dualtimer.c +++ b/hw/timer/cmsdk-apb-dualtimer.c @@ -449,7 +449,7 @@ static void cmsdk_apb_dualtimer_reset(DeviceState *dev) s->timeritop =3D 0; } =20 -static void cmsdk_apb_dualtimer_clk_update(void *opaque) +static void cmsdk_apb_dualtimer_clk_update(void *opaque, ClockEvent event) { CMSDKAPBDualTimer *s =3D CMSDK_APB_DUALTIMER(opaque); int i; @@ -478,7 +478,8 @@ static void cmsdk_apb_dualtimer_init(Object *obj) sysbus_init_irq(sbd, &s->timermod[i].timerint); } s->timclk =3D qdev_init_clock_in(DEVICE(s), "TIMCLK", - cmsdk_apb_dualtimer_clk_update, s); + cmsdk_apb_dualtimer_clk_update, s, + ClockUpdate); } =20 static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index ee51ce3369c..68aa1a76360 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -204,7 +204,7 @@ static void cmsdk_apb_timer_reset(DeviceState *dev) ptimer_transaction_commit(s->timer); } =20 -static void cmsdk_apb_timer_clk_update(void *opaque) +static void cmsdk_apb_timer_clk_update(void *opaque, ClockEvent event) { CMSDKAPBTimer *s =3D CMSDK_APB_TIMER(opaque); =20 @@ -223,7 +223,7 @@ static void cmsdk_apb_timer_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->timerint); s->pclk =3D qdev_init_clock_in(DEVICE(s), "pclk", - cmsdk_apb_timer_clk_update, s); + cmsdk_apb_timer_clk_update, s, ClockUpdat= e); } =20 static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c index 36e2c07db26..4efdf135b82 100644 --- a/hw/timer/npcm7xx_timer.c +++ b/hw/timer/npcm7xx_timer.c @@ -627,7 +627,7 @@ static void npcm7xx_timer_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); qdev_init_gpio_out_named(dev, &w->reset_signal, NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1); - s->clock =3D qdev_init_clock_in(dev, "clock", NULL, NULL); + s->clock =3D qdev_init_clock_in(dev, "clock", NULL, NULL, 0); } =20 static const VMStateDescription vmstate_npcm7xx_base_timer =3D { diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watch= dog.c index 302f1711738..5a2cd46eb76 100644 --- a/hw/watchdog/cmsdk-apb-watchdog.c +++ b/hw/watchdog/cmsdk-apb-watchdog.c @@ -310,7 +310,7 @@ static void cmsdk_apb_watchdog_reset(DeviceState *dev) ptimer_transaction_commit(s->timer); } =20 -static void cmsdk_apb_watchdog_clk_update(void *opaque) +static void cmsdk_apb_watchdog_clk_update(void *opaque, ClockEvent event) { CMSDKAPBWatchdog *s =3D CMSDK_APB_WATCHDOG(opaque); =20 @@ -329,7 +329,8 @@ static void cmsdk_apb_watchdog_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->wdogint); s->wdogclk =3D qdev_init_clock_in(DEVICE(s), "WDOGCLK", - cmsdk_apb_watchdog_clk_update, s); + cmsdk_apb_watchdog_clk_update, s, + ClockUpdate); =20 s->is_luminary =3D false; s->id =3D cmsdk_apb_watchdog_id; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index ad163ead625..2f3d9d2ce2c 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -636,7 +636,7 @@ static void mips_cpu_initfn(Object *obj) MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(obj); =20 cpu_set_cpustate_pointers(cpu); - cpu->clock =3D qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu); + cpu->clock =3D qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0); env->cpu_model =3D mcc->cpu_def; } =20 --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16137462361912.654887936638488; Fri, 19 Feb 2021 06:50:36 -0800 (PST) Received: from localhost ([::1]:33784 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD774-0004MQ-VT for importer@patchew.org; Fri, 19 Feb 2021 09:50:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33360) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73B-0001zG-Ux for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:34 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:54991) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD731-0003M4-Sz for qemu-devel@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=X3f+n7+0c+b3Y+gX92OT7kIrAKPQDQz8ayoCWLv3PMg=; b=VWB/DUuyb0tBp9brES9dBytt3JuUlkTTvflMsghe8zbXYK/KDWXG/5dcW9ZLni+d6J p1+7liCbj+lUPfEYHczHGfDPeEUydDqzjtBd4Ysmdaj/hkeaVR5eZSbyuBWMeqsd9OMA Wu8HT4/8xfejbdong1R7gmLS/crm8EsjQwwYwulI2akcdZdQ/bFh+UtygqV2vt8CrKjP 9R1zoCOpuavFzGrCxwNEz2vDLJuwnJnrekTE/pyOrBjQ2AxiTxwOSvq9xVP9I/cqjXcq IIKYgYm3MezguXA90cLT1Dxbps0tbAQMh3621omaiFtQJX1MHb1jukkNKvEfvrkWEJdQ DEqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X3f+n7+0c+b3Y+gX92OT7kIrAKPQDQz8ayoCWLv3PMg=; b=e3yd6I+V1Tm+g1TOLH9iYwBHDwDFnN80A2asXJeOiBxnAq0d9bgxg3CAVz1X3Dfl74 6kVs/whJAc6ZlQE+pq26VEWpqbycBjGwqpB2N94+qZRUiYLX2Ls4Ld81u/sKgmZwZ6J4 Wc4Vf49FYYWGFlTNy52kdEKNW+Uh7sRJpJYo5y4CcG8Ov/Pgh8bZdZASfcEnVdhvpYtZ MC351QKCjAaorMFBYWs5pBkNlrWQhUsxfcdAdkHbIoyqDaO99aP/BmodhnCpMktcVjgh cGXVYIIXOqC8rBvRrP4eEpGeb8l7M8ftg/4KHQ6f1qRDjWogZx0ycDKDAzPF8LMVJJHI MDjg== X-Gm-Message-State: AOAM531h/0GqqT4iHjzYIrEsXlOltDIEFue147ASyypYDyHCdCEoMRJf LILNqUaXXRWAe/nTE+LZdBoUUw== X-Google-Smtp-Source: ABdhPJw6QMkaJvY0U9jbQz/dmTgs6wYmm6/85lBn6N1sRDqaXPqmKk6lBYhah6lTItsdPEXBewo1Fg== X-Received: by 2002:a7b:c842:: with SMTP id c2mr8582384wml.100.1613745982137; Fri, 19 Feb 2021 06:46:22 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/44] clock: Add ClockPreUpdate callback event type Date: Fri, 19 Feb 2021 14:45:35 +0000 Message-Id: <20210219144617.4782-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Add a new callback event type ClockPreUpdate, which is called on period changes before the period is updated. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel Reviewed-by: Hao Wu Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- docs/devel/clocks.rst | 9 ++++++++- include/hw/clock.h | 1 + hw/core/clock.c | 3 +++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst index cd344e3fe5d..f0391e76b4f 100644 --- a/docs/devel/clocks.rst +++ b/docs/devel/clocks.rst @@ -181,7 +181,14 @@ events. =20 The events currently supported are: =20 - * ``ClockUpdate`` : called after the input clock's period has changed + * ``ClockPreUpdate`` : called when the input clock's period is about to + update. This is useful if the device needs to do some action for + which it needs to know the old value of the clock period. During + this callback, Clock API functions like ``clock_get()`` or + ``clock_ticks_to_ns()`` will use the old period. + * ``ClockUpdate`` : called after the input clock's period has changed. + During this callback, Clock API functions like ``clock_ticks_to_ns()`` + will use the new period. =20 Note that a clock only has one callback: it is not possible to register different functions for different events. You must register a single diff --git a/include/hw/clock.h b/include/hw/clock.h index 282a37f7c5a..2ba44e14424 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -30,6 +30,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(Clock, CLOCK) */ typedef enum ClockEvent { ClockUpdate =3D 1, /* Clock period has just updated */ + ClockPreUpdate =3D 2, /* Clock period is about to update */ } ClockEvent; =20 typedef void ClockCallback(void *opaque, ClockEvent event); diff --git a/hw/core/clock.c b/hw/core/clock.c index 4479eff145b..fc5a99683f8 100644 --- a/hw/core/clock.c +++ b/hw/core/clock.c @@ -81,6 +81,9 @@ static void clock_propagate_period(Clock *clk, bool call_= callbacks) =20 QLIST_FOREACH(child, &clk->children, sibling) { if (child->period !=3D clk->period) { + if (call_callbacks) { + clock_call_callback(child, ClockPreUpdate); + } child->period =3D clk->period; trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk), CLOCK_PERIOD_TO_HZ(clk->period), --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613746410614289.56515040216584; Fri, 19 Feb 2021 06:53:30 -0800 (PST) Received: from localhost ([::1]:44412 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD79t-0000Sl-0x for importer@patchew.org; Fri, 19 Feb 2021 09:53:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33380) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73C-00020Q-OK for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:34 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:40327) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD734-0003MF-Jx for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:34 -0500 Received: by mail-wm1-x332.google.com with SMTP id o24so7861444wmh.5 for ; Fri, 19 Feb 2021 06:46:23 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=a11pg5cH1ykxEu6V8jLMW9ZxX3RV9/5IG0HAgyAT898=; b=bNDZxpGNQsX9JBhRw6fzBVnXo3cFurIa2B5ma421Md8RwMwQ0pMkZqCEc5cPQtAxEk PZ2N0LHEHw8/5vZUv6EjarjI4dY8fo1WrjE/RmpTk5p3CTY4u+EzfksFTnMbsxF/E8lz l5o9Zt0N+5GsT3p+2b+k7ScBhWq8moirp7mEJZAAIB4C6UTajw/y9Xgj1b3DZISIiNd1 02iUzrEX2BUwDNLH3t46oYRaQJRQuUNaUQPklEaCFGhFZ0q3QnC53Jpk7+0v+fyuxyoB I/G3pR4g2nCLinZ2IxVmYrLlZftK5qH/RpMYxyQofdQyL1w6LW/2eiBAbMs6aU6y4e83 rEdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a11pg5cH1ykxEu6V8jLMW9ZxX3RV9/5IG0HAgyAT898=; b=gLqYAXOkxLq5lANduZ7uNq9orU2molk2ZYg7taSh8wP5TbijgaANl3YTbRGKYpMbpY Rw4Wdv5PZ+NVafL03xdVzf0yjEfscRPKEDXPmcUh2AelqQuVXr8W1FkYDM/cpcrEG3Sb 2amV/2X4zLUDWZt3ku/q+rQKpKQFP0RSyoK4+DDx5IMIf38XfqxgKUHVay1urvugo3/M 2vOejjUd+mXl1ntQvzYIZbj81aJfoofvO6bk03l2TmVAhuFOQ1KNgc9W2iG5nwqoPjzs 4kPDVZuwzOYaVVwzJ8bHClMkS2V6F559q4AlMuSXzBq8j9GDJC+eSNoGYTS6y79vkd13 DTig== X-Gm-Message-State: AOAM533NoijMi8reh0eJta8BF902JWrOYn+1mH6fYbZEgfy+LZBzkNRb 51+8keSDXv9G6Sxpx7n5kHY3cl97LbU3ng== X-Google-Smtp-Source: ABdhPJzazil8Coabza58SvKcUBklDyCHd9xjgWWNJWsUWx0bQYn1QyPpf5ZoqhJOjjWWHROaGwUtuw== X-Received: by 2002:a05:600c:20f:: with SMTP id 15mr1315419wmi.88.1613745982798; Fri, 19 Feb 2021 06:46:22 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 03/44] clock: Add clock_ns_to_ticks() function Date: Fri, 19 Feb 2021 14:45:36 +0000 Message-Id: <20210219144617.4782-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Add a clock_ns_to_ticks() function which does the opposite of clock_ticks_to_ns(): given a duration in nanoseconds, it returns the number of clock ticks that would happen in that time. This is useful for devices that have a free running counter register whose value can be calculated when it is read. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel Reviewed-by: Hao Wu Tested-by: Philippe Mathieu-Daud=C3=A9 --- docs/devel/clocks.rst | 12 ++++++++++++ include/hw/clock.h | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst index f0391e76b4f..956bd147ea0 100644 --- a/docs/devel/clocks.rst +++ b/docs/devel/clocks.rst @@ -360,6 +360,18 @@ rather than simply passing it to a QEMUTimer function = like ``timer_mod_ns()`` then you should be careful to avoid overflow in those calculations, of course.) =20 +Obtaining tick counts +--------------------- + +For calculations where you need to know the number of ticks in +a given duration, use ``clock_ns_to_ticks()``. This function handles +possible non-whole-number-of-nanoseconds periods and avoids +potential rounding errors. It will return '0' if the clock is stopped +(i.e. it has period zero). If the inputs imply a tick count that +overflows a 64-bit value (a very long duration for a clock with a +very short period) the output value is truncated, so effectively +the 64-bit output wraps around. + Changing a clock period ----------------------- =20 diff --git a/include/hw/clock.h b/include/hw/clock.h index 2ba44e14424..a7187eab95e 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -286,6 +286,47 @@ static inline uint64_t clock_ticks_to_ns(const Clock *= clk, uint64_t ticks) return ns_low >> 32 | ns_high << 32; } =20 +/** + * clock_ns_to_ticks: + * @clk: the clock to query + * @ns: duration in nanoseconds + * + * Returns the number of ticks this clock would make in the given + * number of nanoseconds. Because a clock can have a period which + * is not a whole number of nanoseconds, it is important to use this + * function rather than attempting to obtain a "period in nanoseconds" + * value and then dividing the duration by that value. + * + * If the clock is stopped (ie it has period zero), returns 0. + * + * For some inputs the result could overflow a 64-bit value (because + * the clock's period is short and the duration is long). In these + * cases we truncate the result to a 64-bit value. This is on the + * assumption that generally the result is going to be used to report + * a 32-bit or 64-bit guest register value, so wrapping either cannot + * happen or is the desired behaviour. + */ +static inline uint64_t clock_ns_to_ticks(const Clock *clk, uint64_t ns) +{ + /* + * ticks =3D duration_in_ns / period_in_ns + * =3D ns / (period / 2^32) + * =3D (ns * 2^32) / period + * The hi, lo inputs to divu128() are (ns << 32) as a 128 bit value. + */ + uint64_t lo =3D ns << 32; + uint64_t hi =3D ns >> 32; + if (clk->period =3D=3D 0) { + return 0; + } + /* + * Ignore divu128() return value as we've caught div-by-zero and don't + * need different behaviour for overflow. + */ + divu128(&lo, &hi, clk->period); + return lo; +} + /** * clock_is_enabled: * @clk: a clock --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613746266675226.651345437523; Fri, 19 Feb 2021 06:51:06 -0800 (PST) Received: from localhost ([::1]:35814 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD77Z-0005NO-Cg for importer@patchew.org; Fri, 19 Feb 2021 09:51:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33338) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73B-0001xG-84 for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:33 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:38701) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD732-0003MN-UW for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:32 -0500 Received: by mail-wm1-x32b.google.com with SMTP id x4so7881199wmi.3 for ; Fri, 19 Feb 2021 06:46:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Kt9byFk/LgRYLWsesWus/pJj6/v7OG/s7CQX0jHU3wU=; b=hJ6ps3LKNijg+I0wue8Ayb2mLLZeqy8OQH9zmRxB7NdxxjfPhQ3iFy2aOiamQ3WjlK UMbxk/Fmd+YSFN1kFlF2ulQYKycOD87SqI7S+japvxE60Qz3H/M3MD3peOoj72Bj+ktR irhG3MRXVCYh0DLq/GPCv229HphRqySikowwTrI+arExZuo3rp+zhuIAvAcGf0m8o3Za 8tPMD6pmKeT5syD0bSEUc1FUTZPQjo87ub4VFunKgKgOn2TkZWZu24y5UUhLKC9enlpO 0u+n1wa4mKxpkzBvaD1h9ZGyuOEJw1Jux9G4CxT1kOxoF4LoHAzi/Y3jDyhasK5HljHV a8Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Kt9byFk/LgRYLWsesWus/pJj6/v7OG/s7CQX0jHU3wU=; b=WtPob9L/hdDhW7j8v7xO+zaSZLbjglhVt6Ny75Oebe17ruo4AR96wzeNl48jaQJ49N adnwmCZUVthusGDY0MOSBNKSi1HjOATHxPzIUDRPLGxDmAQ5HfPrnGZRddYWRTiYEAGQ EduEvLblYMjZRVk8LizVTMBNeDBHphwU/Xh0VEPVBNVP8BvWG7EXSmUd0+gvcbLf1fN1 m3GUfEZyUPEI1Y0Wbp6ZMHm6z/37pNiIATzb+/VCOU5xo/FsTA+7ZIwAqyO2JV4qQ/XS uUjshYdYs/DDTaQULSW0dRqWUfLLE7vKLOptirqqRVu7kY9JKjQcZWVcIJbihZhW4Nre 6BgQ== X-Gm-Message-State: AOAM530WY6aAqOd0fPXd8ANc9HuWw3SAOimMSH3GLfDJ9bgwciKJk5G+ jFGQhPyOqs9p0A6DOloTKjfkiBY4iyQzvQ== X-Google-Smtp-Source: ABdhPJwBjR12sI7Q879d2ix1KipFxrMeoLwHBepUdlCTQUsixYE3Bgbzp0m6FGfpxR1yhM6lkQb63Q== X-Received: by 2002:a05:600c:c3:: with SMTP id u3mr4286341wmm.64.1613745983415; Fri, 19 Feb 2021 06:46:23 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/44] hw/timer/npcm7xx_timer: Use new clock_ns_to_ticks() Date: Fri, 19 Feb 2021 14:45:37 +0000 Message-Id: <20210219144617.4782-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Use the new clock_ns_to_ticks() function in npcm7xx_timer where appropriate. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Hao Wu Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/timer/npcm7xx_timer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c index 4efdf135b82..32f5e021f85 100644 --- a/hw/timer/npcm7xx_timer.c +++ b/hw/timer/npcm7xx_timer.c @@ -138,8 +138,8 @@ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *= t, uint32_t count) /* Convert a time interval in nanoseconds to a timer cycle count. */ static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns) { - return ns / clock_ticks_to_ns(t->ctrl->clock, - npcm7xx_tcsr_prescaler(t->tcsr)); + return clock_ns_to_ticks(t->ctrl->clock, ns) / + npcm7xx_tcsr_prescaler(t->tcsr); } =20 static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTime= r *t) --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613746688511772.5312946732321; Fri, 19 Feb 2021 06:58:08 -0800 (PST) Received: from localhost ([::1]:33268 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7EN-0007je-Ei for importer@patchew.org; Fri, 19 Feb 2021 09:58:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33516) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73H-00026k-WE for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:40 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:40331) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD734-0003NF-Lg for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:39 -0500 Received: by mail-wm1-x336.google.com with SMTP id o24so7861507wmh.5 for ; Fri, 19 Feb 2021 06:46:25 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PMexNJ719krfbbkXchv0cf2DQZcqXIeJxRfo8lnTfNc=; b=us72YYpzEQRypK7yqEvJPgWEnnysZXlTF/Cna4AotPKjvRwnVvNE3Gkq2lVbMc6lzl JPqoLbQkhcrc8oGg9WhIYzqTZGFLBowu9T8/lZlOdotAnTGpDxuoyjbaCqEtsqcITGBp ZDtrBXH72b7tXIog//kb+fJa1v5tEcbflYkTeE+FgRNK+i2t6PQkjPdyTqvb/jjbpp9Z m7DRyUJ4zVd4/U/4lBrf/3ypmVs2umVDbubibrGB8JBMKgwv6up0BEfI1ksNQ+9uafGn EN8cPPUpo4zQoAf7PMu6tZgdPk7fc3BZWqJneMpTjaauPvlJwXYVDM6d1bh45QVrVutw 9INg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PMexNJ719krfbbkXchv0cf2DQZcqXIeJxRfo8lnTfNc=; b=YaflgVb22HX9dBT21CamiiVgTyqtUP/31WDwaplyGf66PAngmA4Zc6fVd5O3kuz5cV O4lOESvxx/9SFEidJXW9xfDUic1toXvs0P0bUJfySt2NbSAoue4BoAlvXA/Pn7RFXRQs 4dYjHeFGa1pgBQtrETInuBKsAmcbHFyTb625rMcDNw9eP+19bBI24Y0feK+d7FnSkaR2 uNivqzM9ZMlqzwkVp4BsohKL3eWTLH+4YhogMqWFA7ciqSat5sPM5gOcrdxraoRTxopu eIRFXUwGDeT1Hz6OitSsZL2Y9ztH/rA26RbvycXdHtL2ZieZ0oKqBBV/OKAakolUgVZq LIzQ== X-Gm-Message-State: AOAM530pc0oLjoeYJR4WP/cVYFC4xz5ORF26ZoR3ORZ1vVxGpcnJITDZ eQ3fEBIPWJrgNvOFkQPr8i8dfQ== X-Google-Smtp-Source: ABdhPJyDhW6qmFOBERZxiiJj/OFhk8mGHYOeuBviVGeiTgMra+bLJJqKns+fDjOiUS38cRdJqED87Q== X-Received: by 2002:a1c:c906:: with SMTP id f6mr8378400wmb.128.1613745984131; Fri, 19 Feb 2021 06:46:24 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 05/44] hw/arm/armsse: Introduce SSE subsystem version property Date: Fri, 19 Feb 2021 14:45:38 +0000 Message-Id: <20210219144617.4782-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We model Arm "Subsystems for Embedded" SoC subsystems using generic code which is split into various sub-devices which are configurable by QOM properties to handle the behaviour differences between the SSE subsystems we implement. Currently the only sub-device which needs to change is the IOTKIT_SYSCTL device, and we do this with a mix of properties that directly specify divergent behaviours (eg CPUWAIT_RST) and passing it the SYS_VERSION register value as a way for it to distinguish IoTKit from SSE-200. The "pass SYS_VERSION" approach is already a bit hacky, since the IOTKIT_SYSCTL device has to know that the different part of the register value happens to be bits [31:28]. For SSE-300 this register is renamed SOC_IDENTITY and has a different format entirely, all of whose fields can be configured by the SoC integrator when they integrate the SSE into their SoC, and so "pass SYS_VERSION" breaks down completely. Switch to using a simple integer property representing an internal-to-QEMU enumeration of the SSE flavour. For the moment we only need this in IOTKIT_SYSCTL, but as we add SSE-300 support a few of the other devices will also need to know. We define and permit a value for the SSE-300 so we can start using it in subsequent commits which add SSE-300 support. The now-redundant is_sse200 flag in IoTKitSysCtl will be removed in the following commit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- I didn't use a full-on qdev/QOM 'enum' property here because that requires messing with the QAPI schema, which seems like overkill for this entirely-internal-to-the-implementation bit of information passing. --- include/hw/arm/armsse-version.h | 42 +++++++++++++++++++++++++++++++++ include/hw/misc/iotkit-sysctl.h | 7 +++--- hw/arm/armsse.c | 8 +++++-- hw/misc/iotkit-sysctl.c | 11 +++++---- 4 files changed, 58 insertions(+), 10 deletions(-) create mode 100644 include/hw/arm/armsse-version.h diff --git a/include/hw/arm/armsse-version.h b/include/hw/arm/armsse-versio= n.h new file mode 100644 index 00000000000..60780fa9843 --- /dev/null +++ b/include/hw/arm/armsse-version.h @@ -0,0 +1,42 @@ +/* + * ARM SSE (Subsystems for Embedded): IoTKit, SSE-200 + * + * Copyright (c) 2020 Linaro Limited + * Written by Peter Maydell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#ifndef ARMSSE_VERSION_H +#define ARMSSE_VERSION_H + + +/* + * Define an enumeration of the possible values of the sse-version + * property implemented by various sub-devices of the SSE, and + * a validation function that checks that a valid value has been passed. + * These are arbitrary QEMU-internal values (nobody should be creating + * the sub-devices of the SSE except for the SSE object itself), but + * we pick obvious numbers for the benefit of people debugging with gdb. + */ +enum { + ARMSSE_IOTKIT =3D 0, + ARMSSE_SSE200 =3D 200, + ARMSSE_SSE300 =3D 300, +}; + +static inline bool armsse_version_valid(uint32_t sse_version) +{ + switch (sse_version) { + case ARMSSE_IOTKIT: + case ARMSSE_SSE200: + case ARMSSE_SSE300: + return true; + default: + return false; + } +} + +#endif diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysct= l.h index 2bc391138db..7cdafea3e25 100644 --- a/include/hw/misc/iotkit-sysctl.h +++ b/include/hw/misc/iotkit-sysctl.h @@ -17,9 +17,8 @@ * "system control register" blocks. * * QEMU interface: - * + QOM property "SYS_VERSION": value of the SYS_VERSION register of the - * system information block of the SSE - * (used to identify whether to provide SSE-200-only registers) + * + QOM property "sse-version": indicates which SSE version this is part= of + * (used to identify whether to provide SSE-200-only registers, etc) * + sysbus MMIO region 0: the system information register bank * + sysbus MMIO region 1: the system control register bank */ @@ -61,7 +60,7 @@ struct IoTKitSysCtl { uint32_t pdcm_pd_sram3_sense; =20 /* Properties */ - uint32_t sys_version; + uint32_t sse_version; uint32_t cpuwait_rst; uint32_t initsvtor0_rst; uint32_t initsvtor1_rst; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index fa155b72022..f509f59d4a8 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -19,6 +19,7 @@ #include "migration/vmstate.h" #include "hw/registerfields.h" #include "hw/arm/armsse.h" +#include "hw/arm/armsse-version.h" #include "hw/arm/boot.h" #include "hw/irq.h" #include "hw/qdev-clock.h" @@ -31,6 +32,7 @@ typedef enum SysConfigFormat { =20 struct ARMSSEInfo { const char *name; + uint32_t sse_version; int sram_banks; int num_cpus; uint32_t sys_version; @@ -71,6 +73,7 @@ static Property armsse_properties[] =3D { static const ARMSSEInfo armsse_variants[] =3D { { .name =3D TYPE_IOTKIT, + .sse_version =3D ARMSSE_IOTKIT, .sram_banks =3D 1, .num_cpus =3D 1, .sys_version =3D 0x41743, @@ -85,6 +88,7 @@ static const ARMSSEInfo armsse_variants[] =3D { }, { .name =3D TYPE_SSE200, + .sse_version =3D ARMSSE_SSE200, .sram_banks =3D 4, .num_cpus =3D 2, .sys_version =3D 0x22041743, @@ -951,8 +955,8 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) /* System information registers */ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000); /* System control registers */ - object_property_set_int(OBJECT(&s->sysctl), "SYS_VERSION", - info->sys_version, &error_abort); + object_property_set_int(OBJECT(&s->sysctl), "sse-version", + info->sse_version, &error_abort); object_property_set_int(OBJECT(&s->sysctl), "CPUWAIT_RST", info->cpuwait_rst, &error_abort); object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR0_RST", diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index 222511c4b04..34b37fe8824 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -28,6 +28,7 @@ #include "hw/registerfields.h" #include "hw/misc/iotkit-sysctl.h" #include "hw/qdev-properties.h" +#include "hw/arm/armsse-version.h" #include "target/arm/arm-powerctl.h" #include "target/arm/cpu.h" =20 @@ -438,10 +439,12 @@ static void iotkit_sysctl_realize(DeviceState *dev, E= rror **errp) { IoTKitSysCtl *s =3D IOTKIT_SYSCTL(dev); =20 - /* The top 4 bits of the SYS_VERSION register tell us if we're an SSE-= 200 */ - if (extract32(s->sys_version, 28, 4) =3D=3D 2) { - s->is_sse200 =3D true; + if (!armsse_version_valid(s->sse_version)) { + error_setg(errp, "invalid sse-version value %d", s->sse_version); + return; } + + s->is_sse200 =3D s->sse_version =3D=3D ARMSSE_SSE200; } =20 static bool sse200_needed(void *opaque) @@ -493,7 +496,7 @@ static const VMStateDescription iotkit_sysctl_vmstate = =3D { }; =20 static Property iotkit_sysctl_props[] =3D { - DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl, sys_version, 0), + DEFINE_PROP_UINT32("sse-version", IoTKitSysCtl, sse_version, 0), DEFINE_PROP_UINT32("CPUWAIT_RST", IoTKitSysCtl, cpuwait_rst, 0), DEFINE_PROP_UINT32("INITSVTOR0_RST", IoTKitSysCtl, initsvtor0_rst, 0x10000000), --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=JjzammxlnoyyAwwWhFgyD6FVkMWPaU3DMBqWjhwZgfk=; b=yelb6rlN3TMEUdtSsK4E/CbAAHpVpT7NJIbyy4l/jesi59UhvzYB3mkkvU85KkntT6 tId7Xw/jX4G4HBiMb52ChjBO4IWqU5EiGplFf1EhCbGqpcGLrjZ1j5/k6ykpPbvjcqNk Bc/LeYKxTRtBD20jiSAnO52EvtoZ+9NAhdWw9AEzRgVtiyNcjex+R3v9MPqTT5RBHtu9 iMOLPe/C0il+QaVUG5o3dxuG2G4YArdFt/UCjZyHl841apvkTnpuvSYi8r2Zh/4ARgB4 yDu/GPLli58I+3UTMXUZoozLlzf2MKorE58NLgJeh/2SyzwryKOZtmoiTpWq8sF7PFYK ti6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JjzammxlnoyyAwwWhFgyD6FVkMWPaU3DMBqWjhwZgfk=; b=gk3pD2/LnoOBnmBejQPPJy3kSviqAKfGeK1kLkafj34U5U2TdSycCnHRD/dAq+DMUc goITsmbDJl0EVud8HO7NXCDWZIi/3/R+dZPnjGf1tRVAS8pmH0Hpg9eYwoH59VFQkV07 PBDWL1eXtkYRYaEjYgFq74WCAz9POhHsnvzJZ7F9e3/XeXF2kCpnuE7Ewrv5EHoG5TxL ddXs85IHLIql4DcL4Po/J9LOyoIppNCFOgNszpstXHGZMKuoXJsHC6a7cmZx7KkMc/h0 K9CIgPew9cZ4N//aEwJ4iOoIvexm64l8dkFrgXvA3gfv8VZgT4k5YoSOfxn0qoRD6n0P kVUQ== X-Gm-Message-State: AOAM5331cxpfkqXXXcEXJTMGvNYwp3aQ1IkJ2bbXvSPH0umgC0+LcKJy ZYJpxSHbawciCAdEWmi+F+pl4A== X-Google-Smtp-Source: ABdhPJzk6PnizGY+7HHeQXL1tWRu3gGKhS+eqkpUuAI2UkY2IcX5wOLfhre4JAI9bt5JmumWkQwIJg== X-Received: by 2002:adf:fa01:: with SMTP id m1mr2165556wrr.209.1613745985002; Fri, 19 Feb 2021 06:46:25 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 06/44] hw/misc/iotkit-sysctl: Remove is_sse200 flag Date: Fri, 19 Feb 2021 14:45:39 +0000 Message-Id: <20210219144617.4782-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Remove the is_sse200 flag in favour of just directly testing the new sse_version field. Since some of these registers exist in the SSE-300 but some do not or have different behaviour, we expand out the if() statements in the read and write functions into switch()es, so we have an easy place to put SSE-300 specific behaviour. (Until we do add the SSE-300 behaviour, the thing preventing us reaching the "unreachable" default cases is that armsse.c doesn't yet pass us an ARMSSE_SSE300 version.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/iotkit-sysctl.h | 2 - hw/misc/iotkit-sysctl.c | 256 +++++++++++++++++++++++--------- 2 files changed, 187 insertions(+), 71 deletions(-) diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysct= l.h index 7cdafea3e25..980c2ddfd3c 100644 --- a/include/hw/misc/iotkit-sysctl.h +++ b/include/hw/misc/iotkit-sysctl.h @@ -64,8 +64,6 @@ struct IoTKitSysCtl { uint32_t cpuwait_rst; uint32_t initsvtor0_rst; uint32_t initsvtor1_rst; - - bool is_sse200; }; =20 #endif diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index 34b37fe8824..c67f5b320ab 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -101,28 +101,48 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwad= dr offset, r =3D s->secure_debug; break; case A_SCSECCTRL: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + r =3D s->scsecctrl; + break; + default: + g_assert_not_reached(); } - r =3D s->scsecctrl; break; case A_FCLK_DIV: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + r =3D s->fclk_div; + break; + default: + g_assert_not_reached(); } - r =3D s->fclk_div; break; case A_SYSCLK_DIV: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + r =3D s->sysclk_div; + break; + default: + g_assert_not_reached(); } - r =3D s->sysclk_div; break; case A_CLOCK_FORCE: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + r =3D s->clock_force; + break; + default: + g_assert_not_reached(); } - r =3D s->clock_force; break; case A_RESET_SYNDROME: r =3D s->reset_syndrome; @@ -137,60 +157,100 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwa= ddr offset, r =3D s->initsvtor0; break; case A_INITSVTOR1: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + r =3D s->initsvtor1; + break; + default: + g_assert_not_reached(); } - r =3D s->initsvtor1; break; case A_CPUWAIT: r =3D s->cpuwait; break; case A_NMI_ENABLE: - /* In IoTKit this is named BUSWAIT but is marked reserved, R/O, ze= ro */ - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: + /* In IoTKit this is named BUSWAIT but marked reserved, R/O, z= ero */ r =3D 0; break; + case ARMSSE_SSE200: + r =3D s->nmi_enable; + break; + default: + g_assert_not_reached(); } - r =3D s->nmi_enable; break; case A_WICCTRL: r =3D s->wicctrl; break; case A_EWCTRL: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + r =3D s->ewctrl; + break; + default: + g_assert_not_reached(); } - r =3D s->ewctrl; break; case A_PDCM_PD_SYS_SENSE: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + r =3D s->pdcm_pd_sys_sense; + break; + default: + g_assert_not_reached(); } - r =3D s->pdcm_pd_sys_sense; break; case A_PDCM_PD_SRAM0_SENSE: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + r =3D s->pdcm_pd_sram0_sense; + break; + default: + g_assert_not_reached(); } - r =3D s->pdcm_pd_sram0_sense; break; case A_PDCM_PD_SRAM1_SENSE: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + r =3D s->pdcm_pd_sram1_sense; + break; + default: + g_assert_not_reached(); } - r =3D s->pdcm_pd_sram1_sense; break; case A_PDCM_PD_SRAM2_SENSE: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + r =3D s->pdcm_pd_sram2_sense; + break; + default: + g_assert_not_reached(); } - r =3D s->pdcm_pd_sram2_sense; break; case A_PDCM_PD_SRAM3_SENSE: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + r =3D s->pdcm_pd_sram3_sense; + break; + default: + g_assert_not_reached(); } - r =3D s->pdcm_pd_sram3_sense; break; case A_PID4 ... A_CID3: r =3D sysctl_id[(offset - A_PID4) / 4]; @@ -284,94 +344,154 @@ static void iotkit_sysctl_write(void *opaque, hwaddr= offset, } break; case A_SCSECCTRL: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemente= d\n"); + s->scsecctrl =3D value; + break; + default: + g_assert_not_reached(); } - qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemented\n"= ); - s->scsecctrl =3D value; break; case A_FCLK_DIV: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented= \n"); + s->fclk_div =3D value; + break; + default: + g_assert_not_reached(); } - qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented\n"); - s->fclk_div =3D value; break; case A_SYSCLK_DIV: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplement= ed\n"); + s->sysclk_div =3D value; + break; + default: + g_assert_not_reached(); } - qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplemented\n= "); - s->sysclk_div =3D value; break; case A_CLOCK_FORCE: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemen= ted\n"); + s->clock_force =3D value; + break; + default: + g_assert_not_reached(); } - qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemented\= n"); - s->clock_force =3D value; break; case A_INITSVTOR1: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + s->initsvtor1 =3D value; + set_init_vtor(1, s->initsvtor1); + break; + default: + g_assert_not_reached(); } - s->initsvtor1 =3D value; - set_init_vtor(1, s->initsvtor1); break; case A_EWCTRL: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n= "); + s->ewctrl =3D value; + break; + default: + g_assert_not_reached(); } - qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n"); - s->ewctrl =3D value; break; case A_PDCM_PD_SYS_SENSE: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n= "); + s->pdcm_pd_sys_sense =3D value; + break; + default: + g_assert_not_reached(); } - qemu_log_mask(LOG_UNIMP, - "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n"); - s->pdcm_pd_sys_sense =3D value; break; case A_PDCM_PD_SRAM0_SENSE: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented= \n"); + s->pdcm_pd_sram0_sense =3D value; + break; + default: + g_assert_not_reached(); } - qemu_log_mask(LOG_UNIMP, - "IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented\n"); - s->pdcm_pd_sram0_sense =3D value; break; case A_PDCM_PD_SRAM1_SENSE: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented= \n"); + s->pdcm_pd_sram1_sense =3D value; + break; + default: + g_assert_not_reached(); } - qemu_log_mask(LOG_UNIMP, - "IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented\n"); - s->pdcm_pd_sram1_sense =3D value; break; case A_PDCM_PD_SRAM2_SENSE: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented= \n"); + s->pdcm_pd_sram2_sense =3D value; + break; + default: + g_assert_not_reached(); } - qemu_log_mask(LOG_UNIMP, - "IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented\n"); - s->pdcm_pd_sram2_sense =3D value; break; case A_PDCM_PD_SRAM3_SENSE: - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto bad_offset; + case ARMSSE_SSE200: + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented= \n"); + s->pdcm_pd_sram3_sense =3D value; + break; + default: + g_assert_not_reached(); } - qemu_log_mask(LOG_UNIMP, - "IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented\n"); - s->pdcm_pd_sram3_sense =3D value; break; case A_NMI_ENABLE: /* In IoTKit this is BUSWAIT: reserved, R/O, zero */ - if (!s->is_sse200) { + switch (s->sse_version) { + case ARMSSE_IOTKIT: goto ro_offset; + case ARMSSE_SSE200: + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplement= ed\n"); + s->nmi_enable =3D value; + break; + default: + g_assert_not_reached(); } - qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n= "); - s->nmi_enable =3D value; break; case A_SECDBGSTAT: case A_PID4 ... A_CID3: @@ -443,15 +563,13 @@ static void iotkit_sysctl_realize(DeviceState *dev, E= rror **errp) error_setg(errp, "invalid sse-version value %d", s->sse_version); return; } - - s->is_sse200 =3D s->sse_version =3D=3D ARMSSE_SSE200; } =20 static bool sse200_needed(void *opaque) { IoTKitSysCtl *s =3D IOTKIT_SYSCTL(opaque); =20 - return s->is_sse200; + return s->sse_version =3D=3D ARMSSE_SSE200; } =20 static const VMStateDescription iotkit_sysctl_sse200_vmstate =3D { --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161374643686569.41403098487888; Fri, 19 Feb 2021 06:53:56 -0800 (PST) Received: from localhost ([::1]:46226 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7AJ-0001Dg-Qg for importer@patchew.org; Fri, 19 Feb 2021 09:53:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33504) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73H-000259-Bl for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:39 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:41232) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD736-0003OS-6s for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:39 -0500 Received: by mail-wr1-x42f.google.com with SMTP id a4so6661523wro.8 for ; Fri, 19 Feb 2021 06:46:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hq96YPYIWAIHr8SDiQfrJt7AxA0+9R+fewTzgtcdfzM=; b=ABwxVvlnX1p9mScPn/apFyf8cN55bKe0se/50Tor9ianEji6u86Hbh+sphbrJq7sEG E9wfPpQCLq82qWq2UfDdpie8CK+HzUQsYetgcqiP/6tcxYL7osPickSWNIqMO1M6QPnU tsRgt/kwia9V3rtCQ/xplioBDu8rKmId1Ug0+y1x3PzlIcfxd55iNl2qPoVOn0x1ef4b za+MLJt9OHt9/Yx64aVA843aYYR2/HeZexCOR6RlRIW+i/4qGsFvtyiTGjvFwa1cBOs3 jrCV1kYyElsp28t6glQiS6njjdssKPQvA/g15iFCISnmPZjYV06KxREMotO31gL+5wdu qO7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hq96YPYIWAIHr8SDiQfrJt7AxA0+9R+fewTzgtcdfzM=; b=TxGow9U2lbYD9AE8DocNiqHFquyZ0zrP3h+X42NMfV6x6VlJqdq6JewJKAOL4OVEOP oDPtwqpd++jk882mekErLOnKa2UYOSWhYVHos8nP7GMnZyUhKUNKVIkxq9YPE2K117pO QOK13c3FInm0lG6NCC66Sgd9yDn55pKMHePXsGL3u16QpqCWo1Ja3L5QrDopR/kt+e27 mwIp3KTq2Ja34zYr5x0jsv7Nk4iLCWC/82gE6uHU3GtnuEixZx1am9LvsRMErXgiVebb 5ocu098QuM4ebf8EnUhiW/FC0ihxVXZL+pw1heTfh2z/cq6xlCeiWOurXhEb0dRrNENd reJg== X-Gm-Message-State: AOAM530uo0qo1i8AxKbpO6NynmHnOuvZrYjV7lj6R+hQEdN8/Zfvsqxi SpTy02P8BD94iAvL76vFonh/NBkneSelPA== X-Google-Smtp-Source: ABdhPJyZYCFs/hzYMOixfeqzhEuqK6be8ICXFWGv14cvUaT1YPdF4H+kVOS8KCVZNsmBpsVBAilUOA== X-Received: by 2002:a5d:5687:: with SMTP id f7mr2137005wrv.56.1613745985727; Fri, 19 Feb 2021 06:46:25 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 07/44] hw/misc/iotkit-secctl.c: Implement SSE-300 PID register values Date: Fri, 19 Feb 2021 14:45:40 +0000 Message-Id: <20210219144617.4782-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The versions of the Secure Access Configuration Register Block and Non-secure Access Configuration Register Block in the SSE-300 are the same as those in the SSE-200, but the CIDR/PIDR ID register values are different. Plumb through the sse-version property and use it to select the correct ID register values. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/iotkit-secctl.h | 2 ++ hw/arm/armsse.c | 2 ++ hw/misc/iotkit-secctl.c | 50 +++++++++++++++++++++++++++++++-- 3 files changed, 52 insertions(+), 2 deletions(-) diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secct= l.h index 227d44abe49..79a36283201 100644 --- a/include/hw/misc/iotkit-secctl.h +++ b/include/hw/misc/iotkit-secctl.h @@ -120,6 +120,8 @@ struct IoTKitSecCtl { IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC]; IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC]; IoTKitSecCtlPPC ahbexp[IOTS_NUM_APB_EXP_PPC]; + + uint32_t sse_version; }; =20 #endif diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index f509f59d4a8..9632c287351 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -654,6 +654,8 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) } =20 /* Security controller */ + object_property_set_int(OBJECT(&s->secctl), "sse-version", + info->sse_version, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->secctl), errp)) { return; } diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c index 9fdb82056a8..7b41cfa8fc5 100644 --- a/hw/misc/iotkit-secctl.c +++ b/hw/misc/iotkit-secctl.c @@ -19,6 +19,8 @@ #include "hw/registerfields.h" #include "hw/irq.h" #include "hw/misc/iotkit-secctl.h" +#include "hw/arm/armsse-version.h" +#include "hw/qdev-properties.h" =20 /* Registers in the secure privilege control block */ REG32(SECRESPCFG, 0x10) @@ -95,6 +97,19 @@ static const uint8_t iotkit_secctl_ns_idregs[] =3D { 0x0d, 0xf0, 0x05, 0xb1, }; =20 +static const uint8_t iotkit_secctl_s_sse300_idregs[] =3D { + 0x04, 0x00, 0x00, 0x00, + 0x52, 0xb8, 0x2b, 0x00, + 0x0d, 0xf0, 0x05, 0xb1, +}; + +static const uint8_t iotkit_secctl_ns_sse300_idregs[] =3D { + 0x04, 0x00, 0x00, 0x00, + 0x53, 0xb8, 0x2b, 0x00, + 0x0d, 0xf0, 0x05, 0xb1, +}; + + /* The register sets for the various PPCs (AHB internal, APB internal, * AHB expansion, APB expansion) are all set up so that they are * in 16-aligned blocks so offsets 0xN0, 0xN4, 0xN8, 0xNC are PPCs @@ -213,7 +228,14 @@ static MemTxResult iotkit_secctl_s_read(void *opaque, = hwaddr addr, case A_CID1: case A_CID2: case A_CID3: - r =3D iotkit_secctl_s_idregs[(offset - A_PID4) / 4]; + switch (s->sse_version) { + case ARMSSE_SSE300: + r =3D iotkit_secctl_s_sse300_idregs[(offset - A_PID4) / 4]; + break; + default: + r =3D iotkit_secctl_s_idregs[(offset - A_PID4) / 4]; + break; + } break; case A_SECPPCINTCLR: case A_SECMSCINTCLR: @@ -473,7 +495,14 @@ static MemTxResult iotkit_secctl_ns_read(void *opaque,= hwaddr addr, case A_CID1: case A_CID2: case A_CID3: - r =3D iotkit_secctl_ns_idregs[(offset - A_PID4) / 4]; + switch (s->sse_version) { + case ARMSSE_SSE300: + r =3D iotkit_secctl_ns_sse300_idregs[(offset - A_PID4) / 4]; + break; + default: + r =3D iotkit_secctl_ns_idregs[(offset - A_PID4) / 4]; + break; + } break; default: qemu_log_mask(LOG_GUEST_ERROR, @@ -710,6 +739,16 @@ static void iotkit_secctl_init(Object *obj) sysbus_init_mmio(sbd, &s->ns_regs); } =20 +static void iotkit_secctl_realize(DeviceState *dev, Error **errp) +{ + IoTKitSecCtl *s =3D IOTKIT_SECCTL(dev); + + if (!armsse_version_valid(s->sse_version)) { + error_setg(errp, "invalid sse-version value %d", s->sse_version); + return; + } +} + static const VMStateDescription iotkit_secctl_ppc_vmstate =3D { .name =3D "iotkit-secctl-ppc", .version_id =3D 1, @@ -775,12 +814,19 @@ static const VMStateDescription iotkit_secctl_vmstate= =3D { }, }; =20 +static Property iotkit_secctl_props[] =3D { + DEFINE_PROP_UINT32("sse-version", IoTKitSecCtl, sse_version, 0), + DEFINE_PROP_END_OF_LIST() +}; + static void iotkit_secctl_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->vmsd =3D &iotkit_secctl_vmstate; dc->reset =3D iotkit_secctl_reset; + dc->realize =3D iotkit_secctl_realize; + device_class_set_props(dc, iotkit_secctl_props); } =20 static const TypeInfo iotkit_secctl_info =3D { --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16137466185151021.3473106973149; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=UqO/lCJ8eIrVtKEmioMtB5Osx/5IZ7fMTosSEvFKa2s=; b=sGejhG3vhk4P8BJd6CLWw1Xb8Gn+hsy572HwLRsrqfnrvMAHjbzb9neDtKI4oo2qg3 9EsciE7lHNJbB7YNgLjHDAsyiZHX5vXRB4lUGF8z3yb4jmRitxsH5OG4sD2FZ/D6kG8K t8asFRwtFzyw8fYiMXVwQa1dlm1y//nYQzeiPYB+ufdK7Nwz06lhfNty5APMYs/JhUMl M64XuPeCuRO26AI1csSiUPOlbcvorGbmjCHLapjaNY8i/pS9K0Zf7ddeulnAyVLDxSgA 809bCAB3SIWr2QwGMDJfReE32CRerEyDUB5Y+//9WVfjXnghqB2X8iz0v44A4AmDzK0D GNVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UqO/lCJ8eIrVtKEmioMtB5Osx/5IZ7fMTosSEvFKa2s=; b=dk1gOwzKOgR7tjANrhM0XpbBKTfBN9xKkvrzEdtxaEBM/b8g7ENeB7Vfr0l7CI1nhw kfxe3iYX9R5mQ1KIknHPCePMYqhvmnP0s1Qei43/FUJwypdGS7tVFiiyayk8wPH5EtsM tk0faSqZu52hevUUhAvD4DZTqK1M6M5GF1LQELjIOCyJajr5z6WCpCoB/zjxym8Q2XQB kymdYc6Ssb/8e5lFrIFrGKuCenjEWkglRYScIbaxKY5dZUA9JTzs5KEyZqJMkVSD/O4d 78Klj/XhENU/V1NLeskyzWLIdcZEZE8pGt49peDEKjAaII3g0Fji2puO0ha+wasGAATV FQnw== X-Gm-Message-State: AOAM530dzXIQa7eW3U3XPCjpQq4DEqQhfv9pSXyW4VA+86rYbxIEOgM1 1cvm5ZYBrvr1NcwdKwqgEk61zw== X-Google-Smtp-Source: ABdhPJwK5DizgIp51qdlYearCqUi4jr7ebSAPAl2Ekj7q5FASOagEWWH7nzQdrIyIY1rfpM8q/6g7A== X-Received: by 2002:adf:82b3:: with SMTP id 48mr9254434wrc.22.1613745986396; Fri, 19 Feb 2021 06:46:26 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/44] hw/misc/iotkit-sysinfo.c: Implement SSE-300 PID register values Date: Fri, 19 Feb 2021 14:45:41 +0000 Message-Id: <20210219144617.4782-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The version of the SYSINFO Register Block in the SSE-300 has different CIDR/PIDR register values to the SSE-200; pass in the sse-version property and use it to select the correct ID register values. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/iotkit-sysinfo.h | 1 + hw/arm/armsse.c | 2 ++ hw/misc/iotkit-sysinfo.c | 29 +++++++++++++++++++++++++++-- 3 files changed, 30 insertions(+), 2 deletions(-) diff --git a/include/hw/misc/iotkit-sysinfo.h b/include/hw/misc/iotkit-sysi= nfo.h index 055771d2098..91bd14bdbff 100644 --- a/include/hw/misc/iotkit-sysinfo.h +++ b/include/hw/misc/iotkit-sysinfo.h @@ -38,6 +38,7 @@ struct IoTKitSysInfo { /* Properties */ uint32_t sys_version; uint32_t sys_config; + uint32_t sse_version; }; =20 #endif diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 9632c287351..67fa4ffe34a 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -951,6 +951,8 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) armsse_sys_config_value(s, info), errp)) { return; } + object_property_set_int(OBJECT(&s->sysinfo), "sse-version", + info->sse_version, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysinfo), errp)) { return; } diff --git a/hw/misc/iotkit-sysinfo.c b/hw/misc/iotkit-sysinfo.c index 52e70053df7..4bd3fd4c8f3 100644 --- a/hw/misc/iotkit-sysinfo.c +++ b/hw/misc/iotkit-sysinfo.c @@ -26,6 +26,7 @@ #include "hw/registerfields.h" #include "hw/misc/iotkit-sysinfo.h" #include "hw/qdev-properties.h" +#include "hw/arm/armsse-version.h" =20 REG32(SYS_VERSION, 0x0) REG32(SYS_CONFIG, 0x4) @@ -49,6 +50,12 @@ static const int sysinfo_id[] =3D { 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ }; =20 +static const int sysinfo_sse300_id[] =3D { + 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ + 0x58, 0xb8, 0x1b, 0x00, /* PID0..PID3 */ + 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ +}; + static uint64_t iotkit_sysinfo_read(void *opaque, hwaddr offset, unsigned size) { @@ -64,7 +71,14 @@ static uint64_t iotkit_sysinfo_read(void *opaque, hwaddr= offset, r =3D s->sys_config; break; case A_PID4 ... A_CID3: - r =3D sysinfo_id[(offset - A_PID4) / 4]; + switch (s->sse_version) { + case ARMSSE_SSE300: + r =3D sysinfo_sse300_id[(offset - A_PID4) / 4]; + break; + default: + r =3D sysinfo_id[(offset - A_PID4) / 4]; + break; + } break; default: qemu_log_mask(LOG_GUEST_ERROR, @@ -99,6 +113,7 @@ static const MemoryRegionOps iotkit_sysinfo_ops =3D { static Property iotkit_sysinfo_props[] =3D { DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysInfo, sys_version, 0), DEFINE_PROP_UINT32("SYS_CONFIG", IoTKitSysInfo, sys_config, 0), + DEFINE_PROP_UINT32("sse-version", IoTKitSysInfo, sse_version, 0), DEFINE_PROP_END_OF_LIST() }; =20 @@ -112,6 +127,16 @@ static void iotkit_sysinfo_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); } =20 +static void iotkit_sysinfo_realize(DeviceState *dev, Error **errp) +{ + IoTKitSysInfo *s =3D IOTKIT_SYSINFO(dev); + + if (!armsse_version_valid(s->sse_version)) { + error_setg(errp, "invalid sse-version value %d", s->sse_version); + return; + } +} + static void iotkit_sysinfo_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -120,7 +145,7 @@ static void iotkit_sysinfo_class_init(ObjectClass *klas= s, void *data) * This device has no guest-modifiable state and so it * does not need a reset function or VMState. */ - + dc->realize =3D iotkit_sysinfo_realize; device_class_set_props(dc, iotkit_sysinfo_props); } =20 --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613746740039567.0057515585629; Fri, 19 Feb 2021 06:59:00 -0800 (PST) Received: from localhost ([::1]:36194 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7FC-0000Yn-Sk for importer@patchew.org; Fri, 19 Feb 2021 09:58:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33618) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73K-0002AO-QV for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:45 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:34484) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD739-0003PL-Hm for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:42 -0500 Received: by mail-wr1-x42f.google.com with SMTP id n4so8911247wrx.1 for ; Fri, 19 Feb 2021 06:46:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Tnnq4eGrbcepmyuwUcHSjw4J1weXAX4V87WXkLtiaMI=; b=iS/6Mi5eEcWQVs5lLqw9gYqEXsdJQ6cL/dAlzbX2avR1NYnVp8EB8rh4SZvQllT76E tsKwIf/+IwPDA/Z7qHgDBs63TZgAG7+bZ+QUZIHgVtcwWm4pYJcJt0aBbP28wI4zA7ud Mi0JQu+tWmJCpr4KCAPT8+8EZu4X1aVoMtaecGS5QbBPtoDw+8FYAG9VFdpPEp/fHeie ef+6VCBFrEb6PePQIpyqkKxzOH4nv+TJ6rEj0xtzwtc9XpJL/jYq6qvuXMAzJvHNqMHj L35zX+rsGof1IIxvEa6t7GJNx81RiXyrBfyYfQBXKBfedCKCIfN+BCSnm9ojWOLFeYpn b2DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Tnnq4eGrbcepmyuwUcHSjw4J1weXAX4V87WXkLtiaMI=; b=q0xFtpFcshrzyL9d7OktXOmS/A8gQg1kX2QKM2fwsJVlBkg/sPaDPIbG76/Vg7zC7d I586ZKhSa4gUdKNv+KUam0mXDpWNDbMywTEQXvXANar1q9uxQU2C1UWAJ4qzmk6FUOEH hJivoAhXGSDhk+ewiNOQeskPPe3YYPYqL70Lox9QuZhuZTk0Ygmazwpa8uZpJrwDlm9d swgU4smupIj/Vcnc9KV1KT5KQTyr1XQLDbLmte9mUIuxWcyXnR9jfI94w+uIr+ArBidq 8rlgVe6lC3L+y9ZecO7y1g9nbqUDEn4WZExErL9GrVS4/fxXhPrMzJ4LxJzFa/pA618M 93dA== X-Gm-Message-State: AOAM532MKTOTP45YWIdZebTuOUXIktzLCySUBY/gx3XN6/SGFpjb6xhw jSFuj2lw47lUSYwSI1GKkd5L/g== X-Google-Smtp-Source: ABdhPJywvV2xKr6Ac+ZMjFb3+TFnh8Q4DgZ8TxfcdrASoWH1uerJO0ajhGfIZm2EVOAAzovGlt6w+w== X-Received: by 2002:adf:9546:: with SMTP id 64mr9776580wrs.247.1613745987018; Fri, 19 Feb 2021 06:46:27 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 09/44] hw/arm/armsse.c: Use correct SYS_CONFIG0 register value for SSE-300 Date: Fri, 19 Feb 2021 14:45:42 +0000 Message-Id: <20210219144617.4782-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In the SSE-300, the format of the SYS_CONFIG0 register has changed again; pass through the correct value to the SYSINFO register block device. We drop the old SysConfigFormat enum, which was implemented in the hope that different flavours of SSE would share the same format; since they all seem to be different and we now have an sse_version enum to key off, just use that. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/armsse.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 67fa4ffe34a..113a783a46a 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -24,12 +24,6 @@ #include "hw/irq.h" #include "hw/qdev-clock.h" =20 -/* Format of the System Information block SYS_CONFIG register */ -typedef enum SysConfigFormat { - IoTKitFormat, - SSE200Format, -} SysConfigFormat; - struct ARMSSEInfo { const char *name; uint32_t sse_version; @@ -37,7 +31,6 @@ struct ARMSSEInfo { int num_cpus; uint32_t sys_version; uint32_t cpuwait_rst; - SysConfigFormat sys_config_format; bool has_mhus; bool has_ppus; bool has_cachectrl; @@ -78,7 +71,6 @@ static const ARMSSEInfo armsse_variants[] =3D { .num_cpus =3D 1, .sys_version =3D 0x41743, .cpuwait_rst =3D 0, - .sys_config_format =3D IoTKitFormat, .has_mhus =3D false, .has_ppus =3D false, .has_cachectrl =3D false, @@ -93,7 +85,6 @@ static const ARMSSEInfo armsse_variants[] =3D { .num_cpus =3D 2, .sys_version =3D 0x22041743, .cpuwait_rst =3D 2, - .sys_config_format =3D SSE200Format, .has_mhus =3D true, .has_ppus =3D true, .has_cachectrl =3D true, @@ -108,13 +99,13 @@ static uint32_t armsse_sys_config_value(ARMSSE *s, con= st ARMSSEInfo *info) /* Return the SYS_CONFIG value for this SSE */ uint32_t sys_config; =20 - switch (info->sys_config_format) { - case IoTKitFormat: + switch (info->sse_version) { + case ARMSSE_IOTKIT: sys_config =3D 0; sys_config =3D deposit32(sys_config, 0, 4, info->sram_banks); sys_config =3D deposit32(sys_config, 4, 4, s->sram_addr_width - 12= ); break; - case SSE200Format: + case ARMSSE_SSE200: sys_config =3D 0; sys_config =3D deposit32(sys_config, 0, 4, info->sram_banks); sys_config =3D deposit32(sys_config, 4, 5, s->sram_addr_width); @@ -125,6 +116,12 @@ static uint32_t armsse_sys_config_value(ARMSSE *s, con= st ARMSSEInfo *info) sys_config =3D deposit32(sys_config, 28, 4, 2); } break; + case ARMSSE_SSE300: + sys_config =3D 0; + sys_config =3D deposit32(sys_config, 0, 4, info->sram_banks); + sys_config =3D deposit32(sys_config, 4, 5, s->sram_addr_width); + sys_config =3D deposit32(sys_config, 16, 3, 3); /* CPU0 =3D Cortex= -M55 */ + break; default: g_assert_not_reached(); } --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613746403643272.2337825104479; Fri, 19 Feb 2021 06:53:23 -0800 (PST) Received: from localhost ([::1]:43778 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD79m-0000CY-Fl for importer@patchew.org; Fri, 19 Feb 2021 09:53:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33672) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73N-0002CH-Pt for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:45 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:37288) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD739-0003Q2-II for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:45 -0500 Received: by mail-wm1-x335.google.com with SMTP id m1so7889096wml.2 for ; Fri, 19 Feb 2021 06:46:28 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/5T7tFYSez4oSWDc06Gf/0iIHyc2I1a1KAWLdAR9tmA=; b=NKuaBH3LSxj8UnBBBcNramKVwh7jFHoZPK7TrNG+lRXg4G1LzHpe9tLhGhKPd3j4JV /9u2XcY6lNy8xlqZSXI5dY5RmJplHP+hq/TKoQ2gaUi99zNbkn1f8gEj/Me8V1MiF6fS DkANO9OiM5ReB0OKSlm7w1zuGYZOIfr7KosczPCwGd7huiTVy7msyP3fSkvp1RnrOIQd v2WwDOaU4ZtbstwVIaux7wvAENpPxs8XxYFhYqQkVX8kDyZfG88APFPpzvFgC4KNWTIz +RzLeLvXgQJcktL/r0qYqmwdD0DICpCpTIgAIYUZCQMGahmxX5YBzvbQqwpIGFAmjdUz LQzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/5T7tFYSez4oSWDc06Gf/0iIHyc2I1a1KAWLdAR9tmA=; b=bVYuHBF/GAaZTc029gLYYXCEpTd5n++T8kMraKIRHNf/Xv+9QclkAg1mqfOg6L/O0g 6ERMd5ZYK5pOy59QlkHLxf9JAhkT0F0kJKwygQZ5d8l6WwTz/gBU5aH7gt3IbPhJbFep JxwN4wDKBPB32THiANIRIcf2/veAyv7iPlt6ibCR0W90/i43KaDLrb86q9TCGk+Mi+yK YK5TvmDgUPh3mthKKj4teuMi/i7juPXtRCQO9gS2WIOh7fulpaU2Gl/7qd9TJJgDCF+8 gbelJf0wn9VH9C+CD5bMCX5Rv7FZuPTz0ZEskicc1H14Jwv5PnuP87Wr7VwvRlPS9Sxw hrWg== X-Gm-Message-State: AOAM531Be/3552XAzrqj81F/HD5PKW8lRtCx9xU1SDDKmoEptEFLtBJQ HKE2/ebKi6x0QEXs4402ZB+w8S0YJ7V+kw== X-Google-Smtp-Source: ABdhPJx6mtrG71H5DWXdM74O+Idqbc5AaiznyMCK0tiQGkhVSBGmYtmD+L9GgTy72gtOfG/17M6Hgw== X-Received: by 2002:a1c:b607:: with SMTP id g7mr8523795wmf.67.1613745987734; Fri, 19 Feb 2021 06:46:27 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 10/44] hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDR Date: Fri, 19 Feb 2021 14:45:43 +0000 Message-Id: <20210219144617.4782-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For SSE-300, the SYSINFO register block has two new registers: * SYS_CONFIG1 indicates the config for a potential CPU2 and CPU3; since the SSE-300 can only be configured with a single CPU it is always zero * IIDR is the subsystem implementation identity register; its value is set by the SoC integrator, so we plumb this in from the armsse.c code as we do with SYS_VERSION and SYS_CONFIG Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/iotkit-sysinfo.h | 1 + hw/arm/armsse.c | 5 +++++ hw/misc/iotkit-sysinfo.c | 22 ++++++++++++++++++++++ 3 files changed, 28 insertions(+) diff --git a/include/hw/misc/iotkit-sysinfo.h b/include/hw/misc/iotkit-sysi= nfo.h index 91bd14bdbff..91c23f90d23 100644 --- a/include/hw/misc/iotkit-sysinfo.h +++ b/include/hw/misc/iotkit-sysinfo.h @@ -39,6 +39,7 @@ struct IoTKitSysInfo { uint32_t sys_version; uint32_t sys_config; uint32_t sse_version; + uint32_t iidr; }; =20 #endif diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 113a783a46a..326e161c8d4 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -30,6 +30,7 @@ struct ARMSSEInfo { int sram_banks; int num_cpus; uint32_t sys_version; + uint32_t iidr; uint32_t cpuwait_rst; bool has_mhus; bool has_ppus; @@ -70,6 +71,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .sram_banks =3D 1, .num_cpus =3D 1, .sys_version =3D 0x41743, + .iidr =3D 0, .cpuwait_rst =3D 0, .has_mhus =3D false, .has_ppus =3D false, @@ -84,6 +86,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .sram_banks =3D 4, .num_cpus =3D 2, .sys_version =3D 0x22041743, + .iidr =3D 0, .cpuwait_rst =3D 2, .has_mhus =3D true, .has_ppus =3D true, @@ -950,6 +953,8 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) } object_property_set_int(OBJECT(&s->sysinfo), "sse-version", info->sse_version, &error_abort); + object_property_set_int(OBJECT(&s->sysinfo), "IIDR", + info->iidr, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysinfo), errp)) { return; } diff --git a/hw/misc/iotkit-sysinfo.c b/hw/misc/iotkit-sysinfo.c index 4bd3fd4c8f3..aaa9305b2ea 100644 --- a/hw/misc/iotkit-sysinfo.c +++ b/hw/misc/iotkit-sysinfo.c @@ -30,6 +30,8 @@ =20 REG32(SYS_VERSION, 0x0) REG32(SYS_CONFIG, 0x4) +REG32(SYS_CONFIG1, 0x8) +REG32(IIDR, 0xfc8) REG32(PID4, 0xfd0) REG32(PID5, 0xfd4) REG32(PID6, 0xfd8) @@ -70,6 +72,24 @@ static uint64_t iotkit_sysinfo_read(void *opaque, hwaddr= offset, case A_SYS_CONFIG: r =3D s->sys_config; break; + case A_SYS_CONFIG1: + switch (s->sse_version) { + case ARMSSE_SSE300: + return 0; + break; + default: + goto bad_read; + } + break; + case A_IIDR: + switch (s->sse_version) { + case ARMSSE_SSE300: + return s->iidr; + break; + default: + goto bad_read; + } + break; case A_PID4 ... A_CID3: switch (s->sse_version) { case ARMSSE_SSE300: @@ -81,6 +101,7 @@ static uint64_t iotkit_sysinfo_read(void *opaque, hwaddr= offset, } break; default: + bad_read: qemu_log_mask(LOG_GUEST_ERROR, "IoTKit SysInfo read: bad offset %x\n", (int)offset); r =3D 0; @@ -114,6 +135,7 @@ static Property iotkit_sysinfo_props[] =3D { DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysInfo, sys_version, 0), DEFINE_PROP_UINT32("SYS_CONFIG", IoTKitSysInfo, sys_config, 0), DEFINE_PROP_UINT32("sse-version", IoTKitSysInfo, sse_version, 0), + DEFINE_PROP_UINT32("IIDR", IoTKitSysInfo, iidr, 0), DEFINE_PROP_END_OF_LIST() }; =20 --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613746463; cv=none; d=zohomail.com; s=zohoarc; b=GMvRc5B6/t4Hei6F67ByJ/VamqdUqoJVJtZARjEbOn9sgN89DkGmNOYj4hCnCrpqF53/X96t7jY/0F7ZAVpM6HcWk4LjeXaI80Ax+iVSxSpI2YNFyY3HiHKb6vvsz2+SPzBAVeuTyLPqQFXkuJuG22HT32W+8CM5UouSaxct1DY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613746463; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vcXyE9Uc4p1UCNBllpHeVJnIxgfcVRjat/zW6vUCjTY=; b=l3Jg1SfU+8/bd/QNPIgMkzKNW2U3Rp+p+kz6+vJKBy6wib7M215HqOtS0el2tHPaTpxp0qo9ytcn0ZZ49cKrG8hrIA8NCKKEf2Gd+H5MVDuM7LtAgEFuIa++cgEOZCiSwYPWq8FGkYdM/YSVdKeZHogDv3ZQ2VhomzWq/sMpMlQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613746463099202.15880402611242; Fri, 19 Feb 2021 06:54:23 -0800 (PST) Received: from localhost ([::1]:47620 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7Aj-0001mB-TZ for importer@patchew.org; Fri, 19 Feb 2021 09:54:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33624) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73L-0002AR-8g for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:45 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:37279) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD739-0003Qs-BS for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:43 -0500 Received: by mail-wm1-x32b.google.com with SMTP id m1so7889194wml.2 for ; Fri, 19 Feb 2021 06:46:29 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vcXyE9Uc4p1UCNBllpHeVJnIxgfcVRjat/zW6vUCjTY=; b=aURy12iVQGAsidtcu4tMnIlUJ5KrE4wNU5tOkbfDl9CRJD2EuOvPbqdsrjhcumUDro SWCiBYXKKgsjcF+yv8CmA901TmAJ1Hz9hK9h9KOEcMwySJT6FIhbETr0tIyb0zsNwGHw DJvfxhk7WRjhmZAh9rWlHbHTYg9ub8WYSBx48f5bRb0iw7llXL9RqCCNROv7ETaYAGF/ 8Nh33qlki7ctZBwafXcfO09Mlt/r9A1Dp1E/f5R8Ei8Ix9697KN35s9uVBBoKyyupGOX nCWgcnv7mEXSZGaCt1yNKhzooob4A5ilpu7KUnPxx2P3oIysnFfLbNcmw+gX/gDniS3M 1kPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vcXyE9Uc4p1UCNBllpHeVJnIxgfcVRjat/zW6vUCjTY=; b=HqTU/n+xwKUfr6AU6hRKui3b7XcqOxJ8YlgTbrD5w2l6pA1NbLPduQsLYATSOe0L0S 3wADapkpCT2f+qPEOc6fkxtD2AspiCwGFcnLg4cmXmfKFwzcI3/X68diHTw6CFE0KXAe FMQNUP6RlOEom0UotK8o8UVrKwYLY0tOlQcHisyOZ6OyHC6oSm3DCJS0KmmmDuPOuV5g MxZbL4Ul1+f2PTwutbGUttMQcgLT1dWh9soNO7Xo8FAmAAC9JL1t6AYcZ4TJu1cp995Y dl60gQ+hCP7zH537mDfAbCmydOjj+VhK4XcFkCIkBwevISoDZh8MkXWUrrVtcnFHAgBl bDtw== X-Gm-Message-State: AOAM532KUseumsnKGnATq/Oi93or2r1Bz9RhHQqeX6VLIJh9PIn/a+cA j9YtR3HMtcImSl3x2/nsSqn1OA== X-Google-Smtp-Source: ABdhPJyB36YnPHPYiRyRgPwiSLEwuDtKmM+auHXgkMTXsE+aacXIyXs7aTYaCHup4SMTGlFAsh+lWA== X-Received: by 2002:a7b:ce95:: with SMTP id q21mr8496697wmj.178.1613745988688; Fri, 19 Feb 2021 06:46:28 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 11/44] hw/timer/sse-counter: Model the SSE Subsystem System Counter Date: Fri, 19 Feb 2021 14:45:44 +0000 Message-Id: <20210219144617.4782-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The SSE-300 includes a counter module; implement a model of it. This counter is documented in the SSE-123 Example Subsystem Technical Reference Manual: https://developer.arm.com/documentation/101370/latest/ Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/timer/sse-counter.h | 105 ++++++++ hw/timer/sse-counter.c | 474 +++++++++++++++++++++++++++++++++ MAINTAINERS | 2 + hw/arm/Kconfig | 1 + hw/timer/Kconfig | 3 + hw/timer/meson.build | 1 + hw/timer/trace-events | 7 + 7 files changed, 593 insertions(+) create mode 100644 include/hw/timer/sse-counter.h create mode 100644 hw/timer/sse-counter.c diff --git a/include/hw/timer/sse-counter.h b/include/hw/timer/sse-counter.h new file mode 100644 index 00000000000..b433e58d370 --- /dev/null +++ b/include/hw/timer/sse-counter.h @@ -0,0 +1,105 @@ +/* + * Arm SSE Subsystem System Counter + * + * Copyright (c) 2020 Linaro Limited + * Written by Peter Maydell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +/* + * This is a model of the "System counter" which is documented in + * the Arm SSE-123 Example Subsystem Technical Reference Manual: + * https://developer.arm.com/documentation/101370/latest/ + * + * QEMU interface: + * + Clock input "CLK": clock + * + sysbus MMIO region 0: the control register frame + * + sysbus MMIO region 1: the status register frame + * + * Consumers of the system counter's timestamp, such as the SSE + * System Timer device, can also use the APIs sse_counter_for_timestamp(), + * sse_counter_tick_to_time() and sse_counter_register_consumer() to + * interact with an instance of the System Counter. Generally the + * consumer device should have a QOM link property which the board + * code can set to the appropriate instance of the system counter. + */ + +#ifndef SSE_COUNTER_H +#define SSE_COUNTER_H + +#include "hw/sysbus.h" +#include "qom/object.h" +#include "qemu/notify.h" + +#define TYPE_SSE_COUNTER "sse-counter" +OBJECT_DECLARE_SIMPLE_TYPE(SSECounter, SSE_COUNTER) + +struct SSECounter { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion control_mr; + MemoryRegion status_mr; + Clock *clk; + NotifierList notifier_list; + + uint32_t cntcr; + uint32_t cntscr0; + + /* + * These are used for handling clock frequency changes: they are a + * tuple of (QEMU_CLOCK_VIRTUAL timestamp, CNTCV at that time), + * taken when the clock frequency changes. sse_cntcv() needs them + * to calculate the current CNTCV. + */ + uint64_t ns_then; + uint64_t ticks_then; +}; + +/* + * These functions are the interface by which a consumer of + * the system timestamp (such as the SSE system timer device) + * can communicate with the SSECounter. + */ + +/** + * sse_counter_for_timestamp: + * @counter: SSECounter + * @ns: timestamp of QEMU_CLOCK_VIRTUAL in nanoseconds + * + * Returns the value of the timestamp counter at the specified + * point in time (assuming that no changes to scale factor, enable, etc + * happen in the meantime). + */ +uint64_t sse_counter_for_timestamp(SSECounter *counter, uint64_t ns); + +/** + * sse_counter_tick_to_time: + * @counter: SSECounter + * @tick: tick value + * + * Returns the time (a QEMU_CLOCK_VIRTUAL timestamp in nanoseconds) + * when the timestamp counter will reach the specified tick count. + * If the counter is not currently running, returns UINT64_MAX. + */ +uint64_t sse_counter_tick_to_time(SSECounter *counter, uint64_t tick); + +/** + * sse_counter_register_consumer: + * @counter: SSECounter + * @notifier: Notifier which is notified on counter changes + * + * Registers @notifier with the SSECounter. When the counter's + * configuration changes in a way that might invalidate information + * previously returned via sse_counter_for_timestamp() or + * sse_counter_tick_to_time(), the notifier will be called. + * Devices which consume the timestamp counter can use this as + * a cue to recalculate timer events. + */ +void sse_counter_register_consumer(SSECounter *counter, Notifier *notifier= ); + +#endif diff --git a/hw/timer/sse-counter.c b/hw/timer/sse-counter.c new file mode 100644 index 00000000000..0384051f151 --- /dev/null +++ b/hw/timer/sse-counter.c @@ -0,0 +1,474 @@ +/* + * Arm SSE Subsystem System Counter + * + * Copyright (c) 2020 Linaro Limited + * Written by Peter Maydell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +/* + * This is a model of the "System counter" which is documented in + * the Arm SSE-123 Example Subsystem Technical Reference Manual: + * https://developer.arm.com/documentation/101370/latest/ + * + * The system counter is a non-stop 64-bit up-counter. It provides + * this count value to other devices like the SSE system timer, + * which are driven by this system timestamp rather than directly + * from a clock. Internally to the counter the count is actually + * 88-bit precision (64.24 fixed point), with a programmable scale factor. + * + * The hardware has the optional feature that it supports dynamic + * clock switching, where two clock inputs are connected, and which + * one is used is selected via a CLKSEL input signal. Since the + * users of this device in QEMU don't use this feature, we only model + * the HWCLKSW=3D0 configuration. + */ +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/timer.h" +#include "qapi/error.h" +#include "trace.h" +#include "hw/timer/sse-counter.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/registerfields.h" +#include "hw/clock.h" +#include "hw/qdev-clock.h" +#include "migration/vmstate.h" + +/* Registers in the control frame */ +REG32(CNTCR, 0x0) + FIELD(CNTCR, EN, 0, 1) + FIELD(CNTCR, HDBG, 1, 1) + FIELD(CNTCR, SCEN, 2, 1) + FIELD(CNTCR, INTRMASK, 3, 1) + FIELD(CNTCR, PSLVERRDIS, 4, 1) + FIELD(CNTCR, INTRCLR, 5, 1) +/* + * Although CNTCR defines interrupt-related bits, the counter doesn't + * appear to actually have an interrupt output. So INTRCLR is + * effectively a RAZ/WI bit, as are the reserved bits [31:6]. + */ +#define CNTCR_VALID_MASK (R_CNTCR_EN_MASK | R_CNTCR_HDBG_MASK | \ + R_CNTCR_SCEN_MASK | R_CNTCR_INTRMASK_MASK | \ + R_CNTCR_PSLVERRDIS_MASK) +REG32(CNTSR, 0x4) +REG32(CNTCV_LO, 0x8) +REG32(CNTCV_HI, 0xc) +REG32(CNTSCR, 0x10) /* Aliased with CNTSCR0 */ +REG32(CNTID, 0x1c) + FIELD(CNTID, CNTSC, 0, 4) + FIELD(CNTID, CNTCS, 16, 1) + FIELD(CNTID, CNTSELCLK, 17, 2) + FIELD(CNTID, CNTSCR_OVR, 19, 1) +REG32(CNTSCR0, 0xd0) +REG32(CNTSCR1, 0xd4) + +/* Registers in the status frame */ +REG32(STATUS_CNTCV_LO, 0x0) +REG32(STATUS_CNTCV_HI, 0x4) + +/* Standard ID registers, present in both frames */ +REG32(PID4, 0xFD0) +REG32(PID5, 0xFD4) +REG32(PID6, 0xFD8) +REG32(PID7, 0xFDC) +REG32(PID0, 0xFE0) +REG32(PID1, 0xFE4) +REG32(PID2, 0xFE8) +REG32(PID3, 0xFEC) +REG32(CID0, 0xFF0) +REG32(CID1, 0xFF4) +REG32(CID2, 0xFF8) +REG32(CID3, 0xFFC) + +/* PID/CID values */ +static const int control_id[] =3D { + 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ + 0xba, 0xb0, 0x0b, 0x00, /* PID0..PID3 */ + 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ +}; + +static const int status_id[] =3D { + 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ + 0xbb, 0xb0, 0x0b, 0x00, /* PID0..PID3 */ + 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ +}; + +static void sse_counter_notify_users(SSECounter *s) +{ + /* + * Notify users of the count timestamp that they may + * need to recalculate. + */ + notifier_list_notify(&s->notifier_list, NULL); +} + +static bool sse_counter_enabled(SSECounter *s) +{ + return (s->cntcr & R_CNTCR_EN_MASK) !=3D 0; +} + +uint64_t sse_counter_tick_to_time(SSECounter *s, uint64_t tick) +{ + if (!sse_counter_enabled(s)) { + return UINT64_MAX; + } + + tick -=3D s->ticks_then; + + if (s->cntcr & R_CNTCR_SCEN_MASK) { + /* Adjust the tick count to account for the scale factor */ + tick =3D muldiv64(tick, 0x01000000, s->cntscr0); + } + + return s->ns_then + clock_ticks_to_ns(s->clk, tick); +} + +void sse_counter_register_consumer(SSECounter *s, Notifier *notifier) +{ + /* + * For the moment we assume that both we and the devices + * which consume us last for the life of the simulation, + * and so there is no mechanism for removing a notifier. + */ + notifier_list_add(&s->notifier_list, notifier); +} + +uint64_t sse_counter_for_timestamp(SSECounter *s, uint64_t now) +{ + /* Return the CNTCV value for a particular timestamp (clock ns value).= */ + uint64_t ticks; + + if (!sse_counter_enabled(s)) { + /* Counter is disabled and does not increment */ + return s->ticks_then; + } + + ticks =3D clock_ns_to_ticks(s->clk, now - s->ns_then); + if (s->cntcr & R_CNTCR_SCEN_MASK) { + /* + * Scaling is enabled. The CNTSCR value is the amount added to + * the underlying 88-bit counter for every tick of the + * underlying clock; CNTCV is the top 64 bits of that full + * 88-bit value. Multiplying the tick count by CNTSCR tells us + * how much the full 88-bit counter has moved on; we then + * divide that by 0x01000000 to find out how much the 64-bit + * visible portion has advanced. muldiv64() gives us the + * necessary at-least-88-bit precision for the intermediate + * result. + */ + ticks =3D muldiv64(ticks, s->cntscr0, 0x01000000); + } + return s->ticks_then + ticks; +} + +static uint64_t sse_cntcv(SSECounter *s) +{ + /* Return the CNTCV value for the current time */ + return sse_counter_for_timestamp(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTU= AL)); +} + +static void sse_write_cntcv(SSECounter *s, uint32_t value, unsigned startb= it) +{ + /* + * Write one 32-bit half of the counter value; startbit is the + * bit position of this half in the 64-bit word, either 0 or 32. + */ + uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint64_t cntcv =3D sse_counter_for_timestamp(s, now); + + cntcv =3D deposit64(cntcv, startbit, 32, value); + s->ticks_then =3D cntcv; + s->ns_then =3D now; + sse_counter_notify_users(s); +} + +static uint64_t sse_counter_control_read(void *opaque, hwaddr offset, + unsigned size) +{ + SSECounter *s =3D SSE_COUNTER(opaque); + uint64_t r; + + switch (offset) { + case A_CNTCR: + r =3D s->cntcr; + break; + case A_CNTSR: + /* + * The only bit here is DBGH, indicating that the counter has been + * halted via the Halt-on-Debug signal. We don't implement halting + * debug, so the whole register always reads as zero. + */ + r =3D 0; + break; + case A_CNTCV_LO: + r =3D extract64(sse_cntcv(s), 0, 32); + break; + case A_CNTCV_HI: + r =3D extract64(sse_cntcv(s), 32, 32); + break; + case A_CNTID: + /* + * For our implementation: + * - CNTSCR can only be written when CNTCR.EN =3D=3D 0 + * - HWCLKSW=3D0, so selected clock is always CLK0 + * - counter scaling is implemented + */ + r =3D (1 << R_CNTID_CNTSELCLK_SHIFT) | (1 << R_CNTID_CNTSC_SHIFT); + break; + case A_CNTSCR: + case A_CNTSCR0: + r =3D s->cntscr0; + break; + case A_CNTSCR1: + /* If HWCLKSW =3D=3D 0, CNTSCR1 is RAZ/WI */ + r =3D 0; + break; + case A_PID4 ... A_CID3: + r =3D control_id[(offset - A_PID4) / 4]; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "SSE System Counter control frame read: bad offset 0= x%x", + (unsigned)offset); + r =3D 0; + break; + } + + trace_sse_counter_control_read(offset, r, size); + return r; +} + +static void sse_counter_control_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + SSECounter *s =3D SSE_COUNTER(opaque); + + trace_sse_counter_control_write(offset, value, size); + + switch (offset) { + case A_CNTCR: + /* + * Although CNTCR defines interrupt-related bits, the counter does= n't + * appear to actually have an interrupt output. So INTRCLR is + * effectively a RAZ/WI bit, as are the reserved bits [31:6]. + * The documentation does not explicitly say so, but we assume + * that changing the scale factor while the counter is enabled + * by toggling CNTCR.SCEN has the same behaviour (making the count= er + * value UNKNOWN) as changing it by writing to CNTSCR, and so we + * don't need to try to recalculate for that case. + */ + value &=3D CNTCR_VALID_MASK; + if ((value ^ s->cntcr) & R_CNTCR_EN_MASK) { + /* + * Whether the counter is being enabled or disabled, the + * required action is the same: sync the (ns_then, ticks_then) + * tuple. + */ + uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + s->ticks_then =3D sse_counter_for_timestamp(s, now); + s->ns_then =3D now; + sse_counter_notify_users(s); + } + s->cntcr =3D value; + break; + case A_CNTCV_LO: + sse_write_cntcv(s, value, 0); + break; + case A_CNTCV_HI: + sse_write_cntcv(s, value, 32); + break; + case A_CNTSCR: + case A_CNTSCR0: + /* + * If the scale registers are changed when the counter is enabled, + * the count value becomes UNKNOWN. So we don't try to recalculate + * anything here but only do it on a write to CNTCR.EN. + */ + s->cntscr0 =3D value; + break; + case A_CNTSCR1: + /* If HWCLKSW =3D=3D 0, CNTSCR1 is RAZ/WI */ + break; + case A_CNTSR: + case A_CNTID: + case A_PID4 ... A_CID3: + qemu_log_mask(LOG_GUEST_ERROR, + "SSE System Counter control frame: write to RO offse= t 0x%x\n", + (unsigned)offset); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "SSE System Counter control frame: write to bad offs= et 0x%x\n", + (unsigned)offset); + break; + } +} + +static uint64_t sse_counter_status_read(void *opaque, hwaddr offset, + unsigned size) +{ + SSECounter *s =3D SSE_COUNTER(opaque); + uint64_t r; + + switch (offset) { + case A_STATUS_CNTCV_LO: + r =3D extract64(sse_cntcv(s), 0, 32); + break; + case A_STATUS_CNTCV_HI: + r =3D extract64(sse_cntcv(s), 32, 32); + break; + case A_PID4 ... A_CID3: + r =3D status_id[(offset - A_PID4) / 4]; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "SSE System Counter status frame read: bad offset 0x= %x", + (unsigned)offset); + r =3D 0; + break; + } + + trace_sse_counter_status_read(offset, r, size); + return r; +} + +static void sse_counter_status_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + trace_sse_counter_status_write(offset, value, size); + + switch (offset) { + case A_STATUS_CNTCV_LO: + case A_STATUS_CNTCV_HI: + case A_PID4 ... A_CID3: + qemu_log_mask(LOG_GUEST_ERROR, + "SSE System Counter status frame: write to RO offset= 0x%x\n", + (unsigned)offset); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "SSE System Counter status frame: write to bad offse= t 0x%x\n", + (unsigned)offset); + break; + } +} + +static const MemoryRegionOps sse_counter_control_ops =3D { + .read =3D sse_counter_control_read, + .write =3D sse_counter_control_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static const MemoryRegionOps sse_counter_status_ops =3D { + .read =3D sse_counter_status_read, + .write =3D sse_counter_status_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static void sse_counter_reset(DeviceState *dev) +{ + SSECounter *s =3D SSE_COUNTER(dev); + + trace_sse_counter_reset(); + + s->cntcr =3D 0; + s->cntscr0 =3D 0x01000000; + s->ns_then =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + s->ticks_then =3D 0; +} + +static void sse_clk_callback(void *opaque, ClockEvent event) +{ + SSECounter *s =3D SSE_COUNTER(opaque); + uint64_t now; + + switch (event) { + case ClockPreUpdate: + /* + * Before the clock period updates, set (ticks_then, ns_then) + * to the current time and tick count (as calculated with + * the old clock period). + */ + if (sse_counter_enabled(s)) { + now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + s->ticks_then =3D sse_counter_for_timestamp(s, now); + s->ns_then =3D now; + } + break; + case ClockUpdate: + sse_counter_notify_users(s); + break; + default: + break; + } +} + +static void sse_counter_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + SSECounter *s =3D SSE_COUNTER(obj); + + notifier_list_init(&s->notifier_list); + + s->clk =3D qdev_init_clock_in(DEVICE(obj), "CLK", sse_clk_callback, s, + ClockPreUpdate | ClockUpdate); + memory_region_init_io(&s->control_mr, obj, &sse_counter_control_ops, + s, "sse-counter-control", 0x1000); + memory_region_init_io(&s->status_mr, obj, &sse_counter_status_ops, + s, "sse-counter-status", 0x1000); + sysbus_init_mmio(sbd, &s->control_mr); + sysbus_init_mmio(sbd, &s->status_mr); +} + +static void sse_counter_realize(DeviceState *dev, Error **errp) +{ + SSECounter *s =3D SSE_COUNTER(dev); + + if (!clock_has_source(s->clk)) { + error_setg(errp, "SSE system counter: CLK must be connected"); + return; + } +} + +static const VMStateDescription sse_counter_vmstate =3D { + .name =3D "sse-counter", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_CLOCK(clk, SSECounter), + VMSTATE_END_OF_LIST() + } +}; + +static void sse_counter_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D sse_counter_realize; + dc->vmsd =3D &sse_counter_vmstate; + dc->reset =3D sse_counter_reset; +} + +static const TypeInfo sse_counter_info =3D { + .name =3D TYPE_SSE_COUNTER, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(SSECounter), + .instance_init =3D sse_counter_init, + .class_init =3D sse_counter_class_init, +}; + +static void sse_counter_register_types(void) +{ + type_register_static(&sse_counter_info); +} + +type_init(sse_counter_register_types); diff --git a/MAINTAINERS b/MAINTAINERS index de5fe1c65f5..1c9b2f446ef 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -742,6 +742,8 @@ F: hw/misc/armsse-cpuid.c F: include/hw/misc/armsse-cpuid.h F: hw/misc/armsse-mhu.c F: include/hw/misc/armsse-mhu.h +F: hw/timer/sse-counter.c +F: include/hw/timer/sse-counter.h F: docs/system/arm/mps2.rst =20 Musca diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index be017b997ab..3081efce20b 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -519,6 +519,7 @@ config ARMSSE select TZ_MSC select TZ_PPC select UNIMP + select SSE_COUNTER =20 config ARMSSE_CPUID bool diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig index 8749edfb6a5..e103c8872ab 100644 --- a/hw/timer/Kconfig +++ b/hw/timer/Kconfig @@ -42,5 +42,8 @@ config RENESAS_TMR config RENESAS_CMT bool =20 +config SSE_COUNTER + bool + config AVR_TIMER16 bool diff --git a/hw/timer/meson.build b/hw/timer/meson.build index be343f68fed..79a3012349d 100644 --- a/hw/timer/meson.build +++ b/hw/timer/meson.build @@ -32,6 +32,7 @@ softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa= 2xx_timer.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_systmr.c')) softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_timer.c')) softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_timer.c')) +softmmu_ss.add(when: 'CONFIG_SSE_COUNTER', if_true: files('sse-counter.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_TIMER', if_true: files('stm32f2xx_t= imer.c')) softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_timer.c')) =20 diff --git a/hw/timer/trace-events b/hw/timer/trace-events index 7a4326d9566..bb9c1000878 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -93,3 +93,10 @@ avr_timer16_interrupt_count(uint8_t cnt) "count: %u" avr_timer16_interrupt_overflow(const char *reason) "overflow: %s" avr_timer16_next_alarm(uint64_t delay_ns) "next alarm: %" PRIu64 " ns from= now" avr_timer16_clksrc_update(uint64_t freq_hz, uint64_t period_ns, uint64_t d= elay_s) "timer frequency: %" PRIu64 " Hz, period: %" PRIu64 " ns (%" PRId64= " us)" + +# sse_counter.c +sse_counter_control_read(uint64_t offset, uint64_t data, unsigned size) "S= SE system counter control frame read: offset 0x%" PRIx64 " data 0x%" PRIx64= " size %u" +sse_counter_control_write(uint64_t offset, uint64_t data, unsigned size) "= SSE system counter control framen write: offset 0x%" PRIx64 " data 0x%" PRI= x64 " size %u" +sse_counter_status_read(uint64_t offset, uint64_t data, unsigned size) "SS= E system counter status frame read: offset 0x%" PRIx64 " data 0x%" PRIx64 "= size %u" +sse_counter_status_write(uint64_t offset, uint64_t data, unsigned size) "S= SE system counter status frame write: offset 0x%" PRIx64 " data 0x%" PRIx64= " size %u" +sse_counter_reset(void) "SSE system counter: reset" --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=e/AKBMpHceDwU1Co+FrJQpPI3HzQZjvhRAO2x8uFtWI=; b=Dk4kjBKM1NgZvK2jWzjNutik0BlkJzDHGsgo3xi+BVsQ5cEnPctzGa2Et1ocWNTR2k lT+lZy7BYZPQFsDC3l2ZvxpEthD7PFdKA01YDpWtrbgZUfDSAa2f7+KqZrx0ZJOG9DSX xY2WMArLBXcwLuPxGRSMkrgw/FHqfSnMfseXUB6X4A+p4aUm1ixP7UXIfNqRHxGbpr3c N3wwyjGv8REjuNZnS+x+qR78Uiy/ogRXRq7q8ExAttV9tP3pe3IAhoRixPENE1qoKNo+ EUiYnac4Gl/c8hEDGVCReBNpUjexdJyOEh8TGMkATJ0jRRefY/e37KRuaL+tyzLk9hF2 Yppg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e/AKBMpHceDwU1Co+FrJQpPI3HzQZjvhRAO2x8uFtWI=; b=cicf50j+EXkRa3ArfI3SoyaR+5bRjvAkzNFnGQX5gialj4GhP+V+6FHj/BfMPzpDjp x3YYNO7bJ1yGPyt1w8dzZQtO0ZDgRvjFp+aapuA0iA2tnCAzRCR6l7LE/kixzrWEkQAx eEH045sFr4cHM73PfMPdGptF+aUSsLt+g0tzPeItPMTax3OjzjngPSWUp4wkoqQP1vc1 dsPzwHOMXjU5IswW9XMdYV4v3XBmCcST0OD7uxKfr+FePOgogvzeQgQBp/Kfxihdn3PK pkE0wt/7FcUbMNOrA6wf/299XfT5JMWkOIUGrKopjMeTiF/wfx643scSF+2AKV2fkzyf S4vw== X-Gm-Message-State: AOAM531I4GQy7lAM5noNb61mshxPNpVbvFtz7JgRQXaHsFsF9zzn4H/s AsObbVNdb2sPd6I5Fvn9sP+cbiVDWgrgog== X-Google-Smtp-Source: ABdhPJz+0kdqVGvq2kU1+lJ6ZgZop61dc2jOejqdhMeQlGKzidflh7MA4M79KdJnDLpdexm5OCoj4A== X-Received: by 2002:a05:600c:430b:: with SMTP id p11mr8630105wme.29.1613745989692; Fri, 19 Feb 2021 06:46:29 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 12/44] hw/timer/sse-timer: Model the SSE Subsystem System Timer Date: Fri, 19 Feb 2021 14:45:45 +0000 Message-Id: <20210219144617.4782-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The SSE-300 includes some timers which are a different kind to those in the SSE-200. Model them. These timers are documented in the SSE-123 Example Subsystem Technical Reference Manual: https://developer.arm.com/documentation/101370/latest/ Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/timer/sse-timer.h | 53 ++++ hw/timer/sse-timer.c | 470 +++++++++++++++++++++++++++++++++++ MAINTAINERS | 2 + hw/arm/Kconfig | 1 + hw/timer/Kconfig | 3 + hw/timer/meson.build | 1 + hw/timer/trace-events | 5 + 7 files changed, 535 insertions(+) create mode 100644 include/hw/timer/sse-timer.h create mode 100644 hw/timer/sse-timer.c diff --git a/include/hw/timer/sse-timer.h b/include/hw/timer/sse-timer.h new file mode 100644 index 00000000000..b4ee8e7f6c4 --- /dev/null +++ b/include/hw/timer/sse-timer.h @@ -0,0 +1,53 @@ +/* + * Arm SSE Subsystem System Timer + * + * Copyright (c) 2020 Linaro Limited + * Written by Peter Maydell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +/* + * This is a model of the "System timer" which is documented in + * the Arm SSE-123 Example Subsystem Technical Reference Manual: + * https://developer.arm.com/documentation/101370/latest/ + * + * QEMU interface: + * + QOM property "counter": link property to be set to the + * TYPE_SSE_COUNTER timestamp counter device this timer runs off + * + sysbus MMIO region 0: the register bank + * + sysbus IRQ 0: timer interrupt + */ + +#ifndef SSE_TIMER_H +#define SSE_TIMER_H + +#include "hw/sysbus.h" +#include "qom/object.h" +#include "hw/timer/sse-counter.h" + +#define TYPE_SSE_TIMER "sse-timer" +OBJECT_DECLARE_SIMPLE_TYPE(SSETimer, SSE_TIMER) + +struct SSETimer { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; + qemu_irq irq; + SSECounter *counter; + QEMUTimer timer; + Notifier counter_notifier; + + uint32_t cntfrq; + uint32_t cntp_ctl; + uint64_t cntp_cval; + uint64_t cntp_aival; + uint32_t cntp_aival_ctl; + uint32_t cntp_aival_reload; +}; + +#endif diff --git a/hw/timer/sse-timer.c b/hw/timer/sse-timer.c new file mode 100644 index 00000000000..8dbe6ac651e --- /dev/null +++ b/hw/timer/sse-timer.c @@ -0,0 +1,470 @@ +/* + * Arm SSE Subsystem System Timer + * + * Copyright (c) 2020 Linaro Limited + * Written by Peter Maydell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +/* + * This is a model of the "System timer" which is documented in + * the Arm SSE-123 Example Subsystem Technical Reference Manual: + * https://developer.arm.com/documentation/101370/latest/ + * + * The timer is based around a simple 64-bit incrementing counter + * (readable from CNTPCT_HI/LO). The timer fires when + * Counter - CompareValue >=3D 0. + * The CompareValue is guest-writable, via CNTP_CVAL_HI/LO. + * CNTP_TVAL is an alternative view of the CompareValue defined by + * TimerValue =3D CompareValue[31:0] - Counter[31:0] + * which can be both read and written. + * This part is similar to the generic timer in an Arm A-class CPU. + * + * The timer also has a separate auto-increment timer. When this + * timer is enabled, then the AutoIncrValue is set to: + * AutoIncrValue =3D Reload + Counter + * and this timer fires when + * Counter - AutoIncrValue >=3D 0 + * at which point, an interrupt is generated and the new AutoIncrValue + * is calculated. + * When the auto-increment timer is enabled, interrupt generation + * via the compare/timervalue registers is disabled. + */ +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/timer.h" +#include "qapi/error.h" +#include "trace.h" +#include "hw/timer/sse-timer.h" +#include "hw/timer/sse-counter.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/registerfields.h" +#include "hw/clock.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" + +REG32(CNTPCT_LO, 0x0) +REG32(CNTPCT_HI, 0x4) +REG32(CNTFRQ, 0x10) +REG32(CNTP_CVAL_LO, 0x20) +REG32(CNTP_CVAL_HI, 0x24) +REG32(CNTP_TVAL, 0x28) +REG32(CNTP_CTL, 0x2c) + FIELD(CNTP_CTL, ENABLE, 0, 1) + FIELD(CNTP_CTL, IMASK, 1, 1) + FIELD(CNTP_CTL, ISTATUS, 2, 1) +REG32(CNTP_AIVAL_LO, 0x40) +REG32(CNTP_AIVAL_HI, 0x44) +REG32(CNTP_AIVAL_RELOAD, 0x48) +REG32(CNTP_AIVAL_CTL, 0x4c) + FIELD(CNTP_AIVAL_CTL, EN, 0, 1) + FIELD(CNTP_AIVAL_CTL, CLR, 1, 1) +REG32(CNTP_CFG, 0x50) + FIELD(CNTP_CFG, AIVAL, 0, 4) +#define R_CNTP_CFG_AIVAL_IMPLEMENTED 1 +REG32(PID4, 0xFD0) +REG32(PID5, 0xFD4) +REG32(PID6, 0xFD8) +REG32(PID7, 0xFDC) +REG32(PID0, 0xFE0) +REG32(PID1, 0xFE4) +REG32(PID2, 0xFE8) +REG32(PID3, 0xFEC) +REG32(CID0, 0xFF0) +REG32(CID1, 0xFF4) +REG32(CID2, 0xFF8) +REG32(CID3, 0xFFC) + +/* PID/CID values */ +static const int timer_id[] =3D { + 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ + 0xb7, 0xb0, 0x0b, 0x00, /* PID0..PID3 */ + 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ +}; + +static bool sse_is_autoinc(SSETimer *s) +{ + return (s->cntp_aival_ctl & R_CNTP_AIVAL_CTL_EN_MASK) !=3D 0; +} + +static bool sse_enabled(SSETimer *s) +{ + return (s->cntp_ctl & R_CNTP_CTL_ENABLE_MASK) !=3D 0; +} + +static uint64_t sse_cntpct(SSETimer *s) +{ + /* Return the CNTPCT value for the current time */ + return sse_counter_for_timestamp(s->counter, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)= ); +} + +static bool sse_timer_status(SSETimer *s) +{ + /* + * Return true if timer condition is met. This is used for both + * the CNTP_CTL.ISTATUS bit and for whether (unless masked) we + * assert our IRQ. + * The documentation is unclear about the behaviour of ISTATUS when + * in autoincrement mode; we assume that it follows CNTP_AIVAL_CTL.CLR + * (ie whether the autoincrement timer is asserting the interrupt). + */ + if (!sse_enabled(s)) { + return false; + } + + if (sse_is_autoinc(s)) { + return s->cntp_aival_ctl & R_CNTP_AIVAL_CTL_CLR_MASK; + } else { + return sse_cntpct(s) >=3D s->cntp_cval; + } +} + +static void sse_update_irq(SSETimer *s) +{ + bool irqstate =3D (!(s->cntp_ctl & R_CNTP_CTL_IMASK_MASK) && + sse_timer_status(s)); + + qemu_set_irq(s->irq, irqstate); +} + +static void sse_set_timer(SSETimer *s, uint64_t nexttick) +{ + /* Set the timer to expire at nexttick */ + uint64_t expiry =3D sse_counter_tick_to_time(s->counter, nexttick); + + if (expiry <=3D INT64_MAX) { + timer_mod_ns(&s->timer, expiry); + } else { + /* + * nexttick is so far in the future that it would overflow the + * signed 64-bit range of a QEMUTimer. Since timer_mod_ns() + * expiry times are absolute, not relative, we are never going + * to be able to set the timer to this value, so we must just + * assume that guest execution can never run so long that it + * reaches the theoretical point when the timer fires. + * This is also the code path for "counter is not running", + * which is signalled by expiry =3D=3D UINT64_MAX. + */ + timer_del(&s->timer); + } +} + +static void sse_recalc_timer(SSETimer *s) +{ + /* Recalculate the normal timer */ + uint64_t count, nexttick; + + if (sse_is_autoinc(s)) { + return; + } + + if (!sse_enabled(s)) { + timer_del(&s->timer); + return; + } + + count =3D sse_cntpct(s); + + if (count >=3D s->cntp_cval) { + /* + * Timer condition already met. In theory we have a transition when + * the count rolls back over to 0, but that is so far in the future + * that it is not representable as a timer_mod() expiry, so in + * fact sse_set_timer() will always just delete the timer. + */ + nexttick =3D UINT64_MAX; + } else { + /* Next transition is when count hits cval */ + nexttick =3D s->cntp_cval; + } + sse_set_timer(s, nexttick); + sse_update_irq(s); +} + +static void sse_autoinc(SSETimer *s) +{ + /* Auto-increment the AIVAL, and set the timer accordingly */ + s->cntp_aival =3D sse_cntpct(s) + s->cntp_aival_reload; + sse_set_timer(s, s->cntp_aival); +} + +static void sse_timer_cb(void *opaque) +{ + SSETimer *s =3D SSE_TIMER(opaque); + + if (sse_is_autoinc(s)) { + uint64_t count =3D sse_cntpct(s); + + if (count >=3D s->cntp_aival) { + /* Timer condition met, set CLR and do another autoinc */ + s->cntp_aival_ctl |=3D R_CNTP_AIVAL_CTL_CLR_MASK; + s->cntp_aival =3D count + s->cntp_aival_reload; + } + sse_set_timer(s, s->cntp_aival); + sse_update_irq(s); + } else { + sse_recalc_timer(s); + } +} + +static uint64_t sse_timer_read(void *opaque, hwaddr offset, unsigned size) +{ + SSETimer *s =3D SSE_TIMER(opaque); + uint64_t r; + + switch (offset) { + case A_CNTPCT_LO: + r =3D extract64(sse_cntpct(s), 0, 32); + break; + case A_CNTPCT_HI: + r =3D extract64(sse_cntpct(s), 32, 32); + break; + case A_CNTFRQ: + r =3D s->cntfrq; + break; + case A_CNTP_CVAL_LO: + r =3D extract64(s->cntp_cval, 0, 32); + break; + case A_CNTP_CVAL_HI: + r =3D extract64(s->cntp_cval, 32, 32); + break; + case A_CNTP_TVAL: + r =3D extract64(s->cntp_cval - sse_cntpct(s), 0, 32); + break; + case A_CNTP_CTL: + r =3D s->cntp_ctl; + if (sse_timer_status(s)) { + r |=3D R_CNTP_CTL_ISTATUS_MASK; + } + break; + case A_CNTP_AIVAL_LO: + r =3D extract64(s->cntp_aival, 0, 32); + break; + case A_CNTP_AIVAL_HI: + r =3D extract64(s->cntp_aival, 32, 32); + break; + case A_CNTP_AIVAL_RELOAD: + r =3D s->cntp_aival_reload; + break; + case A_CNTP_AIVAL_CTL: + /* + * All the bits of AIVAL_CTL are documented as WO, but this is pro= bably + * a documentation error. We implement them as readable. + */ + r =3D s->cntp_aival_ctl; + break; + case A_CNTP_CFG: + r =3D R_CNTP_CFG_AIVAL_IMPLEMENTED << R_CNTP_CFG_AIVAL_SHIFT; + break; + case A_PID4 ... A_CID3: + r =3D timer_id[(offset - A_PID4) / 4]; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "SSE System Timer read: bad offset 0x%x", + (unsigned) offset); + r =3D 0; + break; + } + + trace_sse_timer_read(offset, r, size); + return r; +} + +static void sse_timer_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + SSETimer *s =3D SSE_TIMER(opaque); + + trace_sse_timer_write(offset, value, size); + + switch (offset) { + case A_CNTFRQ: + s->cntfrq =3D value; + break; + case A_CNTP_CVAL_LO: + s->cntp_cval =3D deposit64(s->cntp_cval, 0, 32, value); + sse_recalc_timer(s); + break; + case A_CNTP_CVAL_HI: + s->cntp_cval =3D deposit64(s->cntp_cval, 32, 32, value); + sse_recalc_timer(s); + break; + case A_CNTP_TVAL: + s->cntp_cval =3D sse_cntpct(s) + sextract64(value, 0, 32); + sse_recalc_timer(s); + break; + case A_CNTP_CTL: + { + uint32_t old_ctl =3D s->cntp_ctl; + value &=3D R_CNTP_CTL_ENABLE_MASK | R_CNTP_CTL_IMASK_MASK; + s->cntp_ctl =3D value; + if ((old_ctl ^ s->cntp_ctl) & R_CNTP_CTL_ENABLE_MASK) { + if (sse_enabled(s)) { + if (sse_is_autoinc(s)) { + sse_autoinc(s); + } else { + sse_recalc_timer(s); + } + } + } + sse_update_irq(s); + break; + } + case A_CNTP_AIVAL_RELOAD: + s->cntp_aival_reload =3D value; + break; + case A_CNTP_AIVAL_CTL: + { + uint32_t old_ctl =3D s->cntp_aival_ctl; + + /* EN bit is writeable; CLR bit is write-0-to-clear, write-1-ignor= ed */ + s->cntp_aival_ctl &=3D ~R_CNTP_AIVAL_CTL_EN_MASK; + s->cntp_aival_ctl |=3D value & R_CNTP_AIVAL_CTL_EN_MASK; + if (!(value & R_CNTP_AIVAL_CTL_CLR_MASK)) { + s->cntp_aival_ctl &=3D ~R_CNTP_AIVAL_CTL_CLR_MASK; + } + if ((old_ctl ^ s->cntp_aival_ctl) & R_CNTP_AIVAL_CTL_EN_MASK) { + /* Auto-increment toggled on/off */ + if (sse_enabled(s)) { + if (sse_is_autoinc(s)) { + sse_autoinc(s); + } else { + sse_recalc_timer(s); + } + } + } + sse_update_irq(s); + break; + } + case A_CNTPCT_LO: + case A_CNTPCT_HI: + case A_CNTP_CFG: + case A_CNTP_AIVAL_LO: + case A_CNTP_AIVAL_HI: + case A_PID4 ... A_CID3: + qemu_log_mask(LOG_GUEST_ERROR, + "SSE System Timer write: write to RO offset 0x%x\n", + (unsigned)offset); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "SSE System Timer write: bad offset 0x%x\n", + (unsigned)offset); + break; + } +} + +static const MemoryRegionOps sse_timer_ops =3D { + .read =3D sse_timer_read, + .write =3D sse_timer_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static void sse_timer_reset(DeviceState *dev) +{ + SSETimer *s =3D SSE_TIMER(dev); + + trace_sse_timer_reset(); + + timer_del(&s->timer); + s->cntfrq =3D 0; + s->cntp_ctl =3D 0; + s->cntp_cval =3D 0; + s->cntp_aival =3D 0; + s->cntp_aival_ctl =3D 0; + s->cntp_aival_reload =3D 0; +} + +static void sse_timer_counter_callback(Notifier *notifier, void *data) +{ + SSETimer *s =3D container_of(notifier, SSETimer, counter_notifier); + + /* System counter told us we need to recalculate */ + if (sse_enabled(s)) { + if (sse_is_autoinc(s)) { + sse_set_timer(s, s->cntp_aival); + } else { + sse_recalc_timer(s); + } + } +} + +static void sse_timer_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + SSETimer *s =3D SSE_TIMER(obj); + + memory_region_init_io(&s->iomem, obj, &sse_timer_ops, + s, "sse-timer", 0x1000); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); +} + +static void sse_timer_realize(DeviceState *dev, Error **errp) +{ + SSETimer *s =3D SSE_TIMER(dev); + + if (!s->counter) { + error_setg(errp, "counter property was not set"); + } + + s->counter_notifier.notify =3D sse_timer_counter_callback; + sse_counter_register_consumer(s->counter, &s->counter_notifier); + + timer_init_ns(&s->timer, QEMU_CLOCK_VIRTUAL, sse_timer_cb, s); +} + +static const VMStateDescription sse_timer_vmstate =3D { + .name =3D "sse-timer", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_TIMER(timer, SSETimer), + VMSTATE_UINT32(cntfrq, SSETimer), + VMSTATE_UINT32(cntp_ctl, SSETimer), + VMSTATE_UINT64(cntp_cval, SSETimer), + VMSTATE_UINT64(cntp_aival, SSETimer), + VMSTATE_UINT32(cntp_aival_ctl, SSETimer), + VMSTATE_UINT32(cntp_aival_reload, SSETimer), + VMSTATE_END_OF_LIST() + } +}; + +static Property sse_timer_properties[] =3D { + DEFINE_PROP_LINK("counter", SSETimer, counter, TYPE_SSE_COUNTER, SSECo= unter *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sse_timer_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D sse_timer_realize; + dc->vmsd =3D &sse_timer_vmstate; + dc->reset =3D sse_timer_reset; + device_class_set_props(dc, sse_timer_properties); +} + +static const TypeInfo sse_timer_info =3D { + .name =3D TYPE_SSE_TIMER, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(SSETimer), + .instance_init =3D sse_timer_init, + .class_init =3D sse_timer_class_init, +}; + +static void sse_timer_register_types(void) +{ + type_register_static(&sse_timer_info); +} + +type_init(sse_timer_register_types); diff --git a/MAINTAINERS b/MAINTAINERS index 1c9b2f446ef..df0eddc7170 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -744,6 +744,8 @@ F: hw/misc/armsse-mhu.c F: include/hw/misc/armsse-mhu.h F: hw/timer/sse-counter.c F: include/hw/timer/sse-counter.h +F: hw/timer/sse-timer.c +F: include/hw/timer/sse-timer.h F: docs/system/arm/mps2.rst =20 Musca diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 3081efce20b..ed007267a91 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -520,6 +520,7 @@ config ARMSSE select TZ_PPC select UNIMP select SSE_COUNTER + select SSE_TIMER =20 config ARMSSE_CPUID bool diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig index e103c8872ab..726be4f82ca 100644 --- a/hw/timer/Kconfig +++ b/hw/timer/Kconfig @@ -45,5 +45,8 @@ config RENESAS_CMT config SSE_COUNTER bool =20 +config SSE_TIMER + bool + config AVR_TIMER16 bool diff --git a/hw/timer/meson.build b/hw/timer/meson.build index 79a3012349d..91ab2aa803f 100644 --- a/hw/timer/meson.build +++ b/hw/timer/meson.build @@ -33,6 +33,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2= 835_systmr.c')) softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_timer.c')) softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_timer.c')) softmmu_ss.add(when: 'CONFIG_SSE_COUNTER', if_true: files('sse-counter.c')) +softmmu_ss.add(when: 'CONFIG_SSE_TIMER', if_true: files('sse-timer.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_TIMER', if_true: files('stm32f2xx_t= imer.c')) softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_timer.c')) =20 diff --git a/hw/timer/trace-events b/hw/timer/trace-events index bb9c1000878..f8b9db25c27 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -100,3 +100,8 @@ sse_counter_control_write(uint64_t offset, uint64_t dat= a, unsigned size) "SSE sy sse_counter_status_read(uint64_t offset, uint64_t data, unsigned size) "SS= E system counter status frame read: offset 0x%" PRIx64 " data 0x%" PRIx64 "= size %u" sse_counter_status_write(uint64_t offset, uint64_t data, unsigned size) "S= SE system counter status frame write: offset 0x%" PRIx64 " data 0x%" PRIx64= " size %u" sse_counter_reset(void) "SSE system counter: reset" + +# sse_timer.c +sse_timer_read(uint64_t offset, uint64_t data, unsigned size) "SSE system = timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" +sse_timer_write(uint64_t offset, uint64_t data, unsigned size) "SSE system= timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" +sse_timer_reset(void) "SSE system timer: reset" --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=VlIXUUm5ExpVQJSv3wuqQbS06DQIaBTiir8iebjqnw0=; b=VcScL0gCuf9fLD21jw6ORKCliUJiHUmUmTIjoJ5/X3BayI9sf7zhETvGiM/BT3cup2 WdijjovxoGOpypQkrKjO4sL6ANa+LVp68bNDqjfoegDVOWi+AkOXmx3Cc79YSvdJHwiQ FbSPX+UG9XJkvPC8hlewJOa3uPkiumE5/38dgr7oDhItPhkcAMu7EH+XrqG76ZbprBqu LAu/ylL6iMC2ouiCfsTrI1YLYIA9QNA3Is/l+/QYe7vUJ4kWQ7prWFuwTrM8m2gN8dPz Lacx0SU16kR30nEv1gGq2bKlobopkjsHMFN9X0y0Pu4UVGhx0igcn5i6IXt492GQy2OM 9Mpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VlIXUUm5ExpVQJSv3wuqQbS06DQIaBTiir8iebjqnw0=; b=qWbZR9TrMEZjorNQaNPEOciBf0ZU/jhKrYWTluSas7Mymkaxznc5/6ZRZsc2O4NmDE 7uLcBY7jKzMNe5Neir+WcSCsH/ltTq/i/z6o5LnhNpIIkgPIG2soUwa2xdp5QMY1BYkK BCtFlhvdw+Dxj01XwWqbp/8XiIHAhK/CC+6DfViFAycbh8+KRsV7immudl4mACpI9eez KsRTwdxBU9M43bImud/FC7LOPsjAtDtJW8ocV4XMfF97oQx5R2sk681DY66pu4ZyBnqb sULzE6cOMbg7ig+Ljq8AGnpDEZw7v0qKQbwcrCboFC7RTMJprUKsBKrU4mjdSUfUtL/3 SN+A== X-Gm-Message-State: AOAM532kNCeynP66tUUzol0snEXCKxDLR4oYiOlZb8oEYhaYEjY0jDVf +Sc6NQpKnvgtCH1D8h3kjO0gMIvidlc8FA== X-Google-Smtp-Source: ABdhPJzyjiktcFmT3KFpBLBhqZwBLtp31W8vgWRK1lbopSHyXNU/EwNhrJxH45pz6Sru80VBlX+fDA== X-Received: by 2002:adf:9c8a:: with SMTP id d10mr9729887wre.266.1613745990431; Fri, 19 Feb 2021 06:46:30 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 13/44] hw/misc/iotkit-sysctl: Add SSE-300 cases which match SSE-200 behaviour Date: Fri, 19 Feb 2021 14:45:46 +0000 Message-Id: <20210219144617.4782-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The SSE-300's iokit-sysctl device is similar to the SSE-200, but some registers have moved address or have different behaviours. In this commit we add case statements for the registers where the SSE-300 and SSE-200 have the same behaviour. Some registers are the same on all SSE versions and so need no code change at all. Putting both of these categories together covers: 0x0 SECDBGSTAT 0x4 SECDBGSET 0x8 SECDBGCLR 0xc SCSECCTRL 0x10 CLK_CFG0 -- this is like SSE-200 FCLK_DIV but with a different set of clocks being controlled; our implementation is a dummy reads-as-written anyway 0x14 CLK_CFG1 -- similar to SSE-200 SYSCLK_DIV; our implementation is a dummy 0x18 CLK_FORCE -- similar to SSE-200 but different bit allocations; we have a dummy implementation 0x100 RESET_SYNDROME -- bit allocation differs from SSE-200 but our implementation is a dummy 0x104 RESET_MASK -- bit allocation differs from SSE-200 but our implementation is a dummy 0x108 SWRESET 0x10c GRETREG 0x200 PDCM_PD_SYS_SENSE -- some bit allocations differ, but our implementation is a dummy We also need to migrate the state of these registers which are shared between the SSE-200 and SSE-300, so update the vmstate 'needed' function to do this. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/iotkit-sysctl.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index c67f5b320ab..7f8608c814c 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -105,6 +105,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, case ARMSSE_IOTKIT: goto bad_offset; case ARMSSE_SSE200: + case ARMSSE_SSE300: r =3D s->scsecctrl; break; default: @@ -116,6 +117,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, case ARMSSE_IOTKIT: goto bad_offset; case ARMSSE_SSE200: + case ARMSSE_SSE300: r =3D s->fclk_div; break; default: @@ -127,6 +129,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, case ARMSSE_IOTKIT: goto bad_offset; case ARMSSE_SSE200: + case ARMSSE_SSE300: r =3D s->sysclk_div; break; default: @@ -138,6 +141,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, case ARMSSE_IOTKIT: goto bad_offset; case ARMSSE_SSE200: + case ARMSSE_SSE300: r =3D s->clock_force; break; default: @@ -202,6 +206,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, case ARMSSE_IOTKIT: goto bad_offset; case ARMSSE_SSE200: + case ARMSSE_SSE300: r =3D s->pdcm_pd_sys_sense; break; default: @@ -348,6 +353,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, case ARMSSE_IOTKIT: goto bad_offset; case ARMSSE_SSE200: + case ARMSSE_SSE300: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemente= d\n"); s->scsecctrl =3D value; break; @@ -360,6 +366,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, case ARMSSE_IOTKIT: goto bad_offset; case ARMSSE_SSE200: + case ARMSSE_SSE300: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented= \n"); s->fclk_div =3D value; break; @@ -372,6 +379,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, case ARMSSE_IOTKIT: goto bad_offset; case ARMSSE_SSE200: + case ARMSSE_SSE300: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplement= ed\n"); s->sysclk_div =3D value; break; @@ -384,6 +392,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, case ARMSSE_IOTKIT: goto bad_offset; case ARMSSE_SSE200: + case ARMSSE_SSE300: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemen= ted\n"); s->clock_force =3D value; break; @@ -420,6 +429,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, case ARMSSE_IOTKIT: goto bad_offset; case ARMSSE_SSE200: + case ARMSSE_SSE300: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n= "); s->pdcm_pd_sys_sense =3D value; @@ -569,7 +579,7 @@ static bool sse200_needed(void *opaque) { IoTKitSysCtl *s =3D IOTKIT_SYSCTL(opaque); =20 - return s->sse_version =3D=3D ARMSSE_SSE200; + return s->sse_version !=3D ARMSSE_IOTKIT; } =20 static const VMStateDescription iotkit_sysctl_sse200_vmstate =3D { --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613746626564882.3184409857633; Fri, 19 Feb 2021 06:57:06 -0800 (PST) Received: from localhost ([::1]:56848 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7DN-0005nV-Dl for importer@patchew.org; Fri, 19 Feb 2021 09:57:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33774) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73R-0002JU-0V for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:49 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:38712) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73A-0003SU-CY for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:48 -0500 Received: by mail-wm1-x336.google.com with SMTP id x4so7881610wmi.3 for ; Fri, 19 Feb 2021 06:46:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Vhghzb1KxboqZ+GwFa0MaTa9cSu8tLM6q3ZGrvP0/yI=; b=zWt7xen9sIh++ZpFy7HZ/9gg1zpkaopEVGu/BOzrszGvPGtUhsTmezigIYtERRYv92 t7qKY1JGTNKXiF6Df845qvtEiYQpWV9nZPiyyWgBbZLe3l3cJ57OY8QEl0ErBQ626Xv4 42fWt0FlK0UwwViMwfbPULTmwWsmTcQIJI13gPciRdX2AsYPSzD9TVleu7ErpbXZ5Kgi kx8PC6C5WsjG0xAt9QKEmeAO507z8s0Vm+qYRPmiFSyg/IWy7LsNJ2RTRDFhoZAUIESp liuZ4IgUXUGnfIH0UKlFr5emA+8UlB/Q24MWL1GXJXerVX9tJlM6vF/yROrWFSKfhtuo 0AdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Vhghzb1KxboqZ+GwFa0MaTa9cSu8tLM6q3ZGrvP0/yI=; b=hT04TjnhHG9zaKyIUGFEKzRV1rD3HHAJagnly3En6SOI9JlBo+PRRNTauDv9s6Rb9I whETWWS+2fID4Qsxa8Z8L+NlURWlKMjV2aNBuNRn9ob5SJwW4IKNeCv/VXtzF13f6lvp zYzwS0KvwFZqoyHlVRymMGVOQetbMKu0f5OyLNulRrPcZ2S8PwPkypMXXHmJz0vcmQsV siL56FwjoyGAtkUOzDdEW28GMmXyiM6eMNDnoCGQ/pJcz4yjLT5x5X+4S3G+H7DkqZy9 ncBzAaSShluW3QQ57nvj4kLJf551aM4s+fA8ENHBSKRt94LMv8fkO6EIDmjfQXyU8JZw +wUQ== X-Gm-Message-State: AOAM530IiqHJ05objx9soPVuExUv1x1INaqOkExpyT+5Kz3V7+7lHxUf 0GpTit4goLWJTV6ch0SlrxdeHw== X-Google-Smtp-Source: ABdhPJxPM12ZstDgVxoYBHxk82151pQJAQmNVhmoYZsfK0Mqyie3V0JsHqPSQ/xeYWdFvDP8ZaVUtw== X-Received: by 2002:a1c:e309:: with SMTP id a9mr8484824wmh.99.1613745991111; Fri, 19 Feb 2021 06:46:31 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 14/44] hw/misc/iotkit-sysctl: Handle CPU_WAIT, NMI_ENABLE for SSE-300 Date: Fri, 19 Feb 2021 14:45:47 +0000 Message-Id: <20210219144617.4782-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In the SSE-300 the CPU_WAIT and NMI_ENABLE registers have moved offsets, so they are now where the SSE-200's WICCTRL and EWCTRL were. The SSE-300 does not have WICCTLR or EWCTRL at all, and the old offsets are reserved: Offset SSE-200 SSE-300 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 ----------------------------------- 0x118 CPUWAIT reserved 0x118 NMI_ENABLE reserved 0x120 WICCTRL CPUWAIT 0x124 EWCTRL NMI_ENABLE Handle this reshuffle, and the fact that SSE-300 has only one CPU and so only one active bit in CPUWAIT. Signed-off-by: Peter Maydell --- hw/misc/iotkit-sysctl.c | 88 +++++++++++++++++++++++++++++++++++------ 1 file changed, 76 insertions(+), 12 deletions(-) diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index 7f8608c814c..54004bebcbf 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -172,7 +172,17 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwadd= r offset, } break; case A_CPUWAIT: - r =3D s->cpuwait; + switch (s->sse_version) { + case ARMSSE_IOTKIT: + case ARMSSE_SSE200: + r =3D s->cpuwait; + break; + case ARMSSE_SSE300: + /* In SSE300 this is reserved (for INITSVTOR2) */ + goto bad_offset; + default: + g_assert_not_reached(); + } break; case A_NMI_ENABLE: switch (s->sse_version) { @@ -183,12 +193,26 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwad= dr offset, case ARMSSE_SSE200: r =3D s->nmi_enable; break; + case ARMSSE_SSE300: + /* In SSE300 this is reserved (for INITSVTOR3) */ + goto bad_offset; default: g_assert_not_reached(); } break; case A_WICCTRL: - r =3D s->wicctrl; + switch (s->sse_version) { + case ARMSSE_IOTKIT: + case ARMSSE_SSE200: + r =3D s->wicctrl; + break; + case ARMSSE_SSE300: + /* In SSE300 this offset is CPUWAIT */ + r =3D s->cpuwait; + break; + default: + g_assert_not_reached(); + } break; case A_EWCTRL: switch (s->sse_version) { @@ -197,6 +221,10 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwadd= r offset, case ARMSSE_SSE200: r =3D s->ewctrl; break; + case ARMSSE_SSE300: + /* In SSE300 this offset is is NMI_ENABLE */ + r =3D s->nmi_enable; + break; default: g_assert_not_reached(); } @@ -279,6 +307,21 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwadd= r offset, return r; } =20 +static void cpuwait_write(IoTKitSysCtl *s, uint32_t value) +{ + int num_cpus =3D (s->sse_version =3D=3D ARMSSE_SSE300) ? 1 : 2; + int i; + + for (i =3D 0; i < num_cpus; i++) { + uint32_t mask =3D 1 << i; + if ((s->cpuwait & mask) && !(value & mask)) { + /* Powering up CPU 0 */ + arm_set_cpu_on_and_reset(i); + } + } + s->cpuwait =3D value; +} + static void iotkit_sysctl_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { @@ -319,19 +362,32 @@ static void iotkit_sysctl_write(void *opaque, hwaddr = offset, set_init_vtor(0, s->initsvtor0); break; case A_CPUWAIT: - if ((s->cpuwait & 1) && !(value & 1)) { - /* Powering up CPU 0 */ - arm_set_cpu_on_and_reset(0); + switch (s->sse_version) { + case ARMSSE_IOTKIT: + case ARMSSE_SSE200: + cpuwait_write(s, value); + break; + case ARMSSE_SSE300: + /* In SSE300 this is reserved (for INITSVTOR2) */ + goto bad_offset; + default: + g_assert_not_reached(); } - if ((s->cpuwait & 2) && !(value & 2)) { - /* Powering up CPU 1 */ - arm_set_cpu_on_and_reset(1); - } - s->cpuwait =3D value; break; case A_WICCTRL: - qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl WICCTRL unimplemented\n"); - s->wicctrl =3D value; + switch (s->sse_version) { + case ARMSSE_IOTKIT: + case ARMSSE_SSE200: + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl WICCTRL unimplemented\= n"); + s->wicctrl =3D value; + break; + case ARMSSE_SSE300: + /* In SSE300 this offset is CPUWAIT */ + cpuwait_write(s, value); + break; + default: + g_assert_not_reached(); + } break; case A_SECDBGSET: /* write-1-to-set */ @@ -420,6 +476,11 @@ static void iotkit_sysctl_write(void *opaque, hwaddr o= ffset, qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n= "); s->ewctrl =3D value; break; + case ARMSSE_SSE300: + /* In SSE300 this offset is is NMI_ENABLE */ + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplement= ed\n"); + s->nmi_enable =3D value; + break; default: g_assert_not_reached(); } @@ -499,6 +560,9 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplement= ed\n"); s->nmi_enable =3D value; break; + case ARMSSE_SSE300: + /* In SSE300 this is reserved (for INITSVTOR3) */ + goto bad_offset; default: g_assert_not_reached(); } --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613746593; cv=none; d=zohomail.com; s=zohoarc; b=U9mch+CshEVEJHTqpm3hkofycJQxWsOTjUJYebzgHlInKmCwt+jtrHmeJPh9uMubDfE18TmN/fKFVBfnfs0gIoioGKVQZv5YzeJGzc5KY/WI2GzoddozgAiddQvdjZchJV/Eplm5X3yQ1zAPulV6FIybPanr080cbyhAcBP5NFk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613746593; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qKpO3g5I9T89Pw01l2LVIOco0YgBK3pSTlmYgHP1fjA=; b=GcRNMPjzafQk6s85V+wjXspNr537ZTokcMeNQAGlxPOU+UT/sXPnlvJ/Xu89fb80+r4BRvgaooLh+lfWMwkLbysneTgoc81lg7mnlDjy1dqiiRDEj/I6pY7Lw5km6cmJixQUQIKcUCXl884ZE8tN4ZlPbz3DlUl/RZLonbRzAAg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613746592602706.5884153333632; Fri, 19 Feb 2021 06:56:32 -0800 (PST) Received: from localhost ([::1]:53740 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7Cp-0004OD-BY for importer@patchew.org; Fri, 19 Feb 2021 09:56:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73S-0002KV-8E for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:50 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:36326) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73B-0003Tm-3n for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:49 -0500 Received: by mail-wr1-x431.google.com with SMTP id u14so8897285wri.3 for ; Fri, 19 Feb 2021 06:46:32 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qKpO3g5I9T89Pw01l2LVIOco0YgBK3pSTlmYgHP1fjA=; b=UPc5qbYJ3BncknN1yf8s1CSy4n29Q9AOq7jKpPZkhtQEa0wcGVs2TwlaRiB3pufwTA 0o2N1itB2QAN6w+61DKMcDlU96q+OVKRTMK7SpkUXHdnOtSty+CVEd+PnKvPIPMrtc+6 O1/xIE1YFvg7cjjuUtc2AsTYmuV9WbxqVXXx7nJVn5LjH3gajp6D24TMTGqSHsZQyJjv xj8hqgmLC1z2/RRPMC4HikV4TYJ12kJW/UCCMxc1egdVdOgaxnDkmxLWv0Xgf1UhCs+F IIsKUFQu59FIg2NTD5wph8NAQgupZhy4P+jYuc5CcusMCouTT1fJzq7E4Icdkmx3JZPA Ap5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qKpO3g5I9T89Pw01l2LVIOco0YgBK3pSTlmYgHP1fjA=; b=QvTZnH/TL3FNMbg2Y2duAgQTSHSq0KWaIbftVZaTxHr2bgz6FYhx0fpb6askledo1A Lqp9CfxR8CYSp8dZqm3NGSi3mzSqcmvy5BRUaaWdCQfNRm8Hbccibv1nmJmf1yOMghaO 7oS87CP1umy83hCufql76kKDHwLEgokabDM60t1d4SETgg9BhOV1C/+/EtckQJOFcHX7 QjfHxrLGAxHmtg1wdsGYSVI1w9oQdHP0u2QkG1uq8rXBqCrZiOpcRlvnRq6TRdQD/TP5 yA3T+Hal4Z/zJgbTS8XRF8/fH6M1gFXBse6E1NFs+6mo1JypAcRUGFFs2aEz1B4+18VJ GDNg== X-Gm-Message-State: AOAM531B9FwPFhbaNkZ662LJQYQqrcDyw4wdXkbz7demzDkKafzs6lSc 4KNm+lsUyX6szd0CNLZsWy02gQ== X-Google-Smtp-Source: ABdhPJyvu7riBEgbeotpuQAGeeDW9e6I1433Y4BpYmaa72kFjMR4lTQVxeJ3bnrMd/Wh1X6dzp6ZWg== X-Received: by 2002:a5d:66c5:: with SMTP id k5mr9721886wrw.302.1613745991830; Fri, 19 Feb 2021 06:46:31 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 15/44] hw/misc/iotkit-sysctl: Handle INITSVTOR* for SSE-300 Date: Fri, 19 Feb 2021 14:45:48 +0000 Message-Id: <20210219144617.4782-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The SSE-300 has only one CPU and so no INITSVTOR1. It does have INITSVTOR0, but unlike the SSE-200 this register now has a LOCK bit which can be set to 1 to prevent any further writes to the register. Implement these differences. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/iotkit-sysctl.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index 54004bebcbf..ab97055f529 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -45,6 +45,7 @@ REG32(SWRESET, 0x108) FIELD(SWRESET, SWRESETREQ, 9, 1) REG32(GRETREG, 0x10c) REG32(INITSVTOR0, 0x110) + FIELD(INITSVTOR0, LOCK, 0, 1) REG32(INITSVTOR1, 0x114) REG32(CPUWAIT, 0x118) REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */ @@ -167,6 +168,8 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, case ARMSSE_SSE200: r =3D s->initsvtor1; break; + case ARMSSE_SSE300: + goto bad_offset; default: g_assert_not_reached(); } @@ -358,8 +361,25 @@ static void iotkit_sysctl_write(void *opaque, hwaddr o= ffset, s->gretreg =3D value; break; case A_INITSVTOR0: - s->initsvtor0 =3D value; - set_init_vtor(0, s->initsvtor0); + switch (s->sse_version) { + case ARMSSE_SSE300: + /* SSE300 has a LOCK bit which prevents further writes when se= t */ + if (s->initsvtor0 & R_INITSVTOR0_LOCK_MASK) { + qemu_log_mask(LOG_GUEST_ERROR, + "IoTKit INITSVTOR0 write when register locke= d\n"); + break; + } + s->initsvtor0 =3D value; + set_init_vtor(0, s->initsvtor0 & ~R_INITSVTOR0_LOCK_MASK); + break; + case ARMSSE_IOTKIT: + case ARMSSE_SSE200: + s->initsvtor0 =3D value; + set_init_vtor(0, s->initsvtor0); + break; + default: + g_assert_not_reached(); + } break; case A_CPUWAIT: switch (s->sse_version) { @@ -464,6 +484,8 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, s->initsvtor1 =3D value; set_init_vtor(1, s->initsvtor1); break; + case ARMSSE_SSE300: + goto bad_offset; default: g_assert_not_reached(); } --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613747316650594.2223193675432; Fri, 19 Feb 2021 07:08:36 -0800 (PST) Received: from localhost ([::1]:33734 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7OV-0003lP-JH for importer@patchew.org; Fri, 19 Feb 2021 10:08:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33990) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73b-0002Sp-VK for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:01 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:38364) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73B-0003Ud-Vq for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:59 -0500 Received: by mail-wr1-x429.google.com with SMTP id b3so8885789wrj.5 for ; Fri, 19 Feb 2021 06:46:33 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=TmDv8Ark28Kk9q6F5pp4r3C2pFWL+y0OiDgJ+fBRPtM=; b=XgemUiF3rhqVMDpiCR3mpwvvfjCgIjV/dS9mcUiHa4YtQcttLdMpwWQaM6gu3dtDac Go1eSgONVGMZltDUBuJryvPw3N/7jfC9K4i/+0y99GJelGfPD8axuQnJBMn7oemBXfv5 bEfJ4QBISMtkdag9wCy6NLbSdDqqJqPCVJNrkbLxFFX3fYYygNtD0bo3ujw4qzDhQcEE /A1dm32oCqsW1mGQTON2Z790MBHGc4mxgTaPkkW36zpJlgDp1mlKZDE+0iedsiTpPKAP egSAffQZHGmpxeRKn+fTZfiYFEB3sJfgHY0jU88a9gWIerpAV3LszYzcOqMqiUvWMAzk Fvhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TmDv8Ark28Kk9q6F5pp4r3C2pFWL+y0OiDgJ+fBRPtM=; b=gmmlDRDdfEPveyqQlrZZKuw/1YYU2tbJUkMsvEwkrYv2A7Wt4pbFOzZSI/oB436sLt okxuWiG0DpIuGomX62tHePkfkvKK6uG5XlEQkQIr3OODw3I0wJI2UZ8+FCC9X3kAB7ja qOpZiqymTBnH3K1vA3K3sXeR6r87V/RGI7Vca5K0bMZEsuEFldxBHvM2OCUh0sx6vy7o wznV1ejUnzcBN8+9AIrvimivpwUjQ8D/+irpeNWdykLtlVqeOcEA1OJejHQuJp3wVBaw Mhsnhu4ahFcXa9FWa5QlDEOyQw1ToENN0/MpSWM4v+C2OIi7ycs+370lCllZDYAuWnhX Aonw== X-Gm-Message-State: AOAM532Es3ybst/AIndTG52oHKJmFiQylVgV8Rz3X9BmjgGMaHSBvDK6 zZ6FAhEMSvXX31hT0ptM5fsXng== X-Google-Smtp-Source: ABdhPJxey8WYXdmOccnH0oyLtyKaDSLJUZoh04S/4m5nSg467p/pjI5nOirLd7lYbuQthxDj8s86qQ== X-Received: by 2002:a5d:47a8:: with SMTP id 8mr9264896wrb.180.1613745992570; Fri, 19 Feb 2021 06:46:32 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 16/44] hw/misc/iotkit-sysctl: Implement dummy version of SSE-300 PWRCTRL register Date: Fri, 19 Feb 2021 14:45:49 +0000 Message-Id: <20210219144617.4782-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The SSE-300 has a new PWRCTRL register at offset 0x1fc (previously reserved). This register controls accessibility of some registers in the Power Policy Units (PPUs). Since QEMU doesn't implement the PPUs, we don't need to implement any real behaviour for this register, so we just handle the UNLOCK bit which controls whether writes to the register itself are permitted and otherwise make it be reads-as-written. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/iotkit-sysctl.h | 1 + hw/misc/iotkit-sysctl.c | 52 +++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysct= l.h index 980c2ddfd3c..8859b15d73b 100644 --- a/include/hw/misc/iotkit-sysctl.h +++ b/include/hw/misc/iotkit-sysctl.h @@ -53,6 +53,7 @@ struct IoTKitSysCtl { uint32_t initsvtor1; uint32_t nmi_enable; uint32_t ewctrl; + uint32_t pwrctrl; uint32_t pdcm_pd_sys_sense; uint32_t pdcm_pd_sram0_sense; uint32_t pdcm_pd_sram1_sense; diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index ab97055f529..e8255d26b5a 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -51,6 +51,9 @@ REG32(CPUWAIT, 0x118) REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */ REG32(WICCTRL, 0x120) REG32(EWCTRL, 0x124) +REG32(PWRCTRL, 0x1fc) + FIELD(PWRCTRL, PPU_ACCESS_UNLOCK, 0, 1) + FIELD(PWRCTRL, PPU_ACCESS_FILTER, 1, 1) REG32(PDCM_PD_SYS_SENSE, 0x200) REG32(PDCM_PD_SRAM0_SENSE, 0x20c) REG32(PDCM_PD_SRAM1_SENSE, 0x210) @@ -232,6 +235,18 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwadd= r offset, g_assert_not_reached(); } break; + case A_PWRCTRL: + switch (s->sse_version) { + case ARMSSE_IOTKIT: + case ARMSSE_SSE200: + goto bad_offset; + case ARMSSE_SSE300: + r =3D s->pwrctrl; + break; + default: + g_assert_not_reached(); + } + break; case A_PDCM_PD_SYS_SENSE: switch (s->sse_version) { case ARMSSE_IOTKIT: @@ -507,6 +522,23 @@ static void iotkit_sysctl_write(void *opaque, hwaddr o= ffset, g_assert_not_reached(); } break; + case A_PWRCTRL: + switch (s->sse_version) { + case ARMSSE_IOTKIT: + case ARMSSE_SSE200: + goto bad_offset; + case ARMSSE_SSE300: + if (!(s->pwrctrl & R_PWRCTRL_PPU_ACCESS_UNLOCK_MASK)) { + qemu_log_mask(LOG_GUEST_ERROR, + "IoTKit PWRCTRL write when register locked\n= "); + break; + } + s->pwrctrl =3D value; + break; + default: + g_assert_not_reached(); + } + break; case A_PDCM_PD_SYS_SENSE: switch (s->sse_version) { case ARMSSE_IOTKIT: @@ -634,6 +666,7 @@ static void iotkit_sysctl_reset(DeviceState *dev) s->clock_force =3D 0; s->nmi_enable =3D 0; s->ewctrl =3D 0; + s->pwrctrl =3D 0x3; s->pdcm_pd_sys_sense =3D 0x7f; s->pdcm_pd_sram0_sense =3D 0; s->pdcm_pd_sram1_sense =3D 0; @@ -661,6 +694,24 @@ static void iotkit_sysctl_realize(DeviceState *dev, Er= ror **errp) } } =20 +static bool sse300_needed(void *opaque) +{ + IoTKitSysCtl *s =3D IOTKIT_SYSCTL(opaque); + + return s->sse_version =3D=3D ARMSSE_SSE300; +} + +static const VMStateDescription iotkit_sysctl_sse300_vmstate =3D { + .name =3D "iotkit-sysctl/sse-300", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D sse300_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(pwrctrl, IoTKitSysCtl), + VMSTATE_END_OF_LIST() + } +}; + static bool sse200_needed(void *opaque) { IoTKitSysCtl *s =3D IOTKIT_SYSCTL(opaque); @@ -705,6 +756,7 @@ static const VMStateDescription iotkit_sysctl_vmstate = =3D { }, .subsections =3D (const VMStateDescription*[]) { &iotkit_sysctl_sse200_vmstate, + &iotkit_sysctl_sse300_vmstate, NULL } }; --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613746696433294.5363229302725; Fri, 19 Feb 2021 06:58:16 -0800 (PST) Received: from localhost ([::1]:33886 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7EV-0007zF-CS for importer@patchew.org; Fri, 19 Feb 2021 09:58:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73U-0002Oi-OV for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:52 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:38367) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73C-0003Vg-Qn for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:46:52 -0500 Received: by mail-wr1-x42c.google.com with SMTP id b3so8885864wrj.5 for ; Fri, 19 Feb 2021 06:46:34 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=AJDCZ5O3Sn9dNbDBTisc4ZNJwVgLelQLa4u+3Pzsjbc=; b=KGbPI45tV6zAFAl11w3v9T/2j1hPrCtXbAB4KLaLvn9ErLR2t1oBO+/WUvj4j3vet+ GIRXX3yVklr2WWroUvItxVKOK35salM8tHa/DwgrIs3xD9PIqaGX4GctnF5bLlx227he YkAtMCWzZl/oBrC5OyYt1v7/F/RfN283iA+RlxuNov1FV1zFTII3JYer1nM07lTiRJ7v 2aVlZXWRtUqkbO99vkqLPVQjl6dYZGXEq5JoPbzHml226/gGTMBI+3MgcK6Dlmgclxuw V18PAVlqoFNQSlNkYPumpM3bgE0V+1WRNDKPwpYd1hlKzLImcSlItmPgOlRRBaUQXqZz S2/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AJDCZ5O3Sn9dNbDBTisc4ZNJwVgLelQLa4u+3Pzsjbc=; b=WuV+PHBXKZKFTcrkf5k5m8xVsOnxM44GRgV+Ji0vAum9QAc9DubDck9W+a9TCQtSi5 HF8KTvFzc7uO7XrRK+/DPWZM4e0ELmTCaoUIqvuDzMtH6fQgrn2xBMjd8z8etCasNSsh BTaXprEvi5jlk3b2me949GZgJkhXdhnKv6Zx+MO1J5I1L+RaIpu4iCQYr3ppC09GlPYH C7X9X+q6hYQUW0ZLaWWW6NQXGeA5bMZ+FtxQr45W2X2nT8CilBvYtX5O4e5S415AOX4x Jv5Cu2FXFEmDMLgo19AHj5xRdVBT0RbETND03xO4TPuw/Aqc5LteOVpO5M/z6MgReQFY P4tQ== X-Gm-Message-State: AOAM53305Mfyhp1OLigfvlmD3NaXkKqlAbKKfAWldI1iFKXG1Qwb6m89 KlltiMAFToTdxEEaBYsA3MhLaA== X-Google-Smtp-Source: ABdhPJyLdVG/uo6lpon1Rt/2UEjFa6IMVECvcOsACunzYIR6wzpEoEyn+JTWwR8Ngr51u4T5hjDcRA== X-Received: by 2002:a5d:5109:: with SMTP id s9mr8160185wrt.325.1613745993330; Fri, 19 Feb 2021 06:46:33 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 17/44] hw/misc/iotkit-sysctl: Handle SSE-300 changes to PDCM_PD_*_SENSE registers Date: Fri, 19 Feb 2021 14:45:50 +0000 Message-Id: <20210219144617.4782-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The sysctl PDCM_PD_*_SENSE registers control various power domains in the system and allow the guest to configure which conditions keep a power domain awake and what power state to use when the domain is in a low power state. QEMU doesn't model power domains, so for us these registers are dummy reads-as-written implementations. The SSE-300 has a different power domain setup, so the set of registers is slightly different: Offset SSE-200 SSE-300 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --------------------------------------------------- 0x200 PDCM_PD_SYS_SENSE PDCM_PD_SYS_SENSE 0x204 reserved PDCM_PD_CPU0_SENSE 0x208 reserved reserved 0x20c PDCM_PD_SRAM0_SENSE reserved 0x210 PDCM_PD_SRAM1_SENSE reserved 0x214 PDCM_PD_SRAM2_SENSE PDCM_PD_VMR0_SENSE 0x218 PDCM_PD_SRAM3_SENSE PDCM_PD_VMR1_SENSE Offsets 0x200 and 0x208 are the same for both, so handled in a previous commit; here we deal with 0x204, 0x20c, 0x210, 0x214, 0x218. (We can safely add new lines to the SSE300 vmstate because no board uses this device in an SSE300 yet.) Signed-off-by: Peter Maydell --- include/hw/misc/iotkit-sysctl.h | 3 ++ hw/misc/iotkit-sysctl.c | 61 +++++++++++++++++++++++++++++++-- 2 files changed, 62 insertions(+), 2 deletions(-) diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysct= l.h index 8859b15d73b..481e27f4db1 100644 --- a/include/hw/misc/iotkit-sysctl.h +++ b/include/hw/misc/iotkit-sysctl.h @@ -59,6 +59,9 @@ struct IoTKitSysCtl { uint32_t pdcm_pd_sram1_sense; uint32_t pdcm_pd_sram2_sense; uint32_t pdcm_pd_sram3_sense; + uint32_t pdcm_pd_cpu0_sense; + uint32_t pdcm_pd_vmr0_sense; + uint32_t pdcm_pd_vmr1_sense; =20 /* Properties */ uint32_t sse_version; diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index e8255d26b5a..a80f68b7995 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -55,10 +55,11 @@ REG32(PWRCTRL, 0x1fc) FIELD(PWRCTRL, PPU_ACCESS_UNLOCK, 0, 1) FIELD(PWRCTRL, PPU_ACCESS_FILTER, 1, 1) REG32(PDCM_PD_SYS_SENSE, 0x200) +REG32(PDCM_PD_CPU0_SENSE, 0x204) REG32(PDCM_PD_SRAM0_SENSE, 0x20c) REG32(PDCM_PD_SRAM1_SENSE, 0x210) -REG32(PDCM_PD_SRAM2_SENSE, 0x214) -REG32(PDCM_PD_SRAM3_SENSE, 0x218) +REG32(PDCM_PD_SRAM2_SENSE, 0x214) /* PDCM_PD_VMR0_SENSE on SSE300 */ +REG32(PDCM_PD_SRAM3_SENSE, 0x218) /* PDCM_PD_VMR1_SENSE on SSE300 */ REG32(PID4, 0xfd0) REG32(PID5, 0xfd4) REG32(PID6, 0xfd8) @@ -259,6 +260,18 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwadd= r offset, g_assert_not_reached(); } break; + case A_PDCM_PD_CPU0_SENSE: + switch (s->sse_version) { + case ARMSSE_IOTKIT: + case ARMSSE_SSE200: + goto bad_offset; + case ARMSSE_SSE300: + r =3D s->pdcm_pd_cpu0_sense; + break; + default: + g_assert_not_reached(); + } + break; case A_PDCM_PD_SRAM0_SENSE: switch (s->sse_version) { case ARMSSE_IOTKIT: @@ -266,6 +279,8 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, case ARMSSE_SSE200: r =3D s->pdcm_pd_sram0_sense; break; + case ARMSSE_SSE300: + goto bad_offset; default: g_assert_not_reached(); } @@ -277,6 +292,8 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, case ARMSSE_SSE200: r =3D s->pdcm_pd_sram1_sense; break; + case ARMSSE_SSE300: + goto bad_offset; default: g_assert_not_reached(); } @@ -288,6 +305,9 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, case ARMSSE_SSE200: r =3D s->pdcm_pd_sram2_sense; break; + case ARMSSE_SSE300: + r =3D s->pdcm_pd_vmr0_sense; + break; default: g_assert_not_reached(); } @@ -299,6 +319,9 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, case ARMSSE_SSE200: r =3D s->pdcm_pd_sram3_sense; break; + case ARMSSE_SSE300: + r =3D s->pdcm_pd_vmr1_sense; + break; default: g_assert_not_reached(); } @@ -553,6 +576,20 @@ static void iotkit_sysctl_write(void *opaque, hwaddr o= ffset, g_assert_not_reached(); } break; + case A_PDCM_PD_CPU0_SENSE: + switch (s->sse_version) { + case ARMSSE_IOTKIT: + case ARMSSE_SSE200: + goto bad_offset; + case ARMSSE_SSE300: + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PDCM_PD_CPU0_SENSE unimplemented\= n"); + s->pdcm_pd_cpu0_sense =3D value; + break; + default: + g_assert_not_reached(); + } + break; case A_PDCM_PD_SRAM0_SENSE: switch (s->sse_version) { case ARMSSE_IOTKIT: @@ -562,6 +599,8 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, "IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented= \n"); s->pdcm_pd_sram0_sense =3D value; break; + case ARMSSE_SSE300: + goto bad_offset; default: g_assert_not_reached(); } @@ -575,6 +614,8 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, "IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented= \n"); s->pdcm_pd_sram1_sense =3D value; break; + case ARMSSE_SSE300: + goto bad_offset; default: g_assert_not_reached(); } @@ -588,6 +629,11 @@ static void iotkit_sysctl_write(void *opaque, hwaddr o= ffset, "IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented= \n"); s->pdcm_pd_sram2_sense =3D value; break; + case ARMSSE_SSE300: + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PDCM_PD_VMR0_SENSE unimplemented\= n"); + s->pdcm_pd_vmr0_sense =3D value; + break; default: g_assert_not_reached(); } @@ -601,6 +647,11 @@ static void iotkit_sysctl_write(void *opaque, hwaddr o= ffset, "IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented= \n"); s->pdcm_pd_sram3_sense =3D value; break; + case ARMSSE_SSE300: + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PDCM_PD_VMR1_SENSE unimplemented\= n"); + s->pdcm_pd_vmr1_sense =3D value; + break; default: g_assert_not_reached(); } @@ -672,6 +723,9 @@ static void iotkit_sysctl_reset(DeviceState *dev) s->pdcm_pd_sram1_sense =3D 0; s->pdcm_pd_sram2_sense =3D 0; s->pdcm_pd_sram3_sense =3D 0; + s->pdcm_pd_cpu0_sense =3D 0; + s->pdcm_pd_vmr0_sense =3D 0; + s->pdcm_pd_vmr1_sense =3D 0; } =20 static void iotkit_sysctl_init(Object *obj) @@ -708,6 +762,9 @@ static const VMStateDescription iotkit_sysctl_sse300_vm= state =3D { .needed =3D sse300_needed, .fields =3D (VMStateField[]) { VMSTATE_UINT32(pwrctrl, IoTKitSysCtl), + VMSTATE_UINT32(pdcm_pd_cpu0_sense, IoTKitSysCtl), + VMSTATE_UINT32(pdcm_pd_vmr0_sense, IoTKitSysCtl), + VMSTATE_UINT32(pdcm_pd_vmr1_sense, IoTKitSysCtl), VMSTATE_END_OF_LIST() } }; --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613746933; cv=none; d=zohomail.com; s=zohoarc; b=alw3OXsJju7pIqHEZ1Zkjm1TuvV1KW5DZMHGLnmpxeWI0ZLI2XTnzHXB6/QMiqHMq/LVBkerTYAHkJxGlXuVr+7d9JNk8LUWDyr6FNABqDvejPSWMmorZGNif0uZZOKD9zBg1/UuSP5Gql7oPhHcmyHAr4Pm90N4ZHgntfCBTKw= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=x3QvCng870R2M1an25U0lcsqU4U17wJtXVQiS6BwppM=; b=vBhO5lyBNpcCE87gGkko+ZNIF+1sjB0gHhXKhgSn5LTNk+Ihz/ohrw5KHq5vu2iTMf fOCcJ5jVHVtJV47skJ2C8rQbb8AOu/a0ulSbF9ArxGh3LQJmbUYrO5yl5jtyi/GMSEX4 SZ6o6ZZWBoOOYmBmqv21TsyVn4PJLEMUT0GR2YHpqDMldfFTbJfKclsFs7ZvCjEwphoG n8NagR1+t3IzOqWqwSh5wiG844tEybXlZxAvDmtVvr3lVJx52uLWKsf/+MyLcHjM289k i/2ZkTDgWBOPcPmxpiLT5abolop36Anx7ZnZCYaDSEcCSHCZQMWEZGNGPxpkOFqhbTzb OxTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x3QvCng870R2M1an25U0lcsqU4U17wJtXVQiS6BwppM=; b=ikTcBnm2V57TQjU/tYmgBI+rEKn/JGi9Ikbom3SP3upeewaixGMB37UNKcRoZa5MSV B3+q7+dfQQ9XADlEKGvS4LBRNrIej8sHMA9532Cmo/Yz+YVChMADQ4myAbNhsqeBCEyf IFKMToL4UiCHax+YGG9T3xHxEPYUdnjm/aePCf17RGeJUGj0g/uWBPkQq50WMX3s3mLG XkGjjVXxHe3Yb/7jITqd2VwPX0LYwzuOAUpyin3ItCyVChYiRw7x2hNqPcuCSlks19vZ aw0OhCx1P7XkgN7S7Tb8RlqzGQqisjlkvIM8v7bXP5rpnF6+BJoFpOzq+9SFAS8uiLhj AQFQ== X-Gm-Message-State: AOAM531/QgtaQ/w/gHOFAqVoQ4kCkNHUgN4A/4RgrjG3eXtDCBFg64Vo 5sZ64yHq3we3gNhS6+efG4WILhjuPLiUAg== X-Google-Smtp-Source: ABdhPJxHUbpQyYAKEIu4rZya5kN27ZxgHP2ARqIOEzEvOjo6IMukYIm32mEDhje64xtV4INHcEmvIQ== X-Received: by 2002:a1c:7e4e:: with SMTP id z75mr8597480wmc.168.1613745994121; Fri, 19 Feb 2021 06:46:34 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 18/44] hw/misc/iotkit-sysctl: Implement SSE-200 and SSE-300 PID register values Date: Fri, 19 Feb 2021 14:45:51 +0000 Message-Id: <20210219144617.4782-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The SSE-200 and SSE-300 have different PID register values from the IoTKit for the sysctl register block. We incorrectly implemented the SSE-200 with the same PID values as IoTKit. Fix the SSE-200 bug and report these register values for SSE-300. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/iotkit-sysctl.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index a80f68b7995..54d6b6c165c 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -74,12 +74,19 @@ REG32(CID2, 0xff8) REG32(CID3, 0xffc) =20 /* PID/CID values */ -static const int sysctl_id[] =3D { +static const int iotkit_sysctl_id[] =3D { 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ 0x54, 0xb8, 0x0b, 0x00, /* PID0..PID3 */ 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ }; =20 +/* Also used by the SSE300 */ +static const int sse200_sysctl_id[] =3D { + 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ + 0x54, 0xb8, 0x1b, 0x00, /* PID0..PID3 */ + 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ +}; + /* * Set the initial secure vector table offset address for the core. * This will take effect when the CPU next resets. @@ -327,7 +334,17 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwadd= r offset, } break; case A_PID4 ... A_CID3: - r =3D sysctl_id[(offset - A_PID4) / 4]; + switch (s->sse_version) { + case ARMSSE_IOTKIT: + r =3D iotkit_sysctl_id[(offset - A_PID4) / 4]; + break; + case ARMSSE_SSE200: + case ARMSSE_SSE300: + r =3D sse200_sysctl_id[(offset - A_PID4) / 4]; + break; + default: + g_assert_not_reached(); + } break; case A_SECDBGSET: case A_SECDBGCLR: --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613747114987725.973958420426; Fri, 19 Feb 2021 07:05:14 -0800 (PST) Received: from localhost ([::1]:50226 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7LF-0007GI-G5 for importer@patchew.org; Fri, 19 Feb 2021 10:05:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34018) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73d-0002Sv-E8 for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:01 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:38708) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73E-0003Wc-8l for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:01 -0500 Received: by mail-wm1-x331.google.com with SMTP id x4so7881786wmi.3 for ; Fri, 19 Feb 2021 06:46:35 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LBypvgOw6fm7qnIXg35YZ3arVZ+jYOMAMlK4mBsw2Ys=; b=kxr/SdlydYAojHtL4F9wtQKTtQsLQH589tOfhDQueOiCAhKw6TOVVGxvvjHtiOl/ul /GYQusT4i74aMfYzIcFBVOFfHtlBmlo4eHUByJPb7wZ66XA0cR3g22ZQcp1M9nE+dWWp dl1PndOKMYXOfYZB5fm6c5k6djsOox8lZhJAa4uICh7NhEjzEKU0frq6VfMB8ZKImapl L5d0HflBVjqO2rxTxE5k0g5BGCPYQa6K8BUtdt+AwOosaQagDisXq0sfNWZoXKAc47K3 hqPSYiDwxc1lNX2FMrqU+F0Zl4mH1izrattVGZVi+XSFHXQFtCkKERVEh/qiZ9y+/Bil 08CA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LBypvgOw6fm7qnIXg35YZ3arVZ+jYOMAMlK4mBsw2Ys=; b=atU6GmWT16WPbytpqvJEgUPP/4yB0syALByAusFOhrrsYwxflpwNDSi22dhTOmuDrw +vz6P5wl8L8aWSWpAKdM1xl+IJlWWiUAainjTPcJrPNZMK63F29nJlg/ZlPxCWp4GWE2 SxkGq4XicuNp/XlYm5btvB5acub0NYpHU2CMyu3WC2um9MtyblvT7UCSiWmXC/nyeRTe wY/VRYMwfQn9ME7N9OUZjRHq2wKNkogcvhF6UlSYVp+dbE1QvMgZaXYlLSAwsIcCeqYU YJBLvztu4Al0kH0KMDZOGFEy7IgFmMfu7LLhuWafZAVWZ8RO5haoaVZURD48aT6HfA63 W5Mw== X-Gm-Message-State: AOAM533TSdJde08szUUJE86meg+xHMmO/EJzD2+NsYNwK45f+2fej77u 1IanR06YKBn3mQ5k352GjynuT9iwCLq32w== X-Google-Smtp-Source: ABdhPJxvLe9oV3jdxZRUCsgmXRpmIBFvKMnyPn7RSps/j93UcS8QhuNX24x5gXlpYf40cUQbASixfw== X-Received: by 2002:a7b:ce95:: with SMTP id q21mr8497047wmj.178.1613745994743; Fri, 19 Feb 2021 06:46:34 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 19/44] hw/arm/Kconfig: Move ARMSSE_CPUID and ARMSSE_MHU stanzas to hw/misc Date: Fri, 19 Feb 2021 14:45:52 +0000 Message-Id: <20210219144617.4782-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The ARMSSE_CPUID and ARMSSE_MHU Kconfig stanzas are for the devices implmemented by hw/misc/cpuid.c and hw/misc/armsse-mhu.c. Move them to hw/misc/Kconfig where they belong. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/Kconfig | 6 ------ hw/misc/Kconfig | 6 ++++++ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index ed007267a91..0492b212840 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -521,9 +521,3 @@ config ARMSSE select UNIMP select SSE_COUNTER select SSE_TIMER - -config ARMSSE_CPUID - bool - -config ARMSSE_MHU - bool diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 19c216f3efb..16b96e4dafb 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -2,6 +2,12 @@ config APPLESMC bool depends on ISA_BUS =20 +config ARMSSE_CPUID + bool + +config ARMSSE_MHU + bool + config MAX111X bool =20 --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613747138; cv=none; d=zohomail.com; s=zohoarc; b=LJ3Pu4XDpx0ewYv3cYSSeYTNtfOpuJTCGHACj5Jeht8Jl8AkHjmzknm1zuEpd03AFwS19QFFoj/x5bBNxhFuN4pQtdjsYx0FNg6ntPLr7+tcgeRRyEtMOtbgLMYekGdKW1Z0RJ6DDqVtTkLiE0TOXxlb2lBjFTn8/Du6QYMJmL8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613747138; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ly8Hfh+bGC0RsxpfK2YgK2rysdFpN5/sB98Zuud8DvM=; b=IZq3IW+pOGQWInyrkNldYk4j+/rzelyLBDelz5Yxf1tpoaWGHxEHJbzqfcOZulgnpYrEINId2haf3IuYn/l7a/08HX9sgJ9xzerzHXDC3jeOqIo65pe08Xk7W8oPlIOPa3GYrwbmJiyuJRBFLEnUmupE0YW9qlZG+N0PHOVLlmI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161374713792878.85022729054549; Fri, 19 Feb 2021 07:05:37 -0800 (PST) Received: from localhost ([::1]:52198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7Lc-00083p-N2 for importer@patchew.org; Fri, 19 Feb 2021 10:05:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33996) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73c-0002Sq-BH for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:01 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:42116) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73F-0003XR-UT for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:00 -0500 Received: by mail-wr1-x42c.google.com with SMTP id r21so8867241wrr.9 for ; Fri, 19 Feb 2021 06:46:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Ly8Hfh+bGC0RsxpfK2YgK2rysdFpN5/sB98Zuud8DvM=; b=EBOBvwNYl9RDoN0eLLZIQwfwff01g9M+Fl2I06FHAXg/caIfsw9oLu9liS6oVAj4A6 Jl5IVAnd9SGf+/PhmWxzYlr5JRYGLnNkycwumuSSUsUiLAvffq2cyeZ2sg3AmWgyBABi Mx5qnvKMDpUqlJlirYCal8QqRfYsifUNe+tRe4hb2qtohPHfSf9OPJBhIvPsKxX2cUaL m6W3iq3EboYBFQHg82865XqM+eh4kEerwZh9iDskElel9xFrws4gGYxz1NXZIbffKnr7 6EWvdq0jkEYMfxxOqQKfvPSuDPIyq5omDUy8Es6vsKB3V59SbUev4wGQa4SCZ6rLGL9v Sdzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ly8Hfh+bGC0RsxpfK2YgK2rysdFpN5/sB98Zuud8DvM=; b=LI3SG1vrqCBY1JghgXQIOhZRF/djSrbNvBfnaWd6xPy74AorN/SPU4pFaZP+0FdiuS hGl4RRaWRE8trciVKIbpfG18xVhnsHkx+HXdv6vbjQd70TOj14jgsCbt8d9up0AtTw5k TQt+grCqLeMszcpoXm6GVTDgnXjJ0dxCrO4Md/A9bHu14rTahqiR4TzatpUhIIBQZmwr RlgwRIjREJgcn7H0vJVUdZ8FmrD7DEMsnVxhn6S55MbaLz8qg/BVU3O3lwim2+/yhjvG tiR4OMMF52yfU/pW+c754prE2Zn24HKsaD5rHW2/NlqJeT63mrrWL5BUAH5rdQYf19Xy 0WnA== X-Gm-Message-State: AOAM531RXrWjUV+nzHcutACrLgfPhnMimFfQS7IMJhi1u9rk5/wRyXGZ qFaf3Ph7v6vXJggDSP4OEakqljIAFBmZYg== X-Google-Smtp-Source: ABdhPJy5x4UPKbgTJg9UTk/oiOn5Eq4h2eaK54yjwbiZJbOdP3cm9txAjc6rM5FSVsI3iTeO1XbbJg== X-Received: by 2002:a5d:698d:: with SMTP id g13mr9674333wru.30.1613745995560; Fri, 19 Feb 2021 06:46:35 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 20/44] hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU_PWRCTRL register block Date: Fri, 19 Feb 2021 14:45:53 +0000 Message-Id: <20210219144617.4782-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The SSE-300 has a new register block CPU_PWRCTRL. There is one instance of this per CPU in the system (so just one for the SSE-300), and as well as the usual CIDR/PIDR ID registers it has just one register, CPUPWRCFG. This register allows the guest to configure behaviour of the system in power-down and deep-sleep states. Since QEMU does not model those, we make the register a dummy reads-as-written implementation. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/armsse-cpu-pwrctrl.h | 40 +++++++ hw/misc/armsse-cpu-pwrctrl.c | 149 +++++++++++++++++++++++++++ MAINTAINERS | 2 + hw/arm/Kconfig | 1 + hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/trace-events | 4 + 7 files changed, 200 insertions(+) create mode 100644 include/hw/misc/armsse-cpu-pwrctrl.h create mode 100644 hw/misc/armsse-cpu-pwrctrl.c diff --git a/include/hw/misc/armsse-cpu-pwrctrl.h b/include/hw/misc/armsse-= cpu-pwrctrl.h new file mode 100644 index 00000000000..51d45ede7db --- /dev/null +++ b/include/hw/misc/armsse-cpu-pwrctrl.h @@ -0,0 +1,40 @@ +/* + * ARM SSE CPU PWRCTRL register block + * + * Copyright (c) 2021 Linaro Limited + * Written by Peter Maydell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +/* + * This is a model of the "CPU_PWRCTRL block" which is part of the + * Arm Corstone SSE-300 Example Subsystem and documented in + * https://developer.arm.com/documentation/101773/0000 + * + * QEMU interface: + * + sysbus MMIO region 0: the register bank + */ + +#ifndef HW_MISC_ARMSSE_CPU_PWRCTRL_H +#define HW_MISC_ARMSSE_CPU_PWRCTRL_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +#define TYPE_ARMSSE_CPU_PWRCTRL "armsse-cpu-pwrctrl" +OBJECT_DECLARE_SIMPLE_TYPE(ARMSSECPUPwrCtrl, ARMSSE_CPU_PWRCTRL) + +struct ARMSSECPUPwrCtrl { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; + + uint32_t cpupwrcfg; +}; + +#endif diff --git a/hw/misc/armsse-cpu-pwrctrl.c b/hw/misc/armsse-cpu-pwrctrl.c new file mode 100644 index 00000000000..42fc38879f2 --- /dev/null +++ b/hw/misc/armsse-cpu-pwrctrl.c @@ -0,0 +1,149 @@ +/* + * Arm SSE CPU PWRCTRL register block + * + * Copyright (c) 2021 Linaro Limited + * Written by Peter Maydell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +/* + * This is a model of the "CPU_PWRCTRL block" which is part of the + * Arm Corstone SSE-300 Example Subsystem and documented in + * https://developer.arm.com/documentation/101773/0000 + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "trace.h" +#include "qapi/error.h" +#include "migration/vmstate.h" +#include "hw/sysbus.h" +#include "hw/registerfields.h" +#include "hw/misc/armsse-cpu-pwrctrl.h" + +REG32(CPUPWRCFG, 0x0) +REG32(PID4, 0xfd0) +REG32(PID5, 0xfd4) +REG32(PID6, 0xfd8) +REG32(PID7, 0xfdc) +REG32(PID0, 0xfe0) +REG32(PID1, 0xfe4) +REG32(PID2, 0xfe8) +REG32(PID3, 0xfec) +REG32(CID0, 0xff0) +REG32(CID1, 0xff4) +REG32(CID2, 0xff8) +REG32(CID3, 0xffc) + +/* PID/CID values */ +static const int cpu_pwrctrl_id[] =3D { + 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ + 0x5a, 0xb8, 0x0b, 0x00, /* PID0..PID3 */ + 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ +}; + +static uint64_t pwrctrl_read(void *opaque, hwaddr offset, unsigned size) +{ + ARMSSECPUPwrCtrl *s =3D ARMSSE_CPU_PWRCTRL(opaque); + uint64_t r; + + switch (offset) { + case A_CPUPWRCFG: + r =3D s->cpupwrcfg; + break; + case A_PID4 ... A_CID3: + r =3D cpu_pwrctrl_id[(offset - A_PID4) / 4]; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "SSE CPU_PWRCTRL read: bad offset %x\n", (int)offset= ); + r =3D 0; + break; + } + trace_armsse_cpu_pwrctrl_read(offset, r, size); + return r; +} + +static void pwrctrl_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + ARMSSECPUPwrCtrl *s =3D ARMSSE_CPU_PWRCTRL(opaque); + + trace_armsse_cpu_pwrctrl_write(offset, value, size); + + switch (offset) { + case A_CPUPWRCFG: + qemu_log_mask(LOG_UNIMP, + "SSE CPU_PWRCTRL: CPUPWRCFG unimplemented\n"); + s->cpupwrcfg =3D value; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "SSE CPU_PWRCTRL write: bad offset 0x%x\n", (int)off= set); + break; + } +} + +static const MemoryRegionOps pwrctrl_ops =3D { + .read =3D pwrctrl_read, + .write =3D pwrctrl_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static void pwrctrl_reset(DeviceState *dev) +{ + ARMSSECPUPwrCtrl *s =3D ARMSSE_CPU_PWRCTRL(dev); + + s->cpupwrcfg =3D 0; +} + +static const VMStateDescription pwrctrl_vmstate =3D { + .name =3D "armsse-cpu-pwrctrl", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(cpupwrcfg, ARMSSECPUPwrCtrl), + VMSTATE_END_OF_LIST() + }, +}; + +static void pwrctrl_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + ARMSSECPUPwrCtrl *s =3D ARMSSE_CPU_PWRCTRL(obj); + + memory_region_init_io(&s->iomem, obj, &pwrctrl_ops, + s, "armsse-cpu-pwrctrl", 0x1000); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void pwrctrl_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D pwrctrl_reset; + dc->vmsd =3D &pwrctrl_vmstate; +} + +static const TypeInfo pwrctrl_info =3D { + .name =3D TYPE_ARMSSE_CPU_PWRCTRL, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(ARMSSECPUPwrCtrl), + .instance_init =3D pwrctrl_init, + .class_init =3D pwrctrl_class_init, +}; + +static void pwrctrl_register_types(void) +{ + type_register_static(&pwrctrl_info); +} + +type_init(pwrctrl_register_types); diff --git a/MAINTAINERS b/MAINTAINERS index df0eddc7170..c2103b40b9b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -738,6 +738,8 @@ F: hw/misc/iotkit-sysctl.c F: include/hw/misc/iotkit-sysctl.h F: hw/misc/iotkit-sysinfo.c F: include/hw/misc/iotkit-sysinfo.h +F: hw/misc/armsse-cpu-pwrctrl.c +F: include/hw/misc/armsse-cpu-pwrctrl.h F: hw/misc/armsse-cpuid.c F: include/hw/misc/armsse-cpuid.h F: hw/misc/armsse-mhu.c diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 0492b212840..be9adf18594 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -504,6 +504,7 @@ config ARM11MPCORE config ARMSSE bool select ARM_V7M + select ARMSSE_CPU_PWRCTRL select ARMSSE_CPUID select ARMSSE_MHU select CMSDK_APB_TIMER diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 16b96e4dafb..5426b9b1a1a 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -8,6 +8,9 @@ config ARMSSE_CPUID config ARMSSE_MHU bool =20 +config ARMSSE_CPU_PWRCTRL + bool + config MAX111X bool =20 diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 629283957fc..e30a555db5c 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -96,6 +96,7 @@ softmmu_ss.add(when: 'CONFIG_TZ_MSC', if_true: files('tz-= msc.c')) softmmu_ss.add(when: 'CONFIG_TZ_PPC', if_true: files('tz-ppc.c')) softmmu_ss.add(when: 'CONFIG_IOTKIT_SECCTL', if_true: files('iotkit-secctl= .c')) softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSINFO', if_true: files('iotkit-sysin= fo.c')) +softmmu_ss.add(when: 'CONFIG_ARMSSE_CPU_PWRCTRL', if_true: files('armsse-c= pu-pwrctrl.c')) softmmu_ss.add(when: 'CONFIG_ARMSSE_CPUID', if_true: files('armsse-cpuid.c= ')) softmmu_ss.add(when: 'CONFIG_ARMSSE_MHU', if_true: files('armsse-mhu.c')) =20 diff --git a/hw/misc/trace-events b/hw/misc/trace-events index d626b9d7a7c..4b15db8ca48 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -186,6 +186,10 @@ iotkit_sysctl_read(uint64_t offset, uint64_t data, uns= igned size) "IoTKit SysCtl iotkit_sysctl_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit= SysCtl write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" iotkit_sysctl_reset(void) "IoTKit SysCtl: reset" =20 +# armsse-cpu-pwrctrl.c +armsse_cpu_pwrctrl_read(uint64_t offset, uint64_t data, unsigned size) "SS= E-300 CPU_PWRCTRL read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" +armsse_cpu_pwrctrl_write(uint64_t offset, uint64_t data, unsigned size) "S= SE-300 CPU_PWRCTRL write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" + # armsse-cpuid.c armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 = CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200= CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613747076; cv=none; d=zohomail.com; s=zohoarc; b=gLCLqzkfEL1ccEFtOuQfZKDYPkvkyOmOFVEkHLtVhYtWpZDcaX1w1+d8nncDZhTWxCJsadWy5fuC9eGPKmNKmRR4X8QSdcKDyqc6bDuiAjPmTBgZ6YilAwHrkiOmHzGw5AjtixvhJVi5vQ2PNE3fNir6/5AGYGES6pj2tayBO5E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613747076; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=k6oYzYF2kgG/d9iwOF7hKSmrm8saHh/z9DOwOyvSPH0=; b=LqFg7CE5+KeOXIYEvVJuh/hTaP86sL6nLFOe2Q9ZG+5mafSXwQjgrERh3wMtRCIQuivd1mEgH66V+OApp9Dd9UTU/b8jZNcXOpBapJgLM+BSYnQcVTXalPkFVdw8awQKV0IGYiymFYPIzzthw7mOYkJ804JHiXgehZGUp5w7kyY= ARC-Authentication-Results: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=k6oYzYF2kgG/d9iwOF7hKSmrm8saHh/z9DOwOyvSPH0=; b=DMftuM2myTDxw1qjfmpGuaKguePaIEav2ouS648acRzXsfXbIaYEA0414DRyzJiqT0 pasweguRMliH/dPaYNgny7NOQ2HXhj+QjXTz1CS3fJ8AbCfkVyNss2TLSnku8GKSU50v zovw/klcJ5u+PReu2eZSZ/oUGk4ltS/dkO68V2MPbGs/kd2pXVd5LsCUV+mK7o/ieOKU NKQydUOEtHGXGX2+QWs50M1HY+ENL7dzH004zVaShnQBBl6IEYWGCLNX26J8nloj4tJ1 /coT3Iu6T9mqKuihu6iSvuWr6wPG2cA22mfBHH1lhheVhPo7UokPzjTWeH15q+UkEehW eCXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=k6oYzYF2kgG/d9iwOF7hKSmrm8saHh/z9DOwOyvSPH0=; b=EpezlEaKjY9J7td6j5s/sXltl2ceNplXAzZ1QCjAKfDnat1HmtCVYWfabSrM4fdC5W mySbl+l2+FPLW9pgdCKHUMEoejAyJ2ArEs0cT9TstIaaHRiCPaVMiZuOfKvcOlw0oLG7 lZdwQCzw1E3R4GpCVj04bGPh5/2aJhTSSrnx1+cDodFgQLhhY/QxMcagkHAaN7UYvQGx u4AqtYDnJoAZZtvj6DTndSv5pQTCVsURMlumaNTDLEyOydaacMt5/xY/GniKOxaUBcZc 5PsZLaN0f7GC2gQ3F+bxcnskDOtAFfG9hs+Z34AzOmPGGgG/o+KIfSffcDQiloSZHjC3 T71g== X-Gm-Message-State: AOAM533SlZBy5hCrhs7zTD3RPFQqeSD63YJtvaLGAMh+vrbjhN9I3az8 V1507iKVZKIUn+BprYh1/auaj/eqb1hG3w== X-Google-Smtp-Source: ABdhPJzU2ft5uO2NqLTQ5jCL1cCBNGgxQBTEZ/PReE9zWAPOC0pmhJ4NptGMuiJcI1CUzqicxMB8DA== X-Received: by 2002:a5d:4651:: with SMTP id j17mr9333153wrs.64.1613745996238; Fri, 19 Feb 2021 06:46:36 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 21/44] hw/arm/armsse: Use an array for apb_ppc fields in the state structure Date: Fri, 19 Feb 2021 14:45:54 +0000 Message-Id: <20210219144617.4782-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the apb_ppc0 and apb_ppc1 fields in the ARMSSE state struct to use an array instead of two separate fields. We already had one place in the code that wanted to be able to refer to the PPC by index, and we're about to add more code like that. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/armsse.h | 6 +++--- hw/arm/armsse.c | 32 ++++++++++++++++++-------------- 2 files changed, 21 insertions(+), 17 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 09284ca75cf..771150b0a94 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -124,8 +124,9 @@ OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass, /* We have an IRQ splitter and an OR gate input for each external PPC * and the 2 internal PPCs */ +#define NUM_INTERNAL_PPCS 2 #define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC) -#define NUM_PPCS (NUM_EXTERNAL_PPCS + 2) +#define NUM_PPCS (NUM_EXTERNAL_PPCS + NUM_INTERNAL_PPCS) =20 #define MAX_SRAM_BANKS 4 #if MAX_SRAM_BANKS > IOTS_NUM_MPC @@ -152,8 +153,7 @@ struct ARMSSE { ARMv7MState armv7m[SSE_MAX_CPUS]; CPUClusterState cluster[SSE_MAX_CPUS]; IoTKitSecCtl secctl; - TZPPC apb_ppc0; - TZPPC apb_ppc1; + TZPPC apb_ppc[NUM_INTERNAL_PPCS]; TZMPC mpc[IOTS_NUM_MPC]; CMSDKAPBTimer timer0; CMSDKAPBTimer timer1; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 326e161c8d4..2b25fca1ca2 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -291,8 +291,12 @@ static void armsse_init(Object *obj) } =20 object_initialize_child(obj, "secctl", &s->secctl, TYPE_IOTKIT_SECCTL); - object_initialize_child(obj, "apb-ppc0", &s->apb_ppc0, TYPE_TZ_PPC); - object_initialize_child(obj, "apb-ppc1", &s->apb_ppc1, TYPE_TZ_PPC); + + for (i =3D 0; i < ARRAY_SIZE(s->apb_ppc); i++) { + g_autofree char *name =3D g_strdup_printf("apb-ppc%d", i); + object_initialize_child(obj, name, &s->apb_ppc[i], TYPE_TZ_PPC); + } + for (i =3D 0; i < info->sram_banks; i++) { char *name =3D g_strdup_printf("mpc%d", i); object_initialize_child(obj, name, &s->mpc[i], TYPE_TZ_MPC); @@ -739,7 +743,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, armsse_get_common_irq_in(s, 3)); mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); - object_property_set_link(OBJECT(&s->apb_ppc0), "port[0]", OBJECT(mr), + object_property_set_link(OBJECT(&s->apb_ppc[0]), "port[0]", OBJECT(mr), &error_abort); =20 qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk); @@ -749,7 +753,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, armsse_get_common_irq_in(s, 4)); mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); - object_property_set_link(OBJECT(&s->apb_ppc0), "port[1]", OBJECT(mr), + object_property_set_link(OBJECT(&s->apb_ppc[0]), "port[1]", OBJECT(mr), &error_abort); =20 qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); @@ -759,7 +763,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->dualtimer), 0, armsse_get_common_irq_in(s, 5)); mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); - object_property_set_link(OBJECT(&s->apb_ppc0), "port[2]", OBJECT(mr), + object_property_set_link(OBJECT(&s->apb_ppc[0]), "port[2]", OBJECT(mr), &error_abort); =20 if (info->has_mhus) { @@ -782,7 +786,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) } port =3D g_strdup_printf("port[%d]", i + 3); mr =3D sysbus_mmio_get_region(mhu_sbd, 0); - object_property_set_link(OBJECT(&s->apb_ppc0), port, OBJECT(mr= ), + object_property_set_link(OBJECT(&s->apb_ppc[0]), port, OBJECT(= mr), &error_abort); g_free(port); =20 @@ -802,12 +806,12 @@ static void armsse_realize(DeviceState *dev, Error **= errp) } } =20 - if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc0), errp)) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[0]), errp)) { return; } =20 - sbd_apb_ppc0 =3D SYS_BUS_DEVICE(&s->apb_ppc0); - dev_apb_ppc0 =3D DEVICE(&s->apb_ppc0); + sbd_apb_ppc0 =3D SYS_BUS_DEVICE(&s->apb_ppc[0]); + dev_apb_ppc0 =3D DEVICE(&s->apb_ppc[0]); =20 mr =3D sysbus_mmio_get_region(sbd_apb_ppc0, 0); memory_region_add_subregion(&s->container, 0x40000000, mr); @@ -917,16 +921,16 @@ static void armsse_realize(DeviceState *dev, Error **= errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32ktimer), 0, armsse_get_common_irq_in(s, 2)); mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); - object_property_set_link(OBJECT(&s->apb_ppc1), "port[0]", OBJECT(mr), + object_property_set_link(OBJECT(&s->apb_ppc[1]), "port[0]", OBJECT(mr), &error_abort); =20 - if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc1), errp)) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[1]), errp)) { return; } - mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc1), 0); + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc[1]), 0); memory_region_add_subregion(&s->container, 0x4002f000, mr); =20 - dev_apb_ppc1 =3D DEVICE(&s->apb_ppc1); + dev_apb_ppc1 =3D DEVICE(&s->apb_ppc[1]); qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, qdev_get_gpio_in_named(dev_apb_ppc1, "cfg_nonsec", 0)); @@ -1063,7 +1067,7 @@ static void armsse_realize(DeviceState *dev, Error **= errp) DeviceState *devs =3D DEVICE(&s->ppc_irq_splitter[i]); char *gpioname =3D g_strdup_printf("apb_ppc%d_irq_status", i - NUM_EXTERNAL_PPCS); - TZPPC *ppc =3D (i =3D=3D NUM_EXTERNAL_PPCS) ? &s->apb_ppc0 : &s->a= pb_ppc1; + TZPPC *ppc =3D &s->apb_ppc[i - NUM_EXTERNAL_PPCS]; =20 qdev_connect_gpio_out(devs, 0, qdev_get_gpio_in_named(dev_secctl, gpioname,= 0)); --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613746909; cv=none; d=zohomail.com; s=zohoarc; b=arY9AbZfd8cuRA6F1hHK8ls5Ddm9+yh8qhtbPd4KDQdkbInpG/oAigOmGzc0NHTXurNMXuOVohWMnrupCWzPn5+2/jrlUa5s/wSy2e5Fz0C1czTaaXuKakltNIwUkLuy8w0JzOJ5e56WoMxwmjym1VDkwf/9SYfLI3+ezOoEr7M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613746909; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=B93kEzuBtL1t+F0ap6ZkJU+6zXhaZkvFeOMgU9Fv5ag=; b=xb5RXO32LLtcLp2ZEaEbv/H84UjoXc+9YGP8Wg4Boe7sysDABcpWkBcaxFxavQNHa8 9W/z+Cx8krcm+CYAlkw3kCBKw/P08a3gMipD2IP2rHG/ryHIwJZm3gXlJN4KXKYMMKjm 7G9SURptTyPW70FgZrRZIuHyDcg0zQ6AUuK4gikR1V1ileJfGMdvkrUtEaYP3SMadS8o KAFeEM367pKOJJRfSXAb96HbSQyem9sl7xr6EE1+b24OjRJgdAwlZ6awGPVImVqL0ehV VoHUPB6hYEC0SCsYIhDD5J0Ar1YrFHHS2DOLZpBbdrNabJ6MQc/YlUWVCMKvFzko8wZy Bn6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B93kEzuBtL1t+F0ap6ZkJU+6zXhaZkvFeOMgU9Fv5ag=; b=gku88wyzSk4bD/3fYYyRT46JvmIdDRr0hg9zbAvL0gAR12a2rHaf1cFtpnlOq9vyfc xWqfzfLDQVQCNZ2RhwDaSIUvph5YXld3pOGQMGpNyTu9PGA0CRpqwbb6paL36buI1MDx oJnvQlRbOmERD38Dehs4YdUA7tQpv0Zi77vmFQjzeuH8yragUpNfJXmfBg6IoBUoC7oD p7C+h2RasZUu5kdd6gxegubezEj/g7ss7NqLcb9MJ+pzHaOmx0XqIIb5OgIbGERyI36t WnThJdfvQUnLzSqtmKUISDNiw3ga7hpkytkuIzrxAnqlmtK5xGT82Tfr4ZC+DrRAiHRB 7Hdw== X-Gm-Message-State: AOAM532tnVToYeowsdTzYP6gevXjpisXlCFm41euOPM8gQTECdqHtjU5 9ExtEZzA8sFHX4N+5Lvbat5agg== X-Google-Smtp-Source: ABdhPJzkgr2kNg7zD+cSuygfAulozV3frunF55BSVsM5mL0wI6n39r3i9cOjD/QMDBunMQvE4ZL4dA== X-Received: by 2002:a1c:41d6:: with SMTP id o205mr8230867wma.80.1613745996892; Fri, 19 Feb 2021 06:46:36 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 22/44] hw/arm/armsse: Add a define for number of IRQs used by the SSE itself Date: Fri, 19 Feb 2021 14:45:55 +0000 Message-Id: <20210219144617.4782-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The SSE uses 32 interrupts for its own devices, and then passes through its expansion IRQ inputs to the CPU's interrupts 33 and upward. Add a define for the number of IRQs the SSE uses for itself, instead of hardcoding 32. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/armsse.h | 5 ++++- hw/arm/armsse.c | 4 ++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 771150b0a94..e34263fed8b 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -145,6 +145,9 @@ OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass, #define RAM3_PPU 6 #define NUM_PPUS 7 =20 +/* Number of CPU IRQs used by the SSE itself */ +#define NUM_SSE_IRQS 32 + struct ARMSSE { /*< private >*/ SysBusDevice parent_obj; @@ -165,7 +168,7 @@ struct ARMSSE { qemu_or_irq mpc_irq_orgate; qemu_or_irq nmi_orgate; =20 - SplitIRQ cpu_irq_splitter[32]; + SplitIRQ cpu_irq_splitter[NUM_SSE_IRQS]; =20 CMSDKAPBDualTimer dualtimer; =20 diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 2b25fca1ca2..5ae6ce344ee 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -531,7 +531,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) int j; char *gpioname; =20 - qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32); + qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + NUM_SSE_IR= QS); /* * In real hardware the initial Secure VTOR is set from the INITSV= TOR* * registers in the IoT Kit System Control Register block. In QEMU @@ -602,7 +602,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and u= p */ s->exp_irqs[i] =3D g_new(qemu_irq, s->exp_numirq); for (j =3D 0; j < s->exp_numirq; j++) { - s->exp_irqs[i][j] =3D qdev_get_gpio_in(cpudev, j + 32); + s->exp_irqs[i][j] =3D qdev_get_gpio_in(cpudev, j + NUM_SSE_IRQ= S); } if (i =3D=3D 0) { gpioname =3D g_strdup("EXP_IRQ"); --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161374739660025.61575026002265; Fri, 19 Feb 2021 07:09:56 -0800 (PST) Received: from localhost ([::1]:37414 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7Pn-0005aL-FK for importer@patchew.org; Fri, 19 Feb 2021 10:09:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34054) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73e-0002Um-Ma for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:03 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:44821) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73H-0003Xu-0T for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:02 -0500 Received: by mail-wr1-x435.google.com with SMTP id h98so4078690wrh.11 for ; Fri, 19 Feb 2021 06:46:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=f+OLBFi/yKY6WGo+QIfxChYXGrVkJ8IkV/uSAJg9oV0=; b=Egjf6rn6YZZnIhWCBOANcxSwCnIp5/iwDkWtP1Mo4P04N3rpVpYpUBxPnaoUmXap8D 5zT8YDVwL6HoVjegWeMjG3NmZT1s3DYBKsWzcvnnhLXU0yOg+3x4KGXvGM3bkoR3F98e liX49+a9FvoQg/7Ot5zLxQk7MR2aQGFi2cdQBYOCtR01BuPnrWqPBI8blN/2JCQAc50Q XkLFAvlOLVLW+rupJnsqcvLtGYZogMgoukzmC4VlDitoLtzjnQo9AWdXAanW4HKyaAwW 5NlyHUkuAcdH9TpE32OhXDj6Z4GIqKCNFyz8N+M7O8Y0XFvZJkNH+TbdNVd4UUVRgohq g7nA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f+OLBFi/yKY6WGo+QIfxChYXGrVkJ8IkV/uSAJg9oV0=; b=j7lW+vDjFBbbTWzqnsMxKdpSjv915gkWuFxrmHMiDx04HZiuD4r3/I2VGLCc/Bgrii G3L5hCprfqiiP6At6mmqrws3iCEQBgTntBoCOAHnBZXgZK72aZ4yqX6LUmJuAa+gpd/b TlSphx/tpWqQ35QQAzQF3CSmV3HWA/mar//ngYc+xaRb32vv3l3ErNibaiw/vjXeySZk ZVmhLN3wCLlSqcZXgOr7viu3LnMLhqn47sr2D0HxX6awyjivncWacMgCVDjsgVEcc4tv +P2MIXMHFP6+pA4tAZWIPMjChNTfQvfhosbYtaJrZn9oF6/i+ZUrKIaJqL9H9qzE6XNU UYcA== X-Gm-Message-State: AOAM532Q0dG1jzSr1OwJ2pZZu5+V/froU9kDqMIducHwEbeRdgfQEIth xFoAIVY8uVNW3PyzoIc5HTDLOg== X-Google-Smtp-Source: ABdhPJxDSqJizkhVu4opJimx1gY7S1OlFPah2QnQUhw9Bgs27dl35uocIOqwQqIscvXvcP/odKODKg== X-Received: by 2002:a05:6000:1546:: with SMTP id 6mr9485506wry.398.1613745997670; Fri, 19 Feb 2021 06:46:37 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 23/44] hw/arm/armsse: Add framework for data-driven device placement Date: Fri, 19 Feb 2021 14:45:56 +0000 Message-Id: <20210219144617.4782-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The SSE-300 is mostly the same as the SSE-200, but it has moved some of the devices in the memory map and uses different device types in some cases. To accommodate this, add a framework where the placement and wiring of some devices can be specified in a data table. This commit adds the framework for this data-driven device placement, and makes the CMSDK APB timer devices use it. Subsequent commits will convert the other devices which differ between SSE-200 and SSE-300. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/armsse.h | 3 +- hw/arm/armsse.c | 147 +++++++++++++++++++++++++++++++++------- 2 files changed, 125 insertions(+), 25 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index e34263fed8b..c1f4df295a4 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -158,8 +158,7 @@ struct ARMSSE { IoTKitSecCtl secctl; TZPPC apb_ppc[NUM_INTERNAL_PPCS]; TZMPC mpc[IOTS_NUM_MPC]; - CMSDKAPBTimer timer0; - CMSDKAPBTimer timer1; + CMSDKAPBTimer timer[2]; CMSDKAPBTimer s32ktimer; qemu_or_irq ppc_irq_orgate; SplitIRQ sec_resp_splitter; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 5ae6ce344ee..22dd437a4ba 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -24,6 +24,27 @@ #include "hw/irq.h" #include "hw/qdev-clock.h" =20 +/* + * The SSE-300 puts some devices in different places to the + * SSE-200 (and original IoTKit). We use an array of these structs + * to define how each variant lays out these devices. (Parts of the + * SoC that are the same for all variants aren't handled via these + * data structures.) + */ + +#define NO_IRQ -1 +#define NO_PPC -1 + +typedef struct ARMSSEDeviceInfo { + const char *name; /* name to use for the QOM object; NULL terminates l= ist */ + const char *type; /* QOM type name */ + unsigned int index; /* Which of the N devices of this type is this ? */ + hwaddr addr; + int ppc; /* Index of APB PPC this device is wired up to, or NO_PPC */ + int ppc_port; /* Port number of this device on the PPC */ + int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1 */ +} ARMSSEDeviceInfo; + struct ARMSSEInfo { const char *name; uint32_t sse_version; @@ -38,6 +59,7 @@ struct ARMSSEInfo { bool has_cpusecctrl; bool has_cpuid; Property *props; + const ARMSSEDeviceInfo *devinfo; }; =20 static Property iotkit_properties[] =3D { @@ -64,6 +86,30 @@ static Property armsse_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +static const ARMSSEDeviceInfo sse200_devices[] =3D { + { + .name =3D "timer0", + .type =3D TYPE_CMSDK_APB_TIMER, + .index =3D 0, + .addr =3D 0x40000000, + .ppc =3D 0, + .ppc_port =3D 0, + .irq =3D 3, + }, + { + .name =3D "timer1", + .type =3D TYPE_CMSDK_APB_TIMER, + .index =3D 1, + .addr =3D 0x40001000, + .ppc =3D 0, + .ppc_port =3D 1, + .irq =3D 4, + }, + { + .name =3D NULL, + } +}; + static const ARMSSEInfo armsse_variants[] =3D { { .name =3D TYPE_IOTKIT, @@ -79,6 +125,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cpusecctrl =3D false, .has_cpuid =3D false, .props =3D iotkit_properties, + .devinfo =3D sse200_devices, }, { .name =3D TYPE_SSE200, @@ -94,6 +141,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cpusecctrl =3D true, .has_cpuid =3D true, .props =3D armsse_properties, + .devinfo =3D sse200_devices, }, }; =20 @@ -250,6 +298,7 @@ static void armsse_init(Object *obj) ARMSSE *s =3D ARM_SSE(obj); ARMSSEClass *asc =3D ARM_SSE_GET_CLASS(obj); const ARMSSEInfo *info =3D asc->info; + const ARMSSEDeviceInfo *devinfo; int i; =20 assert(info->sram_banks <=3D MAX_SRAM_BANKS); @@ -290,6 +339,18 @@ static void armsse_init(Object *obj) } } =20 + for (devinfo =3D info->devinfo; devinfo->name; devinfo++) { + assert(devinfo->ppc =3D=3D NO_PPC || devinfo->ppc < ARRAY_SIZE(s->= apb_ppc)); + if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) { + assert(devinfo->index < ARRAY_SIZE(s->timer)); + object_initialize_child(obj, devinfo->name, + &s->timer[devinfo->index], + TYPE_CMSDK_APB_TIMER); + } else { + g_assert_not_reached(); + } + } + object_initialize_child(obj, "secctl", &s->secctl, TYPE_IOTKIT_SECCTL); =20 for (i =3D 0; i < ARRAY_SIZE(s->apb_ppc); i++) { @@ -312,8 +373,6 @@ static void armsse_init(Object *obj) object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); g_free(name); } - object_initialize_child(obj, "timer0", &s->timer0, TYPE_CMSDK_APB_TIME= R); - object_initialize_child(obj, "timer1", &s->timer1, TYPE_CMSDK_APB_TIME= R); object_initialize_child(obj, "s32ktimer", &s->s32ktimer, TYPE_CMSDK_APB_TIMER); object_initialize_child(obj, "dualtimer", &s->dualtimer, @@ -453,6 +512,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) ARMSSE *s =3D ARM_SSE(dev); ARMSSEClass *asc =3D ARM_SSE_GET_CLASS(dev); const ARMSSEInfo *info =3D asc->info; + const ARMSSEDeviceInfo *devinfo; int i; MemoryRegion *mr; Error *err =3D NULL; @@ -736,25 +796,53 @@ static void armsse_realize(DeviceState *dev, Error **= errp) * it to the appropriate PPC port; then we can realize the PPC and * map its upstream ends to the right place in the container. */ - qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) { - return; - } - sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, - armsse_get_common_irq_in(s, 3)); - mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); - object_property_set_link(OBJECT(&s->apb_ppc[0]), "port[0]", OBJECT(mr), - &error_abort); + for (devinfo =3D info->devinfo; devinfo->name; devinfo++) { + SysBusDevice *sbd; + qemu_irq irq; =20 - qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) { - return; + if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) { + sbd =3D SYS_BUS_DEVICE(&s->timer[devinfo->index]); + + qdev_connect_clock_in(DEVICE(sbd), "pclk", s->mainclk); + if (!sysbus_realize(sbd, errp)) { + return; + } + mr =3D sysbus_mmio_get_region(sbd, 0); + } else { + g_assert_not_reached(); + } + + switch (devinfo->irq) { + case NO_IRQ: + irq =3D NULL; + break; + case 0 ... NUM_SSE_IRQS - 1: + irq =3D armsse_get_common_irq_in(s, devinfo->irq); + break; + default: + g_assert_not_reached(); + } + + if (irq) { + sysbus_connect_irq(sbd, 0, irq); + } + + /* + * Devices connected to a PPC are connected to the port here; + * we will map the upstream end of that port to the right address + * in the container later after the PPC has been realized. + * Devices not connected to a PPC can be mapped immediately. + */ + if (devinfo->ppc !=3D NO_PPC) { + TZPPC *ppc =3D &s->apb_ppc[devinfo->ppc]; + g_autofree char *portname =3D g_strdup_printf("port[%d]", + devinfo->ppc_port); + object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), + &error_abort); + } else { + memory_region_add_subregion(&s->container, devinfo->addr, mr); + } } - sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, - armsse_get_common_irq_in(s, 4)); - mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); - object_property_set_link(OBJECT(&s->apb_ppc[0]), "port[1]", OBJECT(mr), - &error_abort); =20 qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { @@ -813,10 +901,6 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) sbd_apb_ppc0 =3D SYS_BUS_DEVICE(&s->apb_ppc[0]); dev_apb_ppc0 =3D DEVICE(&s->apb_ppc[0]); =20 - mr =3D sysbus_mmio_get_region(sbd_apb_ppc0, 0); - memory_region_add_subregion(&s->container, 0x40000000, mr); - mr =3D sysbus_mmio_get_region(sbd_apb_ppc0, 1); - memory_region_add_subregion(&s->container, 0x40001000, mr); mr =3D sysbus_mmio_get_region(sbd_apb_ppc0, 2); memory_region_add_subregion(&s->container, 0x40002000, mr); if (info->has_mhus) { @@ -947,6 +1031,23 @@ static void armsse_realize(DeviceState *dev, Error **= errp) qdev_get_gpio_in_named(dev_apb_ppc1, "cfg_sec_resp", 0)); =20 + /* + * Now both PPCs are realized we can map the upstream ends of + * ports which correspond to entries in the devinfo array. + * The ports which are connected to non-devinfo devices have + * already been mapped. + */ + for (devinfo =3D info->devinfo; devinfo->name; devinfo++) { + SysBusDevice *ppc_sbd; + + if (devinfo->ppc =3D=3D NO_PPC) { + continue; + } + ppc_sbd =3D SYS_BUS_DEVICE(&s->apb_ppc[devinfo->ppc]); + mr =3D sysbus_mmio_get_region(ppc_sbd, devinfo->ppc_port); + memory_region_add_subregion(&s->container, devinfo->addr, mr); + } + if (!object_property_set_int(OBJECT(&s->sysinfo), "SYS_VERSION", info->sys_version, errp)) { return; --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613747563; cv=none; d=zohomail.com; s=zohoarc; b=XMIXBf2kTKWpDVDlkemn+CzALeVNqrGGAnAGze7jblzOwj0OUsATa2FoDXHJ4Uvws7Jgrx2JipYjhAOZ2syUktrDbZQo1RGt+qKlTkeYHClEgB7AvSvjcH5gvm2hr8KkijaR2b21sdgh+BvjKWs6XFwSI6+flNvF/TSGzVlcLqI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613747563; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QkE/LCPztd/fooCg8iFxYM64YiAVSgQbEacYkK19vlo=; b=Qkx/iRck/cudyIUnNS5CqPma71ORtYatNWVXOA39YQTbsOF9Zzh2H8Ug7490iQqOdSRyioAWBjRv/AQt1JMQCU+wiofQ/mLHeXo17VtE4ZDQv/SnDI6xC/caPFWrVyWl2JUEXtwLJb14pVcXF4denPP9w7qS88sJsPqVs5mECY8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613747562606546.5689067054568; Fri, 19 Feb 2021 07:12:42 -0800 (PST) Received: from localhost ([::1]:46246 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7ST-0001OX-G6 for importer@patchew.org; Fri, 19 Feb 2021 10:12:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34064) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73f-0002Uo-2x for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:03 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:40717) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73H-0003Yj-Rq for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:02 -0500 Received: by mail-wr1-x42b.google.com with SMTP id v14so8881255wro.7 for ; Fri, 19 Feb 2021 06:46:39 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=QkE/LCPztd/fooCg8iFxYM64YiAVSgQbEacYkK19vlo=; b=JTrPe5Rzhf6K1cS3Ld+lwMBTyH5JUVWBN5nU675gtdDsjlVcsaVnFs0yNwa/XNt9cE OhI1cktUN+0WCno2LQdcX7cnD6BRQ2enMA+AAP0hO3CYcAyRKLn/rZ015lqAEW5SIE7k R696/FR54wH9OPsHzPJbdi5/hwFjvU5ezw01egGC3GmVmuj6OpU0Okk5HUjWztXzVcqW oIpMYRgecyiQIMWRpOGe4MB9ySpeaLm1EVx1mpFaqcmtqpu0prOwGp5O6vtVtqJEN9nV Zg5Kl0lvJtxR8X8HrMzAwG80gfywP//fMZePN6mUq+hxgiWDOimuqH3VWr2e3h7iq9t8 1TXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QkE/LCPztd/fooCg8iFxYM64YiAVSgQbEacYkK19vlo=; b=QsDixWzJ3IYcV/j+i2Oj0QSBLRb8bTl4qzG5be3qqcaNoFAiiDwCZXxK5qZ7hkO1Ue c3vnqHfXjHnDPQ9JCzq8LLTDN4A4ht7QVxG32ppWUsg6tQrlzHh3bmz5P4e2rUkkzzUB eT8RVMjGuZEoy3+LyuqMMCmzMOkI77jmSFyhXZ3SN1xsU6EoojqAmXT6YiWszSJ53bAv 3Hn+QqYX8B2dhuZcif/0DsSaekBzC1169qEm3lDlSVq197o5x+15ACXem0QukTyIdjls yq12Iho+7dDF2ydfsJUn6JVFXdnKvaEtUVLufGverAkUtz4ZCkGec3i07x7ONLu6rnof tvUQ== X-Gm-Message-State: AOAM532QifcIn38KKSWSiW9Q7t6lAgxb97RJG46GelGfGO6upXtJgnXl aNNC5v35mo7m56QfVyuSDSF9kg== X-Google-Smtp-Source: ABdhPJw5R9JtlOzlLjgLE1sPYw2rb4sQrbj1iCoDHHjtqCfbUzPVFDox/3JNyRCTr4ftlk2Y0j5dHA== X-Received: by 2002:adf:fb51:: with SMTP id c17mr9774198wrs.145.1613745998361; Fri, 19 Feb 2021 06:46:38 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 24/44] hw/arm/armsse: Move dual-timer device into data-driven framework Date: Fri, 19 Feb 2021 14:45:57 +0000 Message-Id: <20210219144617.4782-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Move the CMSDK dualtimer device handling into the data-driven device placement framework. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/armsse.c | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 22dd437a4ba..f8da7fb00f9 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -105,6 +105,15 @@ static const ARMSSEDeviceInfo sse200_devices[] =3D { .ppc_port =3D 1, .irq =3D 4, }, + { + .name =3D "dualtimer", + .type =3D TYPE_CMSDK_APB_DUALTIMER, + .index =3D 0, + .addr =3D 0x40002000, + .ppc =3D 0, + .ppc_port =3D 2, + .irq =3D 5, + }, { .name =3D NULL, } @@ -346,6 +355,10 @@ static void armsse_init(Object *obj) object_initialize_child(obj, devinfo->name, &s->timer[devinfo->index], TYPE_CMSDK_APB_TIMER); + } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_DUALTIMER)) { + assert(devinfo->index =3D=3D 0); + object_initialize_child(obj, devinfo->name, &s->dualtimer, + TYPE_CMSDK_APB_DUALTIMER); } else { g_assert_not_reached(); } @@ -375,8 +388,6 @@ static void armsse_init(Object *obj) } object_initialize_child(obj, "s32ktimer", &s->s32ktimer, TYPE_CMSDK_APB_TIMER); - object_initialize_child(obj, "dualtimer", &s->dualtimer, - TYPE_CMSDK_APB_DUALTIMER); object_initialize_child(obj, "s32kwatchdog", &s->s32kwatchdog, TYPE_CMSDK_APB_WATCHDOG); object_initialize_child(obj, "nswatchdog", &s->nswatchdog, @@ -808,6 +819,14 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) return; } mr =3D sysbus_mmio_get_region(sbd, 0); + } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_DUALTIMER)) { + sbd =3D SYS_BUS_DEVICE(&s->dualtimer); + + qdev_connect_clock_in(DEVICE(sbd), "TIMCLK", s->mainclk); + if (!sysbus_realize(sbd, errp)) { + return; + } + mr =3D sysbus_mmio_get_region(sbd, 0); } else { g_assert_not_reached(); } @@ -844,16 +863,6 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) } } =20 - qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { - return; - } - sysbus_connect_irq(SYS_BUS_DEVICE(&s->dualtimer), 0, - armsse_get_common_irq_in(s, 5)); - mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); - object_property_set_link(OBJECT(&s->apb_ppc[0]), "port[2]", OBJECT(mr), - &error_abort); - if (info->has_mhus) { /* * An SSE-200 with only one CPU should have only one MHU created, @@ -901,8 +910,6 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) sbd_apb_ppc0 =3D SYS_BUS_DEVICE(&s->apb_ppc[0]); dev_apb_ppc0 =3D DEVICE(&s->apb_ppc[0]); =20 - mr =3D sysbus_mmio_get_region(sbd_apb_ppc0, 2); - memory_region_add_subregion(&s->container, 0x40002000, mr); if (info->has_mhus) { mr =3D sysbus_mmio_get_region(sbd_apb_ppc0, 3); memory_region_add_subregion(&s->container, 0x40003000, mr); --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613747285786475.30556425689144; Fri, 19 Feb 2021 07:08:05 -0800 (PST) Received: from localhost ([::1]:59884 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7O0-0002uE-Ka for importer@patchew.org; Fri, 19 Feb 2021 10:08:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34086) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73f-0002Uq-Np for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:03 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:33403) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73I-0003Zk-KH for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:03 -0500 Received: by mail-wr1-x431.google.com with SMTP id 7so8918280wrz.0 for ; Fri, 19 Feb 2021 06:46:40 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ypb9NfsHfVKKOEKmFsF9EWiA17gITygP1HJEOh1ub2g=; b=E6QddN8Rr3BHAQ6mJAsaB6OVciN+FlQPW2EIyhyttI4s/+g3VdsIhlqlRQcMfg5v6S +wtJkTOW6EeSuyfjbLxC0WCFHQnyBSeNvDKahMCAZGHxpzqbsTvcB5IXBTkTE/EbhbfC OC6G9+ZuIkdLZPrL8Tyl1YGH8O+1OCOHBSpN8LANSI98IGGXa7bArA6BrEgLbIxvrgpF H+Dx2uwJc/hXbmy5UhkZnxTX4e3loxyqzviT1pUxeeTSqJAu2mslUoc1XYE2lTz14rDi 95rImNyzWdvu+s4u/UnikdExhJ+jEaiDUOY7S3kPLfady9DbzRIiiqYiI/1W+htjuteD MUcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ypb9NfsHfVKKOEKmFsF9EWiA17gITygP1HJEOh1ub2g=; b=axqm6j2C6DoqjZtT1XRL7tzo80Fx4qR3w265vMtskKVnkwoFnl6TTUhlM0UESlYSo0 wLaqm1KYKVBwa0ZUIDKN/mMa+is4WK3Un6h1mOgtss16QqYmEKvtgBeZbFz4zCdQ7wDu 6YwMKh3nhBtKZEKTjR68odjIhJVmixwiwwVZ2G1fwe4I8FT07TVioX9OBEl7Pher7e9D cInETLXd1h6+3+Ckz2CIuYNdt2soozwqFRyf5nR0oTicHXR6HTZFVLCcnV9gGGIKMDzj 9hRY3WPpkWfnp9ceDu7DreKuRVaNfY6H5VLQ/1kJ8X88/V+6W9LtpI1Tnnomgn/mP2vm NSmw== X-Gm-Message-State: AOAM530mwNpz3R8dyuwgdfH7WdfPFFAdoL1oZh6IBdyWiGyVeLJ7CDNb qWQktudyJkTtoPzfnAavcxYLtw== X-Google-Smtp-Source: ABdhPJwpjR96GIlmzjKPulL9/sVGe6CR3wNvcrjFyDwRXHkGvn1E8kE0iYhne2jR3UI1e9kF7QbdBQ== X-Received: by 2002:adf:82b3:: with SMTP id 48mr9255199wrc.22.1613745999174; Fri, 19 Feb 2021 06:46:39 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 25/44] hw/arm/armsse: Move watchdogs into data-driven framework Date: Fri, 19 Feb 2021 14:45:58 +0000 Message-Id: <20210219144617.4782-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Move the CMSDK watchdog device handling into the data-driven device placement framework. This is slightly more complicated because these devices might wire their IRQs up to the NMI line, and because one of them uses the slow 32KHz clock rather than the main clock. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/armsse.h | 4 +- hw/arm/armsse.c | 109 ++++++++++++++++++++++++---------------- 2 files changed, 66 insertions(+), 47 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index c1f4df295a4..3f8f3750577 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -171,9 +171,7 @@ struct ARMSSE { =20 CMSDKAPBDualTimer dualtimer; =20 - CMSDKAPBWatchdog s32kwatchdog; - CMSDKAPBWatchdog nswatchdog; - CMSDKAPBWatchdog swatchdog; + CMSDKAPBWatchdog cmsdk_watchdog[3]; =20 IoTKitSysCtl sysctl; IoTKitSysCtl sysinfo; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index f8da7fb00f9..6540ffb919b 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -34,6 +34,13 @@ =20 #define NO_IRQ -1 #define NO_PPC -1 +/* + * Special values for ARMSSEDeviceInfo::irq to indicate that this + * device uses one of the inputs to the OR gate that feeds into the + * CPU NMI input. + */ +#define NMI_0 10000 +#define NMI_1 10001 =20 typedef struct ARMSSEDeviceInfo { const char *name; /* name to use for the QOM object; NULL terminates l= ist */ @@ -42,7 +49,8 @@ typedef struct ARMSSEDeviceInfo { hwaddr addr; int ppc; /* Index of APB PPC this device is wired up to, or NO_PPC */ int ppc_port; /* Port number of this device on the PPC */ - int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1 */ + int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */ + bool slowclk; /* true if device uses the slow 32KHz clock */ } ARMSSEDeviceInfo; =20 struct ARMSSEInfo { @@ -114,6 +122,31 @@ static const ARMSSEDeviceInfo sse200_devices[] =3D { .ppc_port =3D 2, .irq =3D 5, }, + { + .name =3D "s32kwatchdog", + .type =3D TYPE_CMSDK_APB_WATCHDOG, + .index =3D 0, + .addr =3D 0x5002e000, + .ppc =3D NO_PPC, + .irq =3D NMI_0, + .slowclk =3D true, + }, + { + .name =3D "nswatchdog", + .type =3D TYPE_CMSDK_APB_WATCHDOG, + .index =3D 1, + .addr =3D 0x40081000, + .ppc =3D NO_PPC, + .irq =3D 1, + }, + { + .name =3D "swatchdog", + .type =3D TYPE_CMSDK_APB_WATCHDOG, + .index =3D 2, + .addr =3D 0x50081000, + .ppc =3D NO_PPC, + .irq =3D NMI_1, + }, { .name =3D NULL, } @@ -359,6 +392,11 @@ static void armsse_init(Object *obj) assert(devinfo->index =3D=3D 0); object_initialize_child(obj, devinfo->name, &s->dualtimer, TYPE_CMSDK_APB_DUALTIMER); + } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) { + assert(devinfo->index < ARRAY_SIZE(s->cmsdk_watchdog)); + object_initialize_child(obj, devinfo->name, + &s->cmsdk_watchdog[devinfo->index], + TYPE_CMSDK_APB_WATCHDOG); } else { g_assert_not_reached(); } @@ -386,14 +424,9 @@ static void armsse_init(Object *obj) object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); g_free(name); } + object_initialize_child(obj, "s32ktimer", &s->s32ktimer, TYPE_CMSDK_APB_TIMER); - object_initialize_child(obj, "s32kwatchdog", &s->s32kwatchdog, - TYPE_CMSDK_APB_WATCHDOG); - object_initialize_child(obj, "nswatchdog", &s->nswatchdog, - TYPE_CMSDK_APB_WATCHDOG); - object_initialize_child(obj, "swatchdog", &s->swatchdog, - TYPE_CMSDK_APB_WATCHDOG); object_initialize_child(obj, "armsse-sysctl", &s->sysctl, TYPE_IOTKIT_SYSCTL); object_initialize_child(obj, "armsse-sysinfo", &s->sysinfo, @@ -797,6 +830,17 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0, armsse_get_common_irq_in(s, 9)); =20 + /* This OR gate wires together outputs from the secure watchdogs to NM= I */ + if (!object_property_set_int(OBJECT(&s->nmi_orgate), "num-lines", 2, + errp)) { + return; + } + if (!qdev_realize(DEVICE(&s->nmi_orgate), NULL, errp)) { + return; + } + qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, + qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI"= , 0)); + /* Devices behind APB PPC0: * 0x40000000: timer0 * 0x40001000: timer1 @@ -827,6 +871,15 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) return; } mr =3D sysbus_mmio_get_region(sbd, 0); + } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) { + sbd =3D SYS_BUS_DEVICE(&s->cmsdk_watchdog[devinfo->index]); + + qdev_connect_clock_in(DEVICE(sbd), "WDOGCLK", + devinfo->slowclk ? s->s32kclk : s->mainc= lk); + if (!sysbus_realize(sbd, errp)) { + return; + } + mr =3D sysbus_mmio_get_region(sbd, 0); } else { g_assert_not_reached(); } @@ -838,6 +891,11 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) case 0 ... NUM_SSE_IRQS - 1: irq =3D armsse_get_common_irq_in(s, devinfo->irq); break; + case NMI_0: + case NMI_1: + irq =3D qdev_get_gpio_in(DEVICE(&s->nmi_orgate), + devinfo->irq - NMI_0); + break; default: g_assert_not_reached(); } @@ -1108,43 +1166,6 @@ static void armsse_realize(DeviceState *dev, Error *= *errp) } } =20 - /* This OR gate wires together outputs from the secure watchdogs to NM= I */ - if (!object_property_set_int(OBJECT(&s->nmi_orgate), "num-lines", 2, - errp)) { - return; - } - if (!qdev_realize(DEVICE(&s->nmi_orgate), NULL, errp)) { - return; - } - qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, - qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI"= , 0)); - - qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) { - return; - } - sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, - qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 0)); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 0x5002e000); - - /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ - - qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) { - return; - } - sysbus_connect_irq(SYS_BUS_DEVICE(&s->nswatchdog), 0, - armsse_get_common_irq_in(s, 1)); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); - - qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) { - return; - } - sysbus_connect_irq(SYS_BUS_DEVICE(&s->swatchdog), 0, - qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 1)); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->swatchdog), 0, 0x50081000); - for (i =3D 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { Object *splitter =3D OBJECT(&s->ppc_irq_splitter[i]); =20 --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613747697; cv=none; d=zohomail.com; s=zohoarc; b=DYnad11jCVO0zbGovT7SJQAxYoazf7jFNWWctF7x15RAmdkANr0dzmvIOouzUUGNm/YZeZLbzr00HHBLUyzltqyHrYdbvS3AV+mzNnu6KB8QCDCuXAbfYB3ZblfoJa2YgCaNXBeCQdklwIofUyiJNEnuZScEQlzozNysDC8yTYA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613747697; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UWgUkQ5pNZaZMRQCNjAYP//R+U9Ab+cfi649cOww/uQ=; b=EqShKA2QZ+l9Oil6o2RouTYArF9neKcfgRo7jFjZofSxLFMcjHucItz+8bvWmbYanOHUMuEUfYa65R9/9b2XKb2LvO5rOWxgx29VDTtl9gzxclTazjbLuSrSNR6QnsnuwZ6+8sIRqgptHkAYc2mmqj0tIIjK5NItYpqQrUFuFKQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613747697457402.6306670565957; Fri, 19 Feb 2021 07:14:57 -0800 (PST) Received: from localhost ([::1]:57164 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7Ue-0005oK-BI for importer@patchew.org; Fri, 19 Feb 2021 10:14:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73i-0002WY-2T for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:10 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:50559) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73J-0003a6-KS for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:05 -0500 Received: by mail-wm1-x32a.google.com with SMTP id a132so7345754wmc.0 for ; Fri, 19 Feb 2021 06:46:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=UWgUkQ5pNZaZMRQCNjAYP//R+U9Ab+cfi649cOww/uQ=; b=up4D5Ybd3VUz639hzzbRDxYYcMYcqQsmROk3eB0pmJw6g1cA2zor4pzSGGKHGg5kie VreIsb1HbeJtRtnP6heucbgKRh6xDaGjRcMkU8w6+UHHZWx4cfwKC2mO3CZqLHyLXTqe 9GM8dfGiKKgmPPTHDqBkzGTcLPtwxL/nY3LqZqRAi5OjbbgukwJF7hqjmEqdmCEFxYRF my1hG4LePkZmCvHOHL3Sv12b/eM3JXyPBJmxfK2X+KjItdsXf655VvYlyT3lan+rF085 7yETKLKWxu8yZS8cOCZ/91QuRRZGM3PA4kIhgO1jczgRbSJTmHllEKxY6p8xXLsb29E6 4zbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UWgUkQ5pNZaZMRQCNjAYP//R+U9Ab+cfi649cOww/uQ=; b=OrYXd9kvA4JMXAHopY/40gAXK2HX7AUfgGRl0zTNiLXrk2ZXr2jW7MVXWcpuBe57cD cPdyrxJ8kicS7rmL0VXBNSghaeAPplO2NDdh3qtA+8hbVurojZVMyJi/6jq+hVElwBkp DaelFVnks16y/petfV+Uo1AHVk9sux2DgtzpoCFGQBD31nL3az8ckc2qU3mSNip1Wk+R EskSauYR1IUUr2q/xkvJPGepuEZ1PtXSgFVYP2SBWlgSuxCLiV9H08PI+/LWnAQ9UMUK y1fdTOLiZ99t1rf5lsaCFLyViIXP5nGBGWlg7NvTMokstFsFDO7LUXH1Stb5fTY2lePd ZYHw== X-Gm-Message-State: AOAM533bg3SMPqor9jtlI1+9IENukVZYq6Ur6A7+B1sJXnPLaojI04ai e4SI2GIOzwL93UkVKUqliLWwnZ7v0YsKqg== X-Google-Smtp-Source: ABdhPJy4zeeikJc3a3dw3zMiwhnypXIHqsBQyFg9j/i/7+U30ayEWKSIHEzyaOn5s2WdsZ8UgLByLg== X-Received: by 2002:a1c:730f:: with SMTP id d15mr8476371wmb.135.1613745999957; Fri, 19 Feb 2021 06:46:39 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 26/44] hw/arm/armsse: Move s32ktimer into data-driven framework Date: Fri, 19 Feb 2021 14:45:59 +0000 Message-Id: <20210219144617.4782-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Move the CMSDK timer that uses the S32K slow clock into the data-driven device placement framework. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/armsse.h | 3 +-- hw/arm/armsse.c | 31 ++++++++++++------------------- 2 files changed, 13 insertions(+), 21 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 3f8f3750577..7416c08a802 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -158,8 +158,7 @@ struct ARMSSE { IoTKitSecCtl secctl; TZPPC apb_ppc[NUM_INTERNAL_PPCS]; TZMPC mpc[IOTS_NUM_MPC]; - CMSDKAPBTimer timer[2]; - CMSDKAPBTimer s32ktimer; + CMSDKAPBTimer timer[3]; qemu_or_irq ppc_irq_orgate; SplitIRQ sec_resp_splitter; SplitIRQ ppc_irq_splitter[NUM_PPCS]; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 6540ffb919b..3270362d599 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -113,6 +113,16 @@ static const ARMSSEDeviceInfo sse200_devices[] =3D { .ppc_port =3D 1, .irq =3D 4, }, + { + .name =3D "s32ktimer", + .type =3D TYPE_CMSDK_APB_TIMER, + .index =3D 2, + .addr =3D 0x4002f000, + .ppc =3D 1, + .ppc_port =3D 0, + .irq =3D 2, + .slowclk =3D true, + }, { .name =3D "dualtimer", .type =3D TYPE_CMSDK_APB_DUALTIMER, @@ -425,8 +435,6 @@ static void armsse_init(Object *obj) g_free(name); } =20 - object_initialize_child(obj, "s32ktimer", &s->s32ktimer, - TYPE_CMSDK_APB_TIMER); object_initialize_child(obj, "armsse-sysctl", &s->sysctl, TYPE_IOTKIT_SYSCTL); object_initialize_child(obj, "armsse-sysinfo", &s->sysinfo, @@ -858,7 +866,8 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) { sbd =3D SYS_BUS_DEVICE(&s->timer[devinfo->index]); =20 - qdev_connect_clock_in(DEVICE(sbd), "pclk", s->mainclk); + qdev_connect_clock_in(DEVICE(sbd), "pclk", + devinfo->slowclk ? s->s32kclk : s->mainc= lk); if (!sysbus_realize(sbd, errp)) { return; } @@ -1059,25 +1068,9 @@ static void armsse_realize(DeviceState *dev, Error *= *errp) } } =20 - /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region = */ - /* Devices behind APB PPC1: - * 0x4002f000: S32K timer - */ - qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { - return; - } - sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32ktimer), 0, - armsse_get_common_irq_in(s, 2)); - mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); - object_property_set_link(OBJECT(&s->apb_ppc[1]), "port[0]", OBJECT(mr), - &error_abort); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[1]), errp)) { return; } - mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc[1]), 0); - memory_region_add_subregion(&s->container, 0x4002f000, mr); =20 dev_apb_ppc1 =3D DEVICE(&s->apb_ppc[1]); qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613747660522985.819228166165; Fri, 19 Feb 2021 07:14:20 -0800 (PST) Received: from localhost ([::1]:53664 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7U3-0004OF-1m for importer@patchew.org; Fri, 19 Feb 2021 10:14:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34180) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73n-0002b5-OX for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:11 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:37288) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73J-0003aK-W5 for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:11 -0500 Received: by mail-wm1-x333.google.com with SMTP id m1so7889734wml.2 for ; Fri, 19 Feb 2021 06:46:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cUkpFgY7tiqXLrCF1eGUleIZNQUHBO/cDgm27ZFyGB4=; b=vEUATXAB9XP69ZbOGOISK88L6OX8Vz+hBAyyyL2ImLN3+JDaMb1B4DoC62G+9jnJsf +wFuLZGM7jqivaNM63tzBK1TrAIxOdZIR7Ezqm0zujGX2RhXLiVr2Km5UptnK86wgGfH SfTHC61zOWAgl/nfg5STV2LZ/e5/+6it5nlTlS1T4NbFlHfQaXGnBAI/iC1/ksY8U153 cOYtuWBFkYojLZkqFG8lk/xmXtPBigpy7vbuB1hrPU4z5rdTZNVK+MPFe2rw1C04ehZ9 L4cMNXX+3OyGdi6QtwztpcJpDIDxwc4FMXR+FfDSzZik/kQXKhtir96Ry0VxvDdVOiIs V5HQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cUkpFgY7tiqXLrCF1eGUleIZNQUHBO/cDgm27ZFyGB4=; b=jK1PJ+we8X/xDflFAdlg1wFZxYfyWBopCiKCdJmmMiUlnlq8Hd+DqM+qIJHc0LznOn cPfS5r7sW924czsu37nx/JqhuH9p5tnCYkzfG1jf1vllI0GPCRG2E/JYPepGHgA2+BhD EMxIgj79H9QleTGOcGTGVxg2fva26K1nQHM2khAyYZeHpyfU8NoVUidXaauFhFkIhpym MpPsgjdEj2GOqp2rcdK1tKYYFbb4ePZFUETo8tn3AcbR+8ewJHfUmX3Xs5FGQ7t9/Mg+ qtoWzGe/LFAF0EWIhSO3pAgUDPThvndqJEXa5t8b9BfeE8hq1hIiMqrVA5gyGL8sUdhw zfaw== X-Gm-Message-State: AOAM533NFw4b5BAm65Cx+krJbCxp2nbQ0QMbyUjuuog+M8HqojeZ4ynQ HTpeqWwfzN3dlAtJzLPP/jr/71k0K4UQmw== X-Google-Smtp-Source: ABdhPJzpLMOV9fxJxWqv8Zv0KRn+Kj8QCeNCcfNUkUQz2qTS89vwzB1SqbytHzdAIF2pT3TMgbh+qA== X-Received: by 2002:a1c:7e85:: with SMTP id z127mr8571215wmc.131.1613746000691; Fri, 19 Feb 2021 06:46:40 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 27/44] hw/arm/armsse: Move sysinfo register block into data-driven framework Date: Fri, 19 Feb 2021 14:46:00 +0000 Message-Id: <20210219144617.4782-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Move the sysinfo register block into the data-driven framework. While we are moving the code for configuring this device around, regularize on using &error_abortw when setting the integer properties: they are all simple DEFINE_PROP_UINT32 properties so the setting can never fail. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/armsse.c | 47 ++++++++++++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 19 deletions(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 3270362d599..91f30b1fdc4 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -157,6 +157,14 @@ static const ARMSSEDeviceInfo sse200_devices[] =3D { .ppc =3D NO_PPC, .irq =3D NMI_1, }, + { + .name =3D "armsse-sysinfo", + .type =3D TYPE_IOTKIT_SYSINFO, + .index =3D 0, + .addr =3D 0x40020000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, { .name =3D NULL, } @@ -407,6 +415,10 @@ static void armsse_init(Object *obj) object_initialize_child(obj, devinfo->name, &s->cmsdk_watchdog[devinfo->index], TYPE_CMSDK_APB_WATCHDOG); + } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSINFO)) { + assert(devinfo->index =3D=3D 0); + object_initialize_child(obj, devinfo->name, &s->sysinfo, + TYPE_IOTKIT_SYSINFO); } else { g_assert_not_reached(); } @@ -437,8 +449,6 @@ static void armsse_init(Object *obj) =20 object_initialize_child(obj, "armsse-sysctl", &s->sysctl, TYPE_IOTKIT_SYSCTL); - object_initialize_child(obj, "armsse-sysinfo", &s->sysinfo, - TYPE_IOTKIT_SYSINFO); if (info->has_mhus) { object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU); object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU); @@ -889,6 +899,22 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) return; } mr =3D sysbus_mmio_get_region(sbd, 0); + } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSINFO)) { + sbd =3D SYS_BUS_DEVICE(&s->sysinfo); + + object_property_set_int(OBJECT(&s->sysinfo), "SYS_VERSION", + info->sys_version, &error_abort); + object_property_set_int(OBJECT(&s->sysinfo), "SYS_CONFIG", + armsse_sys_config_value(s, info), + &error_abort); + object_property_set_int(OBJECT(&s->sysinfo), "sse-version", + info->sse_version, &error_abort); + object_property_set_int(OBJECT(&s->sysinfo), "IIDR", + info->iidr, &error_abort); + if (!sysbus_realize(sbd, errp)) { + return; + } + mr =3D sysbus_mmio_get_region(sbd, 0); } else { g_assert_not_reached(); } @@ -1106,23 +1132,6 @@ static void armsse_realize(DeviceState *dev, Error *= *errp) memory_region_add_subregion(&s->container, devinfo->addr, mr); } =20 - if (!object_property_set_int(OBJECT(&s->sysinfo), "SYS_VERSION", - info->sys_version, errp)) { - return; - } - if (!object_property_set_int(OBJECT(&s->sysinfo), "SYS_CONFIG", - armsse_sys_config_value(s, info), errp)) { - return; - } - object_property_set_int(OBJECT(&s->sysinfo), "sse-version", - info->sse_version, &error_abort); - object_property_set_int(OBJECT(&s->sysinfo), "IIDR", - info->iidr, &error_abort); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysinfo), errp)) { - return; - } - /* System information registers */ - sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000); /* System control registers */ object_property_set_int(OBJECT(&s->sysctl), "sse-version", info->sse_version, &error_abort); --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=QtFzdKHJmcOWhOa7pgzMvs7QBcJQKYPiMAhl2ByGZDs=; b=B5YSSQLtZfWU2QqFJgig9mnVWyr2rMYrQcEZbccx8ZKcreww0TSQKCeSNz9ByCG9VB TFVAESXSzmbAxzJWWXX57kZ64jcwl76XNpUSxxjLoYiisGCLIdpT94NOLBkedu0NUyvd ZMv31YKkQ/geSkWqBrSdLybw6/fe8JzgpzhX+jzOClpXmtReBcBlwxheVie4GE/KamrE EGcnvXnfvqofnq1hRFckvpe02k2UOVuZZ+3ET/jfhOF91yhFgR9L1LGAKkblsjVCbZVg f0gUVI0WV1IKED585uRK65F9Zem4xbMbLuEIHJjWe/rrHYtEZYeDYd76dbHUYFBAVYuK s0dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QtFzdKHJmcOWhOa7pgzMvs7QBcJQKYPiMAhl2ByGZDs=; b=gSF/CyqEX9g75K6cctx/vvPhrrXI+T348V8XwOLI4ZbXpyh56QMrn1yxvU3ICvbouY 4BGB9PLFHqHvts9NlM/05dRGJbfoxfm0b1LDrS5PlEinkomjEpfDdPmWpNl9iiZ9z424 6ZMBARsYSVk5zRSq8lNwg1eae3T/pktr6G5NrECFqrIHbT51EPpbnjhzhD6GlpANvTR0 J0IZ8w1YsChZ3Q/+GDOAApDdli4kvqEmWj0syXQjwEYCkGKThTAYwcGd0GXCYf6jPF/G GSTxmFcpIPzjPEZb1gi8YY30maTjfOzv9mzYVkdL+/NhFxjj0Drs3iM7IO1uTzNumjKG kKJA== X-Gm-Message-State: AOAM532FXwiYv4DMp0ru6DFIAzn84uJ0d87JFFUDTL2x90fZpdW/2a8t tGbcwgY115eo+QOHfdvRbThWHA== X-Google-Smtp-Source: ABdhPJxvbYg23SGotG6SASR1/4Vv9Q3K4S8kxhtGGtUQNNA+NR3vvn2Y0XV9tGX+cTA6IkKeqimQJA== X-Received: by 2002:a7b:c152:: with SMTP id z18mr6790863wmi.0.1613746001339; Fri, 19 Feb 2021 06:46:41 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 28/44] hw/arm/armsse: Move sysctl register block into data-driven framework Date: Fri, 19 Feb 2021 14:46:01 +0000 Message-Id: <20210219144617.4782-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Move the sysctl register block into the data-driven device placement framework. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/armsse.c | 44 ++++++++++++++++++++++++++++---------------- 1 file changed, 28 insertions(+), 16 deletions(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 91f30b1fdc4..961b2d44137 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -165,6 +165,14 @@ static const ARMSSEDeviceInfo sse200_devices[] =3D { .ppc =3D NO_PPC, .irq =3D NO_IRQ, }, + { + .name =3D "armsse-sysctl", + .type =3D TYPE_IOTKIT_SYSCTL, + .index =3D 0, + .addr =3D 0x50021000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, { .name =3D NULL, } @@ -419,6 +427,10 @@ static void armsse_init(Object *obj) assert(devinfo->index =3D=3D 0); object_initialize_child(obj, devinfo->name, &s->sysinfo, TYPE_IOTKIT_SYSINFO); + } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSCTL)) { + assert(devinfo->index =3D=3D 0); + object_initialize_child(obj, devinfo->name, &s->sysctl, + TYPE_IOTKIT_SYSCTL); } else { g_assert_not_reached(); } @@ -447,8 +459,6 @@ static void armsse_init(Object *obj) g_free(name); } =20 - object_initialize_child(obj, "armsse-sysctl", &s->sysctl, - TYPE_IOTKIT_SYSCTL); if (info->has_mhus) { object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU); object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU); @@ -915,6 +925,22 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) return; } mr =3D sysbus_mmio_get_region(sbd, 0); + } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSCTL)) { + /* System control registers */ + sbd =3D SYS_BUS_DEVICE(&s->sysctl); + + object_property_set_int(OBJECT(&s->sysctl), "sse-version", + info->sse_version, &error_abort); + object_property_set_int(OBJECT(&s->sysctl), "CPUWAIT_RST", + info->cpuwait_rst, &error_abort); + object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR0_RST", + s->init_svtor, &error_abort); + object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR1_RST", + s->init_svtor, &error_abort); + if (!sysbus_realize(sbd, errp)) { + return; + } + mr =3D sysbus_mmio_get_region(sbd, 0); } else { g_assert_not_reached(); } @@ -1132,20 +1158,6 @@ static void armsse_realize(DeviceState *dev, Error *= *errp) memory_region_add_subregion(&s->container, devinfo->addr, mr); } =20 - /* System control registers */ - object_property_set_int(OBJECT(&s->sysctl), "sse-version", - info->sse_version, &error_abort); - object_property_set_int(OBJECT(&s->sysctl), "CPUWAIT_RST", - info->cpuwait_rst, &error_abort); - object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR0_RST", - s->init_svtor, &error_abort); - object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR1_RST", - s->init_svtor, &error_abort); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysctl), errp)) { - return; - } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctl), 0, 0x50021000); - if (info->has_ppus) { /* CPUnCORE_PPU for each CPU */ for (i =3D 0; i < info->num_cpus; i++) { --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613747782256774.7361809726; Fri, 19 Feb 2021 07:16:22 -0800 (PST) Received: from localhost ([::1]:34106 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7W0-00084Q-TD for importer@patchew.org; Fri, 19 Feb 2021 10:16:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34210) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73p-0002dv-48 for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:13 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:44821) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73N-0003bW-3S for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:12 -0500 Received: by mail-wr1-x434.google.com with SMTP id h98so4079092wrh.11 for ; Fri, 19 Feb 2021 06:46:42 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cEJKOHogpqzaG7/CktL+aHOimKlEjDZSpK4Nv6pZHUY=; b=Qr9LT1f2UtPifH+i6ZtnWvjbsMW0qY3nyVeCtnVOpakpamBotEfYTR/ezXWPjydmYs TWtY825n0S2ZNy2CjeBDHwsMXNlW9maBQq724dGhN8Ci1IOzETnXgMzVCdtnQ1jXx1z7 a08YgNwMfVWzq7Lcex4LV48ZCv/SnFmBnNiRzO26hQNpAgsb4MMOJQzvuZopyLiUjXaY HU3uPipHILSZvc0lBnL+ClD6TzyPQjTEBpU4Rp9gvVKnLVD194oUfrEL+l98lpr6MNP3 A/kDX9ylxcYUw03ajer3h9F4wi47GyZwy4EDjgsHY9qQ4U8AmtrvGmvUw8g6/kgRBZIE Gp4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cEJKOHogpqzaG7/CktL+aHOimKlEjDZSpK4Nv6pZHUY=; b=otHnt2bpUBbuHsRUAcL9lDhUUhdMe50LO08WrqbBXPvy3zf09goPmByVOODyPgbN2m w50FbXDWbFk1HCAxm1I1PYh3d8alsXcbtQitGxnDKobckCVh6gQLeYJo6ekcO3KtWb8O 51pWpJDVDux9MN95G8IrVt0i/SvoO1SWqk7AtZyac80lkDI1fG++uE/eKLyd1YWpy7So ygYExmIuKY1/H3jWjNiCsj/hCWK3AH4NuwVnHLtlGhSWuXzQa+1OeT8UkSoHa710ZOHx bGNv+xZXw+gk5h/1FBLPrFN2yPtuZTAR77hINmGesfKphZ0AZwuEdrNop0K8MlKNURrV fixA== X-Gm-Message-State: AOAM533pk7ofAaXgiMxAMPWyU0c3+e4+WAEPJuj8dNenqjO38rr8m4l0 c7jQExbl0l0UQeXe/oTkK7kiEYACuxV2Zw== X-Google-Smtp-Source: ABdhPJystj0vcT5ai9jcWApVvd1EdAKEBomwhwecHAqsvujkbf9EpoBH79udPJ6Z9TVkzOlV0XClJA== X-Received: by 2002:adf:9c8a:: with SMTP id d10mr9730644wre.266.1613746002107; Fri, 19 Feb 2021 06:46:42 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 29/44] hw/arm/armsse: Move PPUs into data-driven framework Date: Fri, 19 Feb 2021 14:46:02 +0000 Message-Id: <20210219144617.4782-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Move the PPUs into the data-driven device placement framework. We don't implement them, so they are just TYPE_UNIMPLEMENTED stubs. Because the SSE-200 and the IotKit diverge here (the IoTKit does not have the PPUs) we need to separate out the ARMSSEDeviceInfo for the two variants, and only add the PPUs to the SSE-200. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/armsse.h | 10 +- hw/arm/armsse.c | 222 +++++++++++++++++++++++++++++----------- 2 files changed, 165 insertions(+), 67 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 7416c08a802..eb4e937173f 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -135,14 +135,6 @@ OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass, =20 #define SSE_MAX_CPUS 2 =20 -/* These define what each PPU in the ppu[] index is for */ -#define CPU0CORE_PPU 0 -#define CPU1CORE_PPU 1 -#define DBG_PPU 2 -#define RAM0_PPU 3 -#define RAM1_PPU 4 -#define RAM2_PPU 5 -#define RAM3_PPU 6 #define NUM_PPUS 7 =20 /* Number of CPU IRQs used by the SSE itself */ @@ -176,7 +168,7 @@ struct ARMSSE { IoTKitSysCtl sysinfo; =20 ARMSSEMHU mhu[2]; - UnimplementedDeviceState ppu[NUM_PPUS]; + UnimplementedDeviceState unimp[NUM_PPUS]; UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS]; =20 diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 961b2d44137..f72d1adafea 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -47,6 +47,7 @@ typedef struct ARMSSEDeviceInfo { const char *type; /* QOM type name */ unsigned int index; /* Which of the N devices of this type is this ? */ hwaddr addr; + hwaddr size; /* only needed for TYPE_UNIMPLEMENTED_DEVICE */ int ppc; /* Index of APB PPC this device is wired up to, or NO_PPC */ int ppc_port; /* Port number of this device on the PPC */ int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */ @@ -62,7 +63,6 @@ struct ARMSSEInfo { uint32_t iidr; uint32_t cpuwait_rst; bool has_mhus; - bool has_ppus; bool has_cachectrl; bool has_cpusecctrl; bool has_cpuid; @@ -94,7 +94,7 @@ static Property armsse_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 -static const ARMSSEDeviceInfo sse200_devices[] =3D { +static const ARMSSEDeviceInfo iotkit_devices[] =3D { { .name =3D "timer0", .type =3D TYPE_CMSDK_APB_TIMER, @@ -178,6 +178,153 @@ static const ARMSSEDeviceInfo sse200_devices[] =3D { } }; =20 +static const ARMSSEDeviceInfo sse200_devices[] =3D { + { + .name =3D "timer0", + .type =3D TYPE_CMSDK_APB_TIMER, + .index =3D 0, + .addr =3D 0x40000000, + .ppc =3D 0, + .ppc_port =3D 0, + .irq =3D 3, + }, + { + .name =3D "timer1", + .type =3D TYPE_CMSDK_APB_TIMER, + .index =3D 1, + .addr =3D 0x40001000, + .ppc =3D 0, + .ppc_port =3D 1, + .irq =3D 4, + }, + { + .name =3D "s32ktimer", + .type =3D TYPE_CMSDK_APB_TIMER, + .index =3D 2, + .addr =3D 0x4002f000, + .ppc =3D 1, + .ppc_port =3D 0, + .irq =3D 2, + .slowclk =3D true, + }, + { + .name =3D "dualtimer", + .type =3D TYPE_CMSDK_APB_DUALTIMER, + .index =3D 0, + .addr =3D 0x40002000, + .ppc =3D 0, + .ppc_port =3D 2, + .irq =3D 5, + }, + { + .name =3D "s32kwatchdog", + .type =3D TYPE_CMSDK_APB_WATCHDOG, + .index =3D 0, + .addr =3D 0x5002e000, + .ppc =3D NO_PPC, + .irq =3D NMI_0, + .slowclk =3D true, + }, + { + .name =3D "nswatchdog", + .type =3D TYPE_CMSDK_APB_WATCHDOG, + .index =3D 1, + .addr =3D 0x40081000, + .ppc =3D NO_PPC, + .irq =3D 1, + }, + { + .name =3D "swatchdog", + .type =3D TYPE_CMSDK_APB_WATCHDOG, + .index =3D 2, + .addr =3D 0x50081000, + .ppc =3D NO_PPC, + .irq =3D NMI_1, + }, + { + .name =3D "armsse-sysinfo", + .type =3D TYPE_IOTKIT_SYSINFO, + .index =3D 0, + .addr =3D 0x40020000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "armsse-sysctl", + .type =3D TYPE_IOTKIT_SYSCTL, + .index =3D 0, + .addr =3D 0x50021000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "CPU0CORE_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 0, + .addr =3D 0x50023000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "CPU1CORE_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 1, + .addr =3D 0x50025000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "DBG_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 2, + .addr =3D 0x50029000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "RAM0_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 3, + .addr =3D 0x5002a000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "RAM1_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 4, + .addr =3D 0x5002b000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "RAM2_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 5, + .addr =3D 0x5002c000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "RAM3_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 6, + .addr =3D 0x5002d000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D NULL, + } +}; + static const ARMSSEInfo armsse_variants[] =3D { { .name =3D TYPE_IOTKIT, @@ -188,12 +335,11 @@ static const ARMSSEInfo armsse_variants[] =3D { .iidr =3D 0, .cpuwait_rst =3D 0, .has_mhus =3D false, - .has_ppus =3D false, .has_cachectrl =3D false, .has_cpusecctrl =3D false, .has_cpuid =3D false, .props =3D iotkit_properties, - .devinfo =3D sse200_devices, + .devinfo =3D iotkit_devices, }, { .name =3D TYPE_SSE200, @@ -204,7 +350,6 @@ static const ARMSSEInfo armsse_variants[] =3D { .iidr =3D 0, .cpuwait_rst =3D 2, .has_mhus =3D true, - .has_ppus =3D true, .has_cachectrl =3D true, .has_cpusecctrl =3D true, .has_cpuid =3D true, @@ -431,6 +576,11 @@ static void armsse_init(Object *obj) assert(devinfo->index =3D=3D 0); object_initialize_child(obj, devinfo->name, &s->sysctl, TYPE_IOTKIT_SYSCTL); + } else if (!strcmp(devinfo->type, TYPE_UNIMPLEMENTED_DEVICE)) { + assert(devinfo->index < ARRAY_SIZE(s->unimp)); + object_initialize_child(obj, devinfo->name, + &s->unimp[devinfo->index], + TYPE_UNIMPLEMENTED_DEVICE); } else { g_assert_not_reached(); } @@ -463,26 +613,6 @@ static void armsse_init(Object *obj) object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU); object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU); } - if (info->has_ppus) { - for (i =3D 0; i < info->num_cpus; i++) { - char *name =3D g_strdup_printf("CPU%dCORE_PPU", i); - int ppuidx =3D CPU0CORE_PPU + i; - - object_initialize_child(obj, name, &s->ppu[ppuidx], - TYPE_UNIMPLEMENTED_DEVICE); - g_free(name); - } - object_initialize_child(obj, "DBG_PPU", &s->ppu[DBG_PPU], - TYPE_UNIMPLEMENTED_DEVICE); - for (i =3D 0; i < info->sram_banks; i++) { - char *name =3D g_strdup_printf("RAM%d_PPU", i); - int ppuidx =3D RAM0_PPU + i; - - object_initialize_child(obj, name, &s->ppu[ppuidx], - TYPE_UNIMPLEMENTED_DEVICE); - g_free(name); - } - } if (info->has_cachectrl) { for (i =3D 0; i < info->num_cpus; i++) { char *name =3D g_strdup_printf("cachectrl%d", i); @@ -568,17 +698,6 @@ static qemu_irq armsse_get_common_irq_in(ARMSSE *s, in= t irqno) } } =20 -static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr) -{ - /* Map a PPU unimplemented device stub */ - DeviceState *dev =3D DEVICE(&s->ppu[ppuidx]); - - qdev_prop_set_string(dev, "name", name); - qdev_prop_set_uint64(dev, "size", 0x1000); - sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->ppu[ppuidx]), 0, addr); -} - static void armsse_realize(DeviceState *dev, Error **errp) { ARMSSE *s =3D ARM_SSE(dev); @@ -941,6 +1060,15 @@ static void armsse_realize(DeviceState *dev, Error **= errp) return; } mr =3D sysbus_mmio_get_region(sbd, 0); + } else if (!strcmp(devinfo->type, TYPE_UNIMPLEMENTED_DEVICE)) { + sbd =3D SYS_BUS_DEVICE(&s->unimp[devinfo->index]); + + qdev_prop_set_string(DEVICE(sbd), "name", devinfo->name); + qdev_prop_set_uint64(DEVICE(sbd), "size", devinfo->size); + if (!sysbus_realize(sbd, errp)) { + return; + } + mr =3D sysbus_mmio_get_region(sbd, 0); } else { g_assert_not_reached(); } @@ -1158,28 +1286,6 @@ static void armsse_realize(DeviceState *dev, Error *= *errp) memory_region_add_subregion(&s->container, devinfo->addr, mr); } =20 - if (info->has_ppus) { - /* CPUnCORE_PPU for each CPU */ - for (i =3D 0; i < info->num_cpus; i++) { - char *name =3D g_strdup_printf("CPU%dCORE_PPU", i); - - map_ppu(s, CPU0CORE_PPU + i, name, 0x50023000 + i * 0x2000); - /* - * We don't support CPU debug so don't create the - * CPU0DEBUG_PPU at 0x50024000 and 0x50026000. - */ - g_free(name); - } - map_ppu(s, DBG_PPU, "DBG_PPU", 0x50029000); - - for (i =3D 0; i < info->sram_banks; i++) { - char *name =3D g_strdup_printf("RAM%d_PPU", i); - - map_ppu(s, RAM0_PPU + i, name, 0x5002a000 + i * 0x1000); - g_free(name); - } - } - for (i =3D 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { Object *splitter =3D OBJECT(&s->ppc_irq_splitter[i]); =20 --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613747897822873.2472348003588; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=JMvousW6dbRJz+5fKLTeFi4X/6d1tXrTIZkdqfZYup8=; b=d5RoKX1duLD8Ut+LGi2k9f1iKuckZckCEppMpZNtf3nSsURo9y6kJEubimv7yL0W8g j+PyPZjJyfa4HrRbsa8EulEMadSrFIsCkI0xaYUwhnclgNW/ULQ3I9AvlXrIT8nr21Li Xilp9ezX6dCeBi3rbG7lSJrvAslah7l958GF3jkTIkHKsSFXaZNMo9gJO2B3+LuRIfuW zCK0IkV0fbhC0p7uu68Kpi3WWq4oDw7uLp9PsjJg2yM5xPxsQSH/Qdr+29i+M9hxsuC4 l2cNuT8qlRlfLJ/M4SUFWf42geAqMV9zwq+t/fH5IgBX6aQzlF48Fe4wtTea3Bs7TKkM l3LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JMvousW6dbRJz+5fKLTeFi4X/6d1tXrTIZkdqfZYup8=; b=VSOpyBcP8kVVu3g3TN9aAf4YEOCP0bgY6NUg00gVOoh+mMSyGQI+2lrBk34RFmAnZf 9ygpwTIDMRoJUk29eER+Aw2UsRo3wGbEKLmbWmaeqqZYP/KAWyFAQQ/LZDVU+avvElt0 E8dR9iizqanDb7RG/qX5LZ9s7yR86vkyy1wKXZoUTaESeKhVz3BotfPf2hXzImhBa+v4 +9DTvid/woY3vDpbs9xO+T0Rq2TInkuqS9bVKyrPc6RpC87a7pWoAX1E/iCGt0W8dA1A uJ5pt38wAKCMTlOGghj6RR0sRXF1C890oaDIj4EEExn3OI5Ax8geNq7LruS+daxC33+l fgRQ== X-Gm-Message-State: AOAM533qGuFhcP82jTIw4V82K1GdSi0DNCzXZShBnpbnSLdv2rQ+3NfU GiSt+fbDQdpVGJk64bzmzyFvFDOFiQAWOw== X-Google-Smtp-Source: ABdhPJzuO4J58hqq/t2b9Uqhn0kSVGjYhuNlmCCB6yPNWxVE2+LmDkYqhS7eWh8W2arUW64sCRjsAg== X-Received: by 2002:adf:dfd1:: with SMTP id q17mr7519859wrn.273.1613746002694; Fri, 19 Feb 2021 06:46:42 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 30/44] hw/arm/armsse: Add missing SSE-200 SYS_PPU Date: Fri, 19 Feb 2021 14:46:03 +0000 Message-Id: <20210219144617.4782-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We forgot to implement a TYPE_UNIMPLEMENTED_DEVICE stub for the SYS_PPU in the SSE-200, which is at 0x50022000. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/armsse.h | 2 +- hw/arm/armsse.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index eb4e937173f..104ba8d26ec 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -135,7 +135,7 @@ OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass, =20 #define SSE_MAX_CPUS 2 =20 -#define NUM_PPUS 7 +#define NUM_PPUS 8 =20 /* Number of CPU IRQs used by the SSE itself */ #define NUM_SSE_IRQS 32 diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index f72d1adafea..f43f0524e28 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -320,6 +320,15 @@ static const ARMSSEDeviceInfo sse200_devices[] =3D { .ppc =3D NO_PPC, .irq =3D NO_IRQ, }, + { + .name =3D "SYS_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 7, + .addr =3D 0x50022000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, { .name =3D NULL, } --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613747237; cv=none; d=zohomail.com; s=zohoarc; b=MeGAqXTL+3gGbx1hNrZMoBAVMExmnejoxNdrgXk/XsrVIXhxsG4WFoaPcfWNbvvuJ4bDnsSkRXGyUtWOiPtEXuKaRrJIzzcCtNm9jIuvjmGGDoAH3wg+fOv3mUeq/NJ8ZI8W7sgEeeouK65KamRtjoJZWXXcmqVU0Usw/H7qSUc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613747237; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8JlFA4L9+WCjTt1Xqh1hA9XGzoAG7iZsCgd7Bz2ga0Q=; b=ke9+6oqrrVx5gHbB9Ssq7uagkZLqYO7L/iqtjEJenkJ/CnTpVAWsgp6vwId2EeslK60mKWQh5ahSnlf4S4GlwO6nVrbigqcP+cqhzDV/idnzmcul/nlWbH6etxVy2hQ3yPTrcfcP0jLu3IZpSX3hXD8brLFcSHTygjuek0S1kmI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16137472372571002.7366750158451; Fri, 19 Feb 2021 07:07:17 -0800 (PST) Received: from localhost ([::1]:57278 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7NE-0001oC-1m for importer@patchew.org; Fri, 19 Feb 2021 10:07:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34160) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73m-0002Y6-MZ for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:10 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:39830) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73N-0003cK-2R for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:10 -0500 Received: by mail-wm1-x334.google.com with SMTP id v62so7870011wmg.4 for ; Fri, 19 Feb 2021 06:46:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8JlFA4L9+WCjTt1Xqh1hA9XGzoAG7iZsCgd7Bz2ga0Q=; b=JzJqq7ZhHJs9jmyAQ2Ga8rYBwSr8v1qgCPtzT4jIBvILNBFuDU/fvXHE8aiAfqcEAK w1LFPD05ceA0DftPBf9cxt3iOeGJAs70JLa59KUPY8RXMg5Z7xAtX0YNqNGsdr+04L5C /MbCTJpId0EmSpQqWyNnbEM+jFQnDLGonvW6JCp0EIz38KUIKvSFpLl29OF9mBjB5XHj iIdGJf4RB1+F1McgZF1B7F4Q90kYbXE2Kopxc3QT6EGITx58l+gZiu5THjTvl6c0pmRn T+DSsUjJwtnROl8yIjpTozWOBWma+uPGJXcH68XaD3tbUVTHTjr/Bbgvb0awSz1DDvaD XZzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8JlFA4L9+WCjTt1Xqh1hA9XGzoAG7iZsCgd7Bz2ga0Q=; b=lsqf1yF5m4H4WR4qCE7DwKIrKnLVUnN4avXbSXMhjO06d23p7/gxvnFIIlV+rV9h2n bDOlv8sUOyPkUiNnP0E5Vk0Rgif4WHg4bolRAd5/wnO0yrHHi5C7hBKaFRKaYzASeCgr As+U1zoq5cbBKFragddj4F7aGyXU74oOw8VM2xycKCnqgsdqrbQc7/lAprxd4sZvcWxq O2Q1puonAb9wp/tAHHvjmP4Xhab0wYyUjncXxYHcp2YSfCQwr0UqxxDO0AQpWmGuN642 H0XKbNuxPlq7GYaUkNPtXCI9Lcb59qiguqIiB0fVhOCfJ7S98Nh7Jdt7D/nfxE694Lgr CNhw== X-Gm-Message-State: AOAM533c7/dpo8Mlk/wh5FR95zBKT8R8NsSX3kVAL1HhXnX9l09f9BOU UgjlZXvZRbAqrCHO/c1g7u0FluNPxSO0qQ== X-Google-Smtp-Source: ABdhPJxJwU3SH8kIniS4t3HdR2vlrMh/AnfrGqTAr8DjQJoGMDLOSbrb+SkNNx3aZD9xoCSYEgIhdQ== X-Received: by 2002:a1c:80c6:: with SMTP id b189mr8658115wmd.21.1613746003394; Fri, 19 Feb 2021 06:46:43 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 31/44] hw/arm/armsse: Indirect irq_is_common[] through ARMSSEInfo Date: Fri, 19 Feb 2021 14:46:04 +0000 Message-Id: <20210219144617.4782-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The SSE-300 has a slightly different set of shared-per-CPU interrupts, allow the irq_is_common[] array to be different per SSE variant. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/armsse.c | 39 +++++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 18 deletions(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index f43f0524e28..b316fe69571 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -68,6 +68,7 @@ struct ARMSSEInfo { bool has_cpuid; Property *props; const ARMSSEDeviceInfo *devinfo; + const bool *irq_is_common; }; =20 static Property iotkit_properties[] =3D { @@ -334,6 +335,21 @@ static const ARMSSEDeviceInfo sse200_devices[] =3D { } }; =20 +/* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ +static const bool sse200_irq_is_common[32] =3D { + [0 ... 5] =3D true, + /* 6, 7: per-CPU MHU interrupts */ + [8 ... 12] =3D true, + /* 13: per-CPU icache interrupt */ + /* 14: reserved */ + [15 ... 20] =3D true, + /* 21: reserved */ + [22 ... 26] =3D true, + /* 27: reserved */ + /* 28, 29: per-CPU CTI interrupts */ + /* 30, 31: reserved */ +}; + static const ARMSSEInfo armsse_variants[] =3D { { .name =3D TYPE_IOTKIT, @@ -349,6 +365,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cpuid =3D false, .props =3D iotkit_properties, .devinfo =3D iotkit_devices, + .irq_is_common =3D sse200_irq_is_common, }, { .name =3D TYPE_SSE200, @@ -364,6 +381,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cpuid =3D true, .props =3D armsse_properties, .devinfo =3D sse200_devices, + .irq_is_common =3D sse200_irq_is_common, }, }; =20 @@ -404,21 +422,6 @@ static uint32_t armsse_sys_config_value(ARMSSE *s, con= st ARMSSEInfo *info) /* Clock frequency in HZ of the 32KHz "slow clock" */ #define S32KCLK (32 * 1000) =20 -/* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ -static bool irq_is_common[32] =3D { - [0 ... 5] =3D true, - /* 6, 7: per-CPU MHU interrupts */ - [8 ... 12] =3D true, - /* 13: per-CPU icache interrupt */ - /* 14: reserved */ - [15 ... 20] =3D true, - /* 21: reserved */ - [22 ... 26] =3D true, - /* 27: reserved */ - /* 28, 29: per-CPU CTI interrupts */ - /* 30, 31: reserved */ -}; - /* * Create an alias region in @container of @size bytes starting at @base * which mirrors the memory starting at @orig. @@ -663,7 +666,7 @@ static void armsse_init(Object *obj) } if (info->num_cpus > 1) { for (i =3D 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { - if (irq_is_common[i]) { + if (info->irq_is_common[i]) { char *name =3D g_strdup_printf("cpu-irq-splitter%d", i); SplitIRQ *splitter =3D &s->cpu_irq_splitter[i]; =20 @@ -696,7 +699,7 @@ static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int= irqno) ARMSSEClass *asc =3D ARM_SSE_GET_CLASS(s); const ARMSSEInfo *info =3D asc->info; =20 - assert(irq_is_common[irqno]); + assert(info->irq_is_common[irqno]); =20 if (info->num_cpus =3D=3D 1) { /* Only one CPU -- just connect directly to it */ @@ -878,7 +881,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) /* Wire up the splitters that connect common IRQs to all CPUs */ if (info->num_cpus > 1) { for (i =3D 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { - if (irq_is_common[i]) { + if (info->irq_is_common[i]) { Object *splitter =3D OBJECT(&s->cpu_irq_splitter[i]); DeviceState *devs =3D DEVICE(splitter); int cpunum; --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161374740753374.90800467610745; Fri, 19 Feb 2021 07:10:07 -0800 (PST) Received: from localhost ([::1]:38504 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7Py-00066Y-Bh for importer@patchew.org; Fri, 19 Feb 2021 10:10:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34236) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73p-0002fN-NL for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:13 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:46760) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73N-0003cT-9N for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:13 -0500 Received: by mail-wr1-x42f.google.com with SMTP id t15so8823981wrx.13 for ; Fri, 19 Feb 2021 06:46:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZJZFHHRnw+bIexNpw6ym+fjTBPuLscNy2u0S4pBqSr0=; b=NTMsojNWO++Z1h/0Jg4GPljy1CAJQSlt9ggWk1MIBvQY4mzxnXsbiNNRFFjeUfTp00 qgrkQiy0rlpgkziaZMshbe7ZGm64jhuCEfiWrwY8GDKLJnCreGj3kR2LwEuTW/3/VjYX YvSSTEWUXLFPpzeG35ENF2BqILTQZThELvIbHqLUKdhcEq2SzYPwf3qGLQMzl/7kVO/K O6D1pPbbI+YD7PH2hQ2aYa4nNDkfqO7vgEgzO/DeO6aKOkLLRiTxQdhldaohSVgBN818 CD+6BAlJ6F5FZ54MAnSuWyfAaR5KM1RekQoFJiBbf8OrysPSUsy1DbEEg0A1Z5/5VAoC iYwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZJZFHHRnw+bIexNpw6ym+fjTBPuLscNy2u0S4pBqSr0=; b=TJy4RbFx34DREXSDasVAnZZOYpsh0/3zP3oT0dDv/i06vamA6/wAQ2zr9EakLaWJRd cNIsQIfuTL7UsmMY+dVonIIqSYcRRXrWmb5lsPF4ks1gOW8A0bGGPC7mu90L5a3nQz7p gX/1bPO7j9SXng8N5+NEAkGD6Xs8WPkiZWrUkGi6zpvOwO3b1OLW6UQkKzmE+fmkPdY2 /hO7c+2lqQBDQMkepw5/+dZ8bZX9pGFo1pCKohp9kmAVCIXVg4lSsqRh3/TODZUID5WX G09iaSP4EI3gTVQzpsdCde7WiBbjcsmouGB08L/b9bMypJPmk++iXLGKGSQU2gvGhf/N nQMg== X-Gm-Message-State: AOAM532NchKbY1hGTeFQC92t8ljJWe5gLwxIdBeOAuIvQbd+68LVFn5M LmoimZcyEOzJX/GNMgRSTT3Og+Gabj0Duw== X-Google-Smtp-Source: ABdhPJwynZ44fXK6672WEzILcp7zqzlL/wazNWYqdjhjWgO1IoUeFfHBNLDQbKVT2OoH1pRz+odisQ== X-Received: by 2002:a5d:5109:: with SMTP id s9mr8160882wrt.325.1613746004089; Fri, 19 Feb 2021 06:46:44 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 32/44] hw/arm/armsse: Add support for SSE variants with a system counter Date: Fri, 19 Feb 2021 14:46:05 +0000 Message-Id: <20210219144617.4782-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The SSE-300 has a system counter device; add support for SSE variants having this device. As with the existing devices like the cache control block, CPUID block, etc, we don't try to make the MMIO addresses configurable. We can do that if and when we need to model a future SSE variant which has the counter in a different location. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/armsse.h | 3 +++ hw/arm/armsse.c | 27 +++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 104ba8d26ec..149f17dfc88 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -97,6 +97,7 @@ #include "hw/misc/tz-mpc.h" #include "hw/timer/cmsdk-apb-timer.h" #include "hw/timer/cmsdk-apb-dualtimer.h" +#include "hw/timer/sse-counter.h" #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "hw/misc/iotkit-sysctl.h" #include "hw/misc/iotkit-sysinfo.h" @@ -164,6 +165,8 @@ struct ARMSSE { =20 CMSDKAPBWatchdog cmsdk_watchdog[3]; =20 + SSECounter sse_counter; + IoTKitSysCtl sysctl; IoTKitSysCtl sysinfo; =20 diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index b316fe69571..4387e98376c 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -66,6 +66,7 @@ struct ARMSSEInfo { bool has_cachectrl; bool has_cpusecctrl; bool has_cpuid; + bool has_sse_counter; Property *props; const ARMSSEDeviceInfo *devinfo; const bool *irq_is_common; @@ -363,6 +364,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cachectrl =3D false, .has_cpusecctrl =3D false, .has_cpuid =3D false, + .has_sse_counter =3D false, .props =3D iotkit_properties, .devinfo =3D iotkit_devices, .irq_is_common =3D sse200_irq_is_common, @@ -379,6 +381,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cachectrl =3D true, .has_cpusecctrl =3D true, .has_cpuid =3D true, + .has_sse_counter =3D false, .props =3D armsse_properties, .devinfo =3D sse200_devices, .irq_is_common =3D sse200_irq_is_common, @@ -652,6 +655,11 @@ static void armsse_init(Object *obj) g_free(name); } } + if (info->has_sse_counter) { + object_initialize_child(obj, "sse-counter", &s->sse_counter, + TYPE_SSE_COUNTER); + } + object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, TYPE_OR_IRQ= ); object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate, TYPE_OR_IRQ); @@ -1000,6 +1008,25 @@ static void armsse_realize(DeviceState *dev, Error *= *errp) qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI"= , 0)); =20 + /* The SSE-300 has a System Counter / System Timestamp Generator */ + if (info->has_sse_counter) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->sse_counter); + + qdev_connect_clock_in(DEVICE(sbd), "CLK", s->mainclk); + if (!sysbus_realize(sbd, errp)) { + return; + } + /* + * The control frame is only in the Secure region; + * the status frame is in the NS region (and visible in the + * S region via the alias mapping). + */ + memory_region_add_subregion(&s->container, 0x58100000, + sysbus_mmio_get_region(sbd, 0)); + memory_region_add_subregion(&s->container, 0x48101000, + sysbus_mmio_get_region(sbd, 1)); + } + /* Devices behind APB PPC0: * 0x40000000: timer0 * 0x40001000: timer1 --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613747611135715.009062698893; Fri, 19 Feb 2021 07:13:31 -0800 (PST) Received: from localhost ([::1]:49374 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7TG-0002fy-28 for importer@patchew.org; Fri, 19 Feb 2021 10:13:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34260) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73q-0002iR-T9 for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:14 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:38706) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73N-0003ca-UI for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:14 -0500 Received: by mail-wm1-x32d.google.com with SMTP id x4so7882238wmi.3 for ; Fri, 19 Feb 2021 06:46:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Ou09H48NtnRHyRFT/ewuJC3FR8Ak/PHc4n9tF+Stryo=; b=ouS9eXghQsYzwGTIROUfoXCVce9rqNdrMiXXnMMIElX+nUFEoje+FI94YWNxG+IzZ0 tUHE/5eRLbd/F25mKj9D9RtIp97bSpRbRv5WvoLwcOGOrwWZjxi+u30EStdLMap+AwNv vjfjWqwAJ4kGrCoDrZtelvlcvymVo9zDPRsQ9LfB8eoQvbcjC0mgeMDAfr4cRmLas0sB CXSdJBMHEtRXned/qOvYfLEPBWIkAdQ7F2RfLTJONASTTV9xJRRkvaOaUrGHkXPEkP1y nT09Ihs3Sqvtm4hCe6eBGYjAWCUYsr4zNCehKIfcVoq3sIlgYHF328aifZ32TAxBOyrW EEGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ou09H48NtnRHyRFT/ewuJC3FR8Ak/PHc4n9tF+Stryo=; b=E9x2KHYr8JXXlJzPmtNyUbWhGxDgSqr+8O0rRMhxs0x+s2DPpa/cXoK8j5zE+JrMiP kHc6cqpxUHnwT1eRIKyTzLrZoK6LQvcsbShfG8NRICC9BVgZU2h8bgZB4F2U+DzPNriN I4cZzn3U8m//lGeL1zBkAI8c8XjeOSq7+m+1u5urjMmRWo5DB0r3NLS2dW4I072d6eZc zeirZ1mut4hHDKMQK17b5Q20YhCTWYarstpYr7BA5q5k1rc668GKQOcajDTZMpEzuRCy 5ujqyKgFFfOfychR5JUrFaKzFIfecVkQGhD+7cIo+EO9mQXmu6ZrPIL2mN4bYcnrlwjV MzhQ== X-Gm-Message-State: AOAM531fimSeBl7qBZRr0f8MBPZOzlzOxf4aqtn3aKqozajhtDIuvac+ pDpEL5KVXzVSRYbwZXFGbwgyN28uHMg4jQ== X-Google-Smtp-Source: ABdhPJxfMU/Zl4dUXdv3OTpUem3+YoAX+d1hrr2ZA5jg+GWSrWg8uOJLZq3E44zN6JRZOcY6rmDsjQ== X-Received: by 2002:a1c:20c7:: with SMTP id g190mr8437861wmg.156.1613746004698; Fri, 19 Feb 2021 06:46:44 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 33/44] hw/arm/armsse: Add support for TYPE_SSE_TIMER in ARMSSEDeviceInfo Date: Fri, 19 Feb 2021 14:46:06 +0000 Message-Id: <20210219144617.4782-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The SSE-300 has four timers of type TYPE_SSE_TIMER; add support in the code for having these in an ARMSSEDeviceInfo array. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/armsse.h | 2 ++ hw/arm/armsse.c | 15 +++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 149f17dfc88..f4e2b680479 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -98,6 +98,7 @@ #include "hw/timer/cmsdk-apb-timer.h" #include "hw/timer/cmsdk-apb-dualtimer.h" #include "hw/timer/sse-counter.h" +#include "hw/timer/sse-timer.h" #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "hw/misc/iotkit-sysctl.h" #include "hw/misc/iotkit-sysinfo.h" @@ -166,6 +167,7 @@ struct ARMSSE { CMSDKAPBWatchdog cmsdk_watchdog[3]; =20 SSECounter sse_counter; + SSETimer sse_timer[4]; =20 IoTKitSysCtl sysctl; IoTKitSysCtl sysinfo; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 4387e98376c..ec9c30e0996 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -578,6 +578,11 @@ static void armsse_init(Object *obj) assert(devinfo->index =3D=3D 0); object_initialize_child(obj, devinfo->name, &s->dualtimer, TYPE_CMSDK_APB_DUALTIMER); + } else if (!strcmp(devinfo->type, TYPE_SSE_TIMER)) { + assert(devinfo->index < ARRAY_SIZE(s->sse_timer)); + object_initialize_child(obj, devinfo->name, + &s->sse_timer[devinfo->index], + TYPE_SSE_TIMER); } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) { assert(devinfo->index < ARRAY_SIZE(s->cmsdk_watchdog)); object_initialize_child(obj, devinfo->name, @@ -1058,6 +1063,16 @@ static void armsse_realize(DeviceState *dev, Error *= *errp) return; } mr =3D sysbus_mmio_get_region(sbd, 0); + } else if (!strcmp(devinfo->type, TYPE_SSE_TIMER)) { + sbd =3D SYS_BUS_DEVICE(&s->sse_timer[devinfo->index]); + + assert(info->has_sse_counter); + object_property_set_link(OBJECT(sbd), "counter", + OBJECT(&s->sse_counter), &error_abort= ); + if (!sysbus_realize(sbd, errp)) { + return; + } + mr =3D sysbus_mmio_get_region(sbd, 0); } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) { sbd =3D SYS_BUS_DEVICE(&s->cmsdk_watchdog[devinfo->index]); =20 --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613747709; cv=none; d=zohomail.com; s=zohoarc; b=J/e1+/jMfxFG9+OSDfIkIKR8RuYPEH1mAYHHjwxt1b6mx6X1/olnienoXQ0TTdo0fJZNYqPfm4ew/QgtIAtdDFtOjLXy1wWfzs0t0Par0+EYLrvujLG8amkXADXbDRF5ysIPO2CYSn+vz2XxIUIe0Ne6pdrwfUjAkDHJmEL71EE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613747709; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AbLWZDU49J088c2eS3fP9W433ZG0VZOrayl8b6TQOBc=; b=LUAuYYn4Bt7f+jpgFwiXNTK6zIxOqY73vIf+LwXBGaiGrT9ZyPxhSA/ODEtCXyk2AdDUWKWRecU4SwmmMdBRuzUA5HXzzo+YJGvAv8R0CxnRWA5U9iEiY03i3e8pQ1z1HQkIM3PI52btS118dFlNOw1u3EcEQcEE3/qrpi7qJJQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613747708638606.6888133104491; Fri, 19 Feb 2021 07:15:08 -0800 (PST) Received: from localhost ([::1]:58090 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7Up-0006Ac-8F for importer@patchew.org; Fri, 19 Feb 2021 10:15:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34262) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73q-0002iU-V1 for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:14 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:34484) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73O-0003cs-QZ for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:14 -0500 Received: by mail-wr1-x42a.google.com with SMTP id n4so8912846wrx.1 for ; Fri, 19 Feb 2021 06:46:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=AbLWZDU49J088c2eS3fP9W433ZG0VZOrayl8b6TQOBc=; b=eCQtSIqUDnby2MRJA5kkN6VuIZciSAnwASc/yII6cvWkrMLqaF7q3n/4ScF8JweKej i6iItJ84KqMxa0tTzJnzxTEQ3oj9rhH0Tm/GSsEk+wc0Y9vsTBx46ZJxWzaoLXDeHTSS EG5wqKEOwG2q/6Z4gONbquLfaDQYDkDBK8tLEwJXX89iI2hIMbwTaYV2O9aY7X+AcEKp VbC7zeUZQq+sX4uz9NGzPwLemgL46kuyd09hM7tifBQCq05UdSuDwkGqAKKBhW32hmrL A3NVUqWQgjqJf+/3htDxYt2NA5wEIeoPvYs0hxQTtHAcATmr7h72ZzDmb4KIE0M5HZFC jqEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AbLWZDU49J088c2eS3fP9W433ZG0VZOrayl8b6TQOBc=; b=VBrbMUQrEQ3HJxEpbhVgwvYxCOTl2OkILxds3mniUlSHSKFKRvHK/5uhyfd4Aq3lDo 9lGi+/mYx4FQ8pDDhfMgQTgJP//8GqD0inuzBdGydifRO2Mk5V4zabZsbJK6GvsZoGKH vZDZjweWHJaa+vTtzI1U+XMZOXnjCG6lSG9qtytFiTf6n8eXrNeBs7y13oln588TNMBz fczwJhCrA4HNE62aSIYytd+rzHXadO3FQGiYYgBk6VsLn35+Z++kVnrrd6I7FIMUxBeq XLqKTf0R5YqLgqqOGfCn0FE429FJdDlqKT6eJFwnyCvNLCPfbqanYHoDmpdeU47U0Wrp 1ETA== X-Gm-Message-State: AOAM531ok+2aLZN1kQbE5qycbyVWtA7xNqYicsRzI0QF0mXtgn8hf/xj VB34zbriLn0gysdUz7Th6dj0REmV8MigWg== X-Google-Smtp-Source: ABdhPJxFJRWlrAv73i+PduWiS3Dw0T49dVn2OHTGWwESeO6enljVH2VzRp+VEkaGNUDEgcr18Ilt/g== X-Received: by 2002:a5d:698d:: with SMTP id g13mr9674942wru.30.1613746005401; Fri, 19 Feb 2021 06:46:45 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 34/44] hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL block Date: Fri, 19 Feb 2021 14:46:07 +0000 Message-Id: <20210219144617.4782-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Support SSE variants like the SSE-300 with an ARMSSE_CPU_PWRCTRL register block. Because this block is per-CPU and does not clash with any of the SSE-200 devices, we handle it with a has_cpu_pwrctrl flag like the existing has_cachectrl, has_cpusectrl and has_cpuid, rather than trying to add per-CPU-device support to the devinfo array handling code. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/armsse.h | 3 +++ hw/arm/armsse.c | 26 ++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index f4e2b680479..21d239c381c 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -104,6 +104,7 @@ #include "hw/misc/iotkit-sysinfo.h" #include "hw/misc/armsse-cpuid.h" #include "hw/misc/armsse-mhu.h" +#include "hw/misc/armsse-cpu-pwrctrl.h" #include "hw/misc/unimp.h" #include "hw/or-irq.h" #include "hw/clock.h" @@ -179,6 +180,8 @@ struct ARMSSE { =20 ARMSSECPUID cpuid[SSE_MAX_CPUS]; =20 + ARMSSECPUPwrCtrl cpu_pwrctrl[SSE_MAX_CPUS]; + /* * 'container' holds all devices seen by all CPUs. * 'cpu_container[i]' is the view that CPU i has: this has the diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index ec9c30e0996..2366c49376d 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -66,6 +66,7 @@ struct ARMSSEInfo { bool has_cachectrl; bool has_cpusecctrl; bool has_cpuid; + bool has_cpu_pwrctrl; bool has_sse_counter; Property *props; const ARMSSEDeviceInfo *devinfo; @@ -364,6 +365,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cachectrl =3D false, .has_cpusecctrl =3D false, .has_cpuid =3D false, + .has_cpu_pwrctrl =3D false, .has_sse_counter =3D false, .props =3D iotkit_properties, .devinfo =3D iotkit_devices, @@ -381,6 +383,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cachectrl =3D true, .has_cpusecctrl =3D true, .has_cpuid =3D true, + .has_cpu_pwrctrl =3D false, .has_sse_counter =3D false, .props =3D armsse_properties, .devinfo =3D sse200_devices, @@ -660,6 +663,15 @@ static void armsse_init(Object *obj) g_free(name); } } + if (info->has_cpu_pwrctrl) { + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("cpu_pwrctrl%d", i); + + object_initialize_child(obj, name, &s->cpu_pwrctrl[i], + TYPE_ARMSSE_CPU_PWRCTRL); + g_free(name); + } + } if (info->has_sse_counter) { object_initialize_child(obj, "sse-counter", &s->sse_counter, TYPE_SSE_COUNTER); @@ -1255,6 +1267,8 @@ static void armsse_realize(DeviceState *dev, Error **= errp) * 0x50010000: L1 icache control registers * 0x50011000: CPUSECCTRL (CPU local security control registers) * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block + * The SSE-300 has an extra: + * 0x40012000 and 0x50012000: CPU_PWRCTRL register block */ if (info->has_cachectrl) { for (i =3D 0; i < info->num_cpus; i++) { @@ -1301,6 +1315,18 @@ static void armsse_realize(DeviceState *dev, Error *= *errp) memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, = mr); } } + if (info->has_cpu_pwrctrl) { + for (i =3D 0; i < info->num_cpus; i++) { + MemoryRegion *mr; + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu_pwrctrl[i]), errp))= { + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpu_pwrctrl[i= ]), 0); + memory_region_add_subregion(&s->cpu_container[i], 0x40012000, = mr); + } + } =20 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[1]), errp)) { return; --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=y0IkltMwkMmsntCXmla7YgVCExbHqoOzjdETdOI28dg=; b=wseSwm5R1EC+ycCHupY24rZDlUnOWnFgK8okczW+Z6g+zgVYmKYu1l2KWd+MK1Lh90 R9QZTwMAe7pRkQCqCfSPW5TPQV6Q4WqH0oVz3m6z1LaNWvJHqOYENoxCjBP6ZoKpbg5C LvCk3ygzlyUDG7ZwnIQcaLbwo3uYkAH6B/pcL4RGlgePf+RLU5few3NPaNLf9Ai3g6Cg q8QSCG9+Jzaxv3zbXFFvMASuh0iOjodPFiZbp9qiyF3ZKwXqS/nryvwDmkrIhPCHCfG1 9jv7K8z55xgOrmrPmldERFhkAXsu2Sc5suiRaAiN8o8W7L+46zSoQ7kkarMVRvSX2zSL uImg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y0IkltMwkMmsntCXmla7YgVCExbHqoOzjdETdOI28dg=; b=HlWNWztOVpCNpWWvLoGotiOMYEsHUTFMHIyH40OhmtYIgwzLFy12tEjlymvDA8lnNT XuLiF92MohJU/HesKUt70c2DjFYKw76u7cKegpbr10Uj6KVT9p4JefrFkfDSgseIz+R/ Ho3eLyBOkMIyckVDXP2Rv29bw3I3xhBpiSMQfHVDbjSOM1y8yFb/x0Ec/XZPO8ZKgotV crhzauHLRW8JEqTe/quamzapCmoQq+2CHD5Upwkf8YsdjJ7l5Y7dkJtV/aO/XwW7sqC2 4m4Oe9DmkLqhgtWOfZR2jDyAOboDRK28KyEsnq0egHkrV/w7cDnPFoWEhudKw+EC+lfA i1yg== X-Gm-Message-State: AOAM532aEaBpJwO/q9zqBYujhkUf3FFfcW7J2XOvGAYKcis2lh7UGigg jvF3pYfzvof9Pn4IET64df5wKg== X-Google-Smtp-Source: ABdhPJxk562T7pjJ74OIbrgk9pUWBpaRW9mqfoU5pbFGB4fPZw3pTvkzc98R9KNO2qwv1K1NpWTNyg== X-Received: by 2002:a05:6000:1546:: with SMTP id 6mr9486027wry.398.1613746006201; Fri, 19 Feb 2021 06:46:46 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 35/44] hw/arm/armsse: Add SSE-300 support Date: Fri, 19 Feb 2021 14:46:08 +0000 Message-Id: <20210219144617.4782-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Now we have sufficiently parameterised the code, we can add SSE-300 support by adding a new entry to the armsse_variants[] array. Note that the main watchdog (unlike the s32k watchdog) in the SSE-300 is a different device from the CMSDK watchdog; we don't have a model of it so we leave it as a TYPE_UNIMPLEMENTED_DEVICE stub. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/armsse.h | 1 + hw/arm/armsse.c | 152 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 153 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 21d239c381c..36592be62c5 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -123,6 +123,7 @@ OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass, */ #define TYPE_IOTKIT "iotkit" #define TYPE_SSE200 "sse-200" +#define TYPE_SSE300 "sse-300" =20 /* We have an IRQ splitter and an OR gate input for each external PPC * and the 2 internal PPCs diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 2366c49376d..e5aeb9e485f 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -337,6 +337,128 @@ static const ARMSSEDeviceInfo sse200_devices[] =3D { } }; =20 +static const ARMSSEDeviceInfo sse300_devices[] =3D { + { + .name =3D "timer0", + .type =3D TYPE_SSE_TIMER, + .index =3D 0, + .addr =3D 0x48000000, + .ppc =3D 0, + .ppc_port =3D 0, + .irq =3D 3, + }, + { + .name =3D "timer1", + .type =3D TYPE_SSE_TIMER, + .index =3D 1, + .addr =3D 0x48001000, + .ppc =3D 0, + .ppc_port =3D 1, + .irq =3D 4, + }, + { + .name =3D "timer2", + .type =3D TYPE_SSE_TIMER, + .index =3D 2, + .addr =3D 0x48002000, + .ppc =3D 0, + .ppc_port =3D 2, + .irq =3D 5, + }, + { + .name =3D "timer3", + .type =3D TYPE_SSE_TIMER, + .index =3D 3, + .addr =3D 0x48003000, + .ppc =3D 0, + .ppc_port =3D 5, + .irq =3D 27, + }, + { + .name =3D "s32ktimer", + .type =3D TYPE_CMSDK_APB_TIMER, + .index =3D 0, + .addr =3D 0x4802f000, + .ppc =3D 1, + .ppc_port =3D 0, + .irq =3D 2, + .slowclk =3D true, + }, + { + .name =3D "s32kwatchdog", + .type =3D TYPE_CMSDK_APB_WATCHDOG, + .index =3D 0, + .addr =3D 0x4802e000, + .ppc =3D NO_PPC, + .irq =3D NMI_0, + .slowclk =3D true, + }, + { + .name =3D "watchdog", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 0, + .addr =3D 0x48040000, + .size =3D 0x2000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "armsse-sysinfo", + .type =3D TYPE_IOTKIT_SYSINFO, + .index =3D 0, + .addr =3D 0x48020000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "armsse-sysctl", + .type =3D TYPE_IOTKIT_SYSCTL, + .index =3D 0, + .addr =3D 0x58021000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "SYS_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 1, + .addr =3D 0x58022000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "CPU0CORE_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 2, + .addr =3D 0x50023000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "MGMT_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 3, + .addr =3D 0x50028000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "DEBUG_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 4, + .addr =3D 0x50029000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D NULL, + } +}; + /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ static const bool sse200_irq_is_common[32] =3D { [0 ... 5] =3D true, @@ -352,6 +474,18 @@ static const bool sse200_irq_is_common[32] =3D { /* 30, 31: reserved */ }; =20 +static const bool sse300_irq_is_common[32] =3D { + [0 ... 5] =3D true, + /* 6, 7: per-CPU MHU interrupts */ + [8 ... 12] =3D true, + /* 13: reserved */ + [14 ... 16] =3D true, + /* 17-25: reserved */ + [26 ... 27] =3D true, + /* 28, 29: per-CPU CTI interrupts */ + /* 30, 31: reserved */ +}; + static const ARMSSEInfo armsse_variants[] =3D { { .name =3D TYPE_IOTKIT, @@ -389,6 +523,24 @@ static const ARMSSEInfo armsse_variants[] =3D { .devinfo =3D sse200_devices, .irq_is_common =3D sse200_irq_is_common, }, + { + .name =3D TYPE_SSE300, + .sse_version =3D ARMSSE_SSE300, + .sram_banks =3D 2, + .num_cpus =3D 1, + .sys_version =3D 0x7e00043b, + .iidr =3D 0x74a0043b, + .cpuwait_rst =3D 0, + .has_mhus =3D false, + .has_cachectrl =3D false, + .has_cpusecctrl =3D true, + .has_cpuid =3D true, + .has_cpu_pwrctrl =3D true, + .has_sse_counter =3D true, + .props =3D armsse_properties, + .devinfo =3D sse300_devices, + .irq_is_common =3D sse300_irq_is_common, + }, }; =20 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613747852; cv=none; d=zohomail.com; s=zohoarc; b=c96tWiXy7BEYGBk8AgGMyXffgPzop6DR+ZMxNqmC+sGnWLSIcqRSJWmqbSP48Kr28gy5/r8r0Nbs9JXDf9H3T5oHP23InOXLXP1Os6zMqFJ0UFdodf9jBxRopZnOSqucNtIgh1ylT461TxtTCMNEalqDRSqSKfPQw9iYYKWklAA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613747852; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hW6NWM9nxIp2NHn3uTePVNYECZHKfxs/17qf7kFubg4=; b=VM0+DKaHrS3JpbEE0UVva3fD4o26yZwJLAkHlvKRib0T98bp0k4jemDI8WPVjo64/EC32DOaVN6Jg4SLNgS3XYfECR/rYj4OA2Oas8zj77o6pqbYPRxTjIk8sTfN9YxW9Q94DkZBXTOcBDNjquibg5zZBU8m60RAQ8mx13TyIXM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613747852100607.8001195943935; Fri, 19 Feb 2021 07:17:32 -0800 (PST) Received: from localhost ([::1]:38880 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7X8-0001ik-Oe for importer@patchew.org; Fri, 19 Feb 2021 10:17:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34302) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73s-0002lX-JH for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:16 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:41242) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73Q-0003eQ-Av for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:16 -0500 Received: by mail-wr1-x435.google.com with SMTP id a4so6663388wro.8 for ; Fri, 19 Feb 2021 06:46:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hW6NWM9nxIp2NHn3uTePVNYECZHKfxs/17qf7kFubg4=; b=Ob1xp9NU47jaz+Y0lDxQFURRxnJNpi1p1aB6YNv+/6WyCobBxScM5nz2IOlC/b4dqi WXQ+bZdmyTav3zS1Lh7rK4QfQd03HJXBNJMHWni1jiA6SojfKa/PE7tnC3PvmcqRpQTu xODucm0HA9oCKXGseDNKl3zsQYi9zRYWW3fNQjkvtsYv7Vw13AmlzxWzIKN5N/xlXf7y befj7SpttiPS3aKYIUGUa4vwgaRAKeGqmt8OGtkGN7+1gN7sW9+vyMTr9mw6Tsy5UMD9 rmFlPD3l+30Kx/yAUSvuRXwbj2Lk3WDoeLPpa5zGEoOqBOZo0SrpAnb1VlAqBkQFjRTi 7+LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hW6NWM9nxIp2NHn3uTePVNYECZHKfxs/17qf7kFubg4=; b=gT/hOq3L3Ll3HQFFoA38fjEYip1qK/E8B23gBJKIRyRhen/rnbjaPl11J32OJ2P+no Hg1LxB7luz+GDHsMKk7AJwxPQZB4HLL53fmOGAP0VmysOwLMwU3jWpuQGu3+KEHbyo3v dVdDNkFPa+cgrO10IKpvF9Riew+f7SSFffdYGPqFiyhzqasTvE/cxvvheAcVIsimeZY8 6maIC3E5Vwu2h8xpXzWEAAgzMjB3cnQP67w38jZRv55GNcB6cwpRqzbJFt0QlyFcXy4w UvdXXKjgLVQU5t8JVaVY8Cd+84osmXxLS9g4376ALXHQJtwB1k4c10cklWwo9kffZueW frdQ== X-Gm-Message-State: AOAM530qWEUj5Pc2JsXqsKs3CYD2jczrbdbdBDjKtPGvr/2kQGO+I0RA aTz4wzlqJb46N8p9OkZIzN8RO5Dd8NaZNw== X-Google-Smtp-Source: ABdhPJwNgCxfaoG5gq2K/ECRqsfFaQ7ckgu2A5WQTEgW6hfj+LVS3ArdKsqfoyrnd5IzfXshHMjTsw== X-Received: by 2002:adf:fb51:: with SMTP id c17mr9774726wrs.145.1613746006899; Fri, 19 Feb 2021 06:46:46 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 36/44] hw/arm/mps2-tz: Make UART overflow IRQ board-specific Date: Fri, 19 Feb 2021 14:46:09 +0000 Message-Id: <20210219144617.4782-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The AN547 puts the combined UART overflow IRQ at 48, not 47 like the other images. Make this setting board-specific. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index aca8efba6cf..779fdb9a544 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -111,6 +111,7 @@ struct MPS2TZMachineClass { uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ int numirq; /* Number of external interrupts */ + int uart_overflow_irq; /* number of the combined UART overflow IRQ */ const RAMInfo *raminfo; const char *armsse_type; }; @@ -760,7 +761,7 @@ static void mps2tz_common_init(MachineState *machine) &error_fatal); qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, - get_sse_irq_in(mms, 47)); + get_sse_irq_in(mms, mmc->uart_overflow_irq)); =20 /* Most of the devices in the FPGA are behind Peripheral Protection * Controllers. The required order for initializing things is: @@ -1036,6 +1037,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, = void *data) mmc->fpgaio_num_leds =3D 2; mmc->fpgaio_has_switches =3D false; mmc->numirq =3D 92; + mmc->uart_overflow_irq =3D 47; mmc->raminfo =3D an505_raminfo; mmc->armsse_type =3D TYPE_IOTKIT; mps2tz_set_default_ram_info(mmc); @@ -1059,6 +1061,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, = void *data) mmc->fpgaio_num_leds =3D 2; mmc->fpgaio_has_switches =3D false; mmc->numirq =3D 92; + mmc->uart_overflow_irq =3D 47; mmc->raminfo =3D an505_raminfo; /* AN521 is the same as AN505 here */ mmc->armsse_type =3D TYPE_SSE200; mps2tz_set_default_ram_info(mmc); @@ -1082,6 +1085,7 @@ static void mps3tz_an524_class_init(ObjectClass *oc, = void *data) mmc->fpgaio_num_leds =3D 10; mmc->fpgaio_has_switches =3D true; mmc->numirq =3D 95; + mmc->uart_overflow_irq =3D 47; mmc->raminfo =3D an524_raminfo; mmc->armsse_type =3D TYPE_SSE200; mps2tz_set_default_ram_info(mmc); --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613748163; cv=none; d=zohomail.com; s=zohoarc; b=G9bJFPfj4jI3d/HgQlXXZULEpxQzUwas3Qs49cqVWlMiboaIbTBbM+SnB0g49PJfWvUzHhfSMHapjOr7wRWzViYtQycTBIpzNpljVQ+jmzk3njcppqYyK0lheI+v8TzQYb2vqpif34spxRp1H+xn+Y1LeS9M8Cu22JTHSZnHIN0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613748163; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6R2H7Db1FqG+TCsnIWopGNIyqmv4t5RlxdvA/d2HL4A=; b=UCeZxu+SoRN0q6Hq/FdNbyjMaeN2v4a6gmWmKGZwuZy/ayoIQ2SVwfMPVS6D36/XwMpUT/mb6xnTIbN/P6rxWBcXlnyX0bl/HLVnxr/VMHnxQelz+jXjOHRbDiMfR4ls73cPGeKrPycopp1LTK6QE6NAtJK19ekbH9CI9b6yIrk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613748162941124.04789315890616; Fri, 19 Feb 2021 07:22:42 -0800 (PST) Received: from localhost ([::1]:54086 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7c9-0008AQ-Im for importer@patchew.org; Fri, 19 Feb 2021 10:22:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34360) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73u-0002nT-Ly for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:18 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:34490) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73R-0003ej-4V for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:17 -0500 Received: by mail-wr1-x430.google.com with SMTP id n4so8913036wrx.1 for ; Fri, 19 Feb 2021 06:46:48 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6R2H7Db1FqG+TCsnIWopGNIyqmv4t5RlxdvA/d2HL4A=; b=nTqc9AfgNxxUsn9fG5s84VIFprLWXCgd7o8kxyNuo+ptpRLrwHJLo5OaLBBB1PUBde l/94HMAeMzm//VJsiPR00g5S4vBk6sw9Yjmz1x6el7oqtlNpA/otZDNm49BcDx4DnQZo CTmbWFOBddFOb0tQpXhBGhXOe0ZrcSCQ7jDRUaQQpENuYxpDzeFZ9RJyO+DfmztpoJ0x cTrW0sBifEW2wSUaDt3xwyPRAPs/qIj+5sHmaTFa2lQT+4vqppwEFc8PgSdqPJWZudcg ALsJpEUsSLBH9AbM2OSvz7GJsRM91M6ZoG0SiLXy75Zd9bK1LeevqURusthd2WEZtrFA bs1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6R2H7Db1FqG+TCsnIWopGNIyqmv4t5RlxdvA/d2HL4A=; b=dJDKA42JxnSNTRwz6qYe9bvjmT3ouBH7aR25atSZJevWwm4uf0qJ1ZsJ4Ydh5qxTYi GC8oo99twKvr7tTJVHUydRKCIL+PhrOPzQMy87d2v65exA7o4AeabZThMvRhquwvQiQp jZ1L8zxG/iaDqyGeetD0WAm/I2xds7JuMUia7CvEAJPmfGr3OO8+fVdwX3lvp+rvwLzH aIucCoocTKMhHn19KYc6Bz+lqDnNolBWHb11QguKGutHrNWtx/9Mqkx4zde5+Rdbu3kf fZIFVz2lVa/8v+Je3mgpfeSMTnX+C+k43evMuI5QrICEhNRtWw81LPs3yUh6/NkSLbqc 0XVw== X-Gm-Message-State: AOAM533T/jYPzP4OSg8fQbTdBWksqVwOupxvQUvjTHD4eapDxQZ266Yx 9wxTW164i973dc9xwXxIoPifeQ== X-Google-Smtp-Source: ABdhPJwo+bXazC6RrAeyLeF95NELByqHKy54pm9GZKjk5uSixw93wgsObIYBwPc27YeEcgx9EB9Odg== X-Received: by 2002:adf:82b3:: with SMTP id 48mr9255686wrc.22.1613746007635; Fri, 19 Feb 2021 06:46:47 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 37/44] hw/misc/mps2-fpgaio: Fold counters subsection into main vmstate Date: Fri, 19 Feb 2021 14:46:10 +0000 Message-Id: <20210219144617.4782-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We've already broken migration compatibility for all the MPS boards, so we might as well take advantage of this to simplify the vmstate for the FPGAIO device by folding the counters subsection into the main vmstate description. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/mps2-fpgaio.c | 30 +++++------------------------- 1 file changed, 5 insertions(+), 25 deletions(-) diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c index 76308543fcb..e3fabd58b7b 100644 --- a/hw/misc/mps2-fpgaio.c +++ b/hw/misc/mps2-fpgaio.c @@ -285,41 +285,21 @@ static void mps2_fpgaio_realize(DeviceState *dev, Err= or **errp) } } =20 -static bool mps2_fpgaio_counters_needed(void *opaque) -{ - /* Currently vmstate.c insists all subsections have a 'needed' functio= n */ - return true; -} - -static const VMStateDescription mps2_fpgaio_counters_vmstate =3D { - .name =3D "mps2-fpgaio/counters", +static const VMStateDescription mps2_fpgaio_vmstate =3D { + .name =3D "mps2-fpgaio", .version_id =3D 2, .minimum_version_id =3D 2, - .needed =3D mps2_fpgaio_counters_needed, .fields =3D (VMStateField[]) { + VMSTATE_UINT32(led0, MPS2FPGAIO), + VMSTATE_UINT32(prescale, MPS2FPGAIO), + VMSTATE_UINT32(misc, MPS2FPGAIO), VMSTATE_INT64(clk1hz_tick_offset, MPS2FPGAIO), VMSTATE_INT64(clk100hz_tick_offset, MPS2FPGAIO), VMSTATE_UINT32(counter, MPS2FPGAIO), VMSTATE_UINT32(pscntr, MPS2FPGAIO), VMSTATE_INT64(pscntr_sync_ticks, MPS2FPGAIO), VMSTATE_END_OF_LIST() - } -}; - -static const VMStateDescription mps2_fpgaio_vmstate =3D { - .name =3D "mps2-fpgaio", - .version_id =3D 1, - .minimum_version_id =3D 1, - .fields =3D (VMStateField[]) { - VMSTATE_UINT32(led0, MPS2FPGAIO), - VMSTATE_UINT32(prescale, MPS2FPGAIO), - VMSTATE_UINT32(misc, MPS2FPGAIO), - VMSTATE_END_OF_LIST() }, - .subsections =3D (const VMStateDescription*[]) { - &mps2_fpgaio_counters_vmstate, - NULL - } }; =20 static Property mps2_fpgaio_properties[] =3D { --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613748069; cv=none; d=zohomail.com; s=zohoarc; b=Cr9JGa/cY9383TQibV/cV9OhbL35nhfsAgazYMzfcwTs/1a0udD9fckubghTvK6jLuWldqKdjdpAugcWS5hDnDd+sr8Tk7YhW8Qg94IVJHNPLWmnUdBcC9GNs05C1lXj+bpJByUZ2Blabxa2SlhEcBz3lEG6jBl+XOBnFgmPIkU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613748069; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JWf+GNvIZzMKSxukg2vUD3hEVI958Vuh43UPZKCxICs=; b=IYinN5Mp8aTMjXskpBOdiSYi0QSs/und0kbHdUpkWaLrauhcfaAyCJhaDPMwIUSalAiqUidYixwFAOX2qdSD0n/HLhc8iwdtCqHmIgv0KKTo4TBrfXLxN5N4jB4ulC7irLQJN+mA3N+twPdF7hBhHz5MQkq2FUIznUbr2VZPjUg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613748069489466.17650364118356; Fri, 19 Feb 2021 07:21:09 -0800 (PST) Received: from localhost ([::1]:47642 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7ae-0005QZ-Dd for importer@patchew.org; Fri, 19 Feb 2021 10:21:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34378) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73w-0002qT-DP for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:24 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:40719) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73R-0003eu-O4 for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:20 -0500 Received: by mail-wr1-x42a.google.com with SMTP id v14so8882152wro.7 for ; Fri, 19 Feb 2021 06:46:49 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=JWf+GNvIZzMKSxukg2vUD3hEVI958Vuh43UPZKCxICs=; b=ner1eCb4rurcYxcxdmk/yLwwwEUswOgImZi31DzHXeGXLf3CxYTqBEVK9xC2tZKYQ0 y4iKmxrZA9jLHYoctT0zO3AIJ1yu9RNCItJNBVzk/6eYFHRtKVdoI7MXwf1gLPjmQToH cootVFj5LjtnYryj/bOqbJPPwShr+oGMKaJ+GzEZ9c6V0gTGycglZfjYrbYF3FjAABJk 20WbjdJhCQfUad5rs+H8Lvjtpj7AD+wD8k1CCVzgKtjCH+tEJAw3VRasuppDYX0OOCUm aUjKRYmk+wonZsYJRYBw9KHk7SIHz4a4sT0wdLqqjbslc3S1t9PZjdaI2Gx8I9a8+Xf9 gxNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JWf+GNvIZzMKSxukg2vUD3hEVI958Vuh43UPZKCxICs=; b=X0nrrMyZQqMeF1oM3ZANlFHEbW8foVAgE7A56T69FqPNfRLx+wxWxh1fKN09on6hT7 9sUrQipggtTtSEsMZ8Vec2n0HPPRXM0uIlGsIhWq+gKYF9KmbnvYX8a86L5kelRkhxRX djYVTsbX3wfAyZa4TsNLW7yE/0Bo+i3/gI46L0MKqmyGS3cGSd1ySTmZ52tmYIAYbzNH 74oIwOlN5DkFmTJEM3awNb8/tM8eEanIwIrQbq0PCTisaLTtaISGIw3iytyZ4nwy/EZl c/g/zNbqGqDHjtNWLjhq4NLM6zRDCmJ+tc+swAP8KJA4BDxLn8BrLIR+NWO3EOYWZenS Hiuw== X-Gm-Message-State: AOAM533rwrt0W2PidshgVl1YCrRDwEXTTP7i3ncxK/5kVjwLCDPoxCgS 53BVNnDQNyspdIYXzbEqhBAtZw== X-Google-Smtp-Source: ABdhPJy4118RfbFthBhTvY0FC9hOmonIa39GJD7zrV7Iy9rfcAMW/dyUK0K8v77y36So76vH0i61Xg== X-Received: by 2002:a5d:6d06:: with SMTP id e6mr9664860wrq.425.1613746008432; Fri, 19 Feb 2021 06:46:48 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 38/44] hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register Date: Fri, 19 Feb 2021 14:46:11 +0000 Message-Id: <20210219144617.4782-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For the AN547 image, the FPGAIO block has an extra DBGCTRL register, which is used to control the SPNIDEN, SPIDEN, NPIDEN and DBGEN inputs to the CPU. These signals control when the CPU permits use of the external debug interface. Our CPU models don't implement the external debug interface, so we model the register as reads-as-written. Implement the register, with a property defining whether it is present, and allow mps2-tz boards to specify that it is present. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/mps2-fpgaio.h | 2 ++ hw/arm/mps2-tz.c | 5 +++++ hw/misc/mps2-fpgaio.c | 22 ++++++++++++++++++++-- 3 files changed, 27 insertions(+), 2 deletions(-) diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h index e04fd590b63..7b8bd604de0 100644 --- a/include/hw/misc/mps2-fpgaio.h +++ b/include/hw/misc/mps2-fpgaio.h @@ -39,10 +39,12 @@ struct MPS2FPGAIO { LEDState *led[MPS2FPGAIO_MAX_LEDS]; uint32_t num_leds; bool has_switches; + bool has_dbgctrl; =20 uint32_t led0; uint32_t prescale; uint32_t misc; + uint32_t dbgctrl; =20 /* QEMU_CLOCK_VIRTUAL time at which counter and pscntr were last synce= d */ int64_t pscntr_sync_ticks; diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 779fdb9a544..fe324e86b3d 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -110,6 +110,7 @@ struct MPS2TZMachineClass { const uint32_t *oscclk; uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ + bool fpgaio_has_dbgctrl; /* Does FPGAIO have DBGCTRL register? */ int numirq; /* Number of external interrupts */ int uart_overflow_irq; /* number of the combined UART overflow IRQ */ const RAMInfo *raminfo; @@ -412,6 +413,7 @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mm= s, void *opaque, object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAI= O); qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_swit= ches); + qdev_prop_set_bit(DEVICE(fpgaio), "has-dbgctrl", mmc->fpgaio_has_dbgct= rl); sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); } @@ -1036,6 +1038,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, = void *data) mmc->len_oscclk =3D ARRAY_SIZE(an505_oscclk); mmc->fpgaio_num_leds =3D 2; mmc->fpgaio_has_switches =3D false; + mmc->fpgaio_has_dbgctrl =3D false; mmc->numirq =3D 92; mmc->uart_overflow_irq =3D 47; mmc->raminfo =3D an505_raminfo; @@ -1060,6 +1063,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, = void *data) mmc->len_oscclk =3D ARRAY_SIZE(an505_oscclk); mmc->fpgaio_num_leds =3D 2; mmc->fpgaio_has_switches =3D false; + mmc->fpgaio_has_dbgctrl =3D false; mmc->numirq =3D 92; mmc->uart_overflow_irq =3D 47; mmc->raminfo =3D an505_raminfo; /* AN521 is the same as AN505 here */ @@ -1084,6 +1088,7 @@ static void mps3tz_an524_class_init(ObjectClass *oc, = void *data) mmc->len_oscclk =3D ARRAY_SIZE(an524_oscclk); mmc->fpgaio_num_leds =3D 10; mmc->fpgaio_has_switches =3D true; + mmc->fpgaio_has_dbgctrl =3D false; mmc->numirq =3D 95; mmc->uart_overflow_irq =3D 47; mmc->raminfo =3D an524_raminfo; diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c index e3fabd58b7b..1c699410720 100644 --- a/hw/misc/mps2-fpgaio.c +++ b/hw/misc/mps2-fpgaio.c @@ -29,6 +29,7 @@ #include "qemu/timer.h" =20 REG32(LED0, 0) +REG32(DBGCTRL, 4) REG32(BUTTON, 8) REG32(CLK1HZ, 0x10) REG32(CLK100HZ, 0x14) @@ -129,6 +130,12 @@ static uint64_t mps2_fpgaio_read(void *opaque, hwaddr = offset, unsigned size) case A_LED0: r =3D s->led0; break; + case A_DBGCTRL: + if (!s->has_dbgctrl) { + goto bad_offset; + } + r =3D s->dbgctrl; + break; case A_BUTTON: /* User-pressable board buttons. We don't model that, so just retu= rn * zeroes. @@ -195,6 +202,14 @@ static void mps2_fpgaio_write(void *opaque, hwaddr off= set, uint64_t value, } } break; + case A_DBGCTRL: + if (!s->has_dbgctrl) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, + "MPS2 FPGAIO: DBGCTRL unimplemented\n"); + s->dbgctrl =3D value; + break; case A_PRESCALE: resync_counter(s); s->prescale =3D value; @@ -225,6 +240,7 @@ static void mps2_fpgaio_write(void *opaque, hwaddr offs= et, uint64_t value, s->pscntr =3D value; break; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "MPS2 FPGAIO write: bad offset 0x%x\n", (int) offset= ); break; @@ -287,12 +303,13 @@ static void mps2_fpgaio_realize(DeviceState *dev, Err= or **errp) =20 static const VMStateDescription mps2_fpgaio_vmstate =3D { .name =3D "mps2-fpgaio", - .version_id =3D 2, - .minimum_version_id =3D 2, + .version_id =3D 3, + .minimum_version_id =3D 3, .fields =3D (VMStateField[]) { VMSTATE_UINT32(led0, MPS2FPGAIO), VMSTATE_UINT32(prescale, MPS2FPGAIO), VMSTATE_UINT32(misc, MPS2FPGAIO), + VMSTATE_UINT32(dbgctrl, MPS2FPGAIO), VMSTATE_INT64(clk1hz_tick_offset, MPS2FPGAIO), VMSTATE_INT64(clk100hz_tick_offset, MPS2FPGAIO), VMSTATE_UINT32(counter, MPS2FPGAIO), @@ -308,6 +325,7 @@ static Property mps2_fpgaio_properties[] =3D { /* Number of LEDs controlled by LED0 register */ DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO, num_leds, 2), DEFINE_PROP_BOOL("has-switches", MPS2FPGAIO, has_switches, false), + DEFINE_PROP_BOOL("has-dbgctrl", MPS2FPGAIO, has_dbgctrl, false), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613747536742425.60664331093994; Fri, 19 Feb 2021 07:12:16 -0800 (PST) Received: from localhost ([::1]:45050 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7S3-0000tr-LT for importer@patchew.org; Fri, 19 Feb 2021 10:12:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34362) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD73u-0002nk-OS for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:18 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:36958) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73S-0003f9-Hx for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:18 -0500 Received: by mail-wr1-x432.google.com with SMTP id v15so8902609wrx.4 for ; Fri, 19 Feb 2021 06:46:50 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zKYWvcFtzDPV4Ks85TZ4B/LPAikGy0iTqTLoenNGpWQ=; b=LnSyDFfrmunbU0hI1erWmjP714qjEU9EnpBFLSDkWqWs65rA/R/0LEgElqBdpxwVHU ZdLx6NZTN3mDfBWsaJMQP8hp0TqP8sFkFfed8a02qnb0n845MZOAhY+FtIZn4VQverEs kohVDGqTO37qp4bOFJ1j27ouzOcSgX2qKFVMeEaKIlym9mzLjTjiUfXLdUA4Y+HJl2v9 aXPiXRZ9I49qrSALK4UPbf/gDrqbrsTyszuK1apaUK0SG0rQkfYeUMNa87Wzy8UpZu1j 3YL+vspCgSEFCLZEq41a9kuCCr5SN/X21zB4M/+p/F/cwb9p5mZgg+Oo5y/Bv2upEFmG 33cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zKYWvcFtzDPV4Ks85TZ4B/LPAikGy0iTqTLoenNGpWQ=; b=sf26ODiDi9Sk7T8f2Dhgx6Vv0E7pxJiE9fKxbgyIvMdklxt/YOJZ/OQVUFBb1Z2pIn 7gW4nhX1OiHw8lmwMJCpaY0jilPoVer6jMsUsDg+PmHzQa8yOi4c6p3RxrsOF5T6MN1V D9NXsuk3hFo32e8pOdtjsixC/74z57gHjhljg0vHSHIZCgolw/ONRDbG3hkc17nHH3Sz O6JRo4ZCQ8ScuKqTyBVGnKT0NH7ZrZ3HlJcnfHC1KS8SIz9Nhvc85FNKVre1x+qWLd9u E9jq7RcPXm3JMjhrgSH3m5hfHuKTxx/GWf+wuGsMkS9JIHKbi8UKFgDRXq5mgxzqv/2I q69A== X-Gm-Message-State: AOAM533gDaEpMs/vk6vnXDVA3m6KL2rNwDQk7He4O/coxvGy9K38DKvI VWhF/LmOjbIOfwV05pkF0BhwvJ+Gy3P6bw== X-Google-Smtp-Source: ABdhPJzHGOopwb3g6ljuU2FgaZepkbBMi2WRp6SCG+k82F+HPD1evO6ySRoej9pn35HwQsLhVzW2LQ== X-Received: by 2002:adf:b60e:: with SMTP id f14mr9588342wre.99.1613746009194; Fri, 19 Feb 2021 06:46:49 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 39/44] hw/misc/mps2-scc: Implement changes for AN547 Date: Fri, 19 Feb 2021 14:46:12 +0000 Message-Id: <20210219144617.4782-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the minor changes required to the SCC block for AN547 images: * CFG2 and CFG5 exist (like AN524) * CFG3 is reserved (like AN524) * CFG0 bit 1 is CPU_WAIT; we don't implement it, but note this in the TODO comment Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/mps2-scc.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index 140a4b9ceba..c56aca86ad5 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -110,14 +110,14 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr of= fset, unsigned size) r =3D s->cfg1; break; case A_CFG2: - if (scc_partno(s) !=3D 0x524) { + if (scc_partno(s) !=3D 0x524 && scc_partno(s) !=3D 0x547) { /* CFG2 reserved on other boards */ goto bad_offset; } r =3D s->cfg2; break; case A_CFG3: - if (scc_partno(s) =3D=3D 0x524) { + if (scc_partno(s) =3D=3D 0x524 && scc_partno(s) =3D=3D 0x547) { /* CFG3 reserved on AN524 */ goto bad_offset; } @@ -130,7 +130,7 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offs= et, unsigned size) r =3D s->cfg4; break; case A_CFG5: - if (scc_partno(s) !=3D 0x524) { + if (scc_partno(s) !=3D 0x524 && scc_partno(s) !=3D 0x547) { /* CFG5 reserved on other boards */ goto bad_offset; } @@ -185,7 +185,10 @@ static void mps2_scc_write(void *opaque, hwaddr offset= , uint64_t value, =20 switch (offset) { case A_CFG0: - /* TODO on some boards bit 0 controls RAM remapping */ + /* + * TODO on some boards bit 0 controls RAM remapping; + * on others bit 1 is CPU_WAIT. + */ s->cfg0 =3D value; break; case A_CFG1: @@ -195,7 +198,7 @@ static void mps2_scc_write(void *opaque, hwaddr offset,= uint64_t value, } break; case A_CFG2: - if (scc_partno(s) !=3D 0x524) { + if (scc_partno(s) !=3D 0x524 && scc_partno(s) !=3D 0x547) { /* CFG2 reserved on other boards */ goto bad_offset; } @@ -203,7 +206,7 @@ static void mps2_scc_write(void *opaque, hwaddr offset,= uint64_t value, s->cfg2 =3D value; break; case A_CFG5: - if (scc_partno(s) !=3D 0x524) { + if (scc_partno(s) !=3D 0x524 && scc_partno(s) !=3D 0x547) { /* CFG5 reserved on other boards */ goto bad_offset; } --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=i7J3nfprRkZYSN+DG8dR9uLCK+arEP02h3GtQa9f38U=; b=KN+GuYvbSVfjKtJ59vt/QUmxJzcvbYYkvhX6ODBeZlARXSfS1GHsRVbfy9G7lIqlml GdGYjIXIdZdxwVsQWMpzwmTReQ/dOD2/c/aXVolIqQeBpY53KT63S4+oiKANEyofpHnp oWIT5K5xUobV3r+Q0W2qFjd5GoQ/6ro7O5TCklw7nXm9zAkREAtdSftsT6U0xnMBi903 WvOPSLsB+Y8feyK0ZuMOXCKo3SBpZRa/RfWMbEOI7RSHj6LX1/JpZDSihFzQugAXuL4R qmGOkkrI/oZspSEKjiNa1+uGQtFl7ME7LzQL2D1qg4wuMlLqAxWxysblgtlHxayKUKNb MhRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=i7J3nfprRkZYSN+DG8dR9uLCK+arEP02h3GtQa9f38U=; b=hamkWYW1wDIo4K2u/90vZJSfYAiawhgqHAB2TFOyechNmA7FYr7iXg6fqLjGOViJxp HZH4f+fMAxcjLvUcVZ+2AwZl2Srethu/jY47gltZ2sYA6jOVMz7tp0fhE1jxlRFZExw1 9F45KtFvbo2L+ht8MyAT2Lrj6dKyGfMjrxEuLhRuZA6PQeFaGNRAuzAaDZRz8AkwMKYK pGlwqtJKuccTAmzUPY4ikbqZgo48il3Ill0bMb6cy4MYk6NyZredVsk+c8t4dIAbAEaD nYHmxvYYK+aHIuS2+15nHB3st2+2BbrepjmqQ6NybcY1qrevScAmDGT3SRjd7SM3gyeH 0FiQ== X-Gm-Message-State: AOAM531zlh7dfA6TvzA79AdiU5G66fsGRF3MSua1YDl+2HLcswCPwbRA aOK2PzNZWjATG2hJt4NXITKlUcDg+1MJuw== X-Google-Smtp-Source: ABdhPJz7ERyBoNjWmZcFmITkwyQcmz6ztIyAu2LPVksYnNQznWWM/B0w/s5Nf/eWeELBcDZYd3MCpA== X-Received: by 2002:a5d:5109:: with SMTP id s9mr8161240wrt.325.1613746009958; Fri, 19 Feb 2021 06:46:49 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 40/44] hw/arm/mps2-tz: Support running APB peripherals on different clock Date: Fri, 19 Feb 2021 14:46:13 +0000 Message-Id: <20210219144617.4782-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The AN547 runs the APB peripherals outside the SSE-300 on a different and slightly slower clock than it runs the SSE-300 with. Support making the APB peripheral clock frequency board-specific. (For our implementation only the UARTs actually take a clock.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index fe324e86b3d..47215f1b97c 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -106,6 +106,7 @@ struct MPS2TZMachineClass { MPS2TZFPGAType fpga_type; uint32_t scc_id; uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ + uint32_t apb_periph_frq; /* APB peripheral frequency in Hz */ uint32_t len_oscclk; const uint32_t *oscclk; uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ @@ -369,7 +370,7 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms,= void *opaque, =20 object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART); qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); - qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->sysclk_frq); + qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->apb_periph_frq); sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); s =3D SYS_BUS_DEVICE(uart); sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); @@ -1034,6 +1035,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, = void *data) mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id =3D 0x41045050; mmc->sysclk_frq =3D 20 * 1000 * 1000; /* 20MHz */ + mmc->apb_periph_frq =3D mmc->sysclk_frq; mmc->oscclk =3D an505_oscclk; mmc->len_oscclk =3D ARRAY_SIZE(an505_oscclk); mmc->fpgaio_num_leds =3D 2; @@ -1059,6 +1061,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, = void *data) mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id =3D 0x41045210; mmc->sysclk_frq =3D 20 * 1000 * 1000; /* 20MHz */ + mmc->apb_periph_frq =3D mmc->sysclk_frq; mmc->oscclk =3D an505_oscclk; /* AN521 is the same as AN505 here */ mmc->len_oscclk =3D ARRAY_SIZE(an505_oscclk); mmc->fpgaio_num_leds =3D 2; @@ -1084,6 +1087,7 @@ static void mps3tz_an524_class_init(ObjectClass *oc, = void *data) mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id =3D 0x41045240; mmc->sysclk_frq =3D 32 * 1000 * 1000; /* 32MHz */ + mmc->apb_periph_frq =3D mmc->sysclk_frq; mmc->oscclk =3D an524_oscclk; mmc->len_oscclk =3D ARRAY_SIZE(an524_oscclk); mmc->fpgaio_num_leds =3D 10; --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613748329; cv=none; d=zohomail.com; s=zohoarc; b=EVxGGza+c2tzigjchLykoujm1ZOuzijxLRZ5XFbJQ6ZmEbJT4tfkmHP0Et9wHYG8mlc/myB0C8yE/oo3aTTCETaXZO6077jRWLDUj35aFQHAI4pN2QSG+heuS/+7uRHmaJ8FQ32nkOYc5+lNI6V7VbQu4lyX2W9y92NN6KBFirs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613748329; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LuIzTpv1K9soe7A7vEz88fSEr4MLHte1voPUCjxmGG8=; b=FjBm56OuJTUP3pcevY6+aqM4uxomzCbp/YDzcab96uyjeBEa84npEc3UdC6Kq0WtK8/PPmff1qu+mrywgqX/xsdnc3fKnSX43VwAU/IeP6CLhgyOf+IJ/Wlszyb9RG3QpO0oSvrt+SNGgRiRoggYKm2KV43rO13McaeZM8BMBiU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613748328896858.6529820595545; Fri, 19 Feb 2021 07:25:28 -0800 (PST) Received: from localhost ([::1]:34306 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7em-0003oQ-QC for importer@patchew.org; Fri, 19 Feb 2021 10:25:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34440) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD746-0002wO-2r for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:30 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:52383) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73U-0003gj-3J for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:29 -0500 Received: by mail-wm1-x32a.google.com with SMTP id l17so7298303wmq.2 for ; Fri, 19 Feb 2021 06:46:51 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LuIzTpv1K9soe7A7vEz88fSEr4MLHte1voPUCjxmGG8=; b=ttmgN8WXfodvQ2pdgMfpyYBtddWI9FGGr8+qqJK2H7KxvaumT0QrnkkT2HY1HXvrsc ryrFL+4IwCXI9ZjzL1D1n9Tn8QXZb6DxFEHd9Sl8nzHWmaIUx8YlmLbNSuXmAxsR0HJl aAziqUDE45D6Xo2Xx11EVQQyTo4GVpc6x8jdvekkXLeOO1saSvBDYfNAImBJ6G5Lmvmy y9rlHusp4L5OX2KuaH1SJIq2e913ATV23EHYmaX7X+leggyu+W1zPm1bhcDP8bgHhygI Hm35yEpNdPSZ6C4IaBNjy5TsXeo2ncVj5Vnj7IhU6/nVtEtX1li1PNjGB6W2t7mu+WDV LKig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LuIzTpv1K9soe7A7vEz88fSEr4MLHte1voPUCjxmGG8=; b=Zf8Rjn16e5aSY6q0WVWL4e+nKaUeqC0ATlfMzOhjF36o7xuBZXxm/r2LVaDGtC4wM3 /vQXNCk/l9HwIQEVdDR3VdrbwLgskq9uilC9ijYgGyy4xX1tHjYbdRke5dei2NnGmSne IAe/ck7CmZzOh4ThK6nTwRndNfeQcDdcpWj3n0drquqsFWqxKnTXpm3Kf0eP73B1CzEf xbuQQwbS6EjbmIp4eGhYOzPyemhAbpdnJO1LAqdNs7KWJR7QSUZAOKf1Dqi8qs5dLdR7 0O0UzLEBa8idZIHR5veGUTC4CIJiPOdaqvXah+oGTB/MGoTSc8/X6j9vaS5452XYmvTW 420Q== X-Gm-Message-State: AOAM532OOj+f3gP2zPv5Vqyn7bpPbpDUN2Zo6wEZ8Mn4r/GZ7U6i16b7 Y5dN2lbyY7ewxPnb/WHQO4xiLw== X-Google-Smtp-Source: ABdhPJyOmz8gNiaUdqWoC9/o39wNleXHNQbIw326cBOYBsdlPP+RkVlo95I2FS6ogytTH0lsm3M69A== X-Received: by 2002:a1c:2b05:: with SMTP id r5mr8438318wmr.179.1613746010665; Fri, 19 Feb 2021 06:46:50 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 41/44] hw/arm/mps2-tz: Make initsvtor0 setting board-specific Date: Fri, 19 Feb 2021 14:46:14 +0000 Message-Id: <20210219144617.4782-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The AN547 configures the SSE-300 with a different initsvtor0 setting from its default; make this a board-specific setting. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 47215f1b97c..bb72f78fb55 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -114,6 +114,7 @@ struct MPS2TZMachineClass { bool fpgaio_has_dbgctrl; /* Does FPGAIO have DBGCTRL register? */ int numirq; /* Number of external interrupts */ int uart_overflow_irq; /* number of the combined UART overflow IRQ */ + uint32_t init_svtor; /* init-svtor setting for SSE */ const RAMInfo *raminfo; const char *armsse_type; }; @@ -690,6 +691,7 @@ static void mps2tz_common_init(MachineState *machine) object_property_set_link(OBJECT(&mms->iotkit), "memory", OBJECT(system_memory), &error_abort); qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); + qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor); qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); @@ -1043,6 +1045,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, = void *data) mmc->fpgaio_has_dbgctrl =3D false; mmc->numirq =3D 92; mmc->uart_overflow_irq =3D 47; + mmc->init_svtor =3D 0x10000000; mmc->raminfo =3D an505_raminfo; mmc->armsse_type =3D TYPE_IOTKIT; mps2tz_set_default_ram_info(mmc); @@ -1069,6 +1072,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, = void *data) mmc->fpgaio_has_dbgctrl =3D false; mmc->numirq =3D 92; mmc->uart_overflow_irq =3D 47; + mmc->init_svtor =3D 0x10000000; mmc->raminfo =3D an505_raminfo; /* AN521 is the same as AN505 here */ mmc->armsse_type =3D TYPE_SSE200; mps2tz_set_default_ram_info(mmc); @@ -1095,6 +1099,7 @@ static void mps3tz_an524_class_init(ObjectClass *oc, = void *data) mmc->fpgaio_has_dbgctrl =3D false; mmc->numirq =3D 95; mmc->uart_overflow_irq =3D 47; + mmc->init_svtor =3D 0x10000000; mmc->raminfo =3D an524_raminfo; mmc->armsse_type =3D TYPE_SSE200; mps2tz_set_default_ram_info(mmc); --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613748446; cv=none; d=zohomail.com; s=zohoarc; b=aoplitPIwH/oGcFBKd+GnjBuCkoOg5BV2ky/YImNUr70jiqLV3VK4SBot+tGG2YtGjuveVjtJirEUvvwxTM36sV4ZgKF2aIWlrwh4N8grCjrSxW9POEL3wYw+sZXJ9DE4lbOfNGSyulBEzSh3EAb71DYBee7kxUI9IH2iQAbvlg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613748446; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cLMZo6jufPdvkgmcFJXx7AYUcA7XP1lsTzcJqm42xg4=; b=QJzlUz0Unj6iK304ewRfrr6OkTnCLYi/OA/ztySFLvlgSyR+pGZxkEa7DY3vC8VNMj8/Jo1Eu6eEQFuKBdNJX8ZsGQVDqOfstUNPvrpTQqSj7BDNjTpbV7fQ2yUukxSbHG2JijtS2oS5X9uIEOCeYfuooutijPbSNi0yqEqnlS0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613748445623582.2175887670146; Fri, 19 Feb 2021 07:27:25 -0800 (PST) Received: from localhost ([::1]:43076 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7gi-0007YR-CK for importer@patchew.org; Fri, 19 Feb 2021 10:27:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34466) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD746-0002x0-Sv for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:30 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:35873) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73U-0003h0-NJ for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:30 -0500 Received: by mail-wm1-x32c.google.com with SMTP id a207so7911423wmd.1 for ; Fri, 19 Feb 2021 06:46:52 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cLMZo6jufPdvkgmcFJXx7AYUcA7XP1lsTzcJqm42xg4=; b=XBO+MWbQ243Bfa4AHVjedLMF53Bkvn/dKcAVB48kXkmSGDZdQZIHzT5FPRaKhvMi02 BgovK9WJkxVvNa1n303PLM6+RIp+D399VLbOIqi3NlqC6vIQ9UxmKc8gJxv7fQ7Kxhsb OtyPkbc86xdjYLu2IuuW4JX4UKM7oV7Hgxk2fXqDuHWhe/B4iz6zjoWb2SVEVOTP20G7 R2PV7Hv+cRM7BqhRudhDZObbdX8Gsj8a2DXHC5hLT3Ml+rQ5j8gn0OOJLz+0jIEdIQiU 8OKxLjGxaA0eCVueZK9wqL9JkOxQHzgBAX8MYmx1q9ZzUoKBQPxzMhsW8UMuXPOkc2zT yxtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cLMZo6jufPdvkgmcFJXx7AYUcA7XP1lsTzcJqm42xg4=; b=ZPTGz61nZZnSLmfLGLWV+xup5K/xg/Jh3kxcQNL5FWHEze9f2nSSbHyGYLFK4PNeSc 69jq8Gm3TXjyt3xTtw6Vju+Mu1pRzYpKVIMwCTibCuwIvyoG02yfZCmXXFWH3gl3/RjU nTNTrSO+0MO14tHSuXPjlvYGtTVD9/RsauZAMSr6zICBaCmO/AFASPz/fXff4Oz8vPQX G7wHHZFsk2in4UIKRbrn5PX9L6ONiukRulQS3q8Cf44bGvPp6zSjeeEQE3rf4LCBsxzl 6QLZ5RfiuH88w1bzlMaxLQ/l6SPHKckip87I/mcg26MDJ7OuPsaPB0X++RAORDK6fL+L +hHg== X-Gm-Message-State: AOAM531SEhxoLu0uSKBOhRib5KMC5Z9fLBMVQJhb70b1/5faG4oR1FSR qe0eQS2jRVnSZIRHo/ja/KBHHA== X-Google-Smtp-Source: ABdhPJz8PV6gF9AdZNwwDclGwWFJYe5l+i2Zl7QSH7KtfmN9YafhyGu0ImpZWPlgNPMkfPJ7vVH+mQ== X-Received: by 2002:a05:600c:4fd0:: with SMTP id o16mr7671589wmq.77.1613746011437; Fri, 19 Feb 2021 06:46:51 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 42/44] hw/arm/mps2-tz: Add new mps3-an547 board Date: Fri, 19 Feb 2021 14:46:15 +0000 Message-Id: <20210219144617.4782-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Add support for the mps3-an547 board; this is an SSE-300 based FPGA image that runs on the MPS3. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 146 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 144 insertions(+), 2 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index bb72f78fb55..a1f43555013 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -17,6 +17,7 @@ * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524 + * "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN= 547 * * Links to the TRM for the board itself and to the various Application * Notes which document the FPGA images can be found here: @@ -30,6 +31,8 @@ * https://developer.arm.com/documentation/dai0521/latest/ * Application Note AN524: * https://developer.arm.com/documentation/dai0524/latest/ + * Application Note AN547: + * https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI05= 47B_SSE300_PLUS_U55_FPGA_for_mps3.pdf * * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Gu= ide * (ARM ECM0601256) for the details of some of the device layout: @@ -37,6 +40,8 @@ * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM def= ines * most of the device layout: * https://developer.arm.com/documentation/101104/latest/ + * and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM: + * https://developer.arm.com/documentation/101773/latest/ */ =20 #include "qemu/osdep.h" @@ -68,13 +73,14 @@ #include "hw/qdev-clock.h" #include "qom/object.h" =20 -#define MPS2TZ_NUMIRQ_MAX 95 -#define MPS2TZ_RAM_MAX 4 +#define MPS2TZ_NUMIRQ_MAX 96 +#define MPS2TZ_RAM_MAX 5 =20 typedef enum MPS2TZFPGAType { FPGA_AN505, FPGA_AN521, FPGA_AN524, + FPGA_AN547, } MPS2TZFPGAType; =20 /* @@ -153,6 +159,7 @@ struct MPS2TZMachineState { #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") #define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524") +#define TYPE_MPS3TZ_AN547_MACHINE MACHINE_TYPE_NAME("mps3-an547") =20 OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) =20 @@ -242,6 +249,49 @@ static const RAMInfo an524_raminfo[] =3D { { }, }; =20 +static const RAMInfo an547_raminfo[] =3D { { + .name =3D "itcm", + .base =3D 0x00000000, + .size =3D 512 * KiB, + .mpc =3D -1, + .mrindex =3D 0, + }, { + .name =3D "sram", + .base =3D 0x01000000, + .size =3D 2 * MiB, + .mpc =3D 0, + .mrindex =3D 1, + }, { + .name =3D "dtcm", + .base =3D 0x20000000, + .size =3D 4 * 128 * KiB, + .mpc =3D -1, + .mrindex =3D 2, + }, { + .name =3D "sram 2", + .base =3D 0x21000000, + .size =3D 4 * MiB, + .mpc =3D -1, + .mrindex =3D 3, + }, { + /* We don't model QSPI flash yet; for now expose it as simple ROM = */ + .name =3D "QSPI", + .base =3D 0x28000000, + .size =3D 8 * MiB, + .mpc =3D 1, + .mrindex =3D 4, + .flags =3D IS_ROM, + }, { + .name =3D "DDR", + .base =3D 0x60000000, + .size =3D 2 * GiB, + .mpc =3D 2, + .mrindex =3D -1, + }, { + .name =3D NULL, + }, +}; + static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mp= c) { MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); @@ -883,6 +933,55 @@ static void mps2tz_common_init(MachineState *machine) }, }; =20 + const PPCInfo an547_ppcs[] =3D { { + .name =3D "apb_ppcexp0", + .ports =3D { + { "ssram-mpc", make_mpc, &mms->mpc[0], 0x57000000, 0x1000 = }, + { "qspi-mpc", make_mpc, &mms->mpc[1], 0x57001000, 0x1000 }, + { "ddr-mpc", make_mpc, &mms->mpc[2], 0x57002000, 0x1000 }, + }, + }, { + .name =3D "apb_ppcexp1", + .ports =3D { + { "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000 }, + { "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000 }, + { "spi0", make_spi, &mms->spi[0], 0x49202000, 0x1000, { 53= } }, + { "spi1", make_spi, &mms->spi[1], 0x49203000, 0x1000, { 54= } }, + { "spi2", make_spi, &mms->spi[2], 0x49204000, 0x1000, { 55= } }, + { "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000 }, + { "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000 }, + { /* port 7 reserved */ }, + { "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000 }, + }, + }, { + .name =3D "apb_ppcexp2", + .ports =3D { + { "scc", make_scc, &mms->scc, 0x49300000, 0x1000 }, + { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 0x49301000= , 0x1000 }, + { "fpgaio", make_fpgaio, &mms->fpgaio, 0x49302000, 0x1000 = }, + { "uart0", make_uart, &mms->uart[0], 0x49303000, 0x1000, {= 33, 34, 43 } }, + { "uart1", make_uart, &mms->uart[1], 0x49304000, 0x1000, {= 35, 36, 44 } }, + { "uart2", make_uart, &mms->uart[2], 0x49305000, 0x1000, {= 37, 38, 45 } }, + { "uart3", make_uart, &mms->uart[3], 0x49306000, 0x1000, {= 39, 40, 46 } }, + { "uart4", make_uart, &mms->uart[4], 0x49307000, 0x1000, {= 41, 42, 47 } }, + { "uart5", make_uart, &mms->uart[5], 0x49308000, 0x1000, {= 125, 126, 127 } }, + + { /* port 9 reserved */ }, + { "clcd", make_unimp_dev, &mms->cldc, 0x4930a000, 0x1000 }, + { "rtc", make_rtc, &mms->rtc, 0x4930b000, 0x1000 }, + }, + }, { + .name =3D "ahb_ppcexp0", + .ports =3D { + { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x10= 00 }, + { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x10= 00 }, + { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x10= 00 }, + { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x10= 00 }, + { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 4= 9 } }, + }, + }, + }; + switch (mmc->fpga_type) { case FPGA_AN505: case FPGA_AN521: @@ -893,6 +992,10 @@ static void mps2tz_common_init(MachineState *machine) ppcs =3D an524_ppcs; num_ppcs =3D ARRAY_SIZE(an524_ppcs); break; + case FPGA_AN547: + ppcs =3D an547_ppcs; + num_ppcs =3D ARRAY_SIZE(an547_ppcs); + break; default: g_assert_not_reached(); } @@ -971,6 +1074,11 @@ static void mps2tz_common_init(MachineState *machine) =20 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); =20 + if (mmc->fpga_type =3D=3D FPGA_AN547) { + create_unimplemented_device("U55 timing adapter 0", 0x48102000, 0x= 1000); + create_unimplemented_device("U55 timing adapter 1", 0x48103000, 0x= 1000); + } + create_non_mpc_ram(mms); =20 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, @@ -1105,6 +1213,33 @@ static void mps3tz_an524_class_init(ObjectClass *oc,= void *data) mps2tz_set_default_ram_info(mmc); } =20 +static void mps3tz_an547_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_CLASS(oc); + + mc->desc =3D "ARM MPS3 with AN547 FPGA image for Cortex-M55"; + mc->default_cpus =3D 1; + mc->min_cpus =3D mc->default_cpus; + mc->max_cpus =3D mc->default_cpus; + mmc->fpga_type =3D FPGA_AN547; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m55"); + mmc->scc_id =3D 0x41055470; + mmc->sysclk_frq =3D 32 * 1000 * 1000; /* 32MHz */ + mmc->apb_periph_frq =3D 25 * 1000 * 1000; /* 25MHz */ + mmc->oscclk =3D an524_oscclk; /* same as AN524 */ + mmc->len_oscclk =3D ARRAY_SIZE(an524_oscclk); + mmc->fpgaio_num_leds =3D 10; + mmc->fpgaio_has_switches =3D true; + mmc->fpgaio_has_dbgctrl =3D true; + mmc->numirq =3D 96; + mmc->uart_overflow_irq =3D 48; + mmc->init_svtor =3D 0x00000000; + mmc->raminfo =3D an547_raminfo; + mmc->armsse_type =3D TYPE_SSE300; + mps2tz_set_default_ram_info(mmc); +} + static const TypeInfo mps2tz_info =3D { .name =3D TYPE_MPS2TZ_MACHINE, .parent =3D TYPE_MACHINE, @@ -1136,12 +1271,19 @@ static const TypeInfo mps3tz_an524_info =3D { .class_init =3D mps3tz_an524_class_init, }; =20 +static const TypeInfo mps3tz_an547_info =3D { + .name =3D TYPE_MPS3TZ_AN547_MACHINE, + .parent =3D TYPE_MPS2TZ_MACHINE, + .class_init =3D mps3tz_an547_class_init, +}; + static void mps2tz_machine_init(void) { type_register_static(&mps2tz_info); type_register_static(&mps2tz_an505_info); type_register_static(&mps2tz_an521_info); type_register_static(&mps3tz_an524_info); + type_register_static(&mps3tz_an547_info); } =20 type_init(mps2tz_machine_init); --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613748166139594.9806645933422; Fri, 19 Feb 2021 07:22:46 -0800 (PST) Received: from localhost ([::1]:54384 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7cC-0008Hn-13 for importer@patchew.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=HCUP9aHI+eQ+pUUZGOO1dNsG+dvoHvU/fP6me+Xsa6A=; b=Hrsv3BiFoTZ+BiUKC5Hm/vCDuCK9HBxhaS+Sv4qAxP2d39CkY3gPB1mfYr/o/TtNAS HziB0W9yYocJDO16Esiv/HJYp+ZEwLQQvq5m25gJk93Txy8X+InsveqMJHT4nQ4+w0K5 dq3VC+CE0MmwQxqzvI1DaN+7C7dRgKkKWcnuJLV1dPPYbWVR3SgMD2IZDGUhLFrVQdo4 BFm8zfAA0PMzmuMQMfbyFMDsvjeXQS5pAAbQDYOexkxtnuD8APlghkFBobkdLe0knz66 IomdlT6Y1SDDeCGyHhxXKrDTM1Nfw6uzfXLdNfxqOshD+sgbKEH4wZPhyvkavEEkR2cl wSzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HCUP9aHI+eQ+pUUZGOO1dNsG+dvoHvU/fP6me+Xsa6A=; b=H+UTMbuszcJ+9n4IiY0VFPfLjOzV23nVbuyF17ZfiMGFV3o5X4yUKge7vSdflBW/tD 0xDVZDOzo+v/aC03Buji/zo8AFC4+xg080YVnFdBeumTLFKiJzVUm3/ckTvEXlFpJxbV x9cq6F+VxCqo489aGqWDoirW71AhmJwClaOTmjyToEOu9hI5PPunbz97DbxNjYg/kWcs iuBEAhUR6Yxwv/4usXeGvUQaCYD8tQWH0zer5ntKfPxsTbdqQr8gqdZFgOfPv9tcX0QP iH6/1kcZ1GbEbF+FT0kf9kwAbmGirdZMnYANu5ODK42kFa4qEUVCKtFzHsVvaJZgfken RXtg== X-Gm-Message-State: AOAM531pboz7qrm/4xJfX5sON1Me5wH62NCNays2Ap4dnrzoZU+w3in6 sohvKRuvUzkR2zGo8n38u02K9hQBX60jlw== X-Google-Smtp-Source: ABdhPJxltp0pPj0JX/xMUddZvXenA9vBvR3rdW9gHv/bt/XpKnLzsI5P/6zCqJa+Xdy8UdV6touMzQ== X-Received: by 2002:a7b:c341:: with SMTP id l1mr8345714wmj.182.1613746012193; Fri, 19 Feb 2021 06:46:52 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 43/44] docs/system/arm/mps2.rst: Document the new mps3-an547 board Date: Fri, 19 Feb 2021 14:46:16 +0000 Message-Id: <20210219144617.4782-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Add brief documentation of the new mps3-an547 board. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- docs/system/arm/mps2.rst | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index 601ccea15cb..f83b1517871 100644 --- a/docs/system/arm/mps2.rst +++ b/docs/system/arm/mps2.rst @@ -1,5 +1,5 @@ -Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, = ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, = ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an54= 7``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =20 These board models all use Arm M-profile CPUs. =20 @@ -27,6 +27,8 @@ QEMU models the following FPGA images: Dual Cortex-M33 as documented in Arm Application Note AN521 ``mps3-an524`` Dual Cortex-M33 on an MPS3, as documented in Arm Application Note AN524 +``mps3-an547`` + Cortex-M55 on an MPS3, as documented in Arm Application Note AN547 =20 Differences between QEMU and real hardware: =20 --=20 2.20.1 From nobody Fri May 10 05:24:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613748598; cv=none; d=zohomail.com; s=zohoarc; b=gKMIyRFkZ98qsk8n7AZmkpGAQAKu+vlDjyWnE5eGm3YD6TMyqL8S+u/vF6suP/PzcsCTHF10EuV5h+q8coWUuWT/aZLkcno9/oRXPwA8ZtdH6nVjnWtn+M1DqdC0wKrlQqGQ8CLcEsF3PteW0nkoktzLM9biBUz1bMqZguLK6GI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613748598; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HopB4K6K7gngGK+esxc0vMVA1U5d8Hljyo+ikSSKGQk=; b=VE17As6+48HBDgbO69svLa576VCpdguq5M3MKJH9frzHVwTRkX5ryMM1vPLjWKmboSOYPmmhYci1/m12ia813sCC/A4tS4/HYI4bOrVnEkExjZIEju5zLoyfEau7qq9nofzTg8PPMNv+JWxZWufo3ceAu7p3x4+xFmiTKBAV9dE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613748598254422.9222097903879; Fri, 19 Feb 2021 07:29:58 -0800 (PST) Received: from localhost ([::1]:51666 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD7j8-0002m9-Vf for importer@patchew.org; Fri, 19 Feb 2021 10:29:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34516) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD74D-0002ya-6L for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:37 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:38707) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD73X-0003hb-Tz for qemu-devel@nongnu.org; Fri, 19 Feb 2021 09:47:35 -0500 Received: by mail-wm1-x32d.google.com with SMTP id x4so7882614wmi.3 for ; Fri, 19 Feb 2021 06:46:53 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q18sm2263628wrw.91.2021.02.19.06.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 06:46:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=HopB4K6K7gngGK+esxc0vMVA1U5d8Hljyo+ikSSKGQk=; b=hevCP3IoDNB5HotbfDN76S7xTvg35sT0OB8JzZpXfjqIOh8ua9l1kMHREgG4PWq83T gw29ieXKMMWmY+AzwhH6yS2/kqSeaeW5xKwTXjNvaqmQvI2Dyjkyjxbrh0/l4FlpBWpi g9Zgh+F0IcYqQxdJd6zcEA6sOYoM09b39caWZWDKrYOMvsBhLWp5ya+59iVxqcB2JB9p 81+ZcXSRgqd/NRG7doAqPBZIQlKu6W7JGsGwd4tRxTcdMSosmfEkWLJjXS31MPDR/Pun 32uH1VSzCVdktk/3WhL+xDVsz+oUDeJtf+74Xf/veatG0oU8onfBTS1y9c958RaUOaGk Og/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HopB4K6K7gngGK+esxc0vMVA1U5d8Hljyo+ikSSKGQk=; b=JlIBFM9VCggrm8KZQVMXmBJeLBBd4tbGfXUzhfw/wYdEbRIn/twNYsvgR+JIcG41ob S1mozPl15rtByj0B+0Mdd0xyN+oD4+2OwF7WcIbBlQTg+1z6JYK1oph0m7BhU6RYEjeJ Zt2+uCoTtbvZspRtvmq3hvKZ8kNaODXdnS3iHPqvUl7qzXbaqHb0MbqpKyKMJAn5j1IJ GMpwbk45qNVDV3ycld8IFxDCQFomjtiBg8klxclwQtmMlQjERuWv5lBMiI8Ur7dmJSBc 2nuVG4ymvODoOwmB1PB+H0FxoqdPMwBL2g0OhYh/mg38qEaC4Lss4fPYon9M+6bzOUhZ 4JvA== X-Gm-Message-State: AOAM531wc6+OKczOnh9cgAeWA51bITZ2dj2KGVd/CzMQxccVsaIZerIn XrmpJUCzBrrMEq/q6688PwQkXqjt3CL/vA== X-Google-Smtp-Source: ABdhPJzwiLFboiAIqhe/U0NYLFyNUlkFU37DPNGxByzC0s2SgOodt+1wJai0QvrkcuIYbboIP3Y+jg== X-Received: by 2002:a1c:b607:: with SMTP id g7mr8525222wmf.67.1613746012939; Fri, 19 Feb 2021 06:46:52 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 44/44] tests/qtest/sse-timer-test: Add simple tests of the SSE timer and counter Date: Fri, 19 Feb 2021 14:46:17 +0000 Message-Id: <20210219144617.4782-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210219144617.4782-1-peter.maydell@linaro.org> References: <20210219144617.4782-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Add a simple qtest to exercise the new system counter and system timer device in the SSE-300. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- tests/qtest/sse-timer-test.c | 240 +++++++++++++++++++++++++++++++++++ MAINTAINERS | 1 + tests/qtest/meson.build | 1 + 3 files changed, 242 insertions(+) create mode 100644 tests/qtest/sse-timer-test.c diff --git a/tests/qtest/sse-timer-test.c b/tests/qtest/sse-timer-test.c new file mode 100644 index 00000000000..cb29c995077 --- /dev/null +++ b/tests/qtest/sse-timer-test.c @@ -0,0 +1,240 @@ +/* + * QTest testcase for the SSE timer device + * + * Copyright (c) 2021 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +/* + * SSE-123/SSE-300 timer in the mps3-an547 board, where it is driven + * at 32MHz, so 31.25ns per tick. + */ +#define TIMER_BASE 0x48000000 + +/* PERIPHNSPPC0 register in the SSE-300 Secure Access Configuration block = */ +#define PERIPHNSPPC0 (0x50080000 + 0x70) + +/* Base of the System Counter control frame */ +#define COUNTER_BASE 0x58100000 + +/* SSE counter register offsets in the control frame */ +#define CNTCR 0 +#define CNTSR 0x4 +#define CNTCV_LO 0x8 +#define CNTCV_HI 0xc +#define CNTSCR 0x10 + +/* SSE timer register offsets */ +#define CNTPCT_LO 0 +#define CNTPCT_HI 4 +#define CNTFRQ 0x10 +#define CNTP_CVAL_LO 0x20 +#define CNTP_CVAL_HI 0x24 +#define CNTP_TVAL 0x28 +#define CNTP_CTL 0x2c +#define CNTP_AIVAL_LO 0x40 +#define CNTP_AIVAL_HI 0x44 +#define CNTP_AIVAL_RELOAD 0x48 +#define CNTP_AIVAL_CTL 0x4c + +/* 4 ticks in nanoseconds (so we can work in integers) */ +#define FOUR_TICKS 125 + +static void clock_step_ticks(uint64_t ticks) +{ + /* + * Advance the qtest clock by however many nanoseconds we + * need to move the timer forward the specified number of ticks. + * ticks must be a multiple of 4, so we get a whole number of ns. + */ + assert(!(ticks & 3)); + clock_step(FOUR_TICKS * (ticks >> 2)); +} + +static void reset_counter_and_timer(void) +{ + /* + * Reset the system counter and the timer between tests. This + * isn't a full reset, but it's sufficient for what the tests check. + */ + writel(COUNTER_BASE + CNTCR, 0); + writel(TIMER_BASE + CNTP_CTL, 0); + writel(TIMER_BASE + CNTP_AIVAL_CTL, 0); + writel(COUNTER_BASE + CNTCV_LO, 0); + writel(COUNTER_BASE + CNTCV_HI, 0); +} + +static void test_timer(void) +{ + /* Basic timer functionality test */ + + reset_counter_and_timer(); + /* + * The timer is behind a Peripheral Protection Controller, and + * qtest accesses are always non-secure (no memory attributes), + * so we must program the PPC to accept NS transactions. TIMER0 + * is on port 0 of PPC0, controlled by bit 0 of this register. + */ + writel(PERIPHNSPPC0, 1); + /* We must enable the System Counter or the timer won't run. */ + writel(COUNTER_BASE + CNTCR, 1); + + /* Timer starts disabled and with a counter of 0 */ + g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), =3D=3D, 0); + g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_LO), =3D=3D, 0); + g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_HI), =3D=3D, 0); + + /* Turn it on */ + writel(TIMER_BASE + CNTP_CTL, 1); + + /* Is the timer ticking? */ + clock_step_ticks(100); + g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_LO), =3D=3D, 100); + g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_HI), =3D=3D, 0); + + /* Set the CompareValue to 4000 ticks */ + writel(TIMER_BASE + CNTP_CVAL_LO, 4000); + writel(TIMER_BASE + CNTP_CVAL_HI, 0); + + /* Check TVAL view of the counter */ + g_assert_cmpuint(readl(TIMER_BASE + CNTP_TVAL), =3D=3D, 3900); + + /* Advance to the CompareValue mark and check ISTATUS is set */ + clock_step_ticks(3900); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_TVAL), =3D=3D, 0); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), =3D=3D, 5); + + /* Now exercise the auto-reload part of the timer */ + writel(TIMER_BASE + CNTP_AIVAL_RELOAD, 200); + writel(TIMER_BASE + CNTP_AIVAL_CTL, 1); + + /* Check AIVAL was reloaded and that ISTATUS is now clear */ + g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_LO), =3D=3D, 4200); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_HI), =3D=3D, 0); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), =3D=3D, 1); + + /* + * Check that when we advance forward to the reload time the interrupt + * fires and the value reloads + */ + clock_step_ticks(100); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), =3D=3D, 1); + clock_step_ticks(100); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), =3D=3D, 5); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_LO), =3D=3D, 4400); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_HI), =3D=3D, 0); + + clock_step_ticks(100); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), =3D=3D, 5); + /* Check that writing 0 to CLR clears the interrupt */ + writel(TIMER_BASE + CNTP_AIVAL_CTL, 1); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), =3D=3D, 1); + /* Check that when we move forward to the reload time it fires again */ + clock_step_ticks(100); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), =3D=3D, 5); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_LO), =3D=3D, 4600); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_HI), =3D=3D, 0); + + /* + * Step the clock far enough that we overflow the low half of the + * CNTPCT and AIVAL registers, and check that their high halves + * give the right values. We do the forward movement in + * non-autoinc mode because otherwise it takes forever as the + * timer has to emulate all the 'reload at t + N, t + 2N, etc' + * steps. + */ + writel(TIMER_BASE + CNTP_AIVAL_CTL, 0); + clock_step_ticks(0x42ULL << 32); + g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_LO), =3D=3D, 4400); + g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_HI), =3D=3D, 0x42); + + /* Turn on the autoinc again to check AIVAL_HI */ + writel(TIMER_BASE + CNTP_AIVAL_CTL, 1); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_LO), =3D=3D, 4600); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_HI), =3D=3D, 0x42); +} + +static void test_counter(void) +{ + /* Basic counter functionality test */ + + reset_counter_and_timer(); + /* The counter should start disabled: check that it doesn't move */ + clock_step_ticks(100); + g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_LO), =3D=3D, 0); + g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_HI), =3D=3D, 0); + /* Now enable it and check that it does count */ + writel(COUNTER_BASE + CNTCR, 1); + clock_step_ticks(100); + g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_LO), =3D=3D, 100); + g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_HI), =3D=3D, 0); + /* Check the counter scaling functionality */ + writel(COUNTER_BASE + CNTCR, 0); + writel(COUNTER_BASE + CNTSCR, 0x00100000); /* 1/16th normal speed */ + writel(COUNTER_BASE + CNTCR, 5); /* EN, SCEN */ + clock_step_ticks(160); + g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_LO), =3D=3D, 110); + g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_HI), =3D=3D, 0); +} + +static void test_timer_scale_change(void) +{ + /* + * Test that the timer responds correctly to counter + * scaling changes while it has an active timer. + */ + reset_counter_and_timer(); + /* Give ourselves access to the timer, and enable the counter and time= r */ + writel(PERIPHNSPPC0, 1); + writel(COUNTER_BASE + CNTCR, 1); + writel(TIMER_BASE + CNTP_CTL, 1); + /* Set the CompareValue to 4000 ticks */ + writel(TIMER_BASE + CNTP_CVAL_LO, 4000); + writel(TIMER_BASE + CNTP_CVAL_HI, 0); + /* Advance halfway and check ISTATUS is not set */ + clock_step_ticks(2000); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), =3D=3D, 1); + /* Reprogram the counter to run at 1/16th speed */ + writel(COUNTER_BASE + CNTCR, 0); + writel(COUNTER_BASE + CNTSCR, 0x00100000); /* 1/16th normal speed */ + writel(COUNTER_BASE + CNTCR, 5); /* EN, SCEN */ + /* Advance to where the timer would have fired and check it has not */ + clock_step_ticks(2000); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), =3D=3D, 1); + /* Advance to where the timer must fire at the new clock rate */ + clock_step_ticks(29996); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), =3D=3D, 1); + clock_step_ticks(4); + g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), =3D=3D, 5); +} + +int main(int argc, char **argv) +{ + int r; + + g_test_init(&argc, &argv, NULL); + + qtest_start("-machine mps3-an547"); + + qtest_add_func("/sse-timer/timer", test_timer); + qtest_add_func("/sse-timer/counter", test_counter); + qtest_add_func("/sse-timer/timer-scale-change", test_timer_scale_chang= e); + + r =3D g_test_run(); + + qtest_end(); + + return r; +} diff --git a/MAINTAINERS b/MAINTAINERS index c2103b40b9b..cbe790add60 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -748,6 +748,7 @@ F: hw/timer/sse-counter.c F: include/hw/timer/sse-counter.h F: hw/timer/sse-timer.c F: include/hw/timer/sse-timer.h +F: tests/qtest/sse-timer-test.c F: docs/system/arm/mps2.rst =20 Musca diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index c83bc211b6a..f38ebbf67c3 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -142,6 +142,7 @@ qtests_npcm7xx =3D \ 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] qtests_arm =3D \ + (config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-= dualtimer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-time= r-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-w= atchdog-test'] : []) + \ --=20 2.20.1