From nobody Mon Feb 9 11:06:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1613727963; cv=none; d=zohomail.com; s=zohoarc; b=lwDWX1KV6lPGUnno+Y7SQs4pHhevPbx87mecnyBT3CZlTszyOoyQIQKMimhMbWUCjAtVIFE8vSLFER54Uc+zhNr2ZKvbiCdBqkFRZprNdINujsUBX1MZaERj6t6Qf4/1Ej/wa84KzE2UXqdqLICZcKzh/lBdXhOX6OVv+ngKX5g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613727963; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Edqe9ZnW3DVTj8Eub5reroCfukexcRMjO9kEeLsxbuc=; b=G41JLHMPm14bJp9392lugioIvuatwMS365l6TuEeJCJaLliXc+6Tpokapev7cFeafnryZO+hGrIBJWH6KcRCVuR5ZwI3D1TpXBlP+RcN8lLDmZojCmmfMoauZeaXu3+xtXZYmoWxTGrAZmYRCY0Twi18oEM69WOj47ZZs9Jtt2c= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613727962727177.95174963245586; Fri, 19 Feb 2021 01:46:02 -0800 (PST) Received: from localhost ([::1]:59078 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD2ML-0002ce-JN for importer@patchew.org; Fri, 19 Feb 2021 04:46:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44638) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD2KP-0000v6-Sk; Fri, 19 Feb 2021 04:44:02 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:3045) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD2K8-0006Yc-UU; Fri, 19 Feb 2021 04:44:01 -0500 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4Dhmnf0H0DzjNqR; Fri, 19 Feb 2021 17:42:14 +0800 (CST) Received: from DESKTOP-6NKE0BC.china.huawei.com (10.174.185.210) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.498.0; Fri, 19 Feb 2021 17:43:21 +0800 From: Kunkun Jiang To: Eric Auger , Peter Maydell , Alex Williamson , "open list:ARM SMMU" , "open list:All patches CC here" Subject: [RFC PATCH 3/3] hw/arm/smmuv3: Post-load stage 1 configurations to the host Date: Fri, 19 Feb 2021 17:42:30 +0800 Message-ID: <20210219094230.231-4-jiangkunkun@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20210219094230.231-1-jiangkunkun@huawei.com> References: <20210219094230.231-1-jiangkunkun@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.185.210] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.32; envelope-from=jiangkunkun@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zenghui Yu , wanghaibin.wang@huawei.com, Keqian Zhu , shameerali.kolothum.thodi@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" In nested mode, we call the set_pasid_table() callback on each STE update to pass the guest stage 1 configuration to the host and apply it at physical level. In the case of live migration, we need to manual call the set_pasid_table() to load the guest stage 1 configurations to the host. If this operation is fail, the migration is fail. Signed-off-by: Kunkun Jiang --- hw/arm/smmuv3.c | 60 +++++++++++++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 1 + 2 files changed, 61 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 6c6ed84e78..94ca15375c 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1473,6 +1473,65 @@ static void smmu_realize(DeviceState *d, Error **err= p) smmu_init_irq(s, dev); } =20 +static int smmuv3_manual_set_pci_device_pasid_table(SMMUDevice *sdev) +{ +#ifdef __linux__ + IOMMUMemoryRegion *mr =3D &(sdev->iommu); + int sid =3D smmu_get_sid(sdev); + SMMUEventInfo event =3D {.type =3D SMMU_EVT_NONE, .sid =3D sid, + .inval_ste_allowed =3D true}; + IOMMUConfig iommu_config =3D {}; + SMMUTransCfg *cfg; + int ret =3D -1; + + cfg =3D smmuv3_get_config(sdev, &event); + if (!cfg) { + return ret; + } + + iommu_config.pasid_cfg.argsz =3D sizeof(struct iommu_pasid_table_confi= g); + iommu_config.pasid_cfg.version =3D PASID_TABLE_CFG_VERSION_1; + iommu_config.pasid_cfg.format =3D IOMMU_PASID_FORMAT_SMMUV3; + iommu_config.pasid_cfg.base_ptr =3D cfg->s1ctxptr; + iommu_config.pasid_cfg.pasid_bits =3D 0; + iommu_config.pasid_cfg.vendor_data.smmuv3.version =3D PASID_TABLE_SMMU= V3_CFG_VERSION_1; + + if (cfg->disabled || cfg->bypassed) { + iommu_config.pasid_cfg.config =3D IOMMU_PASID_CONFIG_BYPASS; + } else if (cfg->aborted) { + iommu_config.pasid_cfg.config =3D IOMMU_PASID_CONFIG_ABORT; + } else { + iommu_config.pasid_cfg.config =3D IOMMU_PASID_CONFIG_TRANSLATE; + } + + ret =3D pci_device_set_pasid_table(sdev->bus, sdev->devfn, &iommu_conf= ig); + if (ret) { + error_report("Failed to pass PASID table to host for iommu mr %s (= %m)", + mr->parent_obj.name); + } + + return ret; +#endif +} + +static int smmuv3_post_load(void *opaque, int version_id) +{ + SMMUv3State *s3 =3D opaque; + SMMUState *s =3D &(s3->smmu_state); + SMMUDevice *sdev; + int ret =3D 0; + + QLIST_FOREACH(sdev, &s->devices_with_notifiers, next) { + trace_smmuv3_post_load_sdev(sdev->devfn, sdev->iommu.parent_obj.na= me); + ret =3D smmuv3_manual_set_pci_device_pasid_table(sdev); + if (ret) { + break; + } + } + + return ret; +} + static const VMStateDescription vmstate_smmuv3_queue =3D { .name =3D "smmuv3_queue", .version_id =3D 1, @@ -1491,6 +1550,7 @@ static const VMStateDescription vmstate_smmuv3 =3D { .version_id =3D 1, .minimum_version_id =3D 1, .priority =3D MIG_PRI_IOMMU, + .post_load =3D smmuv3_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINT32(features, SMMUv3State), VMSTATE_UINT8(sid_size, SMMUv3State), diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 35e562ab74..caa864dd72 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -53,4 +53,5 @@ smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifi= er node for iommu mr=3D%s smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova, = uint8_t tg, uint64_t num_pages) "iommu mr=3D%s asid=3D%d iova=3D0x%"PRIx64"= tg=3D%d num_pages=3D0x%"PRIx64 smmuv3_notify_config_change(const char *name, uint8_t config, uint64_t s1c= txptr) "iommu mr=3D%s config=3D%d s1ctxptr=3D0x%"PRIx64 +smmuv3_post_load_sdev(int devfn, const char *name) "sdev devfn=3D%d iommu = mr=3D%s"PRIx64 =20 --=20 2.23.0