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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id b83sm4507958wmd.4.2021.02.18.15.29.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Feb 2021 15:29:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HWEzlOjuX0padjF5jmJWlKBlFUrkpDO3sa2VHTewRFM=; b=cfGrCKROdWsp8c+1vxcVc/rxpe5apTe9y67VYuVPhT02OTvyb49jaPz/jVBMWAfUuA A/CRcC4IaAnngaTY3QjW2v7xKD85QUe8XI+DWMQ7PQK9AFM95stso3G38Dzpt/XGUHef Lm3AABQJTheLakwNRMHouC5JXJ48v0AOposy1b4Hk0D52XsVjs4i5XbrHL8Arvf7K5Oq YSj9qwnxG0KSmesmXKh8aEgG0NANmn4o7UHB8t1jGyUZ4ACA1QbvGtch3onSbn/fgPqP odTFMX1Ko7h3xF4b5CV1gaE7ykUYL6hqBJ1Rf+unQov7SrJVB2azclaQjd4l2Tp38U+6 IeJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=HWEzlOjuX0padjF5jmJWlKBlFUrkpDO3sa2VHTewRFM=; b=C8KxK24ECtn4vMZNj1ObezZo/pefdHMA53ecvzoUq9RVU3yE9OK6UZOWFyQfI3sQHs 3BB7gMauGfBXFqZ5XszS5EDx+9ghFstQDWLOZTq57Jl27g5q5QWRhpqBQEjWyrWLJdvU 4KyYgwG5NzzftA7NZlx06aB9TzKOqmm51BGrPjqfZw3+WczMYsemcKrGnUgVT3MC1QK3 X0MxZ2hERuQC/6vFtceubQOOsdNHGsOPAt9dK+DCQWV4+VC6NaQ76i+20gjTfkKEQsLf J7aA70XzthqcdNOpdu8ZxQOsURFiScOBAkjdO5Wvql0UiV3L7Cy6R9iC9HgcXVUhYKRC FBfg== X-Gm-Message-State: AOAM53178wzXZdhiu+9z9c7RJN2xhUCO4BFEtepME3UhlNPXG9TZoqLK rD+ZNiWFlEoiAALTjHtD3Wg= X-Google-Smtp-Source: ABdhPJzkIqVjTK1WpSmMcBlUqsKWoDrgzrHQdtw3ebEeOakCKmm09zT95WzUogU5qo9OpVR+5vQm/Q== X-Received: by 2002:a1c:4b05:: with SMTP id y5mr5539614wma.37.1613690945331; Thu, 18 Feb 2021 15:29:05 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Richard Henderson Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Stefan Weil , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 5/5] tcg/tci: Merge identical cases in generation (load/store opcodes) Date: Fri, 19 Feb 2021 00:28:40 +0100 Message-Id: <20210218232840.1760806-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210218232840.1760806-1-f4bug@amsat.org> References: <20210218232840.1760806-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) From: Richard Henderson Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 5/5] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tci/tcg-target.c.inc | 49 ++++++++++++---------------------------- 1 file changed, 14 insertions(+), 35 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f9893b9539e..c79f9c32d8b 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -440,25 +440,20 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, tcg_out8(s, args[5]); /* condition */ break; #endif - case INDEX_op_ld8u_i32: - case INDEX_op_ld8s_i32: - case INDEX_op_ld16u_i32: - case INDEX_op_ld16s_i32: + + CASE_32_64(ld8u) + CASE_32_64(ld8s) + CASE_32_64(ld16u) + CASE_32_64(ld16s) case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: + CASE_64(ld32u) + CASE_64(ld32s) + CASE_64(ld) + CASE_32_64(st8) + CASE_32_64(st16) case INDEX_op_st_i32: - case INDEX_op_ld8u_i64: - case INDEX_op_ld8s_i64: - case INDEX_op_ld16u_i64: - case INDEX_op_ld16s_i64: - case INDEX_op_ld32u_i64: - case INDEX_op_ld32s_i64: - case INDEX_op_ld_i64: - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: + CASE_64(st32) + CASE_64(st) stack_bounds_check(args[1], args[2]); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); @@ -552,24 +547,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, #endif =20 case INDEX_op_qemu_ld_i32: - tcg_out_r(s, *args++); - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out_i(s, *args++); - break; - case INDEX_op_qemu_ld_i64: - tcg_out_r(s, *args++); - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_r(s, *args++); - } - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out_i(s, *args++); - break; case INDEX_op_qemu_st_i32: tcg_out_r(s, *args++); tcg_out_r(s, *args++); @@ -578,6 +555,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, } tcg_out_i(s, *args++); break; + + case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: tcg_out_r(s, *args++); if (TCG_TARGET_REG_BITS =3D=3D 32) { --=20 2.26.2