From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613593493; cv=none; d=zohomail.com; s=zohoarc; b=Ke5XdLKP6MaJKlSE8v6klXTGqVdppalpjH9b7FLILswAMy18e3rc/vJq7+Zxw5fENUjHLnwhTPZ33aVpQbZFoSUauuS3DidhXxtp4GNaBCAOSpb4Np9y50Be+/ipQH03X8bspfG/CmOWmeEL4+cwWyRTb+G+Gk7tLJrNWlLTv/U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613593493; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ItHqhLdC4sOUBCwiiiRcMM+Q2th6s4A0m8xxVBo1Ego=; b=X0ePGz4QrrPm5sNXYQN9VIeI2/AlGiCtsZrrZxE0DD+Ky6Xkjt9BNDOidSea98AzbIM+Rejxnovxxmbj0srYcK/S3/GHzgju8OAnzDORA8OQNJ6LgJzkNqfJJKyHMqAvtiNY3BY5X3aYjc51kMmYDMs8iMfewy2M9KEAFE6NL34= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613593493494733.350707220566; Wed, 17 Feb 2021 12:24:53 -0800 (PST) Received: from localhost ([::1]:53490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTNU-0001ha-De for importer@patchew.org; Wed, 17 Feb 2021 15:24:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60370) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTJi-0006D2-Qn for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:20:58 -0500 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:35204) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTJh-0006i2-6Q for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:20:58 -0500 Received: by mail-pg1-x52c.google.com with SMTP id t25so9224681pga.2 for ; Wed, 17 Feb 2021 12:20:56 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.20.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:20:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ItHqhLdC4sOUBCwiiiRcMM+Q2th6s4A0m8xxVBo1Ego=; b=fYBvxMpXzbii6KkhMzkkbayjhcohyg2QOHQekpq+hUxR7jCD9JvDw346PULo4DxSe1 DGccktfIsPNuKB8LbGewhATLAyshMNsavCkvCJ3RZjBllmvAcB9V6qmbXGGDndxTf9hy 6iU40iSk9fyWLKvrqdPD5QGG3huzxF2+qn8pg5MK8D9T+FxS6JDi3LcfcAOCI4/Pj5xf 9OQUjd3+BTbtL1YwEYpWSwe/f2SpR0m5E3818PP5Yf18uAkhAK1pUgKl5qL8ajgzTH4G NxR589I0bivC35eVpGl0LnbGFM1ybsH7QlmcBywdIszUpvdd7rHZ0kd8hd5rAPXRDKD3 NV4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ItHqhLdC4sOUBCwiiiRcMM+Q2th6s4A0m8xxVBo1Ego=; b=uayCFLLTNKXcD/ywUpO8L67tyiU6Asur/uLVz1CL1cfsiKYiJa/J6yhmdooS6YpAq9 62G3uX4NwgZQuHqplWXq3ly1SvfPSVRtQvmBJ+zsBhbt6Ngxs3M6DfzThEkTiCHyefyL 1rFK6HI3fBkPIQcZDPzWfZW1htUu44SxTGM5fxwJjc/UsmJGZhMh71FxE4lsihpLG10m /iTy5wsX5jXC84/xnrSAN4O9t+ddMY7faBTNOHiGoIIxPovJgRLywYCktXAXiGwm+hYJ l0Y1E8H6QW2ylc0mhoVaawyeINXJHQEsdN3RsWQmfTM7C/T/uyVCCKIbxwcgknDXU+KS jcxg== X-Gm-Message-State: AOAM531OWbve4NKZzdpr+siyyacy0/2T3JxGJYgiQuuKnqjIjP7vryIO ZAmMfexxv0/wIuyBtNdeP1x9lZke4xKKvQ== X-Google-Smtp-Source: ABdhPJx+8NM9d51SqWnBxdjXgTK9930zr6ffCtHf5SU8Ql0EEqbIBk58fj0aBFBibPCEZsbRilaHnQ== X-Received: by 2002:a63:5525:: with SMTP id j37mr935270pgb.191.1613593255782; Wed, 17 Feb 2021 12:20:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/71] tcg/tci: Use exec/cpu_ldst.h interfaces Date: Wed, 17 Feb 2021 12:19:26 -0800 Message-Id: <20210217202036.1724901-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Use the provided cpu_ldst.h interfaces. This fixes the build vs the unconverted uses of g2h(), adds missed memory trace events, and correctly recognizes when a SIGSEGV belongs to the guest via set_helper_retaddr(). Fixes: 3e8f1628e864 Signed-off-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tci.c | 73 +++++++++++++++++++++---------------------------------- 1 file changed, 28 insertions(+), 45 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index fb3c97aaf1..1c667537fe 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -346,51 +346,34 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, T= CGCond condition) return result; } =20 -#ifdef CONFIG_SOFTMMU -# define qemu_ld_ub \ - helper_ret_ldub_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_leuw \ - helper_le_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_leul \ - helper_le_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_leq \ - helper_le_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_beuw \ - helper_be_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_beul \ - helper_be_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_beq \ - helper_be_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_st_b(X) \ - helper_ret_stb_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_lew(X) \ - helper_le_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_lel(X) \ - helper_le_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_leq(X) \ - helper_le_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_bew(X) \ - helper_be_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_bel(X) \ - helper_be_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_beq(X) \ - helper_be_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -#else -# define qemu_ld_ub ldub_p(g2h(taddr)) -# define qemu_ld_leuw lduw_le_p(g2h(taddr)) -# define qemu_ld_leul (uint32_t)ldl_le_p(g2h(taddr)) -# define qemu_ld_leq ldq_le_p(g2h(taddr)) -# define qemu_ld_beuw lduw_be_p(g2h(taddr)) -# define qemu_ld_beul (uint32_t)ldl_be_p(g2h(taddr)) -# define qemu_ld_beq ldq_be_p(g2h(taddr)) -# define qemu_st_b(X) stb_p(g2h(taddr), X) -# define qemu_st_lew(X) stw_le_p(g2h(taddr), X) -# define qemu_st_lel(X) stl_le_p(g2h(taddr), X) -# define qemu_st_leq(X) stq_le_p(g2h(taddr), X) -# define qemu_st_bew(X) stw_be_p(g2h(taddr), X) -# define qemu_st_bel(X) stl_be_p(g2h(taddr), X) -# define qemu_st_beq(X) stq_be_p(g2h(taddr), X) -#endif +#define qemu_ld_ub \ + cpu_ldub_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_ld_leuw \ + cpu_lduw_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_ld_leul \ + cpu_ldl_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_ld_leq \ + cpu_ldq_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_ld_beuw \ + cpu_lduw_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_ld_beul \ + cpu_ldl_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_ld_beq \ + cpu_ldq_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_b(X) \ + cpu_stb_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_lew(X) \ + cpu_stw_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_lel(X) \ + cpu_stl_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_leq(X) \ + cpu_stq_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_bew(X) \ + cpu_stw_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_bel(X) \ + cpu_stl_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_beq(X) \ + cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) =20 #if TCG_TARGET_REG_BITS =3D=3D 64 # define CASE_32_64(x) \ --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613593411677772.9492162586091; Wed, 17 Feb 2021 12:23:31 -0800 (PST) Received: from localhost ([::1]:49504 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTM9-0008QJ-Ij for importer@patchew.org; Wed, 17 Feb 2021 15:23:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60398) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTJn-0006JG-1B for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:21:03 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:42960) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTJl-0006mm-G8 for qemu-devel@nongnu.org; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.20.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:20:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rTk7Zu1K9am+nHTK4Qgzw1qdbWz4Og49PpMunTWLZww=; b=yONhUzE/ZFPuJQCJnBW3TFseiiV2XlrJwXnpZRn4SW3SQ/np4YUKjgOBjVdG6Zo7J6 DXX61R7yywJ179YZFdvZCSNgwR9ZhO9btLYtlxplNkrPQ2jrrlrK6SlvHytFAaisy+/s bL3AkGL7L57UbcHwXqrIPZLaKNy34/2ERxV/A7grRAPTJ94M8pB0M+IgX6l8VK5abEiN 7nLb/DA2UicFebNiy44ylQOmYuNbI1icmS/UiXuj2KY2gHBcDuCJ7xz2cmuOLGRs9Ru5 6B/d8FML+8n025eAC2uXJhg5iASRPQHQWikbLRCZGc/OAz8jmsiSjsQe9iXcUHLsyxRF mqxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rTk7Zu1K9am+nHTK4Qgzw1qdbWz4Og49PpMunTWLZww=; b=VHku3LZzXdFX+oEjFkZG9TcCChJa1qNgCIQ7Oonldidgiy64E+UPgIOY+/tHyNnIMk sdjidNaTgoft7Twty+coZ96w+seuAaYu16KISaB8yWZdwBdqK2NeLb6pmZIsBxW+CQv5 RQFK/4B98bOnXgtvscqanANsR0b3/+Ga10cqLXYclpK/ILHsPFS0Fmtrcmor++apR8se WpqF6M9Lma9UdZ62GmM2SPK/41xbANRXFVJCCj768vUezqtER0fMhs0db2DUY3lioNPY qTTZwhxe9eF0vA6Xl7gE8MIEmveOsmjRxeFGaQTKUCabgfZ5jBYmr2uvQSYDoYUeQl9/ Zf3g== X-Gm-Message-State: AOAM532QBClx64UwlAfoMTLv5/nZ9mR8HitX6t8nxVktRo/I3ZZVm7PC Ik6Zpo+8jp//LaImZ7ePcMdtOtPafPtuow== X-Google-Smtp-Source: ABdhPJzzet5zmG+XzUYJMrZDjXenqCCqKLdR32ZQ4MPNqbIR6dMqlPcibnPzvZbqc2V0aY5JEEHhOw== X-Received: by 2002:a63:cd4f:: with SMTP id a15mr934412pgj.105.1613593260075; Wed, 17 Feb 2021 12:21:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 02/71] tcg: Split out tcg_raise_tb_overflow Date: Wed, 17 Feb 2021 12:19:27 -0800 Message-Id: <20210217202036.1724901-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Allow other places in tcg to restart with a smaller tb. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 63a12b197b..bbe3dcee03 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -346,6 +346,12 @@ static void set_jmp_reset_offset(TCGContext *s, int wh= ich) s->tb_jmp_reset_offset[which] =3D tcg_current_code_size(s); } =20 +/* Signal overflow, starting over with fewer guest insns. */ +static void QEMU_NORETURN tcg_raise_tb_overflow(TCGContext *s) +{ + siglongjmp(s->jmp_trans, -2); +} + #define C_PFX1(P, A) P##A #define C_PFX2(P, A, B) P##A##_##B #define C_PFX3(P, A, B, C) P##A##_##B##_##C @@ -1310,8 +1316,7 @@ static TCGTemp *tcg_temp_alloc(TCGContext *s) int n =3D s->nb_temps++; =20 if (n >=3D TCG_MAX_TEMPS) { - /* Signal overflow, starting over with fewer guest insns. */ - siglongjmp(s->jmp_trans, -2); + tcg_raise_tb_overflow(s); } return memset(&s->temps[n], 0, sizeof(TCGTemp)); } --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613593579; cv=none; d=zohomail.com; s=zohoarc; b=PEqvmGxAOEz59SbhRHgNlVOr7P/spLo1ZWJ3K+b7nRpXRM5TzfkrE0uDgymx584I/CGC+TLaVh58H4yECV0YniMOY9a41p65eCBJBx6fBTocF4XHtX+YawJuyv2RmjVjdAaeRtLN1LWPE8y5+hzszmcAaahERZJYEFwisxANn+c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613593579; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xzKpOz1dnkvT+2F/uu8BRDtdRIBrUsrfNHwaFpPfXw4=; b=geiffSCeMU/Sc1AMY75I7WnR5TwAP3sFuwdv6BP1OqCkcqUQ2m2p7ap4tj2a0XKX1dDmAK3qUtv6hUT7EakHm1lfIggNS9Hjx8QJI9FOFik/2IH1usWd+WpOteHXcAOh6nCQW9VkzDlqdO0xttJUoMXkzDfzdbh+BItnNuFC3oQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613593579904564.1836713320405; Wed, 17 Feb 2021 12:26:19 -0800 (PST) Received: from localhost ([::1]:56594 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTOs-00032Q-SI for importer@patchew.org; Wed, 17 Feb 2021 15:26:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60482) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTJv-0006aj-P2 for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:21:11 -0500 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:46394) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTJt-0006qD-W4 for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:21:11 -0500 Received: by mail-pf1-x429.google.com with SMTP id k13so9139595pfh.13 for ; Wed, 17 Feb 2021 12:21:09 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.21.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:21:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xzKpOz1dnkvT+2F/uu8BRDtdRIBrUsrfNHwaFpPfXw4=; b=nCwovk5bxx/ea39Or3udTMgPAlfd296excywL8IkOEsJt9tTErRBp0Wzk10CyP1JN1 /TbYK0jtJiR1XNsZ9te6Gg8qRE5/YsZll7tzHc5wWT6Mmay+uuzVoDSTGSg7zcUTCxEg XfkqbcXkYpSySX7I5RrLg1zwSvJs7D5c5d5CAtkgSFj2oWAq+mFYqFsg2qW0fACM+tSU EDietScp6tzZrsrmvevUAKThOK+nQmvCRxdCfkqUUrhOYqrlxsp2NoeECFFCMqIKjQ64 ORVCTNJyODTM4V0VumO26yOPBFRrIM/wRQQo4bnSLLAICoy8teDb/w9pbxiWyd9Q+bXP kU9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xzKpOz1dnkvT+2F/uu8BRDtdRIBrUsrfNHwaFpPfXw4=; b=t+9Bi4WDK/tF18FtrmMuoklmVgIFj2lDtyyawf08uuEmxIgHnj749BcGUkx3yuIlgD TRZd5RPC0PvZzgsKE5xMogpRZUEdQe3YUX9hPdvFT6TGWiue8G2Fuf+s40KzsSdcNP1Z pu4GuqKilnSLAOCs05t3TKJOCCP2kRPhLbMZ1fWxcKFyOwgutGnsz0JivilTawN4QWr3 OWiGZQ1O4RICMSXCnvj3Di4wTATM01KpCaGsXJsrz4C59MyohsbGcMd0pnu6eyKk30Ks /RwddcBK+PBiMonXgv/qgvj31akt3peKPih0+RsXhW4dpa7FV+RCA853lZc5WuI82mcv th6A== X-Gm-Message-State: AOAM532fG7nwlw5uFjwvt/Z70hsSkYwiQ9lARO2jdCDx0oMyJZCs7uPR r96rgD1P8Sy5mkBW2qwV4yydAs40ZxDA0g== X-Google-Smtp-Source: ABdhPJwDR5ABhzfcrbbPcjiPIO1eQ92bPIpvhwLIX4Gzt2qlGeDHnNzTWwPM6PecyULlAKiQ+ihwqw== X-Received: by 2002:a63:fc07:: with SMTP id j7mr937993pgi.401.1613593268687; Wed, 17 Feb 2021 12:21:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 03/71] tcg: Manage splitwx in tc_ptr_to_region_tree by hand Date: Wed, 17 Feb 2021 12:19:28 -0800 Message-Id: <20210217202036.1724901-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The use in tcg_tb_lookup is given a random pc that comes from the pc of a signal handler. Do not assert that the pointer is already within the code gen buffer at all, much less the writable mirror of it. Fixes: db0c51a3803 Signed-off-by: Richard Henderson --- For TCI, this indicates a bug in handle_cpu_signal, in that we are taking PC from the host signal frame. Which is, nearly, unrelated to TCI at all. The TCI "pc" is tci_tb_ptr (fixed in the next patch to at least be thread-local). We update this only on calls, since we don't expect SEGV during the interpretation loop. Which works ok for softmmu, in which we pass down pc by hand to the helpers, but is not ok for user-only, where we simply perform the raw memory operation. I don't know how to fix this, exactly. Probably by storing to tci_tb_ptr before each qemu_ld/qemu_st operation, with barriers. Then Doing the Right Thing in handle_cpu_signal. And perhaps by clearing tci_tb_ptr whenever we're not expecting a SEGV on behalf of the guest (and thus anything left is a qemu host bug). --- v2: Retain full struct initialization --- tcg/tcg.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index bbe3dcee03..2991112829 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -513,11 +513,21 @@ static void tcg_region_trees_init(void) } } =20 -static struct tcg_region_tree *tc_ptr_to_region_tree(const void *cp) +static struct tcg_region_tree *tc_ptr_to_region_tree(const void *p) { - void *p =3D tcg_splitwx_to_rw(cp); size_t region_idx; =20 + /* + * Like tcg_splitwx_to_rw, with no assert. The pc may come from + * a signal handler over which the caller has no control. + */ + if (!in_code_gen_buffer(p)) { + p -=3D tcg_splitwx_diff; + if (!in_code_gen_buffer(p)) { + return NULL; + } + } + if (p < region.start_aligned) { region_idx =3D 0; } else { @@ -536,6 +546,7 @@ void tcg_tb_insert(TranslationBlock *tb) { struct tcg_region_tree *rt =3D tc_ptr_to_region_tree(tb->tc.ptr); =20 + g_assert(rt !=3D NULL); qemu_mutex_lock(&rt->lock); g_tree_insert(rt->tree, &tb->tc, tb); qemu_mutex_unlock(&rt->lock); @@ -545,6 +556,7 @@ void tcg_tb_remove(TranslationBlock *tb) { struct tcg_region_tree *rt =3D tc_ptr_to_region_tree(tb->tc.ptr); =20 + g_assert(rt !=3D NULL); qemu_mutex_lock(&rt->lock); g_tree_remove(rt->tree, &tb->tc); qemu_mutex_unlock(&rt->lock); @@ -561,6 +573,10 @@ TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr) TranslationBlock *tb; struct tb_tc s =3D { .ptr =3D (void *)tc_ptr }; =20 + if (rt =3D=3D NULL) { + return NULL; + } + qemu_mutex_lock(&rt->lock); tb =3D g_tree_lookup(rt->tree, &s); qemu_mutex_unlock(&rt->lock); --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613593405; cv=none; d=zohomail.com; s=zohoarc; b=dsL6CnkobvyNtFJUGkNc3vYwsUHIme5UN/ajMAQa0C3Z3zq92MXuhR36COKVj/c+nw7plqYqgP4YllckLDZNCTr5yHZHSOaWy98DoIPBpq4XWlINFdZ5CDE8LnubEVs2b2ufJh5zYork2nxPM11RRzef39r2WEfZ/dDOp2byitQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613593405; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VvjDH0d9yENa4ecfbUN1MGRyNECdD1MomwyxKEWSk7s=; b=Avt1ffXvoJxNnr+KRo169t2GHL2b0XVfC0P7GaRTh0oK4oktW27qm2+QnwYXwK9sfyu+iJ2/xt9SJQEy3ruw8iruqkm2Y9Z1fQdpYqukMW2P7D+kbK/H5dagca26AaRfIFmdnj55Kitga8WSTPSYTNUkzqQA1mv6OyDOOdOUhBU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613593404904493.77663234816043; Wed, 17 Feb 2021 12:23:24 -0800 (PST) Received: from localhost ([::1]:49090 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTM1-0008EE-Ov for importer@patchew.org; Wed, 17 Feb 2021 15:23:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60594) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTK9-0006eM-Mf for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:21:28 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:50459) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTK5-0006tk-3m for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:21:25 -0500 Received: by mail-pj1-x102d.google.com with SMTP id cl8so2149361pjb.0 for ; Wed, 17 Feb 2021 12:21:19 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.21.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:21:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VvjDH0d9yENa4ecfbUN1MGRyNECdD1MomwyxKEWSk7s=; b=I3lzKJEizV7zMgZ8OZSkX86X/huDEzrhil1Ku6/t7uU6JxKaSQS1LbnwS+oWmHLqs7 u1Dy5V+QYoDMQzsk2Og37cgqZASYVXYmwStXSp+KreEVidFKpWB3C1tHhlDlAUXEor5M YP1uj+3aZBQxIpZSK2hcIRe4TNirFw1FBkjVGdPD6DR9tuMobUA7vcFFL+ct3x054QLG A0drYczodo8ffWWLisZO0pfdWmzTHLfb0vz68ZtYswiOOeWXwrbXNK/UVPsaEIe0vBXj veE2qIHcNMxP+5IyAKYHtpZksIgHTUJ6NzLpuNfkNJb1UgPyJDi9H+TAVWi/BqcVstBS A26g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VvjDH0d9yENa4ecfbUN1MGRyNECdD1MomwyxKEWSk7s=; b=AjOTdHXTdPIMecQTcDPQ8YE8e6dTpdW0mZRGmKPpQZrzh7tILCg6+dMXVWA6Aq/UUX ECZ8Vt4+clf8ew8+GQMEc5sPHCcC45D6zg8FbUsVcFyBIqFkTTEUJarW2ghSHbUCPDg5 YAw3sozV4HrPavm+cW5FGKnAhUU+83S0Q4X3omTbINSwdQK5BKFPVJb4Xi+5c1xLEr5I GhU690L/muZ8Q9g6m7/IVRVIvVk6b/rJ0nRc3jaZQRuapfCobwsq7kFK52MPkSHb5QSI WXOmNQCDv0pTNbTUX+aq9E1XSRPmMz/5gG8qeCz58PjbpA9EE4UGy2+CaNx4/swKK95B Ql0g== X-Gm-Message-State: AOAM530Rfj1HzdmNVjra41mPJpTZCCl/k0GO8iB4rXJ+Ir0/azRRebPd A5GAQ/BbwIMQYJQ/IAb/uvm0S51+iEdTlw== X-Google-Smtp-Source: ABdhPJy+JAhkyBOukJi4GMDGlQHQqiR5AMj2z2fQrdr5HmKH3moJDaoU5Ibg0rrubp+1zBZYo7O+ZA== X-Received: by 2002:a17:902:ec82:b029:e3:751d:cedf with SMTP id x2-20020a170902ec82b02900e3751dcedfmr742195plg.66.1613593278154; Wed, 17 Feb 2021 12:21:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 04/71] tcg/tci: Merge identical cases in generation Date: Wed, 17 Feb 2021 12:19:29 -0800 Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tci/tcg-target.c.inc | 204 ++++++++++++++------------------------- 1 file changed, 73 insertions(+), 131 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index feac4659cc..c79f9c32d8 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -380,6 +380,18 @@ static inline void tcg_out_call(TCGContext *s, const t= cg_insn_unit *arg) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +#if TCG_TARGET_REG_BITS =3D=3D 64 +# define CASE_32_64(x) \ + case glue(glue(INDEX_op_, x), _i64): \ + case glue(glue(INDEX_op_, x), _i32): +# define CASE_64(x) \ + case glue(glue(INDEX_op_, x), _i64): +#else +# define CASE_32_64(x) \ + case glue(glue(INDEX_op_, x), _i32): +# define CASE_64(x) +#endif + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { @@ -391,6 +403,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, case INDEX_op_exit_tb: tcg_out64(s, args[0]); break; + case INDEX_op_goto_tb: if (s->tb_jmp_insn_offset) { /* Direct jump method. */ @@ -404,15 +417,18 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, } set_jmp_reset_offset(s, args[0]); break; + case INDEX_op_br: tci_out_label(s, arg_label(args[0])); break; - case INDEX_op_setcond_i32: + + CASE_32_64(setcond) tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out8(s, args[3]); /* condition */ break; + #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */ @@ -423,60 +439,54 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, tcg_out_r(s, args[4]); tcg_out8(s, args[5]); /* condition */ break; -#elif TCG_TARGET_REG_BITS =3D=3D 64 - case INDEX_op_setcond_i64: - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out8(s, args[3]); /* condition */ - break; #endif - case INDEX_op_ld8u_i32: - case INDEX_op_ld8s_i32: - case INDEX_op_ld16u_i32: - case INDEX_op_ld16s_i32: + + CASE_32_64(ld8u) + CASE_32_64(ld8s) + CASE_32_64(ld16u) + CASE_32_64(ld16s) case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: + CASE_64(ld32u) + CASE_64(ld32s) + CASE_64(ld) + CASE_32_64(st8) + CASE_32_64(st16) case INDEX_op_st_i32: - case INDEX_op_ld8u_i64: - case INDEX_op_ld8s_i64: - case INDEX_op_ld16u_i64: - case INDEX_op_ld16s_i64: - case INDEX_op_ld32u_i64: - case INDEX_op_ld32s_i64: - case INDEX_op_ld_i64: - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: + CASE_64(st32) + CASE_64(st) stack_bounds_check(args[1], args[2]); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_debug_assert(args[2] =3D=3D (int32_t)args[2]); tcg_out32(s, args[2]); break; - case INDEX_op_add_i32: - case INDEX_op_sub_i32: - case INDEX_op_mul_i32: - case INDEX_op_and_i32: - case INDEX_op_andc_i32: /* Optional (TCG_TARGET_HAS_andc_i32). */ - case INDEX_op_eqv_i32: /* Optional (TCG_TARGET_HAS_eqv_i32). */ - case INDEX_op_nand_i32: /* Optional (TCG_TARGET_HAS_nand_i32). */ - case INDEX_op_nor_i32: /* Optional (TCG_TARGET_HAS_nor_i32). */ - case INDEX_op_or_i32: - case INDEX_op_orc_i32: /* Optional (TCG_TARGET_HAS_orc_i32). */ - case INDEX_op_xor_i32: - case INDEX_op_shl_i32: - case INDEX_op_shr_i32: - case INDEX_op_sar_i32: - case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ - case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ + + CASE_32_64(add) + CASE_32_64(sub) + CASE_32_64(mul) + CASE_32_64(and) + CASE_32_64(or) + CASE_32_64(xor) + CASE_32_64(andc) /* Optional (TCG_TARGET_HAS_andc_*). */ + CASE_32_64(orc) /* Optional (TCG_TARGET_HAS_orc_*). */ + CASE_32_64(eqv) /* Optional (TCG_TARGET_HAS_eqv_*). */ + CASE_32_64(nand) /* Optional (TCG_TARGET_HAS_nand_*). */ + CASE_32_64(nor) /* Optional (TCG_TARGET_HAS_nor_*). */ + CASE_32_64(shl) + CASE_32_64(shr) + CASE_32_64(sar) + CASE_32_64(rotl) /* Optional (TCG_TARGET_HAS_rot_*). */ + CASE_32_64(rotr) /* Optional (TCG_TARGET_HAS_rot_*). */ + CASE_32_64(div) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); break; - case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). = */ + + CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); @@ -486,79 +496,30 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, tcg_out8(s, args[4]); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 - case INDEX_op_add_i64: - case INDEX_op_sub_i64: - case INDEX_op_mul_i64: - case INDEX_op_and_i64: - case INDEX_op_andc_i64: /* Optional (TCG_TARGET_HAS_andc_i64). */ - case INDEX_op_eqv_i64: /* Optional (TCG_TARGET_HAS_eqv_i64). */ - case INDEX_op_nand_i64: /* Optional (TCG_TARGET_HAS_nand_i64). */ - case INDEX_op_nor_i64: /* Optional (TCG_TARGET_HAS_nor_i64). */ - case INDEX_op_or_i64: - case INDEX_op_orc_i64: /* Optional (TCG_TARGET_HAS_orc_i64). */ - case INDEX_op_xor_i64: - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ - case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ - case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - break; - case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). = */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_debug_assert(args[3] <=3D UINT8_MAX); - tcg_out8(s, args[3]); - tcg_debug_assert(args[4] <=3D UINT8_MAX); - tcg_out8(s, args[4]); - break; - case INDEX_op_brcond_i64: + CASE_32_64(brcond) tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out8(s, args[2]); /* condition */ tci_out_label(s, arg_label(args[3])); break; - case INDEX_op_bswap16_i64: /* Optional (TCG_TARGET_HAS_bswap16_i64). = */ - case INDEX_op_bswap32_i64: /* Optional (TCG_TARGET_HAS_bswap32_i64). = */ - case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). = */ - case INDEX_op_not_i64: /* Optional (TCG_TARGET_HAS_not_i64). */ - case INDEX_op_neg_i64: /* Optional (TCG_TARGET_HAS_neg_i64). */ - case INDEX_op_ext8s_i64: /* Optional (TCG_TARGET_HAS_ext8s_i64). */ - case INDEX_op_ext8u_i64: /* Optional (TCG_TARGET_HAS_ext8u_i64). */ - case INDEX_op_ext16s_i64: /* Optional (TCG_TARGET_HAS_ext16s_i64). */ - case INDEX_op_ext16u_i64: /* Optional (TCG_TARGET_HAS_ext16u_i64). */ - case INDEX_op_ext32s_i64: /* Optional (TCG_TARGET_HAS_ext32s_i64). */ - case INDEX_op_ext32u_i64: /* Optional (TCG_TARGET_HAS_ext32u_i64). */ - case INDEX_op_ext_i32_i64: - case INDEX_op_extu_i32_i64: -#endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ - case INDEX_op_neg_i32: /* Optional (TCG_TARGET_HAS_neg_i32). */ - case INDEX_op_not_i32: /* Optional (TCG_TARGET_HAS_not_i32). */ - case INDEX_op_ext8s_i32: /* Optional (TCG_TARGET_HAS_ext8s_i32). */ - case INDEX_op_ext16s_i32: /* Optional (TCG_TARGET_HAS_ext16s_i32). */ - case INDEX_op_ext8u_i32: /* Optional (TCG_TARGET_HAS_ext8u_i32). */ - case INDEX_op_ext16u_i32: /* Optional (TCG_TARGET_HAS_ext16u_i32). */ - case INDEX_op_bswap16_i32: /* Optional (TCG_TARGET_HAS_bswap16_i32). = */ - case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). = */ + + CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ + CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */ + CASE_32_64(ext8s) /* Optional (TCG_TARGET_HAS_ext8s_*). */ + CASE_32_64(ext8u) /* Optional (TCG_TARGET_HAS_ext8u_*). */ + CASE_32_64(ext16s) /* Optional (TCG_TARGET_HAS_ext16s_*). */ + CASE_32_64(ext16u) /* Optional (TCG_TARGET_HAS_ext16u_*). */ + CASE_64(ext32s) /* Optional (TCG_TARGET_HAS_ext32s_i64). */ + CASE_64(ext32u) /* Optional (TCG_TARGET_HAS_ext32u_i64). */ + CASE_64(ext_i32) + CASE_64(extu_i32) + CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ + CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ + CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); break; - case INDEX_op_div_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - case INDEX_op_divu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - break; + #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: @@ -584,31 +545,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, tcg_out_r(s, args[3]); break; #endif - case INDEX_op_brcond_i32: - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out8(s, args[2]); /* condition */ - tci_out_label(s, arg_label(args[3])); - break; + case INDEX_op_qemu_ld_i32: - tcg_out_r(s, *args++); - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out_i(s, *args++); - break; - case INDEX_op_qemu_ld_i64: - tcg_out_r(s, *args++); - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_r(s, *args++); - } - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out_i(s, *args++); - break; case INDEX_op_qemu_st_i32: tcg_out_r(s, *args++); tcg_out_r(s, *args++); @@ -617,6 +555,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, } tcg_out_i(s, *args++); break; + + case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: tcg_out_r(s, *args++); if (TCG_TARGET_REG_BITS =3D=3D 32) { @@ -628,8 +568,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, } tcg_out_i(s, *args++); break; + case INDEX_op_mb: break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.21.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:21:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sl3AXKlBgqeB3AKFBMSA/Bsf7ajPVkdcdF0tA8fk6Xg=; b=jmjEBbcTeIv1cbZb4R53fTgDhoxf4boULWOvhVGatr6JMSSnyeQiDcXGBn3/I0BoHU zOE6WPdtKs8v2HjZ6mbiGJIuUgFH7Hm/MwkmKPRTnkIsIrifWc9ROH7dQ+U/so9iluMa 0Wj8c+h1x+3FsbHtbiY8nBwR4fN4UTOjfQkS1QE7UhsdpzjFnj/F0b0LD838Px7lfAqK h59/pXkyjW3Gkyh0bFrQJqg8SbEFrbYeZ5himZa/yuDb6veQBRjN2VVr60Dbekz01NRw XqHOan5Fwa6KbWFg1hAhav5Pr/p+l+r0GHQqSG9+Cd/FGvFouIHpj9Xa1J9xnNi79Lxb bxqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sl3AXKlBgqeB3AKFBMSA/Bsf7ajPVkdcdF0tA8fk6Xg=; b=WWbXDhbRDocMBP4pfZ/fUoJNuTct/IKGj/72RZXQRmJMg83JsebaaLMBXli+1wn/Ku kmn1Qv0LtMqjvAW1mA6T5DAXLVMzbBw0ljJ7KAjpGZtPJpTP2Qrwq1G375A26T6eEdJg TEiKILZkNlalEeiGBzZjduBN19gNPUjltc8jKb/+z48L/CijKgb07+ToNokn8RFP0rSN /rtX/v/m7N0NDQEjO4OUV9IQ9x/78uhZi1DkU+lCuAoPTmsMj0EFOn+DJM7BKTTq7LPW h5XKe73ch5pgZAaQNa8HQYc+OSZ9o/TpjW/iR/bKZlOeSYDqAOkiPHsjJWKoUXupV5Ph k7hg== X-Gm-Message-State: AOAM533juY+Ucng8tQmHRJI+NZ2ThL+ZpK0VuqApy7WV6o20W0mihTVv +sV8oGBoBmMMY0VAysTmYUnFw/kd2+dKLQ== X-Google-Smtp-Source: ABdhPJxWLUgtVADV9ClaL+GE/HPMPM3a+xniiy368LNDKCv0r2gunzkyTY1nKBrzRJaZ2lFXn2Spcg== X-Received: by 2002:a17:902:8501:b029:e2:ebb4:6e77 with SMTP id bj1-20020a1709028501b02900e2ebb46e77mr721057plb.43.1613593295517; Wed, 17 Feb 2021 12:21:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/71] tcg/tci: Remove tci_read_r8 Date: Wed, 17 Feb 2021 12:19:30 -0800 Message-Id: <20210217202036.1724901-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Use explicit casts for ext8u opcodes, and allow truncation to happen with the store for st8 opcodes. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tci.c | 23 +++++------------------ 1 file changed, 5 insertions(+), 18 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 1c667537fe..4ade0ccaf9 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -78,11 +78,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *r= egs, TCGReg index) } #endif =20 -static uint8_t tci_read_reg8(const tcg_target_ulong *regs, TCGReg index) -{ - return (uint8_t)tci_read_reg(regs, index); -} - static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index) { return (uint16_t)tci_read_reg(regs, index); @@ -169,14 +164,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t= **tb_ptr) return value; } =20 -/* Read indexed register (8 bit) from bytecode. */ -static uint8_t tci_read_r8(const tcg_target_ulong *regs, const uint8_t **t= b_ptr) -{ - uint8_t value =3D tci_read_reg8(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} - #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 /* Read indexed register (8 bit signed) from bytecode. */ static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **t= b_ptr) @@ -533,7 +520,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); break; CASE_32_64(st8) - t0 =3D tci_read_r8(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) =3D t0; @@ -722,8 +709,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext8u_i32 case INDEX_op_ext8u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16u_i32 @@ -916,8 +903,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext8u_i64 case INDEX_op_ext8u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint8_t)t1); break; #endif #if TCG_TARGET_HAS_ext8s_i64 --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613594213; cv=none; d=zohomail.com; s=zohoarc; b=nx/vd1uGMBMixEqfvE2squ8OTrOg2erLLXzuXKDt2xtHv/LaRuEbAoJCb/KCzimsXBRuKRM0fwe0/y+jafujDPRUqXSGbetOMA9IJtj1R4xgJByYQEd+4lVzU0bXYQdQtjF/iyA4+/Ifoisqhn8PVJiGI8YdYeOkI27QnV++qqA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613594213; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=s0epI5FYzBmDpaBBAxqnrVAuCgvURTvdHnKLPkRQG1c=; b=Qm6TIZ40UJPzazAy0H95C4Lf+oP/O9xUvFGTy6IH1v21mEsLgnAskyDVyu5FaXSHBwzSgt8MpJje5z2Dft4ri8iAbqJDBuBePxjk46OCQ8nb1w6EB5nMVeBwz2aRfsNSb1Y2CAAIexxDBStT4ycxu6gq9QNa0KRpyae2OtjzKb4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613594213079465.6348497287486; Wed, 17 Feb 2021 12:36:53 -0800 (PST) Received: from localhost ([::1]:52916 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTZ6-00055j-24 for importer@patchew.org; Wed, 17 Feb 2021 15:36:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60736) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTKi-0006uw-4u for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:00 -0500 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:36010) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTKd-000764-Ap for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:21:59 -0500 Received: by mail-pf1-x42e.google.com with SMTP id z15so9168030pfc.3 for ; Wed, 17 Feb 2021 12:21:52 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.21.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:21:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=s0epI5FYzBmDpaBBAxqnrVAuCgvURTvdHnKLPkRQG1c=; b=cCumBb77wX/VN/L/pDIDQjHxcnjs8CAweag3x/iTLSBKFSo404ZjZzHZX+QRz+w6mL 7019CoNVmMNXLFwLz3LCljhdJL/4RlFwi+Sn1H1Ln7Ly1/giqbP53RBxZY2fmc03F7WS YUVofdpH8Y5quYrNqklHJHGm0TqjgxopyrFUJM7eKKAeGnpLP+00BQKQF78i1d9UeQvd aHLA8n66Ajzn1cGQ9IjBulyi1gkdstA8q3hKLWRv7RWOg9wIRWrhJGbz6i1HiEj3HKxP 3cCFbcI2lQyfiLbF/JBXR/P5k377PzNKQyqTZCIUMOV46m/MKupEzlXlX5Tamy0KvZ7r /1eA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=s0epI5FYzBmDpaBBAxqnrVAuCgvURTvdHnKLPkRQG1c=; b=eaXZfN6DBwFldinbl3HvwXHc+ut0I6YmP1ejAu3ksQHZTFogsF0nE7gjv/jW7C86k4 Gfo6wEeWKRcbJ7pjuDtd9WECf7zJkpw/Xhrf7Rf04mUJn9hcXQoODaLYjP0fv95Bv5gx DbsTyp3BeRC/uU/IefwHMFF1Nib9HA3HgxZmUfnv3ao/SbyVKmu4uR3Ap75j1z3+SNxi WX5w5oCxg1HVBPbXmQGBNo4twK/7CsRBfZW2z3uy/L15PsU+21NsDPJrzsO/18RsrKnB lQa0MJt6Lq3QmAZrYZeoQJDPlrAUE4mmB8zH89/6wUh34wangbM/lb4pCy/iwVd6QduO Ezlw== X-Gm-Message-State: AOAM532OCBOnwmezVro0TgaADC/MSWgiINL5LSBxmfAnds6MTidX7QAM QLLnHVUhMynQgqCIHKVq9ukmTzfVO0/Rhw== X-Google-Smtp-Source: ABdhPJwcOG3650455PWUxfYN810dnzkYmEZaOhmQZR1yv9pDvg7F+okUi1v8beoMWc1WaCYt8OPdOw== X-Received: by 2002:a05:6a00:7cf:b029:1ec:d659:e55c with SMTP id n15-20020a056a0007cfb02901ecd659e55cmr940730pfu.69.1613593311967; Wed, 17 Feb 2021 12:21:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 06/71] tcg/tci: Remove tci_read_r8s Date: Wed, 17 Feb 2021 12:19:31 -0800 Message-Id: <20210217202036.1724901-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Use explicit casts for ext8s opcodes. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tci.c | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 4ade0ccaf9..7325c8bfd0 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ul= ong *regs, TCGReg index) return regs[index]; } =20 -#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -static int8_t tci_read_reg8s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int8_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) { @@ -164,16 +157,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t= **tb_ptr) return value; } =20 -#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -/* Read indexed register (8 bit signed) from bytecode. */ -static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **t= b_ptr) -{ - int8_t value =3D tci_read_reg8s(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} -#endif - /* Read indexed register (16 bit) from bytecode. */ static uint16_t tci_read_r16(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -695,8 +678,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext8s_i32 case INDEX_op_ext8s_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 @@ -910,8 +893,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext8s_i64 case INDEX_op_ext8s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i64 --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613593970805854.8585934958769; Wed, 17 Feb 2021 12:32:50 -0800 (PST) Received: from localhost ([::1]:44088 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTVB-0001Ia-Hr for importer@patchew.org; Wed, 17 Feb 2021 15:32:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60746) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTKj-0006vX-0y for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:01 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:36641) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTKg-00076n-Qp for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:00 -0500 Received: by mail-pl1-x631.google.com with SMTP id e9so8041724plh.3 for ; Wed, 17 Feb 2021 12:21:58 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.21.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:21:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EgfsM+xDw/5+yMWEqnFKIWyZYHRInwuGtrXJDDW2BOY=; b=bp59r9W52AqrOpQmmWqIIz2nu1XMR7KvXlp91r09l/gU3hlTAWA1xE8mGel3Vk0+JX bDey9MsJYU8GpqufIkdypXxzLxKNnCpAARQHmR+QhehuqCEMpfCmIXn0qakSUK/VlKeQ Qyhc3+oG0IAFzLG1UQt2Ifu0S34d+oWUasRs9/cC/ZUNd54wjiFFEUym/fHC+5o2DLqc vqHTvX8hmf6Fm4QsiukwAPpFvxNDF2blO2smwjcHmhSB9wPHdK+RsidtKSkAH0wgyl0F BcQXDNRnxHTnLu2w4lq20vaa0kBXqn2zI2tMb2+spBVRg3IQJAxos86fq8PDDxQugwNj 9i6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EgfsM+xDw/5+yMWEqnFKIWyZYHRInwuGtrXJDDW2BOY=; b=GvFsapBe84ih1ILfiHw+a+BQPx9o7GpbThbe2iFMabXlmTHHBuw9y8XHKCMC5CssDf V10PG0hBB5cbNd3dJxKeWoSF8J9PsaGo1LJ8JKK2TltAGmPiRE+Wya4gjwj7K07OdWuY +jehRHeNFLeFDV+ExmejL95egBUYJUgValZ8q6JD8oWDaxn04SDZzKtI9YOnFXU0W3wG gfySciaHq3REM57g8qOtMn88ziA3EaBYj5z88ldQCVete+lE8Pr27ChxdYWIjdW+GoCu vwLIhHCpF93nCpmqQZn2PoaSbRVmBCR42aDswpYYIEUVuDuGNEq+PEo3dTutK8iGZdAh F+xA== X-Gm-Message-State: AOAM532E+nWpXxAvM/4s5bmJYrjDAxn9iTTOJqaeQpDI8JIeeseG52Nz j0fQ7jlTw3pzbuGxJXLICkKxIsY0K52NAA== X-Google-Smtp-Source: ABdhPJxU7AZwomfcOcTl6OB6ht9ZNjism8A2+6cr5W+2JxTlGotLVR3/2NUcgol08qC86cPnAcXQ1g== X-Received: by 2002:a17:902:9a48:b029:e1:268d:e800 with SMTP id x8-20020a1709029a48b02900e1268de800mr905692plv.69.1613593317614; Wed, 17 Feb 2021 12:21:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/71] tcg/tci: Remove tci_read_r16 Date: Wed, 17 Feb 2021 12:19:32 -0800 Message-Id: <20210217202036.1724901-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Use explicit casts for ext16u opcodes, and allow truncation to happen with the store for st16 opcodes, and with the call for bswap16 opcodes. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tci.c | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 7325c8bfd0..2440da1746 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -71,11 +71,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *r= egs, TCGReg index) } #endif =20 -static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index) -{ - return (uint16_t)tci_read_reg(regs, index); -} - static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index) { return (uint32_t)tci_read_reg(regs, index); @@ -157,15 +152,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t= **tb_ptr) return value; } =20 -/* Read indexed register (16 bit) from bytecode. */ -static uint16_t tci_read_r16(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - uint16_t value =3D tci_read_reg16(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} - #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 /* Read indexed register (16 bit signed) from bytecode. */ static int16_t tci_read_r16s(const tcg_target_ulong *regs, @@ -509,7 +495,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, *(uint8_t *)(t1 + t2) =3D t0; break; CASE_32_64(st16) - t0 =3D tci_read_r16(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) =3D t0; @@ -699,14 +685,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #if TCG_TARGET_HAS_ext16u_i32 case INDEX_op_ext16u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint16_t)t1); break; #endif #if TCG_TARGET_HAS_bswap16_i32 case INDEX_op_bswap16_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif @@ -907,8 +893,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext16u_i64 case INDEX_op_ext16u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint16_t)t1); break; #endif #if TCG_TARGET_HAS_ext32s_i64 @@ -930,7 +916,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_bswap16_i64 case INDEX_op_bswap16_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613594216447319.2740782200797; Wed, 17 Feb 2021 12:36:56 -0800 (PST) Received: from localhost ([::1]:52884 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTZ8-000552-2M for importer@patchew.org; Wed, 17 Feb 2021 15:36:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60790) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTKq-0006yV-AQ for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:09 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:51738) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTKm-00077k-C5 for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:08 -0500 Received: by mail-pj1-x102c.google.com with SMTP id fa16so2146915pjb.1 for ; Wed, 17 Feb 2021 12:22:03 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.21.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sLU2XmKG3JbG1D9u9PmlE0yiGugHvDS0F3Tdhc3De6g=; b=OyUw7VdGURcIpM802vxHhZhiiSF1JUXUsMHvt9qCMycIxLxMwkzYoxlvB3W6uKH4c9 /05QqDMj+FySSI3I/DrM8NoW1tph4tsGpPDom8rqkFLxwGv4IXYEII6yJRmq6XM/bVaM QdvEmduMDvIuD+eOH7miXoBZoKTZ8ppUH1clFG39x7Qbwmp/XQnXLqAVsa/LCyIQPzBq DO8BIemMunACzm5TuuR8VmuXjV1Z5YRsVsrFY52zkJRvOiDUBK0L2JO5GR8N85dqQExW Ya5+nxjw+Tvh921bIvyCfm/QW/KcnmOXcXHGXl5sZMHgWAKcEwrN/FLqQqgSawDPKR/j OtMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sLU2XmKG3JbG1D9u9PmlE0yiGugHvDS0F3Tdhc3De6g=; b=q2OEpW7djvOgi/JsscCu1cusjFGyKp8pYpn1FQXquMB1o3MjNn6LlerCiOUaUNwNz7 Wj4gJq86ihjsUXsZG/iY/6OhaLD3EXeqR+zT2cu69V6ktPQuEa0I88eTNmG5nZBaxlO9 6cVKU/J50lM5EKLZ3uLJkiB5+z35u/FOqaaV1w9PomTzZAFpwAf0Fb5T5A3mV00u+4OW jxege39CDyORQ37Dh/3VfyjJk7ZddRLmrYQvn9jYa3muJ4hetSCiVLfVNI+ai9f2a4+T E9xupM2irBuNOe9YRi/sNLZF2egC+pNNc6+4W76oNgrWB3XsZu359ggxxNLLfZk7J8mB +zfQ== X-Gm-Message-State: AOAM531VXbBdKI3ljRUYk5BXkwk+Wa20UmMiMcN4qpFX831pccWVajBp vHPE9rb0oG/Kq8NkR/YsNLJ5Cbs2xUcE/Q== X-Google-Smtp-Source: ABdhPJztAOrTeUbjA+1MZMQj6+EUFuNiXihf8WukfthUc9/pq3hTqRRg2zp5kkhGMeCR7tj/jeFaVA== X-Received: by 2002:a17:902:e5cc:b029:df:bc77:3aba with SMTP id u12-20020a170902e5ccb02900dfbc773abamr976081plf.72.1613593322556; Wed, 17 Feb 2021 12:22:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 08/71] tcg/tci: Remove tci_read_r16s Date: Wed, 17 Feb 2021 12:19:33 -0800 Message-Id: <20210217202036.1724901-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Use explicit casts for ext16s opcodes. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tci.c | 26 ++++---------------------- 1 file changed, 4 insertions(+), 22 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 2440da1746..8b91e6efc3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ul= ong *regs, TCGReg index) return regs[index]; } =20 -#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int16_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_REG_BITS =3D=3D 64 static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) { @@ -152,17 +145,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t= **tb_ptr) return value; } =20 -#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -/* Read indexed register (16 bit signed) from bytecode. */ -static int16_t tci_read_r16s(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - int16_t value =3D tci_read_reg16s(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} -#endif - /* Read indexed register (32 bit) from bytecode. */ static uint32_t tci_read_r32(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -671,8 +653,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext16s_i32 case INDEX_op_ext16s_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int16_t)t1); break; #endif #if TCG_TARGET_HAS_ext8u_i32 @@ -886,8 +868,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext16s_i64 case INDEX_op_ext16s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int16_t)t1); break; #endif #if TCG_TARGET_HAS_ext16u_i64 --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613594421203545.0237743581907; Wed, 17 Feb 2021 12:40:21 -0800 (PST) Received: from localhost ([::1]:33354 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTcS-0000D2-3X for importer@patchew.org; Wed, 17 Feb 2021 15:40:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60828) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTKu-00075N-PE for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:12 -0500 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:39722) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTKs-00079G-Lc for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:12 -0500 Received: by mail-pg1-x536.google.com with SMTP id o63so9202629pgo.6 for ; Wed, 17 Feb 2021 12:22:10 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1zh4Oi86+XA2CDAVF1jA84UCd8h/wBVxBroPuyJg4Sk=; b=ly2ufi3xjnjaNAJxRT/g+ym1efXBUj6EITfbJpmYJPxUvLC8WeKY2uYg7MMkRBifl4 6cw6+IgEHxKS7dxt8HozshISgW1swLT1FX52LEyiw4OkxQqtNPsuo/uAijWHFPK/xe5f qcI0KScjiiT25pzLTHKqhXJBmwG7D5ta8Expe5C094IsPSc/mY2wB1g2TdJ6hF8BmdZP KxDzWA0ZKTSK1JAd2qGG7NNygu3o5KPlD6A5ARIau7olU28unyGmhvKmgdTjr5NfopIy ku7J7T1JxtTmwIm4wlJELfudXMcyYy2YpCLxdudMGJb6a5tbvyja7DyXVCyK6PmRJCte lZtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1zh4Oi86+XA2CDAVF1jA84UCd8h/wBVxBroPuyJg4Sk=; b=JC+zy07Vj2yWSBDHfa3/uBlAk7tHmvOy1v9b5CYpeJcFXN/NU1Ls/eLo8878THz1/I hMIv8an59UFfn5+vfH3mmSrNOn1UjbwBYgq/xGklMLj+aaSV1SLysGiXkwqele0NPhLm DanVTA/HDLuwNESQhXSetfaS4OznX7O+Bgt0NmW1LfnmkmRTtlLjw3n/TAHgezpuVadx /4ans/ANiz/W9AaaE1YSCo2NHrFIEEIU4ZaqlvUOy/H3dn2CLpez08W8vzLs8hQlefjJ FHs90SWZdR5jxNSml1tVnwG3b4zsxcf7RBhZgDadTqXesEtMGia32UDpidRDSiwge+lY D8IA== X-Gm-Message-State: AOAM533cc6PKRGf5aQwi0zMc6qskfVi3Cm8ZoQ8c9jmBa3wdRlS9SBP7 LkArSk6/xLWJ+3ioMGK/F1R+4duQzMcj9w== X-Google-Smtp-Source: ABdhPJwv9DOuoaNcB4wn/xftzQ3Xh1vxNzgEGKEGOo90Tf4S8lJt2EeSi7dt3F7aEPw22L/UCqnPlA== X-Received: by 2002:a62:4ec4:0:b029:1e0:f67e:b2f2 with SMTP id c187-20020a624ec40000b02901e0f67eb2f2mr972251pfb.81.1613593329392; Wed, 17 Feb 2021 12:22:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 09/71] tcg/tci: Remove tci_read_r32 Date: Wed, 17 Feb 2021 12:19:34 -0800 Message-Id: <20210217202036.1724901-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Use explicit casts for ext32u opcodes, and allow truncation to happen for other users. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tci.c | 122 ++++++++++++++++++++++++------------------------------ 1 file changed, 54 insertions(+), 68 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 8b91e6efc3..a5aaa763f8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -64,11 +64,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *r= egs, TCGReg index) } #endif =20 -static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index) -{ - return (uint32_t)tci_read_reg(regs, index); -} - #if TCG_TARGET_REG_BITS =3D=3D 64 static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) { @@ -145,22 +140,13 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_= t **tb_ptr) return value; } =20 -/* Read indexed register (32 bit) from bytecode. */ -static uint32_t tci_read_r32(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - uint32_t value =3D tci_read_reg32(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} - #if TCG_TARGET_REG_BITS =3D=3D 32 /* Read two indexed registers (2 * 32 bit) from bytecode. */ static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - uint32_t low =3D tci_read_r32(regs, tb_ptr); - return tci_uint64(tci_read_r32(regs, tb_ptr), low); + uint32_t low =3D tci_read_r(regs, tb_ptr); + return tci_uint64(tci_read_r(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 /* Read indexed register (32 bit signed) from bytecode. */ @@ -404,8 +390,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, continue; case INDEX_op_setcond_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); condition =3D *tb_ptr++; tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); break; @@ -428,7 +414,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif case INDEX_op_mov_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i32: @@ -484,7 +470,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; case INDEX_op_st_i32: CASE_64(st32) - t0 =3D tci_read_r32(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint32_t *)(t1 + t2) =3D t0; @@ -494,62 +480,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_add_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; case INDEX_op_sub_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; case INDEX_op_mul_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; case INDEX_op_div_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); break; case INDEX_op_divu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 / t2); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2); break; case INDEX_op_rem_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); break; case INDEX_op_remu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 % t2); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); break; case INDEX_op_and_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 & t2); break; case INDEX_op_or_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 | t2); break; case INDEX_op_xor_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 ^ t2); break; =20 @@ -557,41 +543,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_shl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 << (t2 & 31)); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31)); break; case INDEX_op_shr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 >> (t2 & 31)); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31)); break; case INDEX_op_sar_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, ((int32_t)t1 >> (t2 & 31))); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31)); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, rol32(t1, t2 & 31)); break; case INDEX_op_rotr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ror32(t1, t2 & 31)); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp32 =3D (((1 << tmp8) - 1) << tmp16); @@ -599,8 +585,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i32: - t0 =3D tci_read_r32(regs, &tb_ptr); - t1 =3D tci_read_r32(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare32(t0, t1, condition)) { @@ -638,9 +624,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_mulu2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - t2 =3D tci_read_r32(regs, &tb_ptr); - tmp64 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, t2 * tmp64); + t2 =3D tci_read_r(regs, &tb_ptr); + tmp64 =3D (uint32_t)tci_read_r(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 @@ -681,21 +667,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #if TCG_TARGET_HAS_bswap32_i32 case INDEX_op_bswap32_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_not_i32 case INDEX_op_not_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i32 case INDEX_op_neg_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif @@ -892,8 +878,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif case INDEX_op_extu_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1); break; #if TCG_TARGET_HAS_bswap16_i64 case INDEX_op_bswap16_i64: @@ -905,7 +891,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_bswap32_i64 case INDEX_op_bswap32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); break; #endif --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613594419076121.58455603787331; Wed, 17 Feb 2021 12:40:19 -0800 (PST) Received: from localhost ([::1]:33340 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTcP-0000Cl-SI for importer@patchew.org; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Eg77pQQlLC4zBnjShq/Ox8hKnBoPA3tCVlP/vVaohvk=; b=In9u7mHMyXe2EG6Fs88jIzDoIewGtcK4znuZW0Npwa5nUgTSut/SraMvIQbUGKXwjS M46sixawv8hymftWDP/9Ii+LkV4tH1hGbhrWeh+RKPlNKYu3uAOGfMxNXAmK0Mv7bUOa +c4B1Xx0OOive2v04RAVbJSthX40ZqvqlhxbuIMHRrQ10dxgIS0zmWFtCicK2M3+cM8F Kqw4vILGuNLoOcDcALo3r/iMylJuWp7ru+XPlJqy32uqcF1KFN5uWGCJopv5KdsgmC8H IJzdG8JvT1R5LAYa5lP2nC92HHuPirnhZMOkvfZrStaAVvFMXe7ntBKUXzNFzZ874W1Y uDSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Eg77pQQlLC4zBnjShq/Ox8hKnBoPA3tCVlP/vVaohvk=; b=UfVBcupHNw93AejKIGaZc2KQqbHr3jl+Pfq/VwUZcXEyZiK2naHRlyvdxU6mNjZQ9s Z6BnbPIKs8uapsynQt0xeP4e3b9631erAhuWRZ+FwPQg4ZWoG3qKnXCh8AprIAGCQ+7u unpOfIcBpaKdaoLzQo6yDYLcMeNqUeELI0rNA5I+xQZriFyQSR2z6anVTacU3Tqj6zZB E2TPVoDHVSN0n/FMRbHB63NPW4o0OGK7JspcX61Z+EPgo4vT4wLXjUQnfF9/LrDer/tu KBer8KXEOzUllSKdWsmyOdwnyYY1ZuiPOhKTLOp1fIp0C8dxEHoJXeHq9udoIoFG5LYo ZjmQ== X-Gm-Message-State: AOAM532ksrfpoOF4adzQ0n2M6HpRRqX9hD26Ar8D2I6BbDnC6ixgQ9zq pNJHw2/dHBuZ8X4Zjs67wwm0xA31sRaIlw== X-Google-Smtp-Source: ABdhPJzGquwiQQeU32hMzJeGrgcnLWYjt9odmWf5EzpK7OzoMf259tHJEQiKeksgnCr96JxowinbgA== X-Received: by 2002:a63:5f11:: with SMTP id t17mr946817pgb.391.1613593331356; Wed, 17 Feb 2021 12:22:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 10/71] tcg/tci: Remove tci_read_r32s Date: Wed, 17 Feb 2021 12:19:35 -0800 Message-Id: <20210217202036.1724901-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Use explicit casts for ext32s opcodes. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tci.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index a5aaa763f8..cef12f263d 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ul= ong *regs, TCGReg index) return regs[index]; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int32_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_REG_BITS =3D=3D 64 static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) { @@ -149,15 +142,6 @@ static uint64_t tci_read_r64(const tcg_target_ulong *r= egs, return tci_uint64(tci_read_r(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 -/* Read indexed register (32 bit signed) from bytecode. */ -static int32_t tci_read_r32s(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - int32_t value =3D tci_read_reg32s(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} - /* Read indexed register (64 bit) from bytecode. */ static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -870,8 +854,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif case INDEX_op_ext_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int32_t)t1); break; #if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613593577; cv=none; d=zohomail.com; s=zohoarc; b=MHWFgsuMptW8NrJYnvyPp9NA80aAnRCVVzig30tm8d3vqKbHanGkw7qiUuMsQrd2b+Tk0IEbjyjB01B272AoblXhcQvUL7sr/S5mEyFzkYagmOSugMqqaGFFD0SHtEimmd6ImOg/tegmrCZ62u8s2GNmND50+FCjxjAveaVzT24= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613593577; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/cgl87lXykdJMny21/UJVDiccpgPXiqD0uRpK0C4eyY=; b=gQ90xp/9Ns6/rYk6fmtV2juqz5ZRWDMZ2N4pzTc2r1Urh7Ggs1GMnOqoCwcMQbHMfAIzif/An9xrL9g9sspoyzTxP/dcVVsMq/Ketx7m58sG9yjoh1yjThxaiscwon+cAy+TQ5en46W1asqx4EmcZv/EJKq4a1yiPyBAe2vVVm4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613593577214105.8989237396504; Wed, 17 Feb 2021 12:26:17 -0800 (PST) Received: from localhost ([::1]:56364 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTOp-0002wi-TV for importer@patchew.org; Wed, 17 Feb 2021 15:26:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60884) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTL2-0007M5-7N for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:20 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:54055) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTL0-0007BS-8W for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:19 -0500 Received: by mail-pj1-x102b.google.com with SMTP id c19so2143343pjq.3 for ; Wed, 17 Feb 2021 12:22:17 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/cgl87lXykdJMny21/UJVDiccpgPXiqD0uRpK0C4eyY=; b=EaySR6UeAsJYW/hnOYJBvhhFEfYOwC30x/VPoS8QEZcmSM17yjFHzqnn77nOIeaqIL t+PJ7bG0EUZ9vOe9mZkemyeGn463iQ4DfJSyl+lXPmMUf6pHFVQNM9taup+fRyt/hwwF ONDjNLA0TmR7+e9TERqae+Biw7ccyc40UpCVDbtgsK2Yx8V3BOE7kltQ6uKC0fw/iEpT lOzxxa4F7Fm3ESlEGJ0VBHOFV/DgotvMCPY463oqzqUGd6gEy+kT73TP2LlszvTCifzs Kyv0P0skPwaiVsKpY056dIHWbqwG+otETJqRBiNEjTnICLkPMCXNVUgFdgVdcYwghw5X Ttyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/cgl87lXykdJMny21/UJVDiccpgPXiqD0uRpK0C4eyY=; b=KAMOC0DzPqXuUo6rGgk3G1nE06XRhAjbBTt91jqoBMctvc+YP6FnANawAp2tNFBt9g Z3AR+AkzAazu4iTAz5xybY23RkIg1GUQi2bfOJQ6zrhE3yZwp4mONNy63RTKkHKaQrcq Cq7I8fQ0ZLyqJkrPtCRUVk50b4CzJLDvDJA9TgB2T5JwV4BiCm09QHUWGc0Hh0iW7h3r rO1m4vJoMOxnLVqOq443Pl7Kdb6kFANNVAliVbOrp37yOk2WzXZwDVgho6jTNLq0IVhT 5mHKHdVlBJqux9vvdGBTAo4kMhdLbG4EyFXGXTilKLJVuMrELBcOsZYGN52rKqdgevUj RN1g== X-Gm-Message-State: AOAM530aB0CngywQcTJLixDFzCST3+meZ9E0CK74G5Cvm+vqQZcC/yX9 m9Bfx4KXoZ6Q75QI0EkYQR6aBFpXDEUIpQ== X-Google-Smtp-Source: ABdhPJznstbmwtmLWjA5xxJUgzEyDCOfPvRWYcfkGu7bweWRyHh2kFm5UbD69OkzdGEU8fonQOtmHQ== X-Received: by 2002:a17:902:ce83:b029:de:6b3c:fcd2 with SMTP id f3-20020a170902ce83b02900de6b3cfcd2mr707362plg.67.1613593336973; Wed, 17 Feb 2021 12:22:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 11/71] tcg/tci: Reduce use of tci_read_r64 Date: Wed, 17 Feb 2021 12:19:36 -0800 Message-Id: <20210217202036.1724901-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" In all cases restricted to 64-bit hosts, tcg_read_r is identical. We retain the 64-bit symbol for the single case of INDEX_op_qemu_st_i64. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tci.c | 93 +++++++++++++++++++++++++------------------------------ 1 file changed, 42 insertions(+), 51 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index cef12f263d..9efe69d05f 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ul= ong *regs, TCGReg index) return regs[index]; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) -{ - return tci_read_reg(regs, index); -} -#endif - static void tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) { @@ -146,9 +139,7 @@ static uint64_t tci_read_r64(const tcg_target_ulong *re= gs, static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - uint64_t value =3D tci_read_reg64(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; + return tci_read_r(regs, tb_ptr); } #endif =20 @@ -390,8 +381,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); condition =3D *tb_ptr++; tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; @@ -672,7 +663,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_mov_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i64: @@ -696,7 +687,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st_i64: - t0 =3D tci_read_r64(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint64_t *)(t1 + t2) =3D t0; @@ -706,62 +697,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_add_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; case INDEX_op_sub_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; case INDEX_op_mul_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; case INDEX_op_div_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); break; case INDEX_op_divu_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); break; case INDEX_op_rem_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); break; case INDEX_op_remu_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; case INDEX_op_and_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 & t2); break; case INDEX_op_or_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 | t2); break; case INDEX_op_xor_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 ^ t2); break; =20 @@ -769,41 +760,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_shl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp64 =3D (((1ULL << tmp8) - 1) << tmp16); @@ -811,8 +802,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i64: - t0 =3D tci_read_r64(regs, &tb_ptr); - t1 =3D tci_read_r64(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { @@ -882,21 +873,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap64(t1)); break; #endif #if TCG_TARGET_HAS_not_i64 case INDEX_op_not_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i64 case INDEX_op_neg_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q8ATFxOFO2yR9AaepzxKx2luv+FtTID7dtKlxe4pkRs=; b=BsYjuxPUDPsYndixf5IV+lLZygdkyphnJMX6g2ETbgope4z/6lg+c05tahz7nbnrtC 9CONWuO/Dk0wgn6YUWA07pheFPSqZnBErANhoCjBbmFhupNgnH6zX87V4/oBh/mcHX+4 aN/gB14ftGz6a5BxZAAd0/OepzSaICMzzINoSKnipl8ZaTivxyMrFPJC69o39m70Ktw/ /QTCfzyEWoNNbqyRp5B/qJ413NR9E9sGobiKeRkuueXeHQKOk8+7ey6ivsczOHqpHfRv kQRrm2CVhaKd/L9wX/AMAUzwOLi96ZBu8kj3+3AOeNV9RcxrmvgGAUVZ6f9EE6ps4d0T 1zfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q8ATFxOFO2yR9AaepzxKx2luv+FtTID7dtKlxe4pkRs=; b=uJOq5MRgm5ap+q6ofOLclqqXgh85sQ5yOYzv0l5XSzbo1KlZylGa+FvG8M9Pfq1vDN 6ZWCqL5YHrrHFOBd6ReibKKQglNLmPs4v8PXsl88uJWjkcsM+2nQkNjTFDeulTE94HeY 7KK239xcLeddJIK/HZI7uIh/ztBf2h/DQkyqaVA6vHq4g5xH5W9onFF2eDULDMuUwn0k 5HtWrgnxBaTFrkbFc0wEkXS68vATGP6Br+kWEDolpOGYV/MbWgp2twHgVw2IbvToPMNF 0hGY78TwtIU3tgPOJKOEE7p5MYnOo6Uf8wMBcTSNcFAjRS/wUKVtuuGdMXHOfZRLq/It Z2xw== X-Gm-Message-State: AOAM533yXna6R2wJW3kBGqX0F0cHqwfy82no5svFCbyiaBFSP7GPMlb+ AwXa5ylvIbqRd60JNthTslX5wOmVO18okw== X-Google-Smtp-Source: ABdhPJzzQEJ1MzFOObgFzfQ+np7FFR2MkyFOesq1UlWVpbL3iJrxDL54edZfb6/uQCX2ZTE2AvXHhQ== X-Received: by 2002:a17:90a:2c9:: with SMTP id d9mr526965pjd.67.1613593345200; Wed, 17 Feb 2021 12:22:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 12/71] tcg/tci: Merge basic arithmetic operations Date: Wed, 17 Feb 2021 12:19:37 -0800 Message-Id: <20210217202036.1724901-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This includes add, sub, mul, and, or, xor. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tci.c | 83 +++++++++++++++++-------------------------------------- 1 file changed, 25 insertions(+), 58 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 9efe69d05f..d0bf810781 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -451,26 +451,47 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, *(uint32_t *)(t1 + t2) =3D t0; break; =20 - /* Arithmetic operations (32 bit). */ + /* Arithmetic operations (mixed 32/64 bit). */ =20 - case INDEX_op_add_i32: + CASE_32_64(add) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; - case INDEX_op_sub_i32: + CASE_32_64(sub) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; - case INDEX_op_mul_i32: + CASE_32_64(mul) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; + CASE_32_64(and) + t0 =3D *tb_ptr++; + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, t1 & t2); + break; + CASE_32_64(or) + t0 =3D *tb_ptr++; + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, t1 | t2); + break; + CASE_32_64(xor) + t0 =3D *tb_ptr++; + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, t1 ^ t2); + break; + + /* Arithmetic operations (32 bit). */ + case INDEX_op_div_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); @@ -495,24 +516,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); break; - case INDEX_op_and_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); - break; - case INDEX_op_or_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); - break; - case INDEX_op_xor_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); - break; =20 /* Shift/rotate operations (32 bit). */ =20 @@ -695,24 +698,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, =20 /* Arithmetic operations (64 bit). */ =20 - case INDEX_op_add_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 + t2); - break; - case INDEX_op_sub_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 - t2); - break; - case INDEX_op_mul_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 * t2); - break; case INDEX_op_div_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); @@ -737,24 +722,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; - case INDEX_op_and_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); - break; - case INDEX_op_or_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); - break; - case INDEX_op_xor_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); - break; =20 /* Shift/rotate operations (64 bit). */ =20 --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613594852814629.689828754823; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tPaxTbuiDkAE4NCvOvCez8qzkP8DbZsP3e+2STkMSPw=; b=q88ZXsd43CxDO378vAwGMQurT1lI4lCK7/E6wUKbqkoIeNPu26u/DTNmejlS4fukeh ZMbZiKuUqQluBto/eBin6v6oJbe1681lUkZAIOaYJmjYTsxmMHaglBn6hKpu7+W9YJ5s mPQE5Xk4mrISOvMcPP0VSuZEudpVcqUEIK8Myn+cc2Sza4Io15clzJ927/sRbwVx1NtN /g3OdsPhi5HuY0qmdRsCmQ8ZjgAAr4S0IEPt2UI0labJ+EWrLdBe9vnR2S/df/cXUCfp zjtj2m8ZMzARXlFHZ0sL6J2JWkwN/9S4UNJIIbV3Vhbia4Nwelr3YNDVBOtXzKXR8Ydn 5QKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tPaxTbuiDkAE4NCvOvCez8qzkP8DbZsP3e+2STkMSPw=; b=nQJaO4KSqKXxlTGBASi18O16N7I2C1Nb/nJ9KSROQDhJ4o2ETRhU/QaThM3hUqe4H7 3vcIUEh+bbjo4BAQrl+9NWg1sMSL+yyXTP9IkGiNTWNSSWzvFZmd7ym7SPDLJIkUDJg7 swR/3CkwC0+qQkFv+cqlyvRtl1Z1WiH7+ZQ669uI6zPHBtzfjHI6CjFaQDD4rIQg+Vgs oIY1XIjo6s4eeHaIBzDpkMGWv2GlCTVKbapp65+UeZU7F2WWOQbh7nbIOAu63b1vFBuc IBwY0/IdYkYTSg7IYG/G33xGIImT2YuK7KDlvp/Z9FhApHLHOWOSvLVSCbBlc60SLdpM 75DA== X-Gm-Message-State: AOAM532nICWkc7jWDv0EmIpSvrI1LOKOFq+PjLXjqgFzGaHzgRgG878m PH/QaHP81FVI03t5ClljnXrFrKENpFLvZQ== X-Google-Smtp-Source: ABdhPJxb4PFk3HCiryJnyZCt0iPoo+K47Il1vq19OAzg+uTnan9gbgt03+PcbfylJmcuufNEqE+jRA== X-Received: by 2002:a17:90a:19d0:: with SMTP id 16mr521299pjj.121.1613593348167; Wed, 17 Feb 2021 12:22:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 13/71] tcg/tci: Merge extension operations Date: Wed, 17 Feb 2021 12:19:38 -0800 Message-Id: <20210217202036.1724901-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This includes ext8s, ext8u, ext16s, ext16u. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tci.c | 44 ++++++++------------------------------------ 1 file changed, 8 insertions(+), 36 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index d0bf810781..73f639d23a 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -607,29 +607,29 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ -#if TCG_TARGET_HAS_ext8s_i32 - case INDEX_op_ext8s_i32: +#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 + CASE_32_64(ext8s) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int8_t)t1); break; #endif -#if TCG_TARGET_HAS_ext16s_i32 - case INDEX_op_ext16s_i32: +#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 + CASE_32_64(ext16s) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int16_t)t1); break; #endif -#if TCG_TARGET_HAS_ext8u_i32 - case INDEX_op_ext8u_i32: +#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 + CASE_32_64(ext8u) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint8_t)t1); break; #endif -#if TCG_TARGET_HAS_ext16u_i32 - case INDEX_op_ext16u_i32: +#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 + CASE_32_64(ext16u) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint16_t)t1); @@ -779,34 +779,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, continue; } break; -#if TCG_TARGET_HAS_ext8u_i64 - case INDEX_op_ext8u_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint8_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext8s_i64 - case INDEX_op_ext8s_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (int8_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext16s_i64 - case INDEX_op_ext16s_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (int16_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext16u_i64 - case INDEX_op_ext16u_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint16_t)t1); - break; -#endif #if TCG_TARGET_HAS_ext32s_i64 case INDEX_op_ext32s_i64: #endif --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613593724; cv=none; d=zohomail.com; s=zohoarc; b=mhQ209AsghHzaguVOi/qwCq6cOt0mH47LEwepghhUgNVuU7PbgCOUapXufJ31pJLceU309s0R7TCr1PPd6Q60aOBQnQCerbHVUZ7h0gVPYGi+FRoWeYyTJPw+QSvhWJkgbB+MgsQC+dsMZ5klK6WYAuTuaIkgDkT4PQq6OXShxo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613593724; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xccDHlZG+A/og+PXFW/xFbu9lxlDn8hKgHX6EMXyYhQ=; b=fuLe1QcR5phPC43pis2HuFcSfk5Bd9ge588qoXQcEEWDdURMCg5RWeW23UFc0908ySfFKebuBo/4xw6ZQPg1lDs9cnbTA/lPM/W7IOe4mATJu/8NezIJwt0XPgX++LTeXvpgOSQ8dds4M1cp4kMIagQCGLti9/bV5WrQNrlAj3Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613593723760466.87865755880875; Wed, 17 Feb 2021 12:28:43 -0800 (PST) Received: from localhost ([::1]:35732 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTRC-00067R-Eq for importer@patchew.org; Wed, 17 Feb 2021 15:28:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60968) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTLF-0007oE-Iy for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:33 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:51741) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTLE-0007G6-1T for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:33 -0500 Received: by mail-pj1-x102d.google.com with SMTP id fa16so2147545pjb.1 for ; Wed, 17 Feb 2021 12:22:31 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xccDHlZG+A/og+PXFW/xFbu9lxlDn8hKgHX6EMXyYhQ=; b=YtqmEbw+3CVvTfaofmW8HQBsfLh0yQa2t2aOmlIDcPJr0JyMO33W4x50/dNsQ5FQSn KF6fM0dxcflZReutsLTlOTOgAPvqdApiIKe+V0lGEyTPobWBA1tK3R7lb4fc+e882X5L tXa6EmC2G+S99ssGhowE/cPXoN/1bkAMmUrGcXLuo8125q9UKdj61PiPc12UM9AyJ9ZH SGfpZb9RvH9BT4S8zv8D0SIVFU4KHzRTyAnBd6R2GNiJAMZjRgZ/J6tXtJ6BW7kv4Q3h Yk4C6PPI/xd7Zw3juAMIGcQhcEogTUEmTU5LZ3Ps4ZHUdjBa7pSpyVL68y7bfKeD0Wjm 2KIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xccDHlZG+A/og+PXFW/xFbu9lxlDn8hKgHX6EMXyYhQ=; b=G4gOQ9bjxSpPMNlWNM5SXHywlPcYITuvinG/766CLGqCqqG/gVE+Sfs2bV7FmueTn9 CZmePIPq9vslCf6obkW76HUoKEk+U9vLA291dyoafAjxj0AuPTyVoEfP6AVxLmKksEmm WrJV4EB7kIn2RuOLIsV3vzCIi4/oh06Cy5jVd7G2jg4+enxuIbhCV8BR9150wp7Aw+Q/ sAjpdYIQKnuwVdACktiHnSFRVp+X3vO0xwtjG7lB77W3z6GkJIO3PauQftas9f7fotya VlWkZAdqejv+45yeXob0V/3eotToHERNwqYtx/1klTr5y2GpsL/Ch2cTNdwUkPxD4TEv TP/g== X-Gm-Message-State: AOAM530TRgBtRJcl0PMW7y8/bKSt892M2hAL1lv9LNvsOnlQZfXSSMhG 9sRekz71Cu+qhKY1RrwIZMKbmhryXY7g0w== X-Google-Smtp-Source: ABdhPJyUIkJJzpe8Z4E/9uHBJsXBaQXvBhMltP7Vev8uPqvRANKaCpIKplXpjujllob40+oXGvTERg== X-Received: by 2002:a17:90b:1649:: with SMTP id il9mr545479pjb.62.1613593350784; Wed, 17 Feb 2021 12:22:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 14/71] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64 Date: Wed, 17 Feb 2021 12:19:39 -0800 Message-Id: <20210217202036.1724901-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" These operations are always available under different names: INDEX_op_ext_i32_i64 and INDEX_op_extu_i32_i64, so we remove no code with the ifdef. Signed-off-by: Richard Henderson --- tcg/tci.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 73f639d23a..a5ee37eb4e 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -779,17 +779,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, continue; } break; -#if TCG_TARGET_HAS_ext32s_i64 case INDEX_op_ext32s_i64: -#endif case INDEX_op_ext_i32_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1); break; -#if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: -#endif case INDEX_op_extu_i32_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613594626; cv=none; d=zohomail.com; s=zohoarc; b=L0komYhqloXGjQ/vZOKBhrSrqClwPRGYLqoXmcCIIJVW36RL7AYi2PT0RcIFoS06ui5Z4R5tAVg6Q4mYqgXYkz5SxIlVM8NnmudSTlw5+C6J1Aomnn9OCUJunN5lJ04iy5aRM1D4XJ2AymVp9yDJFAnbze+78lvk9NLVcVqs5Hs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613594626; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OneSdNbhFRwD/gEDSE1iypW9deQBMDbQopH2CXvtbwE=; b=JRoKHgXmAW06n66qQkYRbtFFGx+q6CoqB5zmcjAdcAqDW4Vowb4pXS/PeMSKHJU92pBghhgX12L7602tqqr7aqFjnX8paBt1yK4l38zdcSpc8WwSjsnZwFFHe6SozXLECcq+xFQJsb8FAEfyC3+07HLMpGIMdjvt8sJb0pmdKeU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613594625744650.9578493212939; Wed, 17 Feb 2021 12:43:45 -0800 (PST) Received: from localhost ([::1]:42142 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTfi-00040R-VY for importer@patchew.org; Wed, 17 Feb 2021 15:43:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60988) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTLG-0007rB-Rr for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:34 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:54054) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTLF-0007GG-B7 for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:34 -0500 Received: by mail-pj1-x1029.google.com with SMTP id c19so2143701pjq.3 for ; Wed, 17 Feb 2021 12:22:32 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OneSdNbhFRwD/gEDSE1iypW9deQBMDbQopH2CXvtbwE=; b=w1z/tEvSl4UvzRpU4Yns377zAFekAd0cAm0jjD6Urf4KkeeSuW8LVC4YdVx/TSGAja k8XZinSlvCZuMTCbiQTfgN5sfJekMD28pcED438TprklN5nWdU+rvtac3BPCuIemGFbX wJk8Uf60iUPNelfNbAdPPH0ZaPqwKpj0m42xzAcMCGlrs126mql1oafz00M1Vg9T+3AK pYT4qJm99DLlli89PRt3tY3tKro1UbkJ6h7sjV3KaiP5Hk7Oz9672Z0wBkbl0R7dSwBk xzR49XTGAXe2bx8tWGvFQxbOnc44IVbWqU+5SKNcQuvAOkthnPhVYU2EG8f+d/8VHyDA DJmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OneSdNbhFRwD/gEDSE1iypW9deQBMDbQopH2CXvtbwE=; b=XpYN2mZvfwHZQdJ34lD3DFbgzz/GC4rxCoBXCwc5/mMynoR8iZMPLWGz8/bzZPiJfD GbSPmgPI7J97QhAABubEV+oqVsvRmXtAyBiNK1FkPP0HFYvysCMTSrs/FJv6UD98j2xM xutC48dBakprL5pIb45EQ/GqCRJNelqDbBnONGpfKwN4SQgioPDTLRTxgWMgy6UybsKh 6EI1r+yp46ZArqiCfWLxdpsS7InuZul8fXR/KUNIv5acUQGafUpLg2U+2/IytxmncJWq HUrYZj2Ui0rN/GMcvAJSDsEk5TpzzYLWf+WYS7nNgxGHQuIuwk3P5rrVgZ4MR3ktodV2 /g5Q== X-Gm-Message-State: AOAM531Try4oG6e2iyFUVh5X+eU4LBWCZRSBDUPTxkWwzqSho8yTx70G N6T48M+426C98S/02XjVnVuoGYb0ma2SyA== X-Google-Smtp-Source: ABdhPJzqQntpHhtXR0eotyEAd4esY8IHBwBGHEkXaS9IH9vvoZnFBYnsUYcvO1AP4V1IQzIJIMYECw== X-Received: by 2002:a17:902:52a:b029:da:989f:6c01 with SMTP id 39-20020a170902052ab02900da989f6c01mr721322plf.45.1613593352065; Wed, 17 Feb 2021 12:22:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 15/71] tcg/tci: Merge bswap operations Date: Wed, 17 Feb 2021 12:19:40 -0800 Message-Id: <20210217202036.1724901-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This includes bswap16 and bswap32. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tci.c | 22 ++++------------------ 1 file changed, 4 insertions(+), 18 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index a5ee37eb4e..288a70287e 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -635,15 +635,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tci_write_reg(regs, t0, (uint16_t)t1); break; #endif -#if TCG_TARGET_HAS_bswap16_i32 - case INDEX_op_bswap16_i32: +#if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 + CASE_32_64(bswap16) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif -#if TCG_TARGET_HAS_bswap32_i32 - case INDEX_op_bswap32_i32: +#if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 + CASE_32_64(bswap32) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); @@ -791,20 +791,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1); break; -#if TCG_TARGET_HAS_bswap16_i64 - case INDEX_op_bswap16_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap16(t1)); - break; -#endif -#if TCG_TARGET_HAS_bswap32_i64 - case INDEX_op_bswap32_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap32(t1)); - break; -#endif #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 =3D *tb_ptr++; --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161359397213930.30692291011644; Wed, 17 Feb 2021 12:32:52 -0800 (PST) Received: from localhost ([::1]:44300 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTVC-0001Nn-V3 for importer@patchew.org; Wed, 17 Feb 2021 15:32:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60998) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTLI-0007u0-4p for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:36 -0500 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:41788) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTLG-0007H0-K9 for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:35 -0500 Received: by mail-pg1-x52b.google.com with SMTP id t11so9205589pgu.8 for ; Wed, 17 Feb 2021 12:22:34 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tci.c | 29 +++++------------------------ 1 file changed, 5 insertions(+), 24 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 288a70287e..6a0bdf028b 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -387,7 +387,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; #endif - case INDEX_op_mov_i32: + CASE_32_64(mov) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1); @@ -649,26 +649,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tci_write_reg(regs, t0, bswap32(t1)); break; #endif -#if TCG_TARGET_HAS_not_i32 - case INDEX_op_not_i32: +#if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 + CASE_32_64(not) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif -#if TCG_TARGET_HAS_neg_i32 - case INDEX_op_neg_i32: +#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 + CASE_32_64(neg) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif #if TCG_TARGET_REG_BITS =3D=3D 64 - case INDEX_op_mov_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); - break; case INDEX_op_tci_movi_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_i64(&tb_ptr); @@ -798,20 +793,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_write_reg(regs, t0, bswap64(t1)); break; #endif -#if TCG_TARGET_HAS_not_i64 - case INDEX_op_not_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, ~t1); - break; -#endif -#if TCG_TARGET_HAS_neg_i64 - case INDEX_op_neg_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, -t1); - break; -#endif #endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ =20 /* QEMU specific operations. */ --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613595086; cv=none; d=zohomail.com; s=zohoarc; b=SxYlDEn4j7fRhCkDxnPSdS2e5lGkK1LhOR+P6oSVdGPZXEllDnS1oCR9dk4IPMKofRmqFJatCFOvlfpCLbObkBFZ7zSoL/jmhAQXEo1ZDMtJDxLm0fSUwfkfepVCgDAnF9AIVgPuVARloLckD2kXAQ/iqBScxmmVd/9xtl6HNXE= ARC-Message-Signature: i=1; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HbTxBt2WPdzVO5wl5gS1nGoA2iunBjuWMOYCOEc7KuY=; b=rJgM/yrvA5fp/eJbRknV7KB2u4XuxCXJY+PrgeCuOzdZSMsqimvSD8IsEOgwk2knCS eM7jtlRdmTCSvRT5eTWcZQ3NX19Jei0lJZlSrSO0U19EPCDyMuX1KpwJdNoUGLSTJ1zk GizHctoKQrKxDzHVLu2EXvweTrVAVOsocIv7jPHtjfiaatmttEF9lhuM09QryqPWM6gP 5/fL63hBQzVzXdheAOZXL2sjWNjLMWoFw8A/SejUEgha87i7crO0h9xGIHZZgpd8FfFj qzmc3X2hKBsur1783GbbXkDGx/z63ASyelM1qbHN/quOPI4xwT5xdxLRNbC/1Uf428mQ l16w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HbTxBt2WPdzVO5wl5gS1nGoA2iunBjuWMOYCOEc7KuY=; b=IM8FX93OmaDmfehGjzT6w0RSkcY/uaFs+glR/+teGHcybVaPf3hdZ0KiUdyiKhGpHM 0jFisOwrKgKFoI9bN0PTeKn6vrcychE4bK6I2GVs4tmyY1F+9+vcqudv49elCuI9fsD7 H8tf1N90LYXfoZ9u05DVo/Z56xDyW3qa3GY8lfxmwDWnap5U8dZi/sCKbZF8U4X5XhqI dM5N1PIZI3lXuqEtGDjRHHAJI8+GtFe4/2spW3P2DYqRM4uhqc8zqqyskO6G0jE/PV30 eKp2PoJahAbSKSN7hA8Xz301Cmp2kH5xpzO73l/gwWL4gHAPpXfE5RgTRqQKDX1GsA4K 7H5g== X-Gm-Message-State: AOAM531ACoLBXVzzVv+v0hI+HqdMNbDoGMriwObCix0RbYv6kebAd212 G2/z+5AwYIT9Oq+cBg5/hp6V/iaADlxc7g== X-Google-Smtp-Source: ABdhPJyP86sHa0Swpx56GGA2OYpehkjFJjoE1LGq91SwEMqI8y8bh/t5agcL7i1wdxQI7dNN1teimw== X-Received: by 2002:a62:8453:0:b029:1e4:3a6a:d5ba with SMTP id k80-20020a6284530000b02901e43a6ad5bamr945351pfd.54.1613593355122; Wed, 17 Feb 2021 12:22:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 17/71] tcg/tci: Rename tci_read_r to tci_read_rval Date: Wed, 17 Feb 2021 12:19:42 -0800 Message-Id: <20210217202036.1724901-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" In the next patches, we want to use tci_read_r to return the raw register number. So rename the existing function, which returns the register value, to tci_read_rval. Signed-off-by: Richard Henderson --- tcg/tci.c | 192 +++++++++++++++++++++++++++--------------------------- 1 file changed, 96 insertions(+), 96 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 6a0bdf028b..6d6a5510da 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -119,7 +119,7 @@ static uint64_t tci_read_i64(const uint8_t **tb_ptr) =20 /* Read indexed register (native size) from bytecode. */ static tcg_target_ulong -tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) +tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { tcg_target_ulong value =3D tci_read_reg(regs, **tb_ptr); *tb_ptr +=3D 1; @@ -131,15 +131,15 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_= t **tb_ptr) static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - uint32_t low =3D tci_read_r(regs, tb_ptr); - return tci_uint64(tci_read_r(regs, tb_ptr), low); + uint32_t low =3D tci_read_rval(regs, tb_ptr); + return tci_uint64(tci_read_rval(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 /* Read indexed register (64 bit) from bytecode. */ static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - return tci_read_r(regs, tb_ptr); + return tci_read_rval(regs, tb_ptr); } #endif =20 @@ -147,9 +147,9 @@ static uint64_t tci_read_r64(const tcg_target_ulong *re= gs, static target_ulong tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - target_ulong taddr =3D tci_read_r(regs, tb_ptr); + target_ulong taddr =3D tci_read_rval(regs, tb_ptr); #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - taddr +=3D (uint64_t)tci_read_r(regs, tb_ptr) << 32; + taddr +=3D (uint64_t)tci_read_rval(regs, tb_ptr) << 32; #endif return taddr; } @@ -365,8 +365,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, continue; case INDEX_op_setcond_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); condition =3D *tb_ptr++; tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); break; @@ -381,15 +381,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); condition =3D *tb_ptr++; tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; #endif CASE_32_64(mov) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i32: @@ -402,51 +402,51 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 CASE_32_64(ld8u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2)); break; CASE_32_64(ld8s) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); break; CASE_32_64(ld16u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2)); break; CASE_32_64(ld16s) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(int16_t *)(t1 + t2)); break; case INDEX_op_ld_i32: CASE_64(ld32u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); break; CASE_32_64(st8) - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) =3D t0; break; CASE_32_64(st16) - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) =3D t0; break; case INDEX_op_st_i32: CASE_64(st32) - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint32_t *)(t1 + t2) =3D t0; break; @@ -455,38 +455,38 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 CASE_32_64(add) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; CASE_32_64(sub) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; CASE_32_64(mul) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; CASE_32_64(and) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 & t2); break; CASE_32_64(or) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 | t2); break; CASE_32_64(xor) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 ^ t2); break; =20 @@ -494,26 +494,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_div_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); break; case INDEX_op_divu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2); break; case INDEX_op_rem_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); break; case INDEX_op_remu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); break; =20 @@ -521,41 +521,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_shl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31)); break; case INDEX_op_shr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31)); break; case INDEX_op_sar_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31)); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, rol32(t1, t2 & 31)); break; case INDEX_op_rotr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ror32(t1, t2 & 31)); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp32 =3D (((1 << tmp8) - 1) << tmp16); @@ -563,8 +563,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i32: - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare32(t0, t1, condition)) { @@ -602,64 +602,64 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, case INDEX_op_mulu2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - t2 =3D tci_read_r(regs, &tb_ptr); - tmp64 =3D (uint32_t)tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); + tmp64 =3D (uint32_t)tci_read_rval(regs, &tb_ptr); tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 CASE_32_64(ext16s) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int16_t)t1); break; #endif #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 CASE_32_64(ext8u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 CASE_32_64(ext16u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint16_t)t1); break; #endif #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 CASE_32_64(bswap16) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 CASE_32_64(bswap32) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 CASE_32_64(not) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 CASE_32_64(neg) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif @@ -674,19 +674,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_ld32s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(int32_t *)(t1 + t2)); break; case INDEX_op_ld_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st_i64: - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint64_t *)(t1 + t2) =3D t0; break; @@ -695,26 +695,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_div_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); break; case INDEX_op_divu_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); break; case INDEX_op_rem_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); break; case INDEX_op_remu_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; =20 @@ -722,41 +722,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_shl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp64 =3D (((1ULL << tmp8) - 1) << tmp16); @@ -764,8 +764,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i64: - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { @@ -777,19 +777,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, case INDEX_op_ext32s_i64: case INDEX_op_ext_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1); break; case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1); break; #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, bswap64(t1)); break; #endif @@ -896,7 +896,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, } break; case INDEX_op_qemu_st_i32: - t0 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613594144183619.0496733544361; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=37vrLTjOf1a+ywG8JRaN/eT08mH7//Hhw6kYDqN5YOo=; b=Ygca+fC9eoeyVIyDE2xIp1nK5GOPDLMBwVJ7QaFDeIDHki9uyjaLrim2ZM6b02/qpi lDQwRFxJbcXTdZz/flWu697teKwtDuvkawoFeYXR1wp3FBsWn0RpDY2aF/YQLVjQRRWQ yJv4CFxu9Y0gLUdSaPqFU6vKCPpp1wc/WrTEjdZ37a6vl+I50H0aGUQETZknMYQ55blh 8jI6AZFXeaIXi55sj/KaocU0EHb8Us31bV+tl06Rqp+YDsr9v2DoefKsKjVy7KVmxO8x OBW7EFfWG5YZptJ4pH4E8b2yEQu8MjumyZ8r73VmdrGVu5YrVhiMNJ9xRx1m94DTeiQC JVyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=37vrLTjOf1a+ywG8JRaN/eT08mH7//Hhw6kYDqN5YOo=; b=GHneAvqfPvV9trtW09lacv+9lA4a8rCqa35Vhlz+WcxpfH/ze6OJYnL3H5d1ZiCGP2 SLiRvhtT49AL2WC3anv7M3hlIG0GZOQecBoDDXErtDyFVMBUKjw1RnZccFpXK4LUPD6o VqxMfAZNDIqNXp300IqNH2kEiXR2M3XPGN4n+XtSv8oCbRFqJu5u8ZIYjxRDETmWkPeg pdy/qIZcTMA1uMIzmzIoADSd8hI6BEhqfg8XW54tW/QBbKXdgo3rrLevY7W9uD+hSul4 THWwDM6Bkb7xLlxXPxMPW6WsUB67gcaj+bPWU5LtR9tRuVd36l7jWlMwOjWmcKccW8cX TGdA== X-Gm-Message-State: AOAM532rKVfdQSr1q8MeAVYdk57h/TtZBaBz2fbKvP7ewUkHMcRHIcOZ qrfevVU9LJpVhxEIUFOvea/G9L5nxBS9VQ== X-Google-Smtp-Source: ABdhPJzdvIedwJYlkdcw8rYsKrEZVlJodUiBxnv4DeTJmF9CkXQe/TTlD/MycJ5rwZw/nNiFqY7QBQ== X-Received: by 2002:a63:da03:: with SMTP id c3mr947623pgh.176.1613593356862; Wed, 17 Feb 2021 12:22:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 18/71] tcg/tci: Split out tci_args_rrs Date: Wed, 17 Feb 2021 12:19:43 -0800 Message-Id: <20210217202036.1724901-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Begin splitting out functions that do pure argument decode, without actually loading values from the register set. This means that decoding need not concern itself between input and output registers. We can assert that the register number is in range during decode, so that it is safe to simply dereference from regs[] later. Signed-off-by: Richard Henderson --- tcg/tci.c | 111 ++++++++++++++++++++++++++++++++---------------------- 1 file changed, 67 insertions(+), 44 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 6d6a5510da..5acf5c38c3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -83,6 +83,20 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low) } #endif =20 +/* Read constant byte from bytecode. */ +static uint8_t tci_read_b(const uint8_t **tb_ptr) +{ + return *(tb_ptr[0]++); +} + +/* Read register number from bytecode. */ +static TCGReg tci_read_r(const uint8_t **tb_ptr) +{ + uint8_t regno =3D tci_read_b(tb_ptr); + tci_assert(regno < TCG_TARGET_NB_REGS); + return regno; +} + /* Read constant (native size) from bytecode. */ static tcg_target_ulong tci_read_i(const uint8_t **tb_ptr) { @@ -161,6 +175,23 @@ static tcg_target_ulong tci_read_label(const uint8_t *= *tb_ptr) return label; } =20 +/* + * Load sets of arguments all at once. The naming convention is: + * tci_args_ + * where arguments is a sequence of + * + * r =3D register + * s =3D signed ldst offset + */ + +static void tci_args_rrs(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, int32_t *i2) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *i2 =3D tci_read_s32(tb_ptr); +} + static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { bool result =3D false; @@ -311,6 +342,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint8_t op_size =3D tb_ptr[1]; const uint8_t *old_code_ptr =3D tb_ptr; #endif + TCGReg r0, r1; tcg_target_ulong t0; tcg_target_ulong t1; tcg_target_ulong t2; @@ -325,6 +357,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint64_t v64; #endif TCGMemOpIdx oi; + int32_t ofs; + void *ptr; =20 /* Skip opcode and size entry. */ tb_ptr +=3D 2; @@ -401,54 +435,46 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, /* Load/store operations (32 bit). */ =20 CASE_32_64(ld8u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint8_t *)ptr; break; CASE_32_64(ld8s) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(int8_t *)ptr; break; CASE_32_64(ld16u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint16_t *)ptr; break; CASE_32_64(ld16s) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(int16_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(int16_t *)ptr; break; case INDEX_op_ld_i32: CASE_64(ld32u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint32_t *)ptr; break; CASE_32_64(st8) - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - *(uint8_t *)(t1 + t2) =3D t0; + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + *(uint8_t *)ptr =3D regs[r0]; break; CASE_32_64(st16) - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - *(uint16_t *)(t1 + t2) =3D t0; + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + *(uint16_t *)ptr =3D regs[r0]; break; case INDEX_op_st_i32: CASE_64(st32) - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - *(uint32_t *)(t1 + t2) =3D t0; + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + *(uint32_t *)ptr =3D regs[r0]; break; =20 /* Arithmetic operations (mixed 32/64 bit). */ @@ -673,22 +699,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, /* Load/store operations (64 bit). */ =20 case INDEX_op_ld32s_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(int32_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(int32_t *)ptr; break; case INDEX_op_ld_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint64_t *)ptr; break; case INDEX_op_st_i64: - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 67 +++++++++++++++++++++++++------------------------------ 1 file changed, 31 insertions(+), 36 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 5acf5c38c3..e5aba3a9fa 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -184,6 +184,13 @@ static tcg_target_ulong tci_read_label(const uint8_t *= *tb_ptr) * s =3D signed ldst offset */ =20 +static void tci_args_rr(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); +} + static void tci_args_rrs(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, int32_t *i2) { @@ -422,9 +429,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif CASE_32_64(mov) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D regs[r1]; break; case INDEX_op_tci_movi_i32: t0 =3D *tb_ptr++; @@ -635,58 +641,50 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int8_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (int8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 CASE_32_64(ext16s) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int16_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (int16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 CASE_32_64(ext8u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint8_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (uint8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 CASE_32_64(ext16u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint16_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (uint16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 CASE_32_64(bswap16) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap16(t1)); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D bswap16(regs[r1]); break; #endif #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 CASE_32_64(bswap32) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap32(t1)); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D bswap32(regs[r1]); break; #endif #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 CASE_32_64(not) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, ~t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D ~regs[r1]; break; #endif #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 CASE_32_64(neg) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, -t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D -regs[r1]; break; #endif #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -799,21 +797,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; case INDEX_op_ext32s_i64: case INDEX_op_ext_i32_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (int32_t)regs[r1]; break; case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (uint32_t)regs[r1]; break; #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap64(t1)); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D bswap64(regs[r1]); break; #endif #endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613595295; cv=none; d=zohomail.com; s=zohoarc; b=QcsOc4tf5DjnBPz5w9ekIUmg6uofAc38yFCMm4AaXkcPKn8Wt41GxbOMBdMluxc4gGfRby1YkOE35YEm515idwu+F+xrfegsG5HkvZ83bOJdf1AjOhRDY0tUoavH7ZZXQgi7nX3XQBlJ3BR5CSNouU7vU7VF0Bcnm5OrJJz4m/M= ARC-Message-Signature: i=1; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JTYpj8j1BDaPmAY+nQ2t8wqeA00FmJJ79xXvarenAZc=; b=VSIEpuYy1KK6CMXSFshvldt+HmJCp4wCM+haWpdRDsY1W0URVXJ5JoKB9KaJIsd1Gr hzS7DSlbPkaEZ9cpqcBYBOmhFHvhS3C6PFi8Gf+4bCd4uflSadLdWfUfCmb6Ng1PSpHR s9RsVE5NjFgtUUPgTkobZAuchHk6yMoHwwzQfIFYm4Hpf66pXY0p/C1k0YKHcjIl0Frt 1wTKvhHt2KgYdR/eNGh7qLACP2/T8Bvq0Pi+wpHgLti9uwjNrfiL5lX7L4byxUuVNWLw I+0jgeE85Nu0DTpp5HK1WTWLqT6C1y0/jUJk8epuJZHHqPrqcKEIIrnptRnq4fJ1Qnym Cp7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JTYpj8j1BDaPmAY+nQ2t8wqeA00FmJJ79xXvarenAZc=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 154 ++++++++++++++++++++---------------------------------- 1 file changed, 57 insertions(+), 97 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index e5aba3a9fa..1c879a2536 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -191,6 +191,14 @@ static void tci_args_rr(const uint8_t **tb_ptr, *r1 =3D tci_read_r(tb_ptr); } =20 +static void tci_args_rrr(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); +} + static void tci_args_rrs(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, int32_t *i2) { @@ -349,7 +357,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint8_t op_size =3D tb_ptr[1]; const uint8_t *old_code_ptr =3D tb_ptr; #endif - TCGReg r0, r1; + TCGReg r0, r1, r2; tcg_target_ulong t0; tcg_target_ulong t1; tcg_target_ulong t2; @@ -486,101 +494,71 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchS= tate *env, /* Arithmetic operations (mixed 32/64 bit). */ =20 CASE_32_64(add) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 + t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] + regs[r2]; break; CASE_32_64(sub) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 - t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] - regs[r2]; break; CASE_32_64(mul) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 * t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] * regs[r2]; break; CASE_32_64(and) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] & regs[r2]; break; CASE_32_64(or) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] | regs[r2]; break; CASE_32_64(xor) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] ^ regs[r2]; break; =20 /* Arithmetic operations (32 bit). */ =20 case INDEX_op_div_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int32_t)regs[r1] / (int32_t)regs[r2]; break; case INDEX_op_divu_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint32_t)regs[r1] / (uint32_t)regs[r2]; break; case INDEX_op_rem_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int32_t)regs[r1] % (int32_t)regs[r2]; break; case INDEX_op_remu_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint32_t)regs[r1] % (uint32_t)regs[r2]; break; =20 /* Shift/rotate operations (32 bit). */ =20 case INDEX_op_shl_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint32_t)regs[r1] << (regs[r2] & 31); break; case INDEX_op_shr_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint32_t)regs[r1] >> (regs[r2] & 31); break; case INDEX_op_sar_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int32_t)regs[r1] >> (regs[r2] & 31); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, rol32(t1, t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D rol32(regs[r1], regs[r2] & 31); break; case INDEX_op_rotr_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, ror32(t1, t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D ror32(regs[r1], regs[r2] & 31); break; #endif #if TCG_TARGET_HAS_deposit_i32 @@ -715,62 +693,44 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, /* Arithmetic operations (64 bit). */ =20 case INDEX_op_div_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int64_t)regs[r1] / (int64_t)regs[r2]; break; case INDEX_op_divu_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint64_t)regs[r1] / (uint64_t)regs[r2]; break; case INDEX_op_rem_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int64_t)regs[r1] % (int64_t)regs[r2]; break; case INDEX_op_remu_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint64_t)regs[r1] % (uint64_t)regs[r2]; break; =20 /* Shift/rotate operations (64 bit). */ =20 case INDEX_op_shl_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 << (t2 & 63)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] << (regs[r2] & 63); break; case INDEX_op_shr_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 >> (t2 & 63)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] >> (regs[r2] & 63); break; case INDEX_op_sar_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int64_t)regs[r1] >> (regs[r2] & 63); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, rol64(t1, t2 & 63)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D rol64(regs[r1], regs[r2] & 63); break; case INDEX_op_rotr_i64: - t0 =3D *tb_ptr++; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BT+fbUWdo2Z5pG47CxveBKKbFIzxyg6+zMffoyRH9Us=; b=PC0tvNLPwANw9F53zcwvjAyGCgpRj9nbl4QTRqolTDl3w0o4OjR40i2nlalIzmJ+Jg wkFdoHLeqvSKYhrMJLg5SvGElxpHgYxZNMZE/xy8Or2xs6p88+r3ee31C7N8FsuwsNXV 2EK9wWHUccyLbgVn6kW1Ulv9ez61Qyq9DEhXIkbSGdTBAMXoCkHcbcrX7r3AcZ2+0bxN egooAN4ShkpWMnDY4FuuFn076NMeg8GBZUB1gci3gTrG2M8+Hg+fNXtB/xCsLR6tK2gw VhTwHFpHpHL8VcyyMwc69vNfBsgLl2AhIrEV6JAC6iwQNxrrogq+EfsgPIjGhhRieHCX miEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BT+fbUWdo2Z5pG47CxveBKKbFIzxyg6+zMffoyRH9Us=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 1c879a2536..bdd2127ec8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -207,6 +207,15 @@ static void tci_args_rrs(const uint8_t **tb_ptr, *i2 =3D tci_read_s32(tb_ptr); } =20 +static void tci_args_rrrc(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *c3 =3D tci_read_b(tb_ptr); +} + static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { bool result =3D false; @@ -413,11 +422,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tb_ptr =3D (uint8_t *)label; continue; case INDEX_op_setcond_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - condition =3D *tb_ptr++; - tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); + tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + regs[r0] =3D tci_compare32(regs[r1], regs[r2], condition); break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: @@ -429,11 +435,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, break; #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - condition =3D *tb_ptr++; - tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); + tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + regs[r0] =3D tci_compare64(regs[r1], regs[r2], condition); break; #endif CASE_32_64(mov) --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613595083; cv=none; d=zohomail.com; s=zohoarc; b=YSUCoKrpm1SfqW44EqaGxf+Ue+lZi0v4C0DKgVswEdEBnDPS2XtoNAb0eVToJT+XAwo9lpUIg+j8E+WgDgL8XRPIG54Mqm3BzUpQMPUY4iXXNYlLnP88JyWypn6JoSuim4bI2XPzSgTZvOhTnOdwfQoNqLEaB9QjZERKNcM3sUs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613595083; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index bdd2127ec8..6e9d482885 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -184,6 +184,11 @@ static tcg_target_ulong tci_read_label(const uint8_t *= *tb_ptr) * s =3D signed ldst offset */ =20 +static void tci_args_l(const uint8_t **tb_ptr, void **l0) +{ + *l0 =3D (void *)tci_read_label(tb_ptr); +} + static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { @@ -417,9 +422,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif break; case INDEX_op_br: - label =3D tci_read_label(&tb_ptr); + tci_args_l(&tb_ptr, &ptr); tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr =3D (uint8_t *)label; + tb_ptr =3D ptr; continue; case INDEX_op_setcond_i32: tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613594327043878.3122079031061; Wed, 17 Feb 2021 12:38:47 -0800 (PST) Received: from localhost ([::1]:57170 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTav-0006s4-NA for importer@patchew.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 6e9d482885..558d03fd1b 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -221,6 +221,19 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, *c3 =3D tci_read_b(tb_ptr); } =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 +static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); + *r4 =3D tci_read_r(tb_ptr); + *c5 =3D tci_read_b(tb_ptr); +} +#endif + static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { bool result =3D false; @@ -383,7 +396,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 - uint64_t v64; + TCGReg r3, r4; + uint64_t v64, T1, T2; #endif TCGMemOpIdx oi; int32_t ofs; @@ -432,11 +446,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: - t0 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(regs, &tb_ptr); - v64 =3D tci_read_r64(regs, &tb_ptr); - condition =3D *tb_ptr++; - tci_write_reg(regs, t0, tci_compare64(tmp64, v64, condition)); + tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &condition); + T1 =3D tci_uint64(regs[r2], regs[r1]); + T2 =3D tci_uint64(regs[r4], regs[r3]); + regs[r0] =3D tci_compare64(T1, T2, condition); break; #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613595288; cv=none; d=zohomail.com; s=zohoarc; b=IGI4y+M3NfLhVcVeU6uvmc6drinhsZi8xd2uk6o/krOr8DAUvxjWJEi34tXOq7tOKd9xbugmriXDY4NvEL/zBhBSjyKy9fSep98xXofBr8tZb0X/qIPug7vOhfDd3G9ekc8v1mC7WbM+SyG5r8BZG1hjAHbuphUT9dHgN9J+c78= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613595288; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V1TX4A2lg1baFpq2pztWBLMIOT18SzH84zy/1htPZ+g=; b=fjfRHSqoT3KcXMgVp1TnBQDl0srvYfG6KB7FJTr8vQJVkWKYJYkTZ3S8ENBs7IwfgB YbmJGzNRaEj0polNcXuMZU/p83GnzKKlN8EBPE5h+LwU6wpAz7nnBaxxNBGHOlxAeA3p xgoZ93su8jEkbBSpc365wnPpCwuPchTyPOYUsLtvZoWXkhs7fXiTBXlVzRHxz27wiMOB 2YzcoFaWOSsNSwrIQkfpvMAnJjzbUd05ClGNhd/Jsazmc2mX+/bmfSyfzupoUMNNdLnm I5XIsUxolqUM7LXsRuZ3QYteQpma17nUieSATprLKBgURqdCiLrxFGwC6uFlkTbS1kMr mUOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V1TX4A2lg1baFpq2pztWBLMIOT18SzH84zy/1htPZ+g=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 52 ++++++++++++++++++++++++++++++++-------------------- 1 file changed, 32 insertions(+), 20 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 558d03fd1b..c8df45ce28 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -212,6 +212,15 @@ static void tci_args_rrs(const uint8_t **tb_ptr, *i2 =3D tci_read_s32(tb_ptr); } =20 +static void tci_args_rrcl(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *c2 =3D tci_read_b(tb_ptr); + *l3 =3D (void *)tci_read_label(tb_ptr); +} + static void tci_args_rrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { @@ -222,6 +231,17 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 +static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); + *c4 =3D tci_read_b(tb_ptr); + *l5 =3D (void *)tci_read_label(tb_ptr); +} + static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) { @@ -388,7 +408,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tcg_target_ulong t0; tcg_target_ulong t1; tcg_target_ulong t2; - tcg_target_ulong label; TCGCond condition; target_ulong taddr; uint8_t tmp8; @@ -397,7 +416,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 TCGReg r3, r4; - uint64_t v64, T1, T2; + uint64_t T1, T2; #endif TCGMemOpIdx oi; int32_t ofs; @@ -594,13 +613,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; #endif case INDEX_op_brcond_i32: - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - condition =3D *tb_ptr++; - label =3D tci_read_label(&tb_ptr); - if (tci_compare32(t0, t1, condition)) { + tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); + if (tci_compare32(regs[r0], regs[r1], condition)) { tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr =3D (uint8_t *)label; + tb_ptr =3D ptr; continue; } break; @@ -620,13 +636,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tci_write_reg64(regs, t1, t0, tmp64); break; case INDEX_op_brcond2_i32: - tmp64 =3D tci_read_r64(regs, &tb_ptr); - v64 =3D tci_read_r64(regs, &tb_ptr); - condition =3D *tb_ptr++; - label =3D tci_read_label(&tb_ptr); - if (tci_compare64(tmp64, v64, condition)) { + tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr); + T1 =3D tci_uint64(regs[r1], regs[r0]); + T2 =3D tci_uint64(regs[r3], regs[r2]); + if (tci_compare64(T1, T2, condition)) { tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr =3D (uint8_t *)label; + tb_ptr =3D ptr; continue; } break; @@ -766,13 +781,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; #endif case INDEX_op_brcond_i64: - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - condition =3D *tb_ptr++; - label =3D tci_read_label(&tb_ptr); - if (tci_compare64(t0, t1, condition)) { + tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); + if (tci_compare64(regs[r0], regs[r1], condition)) { tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr =3D (uint8_t *)label; + tb_ptr =3D ptr; continue; } break; --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613594424; cv=none; d=zohomail.com; s=zohoarc; b=bihRoFpITQwwaMeKWGWPlH2bID2PB7G6Nr1WZTyWzTsC7zsxR20FW2ow2SGqmiMqf3/zeEd90mQFk+XK1YW49L0SmIBeGJMw6qmPHyY3B0X2q1rsQsW/T9Lqyb2H4dU/6DaxY7A16jD4+4qT9kpVRGr9Y4pghlI0fTgixxgOUGM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613594424; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=R2pchzDBkrNufC2Bz/6i9wxXtvGi5yfeV/PYKcIix9Y=; b=CGS8iqFPMudfUOvgHmivLsyGhaj8UM3V1sAHtGr05iJg3cPCRutUbVpg+ROxoJUnjoHNYVW5cY8F5qu1Ax+gHTZAcJU/XY1kH2AufRc5bvw9jgwbHUZ4XvLBc+nF0Uj9oV1NIjf0tHpUASSi0VLt1pjAF1NAQM0RzEzFm0sJGVY= ARC-Authentication-Results: i=1; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R2pchzDBkrNufC2Bz/6i9wxXtvGi5yfeV/PYKcIix9Y=; b=cHVkgJi7HJHMLSwOoO2W+4kHwo0GwDFA14C1bo4zUsihRCbjquoQaRF+9pc4U9Kx9d kTEZDEzw5J8LQXIYL5Mv2gIvn0yumTwCU4gslHr7XsY2vRX8qUaroJZD/U7h5OgnjmOC Wxi5p38UQGna3VSic4QCPY1rYrMi6Af2gXEhHk1r5bc76N7klP+tG1XIFZDGMy9A6n9c pfwCWDxNETvo2SxCY1hz+pnwRrjVT1gvoTtPhlmtrSoxQclAjrzNv4n8mmh2nbcYTume ehguw6jLtGMdZpBY4UiHyx6O4NUptskDm8dLL+t/Ut0+RFfc+jNZzBomrJldXMY5AZVT 8BGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R2pchzDBkrNufC2Bz/6i9wxXtvGi5yfeV/PYKcIix9Y=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index c8df45ce28..cfbe039fa6 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -121,16 +121,6 @@ static int32_t tci_read_s32(const uint8_t **tb_ptr) return value; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -/* Read constant (64 bit) from bytecode. */ -static uint64_t tci_read_i64(const uint8_t **tb_ptr) -{ - uint64_t value =3D *(const uint64_t *)(*tb_ptr); - *tb_ptr +=3D sizeof(value); - return value; -} -#endif - /* Read indexed register (native size) from bytecode. */ static tcg_target_ulong tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -180,6 +170,8 @@ static tcg_target_ulong tci_read_label(const uint8_t **= tb_ptr) * tci_args_ * where arguments is a sequence of * + * i =3D immediate (uint32_t) + * I =3D immediate (tcg_target_ulong) * r =3D register * s =3D signed ldst offset */ @@ -196,6 +188,22 @@ static void tci_args_rr(const uint8_t **tb_ptr, *r1 =3D tci_read_r(tb_ptr); } =20 +static void tci_args_ri(const uint8_t **tb_ptr, + TCGReg *r0, tcg_target_ulong *i1) +{ + *r0 =3D tci_read_r(tb_ptr); + *i1 =3D tci_read_i32(tb_ptr); +} + +#if TCG_TARGET_REG_BITS =3D=3D 64 +static void tci_args_rI(const uint8_t **tb_ptr, + TCGReg *r0, tcg_target_ulong *i1) +{ + *r0 =3D tci_read_r(tb_ptr); + *i1 =3D tci_read_i(tb_ptr); +} +#endif + static void tci_args_rrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2) { @@ -481,9 +489,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, regs[r0] =3D regs[r1]; break; case INDEX_op_tci_movi_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_i32(&tb_ptr); - tci_write_reg(regs, t0, t1); + tci_args_ri(&tb_ptr, &r0, &t1); + regs[r0] =3D t1; break; =20 /* Load/store operations (32 bit). */ @@ -703,9 +710,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif #if TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_tci_movi_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_i64(&tb_ptr); - tci_write_reg(regs, t0, t1); + tci_args_rI(&tb_ptr, &r0, &t1); + regs[r0] =3D t1; break; =20 /* Load/store operations (64 bit). */ --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9Vh7s6UroDOBSVmOQabkt7Snkgw14XUdmLA5IgFSZHM=; b=jXwm0HpXebmm980AAmIIi1WZXgXBDxKnwoPo9ayhrYZE4EiJxtl49Uft1pRryxIBL2 7L3OZIXs93o5WD1kKdk8QmOdxAQMy6pnYoIq8GMoA3CcA71OpDwdeqffSrbwD+2idXnA dVwoHGSqK49kCEUjO6nWMT9sMgaxVcg9cOx5bNh2OA8ikYecRJgMXCT/cQs+twKvFBgu UL22WViRe7VZ5ZAD6uZvSk3tqpJXsVckEsn47aQZ+LJ1/fB49aktmtOrO9d+lrY2RiFx y7nrGBcEdFMCO0vxCunKLWMa3DyoUfCDrsN6F9b/i+0okmYNV2j0xYSrg1Z60zRlelQz kgJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9Vh7s6UroDOBSVmOQabkt7Snkgw14XUdmLA5IgFSZHM=; b=ey9FmQxyYsfGHV8EpwkStdG/kftYF25PdBWD+9HmdQREDmpLjKOdKlK/pLF3bu9yUp 5vftXe0MGKLFTbw2copyliEJkidLoh1wWdditX47Ojf2HPRiKNZRL4Q/LGWae0RdjEzb j+tl6ltjVX+FNjkPBIXXYmqHsmVNlk2gp2nQ7VD3Y6Ejzd9MVtXadfZS2pZtr1R6NkW2 hupVr01gGFOnhiPGAtHgq9zrxupR97x17MNopPDiTVBHEaWPirTk6xhsSaeKpQy69DI/ YOYnJHItwGSbKJzoo+Ex2PgojF2mAW18D3Qpe5XOkyYS48KXP02R9dniUasCa+2N2Zjn 3uPw== X-Gm-Message-State: AOAM532zDoZ9eUW3KbEHAvS+7QoVF8rh9apLJRTFyTUXGFBWIBkIUuV6 WoJvTgxCTbRarTIKB1CY8/tOFJEAPQOBrQ== X-Google-Smtp-Source: ABdhPJz5xCmqEb5Gz4nBa49Ih3lg/RquOUhmaaEv4zxm8Tb8JgKRRDvUtuCQE3n8wJFogwiXPbiQjA== X-Received: by 2002:a65:5a09:: with SMTP id y9mr915946pgs.243.1613593368638; Wed, 17 Feb 2021 12:22:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 26/71] tcg/tci: Reuse tci_args_l for calls. Date: Wed, 17 Feb 2021 12:19:51 -0800 Message-Id: <20210217202036.1724901-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index cfbe039fa6..066e27b492 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -435,30 +435,30 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 switch (opc) { case INDEX_op_call: - t0 =3D tci_read_i(&tb_ptr); + tci_args_l(&tb_ptr, &ptr); tci_tb_ptr =3D (uintptr_t)tb_ptr; #if TCG_TARGET_REG_BITS =3D=3D 32 - tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5), - tci_read_reg(regs, TCG_REG_R6), - tci_read_reg(regs, TCG_REG_R7), - tci_read_reg(regs, TCG_REG_R8), - tci_read_reg(regs, TCG_REG_R9), - tci_read_reg(regs, TCG_REG_R10), - tci_read_reg(regs, TCG_REG_R11)); + tmp64 =3D ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0= ), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R4), + tci_read_reg(regs, TCG_REG_R5), + tci_read_reg(regs, TCG_REG_R6), + tci_read_reg(regs, TCG_REG_R7), + tci_read_reg(regs, TCG_REG_R8), + tci_read_reg(regs, TCG_REG_R9), + tci_read_reg(regs, TCG_REG_R10), + tci_read_reg(regs, TCG_REG_R11)= ); tci_write_reg(regs, TCG_REG_R0, tmp64); tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); #else - tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5)); + tmp64 =3D ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0= ), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R4), + tci_read_reg(regs, TCG_REG_R5)); tci_write_reg(regs, TCG_REG_R0, tmp64); #endif break; --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613594620329150.33349147534125; Wed, 17 Feb 2021 12:43:40 -0800 (PST) Received: from localhost ([::1]:42132 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTff-00040C-7O for importer@patchew.org; Wed, 17 Feb 2021 15:43:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32974) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTLa-0008AK-Fe for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:54 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:39836) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTLX-0007Lt-N8 for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:54 -0500 Received: by mail-pl1-x62b.google.com with SMTP id k22so8037388pll.6 for ; Wed, 17 Feb 2021 12:22:51 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Cx+nFCxFv3Yh5ev57gtG/OnK3pXMi4fhwChTqjnm+qQ=; b=D7nLrH2fAEU/I1rluHhYO3MD7CIEtgOY2IB9/dUG8uIwRytDwHw8naY+5qrzNhrSQT MEEZ1oJAqfrQGyEYi5Luaj5ug0zE6tjTWOSQUL+Elw9dm9SGiBRtbFsA9JMZYtn91cXo XIauc362IvpAfu/Hf61V6Cmuvr1IRULvk7KvJ8vMGHPHRaJYQ/3PL0Bix1Ey/XN3uweE 4/G1mEHEpa5LGWhFMxbIA5owppiAMKbAcGx3mvxIzY155T4VK1pd3SmH17gMJ/clFCUb 6XBQH5L5aNN4pUhQSXLwL39nkppHyozvO9Mqg1LRLcUphEfUFDPpP7X73K7OMHPgzM+3 3wWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Cx+nFCxFv3Yh5ev57gtG/OnK3pXMi4fhwChTqjnm+qQ=; b=Ql0up6E6675g6zYKD+Y6aZED4/cjo4/TAAtOAllnpAMTdRZrnJKJBxJEAqBmG9viK1 zDLS6SnOnlMU4hCx5BgOQ2Ig7tyHFZnNT5zdMtqmtvEh2KpHA+t0o5pZfzK0pd/0PqnZ h3ipQ8GyA9vC0qHJ4jja9Y1bXSFDdCw6+H1XUE7RzlcU4I9dj9azcDoVfsB47XAMMxq8 sFLRDVxgH+q438gC/cqzLeXWBLrQBsQ6aYMU4o4EEqZKogMnvL3iojE8nvXPx4eJ8ZE4 UTIFYqjmEz/2CfTuC7Pxvk0kjpeL/tryOYJjCNusIjhFlgx7eZljdUo9B/MsO6xOgxag wCpw== X-Gm-Message-State: AOAM533Ng3RcvL57Ih9jCTAJtFYocW3Nvmp3IyIUk3cXLy71akAqvZc1 I5hsaeBwmCzFUzqk6+JR/B6IB86pWVlD3Q== X-Google-Smtp-Source: ABdhPJzExw6y4IaxErHS6b1VhIFGPVbMugMrPsEMFE04XC2gtGYbiTQB68drwWk2BFyl4K+zyOegPQ== X-Received: by 2002:a17:90b:33ca:: with SMTP id lk10mr542705pjb.186.1613593370208; Wed, 17 Feb 2021 12:22:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 27/71] tcg/tci: Reuse tci_args_l for exit_tb Date: Wed, 17 Feb 2021 12:19:52 -0800 Message-Id: <20210217202036.1724901-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Do not emit a uint64_t, but a tcg_target_ulong, aka uintptr_t. This reduces the size of the constant on 32-bit hosts. The assert for label !=3D NULL has to be removed because that is a valid value for exit_tb. Signed-off-by: Richard Henderson --- tcg/tci.c | 13 ++++--------- tcg/tci/tcg-target.c.inc | 2 +- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 066e27b492..6fbbc48ecf 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -160,9 +160,7 @@ tci_read_ulong(const tcg_target_ulong *regs, const uint= 8_t **tb_ptr) =20 static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) { - tcg_target_ulong label =3D tci_read_i(tb_ptr); - tci_assert(label !=3D 0); - return label; + return tci_read_i(tb_ptr); } =20 /* @@ -400,7 +398,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tcg_target_ulong regs[TCG_TARGET_NB_REGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS]; uintptr_t sp_value =3D (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); - uintptr_t ret =3D 0; =20 regs[TCG_AREG0] =3D (tcg_target_ulong)env; regs[TCG_REG_CALL_STACK] =3D sp_value; @@ -815,9 +812,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, /* QEMU specific operations. */ =20 case INDEX_op_exit_tb: - ret =3D *(uint64_t *)tb_ptr; - goto exit; - break; + tci_args_l(&tb_ptr, &ptr); + return (uintptr_t)ptr; + case INDEX_op_goto_tb: /* Jump address is aligned */ tb_ptr =3D QEMU_ALIGN_PTR_UP(tb_ptr, 4); @@ -975,6 +972,4 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, } tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); } -exit: - return ret; } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c79f9c32d8..ff8040510f 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -401,7 +401,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, =20 switch (opc) { case INDEX_op_exit_tb: - tcg_out64(s, args[0]); + tcg_out_i(s, args[0]); break; =20 case INDEX_op_goto_tb: --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161359508369311.681795547096272; Wed, 17 Feb 2021 12:51:23 -0800 (PST) Received: from localhost ([::1]:59350 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTn8-0002q2-M0 for importer@patchew.org; Wed, 17 Feb 2021 15:51:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32984) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTLb-0008CZ-FI for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:55 -0500 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:41797) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTLY-0007M4-SZ for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:55 -0500 Received: by mail-pg1-x533.google.com with SMTP id t11so9206103pgu.8 for ; Wed, 17 Feb 2021 12:22:52 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tDBHUplRWlhhF0tIGzcFewPFwl6oh2HCB/aPTX+DVBc=; b=w4mhJFizPV4fSDWVyq/Ql72ricgdjnOie+ZV85pOM8qj0PlLygxmBQUOTQA0RbyzLd Vibaa/cy6V6qViM4Y1/OR0fygNTUzsGJCNQwx0qED6dP/Ep5EIKbAfnMpQVj3lBiTDG3 dQDiPGecm60vWFgo+Pu8Id5F7ctnD4PvLgUO4Frid389V7j4F1UQvlntQNxbTPr/7D1F Pbw6GEYu2fXFw+rPCt18JztCmtyW69h2kQu/kiLTIqEJr5DfmkmGLBJLxLfGMptjisT2 +i029mgQJevAAHI/66XBTy79q/zHOdjb3DyOYi55OF6C1uI391CvVdYMpuuZRDF76w7G IVNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tDBHUplRWlhhF0tIGzcFewPFwl6oh2HCB/aPTX+DVBc=; b=jcKzPvFg/+v7v1rKooZLlzIRoIKXUVssRcJDQV977FHYdKFRJDpqqpIjFCz3QmNb9K r9LS6ThaQmjQYfjYpUHPhWqotMZ9F9eakpEdtns6TzV20Qxx8jQeLpDj/42wC6mbB0By NC3rBXevmrlCiPalC2GFrHCKq7YcmwuEioFrqOYZEVkQ62pRrx580eUl39WKqQnklwi4 ze9Ecj1wKX/ZcGsi5r6ak59yXM8tRZYKzMCC8897JZOGwJMSqA7EZaboznrlcpypGWlJ GON9B/v2Ss6cgZ3OJ/Xs6KWkm59rYbGvb6POFo6cwegV5AohqdYslTW5PGttgykCIHk4 vIVw== X-Gm-Message-State: AOAM530PHg841snTSwh/+Prga8CYTC+d5AdZ5Zj3S8/WAsTDOo0eZPFK rArD2u07iHsIbYI1ULsFhF+E6ntQJdkEWg== X-Google-Smtp-Source: ABdhPJwxCFtJSSkRqyYY4S9CKdUsNbyd0byMAgo/+z6c1rnXxPXAZg7nPMV9ZTVJrwr4R9yw/S76xw== X-Received: by 2002:a63:580d:: with SMTP id m13mr952598pgb.342.1613593371653; Wed, 17 Feb 2021 12:22:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 28/71] tcg/tci: Reuse tci_args_l for goto_tb Date: Wed, 17 Feb 2021 12:19:53 -0800 Message-Id: <20210217202036.1724901-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert to indirect jumps, as it's less complicated. Then we just have a pointer to the tb address at which the chain is stored, from which we read. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 11 +++-------- tcg/tci.c | 8 +++----- tcg/tci/tcg-target.c.inc | 13 +++---------- 3 files changed, 9 insertions(+), 23 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 9c0021a26f..9285c930a2 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -87,7 +87,7 @@ #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 0 -#define TCG_TARGET_HAS_direct_jump 1 +#define TCG_TARGET_HAS_direct_jump 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -174,12 +174,7 @@ void tci_disas(uint8_t opc); =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 -static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jm= p_rx, - uintptr_t jmp_rw, uintptr_t ad= dr) -{ - /* patch the branch destination */ - qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4)); - /* no need to flush icache explicitly */ -} +/* not defined -- call should be eliminated at compile time */ +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 #endif /* TCG_TARGET_H */ diff --git a/tcg/tci.c b/tcg/tci.c index 6fbbc48ecf..3fe0831b33 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -816,13 +816,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, return (uintptr_t)ptr; =20 case INDEX_op_goto_tb: - /* Jump address is aligned */ - tb_ptr =3D QEMU_ALIGN_PTR_UP(tb_ptr, 4); - t0 =3D qatomic_read((int32_t *)tb_ptr); - tb_ptr +=3D sizeof(int32_t); + tci_args_l(&tb_ptr, &ptr); tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr +=3D (int32_t)t0; + tb_ptr =3D *(void **)ptr; continue; + case INDEX_op_qemu_ld_i32: t0 =3D *tb_ptr++; taddr =3D tci_read_ulong(regs, &tb_ptr); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index ff8040510f..2c64b4f617 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -405,16 +405,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, break; =20 case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset) { - /* Direct jump method. */ - /* Align for atomic patching and thread safety */ - s->code_ptr =3D QEMU_ALIGN_PTR_UP(s->code_ptr, 4); - s->tb_jmp_insn_offset[args[0]] =3D tcg_current_code_size(s); - tcg_out32(s, 0); - } else { - /* Indirect jump method. */ - TODO(); - } + tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); + /* indirect jump method. */ + tcg_out_i(s, (uintptr_t)(s->tb_jmp_target_addr + args[0])); set_jmp_reset_offset(s, args[0]); break; =20 --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613595494; cv=none; d=zohomail.com; s=zohoarc; b=Iwv/uNnW4qsVYtICb7+jl8C10GlxTNm84J55ohEqayqytSCyJ269DfG8Je1VzJtRBc8gx5M/g/ZJDpME8Atyd0DwVQNlHult1ev7b14PbelpmivOoIvqae0W6yB6GlBFcoWLgtXstXRrxfKNpJ2blhF5D1tqPJsK2vHC4Y+GSWA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613595494; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=E7uiPbIkaltXGyGrTOejJhAFYjDYkkPY5RpXmb9ap/U=; b=Cy2OGBF/c1hBXN82jOS0iMRfh5oy2QN2zzAC5txzwGHC4K+7bMMr7K0lW7B11Hot0Z2jMW/KYu+ruyIXI6mdaW6VfPYN2myFPKyAi5hZvpXpwoY4ABl3P3K+c0vSzkdRhnpWQAu2wl6aW7HTPnS/fbffHmuEzc3EGbXpQZQkhfE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613595493646159.68727995710628; Wed, 17 Feb 2021 12:58:13 -0800 (PST) Received: from localhost ([::1]:48844 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTtk-0001hk-IG for importer@patchew.org; Wed, 17 Feb 2021 15:58:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32986) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTLb-0008Cr-K5 for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:55 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:46681) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTLa-0007MF-7C for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:22:55 -0500 Received: by mail-pl1-x631.google.com with SMTP id u11so8013615plg.13 for ; Wed, 17 Feb 2021 12:22:53 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E7uiPbIkaltXGyGrTOejJhAFYjDYkkPY5RpXmb9ap/U=; b=FNVb6l0ZZN/yAsRyue5pG1InpKjE5TRb2FP5CnT8wuVA+FAdDwwhmXySt4ngzPwVk9 W4zAbJXCgBk/t2wLB9L2NZd2KEYZXyv5hJHxl7qOPcEExwdib6o/bcoMC2SBi+d38sIa R4bP7u0eYUVzec3hCckoYyYrU0DwWnEscyQbjNMxgsdAG0KEgtKQFqxMgr4FBxyCRJTW iYJDprKjEeNXbC6B8u/CU3aE2blc3eVaciedX2b5ZHZmw2wnrrKd44p4/mEYzfVlCup8 2CzXlNpjdW3MFByJBsM/qgewR4dMJn1Id8UDInCOOnWbaSIMKEbdd74uMYsWLD4PKRAK fadQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E7uiPbIkaltXGyGrTOejJhAFYjDYkkPY5RpXmb9ap/U=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 3fe0831b33..8b38687d9a 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -258,6 +258,17 @@ static void tci_args_rrrrrc(const uint8_t **tb_ptr, TC= GReg *r0, TCGReg *r1, *r4 =3D tci_read_r(tb_ptr); *c5 =3D tci_read_b(tb_ptr); } + +static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); + *r4 =3D tci_read_r(tb_ptr); + *r5 =3D tci_read_r(tb_ptr); +} #endif =20 static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) @@ -420,7 +431,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r3, r4; + TCGReg r3, r4, r5; uint64_t T1, T2; #endif TCGMemOpIdx oi; @@ -626,18 +637,16 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: - t0 =3D *tb_ptr++; - t1 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(regs, &tb_ptr); - tmp64 +=3D tci_read_r64(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, tmp64); + tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + T1 =3D tci_uint64(regs[r3], regs[r2]); + T2 =3D tci_uint64(regs[r5], regs[r4]); + tci_write_reg64(regs, r1, r0, T1 + T2); break; case INDEX_op_sub2_i32: - t0 =3D *tb_ptr++; - t1 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(regs, &tb_ptr); - tmp64 -=3D tci_read_r64(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, tmp64); + tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + T1 =3D tci_uint64(regs[r3], regs[r2]); + T2 =3D tci_uint64(regs[r5], regs[r4]); + tci_write_reg64(regs, r1, r0, T1 - T2); break; case INDEX_op_brcond2_i32: tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr); --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613594562170356.0057438647134; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 8b38687d9a..10f58e4f25 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -237,6 +237,15 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 +static void tci_args_rrrr(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); +} + static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) { @@ -659,11 +668,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, } break; case INDEX_op_mulu2_i32: - t0 =3D *tb_ptr++; - t1 =3D *tb_ptr++; - t2 =3D tci_read_rval(regs, &tb_ptr); - tmp64 =3D (uint32_t)tci_read_rval(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); + tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e1N26oOEBH/mKZCKJR62A/M2uXOOm6+5WQ72+nFodnM=; b=J7Af9yOH18dARi2PcdpBtXXYHttHlEam0mx213NtewSO5V6NGeJYi/Hf9wimR8tJ+8 vqwu9+ujj6Ii0/zJ8QGXOcs6xpnaO7C6/JtQ4EEQEWa84VCCn36rIZUbrcmleWMPTNa0 WbKDx0DFD9ytVc93EPvd9H9jBQ9CqZCCj+zkTLBodwlcGh0f8g+MCmlCvHPmyIytC5t2 PWUBVXU02fjr5WWuwk07YoJbBE7Kz1fjujx1grEQf5O95jNOKBijHAusIG2AHeWUJeRs DwztLRqo+9vCTGINpESlLtJmXkFQ6iyiBbYTaFrFz0cbRQYjn00KwRiRMtJOYt1akAl5 HeYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e1N26oOEBH/mKZCKJR62A/M2uXOOm6+5WQ72+nFodnM=; b=tP+vVrSOFf743Rq+hVO83vTZlQdJtot0Dz/cmDvZGdcX2EhZnL5tMuI4Oc0JF2zsfN 2D7WXscdTy0hdFGR2+qAknW4PU2es+JD8LM8FgDGQHjRHBrvz6z37Zq9wZKiifkckBNW ZdIdIlrWkAIEciwJX3B0PyMG37gJa4n8EWpVwGF7k4CeAx//M+ZGfsCxk+2sLJibnnwk wVQuSfo7GD2cfetQzrPG/TKmubx/D7SyUjHrWs42o9x1r1XYQBdfGuiuQoMyIxiKW/TG Wo3ccj4TQI+FpnJkL+wsg56WqngJYvJKxXPsLhVgaAUdFJecYfYgqglrJplogQfG4XIu EVTA== X-Gm-Message-State: AOAM5333ZGPjcprj61e586oB0V8sQ2Jj16mbAy6UN37T2jmZMQjeBsap Nu1lGw425j2zh181Y+kKVeIGQ+qQefgLJQ== X-Google-Smtp-Source: ABdhPJxBh1QANrGY1LRuXQnGPOIpv/rpNNUy4/jrnlygjCw0q6akZL7KGGqQueLtDPNc1/H/CsuviQ== X-Received: by 2002:a17:903:18c:b029:e1:f4f0:dc26 with SMTP id z12-20020a170903018cb02900e1f4f0dc26mr768272plg.22.1613593376863; Wed, 17 Feb 2021 12:22:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 31/71] tcg/tci: Clean up deposit operations Date: Wed, 17 Feb 2021 12:19:56 -0800 Message-Id: <20210217202036.1724901-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Use the correct set of asserts during code generation. We do not require the first input to overlap the output; the existing interpreter already supported that. Split out tci_args_rrrbb in the translator. Use the deposit32/64 functions rather than inline expansion. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-con-set.h | 1 - tcg/tci.c | 33 ++++++++++++++++----------------- tcg/tci/tcg-target.c.inc | 24 ++++++++++++++---------- 3 files changed, 30 insertions(+), 28 deletions(-) diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h index f51b7bcb13..316730f32c 100644 --- a/tcg/tci/tcg-target-con-set.h +++ b/tcg/tci/tcg-target-con-set.h @@ -13,7 +13,6 @@ C_O0_I2(r, r) C_O0_I3(r, r, r) C_O0_I4(r, r, r, r) C_O1_I1(r, r) -C_O1_I2(r, 0, r) C_O1_I2(r, r, r) C_O1_I4(r, r, r, r, r) C_O2_I1(r, r, r) diff --git a/tcg/tci.c b/tcg/tci.c index 10f58e4f25..3ce2b72316 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -168,6 +168,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **= tb_ptr) * tci_args_ * where arguments is a sequence of * + * b =3D immediate (bit position) * i =3D immediate (uint32_t) * I =3D immediate (tcg_target_ulong) * r =3D register @@ -236,6 +237,16 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, *c3 =3D tci_read_b(tb_ptr); } =20 +static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, uint8_t *i3, uint8_t *i4) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *i3 =3D tci_read_b(tb_ptr); + *i4 =3D tci_read_b(tb_ptr); +} + #if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) @@ -432,11 +443,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, TCGReg r0, r1, r2; tcg_target_ulong t0; tcg_target_ulong t1; - tcg_target_ulong t2; TCGCond condition; target_ulong taddr; - uint8_t tmp8; - uint16_t tmp16; + uint8_t pos, len; uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 @@ -627,13 +636,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tmp16 =3D *tb_ptr++; - tmp8 =3D *tb_ptr++; - tmp32 =3D (((1 << tmp8) - 1) << tmp16); - tci_write_reg(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32= )); + tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + regs[r0] =3D deposit32(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i32: @@ -789,13 +793,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tmp16 =3D *tb_ptr++; - tmp8 =3D *tb_ptr++; - tmp64 =3D (((1ULL << tmp8) - 1) << tmp16); - tci_write_reg(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64= )); + tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + regs[r0] =3D deposit64(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i64: diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 2c64b4f617..640407b4a8 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -126,11 +126,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpco= de op) case INDEX_op_rotr_i64: case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - return C_O1_I2(r, r, r); - case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return C_O1_I2(r, 0, r); + return C_O1_I2(r, r, r); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: @@ -480,13 +478,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, break; =20 CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_debug_assert(args[3] <=3D UINT8_MAX); - tcg_out8(s, args[3]); - tcg_debug_assert(args[4] <=3D UINT8_MAX); - tcg_out8(s, args[4]); + { + TCGArg pos =3D args[3], len =3D args[4]; + TCGArg max =3D opc =3D=3D INDEX_op_deposit_i32 ? 32 : 64; + + tcg_debug_assert(pos < max); + tcg_debug_assert(pos + len <=3D max); + + tcg_out_r(s, args[0]); + tcg_out_r(s, args[1]); + tcg_out_r(s, args[2]); + tcg_out8(s, pos); + tcg_out8(s, len); + } break; =20 CASE_32_64(brcond) --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613595731; cv=none; d=zohomail.com; s=zohoarc; b=W57My1VxGbvE1ZX7QchYEQSqISsRvI7fGE3ZdTK77aODeF7IgB8/BvQ4C+x4ycztTKjdaglMydLWDLyxDiBMC9i++A5sb8Yl4D9c+CCSMadTUUBcEH98lfzwno5sZBVpJ7BCDLpKqe7un19rnAItJIa48y9otw6wSFY3b7pyG28= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613595731; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NtYy7CVHSUTsrLhd0g6enXEgT6j0TcJMSjVB1gNIEaI=; b=G4Vf7QDmz858KH9uOXL/GJ5OCRhRb1fyo49cxpJIiJlqdIII7YnJTTGkAz/yyNTkovl0KPSTxC1g6wk+EeLsfSVNSwoV4WluISB43iZ/nDAa8teqQ0dsPON1qxKEIEQJpr18xsoqDSU5CCcp+c568+5ivPyTuk8GsZLTqumaA2Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613595730598869.9366979500797; Wed, 17 Feb 2021 13:02:10 -0800 (PST) Received: from localhost ([::1]:56906 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTxZ-00055c-Cv for importer@patchew.org; Wed, 17 Feb 2021 16:02:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33028) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTLh-0008Il-5D for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:23:01 -0500 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:38267) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTLf-0007Np-LP for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:23:00 -0500 Received: by mail-pf1-x432.google.com with SMTP id y25so5879415pfp.5 for ; Wed, 17 Feb 2021 12:22:59 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NtYy7CVHSUTsrLhd0g6enXEgT6j0TcJMSjVB1gNIEaI=; b=gR7aFSjHpQmAgj2FZQrKghYvA5B5AYdngNW8sro1XAHNpuTqSGxQ5AxWlGBAm16ctT 6nT8h4xD9xiPSls1nTqbOkqn4gSUNYZdxubgj+MPzOVJY35yTzq3UtZ3RkUOIQdUuDeO c+KkMwxmxgWYJkO1m91lkcnH1urflFdlqW7ymsTR8LSvs3R8LSf93t8wCBxoNKKGDsD5 Qr/1D1MgP8oXI7zx41cvHOhRQJT2KppnJ+XFazZ3iZYdM33gjEnf07Cygeou5Rxo1xBu Qe3gCHXnhZtEbnbHtmzx4kOja8xrty/Qn6NdyBlx4wtDA4+8PGBglQfsTM9ebX6n/4jT BOaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NtYy7CVHSUTsrLhd0g6enXEgT6j0TcJMSjVB1gNIEaI=; b=F1FAVvtY1UkDnvN6UQV2hI/0UBhUrQJxagQXe8IhhSmsHCV/paAkkBWir95mYA6G9h to/scQWd7cByEXH3rTJVIdA0f7JS5qowX3VPVm524bnxaWwL6QmZgt5Xy64F7YKV8Eq8 kQ0U5iPtW36XEu3LdUFXMt49XOQxTTRruAgtZiZ4xHp373hO0dpoAX0QYJ6067bFnvzY pdiKqRu9/yi/rgIbpgcNdHDp4VDHPk9qnHlE44+j0j5LDkS4uoYnTmivhNGT7dSTmRK5 qhLleBWoQ1v/WYAuTFwCZbdOhv3Cz+LP5MJUmeB7iHLlqZ9ucXXotysZ/XeL7vIIfq6t +JNg== X-Gm-Message-State: AOAM530mUUTyd3sNUiIq/VIPAxFmRcw7lVmO8J79j5FY40UpFHi0ov3Z XdDnCMNP8nV1L1O8HwrVE4wHZ9EcKpF1Sw== X-Google-Smtp-Source: ABdhPJzPDW2xUOsMYYBhKicHL3+O5O3ghnX2St8GAj8SovGAbhJ3yEYupsTUscgX+crAGWGGCrhL/g== X-Received: by 2002:a05:6a00:16c7:b029:1b6:68a6:985a with SMTP id l7-20020a056a0016c7b02901b668a6985amr967103pfc.44.1613593378447; Wed, 17 Feb 2021 12:22:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 32/71] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits Date: Wed, 17 Feb 2021 12:19:57 -0800 Message-Id: <20210217202036.1724901-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" We are currently using the "natural" size routine, which uses 64-bits on a 64-bit host. The TCGMemOpIdx operand has 11 bits, so we can safely reduce to 32-bits. Signed-off-by: Richard Henderson --- tcg/tci.c | 8 ++++---- tcg/tci/tcg-target.c.inc | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 3ce2b72316..583059f319 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -838,7 +838,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_qemu_ld_i32: t0 =3D *tb_ptr++; taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i(&tb_ptr); + oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp32 =3D qemu_ld_ub; @@ -875,7 +875,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t1 =3D *tb_ptr++; } taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i(&tb_ptr); + oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp64 =3D qemu_ld_ub; @@ -924,7 +924,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_qemu_st_i32: t0 =3D tci_read_rval(regs, &tb_ptr); taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i(&tb_ptr); + oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: qemu_st_b(t0); @@ -948,7 +948,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_qemu_st_i64: tmp64 =3D tci_read_r64(regs, &tb_ptr); taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i(&tb_ptr); + oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: qemu_st_b(tmp64); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 640407b4a8..6c187a25cc 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -550,7 +550,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { tcg_out_r(s, *args++); } - tcg_out_i(s, *args++); + tcg_out32(s, *args++); break; =20 case INDEX_op_qemu_ld_i64: @@ -563,7 +563,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { tcg_out_r(s, *args++); } - tcg_out_i(s, *args++); + tcg_out32(s, *args++); break; =20 case INDEX_op_mb: --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613595929; cv=none; d=zohomail.com; s=zohoarc; b=IB57Q/LjnnD+Yym4APW1T89QgdJ4RLVj6Bz5xdwhkpGldBu1aY9/wSfmHrQYZBqiM9imC6VQKfnp/mfYHk/QXhe/+QnXXbjzaWLL4XHr6JCtZD+kg1cvF/quiGj7lwyzBayEbD6QX22pLHA/glN3AiBOWtgc48E9qVpT4N2lnlE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613595929; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BGjOxn7oBYKM0brcxUQhOzUdPq+WpZr2L0yE6bqXqs8=; b=BwXem0tiS8owJRf9Uo6VQq14wRblcDzohsKUYSyuHb1yz8LSAfvnvGzKjuQh9zr+WtfeVjl3VwTCerleMbBwIgTw4ysPDzlCE1+YYGOHM1cTIvKq7tfsRxQJRu0XbSu+SfrB+0TjABVhx8x+RrqljDTMXDiwp8AqUlW5HDb6RxQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613595928897656.0608402641767; Wed, 17 Feb 2021 13:05:28 -0800 (PST) Received: from localhost ([::1]:37276 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCU0l-0000Xt-Mt for importer@patchew.org; Wed, 17 Feb 2021 16:05:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTLj-0008O6-89 for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:23:03 -0500 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]:43621) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTLh-0007O1-7r for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:23:03 -0500 Received: by mail-pg1-x52e.google.com with SMTP id n10so9193467pgl.10 for ; Wed, 17 Feb 2021 12:23:00 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BGjOxn7oBYKM0brcxUQhOzUdPq+WpZr2L0yE6bqXqs8=; b=DkwnQBxw6tYUOXWZT5dww3i2HNIg/74Scr7jmVd5IjDOnlD+an/6YggEazPlyOSc+v ZwAE6qXK0lSPZ/jBxyLTVzQi1rHa8UuqMcqY+GEfmxjfQcGC3/xtYR0htb7YrCP1YliK KxFju+A+RUXtqIuI9ofeFIS6/iX8Ygdp5FphVzZ63dozHkFO5SWnPSLBshpoARAG4SR+ LDO1ykz7rznVjdhYwcN0fGaDv68O7fWcHqPz6zIU80R1AuxJGSzNs3dwJtXs551dA7Ef FkFg9XtinDIf1bSHbH2fUcjYaWCP2gzX6GBjSTMgsdxz+OxCv3FU45Bbhtgw9hbcELaz jHrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BGjOxn7oBYKM0brcxUQhOzUdPq+WpZr2L0yE6bqXqs8=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 147 ++++++++++++++++++++++++++++++------------------------ 1 file changed, 81 insertions(+), 66 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 583059f319..f6cc5a3ab0 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -66,22 +66,18 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg= _target_ulong value) regs[index] =3D value; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, uint32_t low_index, uint64_t value) { tci_write_reg(regs, low_index, value); tci_write_reg(regs, high_index, value >> 32); } -#endif =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 /* Create a 64 bit value from two 32 bit values. */ static uint64_t tci_uint64(uint32_t high, uint32_t low) { return ((uint64_t)high << 32) + low; } -#endif =20 /* Read constant byte from bytecode. */ static uint8_t tci_read_b(const uint8_t **tb_ptr) @@ -121,43 +117,6 @@ static int32_t tci_read_s32(const uint8_t **tb_ptr) return value; } =20 -/* Read indexed register (native size) from bytecode. */ -static tcg_target_ulong -tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr) -{ - tcg_target_ulong value =3D tci_read_reg(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} - -#if TCG_TARGET_REG_BITS =3D=3D 32 -/* Read two indexed registers (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_r64(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - uint32_t low =3D tci_read_rval(regs, tb_ptr); - return tci_uint64(tci_read_rval(regs, tb_ptr), low); -} -#elif TCG_TARGET_REG_BITS =3D=3D 64 -/* Read indexed register (64 bit) from bytecode. */ -static uint64_t tci_read_r64(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - return tci_read_rval(regs, tb_ptr); -} -#endif - -/* Read indexed register(s) with target address from bytecode. */ -static target_ulong -tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr) -{ - target_ulong taddr =3D tci_read_rval(regs, tb_ptr); -#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - taddr +=3D (uint64_t)tci_read_rval(regs, tb_ptr) << 32; -#endif - return taddr; -} - static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) { return tci_read_i(tb_ptr); @@ -171,6 +130,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **= tb_ptr) * b =3D immediate (bit position) * i =3D immediate (uint32_t) * I =3D immediate (tcg_target_ulong) + * m =3D immediate (TCGMemOpIdx) * r =3D register * s =3D signed ldst offset */ @@ -203,6 +163,14 @@ static void tci_args_rI(const uint8_t **tb_ptr, } #endif =20 +static void tci_args_rrm(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *m2 =3D tci_read_i32(tb_ptr); +} + static void tci_args_rrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2) { @@ -237,6 +205,15 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, *c3 =3D tci_read_b(tb_ptr); } =20 +static void tci_args_rrrm(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx = *m3) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *m3 =3D tci_read_i32(tb_ptr); +} + static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, uint8_t *i3, uint8_t *i4) { @@ -247,6 +224,16 @@ static void tci_args_rrrbb(const uint8_t **tb_ptr, TCG= Reg *r0, TCGReg *r1, *i4 =3D tci_read_b(tb_ptr); } =20 +static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); + *m4 =3D tci_read_i32(tb_ptr); +} + #if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) @@ -440,8 +427,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint8_t op_size =3D tb_ptr[1]; const uint8_t *old_code_ptr =3D tb_ptr; #endif - TCGReg r0, r1, r2; - tcg_target_ulong t0; + TCGReg r0, r1, r2, r3; tcg_target_ulong t1; TCGCond condition; target_ulong taddr; @@ -449,7 +435,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r3, r4, r5; + TCGReg r4, r5; uint64_t T1, T2; #endif TCGMemOpIdx oi; @@ -836,9 +822,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, continue; =20 case INDEX_op_qemu_ld_i32: - t0 =3D *tb_ptr++; - taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i32(&tb_ptr); + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr =3D regs[r1]; + } else { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr =3D tci_uint64(regs[r2], regs[r1]); + } switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp32 =3D qemu_ld_ub; @@ -867,15 +857,20 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, default: g_assert_not_reached(); } - tci_write_reg(regs, t0, tmp32); + regs[r0] =3D tmp32; break; + case INDEX_op_qemu_ld_i64: - t0 =3D *tb_ptr++; - if (TCG_TARGET_REG_BITS =3D=3D 32) { - t1 =3D *tb_ptr++; + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr =3D regs[r1]; + } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr =3D regs[r2]; + } else { + tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + taddr =3D tci_uint64(regs[r3], regs[r2]); } - taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp64 =3D qemu_ld_ub; @@ -916,39 +911,58 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, default: g_assert_not_reached(); } - tci_write_reg(regs, t0, tmp64); if (TCG_TARGET_REG_BITS =3D=3D 32) { - tci_write_reg(regs, t1, tmp64 >> 32); + tci_write_reg64(regs, r1, r0, tmp64); + } else { + regs[r0] =3D tmp64; } break; + case INDEX_op_qemu_st_i32: - t0 =3D tci_read_rval(regs, &tb_ptr); - taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i32(&tb_ptr); + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr =3D regs[r1]; + } else { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr =3D tci_uint64(regs[r2], regs[r1]); + } + tmp32 =3D regs[r0]; switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: - qemu_st_b(t0); + qemu_st_b(tmp32); break; case MO_LEUW: - qemu_st_lew(t0); + qemu_st_lew(tmp32); break; case MO_LEUL: - qemu_st_lel(t0); + qemu_st_lel(tmp32); break; case MO_BEUW: - qemu_st_bew(t0); + qemu_st_bew(tmp32); break; case MO_BEUL: - qemu_st_bel(t0); + qemu_st_bel(tmp32); break; default: g_assert_not_reached(); } break; + case INDEX_op_qemu_st_i64: - tmp64 =3D tci_read_r64(regs, &tb_ptr); - taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i32(&tb_ptr); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr =3D regs[r1]; + tmp64 =3D regs[r0]; + } else { + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr =3D regs[r2]; + } else { + tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + taddr =3D tci_uint64(regs[r3], regs[r2]); + } + tmp64 =3D tci_uint64(regs[r1], regs[r0]); + } switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: qemu_st_b(tmp64); @@ -975,6 +989,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, g_assert_not_reached(); } break; + case INDEX_op_mb: /* Ensure ordering for all kinds */ smp_mb(); --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.23.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cto0meToeqhl4dng/D5GTO+M9plTBCVNCtbljoyaQQ8=; b=iaORFVKeEW06UCQwJ+CdPX/yHo1aRdZtjNBfH0rI6bU3UOIX/r2FHZdyKECFUQ6eI8 rE6rdi3Bwc+h+er9PwFuTbYQUv7mOYmBmRLsNjqTLPJtejHAAPaPlXFKuWddPKCGwiWW 9IiGnY74ECe/Q9aQQB+MFwK1AZl0Dn0oF3Tw4mi8EnV79WwZPcSn0m7qkA4cjaacZZv3 q+5p5P+5UEoN5FNm+cSEXtu45gLS39A+jurYuQqW4OwVTfB9sAl8S7aa9DCvF6ZPDNxB EsBjOXVkIZ8AaOV7TEKn12RdMNEQgimuAEzz9hhTMvPYiZtXZIZkqdJcY5SwrLAmpQe/ qNMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cto0meToeqhl4dng/D5GTO+M9plTBCVNCtbljoyaQQ8=; b=oD7Gk7p7jHkhTENOCg6UaM+x8iCXlGj13HZwR02Ko7/cwKmv6sIOcfx+pcv2VJ+55v hClHXF3KKfAd0HtXLEY9jWBvBpFtgIWQis5elblu0sGpdV4fJOXzox7l3I9bohGArzdf c4OUqyNaQaphTlFBk/ChNbzl0GWGI03rWYMr6AffvSkXaPEpCZo+yNJO1ynf5UtLnpTb MyrBr7y04Z9hiP3WsETwUYe1fcvIt2CPhur+UwqWi2cKdhBDmgdhU0sxXtSmOSO7YDn/ VA31rwCpWYHHsAGvR4IvvYdxsnE/dKJbmvsyLeRssKDsw7w6dzfesCicz1FTu+oGVj/q a8Dw== X-Gm-Message-State: AOAM5339zbY7rJRUqOlAhuaO9Gi+PcJMfMuUagktxuQT/T+6vKM0NxWl JeY3D+sfOqnjAM1GJSGoW8aUSfOM//x1IQ== X-Google-Smtp-Source: ABdhPJx9lJauDYJRI8UQIDHG1JHsU42z99vbEmrMP6XFG96ve2/oQKcGxTFj3R3EWBD2YFAQhRi4sg== X-Received: by 2002:a05:6a00:2ac:b029:1e9:3cb7:324a with SMTP id q12-20020a056a0002acb02901e93cb7324amr985906pfs.36.1613593381967; Wed, 17 Feb 2021 12:23:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 34/71] tcg/tci: Hoist op_size checking into tci_args_* Date: Wed, 17 Feb 2021 12:19:59 -0800 Message-Id: <20210217202036.1724901-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This performs the size check while reading the arguments, which means that we don't have to arrange for it to be done after the operation. Which tidies all of the branches. Signed-off-by: Richard Henderson --- tcg/tci.c | 87 ++++++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 73 insertions(+), 14 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index f6cc5a3ab0..6b63beea28 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -24,7 +24,7 @@ #if defined(CONFIG_DEBUG_TCG) # define tci_assert(cond) assert(cond) #else -# define tci_assert(cond) ((void)0) +# define tci_assert(cond) ((void)(cond)) #endif =20 #include "qemu-common.h" @@ -135,146 +135,217 @@ static tcg_target_ulong tci_read_label(const uint8_= t **tb_ptr) * s =3D signed ldst offset */ =20 +static void check_size(const uint8_t *start, const uint8_t **tb_ptr) +{ + const uint8_t *old_code_ptr =3D start - 2; + uint8_t op_size =3D old_code_ptr[1]; + tci_assert(*tb_ptr =3D=3D old_code_ptr + op_size); +} + static void tci_args_l(const uint8_t **tb_ptr, void **l0) { + const uint8_t *start =3D *tb_ptr; + *l0 =3D (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_ri(const uint8_t **tb_ptr, TCGReg *r0, tcg_target_ulong *i1) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *i1 =3D tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 static void tci_args_rI(const uint8_t **tb_ptr, TCGReg *r0, tcg_target_ulong *i1) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *i1 =3D tci_read_i(tb_ptr); + + check_size(start, tb_ptr); } #endif =20 static void tci_args_rrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *m2 =3D tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrs(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, int32_t *i2) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *i2 =3D tci_read_s32(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *c2 =3D tci_read_b(tb_ptr); *l3 =3D (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *c3 =3D tci_read_b(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx = *m3) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *m3 =3D tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, uint8_t *i3, uint8_t *i4) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *i3 =3D tci_read_b(tb_ptr); *i4 =3D tci_read_b(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); *m4 =3D tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); *c4 =3D tci_read_b(tb_ptr); *l5 =3D (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); *r4 =3D tci_read_r(tb_ptr); *c5 =3D tci_read_b(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); *r4 =3D tci_read_r(tb_ptr); *r5 =3D tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } #endif =20 @@ -423,10 +494,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, =20 for (;;) { TCGOpcode opc =3D tb_ptr[0]; -#if defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG) - uint8_t op_size =3D tb_ptr[1]; - const uint8_t *old_code_ptr =3D tb_ptr; -#endif TCGReg r0, r1, r2, r3; tcg_target_ulong t1; TCGCond condition; @@ -476,7 +543,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; case INDEX_op_br: tci_args_l(&tb_ptr, &ptr); - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D ptr; continue; case INDEX_op_setcond_i32: @@ -629,9 +695,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_brcond_i32: tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); if (tci_compare32(regs[r0], regs[r1], condition)) { - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D ptr; - continue; } break; #if TCG_TARGET_REG_BITS =3D=3D 32 @@ -652,7 +716,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, T1 =3D tci_uint64(regs[r1], regs[r0]); T2 =3D tci_uint64(regs[r3], regs[r2]); if (tci_compare64(T1, T2, condition)) { - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D ptr; continue; } @@ -786,9 +849,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_brcond_i64: tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); if (tci_compare64(regs[r0], regs[r1], condition)) { - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D ptr; - continue; } break; case INDEX_op_ext32s_i64: @@ -817,9 +878,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, =20 case INDEX_op_goto_tb: tci_args_l(&tb_ptr, &ptr); - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D *(void **)ptr; - continue; + break; =20 case INDEX_op_qemu_ld_i32: if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { @@ -997,6 +1057,5 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, default: g_assert_not_reached(); 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.23.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7AU7AuzkprD1DzoX758oP/Mpq/Dm/wXzaoKexxvkWBk=; b=LS6rtZx+4ivLf4VFVAv5uhE44x1uSydEJwQUaVSYdDG+vhvKBpPHfTypHN3WzcMTnE 2DgxBIfMp6oGGoerAXvVYzQ/uMz3E/heS/gvV55zXG1mk9vcA2L7I80AGhFkxmaxeKI+ hzOkJ1dlvR6PgAQ81N7inMCPqnokVPGaU4AMFGUodcokwr1R4lpNlBoVVwigxreFUhPC PH7x3KV0C8vwsY5rctqPqZQuxF8F8HWQNPxqKL+QECF6eg8hNAy+QwhkqAp37ios5gb/ hKJaECYku3iXv+2zGbM5TX8GbD+98Fjlz3LiufEXzxFgdNbWEwoQH00pFLeTIEYQVr/V +OqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7AU7AuzkprD1DzoX758oP/Mpq/Dm/wXzaoKexxvkWBk=; b=eEqVZ26vbvaRdFvLYkAb0SNhQhCUnhZ0mFABAz7ystN7dv2xOT9BjDq8zfeh3HtDvV 65QKVYUX+15FVe0rPQZov5BY3JeRbv7g+lmFz6iFBmCpKUEaUNPvCCcYGzl+zKA6uIOh v5W2yD8O00zsIBwhjRWTkJeEWR+Wx1H+pMmuosWlDqWcC7Wj0nepGKf578xucAUyXPez RhW3yeiilGmIb33PhQpy13ULPHFyyO1Mt2XWj0zg+G4lko2CM57M4VWER8YmmB2LAIga ZYT/OhbLH/C54Kye5g15EYLePqAK3vPMYjp50TMq4XOyCtfJ7h7Punh1hJW2J+pGpd5d GT7A== X-Gm-Message-State: AOAM530Du5NO2cZaFfO2oIVTln7vD5rAlM0TsM6SEcur7Dc8mtG9JuSd XX27MFA5+yMrQAxPHSILCspLCUpw6O+aGw== X-Google-Smtp-Source: ABdhPJxXEIdDpbjR37NIDnkJVMnpSlaGo0x59vkfgDg+XkXwrhRJ0/GT4iXvth0hBx+uttEaPoivfA== X-Received: by 2002:a62:cd48:0:b029:1ec:deac:28cd with SMTP id o69-20020a62cd480000b02901ecdeac28cdmr911788pfg.75.1613593383416; Wed, 17 Feb 2021 12:23:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 35/71] tcg/tci: Remove tci_disas Date: Wed, 17 Feb 2021 12:20:00 -0800 Message-Id: <20210217202036.1724901-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FUZZY_BITCOIN=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This function is unused. It's not even the disassembler, which is print_insn_tci, located in disas/tci.c. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 2 -- tcg/tci/tcg-target.c.inc | 10 ---------- 2 files changed, 12 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 9285c930a2..52af6d8bc5 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -163,8 +163,6 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_STACK_ALIGN 16 =20 -void tci_disas(uint8_t opc); - #define HAVE_TCG_QEMU_TB_EXEC =20 /* We could notice __i386__ or __s390x__ and reduce the barriers depending diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 6c187a25cc..7fb3b04eaf 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -253,16 +253,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, return true; } =20 -#if defined(CONFIG_DEBUG_TCG_INTERPRETER) -/* Show current bytecode. Used by tcg interpreter. */ -void tci_disas(uint8_t opc) -{ - const TCGOpDef *def =3D &tcg_op_defs[opc]; - fprintf(stderr, "TCG %s %u, %u, %u\n", - def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs); -} -#endif - /* Write value (native size). */ static void tcg_out_i(TCGContext *s, tcg_target_ulong v) { --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613595003261699.323188682589; Wed, 17 Feb 2021 12:50:03 -0800 (PST) Received: from localhost ([::1]:54806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTlp-0000tP-OV for importer@patchew.org; Wed, 17 Feb 2021 15:50:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33106) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTLo-00007x-BR for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:23:08 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:36579) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTLl-0007QD-W0 for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:23:08 -0500 Received: by mail-pj1-x102d.google.com with SMTP id gx20so2401736pjb.1 for ; Wed, 17 Feb 2021 12:23:05 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.23.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=myNnxOdd6aR6rNRnu4Iw7VN5PbwCEgYK5JJ5Ief1/yY=; b=knbUTgwtE/2I+KZHpzgL8r20A6xNB6VqSwh8Xwl0fpDS9jK8homR1Tc2D0unC7tN77 E8PeHDTZBHC7S6z7d4iWJsIcjAeZbMXrCqXsBrqy9u2+AP4Ag1XdjJ+22EFBQqGpWIVA 116VL51GTwZKYTZvSq8Ms1VLKa12aqze+fptdqCI9BrXUbpzJC7tpCiEAdK41AGkwjUD wPUzJIfc4XNjFrRbUH1Vnpq+Rvk/K25j7NwkdnWP5x6zzXOpxbiQrnQFPEEWkX3JXbsq BK6mvLXG4oQDj8Nh868ka2ZIVFpjsRak5w6UOlGm4q8Ot9yIc6p6nfCvv6lqEiqkXryo dopQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=myNnxOdd6aR6rNRnu4Iw7VN5PbwCEgYK5JJ5Ief1/yY=; b=Yrt+aaSxKXvkuwxYhsBSZMvMayFw03scDh+YuZMXj9WpCarNlO9bYYPnR80WiVaKd9 usB6YCt40QOHGj6rsurss7eJ26DvMD5wcc+FU5PA0BZVwVlm9GigquVWRpIi2M5kBqAH 3lK7HDKyB5tk3Xs7Ody/OXA1E7ytbRGy1pvcAGcm+sC11io4g/GpBS9SGw/+gb4yHlD7 u5Nk7wlfsx2yoq42g+m+JqRWYu2V/Zhr/23bDZ9zJooos01yzm0Ky+CYWA45kx+mCRyP qARxhiYa8nttnbStd0VHloXxWhEGtxJJQuFjRw38ALKEn4A3VAFzg6PCvQle+wcCPeM6 /Olw== X-Gm-Message-State: AOAM533QQtQ3VsJ1fYiFS7XcdkARihfhUn2SpdL/iw/mxaPTfXOKQ52j k6kTCzmihzcjTfzVfWkQMmVcPP1C/4xdBA== X-Google-Smtp-Source: ABdhPJzFi3TjMv8tAbaWnrnWS20j9NcwaVT9v9yVJFEYoM+J2NdAWXdoNSj+NWFYQzk1LmpVioAVTQ== X-Received: by 2002:a17:90a:cd06:: with SMTP id d6mr586546pju.86.1613593384736; Wed, 17 Feb 2021 12:23:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 36/71] tcg/tci: Implement the disassembler properly Date: Wed, 17 Feb 2021 12:20:01 -0800 Message-Id: <20210217202036.1724901-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Actually print arguments as opposed to simply the opcodes and, uselessly, the argument counts. Reuse all of the helpers developed as part of the interpreter. Signed-off-by: Richard Henderson --- meson.build | 2 +- include/tcg/tcg-opc.h | 2 - disas/tci.c | 61 --------- tcg/tci.c | 283 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 284 insertions(+), 64 deletions(-) delete mode 100644 disas/tci.c diff --git a/meson.build b/meson.build index a923f249d8..da225d68a7 100644 --- a/meson.build +++ b/meson.build @@ -1925,7 +1925,7 @@ specific_ss.add(when: 'CONFIG_TCG', if_true: files( 'tcg/tcg-op.c', 'tcg/tcg.c', )) -specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('disas/tci.= c', 'tcg/tci.c')) +specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('tcg/tci.c'= )) =20 subdir('backends') subdir('disas') diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 900984c005..bbb0884af8 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -278,10 +278,8 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) #ifdef TCG_TARGET_INTERPRETER /* These opcodes are only for use between the tci generator and interprete= r. */ DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) -#if TCG_TARGET_REG_BITS =3D=3D 64 DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) #endif -#endif =20 #undef TLADDR_ARGS #undef DATA64_ARGS diff --git a/disas/tci.c b/disas/tci.c deleted file mode 100644 index f1d6c6b469..0000000000 --- a/disas/tci.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Tiny Code Interpreter for QEMU - disassembler - * - * Copyright (c) 2011 Stefan Weil - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "qemu/osdep.h" -#include "qemu-common.h" -#include "disas/dis-asm.h" -#include "tcg/tcg.h" - -/* Disassemble TCI bytecode. */ -int print_insn_tci(bfd_vma addr, disassemble_info *info) -{ - int length; - uint8_t byte; - int status; - TCGOpcode op; - - status =3D info->read_memory_func(addr, &byte, 1, info); - if (status !=3D 0) { - info->memory_error_func(status, addr, info); - return -1; - } - op =3D byte; - - addr++; - status =3D info->read_memory_func(addr, &byte, 1, info); - if (status !=3D 0) { - info->memory_error_func(status, addr, info); - return -1; - } - length =3D byte; - - if (op >=3D tcg_op_defs_max) { - info->fprintf_func(info->stream, "illegal opcode %d", op); - } else { - const TCGOpDef *def =3D &tcg_op_defs[op]; - int nb_oargs =3D def->nb_oargs; - int nb_iargs =3D def->nb_iargs; - int nb_cargs =3D def->nb_cargs; - /* TODO: Improve disassembler output. */ - info->fprintf_func(info->stream, "%s\to=3D%d i=3D%d c=3D%d", - def->name, nb_oargs, nb_iargs, nb_cargs); - } - - return length; -} diff --git a/tcg/tci.c b/tcg/tci.c index 6b63beea28..41d73edc3a 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -1059,3 +1059,286 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArch= State *env, } } } + +/* + * Disassembler that matches the interpreter + */ + +static const char *str_r(TCGReg r) +{ + static const char regs[TCG_TARGET_NB_REGS][4] =3D { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "env", "sp" + }; + + QEMU_BUILD_BUG_ON(TCG_AREG0 !=3D TCG_REG_R14); + QEMU_BUILD_BUG_ON(TCG_REG_CALL_STACK !=3D TCG_REG_R15); + + assert((unsigned)r < TCG_TARGET_NB_REGS); + return regs[r]; +} + +static const char *str_c(TCGCond c) +{ + static const char cond[16][8] =3D { + [TCG_COND_NEVER] =3D "never", + [TCG_COND_ALWAYS] =3D "always", + [TCG_COND_EQ] =3D "eq", + [TCG_COND_NE] =3D "ne", + [TCG_COND_LT] =3D "lt", + [TCG_COND_GE] =3D "ge", + [TCG_COND_LE] =3D "le", + [TCG_COND_GT] =3D "gt", + [TCG_COND_LTU] =3D "ltu", + [TCG_COND_GEU] =3D "geu", + [TCG_COND_LEU] =3D "leu", + [TCG_COND_GTU] =3D "gtu", + }; + + assert((unsigned)c < ARRAY_SIZE(cond)); + assert(cond[c][0] !=3D 0); + return cond[c]; +} + +/* Disassemble TCI bytecode. */ +int print_insn_tci(bfd_vma addr, disassemble_info *info) +{ + uint8_t buf[256]; + int length, status; + const TCGOpDef *def; + const char *op_name; + TCGOpcode op; + TCGReg r0, r1, r2, r3; +#if TCG_TARGET_REG_BITS =3D=3D 32 + TCGReg r4, r5; +#endif + tcg_target_ulong i1; + int32_t s2; + TCGCond c; + TCGMemOpIdx oi; + uint8_t pos, len; + void *ptr; + const uint8_t *tb_ptr; + + status =3D info->read_memory_func(addr, buf, 2, info); + if (status !=3D 0) { + info->memory_error_func(status, addr, info); + return -1; + } + op =3D buf[0]; + length =3D buf[1]; + + if (length < 2) { + info->fprintf_func(info->stream, "invalid length %d", length); + return 1; + } + + status =3D info->read_memory_func(addr + 2, buf + 2, length - 2, info); + if (status !=3D 0) { + info->memory_error_func(status, addr + 2, info); + return -1; + } + + def =3D &tcg_op_defs[op]; + op_name =3D def->name; + tb_ptr =3D buf + 2; + + switch (op) { + case INDEX_op_br: + case INDEX_op_call: + case INDEX_op_exit_tb: + case INDEX_op_goto_tb: + tci_args_l(&tb_ptr, &ptr); + info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); + break; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%p", + op_name, str_r(r0), str_r(r1), str_c(c), ptr); + break; + + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &c); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", + op_name, str_r(r0), str_r(r1), str_r(r2), str_c= (c)); + break; + + case INDEX_op_tci_movi_i32: + tci_args_ri(&tb_ptr, &r0, &i1); + info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "", + op_name, str_r(r0), i1); + break; + +#if TCG_TARGET_REG_BITS =3D=3D 64 + case INDEX_op_tci_movi_i64: + tci_args_rI(&tb_ptr, &r0, &i1); + info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "", + op_name, str_r(r0), i1); + break; +#endif + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i32: + case INDEX_op_ld_i64: + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i32: + case INDEX_op_st_i64: + tci_args_rrs(&tb_ptr, &r0, &r1, &s2); + info->fprintf_func(info->stream, "%-12s %s,%s,%d", + op_name, str_r(r0), str_r(r1), s2); + break; + + case INDEX_op_mov_i32: + case INDEX_op_mov_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + case INDEX_op_not_i32: + case INDEX_op_not_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + tci_args_rr(&tb_ptr, &r0, &r1); + info->fprintf_func(info->stream, "%-12s %s,%s", + op_name, str_r(r0), str_r(r1)); + break; + + case INDEX_op_add_i32: + case INDEX_op_add_i64: + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + case INDEX_op_and_i32: + case INDEX_op_and_i64: + case INDEX_op_or_i32: + case INDEX_op_or_i64: + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + case INDEX_op_div_i32: + case INDEX_op_div_i64: + case INDEX_op_rem_i32: + case INDEX_op_rem_i64: + case INDEX_op_divu_i32: + case INDEX_op_divu_i64: + case INDEX_op_remu_i32: + case INDEX_op_remu_i64: + case INDEX_op_shl_i32: + case INDEX_op_shl_i64: + case INDEX_op_shr_i32: + case INDEX_op_shr_i64: + case INDEX_op_sar_i32: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + info->fprintf_func(info->stream, "%-12s %s,%s,%s", + op_name, str_r(r0), str_r(r1), str_r(r2)); + break; + + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%d,%d", + op_name, str_r(r0), str_r(r1), str_r(r2), pos, = len); + break; + +#if TCG_TARGET_REG_BITS =3D=3D 32 + case INDEX_op_setcond2_i32: + tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &c); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", + op_name, str_r(r0), str_r(r1), str_r(r2), + str_r(r3), str_r(r4), str_c(c)); + break; + + case INDEX_op_brcond2_i32: + tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &c, &ptr); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%p", + op_name, str_r(r0), str_r(r1), + str_r(r2), str_r(r3), str_c(c), ptr); + break; + + case INDEX_op_mulu2_i32: + tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", + op_name, str_r(r0), str_r(r1), + str_r(r2), str_r(r3)); + break; + + case INDEX_op_add2_i32: + case INDEX_op_sub2_i32: + tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", + op_name, str_r(r0), str_r(r1), str_r(r2), + str_r(r3), str_r(r4), str_r(r5)); + break; +#endif + + case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_st_i64: + len =3D DIV_ROUND_UP(64, TCG_TARGET_REG_BITS); + goto do_qemu_ldst; + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_st_i32: + len =3D 1; + do_qemu_ldst: + len +=3D DIV_ROUND_UP(TARGET_LONG_BITS, TCG_TARGET_REG_BITS); + switch (len) { + case 2: + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + info->fprintf_func(info->stream, "%-12s %s,%s,%x", + op_name, str_r(r0), str_r(r1), oi); + break; + case 3: + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%x", + op_name, str_r(r0), str_r(r1), str_r(r2), o= i); + break; + case 4: + tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%x", + op_name, str_r(r0), str_r(r1), + str_r(r2), str_r(r3), oi); + break; + default: + g_assert_not_reached(); + } + break; + + default: + info->fprintf_func(info->stream, "illegal opcode %d", op); + break; + } + + return length; +} --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.23.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IZJYtj1LIQJQfBG9GiqiNyDssVPoT54B6WtqSi2XL6w=; b=wEkrR4NKcI4P3O6oC30ZeFcjLUEvdQdr1DdzdyizJLPPWkgea6IMrjbfJuEd/aqnkU T2gSVDzBbTTT0FuGXvz6OehA1DBHiYs75NFvfoIF1gpZusaYVKYLtN/4IbpKrvayMYaj YxLpVEIra+qaa/2ac7p2YaiP3OzRsoZULzMZufb0mZMCEgXzwOXL4+zihFSNR38Ax7Ws opRXonykh836kms8SNtkeDsOM7yABQoGl+l0MQy+IUZYhcxPWFEVgWtrMfrh9lk2c9WH 9CuRloRfKZlow+LM6TG1rHD2xD02WdZiHrWvWlKM5MH4b0AK5lYY9mNIoeBa1dtzjGTz RTVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IZJYtj1LIQJQfBG9GiqiNyDssVPoT54B6WtqSi2XL6w=; b=LZjpUlqDDm6aFCQBR46nu3gcxx5KKCB2+C2pmnMOL6Tq1XJEZ0mS31CzJLhcdC9jkt DWJqyWe74zE6IvUTXHGYdVXZ1w43TdumUxN0CcAJLkxa0qmq9J0PCJ1c2K/9b/6HGpsj d4QMSrmmN1bR14O+PFHT0UUnjD9QsjLWE6Tbqzo/p4XRyq1kQrZyLSoQiJLmdIPHm77C 9bMVCJZA4FOtGagN9b6+hfgZpLtHHAuo6tYy+Zh9dWyMrrQYTvsJ5uamuzNCzxA1l+in BCWbDC6MaL1EJQvwR1ec80G+umRb1oVtW6RGsv5T6EveK/ez9vh6TfQValE1R4/yzVea 6EkQ== X-Gm-Message-State: AOAM531AALobq1yMPLlIYYNiEzfiil88SPOI5fVY5wYV5uVbgqc7j7PD Nuaa7UD5HSbFcdtz4w3ZrNJxuTvCQ176xg== X-Google-Smtp-Source: ABdhPJwR613ZywkV+gyVzma++P5f20dp1AiJ/8w05AE3KGk9wbdi8Op4Qes+fgb4BDn7R/LRTIcd3w== X-Received: by 2002:a17:90a:2c9:: with SMTP id d9mr529476pjd.67.1613593386357; Wed, 17 Feb 2021 12:23:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 37/71] tcg: Build ffi data structures for helpers Date: Wed, 17 Feb 2021 12:20:02 -0800 Message-Id: <20210217202036.1724901-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" We will shortly use libffi for tci, as that is the only portable way of calling arbitrary functions. Signed-off-by: Richard Henderson --- meson.build | 9 +- include/exec/helper-ffi.h | 115 +++++++++++++++++++++++++ include/exec/helper-tcg.h | 24 ++++-- target/hppa/helper.h | 2 + target/i386/ops_sse_header.h | 6 ++ target/m68k/helper.h | 1 + target/ppc/helper.h | 3 + tcg/tcg.c | 20 +++++ tests/docker/dockerfiles/fedora.docker | 1 + 9 files changed, 172 insertions(+), 9 deletions(-) create mode 100644 include/exec/helper-ffi.h diff --git a/meson.build b/meson.build index da225d68a7..6d5d1b914b 100644 --- a/meson.build +++ b/meson.build @@ -1925,7 +1925,14 @@ specific_ss.add(when: 'CONFIG_TCG', if_true: files( 'tcg/tcg-op.c', 'tcg/tcg.c', )) -specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('tcg/tci.c'= )) + +if get_option('tcg_interpreter') + libffi =3D dependency('libffi', version: '>=3D3.0', + static: enable_static, method: 'pkg-config', + required: true) + specific_ss.add(libffi) + specific_ss.add(files('tcg/tci.c')) +endif =20 subdir('backends') subdir('disas') diff --git a/include/exec/helper-ffi.h b/include/exec/helper-ffi.h new file mode 100644 index 0000000000..3af1065af3 --- /dev/null +++ b/include/exec/helper-ffi.h @@ -0,0 +1,115 @@ +/* + * Helper file for declaring TCG helper functions. + * This one defines data structures private to tcg.c. + */ + +#ifndef HELPER_FFI_H +#define HELPER_FFI_H 1 + +#include "exec/helper-head.h" + +#define dh_ffitype_i32 &ffi_type_uint32 +#define dh_ffitype_s32 &ffi_type_sint32 +#define dh_ffitype_int &ffi_type_sint +#define dh_ffitype_i64 &ffi_type_uint64 +#define dh_ffitype_s64 &ffi_type_sint64 +#define dh_ffitype_f16 &ffi_type_uint32 +#define dh_ffitype_f32 &ffi_type_uint32 +#define dh_ffitype_f64 &ffi_type_uint64 +#ifdef TARGET_LONG_BITS +# if TARGET_LONG_BITS =3D=3D 32 +# define dh_ffitype_tl &ffi_type_uint32 +# else +# define dh_ffitype_tl &ffi_type_uint64 +# endif +#endif +#define dh_ffitype_ptr &ffi_type_pointer +#define dh_ffitype_cptr &ffi_type_pointer +#define dh_ffitype_void &ffi_type_void +#define dh_ffitype_noreturn &ffi_type_void +#define dh_ffitype_env &ffi_type_pointer +#define dh_ffitype(t) glue(dh_ffitype_, t) + +#define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 0, \ + }; + +#define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \ + static ffi_type *glue(cif_args_,NAME)[1] =3D { dh_ffitype(t1) }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 1, = \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \ + static ffi_type *glue(cif_args_,NAME)[2] =3D { \ + dh_ffitype(t1), dh_ffitype(t2) \ + }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 2, \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \ + static ffi_type *glue(cif_args_,NAME)[3] =3D { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3) \ + }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 3, \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \ + static ffi_type *glue(cif_args_,NAME)[4] =3D { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), dh_ffitype(t4) \ + }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 4, = \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \ + static ffi_type *glue(cif_args_,NAME)[5] =3D { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), \ + dh_ffitype(t4), dh_ffitype(t5) \ + }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 5, = \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \ + static ffi_type *glue(cif_args_,NAME)[6] =3D { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), \ + dh_ffitype(t4), dh_ffitype(t5), dh_ffitype(t6) \ + }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 6, = \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \ + static ffi_type *glue(cif_args_,NAME)[7] =3D { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), \ + dh_ffitype(t4), dh_ffitype(t5), dh_ffitype(t6), dh_ffitype(t7) \ + }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 7, = \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#include "helper.h" +#include "trace/generated-helpers.h" +#include "tcg-runtime.h" + +#undef DEF_HELPER_FLAGS_0 +#undef DEF_HELPER_FLAGS_1 +#undef DEF_HELPER_FLAGS_2 +#undef DEF_HELPER_FLAGS_3 +#undef DEF_HELPER_FLAGS_4 +#undef DEF_HELPER_FLAGS_5 +#undef DEF_HELPER_FLAGS_6 +#undef DEF_HELPER_FLAGS_7 + +#endif /* HELPER_FFI_H */ diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h index 27870509a2..a71b848576 100644 --- a/include/exec/helper-tcg.h +++ b/include/exec/helper-tcg.h @@ -10,50 +10,57 @@ to get all the macros expanded first. */ #define str(s) #s =20 +#ifdef CONFIG_TCG_INTERPRETER +# define DO_CIF(NAME) .cif =3D &cif_##NAME, +#else +# define DO_CIF(NAME) +#endif + #define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) }, =20 #define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) }, =20 #define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) }, =20 #define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) }, =20 #define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) }, =20 #define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | dh_sizemask(t5, 5) }, =20 #define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) }, =20 #define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), .flags =3D FLAGS, \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ + .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) | dh_sizemask(t7, 7) }, @@ -64,6 +71,7 @@ #include "plugin-helpers.h" =20 #undef str +#undef DO_CIF #undef DEF_HELPER_FLAGS_0 #undef DEF_HELPER_FLAGS_1 #undef DEF_HELPER_FLAGS_2 diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 2d483aab58..35c612f09d 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -1,9 +1,11 @@ #if TARGET_REGISTER_BITS =3D=3D 64 # define dh_alias_tr i64 # define dh_is_64bit_tr 1 +# define dh_ffitype_tr dh_ffitype_i64 #else # define dh_alias_tr i32 # define dh_is_64bit_tr 0 +# define dh_ffitype_tr dh_ffitype_i32 #endif #define dh_ctype_tr target_ureg #define dh_is_signed_tr 0 diff --git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h index 6c0c849347..cae50f77eb 100644 --- a/target/i386/ops_sse_header.h +++ b/target/i386/ops_sse_header.h @@ -27,13 +27,19 @@ #define dh_alias_Reg ptr #define dh_alias_ZMMReg ptr #define dh_alias_MMXReg ptr + #define dh_ctype_Reg Reg * #define dh_ctype_ZMMReg ZMMReg * #define dh_ctype_MMXReg MMXReg * + #define dh_is_signed_Reg dh_is_signed_ptr #define dh_is_signed_ZMMReg dh_is_signed_ptr #define dh_is_signed_MMXReg dh_is_signed_ptr =20 +#define dh_ffitype_Reg dh_ffitype_ptr +#define dh_ffitype_ZMMReg dh_ffitype_ptr +#define dh_ffitype_MMXReg dh_ffitype_ptr + DEF_HELPER_3(glue(psrlw, SUFFIX), void, env, Reg, Reg) DEF_HELPER_3(glue(psraw, SUFFIX), void, env, Reg, Reg) DEF_HELPER_3(glue(psllw, SUFFIX), void, env, Reg, Reg) diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 77808497a9..672c99d5de 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -18,6 +18,7 @@ DEF_HELPER_4(cas2l_parallel, void, env, i32, i32, i32) #define dh_alias_fp ptr #define dh_ctype_fp FPReg * #define dh_is_signed_fp dh_is_signed_ptr +#define dh_ffitype_fp dh_ffitype_ptr =20 DEF_HELPER_3(exts32, void, env, fp, s32) DEF_HELPER_3(extf32, void, env, fp, f32) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 6a4dccf70c..bbd4700064 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -108,10 +108,12 @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i= 64) #define dh_alias_avr ptr #define dh_ctype_avr ppc_avr_t * #define dh_is_signed_avr dh_is_signed_ptr +#define dh_ffitype_avr dh_ffitype_ptr =20 #define dh_alias_vsr ptr #define dh_ctype_vsr ppc_vsr_t * #define dh_is_signed_vsr dh_is_signed_ptr +#define dh_ffitype_vsr dh_ffitype_ptr =20 DEF_HELPER_3(vavgub, void, avr, avr, avr) DEF_HELPER_3(vavguh, void, avr, avr, avr) @@ -696,6 +698,7 @@ DEF_HELPER_3(store_601_batu, void, env, i32, tl) #define dh_alias_fprp ptr #define dh_ctype_fprp ppc_fprp_t * #define dh_is_signed_fprp dh_is_signed_ptr +#define dh_ffitype_fprp dh_ffitype_ptr =20 DEF_HELPER_4(dadd, void, env, fprp, fprp, fprp) DEF_HELPER_4(daddq, void, env, fprp, fprp, fprp) diff --git a/tcg/tcg.c b/tcg/tcg.c index 2991112829..6382112215 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -66,6 +66,10 @@ #include "exec/log.h" #include "sysemu/sysemu.h" =20 +#ifdef CONFIG_TCG_INTERPRETER +#include +#endif + /* Forward declarations for functions declared in tcg-target.c.inc and used here. */ static void tcg_target_init(TCGContext *s); @@ -1082,6 +1086,9 @@ void tcg_pool_reset(TCGContext *s) =20 typedef struct TCGHelperInfo { void *func; +#ifdef CONFIG_TCG_INTERPRETER + ffi_cif *cif; +#endif const char *name; unsigned flags; unsigned sizemask; @@ -1089,6 +1096,10 @@ typedef struct TCGHelperInfo { =20 #include "exec/helper-proto.h" =20 +#ifdef CONFIG_TCG_INTERPRETER +#include "exec/helper-ffi.h" +#endif + static const TCGHelperInfo all_helpers[] =3D { #include "exec/helper-tcg.h" }; @@ -1136,6 +1147,15 @@ void tcg_context_init(TCGContext *s) (gpointer)&all_helpers[i]); } =20 +#ifdef CONFIG_TCG_INTERPRETER + for (i =3D 0; i < ARRAY_SIZE(all_helpers); ++i) { + ffi_cif *cif =3D all_helpers[i].cif; + ffi_status ok =3D ffi_prep_cif(cif, FFI_DEFAULT_ABI, cif->nargs, + cif->rtype, cif->arg_types); + tcg_debug_assert(ok =3D=3D FFI_OK); + } +#endif + tcg_target_init(s); process_op_defs(s); =20 diff --git a/tests/docker/dockerfiles/fedora.docker b/tests/docker/dockerfi= les/fedora.docker index 0d7602abbe..45fc1a77bd 100644 --- a/tests/docker/dockerfiles/fedora.docker +++ b/tests/docker/dockerfiles/fedora.docker @@ -32,6 +32,7 @@ ENV PACKAGES \ libcurl-devel \ libepoxy-devel \ libfdt-devel \ + libffi-devel \ libiscsi-devel \ libjpeg-devel \ libpmem-devel \ --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613596128; cv=none; d=zohomail.com; s=zohoarc; b=bLi1vVIzqeErwEl3CXxx8k6FveWUvzOI4HdkTl+HpTcBWnh5+HlkOTr4ivgJiVtknk9XDo9ZyB9Fv1TY0sBqQtbMIwBlGLmwJtWFzFIdtZiYQeey8IMvAX4FgZr2hSRBbIY1DZ5NJXpGwc8gSOZBnSeCcDAhnxme2FG7g9it+rE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.23.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gGw3KxVq5Tq8weV/0bnuBl/4JXq/wSN4ULQQQb9LWe0=; b=ofA4L56/zPktkHSFbkdy5RdO+MVYsInHehvvYFJwVJtb4umb1mTzSthFOjbojM8TM6 nkTQyeXzxlR+oHr1h+ql6EbBfDDYqwGVUd7bHcqw15QRV5Lbf+iuyrF86rVzNhmyA981 h30+cCuI++Nl+DrE3ebYhGHlcQ/cINWvlBVaUrj7tQvKb/H4ju970ki1CxJx2TLKtHdp suBytHXJk5xuCXLBge4ZZT2YwJ2pwt7Fq8t0WSq+psIBTC9VxYPf/T/nACBBD6A+2hWO ZPjyl6fxSx3511ZL7vqoi27/V0S4KXH6atThEIRsIJaOwuTmRB/Oo94XsRl+8HsQlWkk gn3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gGw3KxVq5Tq8weV/0bnuBl/4JXq/wSN4ULQQQb9LWe0=; b=XS9iK52v/yh6gFZZduJq61OOArGEKRt/v9mz9qCYXulnKzFReTbBmgQkmgpHa66OFL s8jvDPnkSxevCvC+BtUvts3/FpixtozqYPjCvCpdMDHNVdsXtcB39jCT3eUVDdRCThlq j+qSMv+ZJe8se8nkgqyRLCc6XmFAelWxw6tfC0a5mE1v4iIBGeeAElbajfe9Ad1Mvc6I bZDrtucziCLH+WI65cnGDEOY37u06zSrjzRSg+numKRV+XgcS6cS6cXwoHdrAoMiMjX/ iTrSwRbjWHvYeqiq2rQ2Q96balHdO0EcPD8OW9j7D6ApbAglV02nT3BZJCmqd/YqbeZS kolg== X-Gm-Message-State: AOAM531I/lx/57v5aRsEXHSpuaNxhM5cXZa7zrPMNv2bq8pnpif1DNST ujsOQiDbew6ANXEqe+KevcKgz3O2N9ttDA== X-Google-Smtp-Source: ABdhPJwcgIhqtuyuC8eH76wfki15/QQk/8CFa4igWGPfwcxKOMvt9UcN1VNuaxJOPaMF11iTzR9hEQ== X-Received: by 2002:a17:90b:797:: with SMTP id l23mr542349pjz.170.1613593387850; Wed, 17 Feb 2021 12:23:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 38/71] tcg/tci: Use ffi for calls Date: Wed, 17 Feb 2021 12:20:03 -0800 Message-Id: <20210217202036.1724901-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This requires adjusting where arguments are stored. Place them on the stack at left-aligned positions. Adjust the stack frame to be at entirely positive offsets. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 + tcg/tci/tcg-target.h | 2 +- tcg/tcg.c | 72 ++++++++++++-------- tcg/tci.c | 138 +++++++++++++++++++++++---------------- tcg/tci/tcg-target.c.inc | 50 +++++++------- 5 files changed, 150 insertions(+), 113 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 0f0695e90d..e5573a9877 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -53,6 +53,7 @@ #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) =20 #define CPU_TEMP_BUF_NLONGS 128 +#define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) =20 /* Default target word size to pointer size. */ #ifndef TCG_TARGET_REG_BITS diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 52af6d8bc5..4df10e2e83 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -161,7 +161,7 @@ typedef enum { =20 /* Used for function call generation. */ #define TCG_TARGET_CALL_STACK_OFFSET 0 -#define TCG_TARGET_STACK_ALIGN 16 +#define TCG_TARGET_STACK_ALIGN 8 =20 #define HAVE_TCG_QEMU_TB_EXEC =20 diff --git a/tcg/tcg.c b/tcg/tcg.c index 6382112215..92aec0d238 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -208,6 +208,18 @@ static size_t tree_size; static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT]; static TCGRegSet tcg_target_call_clobber_regs; =20 +typedef struct TCGHelperInfo { + void *func; +#ifdef CONFIG_TCG_INTERPRETER + ffi_cif *cif; +#endif + const char *name; + unsigned flags; + unsigned sizemask; +} TCGHelperInfo; + +static GHashTable *helper_table; + #if TCG_TARGET_INSN_UNIT_SIZE =3D=3D 1 static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t= v) { @@ -1084,16 +1096,6 @@ void tcg_pool_reset(TCGContext *s) s->pool_current =3D NULL; } =20 -typedef struct TCGHelperInfo { - void *func; -#ifdef CONFIG_TCG_INTERPRETER - ffi_cif *cif; -#endif - const char *name; - unsigned flags; - unsigned sizemask; -} TCGHelperInfo; - #include "exec/helper-proto.h" =20 #ifdef CONFIG_TCG_INTERPRETER @@ -1103,7 +1105,6 @@ typedef struct TCGHelperInfo { static const TCGHelperInfo all_helpers[] =3D { #include "exec/helper-tcg.h" }; -static GHashTable *helper_table; =20 static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)= ]; static void process_op_defs(TCGContext *s); @@ -2081,25 +2082,38 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int na= rgs, TCGTemp **args) =20 real_args =3D 0; for (i =3D 0; i < nargs; i++) { - int is_64bit =3D sizemask & (1 << (i+1)*2); - if (TCG_TARGET_REG_BITS < 64 && is_64bit) { -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - /* some targets want aligned 64 bit args */ - if (real_args & 1) { - op->args[pi++] =3D TCG_CALL_DUMMY_ARG; - real_args++; - } + bool is_64bit =3D sizemask & (1 << (i+1)*2); + bool want_align =3D false; + +#if defined(CONFIG_TCG_INTERPRETER) + /* + * Align all arguments, so that they land in predictable places + * for passing off to ffi_call. + */ + want_align =3D true; +#elif defined(TCG_TARGET_CALL_ALIGN_ARGS) + /* Some targets want aligned 64 bit args */ + want_align =3D is_64bit; #endif - /* If stack grows up, then we will be placing successive - arguments at lower addresses, which means we need to - reverse the order compared to how we would normally - treat either big or little-endian. For those arguments - that will wind up in registers, this still works for - HPPA (the only current STACK_GROWSUP target) since the - argument registers are *also* allocated in decreasing - order. If another such target is added, this logic may - have to get more complicated to differentiate between - stack arguments and register arguments. */ + + if (TCG_TARGET_REG_BITS < 64 && want_align && (real_args & 1)) { + op->args[pi++] =3D TCG_CALL_DUMMY_ARG; + real_args++; + } + + if (TCG_TARGET_REG_BITS < 64 && is_64bit) { + /* + * If stack grows up, then we will be placing successive + * arguments at lower addresses, which means we need to + * reverse the order compared to how we would normally + * treat either big or little-endian. For those arguments + * that will wind up in registers, this still works for + * HPPA (the only current STACK_GROWSUP target) since the + * argument registers are *also* allocated in decreasing + * order. If another such target is added, this logic may + * have to get more complicated to differentiate between + * stack arguments and register arguments. + */ #if defined(HOST_WORDS_BIGENDIAN) !=3D defined(TCG_TARGET_STACK_GROWSUP) op->args[pi++] =3D temp_arg(args[i] + 1); op->args[pi++] =3D temp_arg(args[i]); diff --git a/tcg/tci.c b/tcg/tci.c index 41d73edc3a..5718fc42a6 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -18,6 +18,13 @@ */ =20 #include "qemu/osdep.h" +#include "qemu-common.h" +#include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */ +#include "exec/cpu_ldst.h" +#include "tcg/tcg-op.h" +#include "qemu/compiler.h" +#include + =20 /* Enable TCI assertions only when debugging TCG (and without NDEBUG defin= ed). * Without assertions, the interpreter runs much faster. */ @@ -27,36 +34,8 @@ # define tci_assert(cond) ((void)(cond)) #endif =20 -#include "qemu-common.h" -#include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */ -#include "exec/cpu_ldst.h" -#include "tcg/tcg-op.h" -#include "qemu/compiler.h" - -#if MAX_OPC_PARAM_IARGS !=3D 6 -# error Fix needed, number of supported input arguments changed! -#endif -#if TCG_TARGET_REG_BITS =3D=3D 32 -typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong); -#else -typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong); -#endif - __thread uintptr_t tci_tb_ptr; =20 -static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg = index) -{ - tci_assert(index < TCG_TARGET_NB_REGS); - return regs[index]; -} - static void tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) { @@ -131,6 +110,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **= tb_ptr) * i =3D immediate (uint32_t) * I =3D immediate (tcg_target_ulong) * m =3D immediate (TCGMemOpIdx) + * n =3D immediate (call return length) * r =3D register * s =3D signed ldst offset */ @@ -151,6 +131,16 @@ static void tci_args_l(const uint8_t **tb_ptr, void **= l0) check_size(start, tb_ptr); } =20 +static void tci_args_nl(const uint8_t **tb_ptr, uint8_t *n0, void **l1) +{ + const uint8_t *start =3D *tb_ptr; + + *n0 =3D tci_read_b(tb_ptr); + *l1 =3D (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); +} + static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { @@ -474,6 +464,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCG= Cond condition) # define CASE_64(x) #endif =20 + /* Interpret pseudo code in tb. */ /* * Disable CFI checks. @@ -485,11 +476,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, { const uint8_t *tb_ptr =3D v_tb_ptr; tcg_target_ulong regs[TCG_TARGET_NB_REGS]; - long tcg_temps[CPU_TEMP_BUF_NLONGS]; - uintptr_t sp_value =3D (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); + uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) + / sizeof(uint64_t)]; + void *call_slots[TCG_STATIC_CALL_ARGS_SIZE / sizeof(uint64_t)]; =20 regs[TCG_AREG0] =3D (tcg_target_ulong)env; - regs[TCG_REG_CALL_STACK] =3D sp_value; + regs[TCG_REG_CALL_STACK] =3D (uintptr_t)stack; + call_slots[0] =3D NULL; tci_assert(tb_ptr); =20 for (;;) { @@ -514,33 +507,60 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 switch (opc) { case INDEX_op_call: - tci_args_l(&tb_ptr, &ptr); + /* + * We are passed a pointer to the TCGHelperInfo, which contains + * the function pointer followed by the ffi_cif pointer. + */ + tci_args_nl(&tb_ptr, &len, &ptr); + + /* Helper functions may need to access the "return address" */ tci_tb_ptr =3D (uintptr_t)tb_ptr; -#if TCG_TARGET_REG_BITS =3D=3D 32 - tmp64 =3D ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0= ), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5), - tci_read_reg(regs, TCG_REG_R6), - tci_read_reg(regs, TCG_REG_R7), - tci_read_reg(regs, TCG_REG_R8), - tci_read_reg(regs, TCG_REG_R9), - tci_read_reg(regs, TCG_REG_R10), - tci_read_reg(regs, TCG_REG_R11)= ); - tci_write_reg(regs, TCG_REG_R0, tmp64); - tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); -#else - tmp64 =3D ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0= ), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5)); - tci_write_reg(regs, TCG_REG_R0, tmp64); -#endif + + /* + * Set up the ffi_avalue array once, delayed until now + * because many TB's do not make any calls. In tcg_gen_callN, + * we arranged for every real argument to be "left-aligned" + * in each 64-bit slot. + */ + if (call_slots[0] =3D=3D NULL) { + for (int i =3D 0; i < ARRAY_SIZE(call_slots); ++i) { + call_slots[i] =3D &stack[i]; + } + } + + /* + * Call the helper function. Any result winds up + * "left-aligned" in the stack[0] slot. + */ + { + void **pptr =3D ptr; + ffi_call(pptr[1], pptr[0], stack, call_slots); + } + switch (len) { + case 0: /* void */ + break; + case 1: /* uint32_t */ + /* + * Note that libffi has an odd special case in that it will + * always widen an integral result to ffi_arg. + */ + if (sizeof(ffi_arg) =3D=3D 4) { + regs[TCG_REG_R0] =3D *(uint32_t *)stack; + break; + } + /* fall through */ + case 2: /* uint64_t */ + if (TCG_TARGET_REG_BITS =3D=3D 32) { + tci_write_reg64(regs, TCG_REG_R1, TCG_REG_R0, stack[0]= ); + } else { + regs[TCG_REG_R0] =3D stack[0]; + } + break; + default: + g_assert_not_reached(); + } break; + case INDEX_op_br: tci_args_l(&tb_ptr, &ptr); tb_ptr =3D ptr; @@ -1145,13 +1165,17 @@ int print_insn_tci(bfd_vma addr, disassemble_info *= info) =20 switch (op) { case INDEX_op_br: - case INDEX_op_call: case INDEX_op_exit_tb: case INDEX_op_goto_tb: tci_args_l(&tb_ptr, &ptr); info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); break; =20 + case INDEX_op_call: + tci_args_nl(&tb_ptr, &len, &ptr); + info->fprintf_func(info->stream, "%-12s %d,%p", op_name, len, ptr= ); + break; + case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 7fb3b04eaf..8d75482546 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -192,23 +192,8 @@ static const int tcg_target_reg_alloc_order[] =3D { # error Fix needed, number of supported input arguments changed! #endif =20 -static const int tcg_target_call_iarg_regs[] =3D { - TCG_REG_R0, - TCG_REG_R1, - TCG_REG_R2, - TCG_REG_R3, - TCG_REG_R4, - TCG_REG_R5, -#if TCG_TARGET_REG_BITS =3D=3D 32 - /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */ - TCG_REG_R6, - TCG_REG_R7, - TCG_REG_R8, - TCG_REG_R9, - TCG_REG_R10, - TCG_REG_R11, -#endif -}; +/* No call arguments via registers. All will be stored on the "stack". */ +static const int tcg_target_call_iarg_regs[] =3D { }; =20 static const int tcg_target_call_oarg_regs[] =3D { TCG_REG_R0, @@ -292,8 +277,9 @@ static void tci_out_label(TCGContext *s, TCGLabel *labe= l) static void stack_bounds_check(TCGReg base, target_long offset) { if (base =3D=3D TCG_REG_CALL_STACK) { - tcg_debug_assert(offset < 0); - tcg_debug_assert(offset >=3D -(CPU_TEMP_BUF_NLONGS * sizeof(long))= ); + tcg_debug_assert(offset >=3D 0); + tcg_debug_assert(offset < (TCG_STATIC_CALL_ARGS_SIZE + + TCG_STATIC_FRAME_SIZE)); } } =20 @@ -360,11 +346,25 @@ static void tcg_out_movi(TCGContext *s, TCGType type, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 -static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { uint8_t *old_code_ptr =3D s->code_ptr; + const TCGHelperInfo *info; + uint8_t which; + + info =3D g_hash_table_lookup(helper_table, (gpointer)arg); + if (info->cif->rtype =3D=3D &ffi_type_void) { + which =3D 0; + } else if (info->cif->rtype->size =3D=3D 4) { + which =3D 1; + } else { + tcg_debug_assert(info->cif->rtype->size =3D=3D 8); + which =3D 2; + } tcg_out_op_t(s, INDEX_op_call); - tcg_out_i(s, (uintptr_t)arg); + tcg_out8(s, which); + tcg_out_i(s, (uintptr_t)info); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 @@ -629,11 +629,9 @@ static void tcg_target_init(TCGContext *s) s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); =20 - /* We use negative offsets from "sp" so that we can distinguish - stores that might pretend to be call arguments. */ - tcg_set_frame(s, TCG_REG_CALL_STACK, - -CPU_TEMP_BUF_NLONGS * sizeof(long), - CPU_TEMP_BUF_NLONGS * sizeof(long)); + /* The call arguments come first, followed by the temp storage. */ + tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, + TCG_STATIC_FRAME_SIZE); } =20 /* Generate global QEMU prologue and epilogue code. */ --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613596357; cv=none; d=zohomail.com; s=zohoarc; b=QXb04BBJDodjnZf8UvvQdXsxZuQsTzZAlkL/EM9siiEy5a1WkJg6rVEadCVlBaIa/Qoocy99LiGbG5ZE10PZ4jhj2rFIA/CFMPRzabkchkqTtffV5teLf/+fvLRmkBs89LCeJJ3eE/2PxZZzIbfj9hVJPkqHRs37jdUivKQbGJQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613596357; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YQBNB7jLXwaZJSYBL0BvoU6n3wPE6zwxayv+Hpeg13U=; b=AwpHeWdQy2ow2eE8vJiojIEXrZ5HHEzGll8hH1Eqw1pYeTNFYoQ5XVEV9V6EWeU7qZmKdkwf7jpEiXOqGLHAA7JM7EFMhOHsO8+ngJeEJg3o3dCM9LZO6nDXW+o1+vpbcNit49puqdFaJhvBJQ0J/k5oVC5rIoXCPraGFUeW/ss= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613596357150778.9849867657409; Wed, 17 Feb 2021 13:12:37 -0800 (PST) Received: from localhost ([::1]:54970 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCU7f-0008HO-PB for importer@patchew.org; Wed, 17 Feb 2021 16:12:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33168) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTLr-0000Gf-Sv for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:23:11 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:39835) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTLq-0007RX-9A for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:23:11 -0500 Received: by mail-pl1-x629.google.com with SMTP id k22so8037857pll.6 for ; Wed, 17 Feb 2021 12:23:09 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.23.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YQBNB7jLXwaZJSYBL0BvoU6n3wPE6zwxayv+Hpeg13U=; b=CrIcLrHZ0Rh52t2wb7GUyu+5r8ddJfmHxQCpdvw75u/7d0Y7QkeJBtG6pmP4ckjNDi FleiHPCx5dlDiZbLkXYnjeL6YLCBjNszg3Sokb/3G2f++HyCAwgnc6EtU0YzRzKroRrB 01KJ4M0/ygEpUtWEX/UNMQcvf5vHwjtq4aAifon4be2hPX1arYCuuJcXLqhcp9dp5jvM A/3QUROtzBQIsQaabIL4ZzlO1TS/IWsSy5YfT4m4GmHohxDMLG3bLKnElNdUWLnw+yBo rEmbMnBVV4vSBYwvtqvXJcI1MqBgtB9Xb7/d+AxWmmlTUWDy8h6HtM/wWHtwyx77eOXI SExQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YQBNB7jLXwaZJSYBL0BvoU6n3wPE6zwxayv+Hpeg13U=; b=n5fKuK19npEtgMjFl6R7LH6LYsDkJZj2gqWO0Nn9dNMuv55VQ4C1ilT5eBCUYBg6GZ elcWCe/c/BMk8pVuva7eui9fnxd4w2j0kssAeDP2uckGtR/rahrzutV22THv4L9ou/52 gsVK9g7KZdxVomSpuixO8IccTnV9bWubsigWY08ETonQ6IfH8hvcMeA4DtLlN5Rh7CQK OFRQC9PPdk6QlJm5AvUE/sgAr0gsuE/+u5H9ndjJC157alfzlgyL4SiqfblhWp075tBb 6xTB+g04ePJO8313ciU8jEecs5ay3epzXb7udry0ZymyPI1MlVFuHdz1iolbg6GDhHnn 3dpA== X-Gm-Message-State: AOAM531331APzPLMCF28ivoSpLzgHeITqgaup/28f2slmUo3+MwIe3fH apoSCu8RC5TloiqeXkLpzfzgnwsi5zc5jA== X-Google-Smtp-Source: ABdhPJxcne1Cug68p6O1gvazKjRXUyy2WzSgXSoDbhBy4lDwOSgLzOqI8pd6A1OU/UD++zvHGXxUew== X-Received: by 2002:a17:90a:9414:: with SMTP id r20mr528915pjo.222.1613593389107; Wed, 17 Feb 2021 12:23:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 39/71] tcg/tci: Improve tcg_target_call_clobber_regs Date: Wed, 17 Feb 2021 12:20:04 -0800 Message-Id: <20210217202036.1724901-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The current setting is much too pessimistic. Indicating only the one or two registers that are actually assigned after a call should avoid unnecessary movement between the register array and the stack array. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8d75482546..4dae09deda 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -623,8 +623,14 @@ static void tcg_target_init(TCGContext *s) tcg_target_available_regs[TCG_TYPE_I32] =3D BIT(TCG_TARGET_NB_REGS) - = 1; /* Registers available for 64 bit operations. */ tcg_target_available_regs[TCG_TYPE_I64] =3D BIT(TCG_TARGET_NB_REGS) - = 1; - /* TODO: Which registers should be set here? */ - tcg_target_call_clobber_regs =3D BIT(TCG_TARGET_NB_REGS) - 1; + /* + * The interpreter "registers" are in the local stack frame and + * cannot be clobbered by the called helper functions. However, + * the interpreter assumes a 64-bit return value and assigns to + * the return value registers. + */ + tcg_target_call_clobber_regs =3D + MAKE_64BIT_MASK(TCG_REG_R0, 64 / TCG_TARGET_REG_BITS); =20 s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613596188; cv=none; d=zohomail.com; s=zohoarc; b=kg1Mn8FryEVhZVtfBuyNmRXy4Q84TcZDGRxijFk756n+lYB7jL4e+BiDmTVZJKf1s/+Q1hQsdcSW2OQwFcrhseugs/3ETlhBfkVcYMnI+JUpWZOp+VZP7O641Wbrbe0abWKhGNjOve0i1wBsGusjuWq6M2+Oo3L2BBH6G1MhH3g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613596188; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LAWykP8xawhD0n2LEjnvxt6U+It9ZnMCGaTxxtC6jn0=; b=LyTBjywBeUcmFOaFttjolhTM0YbmHmQxRYSk9Ovy99sc0xuVAsQOGFsjBwh7Rb3eZvj//PujFeyz1c0mt/SUMchskOvah8aVVub0wU6Spo7Ly7jBdKLgLiwPR3SnSKalwrae4at8Lqbetru5ZSpzj3Eg6Mhu8OU60/6FFoysKQI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613596188532476.9533844756064; Wed, 17 Feb 2021 13:09:48 -0800 (PST) Received: from localhost ([::1]:48766 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCU4p-0005Tm-SK for importer@patchew.org; Wed, 17 Feb 2021 16:09:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33260) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTMO-0000tZ-Rl for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:23:44 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:36584) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTMN-0007ak-AS for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:23:44 -0500 Received: by mail-pj1-x1031.google.com with SMTP id gx20so2402839pjb.1 for ; Wed, 17 Feb 2021 12:23:42 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LAWykP8xawhD0n2LEjnvxt6U+It9ZnMCGaTxxtC6jn0=; b=RF/wS19OjYDrXX9MRqwQBBfr6rQ2B/b8VxyVB1k6E7/TQrYfhvWORXr1AkvU4DZuA2 NuY/u0OQGr0oi4qbV3JAC5m1lWFej+cQc1Fqd5cg/WjeTM0qTIvQ9nSqCyFVR6rC60+9 m4jzDSbvBcgpCoAZBTpLkRDOU/q6hXiJMBuzkVJw0lQDktvB5F2JZAf/gwtw0a3BcjwK wPnDzFfgKjL/0uKgzqzeaRWTgvBfhfUHLSO6yNIB2WKme4x3AtS+H6jvF+hSFiA80bkg fNtz0oGJxo87Ac3vuw9eyJGXN2e/Ay8t3S6jYK/IdQ5umiBbhHWG0WLUswjNnAkX1sJ5 tiFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LAWykP8xawhD0n2LEjnvxt6U+It9ZnMCGaTxxtC6jn0=; b=Ajx3uELMM5vHRagZWLFWY8PIFfhTt55DpfrRsgK5J1R3mMu37VIsNZI7hhy0bz3LVQ a8oEeFLTDgo9aK9tkilZWD8Y2su+9IsvbgFCrSmwckqgB87KXQ/WMJv4o/Mi+69BAVpv dkSY1c/mhk/Gp9ZOIKOqMagYPHjyd9nkI0UvkADhMylvtr88zBO6KrljabXCDOHwxxqo XHvyeMpcCAJBVEnaZGDl4TyGle66nRCA1rEeCbXv2tIgNybdnBtw60R7pbGZUl9x05o5 Dzz81pn2OQ/WvLT+AxBg9lx8+4FYzvNY4qRrLq07ejPtQrJDdQOuPWEXMbDbPEFXSNv4 I6ug== X-Gm-Message-State: AOAM532LwWtE2qbrsBp/TULf9EBH4c/4D0TeHHAE05i1olvbsIxVG8jN qIgatX+P+/xme1bFI82xwGR6E/RHpxGCYw== X-Google-Smtp-Source: ABdhPJzatcD9kgRVaKzzokgySVA3bPcqHirNRZnRFwyE9d0m7YwNHMF6IsCrkKpE7S0Iup2bXio5gA== X-Received: by 2002:a17:903:2093:b029:e3:790:81fe with SMTP id d19-20020a1709032093b02900e3079081femr974856plc.39.1613593421927; Wed, 17 Feb 2021 12:23:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 40/71] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Date: Wed, 17 Feb 2021 12:20:05 -0800 Message-Id: <20210217202036.1724901-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" As the only call-clobbered regs for TCI, these should receive the least priority. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 4dae09deda..53edc50a3b 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -170,8 +170,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcod= e op) } =20 static const int tcg_target_reg_alloc_order[] =3D { - TCG_REG_R0, - TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, TCG_REG_R4, @@ -186,6 +184,8 @@ static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, + TCG_REG_R1, + TCG_REG_R0, }; =20 #if MAX_OPC_PARAM_IARGS !=3D 6 --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613595288; cv=none; d=zohomail.com; s=zohoarc; b=SSFWtk+emwptRmsGeZThxmnTQ9RVq/H1BMz6tX1P98fbV2LyGvjN0rRRmaf1w7Uu0ON6pbWIuPFwf0wx74fiIf8WYn1SvhUZlGZQrTPqSahU9EjJqx+oEo673xLf5HDdJEWpBk8vrcg8IoWJ9bbHxdLC0ZFfRlgzFE9P3vIf16o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613595288; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=akuogNqTsRbdFKyineyOU7+0wNNNt+eZ2/k7lVk1LqY=; b=MHy7D84Glyej4QflL9W6IfGh+sczXNE35rRpF4T0CuQe+e7ir7hw4ld97zrfVkZmUVh9U1cIH1trqBd6Y/oxd+RB4KPGnVJN6VeuzlTqbG7EY0DITeeMhUZdc0lSe7s0LJ9gl0fGtesndCOEj2cx98hX6s6r6qxzxj5Co5ZH6eg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613595288375977.8740477069048; Wed, 17 Feb 2021 12:54:48 -0800 (PST) Received: from localhost ([::1]:39662 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTqR-0006IV-82 for importer@patchew.org; Wed, 17 Feb 2021 15:54:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33282) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTMQ-0000xx-M6 for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:23:46 -0500 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:43163) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTMO-0007b6-RW for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:23:46 -0500 Received: by mail-pf1-x432.google.com with SMTP id c11so9143115pfp.10 for ; Wed, 17 Feb 2021 12:23:44 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=akuogNqTsRbdFKyineyOU7+0wNNNt+eZ2/k7lVk1LqY=; b=raMcAiBmtMJDK7ZiSlDOHI2KrAo3JSbjWZ+jSM25rOEkM33vGZLcfa2qxvUk0xcaLS 76lwbzLvi65MdNAKJC27U7XfzYDJjYaHiBy/RMq7LmI2vQVr7LKrL1FbbpC356yLBJsn 1/ztYpRdRFMtFyTccYyUPyqd4VELKT918PfGLcZ9tj+vh+BLfcoTlQXAdeDIVpaR+nmS mh5VJhQbW+2ei2BQj6h8YT6E2HmqobKgVEMaAHInd4ie62vNpcoPkB9Vk3avjwwfXEZd ev2EWbLo34gutZjtZ1aj9ZgjF87TmGZjgIoEQoCOZfRg4lqrhO11lbiPKb9of/jDsWHd kaXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=akuogNqTsRbdFKyineyOU7+0wNNNt+eZ2/k7lVk1LqY=; b=GNWEQQa8uqGYOXgmFL+PBKEnW5/TjSqw6LlgV6qsdE2KFmcD1xF/MSJCOBBoxfkGgC kZKGfoIe/Ytxyoz+QdiZLW5Ho6R5TUPFFYuePvFPZSfnLM3y+rsGscgMtEwLr1QXugBN +tmOU1lD6dzIYMV8W/+2uN0sLJJYcqbvFLgxV44AB4romiv9b6Bj2hd1yE8fdrRfit0B 74Q5+uBStXy9AE7V/OjDa/RpF+fje+8Det6K31IRzIy+q5+p8bwXtP3tcB1LVr1IcEIQ ikGDff/QojVHrIYZ0rfocCGjGJxeQHliHqhkWgxam3T9OffK1t6dIp23/x3bEQUclkLm yddA== X-Gm-Message-State: AOAM530UO6pSDxWrhGnmowkUV/yqCF37tfzu4PGoFaTixziM8quNVgWe q1pSmU+YxMaenKSv544qIx3V7RnOii/uZg== X-Google-Smtp-Source: ABdhPJx1vYNhk7OuM5bT/RPcTVYvxbeGL88fgfUcx8QEL0YIWUsFzKcAl3yPOEFD/oC2wWf32dpURQ== X-Received: by 2002:a62:8fca:0:b029:1a9:39bc:ed37 with SMTP id n193-20020a628fca0000b02901a939bced37mr836135pfd.61.1613593423285; Wed, 17 Feb 2021 12:23:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 41/71] tcg/tci: Push opcode emit into each case Date: Wed, 17 Feb 2021 12:20:06 -0800 Message-Id: <20210217202036.1724901-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" We're about to split out bytecode output into helpers, but we can't do that one at a time if tcg_out_op_t is being done outside of the switch. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 53edc50a3b..050d514853 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -385,40 +385,48 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, { uint8_t *old_code_ptr =3D s->code_ptr; =20 - tcg_out_op_t(s, opc); - switch (opc) { case INDEX_op_exit_tb: + tcg_out_op_t(s, opc); tcg_out_i(s, args[0]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_goto_tb: tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); /* indirect jump method. */ + tcg_out_op_t(s, opc); tcg_out_i(s, (uintptr_t)(s->tb_jmp_target_addr + args[0])); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; set_jmp_reset_offset(s, args[0]); break; =20 case INDEX_op_br: + tcg_out_op_t(s, opc); tci_out_label(s, arg_label(args[0])); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(setcond) + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out8(s, args[3]); /* condition */ + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */ + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); tcg_out_r(s, args[4]); tcg_out8(s, args[5]); /* condition */ + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; #endif =20 @@ -436,10 +444,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, CASE_64(st32) CASE_64(st) stack_bounds_check(args[1], args[2]); + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_debug_assert(args[2] =3D=3D (int32_t)args[2]); tcg_out32(s, args[2]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(add) @@ -462,12 +472,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ + tcg_out_op_t(s, opc); { TCGArg pos =3D args[3], len =3D args[4]; TCGArg max =3D opc =3D=3D INDEX_op_deposit_i32 ? 32 : 64; @@ -481,13 +494,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, tcg_out8(s, pos); tcg_out8(s, len); } + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(brcond) + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out8(s, args[2]); /* condition */ tci_out_label(s, arg_label(args[3])); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ @@ -503,48 +519,59 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); tcg_out_r(s, args[4]); tcg_out_r(s, args[5]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; case INDEX_op_brcond2_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); tcg_out8(s, args[4]); /* condition */ tci_out_label(s, arg_label(args[5])); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; case INDEX_op_mulu2_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; #endif =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_st_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, *args++); tcg_out_r(s, *args++); if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { tcg_out_r(s, *args++); } tcg_out32(s, *args++); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: + tcg_out_op_t(s, opc); tcg_out_r(s, *args++); if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_out_r(s, *args++); @@ -554,9 +581,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, tcg_out_r(s, *args++); } tcg_out32(s, *args++); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_mb: + tcg_out_op_t(s, opc); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ @@ -565,7 +595,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, default: tcg_abort(); } - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg= 1, --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 84 +++++++++++++++++++--------------------- 1 file changed, 39 insertions(+), 45 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 050d514853..707f801099 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -283,32 +283,38 @@ static void stack_bounds_check(TCGReg base, target_lo= ng offset) } } =20 -static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg= 1, - intptr_t arg2) +static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, intptr_t i2) { uint8_t *old_code_ptr =3D s->code_ptr; =20 - stack_bounds_check(arg1, arg2); - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_op_t(s, INDEX_op_ld_i32); - tcg_out_r(s, ret); - tcg_out_r(s, arg1); - tcg_out32(s, arg2); - } else { - tcg_debug_assert(type =3D=3D TCG_TYPE_I64); -#if TCG_TARGET_REG_BITS =3D=3D 64 - tcg_out_op_t(s, INDEX_op_ld_i64); - tcg_out_r(s, ret); - tcg_out_r(s, arg1); - tcg_debug_assert(arg2 =3D=3D (int32_t)arg2); - tcg_out32(s, arg2); -#else - TODO(); -#endif - } + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_debug_assert(i2 =3D=3D (int32_t)i2); + tcg_out32(s, i2); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, + intptr_t offset) +{ + stack_bounds_check(base, offset); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_rrs(s, INDEX_op_ld_i32, val, base, offset); + break; +#if TCG_TARGET_REG_BITS =3D=3D 64 + case TCG_TYPE_I64: + tcg_out_op_rrs(s, INDEX_op_ld_i64, val, base, offset); + break; +#endif + default: + g_assert_not_reached(); + } +} + static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { uint8_t *old_code_ptr =3D s->code_ptr; @@ -444,12 +450,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, CASE_64(st32) CASE_64(st) stack_bounds_check(args[1], args[2]); - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_debug_assert(args[2] =3D=3D (int32_t)args[2]); - tcg_out32(s, args[2]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrs(s, opc, args[0], args[1], args[2]); break; =20 CASE_32_64(add) @@ -597,29 +598,22 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, } } =20 -static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg= 1, - intptr_t arg2) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, + intptr_t offset) { - uint8_t *old_code_ptr =3D s->code_ptr; - - stack_bounds_check(arg1, arg2); - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_op_t(s, INDEX_op_st_i32); - tcg_out_r(s, arg); - tcg_out_r(s, arg1); - tcg_out32(s, arg2); - } else { - tcg_debug_assert(type =3D=3D TCG_TYPE_I64); + stack_bounds_check(base, offset); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_rrs(s, INDEX_op_st_i32, val, base, offset); + break; #if TCG_TARGET_REG_BITS =3D=3D 64 - tcg_out_op_t(s, INDEX_op_st_i64); - tcg_out_r(s, arg); - tcg_out_r(s, arg1); - tcg_out32(s, arg2); -#else - TODO(); + case TCG_TYPE_I64: + tcg_out_op_rrs(s, INDEX_op_st_i64, val, base, offset); + break; #endif + default: + g_assert_not_reached(); } - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 707f801099..1e3f2c4049 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -283,6 +283,16 @@ static void stack_bounds_check(TCGReg base, target_lon= g offset) } } =20 +static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tci_out_label(s, l0); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -408,9 +418,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, break; =20 case INDEX_op_br: - tcg_out_op_t(s, opc); - tci_out_label(s, arg_label(args[0])); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_l(s, opc, arg_label(args[0])); break; =20 CASE_32_64(setcond) --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613595370; cv=none; d=zohomail.com; s=zohoarc; b=jfk/669ijuTc/QdIrzd3H2iZffVCiwm53xBuuYaayGVXoQkWCCtOqFIx7GTcaaSiGuIKGKXgNiRapQ4eqy6tk6bXvwfMkPknFh2bwIRDseRYizlQFTOuOb8BOJ4iGhF6myJ1htpo1fWGqKoP2nAGjtjdQaqUYvoxvko138aDTWQ= ARC-Message-Signature: i=1; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=06Y+cyMxl+dC1AQMaIsueXy7S/PiohsOvXqBqGkx3uw=; b=H4TMAZoXr8ESREzxfE/t8v2Hs3fkokNScYaye/B7hd0tlH2CVZX2ZO4VQXsTgYvKDC 4HB8QoMiBvS7txg9wbx13DmbZAPBCXT3Vj8YAbfWS96mKsKJNCarbEretqqOZ9MCoS2v AVdqsKhymfZXZygWSW5RE/iB+SFdcgYsrBGOaFYMLuxtBUXm7Yl/L2Q7/IjzICgQlZTw 9sXx0DtZ5qMjPOLN6V/8Vw8BUztxtvDST4bhSFdIVa26XeqN6/y7f4vu6kDMTUDN0uiY wMQ98TvVcHFBOYPAdrVzzS48zCTRxm+SL7CvK3780uB2mON2wJyP+xSLAROEawZnC3dR yPmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=06Y+cyMxl+dC1AQMaIsueXy7S/PiohsOvXqBqGkx3uw=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 1e3f2c4049..cb0cbbb8da 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -293,6 +293,16 @@ static void tcg_out_op_l(TCGContext *s, TCGOpcode op, = TCGLabel *l0) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_i(s, (uintptr_t)p0); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -403,17 +413,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, =20 switch (opc) { case INDEX_op_exit_tb: - tcg_out_op_t(s, opc); - tcg_out_i(s, args[0]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_p(s, opc, (void *)args[0]); break; =20 case INDEX_op_goto_tb: tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); /* indirect jump method. */ - tcg_out_op_t(s, opc); - tcg_out_i(s, (uintptr_t)(s->tb_jmp_target_addr + args[0])); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_p(s, opc, s->tb_jmp_target_addr + args[0]); set_jmp_reset_offset(s, args[0]); break; =20 --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Kpfe6JZmwXM15Cw7O9Ulgnnkm0DVoqv1s4+DGCwKajc=; b=sw3uO+4Pc571fxp22wc+dRQWWY/hHiIjpfm15qKE/kIViK6iyATF6i85Pzovx8wSu9 LuPRJLtJ9KwmXeBKKI/CDNiJTjpKKl1+FXJ9HQdH4fFz+xjfp9OjgNBI9otqw7F07EJh CEd+zdRffqp14ks4C7wT9LcGBrnpYKlaYz/3xfeaE/IEjnJibQqmGlMMvGIxxlLQYh3u Vr0KWo+ZwYVqvj1VexRl2xYisM6cRua/GP3wTOuHKjPHfXonPb6hXu4tTcKp4NFGFldP y8Ni61QzUBjkcwnljqiGsvgmxPnIli7ObNSQwPhkZ9DIMQ60E3jNy9bhvBU8y8umbW43 x51A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Kpfe6JZmwXM15Cw7O9Ulgnnkm0DVoqv1s4+DGCwKajc=; b=WQrpyatDh8GxCGq3IHNuqLj2avV2rleRAxLnKL7KkwBF4+7ygKJneS4UazbdnczksS lMLTqaOclBc3MuVzuvSYFRL6zJxdoUXtrPrcuyiys5pzZcoEm2AdMm9nHEyPWnWuHLkh 6nBa9YhRN53RT4/D4H8xEddPPSrs76eVYRJMyzJXlUR8ACcZ2w8mNzzpAAFnR1l2jg8T qXNkkwBFS/j9bFqwfRKryzR1x0SW0stqMhD/nJeyQGEPh7j2is9VeG9yLXlLwCbX5Swn zS8i0wTpeHBc+YWSoZJgA/InPrpmf8Qetq5D1TdvGhOBImBEsNoWFFihECllryCmh5AM Kt1g== X-Gm-Message-State: AOAM530w7KrJzHeRn83zZR8YROiflkrHhijljV1sdzZOed9euvbYbkOL iGWGkX8yt+ifkEn0mRt/RyVMmeb1m1VcWA== X-Google-Smtp-Source: ABdhPJwcTtayNtf9uEq34bk4iJL3bHwt3t7fCsVwRF81N6Lh+IvsK/Hdl6tzzKHzaZoTJvWXqJvexA== X-Received: by 2002:a17:90a:ee96:: with SMTP id i22mr514322pjz.157.1613593428986; Wed, 17 Feb 2021 12:23:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 45/71] tcg/tci: Split out tcg_out_op_rr Date: Wed, 17 Feb 2021 12:20:10 -0800 Message-Id: <20210217202036.1724901-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" At the same time, validate the type argument in tcg_out_mov. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index cb0cbbb8da..272e3ca70b 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -303,6 +303,17 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, = void *p0) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -337,16 +348,18 @@ static void tcg_out_ld(TCGContext *s, TCGType type, T= CGReg val, TCGReg base, =20 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { - uint8_t *old_code_ptr =3D s->code_ptr; - tcg_debug_assert(ret !=3D arg); -#if TCG_TARGET_REG_BITS =3D=3D 32 - tcg_out_op_t(s, INDEX_op_mov_i32); -#else - tcg_out_op_t(s, INDEX_op_mov_i64); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_rr(s, INDEX_op_mov_i32, ret, arg); + break; +#if TCG_TARGET_REG_BITS =3D=3D 64 + case TCG_TYPE_I64: + tcg_out_op_rr(s, INDEX_op_mov_i64, ret, arg); + break; #endif - tcg_out_r(s, ret); - tcg_out_r(s, arg); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + default: + g_assert_not_reached(); + } return true; } =20 @@ -534,10 +547,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rr(s, opc, args[0], args[1]); break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613596396; cv=none; d=zohomail.com; s=zohoarc; b=lUN5Fg7JFRAb0PNrTtY/za32AIU3oqc9DCWidZgX4X1VXvgPMv+EukwSLramspDl4eBcFIAbCgGwrxcvKwtkQ+c3WnpStjaM2Fq+/eDRss1BhUudQ9ZgA5rkDQ224GOXsG5U4wg84nougvzFIrWuT0Lfx11RQ8LwScuKIsX4oNw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613596396; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RzFAVc3cWW3yr0pGO36GqM64ymG+VJfs9mt8bjfFgIQ=; b=kAjMAAUrU8NNM/rdL+gH+3OiAZAcTx2sJWSm7754z92vCjOB39/ggllZCKCNrx8GKRtVZDkXoPqsYYQJQ6eeAYoNBQj2c1Hhsg3g6JL+CXlcLWtFo7iQSbnuyaUQzHsDImUesH3ypz7jsNA2+OkyqNw6ggGRqeZbm+oiEx3DE0M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613596395610488.8393653135761; Wed, 17 Feb 2021 13:13:15 -0800 (PST) Received: from localhost ([::1]:57114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCU8I-0000mh-JC for importer@patchew.org; Wed, 17 Feb 2021 16:13:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33346) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTMX-0001Bp-6b for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:23:53 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:50472) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTMV-0007dF-KL for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:23:52 -0500 Received: by mail-pj1-x1032.google.com with SMTP id cl8so2153109pjb.0 for ; Wed, 17 Feb 2021 12:23:51 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RzFAVc3cWW3yr0pGO36GqM64ymG+VJfs9mt8bjfFgIQ=; b=VhbggrppflsZjzAuM1zhjdtndIJqk9zecFP2kBash6OLagSrTzKfpr1mYEwxn89Xhp 6fhsSrYJ14L/tJLtuRLMWEip42AoDHmyuX9uFwhqlxfnnCDegQaRpLifmNUM7eazQczV I6WZkhK5pK5Zw5Iz8sgaViP9VsWHmqEiLuiDmHED1IcVUI1ADIKpeEjMO7gspRzFtjJ2 XfFZ6eX13DfZK8dyVP6W2Gicu1yhB+XE/Vx3aMBFWW4DtPhxw6ZpPv3p0mruQdyqnrmO sYbRJz+n0RdmbSnBCE8LVRwHX4F2SyR229wIbTZ0IuZvVwRubHTStZ4g1GBsIzUPg5zQ F2Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RzFAVc3cWW3yr0pGO36GqM64ymG+VJfs9mt8bjfFgIQ=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 272e3ca70b..546424c2bd 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -314,6 +314,19 @@ static void tcg_out_op_rr(TCGContext *s, TCGOpcode op,= TCGReg r0, TCGReg r1) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -500,11 +513,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrr(s, opc, args[0], args[1], args[2]); break; =20 CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 546424c2bd..5848779208 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -341,6 +341,20 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out8(s, c3); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, intptr_t offset) { @@ -454,12 +468,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, break; =20 CASE_32_64(setcond) - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out8(s, args[3]); /* condition */ - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrc(s, opc, args[0], args[1], args[2], args[3]); break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A8+oxGont/+bDGkQ3AaEp3aS+SzJCnRbYSKjy2ImL7Q=; b=q7cKT6OxTrpZSsoYOU/LRNJ8BKlZ5FGXjNtyFBA55FT1zGZtTQkwdU+5i4cgiOoDi3 AC5NGfLid6no1tYiyaHZPyrejCJPdBVE8ovyfPwplrfCNzM7LIRlPH4xzX624frUQ0h4 YA6T7utKPz1Iyc6M8UGE/SOMb2q0Wyu3yPyh7dCZAgUx9clZUX+tCVcSsB/nfOb7hYX/ tB4CNg49thvBNoAxLlH4Qgdd6b6nM3r54tqZwcUW7cL1T0VbJFaTe2DO80Lqn1oIb7dG h8JNXCYMrhLxq9BT109oTn44HexyQpQZQK89ruFbLb/C49Mi2ZKFthCJWSmbKo+CXej/ dDtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A8+oxGont/+bDGkQ3AaEp3aS+SzJCnRbYSKjy2ImL7Q=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 5848779208..8eda159dde 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -355,6 +355,25 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 +static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, + TCGReg r3, TCGReg r4, TCGCond c5) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out_r(s, r4); + tcg_out8(s, c5); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} +#endif + static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, intptr_t offset) { @@ -473,15 +492,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, =20 #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: - /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */ - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - tcg_out_r(s, args[4]); - tcg_out8(s, args[5]); /* condition */ - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrrrc(s, opc, args[0], args[1], args[2], + args[3], args[4], args[5]); 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6fN3MzHzuWIrC3R6bdCZxAnV3xyNnPemffGo42IAOp8=; b=ZLdZVS51kAwmDH4cPjd+xNZnIyo8PIRrScTOEaPTgsJk0FucV2v8Cxu6ebICCTYSeU mpscy+3N1gnizzes8ajqTCV3r+bNbD39r1CQ1MWcX/CLrK/fdW8kyQLPjDdVdcLugjM1 MB03WaZi34GgzUHtT8tzAMkN0ENQzHyY2zsRxLH7B9pw35skFPWttM3HjMKfCXMMS/FR dpLuM7n+liyK06ZLQ4uDbd/jE+i5+IMGPfn79WP9YR0W+0Oz/XNw/F5L029YZqOqd14D 2bub2N50hpxAMDZWin0Ba3piP4LAKKnmfYxEKN9Y+yZjovoa1arusXZ0Adbk2Ba/k05+ LjiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6fN3MzHzuWIrC3R6bdCZxAnV3xyNnPemffGo42IAOp8=; b=TPFZdp4rnFs1Bf8dQ2UGr0ZOhKhY21ma/ljrIfWtn5jWDsp15sRX+X0ucYtUdzoAI8 G9tPLr/j9/P/hyHnIDecYbjgiBiWwCxuJX0nX+k9DNOAhOSR5kyoixCPPlxUsrE7ntsI IpExNX+sDqu/86xW33ddXBQvCeFI908aZS8jU6ySCozBPqvYn/Kl5RohyCNAcd1sxBPb XBJ44t1ByZ1RzDpdN8mRBJO/HyeW8NY5ZRB6NbOzR2KKY2Y4b6LxwOOscOT5jzpux2Kw SM/P+sE8z+Tt6ktHN4nY6XEeYEmetz7YuyLTRlw8fgINuh24ebc+cveoliWLoomyG+oX RkiQ== X-Gm-Message-State: AOAM530ccqJnr8fPcLU2x1QsVzBIP5rfmq978Vg4+Fy8mRhAhmN11isV yW0XnMF2wNWzV6V8y9W/2eUWLdLxpJ1dXg== X-Google-Smtp-Source: ABdhPJxgOyPSMgcrMakTahGZJed654EMl4d1AFPFsSxp3CUivrBFMtUR2U9sU1AeJyA5pC5jjGJ3XQ== X-Received: by 2002:a17:90a:4dc1:: with SMTP id r1mr589123pjl.12.1613593435042; Wed, 17 Feb 2021 12:23:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 49/71] tcg/tci: Split out tcg_out_op_rrrbb Date: Wed, 17 Feb 2021 12:20:14 -0800 Message-Id: <20210217202036.1724901-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8eda159dde..6c743a8fbd 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -355,6 +355,21 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out8(s, b3); + tcg_out8(s, b4); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + #if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, @@ -538,7 +553,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, break; =20 CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ - tcg_out_op_t(s, opc); { TCGArg pos =3D args[3], len =3D args[4]; TCGArg max =3D opc =3D=3D INDEX_op_deposit_i32 ? 32 : 64; @@ -546,13 +560,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, tcg_debug_assert(pos < max); tcg_debug_assert(pos + len <=3D max); =20 - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out8(s, pos); - tcg_out8(s, len); + tcg_out_op_rrrbb(s, opc, args[0], args[1], args[2], pos, len); } - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(brcond) --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613595730; cv=none; d=zohomail.com; s=zohoarc; b=RvoTBFYSBpKp2LneouR0olbEZSKTC25evzdGbNAZ1dpBlqvRtV0He74cXnX1dhKZqjZNLz4NQ7tU5zPwzT/XeBa+FHXg1w2zFeOwO+AkPREciFa0CgwJ2dcW8dbTJfUvLMh+4e2YhmkiXOuHy8Qw9XcGOG0BXY3/SlW45+3pBfQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613595730; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=p6E9LDuPBslW5lnZ+lbP25axObg1A1JUNAlm8q5oVbA=; b=kp8iSvhY3lQNugXHcHvtHpRotPZaxUa408k5/aOqICiG3Yu7dxEWDpOR+17S3jfRWA3F0Q3B/pFQAqdDuK04yP4YMxcZb03aNxB6JGJjgEG7XjCtfo4F86JvjoueMau2h9C+9gqvYV1zt+tFAJqEaaR1jWkKdzGH18tdXwT3dxw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613595730329145.88796630251284; Wed, 17 Feb 2021 13:02:10 -0800 (PST) Received: from localhost ([::1]:56892 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCTxY-00055M-ON for importer@patchew.org; Wed, 17 Feb 2021 16:02:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33438) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTMd-0001Pp-Hh for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:23:59 -0500 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:36252) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTMc-0007fL-2A for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:23:59 -0500 Received: by mail-pg1-x536.google.com with SMTP id t26so9228207pgv.3 for ; Wed, 17 Feb 2021 12:23:57 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=p6E9LDuPBslW5lnZ+lbP25axObg1A1JUNAlm8q5oVbA=; b=EClC1AzBeHyf2FEDiEOQOKgZL7ej1kn4Hi+/sv7hVboSU4/4tBxuPCL/4X5oJEKCbJ 3yiDw2qWW+ONnewSwN00E90qNJpYViYcQ8/38eSYQIq7aDgKSjX/B1jyQdfjwUwcnqAn cyCmQqGtdY6LOS3fPk2F2L+5LQppRk38gTm4boSpPkFAmBg3zAcBX38lLL3vVr53iLtF /IBcQDe2cF+qxhqX1hVB/p7APaV15Dd5nIdkdupm5OXPvW/XRUXpH0hsjLgxJqInWnga NV8wxE+TSFdJBVh3f+sDTLnHen4cU9sYi/xGU+56lz/hpseqt86Ah6r4/CDp/qdpgRyv 5chA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=p6E9LDuPBslW5lnZ+lbP25axObg1A1JUNAlm8q5oVbA=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 6c743a8fbd..8cc63124d4 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -341,6 +341,20 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrcl(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGCond c2, TCGLabel *l3) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out8(s, c2); + tci_out_label(s, l3); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { @@ -565,12 +579,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, break; =20 CASE_32_64(brcond) - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out8(s, args[2]); /* condition */ - tci_out_label(s, arg_label(args[3])); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrcl(s, opc, args[0], args[1], args[2], arg_label(args[= 3])); break; =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8cc63124d4..f7595fbd65 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -401,6 +401,23 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode= op, =20 old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } + +static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, + TCGReg r3, TCGReg r4, TCGReg r5) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out_r(s, r4); + tcg_out_r(s, r5); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} #endif =20 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, @@ -601,14 +618,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - tcg_out_r(s, args[4]); - tcg_out_r(s, args[5]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2], + args[3], args[4], args[5]); break; case INDEX_op_brcond2_i32: tcg_out_op_t(s, opc); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f7595fbd65..c2bbd85130 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -385,6 +385,20 @@ static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode = op, TCGReg r0, } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 +static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) @@ -632,12 +646,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; case INDEX_op_mulu2_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); break; #endif =20 --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c2bbd85130..fb4aacaca3 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -399,6 +399,23 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrrcl(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, + TCGCond c4, TCGLabel *l5) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out8(s, c4); + tci_out_label(s, l5); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) @@ -636,14 +653,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, args[3], args[4], args[5]); break; case INDEX_op_brcond2_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - tcg_out8(s, args[4]); /* condition */ - tci_out_label(s, arg_label(args[5])); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrrcl(s, opc, args[0], args[1], args[2], + args[3], args[4], arg_label(args[5])); break; case INDEX_op_mulu2_i32: tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613596110933112.2757578363279; Wed, 17 Feb 2021 13:08:30 -0800 (PST) Received: from localhost ([::1]:45652 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCU3h-00049N-Pt for importer@patchew.org; Wed, 17 Feb 2021 16:08:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33522) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTMj-0001cu-8c for qemu-devel@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 70 ++++++++++++++++++++++++++++++---------- 1 file changed, 53 insertions(+), 17 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index fb4aacaca3..f93772f01f 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -314,6 +314,19 @@ static void tcg_out_op_rr(TCGContext *s, TCGOpcode op,= TCGReg r0, TCGReg r1) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrm(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGArg m2) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out32(s, m2); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2) { @@ -369,6 +382,20 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrm(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGArg m3) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out32(s, m3); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4) { @@ -384,6 +411,21 @@ static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode = op, TCGReg r0, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrrm(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, TCGReg r2, TCGReg r3, TCGArg m4) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out32(s, m4); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + #if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) @@ -663,29 +705,23 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_st_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, *args++); - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); + } else { + tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); } - tcg_out32(s, *args++); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: - tcg_out_op_t(s, opc); - tcg_out_r(s, *args++); - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_r(s, *args++); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); + } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); + } else { + tcg_out_op_rrrrm(s, opc, args[0], args[1], + args[2], args[3], args[4]); } - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out32(s, *args++); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_mb: --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f93772f01f..eeafec6d44 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -303,6 +303,15 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, = void *p0) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_v(TCGContext *s, TCGOpcode op) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { uint8_t *old_code_ptr =3D s->code_ptr; @@ -587,8 +596,6 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_= unit *arg) static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { - uint8_t *old_code_ptr =3D s->code_ptr; - switch (opc) { case INDEX_op_exit_tb: tcg_out_op_p(s, opc, (void *)args[0]); @@ -725,8 +732,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, break; =20 case INDEX_op_mb: - tcg_out_op_t(s, opc); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_v(s, opc); break; =20 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kQwYPaxcLPGVIBaZFpt4Ukjta9EglPQhHZw+11ye7O8=; b=VqjdErixzb6CV2VBQk8tapBPYmngSWE1MtinsyfRLzo8ZyIS8cz8ajVghhUaui/qmP xZ5C8COoUWmWnuQtYxyS0hdgWyLfbDpwYn6aawVYa7IHnRNVv/sDi5SyDWGl8ObG6Syk l2cIL+7yuid12XkOml/ApP+Ukl6tZVujS3zBCG8cP5kBVkhR/AFVVYWFSZPHSWHzrqWi Lia1Fj2LjW682v+LElmMAfo9gAK2VrNTmSsgEhgfuAIsbF4tex95yotUJcRH0SKvjOwA c0/LnRuF7LjulF4QZKZ3LrFQU2oBbyz95mi6lGzT8VzVuDxc72ITK+qxH++c0EBkApPY vLDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kQwYPaxcLPGVIBaZFpt4Ukjta9EglPQhHZw+11ye7O8=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index eeafec6d44..e4a5872b2a 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -312,6 +312,18 @@ static void tcg_out_op_v(TCGContext *s, TCGOpcode op) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_np(TCGContext *s, TCGOpcode op, + uint8_t n0, const void *p1) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out8(s, n0); + tcg_out_i(s, (uintptr_t)p1); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { uint8_t *old_code_ptr =3D s->code_ptr; @@ -561,7 +573,6 @@ static void tcg_out_movi(TCGContext *s, TCGType type, =20 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { - uint8_t *old_code_ptr =3D s->code_ptr; const TCGHelperInfo *info; uint8_t which; =20 @@ -574,11 +585,8 @@ static void tcg_out_call(TCGContext *s, const tcg_insn= _unit *arg) tcg_debug_assert(info->cif->rtype->size =3D=3D 8); which =3D 2; } - tcg_out_op_t(s, INDEX_op_call); - tcg_out8(s, which); - tcg_out_i(s, (uintptr_t)info); =20 - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_np(s, INDEX_op_call, which, info); } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nbzdCRnUzVvHAlHdm0W/U/kL5Ps02KKsV67u0VtR3Rc=; b=ER/NplcnuZ/Yrth49dhkpkbWSVRyZZF0DnQg5xki9M77awBu1/OeVjdiPg67QwZdBl eI9HYY3PQDLmIUSKVl3FJHxre6UWWaYxQnvFARTN/J0rht87OPC64mUbzYJIMyYfOVHn UzfTPDEWA5nucUT7OHdqKpBs1acV1PVriNt9BZu4TZkx/22uaqJHmDnpv6SYsQiKf6q2 FXpQPJ9VPmpa6cNXtePQsu6v4H9GCAbVwmN24nTOiTmgYmv2hczECCImBQBdCZRWvc7K 3ytmZGSQrHk4sHdJ/vZHUdQBzmaucUZX0dtE3mgGV3q94bHnJAXdhJuemZXoKjEIRGSD LEhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nbzdCRnUzVvHAlHdm0W/U/kL5Ps02KKsV67u0VtR3Rc=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 50 ++++++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 15 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index e4a5872b2a..c2d2bd24d7 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -324,6 +324,31 @@ static void tcg_out_op_np(TCGContext *s, TCGOpcode op, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t = i1) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out32(s, i1); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + +#if TCG_TARGET_REG_BITS =3D=3D 64 +static void tcg_out_op_rI(TCGContext *s, TCGOpcode op, + TCGReg r0, uint64_t i1) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out64(s, i1); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} +#endif + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { uint8_t *old_code_ptr =3D s->code_ptr; @@ -550,25 +575,20 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, = TCGReg ret, TCGReg arg) } =20 static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg t0, tcg_target_long arg) + TCGReg ret, tcg_target_long arg) { - uint8_t *old_code_ptr =3D s->code_ptr; - uint32_t arg32 =3D arg; - if (type =3D=3D TCG_TYPE_I32 || arg =3D=3D arg32) { - tcg_out_op_t(s, INDEX_op_tci_movi_i32); - tcg_out_r(s, t0); - tcg_out32(s, arg32); - } else { - tcg_debug_assert(type =3D=3D TCG_TYPE_I64); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_ri(s, INDEX_op_tci_movi_i32, ret, arg); + break; #if TCG_TARGET_REG_BITS =3D=3D 64 - tcg_out_op_t(s, INDEX_op_tci_movi_i64); - tcg_out_r(s, t0); - tcg_out64(s, arg); -#else - TODO(); + case TCG_TYPE_I64: + tcg_out_op_rI(s, INDEX_op_tci_movi_i64, ret, arg); + break; #endif + default: + g_assert_not_reached(); } - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613596405; cv=none; d=zohomail.com; s=zohoarc; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=j84CVB2/9NSVvHC05jyj/ExvjNOevKnlsYLw94URCgw=; b=vEpWI1fy0sP0JYLo83buVsTAoViHBAOeXv8X6MuaAUp/MFUDs9QO92JNZ7qruRFI1q WWqD3X/i02OBTADliHCrl/bHQyWPSz9PCpuVOlVY30/rp9e5y8tjr2jEsfSe6Y86qn0s +jUG4wNpKfF0rbOyuj8fxgKe//8hUIsFhg6T4AY0JZJUWjoU/f4BFPvOoFBcFdUvnv4S LcbfR0T+PfJ1XFxXH4AbWL1Mp6L4GnqLG/7oBauCpEPquLCe07r99um5X/Caf2RYPQUZ S1YpN2lB1H1H2C3DCXf6pbRPBnYG1fH5FcDyFVZIw+itgdt4OM128vKf+FrpmkLqS7fG uIcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j84CVB2/9NSVvHC05jyj/ExvjNOevKnlsYLw94URCgw=; b=a36UetQt4Rl9fJIBc9BqBeeb8usBw4rsKJusks7SPs+lv+sHPSzj5DCqBDX0K8QN2R m+UakEN+aJHoP81L0ohiaBshx6zAU1Eu4qqi6lrbrxdy9Fn48H0TuOE2XLgScmRL7/vl tKxRZht+4hl5Un5MK73zj5AL7xZmp1ORewhZP1HgBfFv5FeaVsl5Hb2siqYM+0kqZDzK a+Z0SUrhOwKPfKkVY+kSQb72+J6HJjvy9J0nEzgXJlr9O02+rlICIsBAAEHPPmjS+vw4 Mwdz3Igtay3RV88WoZqGu7+lNI3lMKzkdGg7gh9ij/wYMcB0T8VmJTiD7pZHkXIc5k/Y Z+Nw== X-Gm-Message-State: AOAM532nxuIGRy2uX4ovUePEIH59ePIV7LHGDpm6rtbjrKT31YxLCgip E2hqWECihcXWKEalcx91oHfV6pXv/jgFqQ== X-Google-Smtp-Source: ABdhPJwmkWRg/gQ7T9xCkjK8VH2dzJrPmDxpSZQI0skCTuwEQBcNHCxpiPl1CZ+aII2WM87f/UJVSA== X-Received: by 2002:a17:90a:1082:: with SMTP id c2mr524226pja.183.1613593448216; Wed, 17 Feb 2021 12:24:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 58/71] tcg/tci: Reserve r13 for a temporary Date: Wed, 17 Feb 2021 12:20:23 -0800 Message-Id: <20210217202036.1724901-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" We're about to adjust the offset range on host memory ops, and the format of branches. Both will require a temporary. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 1 + tcg/tci/tcg-target.c.inc | 1 + 2 files changed, 2 insertions(+) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 4df10e2e83..1558a6e44e 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -155,6 +155,7 @@ typedef enum { TCG_REG_R14, TCG_REG_R15, =20 + TCG_REG_TMP =3D TCG_REG_R13, TCG_AREG0 =3D TCG_REG_R14, TCG_REG_CALL_STACK =3D TCG_REG_R15, } TCGReg; diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c2d2bd24d7..b29e75425d 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -829,6 +829,7 @@ static void tcg_target_init(TCGContext *s) MAKE_64BIT_MASK(TCG_REG_R0, 64 / TCG_TARGET_REG_BITS); =20 s->reserved_regs =3D 0; + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); =20 /* The call arguments come first, followed by the temp storage. */ --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613596326425937.3593261713655; Wed, 17 Feb 2021 13:12:06 -0800 (PST) Received: from localhost ([::1]:54052 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCU7B-0007qQ-9X for importer@patchew.org; Wed, 17 Feb 2021 16:12:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33654) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTMs-0001u5-Ks for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:24:14 -0500 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:38741) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTMo-0007jd-So for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:24:14 -0500 Received: by mail-pg1-x529.google.com with SMTP id m2so9218425pgq.5 for ; Wed, 17 Feb 2021 12:24:10 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xVPJpsDWn13Ikd2YVdvJyZUJO3co9ndv44w3DFxxxYY=; b=n5JhAdaoCpZs4UIrCwZfG25PPl6Q7GwnWdHx0QqnhHDdGinjc2k8n5bpIGWsiRWSUV 9qKStwKk933xK66ELC/oMrWWvHxZFbaKDbgWreoQYibDVT2GS41pWdi1Kdez6PZPSDA8 6aVAvmppcFlWNhDaohvNzP9FAqMT6HE7TrOmLdU/qZQjLDlDMBxZqNnD0wenlOuClyFr 0saH6EvVU4kC1QkhGOBeTb/FQPBzc5AbfdeT9qRvHOAMWCYV+PGDEtV2eYiHCrXqmpgh hPTZyTZHUpCQ2vfsfVPJlsKsMBuFMu0+8vfPd/PN56FT3TrXaf+7YCYWLDUm0WzUHedj +TUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xVPJpsDWn13Ikd2YVdvJyZUJO3co9ndv44w3DFxxxYY=; b=mogDaoAufK7TFvFVB5L4crtNjAcAj+BrFpbPbn/nZnJRW3LSM3h4rJ77R3OjmGvjym YOop/WiJUFLAUq40Gq+aAN2WpfvQPICt8RTFt675UEMxkD0Ce9M2Aq4yZ91aeJqMmg4G IfTdC0Q2UT49SrNLVfb9efrhkwQkf9hlgj9C8T/Ml3YGoObgRpgItDFAUmeJxB0XQmsL +blCvfANO2ZID4CMGC/fUI1l6hqUmbE+BQnTNi+K0mVkbqLmmCR/IKogPrMFeefCaXqa ldAh6V0qua8JR4eTb4Fpzh82gSKF5zmiGEpYOoXhsCkf3Uyc3QOS6T5m9o3Bl17Vcie0 rpaw== X-Gm-Message-State: AOAM530kbtNWUGOkN71C5ikxdFRM+qnosMbk9q1tmFLNaRI/12gEjxY0 N4E9DM3CFX+6Nl4gz6bcltlo2ToDJ/snEg== X-Google-Smtp-Source: ABdhPJzJJEXDtRy4uysYa+S7pGFRqSLiZVsvtFU+5wrsohdRSz5eAQhJ4ENekYnAlE/+b4gJdTN7Rw== X-Received: by 2002:aa7:9e82:0:b029:1ec:c566:50b2 with SMTP id p2-20020aa79e820000b02901ecc56650b2mr989607pfq.22.1613593449589; Wed, 17 Feb 2021 12:24:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 59/71] tcg/tci: Emit setcond before brcond Date: Wed, 17 Feb 2021 12:20:24 -0800 Message-Id: <20210217202036.1724901-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The encoding planned for tci does not have enough room for brcond2, with 4 registers and a condition as input as well as the label. Resolve the condition into TCG_REG_TMP, and relax brcond to one register plus a label, considering the condition to always be reg !=3D 0. Signed-off-by: Richard Henderson --- tcg/tci.c | 68 ++++++++++------------------------------ tcg/tci/tcg-target.c.inc | 52 +++++++++++------------------- 2 files changed, 35 insertions(+), 85 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 5718fc42a6..3f8c6a0291 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -141,6 +141,16 @@ static void tci_args_nl(const uint8_t **tb_ptr, uint8_= t *n0, void **l1) check_size(start, tb_ptr); } =20 +static void tci_args_rl(const uint8_t **tb_ptr, TCGReg *r0, void **l1) +{ + const uint8_t *start =3D *tb_ptr; + + *r0 =3D tci_read_r(tb_ptr); + *l1 =3D (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); +} + static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { @@ -212,19 +222,6 @@ static void tci_args_rrs(const uint8_t **tb_ptr, check_size(start, tb_ptr); } =20 -static void tci_args_rrcl(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3) -{ - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *c2 =3D tci_read_b(tb_ptr); - *l3 =3D (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); -} - static void tci_args_rrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { @@ -293,21 +290,6 @@ static void tci_args_rrrr(const uint8_t **tb_ptr, check_size(start, tb_ptr); } =20 -static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, - TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) -{ - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *r3 =3D tci_read_r(tb_ptr); - *c4 =3D tci_read_b(tb_ptr); - *l5 =3D (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); -} - static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) { @@ -713,8 +695,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i32: - tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); - if (tci_compare32(regs[r0], regs[r1], condition)) { + tci_args_rl(&tb_ptr, &r0, &ptr); + if ((uint32_t)regs[r0]) { tb_ptr =3D ptr; } break; @@ -731,15 +713,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, T2 =3D tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; - case INDEX_op_brcond2_i32: - tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr); - T1 =3D tci_uint64(regs[r1], regs[r0]); - T2 =3D tci_uint64(regs[r3], regs[r2]); - if (tci_compare64(T1, T2, condition)) { - tb_ptr =3D ptr; - continue; - } - break; case INDEX_op_mulu2_i32: tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); @@ -867,8 +840,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i64: - tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); - if (tci_compare64(regs[r0], regs[r1], condition)) { + tci_args_rl(&tb_ptr, &r0, &ptr); + if (regs[r0]) { tb_ptr =3D ptr; } break; @@ -1178,9 +1151,9 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr); - info->fprintf_func(info->stream, "%-12s %s,%s,%s,%p", - op_name, str_r(r0), str_r(r1), str_c(c), ptr); + tci_args_rl(&tb_ptr, &r0, &ptr); + info->fprintf_func(info->stream, "%-12s %s,0,ne,%p", + op_name, str_r(r0), ptr); break; =20 case INDEX_op_setcond_i32: @@ -1305,13 +1278,6 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) str_r(r3), str_r(r4), str_c(c)); break; =20 - case INDEX_op_brcond2_i32: - tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &c, &ptr); - info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%p", - op_name, str_r(r0), str_r(r1), - str_r(r2), str_r(r3), str_c(c), ptr); - break; - case INDEX_op_mulu2_i32: tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index b29e75425d..e06d4e9380 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -349,6 +349,17 @@ static void tcg_out_op_rI(TCGContext *s, TCGOpcode op, } #endif =20 +static void tcg_out_op_rl(TCGContext *s, TCGOpcode op, TCGReg r0, TCGLabel= *l1) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tci_out_label(s, l1); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { uint8_t *old_code_ptr =3D s->code_ptr; @@ -400,20 +411,6 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 -static void tcg_out_op_rrcl(TCGContext *s, TCGOpcode op, - TCGReg r0, TCGReg r1, TCGCond c2, TCGLabel *l3) -{ - uint8_t *old_code_ptr =3D s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out8(s, c2); - tci_out_label(s, l3); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; -} - static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { @@ -487,23 +484,6 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 -static void tcg_out_op_rrrrcl(TCGContext *s, TCGOpcode op, - TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, - TCGCond c4, TCGLabel *l5) -{ - uint8_t *old_code_ptr =3D s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out8(s, c4); - tci_out_label(s, l5); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; -} - static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) @@ -704,7 +684,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, break; =20 CASE_32_64(brcond) - tcg_out_op_rrcl(s, opc, args[0], args[1], args[2], arg_label(args[= 3])); + tcg_out_op_rrrc(s, (opc =3D=3D INDEX_op_brcond_i32 + ? INDEX_op_setcond_i32 : INDEX_op_setcond_i64), + TCG_REG_TMP, args[0], args[1], args[2]); + tcg_out_op_rl(s, opc, TCG_REG_TMP, arg_label(args[3])); break; =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ @@ -730,8 +713,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, args[3], args[4], args[5]); break; case INDEX_op_brcond2_i32: - tcg_out_op_rrrrcl(s, opc, args[0], args[1], args[2], - args[3], args[4], arg_label(args[5])); + tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, TCG_REG_TMP, + args[0], args[1], args[2], args[3], args[4]); + tcg_out_op_rl(s, INDEX_op_brcond_i32, TCG_REG_TMP, arg_label(args[= 5])); break; case INDEX_op_mulu2_i32: tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613596707; cv=none; d=zohomail.com; s=zohoarc; b=SJi8HzVQqTuLbzjpQrWBo8325x4Tc/TzqnxthvEUyJulXfE0NizmXQlj8HcTv9hF4GlD3/zJyCySP/m7lIV4rRakJEQNkxTIDPLoqAcoSunJ2xsCa7S4tkwTELELj0e8szQ2iUc7Zlsc8KgTp4ky/DqyQ5U8r4JB/mvlw37dYeM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613596707; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Oqjirx8sUQyYnS7vrLSDlLS9gocI/IN6++5opPveqXM=; b=DtOxPjI2/j3mkg6aIJZjMB4oi9yCFC9mW3QK/vRvNjLnc19dCw08R0aOHPXoNOfnzklbd1XEBJkW/DKtY75/+zfutPdmfDqbC1Dkmjun30ERWNflRF6TB4HRN9f+/7boqyZqVi9vcHVbnHDfuOLOBHsbnQkRrdoSIhUB+pxrchc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613596706946962.5437381693167; Wed, 17 Feb 2021 13:18:26 -0800 (PST) Received: from localhost ([::1]:45358 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCUDJ-0007uy-L5 for importer@patchew.org; Wed, 17 Feb 2021 16:18:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33656) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTMs-0001uH-Ty for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:24:15 -0500 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:42724) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTMq-0007jo-12 for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:24:14 -0500 Received: by mail-pg1-x52b.google.com with SMTP id o38so9194945pgm.9 for ; Wed, 17 Feb 2021 12:24:11 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Oqjirx8sUQyYnS7vrLSDlLS9gocI/IN6++5opPveqXM=; b=tRZfwSOtuKbty8uaE1wPHZMbhxFhsKeVVxaEdHXf0Tz6SGWx9LNPFDCdB5A3XcWxg0 P3dfNpYg8EQT7Q+mgNjYkhAPl6fY6JpYxbQiJ3yy8Wvfjq+Re37IqBY7Jh1IR5E0Udnl jytXNmC/DN/wq0FE3r8RzbRpUkIgN4mY1wmyMJ2j7nlI2fRA8LqI/KnFZlpSDv6HC6DO hDyGwcZiEv+vn1q0GBbURyOWFH5Z3YPfqsBOjhc88ZIz2UeV5WscgZNWumNPlEx7VU7Z OolEB/UyxwZGzr6t5KlWWVESlVAKvfo2x2C4vULDJcvz07gFRrrhXoHoqs2WG3lLGXex LTkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Oqjirx8sUQyYnS7vrLSDlLS9gocI/IN6++5opPveqXM=; b=doxwDMCVtw+ep2SfjBjh5O0ty7l7wFjiphNmuY5GiAG5f3dUywdLJhZHPefOr11WUN KPIVgBOPIG9NXjPESljx3cNEoWJSVPbhsSUyFqojt04x0bzOI1iy7S7H/55x4smz2jQ5 CctrDEr7J984QBfxgnAUo/BjMRUmwXW60Ycghe16KvvtkoDVJSPRYu4YN6FzTq0G53P8 X3eMiQoYMw93f+MkUMUwvYF/UzNGn09mvm99/pMAvE5QLhI+nH/2cCGwsLyZnYD1jIY0 Uf94lo08qkcpT92aVo8T0qMqbNvAoUS3i4BLdHnhmolXOAXyOr5AkmkXnnPbH6hdpHAG uyVQ== X-Gm-Message-State: AOAM531JPhtIaSYzmFBDaR6xVNo5Am79uIBy4Enya5NWRxbfAyaEh3CC ahAvSxY9yUd8le7HgfR6Syrcl7Gq5cvq8Q== X-Google-Smtp-Source: ABdhPJz9+X3eKuKDc3b2fmmuUQFKS5X6dLE4qiWx/4kfhywm2JQfhbwClVT8d1SpQLhmuPTogp3JNw== X-Received: by 2002:a62:b410:0:b029:1a4:7868:7e4e with SMTP id h16-20020a62b4100000b02901a478687e4emr1057036pfn.62.1613593450883; Wed, 17 Feb 2021 12:24:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 60/71] tcg/tci: Remove tci_write_reg Date: Wed, 17 Feb 2021 12:20:25 -0800 Message-Id: <20210217202036.1724901-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Inline it into its one caller, tci_write_reg64. Drop the asserts that are redundant with tcg_read_r. Signed-off-by: Richard Henderson --- tcg/tci.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 3f8c6a0291..0b2bc905ea 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -36,20 +36,11 @@ =20 __thread uintptr_t tci_tb_ptr; =20 -static void -tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) -{ - tci_assert(index < TCG_TARGET_NB_REGS); - tci_assert(index !=3D TCG_AREG0); - tci_assert(index !=3D TCG_REG_CALL_STACK); - regs[index] =3D value; -} - static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, uint32_t low_index, uint64_t value) { - tci_write_reg(regs, low_index, value); - tci_write_reg(regs, high_index, value >> 32); + regs[low_index] =3D value; + regs[high_index] =3D value >> 32; } =20 /* Create a 64 bit value from two 32 bit values. */ --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613596487; cv=none; d=zohomail.com; s=zohoarc; b=ajVBeLGdmwZZisvWPQ58xMTfRqjeEDV6qbco28Ym2fcxQK9i7CIcOicSSdVu3R0DwjL6CpHK2cnFB10WcJ0V+nA1v5cvvANSh7JgQRTmkIFQd8qxUq6a78KycPbWua0AUo1mTgpprWOZC2DGWpgcfEQgUYbO8c8pxVmhEWZbyrg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613596487; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AVuOZddbattcoPTiU8kVVR2IlSzEN7KnRCfoZW6Xl64=; b=XzpVQwCHaNM6XMoY5U0D4wKNt1AzTBIu+h5tcDeOulme3X5+CDng9qADucWsUYNDA/sKviOkD+OEyCYG0+x4nyo79skwqOTJYHxBRU2GXX2hY117eHJr9ajrX9JwFe0tXYbWICykU4caDfD2CMdSy8aqL3/fCsUJfN+1h9HwXkk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613596487006126.04919518756128; Wed, 17 Feb 2021 13:14:47 -0800 (PST) Received: from localhost ([::1]:34512 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCU9l-0003Bs-TD for importer@patchew.org; Wed, 17 Feb 2021 16:14:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33726) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTMy-0001yC-EO for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:24:20 -0500 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:35224) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTMt-0007kH-1e for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:24:20 -0500 Received: by mail-pg1-x530.google.com with SMTP id t25so9230480pga.2 for ; Wed, 17 Feb 2021 12:24:14 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AVuOZddbattcoPTiU8kVVR2IlSzEN7KnRCfoZW6Xl64=; b=VhixfVJhCt04oa0XZ4n97WdWoM2YLDDx+oLPX6VIp6G6lIAt2b2tg1YjMqaLKTiidH 6HcCOgXSwJAYT0cbVhX49AqI7kMJwya18/cRcIlXSLZtZ6mp5PRNf+8lQ40gnIwWxNZf BHtCVzmbel72+OYMRoOcGm2iVXAEes7IiWo9198KdYpmAFUUgfN0XBMN9hA+cjNL6OIr r2E1S9IoXxiqWqCyHpot+5e+jofULrByUOsLdJEhjdxJSUvALPDr94r/sr/v6Nxi7t/z qwfWylbGGeyr6qac9O0byDKAvvO3m5fOESgm8fMcqTYONo5YtZwy51fOSvIEhcg0RwMI /sUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AVuOZddbattcoPTiU8kVVR2IlSzEN7KnRCfoZW6Xl64=; b=QfPrLOGnzSZHXc5xG60QkMl9cCsHNuqbhFpGyN9Q4WLBumOlTMmonPtL5qUOMEr1rB KzCE1Husw16Tiq5W+J4Q7kfbzrNHTU55bAbYqz38bji54QZJX+f+ug6XwDvt22bNSJfL dldObT/O67EJ4npGHn4alOTN+IRnqydHS0oKFk7qtFirBVwwllLDoINVGk0d6Kc6iPOX uNaHFfmghV1RgkfTl1OSgYRbhsSCLn7Ch2oxLRMjIFbK5IyuuJeGZd8Hp8dN02oZOlOw HQNX2BaStn7qwgIakbwbpHF0aIZQd4FsJggjRrFYn5N9uvN7kLDeQZRL3uzOgiEVLBko KMTQ== X-Gm-Message-State: AOAM530uQPAmE8iCKFW9FRMldGI7irr9i3RSPDWPH2aO/GfiPoeaZk3/ 2X5DOO/ohIOKRGyKx9uVFZfjBxHRU1H/Ug== X-Google-Smtp-Source: ABdhPJwwdux/YliXdD/er4faAFHQ+HRuke63vJNucqlcu0bKK33VxQVnqbNIugVe2ghljuEZ9t/awQ== X-Received: by 2002:a05:6a00:2b3:b029:1ec:adc7:645d with SMTP id q19-20020a056a0002b3b02901ecadc7645dmr1016083pfs.30.1613593453134; Wed, 17 Feb 2021 12:24:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 61/71] tcg/tci: Change encoding to uint32_t units Date: Wed, 17 Feb 2021 12:20:26 -0800 Message-Id: <20210217202036.1724901-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This removes all of the problems with unaligned accesses to the bytecode stream. With an 8-bit opcode at the bottom, we have 24 bits remaining, which are generally split into 6 4-bit slots. This fits well with the maximum length opcodes, e.g. INDEX_op_add2_i386, which have 6 register operands. We have, in previous patches, rearranged things such that there are no operations with a label, which have more than one other operand. Which leaves us with a 20-bit field in which to encode a label, giving us a maximum TB size of 512k -- easily large. Change the INDEX_op_tci_movi_{i32,i64} opcodes to tci_mov[il]. The former puts the immediate in the upper 20 bits of the insn, like we do for the label displacement. The later uses a label to reference an entry in the constant pool. Thus, in the worst case we still have a single memory reference for any constant, but now the constants are out-of-line of the bytecode and can be shared between different moves saving space. Change INDEX_op_call to use a label to reference a pair of pointers in the constant pool. This removes the only slightly dodgy link with the layout of struct TCGHelperInfo. The re-encode cannot be done in pieces. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 4 +- tcg/tci/tcg-target.h | 3 +- tcg/tci.c | 534 +++++++++++++++------------------------ tcg/tci/tcg-target.c.inc | 386 +++++++++++++--------------- tcg/tci/README | 20 +- 5 files changed, 380 insertions(+), 567 deletions(-) diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index bbb0884af8..5bbec858aa 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -277,8 +277,8 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) =20 #ifdef TCG_TARGET_INTERPRETER /* These opcodes are only for use between the tci generator and interprete= r. */ -DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) -DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) +DEF(tci_movi, 1, 0, 1, TCG_OPF_NOT_PRESENT) +DEF(tci_movl, 1, 0, 1, TCG_OPF_NOT_PRESENT) #endif =20 #undef TLADDR_ARGS diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 1558a6e44e..d953f2ead3 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -41,7 +41,7 @@ #define TCG_TARGET_H =20 #define TCG_TARGET_INTERPRETER 1 -#define TCG_TARGET_INSN_UNIT_SIZE 1 +#define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 =20 #if UINTPTR_MAX =3D=3D UINT32_MAX @@ -165,6 +165,7 @@ typedef enum { #define TCG_TARGET_STACK_ALIGN 8 =20 #define HAVE_TCG_QEMU_TB_EXEC +#define TCG_TARGET_NEED_POOL_LABELS =20 /* We could notice __i386__ or __s390x__ and reduce the barriers depending on the host. But if you want performance, you use the normal backend. diff --git a/tcg/tci.c b/tcg/tci.c index 0b2bc905ea..76bbf440a8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -49,49 +49,6 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low) return ((uint64_t)high << 32) + low; } =20 -/* Read constant byte from bytecode. */ -static uint8_t tci_read_b(const uint8_t **tb_ptr) -{ - return *(tb_ptr[0]++); -} - -/* Read register number from bytecode. */ -static TCGReg tci_read_r(const uint8_t **tb_ptr) -{ - uint8_t regno =3D tci_read_b(tb_ptr); - tci_assert(regno < TCG_TARGET_NB_REGS); - return regno; -} - -/* Read constant (native size) from bytecode. */ -static tcg_target_ulong tci_read_i(const uint8_t **tb_ptr) -{ - tcg_target_ulong value =3D *(const tcg_target_ulong *)(*tb_ptr); - *tb_ptr +=3D sizeof(value); - return value; -} - -/* Read unsigned constant (32 bit) from bytecode. */ -static uint32_t tci_read_i32(const uint8_t **tb_ptr) -{ - uint32_t value =3D *(const uint32_t *)(*tb_ptr); - *tb_ptr +=3D sizeof(value); - return value; -} - -/* Read signed constant (32 bit) from bytecode. */ -static int32_t tci_read_s32(const uint8_t **tb_ptr) -{ - int32_t value =3D *(const int32_t *)(*tb_ptr); - *tb_ptr +=3D sizeof(value); - return value; -} - -static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) -{ - return tci_read_i(tb_ptr); -} - /* * Load sets of arguments all at once. The naming convention is: * tci_args_ @@ -106,209 +63,128 @@ static tcg_target_ulong tci_read_label(const uint8_t= **tb_ptr) * s =3D signed ldst offset */ =20 -static void check_size(const uint8_t *start, const uint8_t **tb_ptr) +static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0) { - const uint8_t *old_code_ptr =3D start - 2; - uint8_t op_size =3D old_code_ptr[1]; - tci_assert(*tb_ptr =3D=3D old_code_ptr + op_size); + int diff =3D sextract32(insn, 12, 20); + *l0 =3D diff ? (void *)tb_ptr + diff : NULL; } =20 -static void tci_args_l(const uint8_t **tb_ptr, void **l0) +static void tci_args_nl(uint32_t insn, const void *tb_ptr, + uint8_t *n0, void **l1) { - const uint8_t *start =3D *tb_ptr; - - *l0 =3D (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); + *n0 =3D extract32(insn, 8, 4); + *l1 =3D sextract32(insn, 12, 20) + (void *)tb_ptr; } =20 -static void tci_args_nl(const uint8_t **tb_ptr, uint8_t *n0, void **l1) +static void tci_args_rl(uint32_t insn, const void *tb_ptr, + TCGReg *r0, void **l1) { - const uint8_t *start =3D *tb_ptr; - - *n0 =3D tci_read_b(tb_ptr); - *l1 =3D (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *l1 =3D sextract32(insn, 12, 20) + (void *)tb_ptr; } =20 -static void tci_args_rl(const uint8_t **tb_ptr, TCGReg *r0, void **l1) +static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *l1 =3D (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); } =20 -static void tci_args_rr(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1) +static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_target_ulong *i1) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *i1 =3D sextract32(insn, 12, 20); } =20 -static void tci_args_ri(const uint8_t **tb_ptr, - TCGReg *r0, tcg_target_ulong *i1) +static void tci_args_rrm(uint32_t insn, TCGReg *r0, + TCGReg *r1, TCGMemOpIdx *m2) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *i1 =3D tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *m2 =3D extract32(insn, 20, 12); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -static void tci_args_rI(const uint8_t **tb_ptr, - TCGReg *r0, tcg_target_ulong *i1) +static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *i1 =3D tci_read_i(tb_ptr); - - check_size(start, tb_ptr); -} -#endif - -static void tci_args_rrm(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2) -{ - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *m2 =3D tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); } =20 -static void tci_args_rrr(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, TCGReg *r2) +static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i= 2) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *i2 =3D sextract32(insn, 16, 16); } =20 -static void tci_args_rrs(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, int32_t *i2) -{ - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *i2 =3D tci_read_s32(tb_ptr); - - check_size(start, tb_ptr); -} - -static void tci_args_rrrc(const uint8_t **tb_ptr, +static void tci_args_rrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *c3 =3D tci_read_b(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *c3 =3D extract32(insn, 20, 4); } =20 -static void tci_args_rrrm(const uint8_t **tb_ptr, +static void tci_args_rrrm(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx = *m3) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *m3 =3D tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *m3 =3D extract32(insn, 20, 12); } =20 -static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, +static void tci_args_rrrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, uint8_t *i3, uint8_t *i4) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *i3 =3D tci_read_b(tb_ptr); - *i4 =3D tci_read_b(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *i3 =3D extract32(insn, 20, 6); + *i4 =3D extract32(insn, 26, 6); } =20 -static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, - TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4) +static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGReg *r4) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *r3 =3D tci_read_r(tb_ptr); - *m4 =3D tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *r3 =3D extract32(insn, 20, 4); + *r4 =3D extract32(insn, 24, 4); } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 -static void tci_args_rrrr(const uint8_t **tb_ptr, +static void tci_args_rrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *r3 =3D tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *r3 =3D extract32(insn, 20, 4); } =20 -static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, +static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *r3 =3D tci_read_r(tb_ptr); - *r4 =3D tci_read_r(tb_ptr); - *c5 =3D tci_read_b(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *r3 =3D extract32(insn, 20, 4); + *r4 =3D extract32(insn, 24, 4); + *c5 =3D extract32(insn, 28, 4); } =20 -static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, +static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *r3 =3D tci_read_r(tb_ptr); - *r4 =3D tci_read_r(tb_ptr); - *r5 =3D tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *r3 =3D extract32(insn, 20, 4); + *r4 =3D extract32(insn, 24, 4); + *r5 =3D extract32(insn, 28, 4); } #endif =20 @@ -447,7 +323,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCG= Cond condition) uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, const void *v_tb_ptr) { - const uint8_t *tb_ptr =3D v_tb_ptr; + const uint32_t *tb_ptr =3D v_tb_ptr; tcg_target_ulong regs[TCG_TARGET_NB_REGS]; uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) / sizeof(uint64_t)]; @@ -459,8 +335,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_assert(tb_ptr); =20 for (;;) { - TCGOpcode opc =3D tb_ptr[0]; - TCGReg r0, r1, r2, r3; + uint32_t insn; + TCGOpcode opc; + TCGReg r0, r1, r2, r3, r4; tcg_target_ulong t1; TCGCond condition; target_ulong taddr; @@ -468,23 +345,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r4, r5; + TCGReg r5; uint64_t T1, T2; #endif TCGMemOpIdx oi; int32_t ofs; void *ptr; =20 - /* Skip opcode and size entry. */ - tb_ptr +=3D 2; + insn =3D *tb_ptr++; + opc =3D extract32(insn, 0, 8); =20 switch (opc) { case INDEX_op_call: - /* - * We are passed a pointer to the TCGHelperInfo, which contains - * the function pointer followed by the ffi_cif pointer. - */ - tci_args_nl(&tb_ptr, &len, &ptr); + tci_args_nl(insn, tb_ptr, &len, &ptr); =20 /* Helper functions may need to access the "return address" */ tci_tb_ptr =3D (uintptr_t)tb_ptr; @@ -502,8 +375,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, } =20 /* - * Call the helper function. Any result winds up - * "left-aligned" in the stack[0] slot. + * We are passed a pointer into the constant pool, which + * contains a pair of the function pointer and the cif pointer. + * Any result winds up "left-aligned" in the stack[0] slot. */ { void **pptr =3D ptr; @@ -535,76 +409,80 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; =20 case INDEX_op_br: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); tb_ptr =3D ptr; continue; case INDEX_op_setcond_i32: - tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] =3D tci_compare32(regs[r1], regs[r2], condition); break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: - tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &condition); + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); T1 =3D tci_uint64(regs[r2], regs[r1]); T2 =3D tci_uint64(regs[r4], regs[r3]); regs[r0] =3D tci_compare64(T1, T2, condition); break; #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: - tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] =3D tci_compare64(regs[r1], regs[r2], condition); break; #endif CASE_32_64(mov) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D regs[r1]; break; - case INDEX_op_tci_movi_i32: - tci_args_ri(&tb_ptr, &r0, &t1); + case INDEX_op_tci_movi: + tci_args_ri(insn, &r0, &t1); regs[r0] =3D t1; break; + case INDEX_op_tci_movl: + tci_args_rl(insn, tb_ptr, &r0, &ptr); + regs[r0] =3D *(tcg_target_ulong *)ptr; + break; =20 /* Load/store operations (32 bit). */ =20 CASE_32_64(ld8u) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(uint8_t *)ptr; break; CASE_32_64(ld8s) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(int8_t *)ptr; break; CASE_32_64(ld16u) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(uint16_t *)ptr; break; CASE_32_64(ld16s) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(int16_t *)ptr; break; case INDEX_op_ld_i32: CASE_64(ld32u) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(uint32_t *)ptr; break; CASE_32_64(st8) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); *(uint8_t *)ptr =3D regs[r0]; break; CASE_32_64(st16) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); *(uint16_t *)ptr =3D regs[r0]; break; case INDEX_op_st_i32: CASE_64(st32) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); *(uint32_t *)ptr =3D regs[r0]; break; @@ -612,171 +490,166 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArch= State *env, /* Arithmetic operations (mixed 32/64 bit). */ =20 CASE_32_64(add) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] + regs[r2]; break; CASE_32_64(sub) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] - regs[r2]; break; CASE_32_64(mul) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] * regs[r2]; break; CASE_32_64(and) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] & regs[r2]; break; CASE_32_64(or) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] | regs[r2]; break; CASE_32_64(xor) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] ^ regs[r2]; break; =20 /* Arithmetic operations (32 bit). */ =20 case INDEX_op_div_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (int32_t)regs[r1] / (int32_t)regs[r2]; break; case INDEX_op_divu_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint32_t)regs[r1] / (uint32_t)regs[r2]; break; case INDEX_op_rem_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (int32_t)regs[r1] % (int32_t)regs[r2]; break; case INDEX_op_remu_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint32_t)regs[r1] % (uint32_t)regs[r2]; break; =20 /* Shift/rotate operations (32 bit). */ =20 case INDEX_op_shl_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint32_t)regs[r1] << (regs[r2] & 31); break; case INDEX_op_shr_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint32_t)regs[r1] >> (regs[r2] & 31); break; case INDEX_op_sar_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (int32_t)regs[r1] >> (regs[r2] & 31); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D rol32(regs[r1], regs[r2] & 31); break; case INDEX_op_rotr_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D ror32(regs[r1], regs[r2] & 31); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: - tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] =3D deposit32(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i32: - tci_args_rl(&tb_ptr, &r0, &ptr); + tci_args_rl(insn, tb_ptr, &r0, &ptr); if ((uint32_t)regs[r0]) { tb_ptr =3D ptr; } break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: - tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 =3D tci_uint64(regs[r3], regs[r2]); T2 =3D tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 + T2); break; case INDEX_op_sub2_i32: - tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 =3D tci_uint64(regs[r3], regs[r2]); T2 =3D tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; case INDEX_op_mulu2_i32: - tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D (int8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 CASE_32_64(ext16s) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D (int16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 CASE_32_64(ext8u) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D (uint8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 CASE_32_64(ext16u) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D (uint16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 CASE_32_64(bswap16) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D bswap16(regs[r1]); break; #endif #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 CASE_32_64(bswap32) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D bswap32(regs[r1]); break; #endif #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 CASE_32_64(not) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D ~regs[r1]; break; #endif #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 CASE_32_64(neg) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D -regs[r1]; break; #endif #if TCG_TARGET_REG_BITS =3D=3D 64 - case INDEX_op_tci_movi_i64: - tci_args_rI(&tb_ptr, &r0, &t1); - regs[r0] =3D t1; - break; - /* Load/store operations (64 bit). */ =20 case INDEX_op_ld32s_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(int32_t *)ptr; break; case INDEX_op_ld_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(uint64_t *)ptr; break; case INDEX_op_st_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); *(uint64_t *)ptr =3D regs[r0]; break; @@ -784,71 +657,71 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, /* Arithmetic operations (64 bit). */ =20 case INDEX_op_div_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (int64_t)regs[r1] / (int64_t)regs[r2]; break; case INDEX_op_divu_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint64_t)regs[r1] / (uint64_t)regs[r2]; break; case INDEX_op_rem_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (int64_t)regs[r1] % (int64_t)regs[r2]; break; case INDEX_op_remu_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint64_t)regs[r1] % (uint64_t)regs[r2]; break; =20 /* Shift/rotate operations (64 bit). */ =20 case INDEX_op_shl_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] << (regs[r2] & 63); break; case INDEX_op_shr_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] >> (regs[r2] & 63); break; case INDEX_op_sar_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (int64_t)regs[r1] >> (regs[r2] & 63); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D rol64(regs[r1], regs[r2] & 63); break; case INDEX_op_rotr_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D ror64(regs[r1], regs[r2] & 63); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: - tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] =3D deposit64(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i64: - tci_args_rl(&tb_ptr, &r0, &ptr); + tci_args_rl(insn, tb_ptr, &r0, &ptr); if (regs[r0]) { tb_ptr =3D ptr; } break; case INDEX_op_ext32s_i64: case INDEX_op_ext_i32_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D (int32_t)regs[r1]; break; case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D (uint32_t)regs[r1]; break; #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D bswap64(regs[r1]); break; #endif @@ -857,20 +730,20 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, /* QEMU specific operations. */ =20 case INDEX_op_exit_tb: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); return (uintptr_t)ptr; =20 case INDEX_op_goto_tb: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); tb_ptr =3D *(void **)ptr; break; =20 case INDEX_op_qemu_ld_i32: if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; } else { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr =3D tci_uint64(regs[r2], regs[r1]); } switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { @@ -906,14 +779,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_qemu_ld_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr =3D regs[r2]; } else { - tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); taddr =3D tci_uint64(regs[r3], regs[r2]); + oi =3D regs[r4]; } switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: @@ -964,10 +838,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_qemu_st_i32: if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; } else { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr =3D tci_uint64(regs[r2], regs[r1]); } tmp32 =3D regs[r0]; @@ -994,16 +868,17 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_qemu_st_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; tmp64 =3D regs[r0]; } else { if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr =3D regs[r2]; } else { - tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); taddr =3D tci_uint64(regs[r3], regs[r2]); + oi =3D regs[r4]; } tmp64 =3D tci_uint64(regs[r1], regs[r0]); } @@ -1087,14 +962,14 @@ static const char *str_c(TCGCond c) /* Disassemble TCI bytecode. */ int print_insn_tci(bfd_vma addr, disassemble_info *info) { - uint8_t buf[256]; - int length, status; + const uint32_t *tb_ptr =3D (const void *)(uintptr_t)addr; const TCGOpDef *def; const char *op_name; + uint32_t insn; TCGOpcode op; - TCGReg r0, r1, r2, r3; + TCGReg r0, r1, r2, r3, r4; #if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r4, r5; + TCGReg r5; #endif tcg_target_ulong i1; int32_t s2; @@ -1102,71 +977,54 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) TCGMemOpIdx oi; uint8_t pos, len; void *ptr; - const uint8_t *tb_ptr; =20 - status =3D info->read_memory_func(addr, buf, 2, info); - if (status !=3D 0) { - info->memory_error_func(status, addr, info); - return -1; - } - op =3D buf[0]; - length =3D buf[1]; + /* TCI is always the host, so we don't need to load indirect. */ + insn =3D *tb_ptr++; =20 - if (length < 2) { - info->fprintf_func(info->stream, "invalid length %d", length); - return 1; - } - - status =3D info->read_memory_func(addr + 2, buf + 2, length - 2, info); - if (status !=3D 0) { - info->memory_error_func(status, addr + 2, info); - return -1; - } + info->fprintf_func(info->stream, "%08x ", insn); =20 + op =3D extract32(insn, 0, 8); def =3D &tcg_op_defs[op]; op_name =3D def->name; - tb_ptr =3D buf + 2; =20 switch (op) { case INDEX_op_br: case INDEX_op_exit_tb: case INDEX_op_goto_tb: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); break; =20 case INDEX_op_call: - tci_args_nl(&tb_ptr, &len, &ptr); + tci_args_nl(insn, tb_ptr, &len, &ptr); info->fprintf_func(info->stream, "%-12s %d,%p", op_name, len, ptr= ); break; =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - tci_args_rl(&tb_ptr, &r0, &ptr); + tci_args_rl(insn, tb_ptr, &r0, &ptr); info->fprintf_func(info->stream, "%-12s %s,0,ne,%p", op_name, str_r(r0), ptr); break; =20 case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &c); + tci_args_rrrc(insn, &r0, &r1, &r2, &c); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_c= (c)); break; =20 - case INDEX_op_tci_movi_i32: - tci_args_ri(&tb_ptr, &r0, &i1); + case INDEX_op_tci_movi: + tci_args_ri(insn, &r0, &i1); info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "", op_name, str_r(r0), i1); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 - case INDEX_op_tci_movi_i64: - tci_args_rI(&tb_ptr, &r0, &i1); - info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "", - op_name, str_r(r0), i1); + case INDEX_op_tci_movl: + tci_args_rl(insn, tb_ptr, &r0, &ptr); + info->fprintf_func(info->stream, "%-12s %s,%p", + op_name, str_r(r0), ptr); break; -#endif =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: @@ -1187,7 +1045,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) case INDEX_op_st32_i64: case INDEX_op_st_i32: case INDEX_op_st_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &s2); + tci_args_rrs(insn, &r0, &r1, &s2); info->fprintf_func(info->stream, "%-12s %s,%s,%d", op_name, str_r(r0), str_r(r1), s2); break; @@ -1214,7 +1072,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) case INDEX_op_not_i64: case INDEX_op_neg_i32: case INDEX_op_neg_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); info->fprintf_func(info->stream, "%-12s %s,%s", op_name, str_r(r0), str_r(r1)); break; @@ -1249,28 +1107,28 @@ int print_insn_tci(bfd_vma addr, disassemble_info *= info) case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); info->fprintf_func(info->stream, "%-12s %s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2)); break; =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%d,%d", op_name, str_r(r0), str_r(r1), str_r(r2), pos, = len); break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: - tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &c); + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3), str_r(r4), str_c(c)); break; =20 case INDEX_op_mulu2_i32: - tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3)); @@ -1278,7 +1136,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) =20 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3), str_r(r4), str_r(r5)); @@ -1296,30 +1154,38 @@ int print_insn_tci(bfd_vma addr, disassemble_info *= info) len +=3D DIV_ROUND_UP(TARGET_LONG_BITS, TCG_TARGET_REG_BITS); switch (len) { case 2: - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); info->fprintf_func(info->stream, "%-12s %s,%s,%x", op_name, str_r(r0), str_r(r1), oi); break; case 3: - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%x", op_name, str_r(r0), str_r(r1), str_r(r2), o= i); break; case 4: - tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); - info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%x", + tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s", op_name, str_r(r0), str_r(r1), - str_r(r2), str_r(r3), oi); + str_r(r2), str_r(r3), str_r(r4)); break; default: g_assert_not_reached(); } break; =20 + case 0: + /* tcg_out_nop_fill uses zeros */ + if (insn =3D=3D 0) { + info->fprintf_func(info->stream, "align"); + break; + } + /* fall through */ + default: info->fprintf_func(info->stream, "illegal opcode %d", op); break; } =20 - return length; + return sizeof(insn); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index e06d4e9380..0df8384be7 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -22,20 +22,7 @@ * THE SOFTWARE. */ =20 -/* TODO list: - * - See TODO comments in code. - */ - -/* Marker for missing code. */ -#define TODO() \ - do { \ - fprintf(stderr, "TODO %s:%u: %s()\n", \ - __FILE__, __LINE__, __func__); \ - tcg_abort(); \ - } while (0) - -/* Bitfield n...m (in 32 bit value). */ -#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) +#include "../tcg-pool.c.inc" =20 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { @@ -226,52 +213,16 @@ static const char *const tcg_target_reg_names[TCG_TAR= GET_NB_REGS] =3D { static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - /* tcg_out_reloc always uses the same type, addend. */ - tcg_debug_assert(type =3D=3D sizeof(tcg_target_long)); + intptr_t diff =3D value - (intptr_t)(code_ptr + 1); + tcg_debug_assert(addend =3D=3D 0); - tcg_debug_assert(value !=3D 0); - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_patch32(code_ptr, value); - } else { - tcg_patch64(code_ptr, value); - } - return true; -} - -/* Write value (native size). */ -static void tcg_out_i(TCGContext *s, tcg_target_ulong v) -{ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out32(s, v); - } else { - tcg_out64(s, v); - } -} - -/* Write opcode. */ -static void tcg_out_op_t(TCGContext *s, TCGOpcode op) -{ - tcg_out8(s, op); - tcg_out8(s, 0); -} - -/* Write register. */ -static void tcg_out_r(TCGContext *s, TCGArg t0) -{ - tcg_debug_assert(t0 < TCG_TARGET_NB_REGS); - tcg_out8(s, t0); -} - -/* Write label. */ -static void tci_out_label(TCGContext *s, TCGLabel *label) -{ - if (label->has_value) { - tcg_out_i(s, label->u.value); - tcg_debug_assert(label->u.value); - } else { - tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), label, 0); - s->code_ptr +=3D sizeof(tcg_target_ulong); + tcg_debug_assert(type =3D=3D 20); + + if (diff =3D=3D sextract32(diff, 0, type)) { + tcg_patch32(code_ptr, deposit32(*code_ptr, 32 - type, type, diff)); + return true; } + return false; } =20 static void stack_bounds_check(TCGReg base, target_long offset) @@ -285,251 +236,236 @@ static void stack_bounds_check(TCGReg base, target_= long offset) =20 static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tci_out_label(s, l0); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_reloc(s, s->code_ptr, 20, l0, 0); + insn =3D deposit32(insn, 0, 8, op); + tcg_out32(s, insn); } =20 static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; + intptr_t diff; =20 - tcg_out_op_t(s, op); - tcg_out_i(s, (uintptr_t)p0); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + /* Special case for exit_tb: map null -> 0. */ + if (p0 =3D=3D NULL) { + diff =3D 0; + } else { + diff =3D p0 - (void *)(s->code_ptr + 1); + tcg_debug_assert(diff !=3D 0); + if (diff !=3D sextract32(diff, 0, 20)) { + tcg_raise_tb_overflow(s); + } + } + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 12, 20, diff); + tcg_out32(s, insn); } =20 static void tcg_out_op_v(TCGContext *s, TCGOpcode op) { - uint8_t *old_code_ptr =3D s->code_ptr; - - tcg_out_op_t(s, op); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; -} - -static void tcg_out_op_np(TCGContext *s, TCGOpcode op, - uint8_t n0, const void *p1) -{ - uint8_t *old_code_ptr =3D s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out8(s, n0); - tcg_out_i(s, (uintptr_t)p1); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out32(s, (uint8_t)op); } =20 static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t = i1) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out32(s, i1); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_debug_assert(i1 =3D=3D sextract32(i1, 0, 20)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 20, i1); + tcg_out32(s, insn); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -static void tcg_out_op_rI(TCGContext *s, TCGOpcode op, - TCGReg r0, uint64_t i1) -{ - uint8_t *old_code_ptr =3D s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out64(s, i1); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; -} -#endif - static void tcg_out_op_rl(TCGContext *s, TCGOpcode op, TCGReg r0, TCGLabel= *l1) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tci_out_label(s, l1); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_reloc(s, s->code_ptr, 20, l1, 0); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + tcg_out32(s, insn); } =20 static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrm(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGArg m2) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out32(s, m2); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_debug_assert(m2 =3D=3D extract32(m2, 0, 12)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 20, 12, m2); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_debug_assert(i2 =3D=3D (int32_t)i2); - tcg_out32(s, i2); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_debug_assert(i2 =3D=3D sextract32(i2, 0, 16)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 16, i2); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out8(s, c3); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 4, c3); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrrm(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGArg m3) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out32(s, m3); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_debug_assert(m3 =3D=3D extract32(m3, 0, 12)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 12, m3); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out8(s, b3); - tcg_out8(s, b4); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_debug_assert(b3 =3D=3D extract32(b3, 0, 6)); + tcg_debug_assert(b4 =3D=3D extract32(b4, 0, 6)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 6, b3); + insn =3D deposit32(insn, 26, 6, b4); + tcg_out32(s, insn); } =20 -static void tcg_out_op_rrrrm(TCGContext *s, TCGOpcode op, TCGReg r0, - TCGReg r1, TCGReg r2, TCGReg r3, TCGArg m4) +static void tcg_out_op_rrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out32(s, m4); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 4, r3); + insn =3D deposit32(insn, 24, 4, r4); + tcg_out32(s, insn); } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 4, r3); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out_r(s, r4); - tcg_out8(s, c5); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 4, r3); + insn =3D deposit32(insn, 24, 4, r4); + insn =3D deposit32(insn, 28, 4, c5); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGReg r5) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out_r(s, r4); - tcg_out_r(s, r5); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 4, r3); + insn =3D deposit32(insn, 24, 4, r4); + insn =3D deposit32(insn, 28, 4, r5); + tcg_out32(s, insn); } #endif =20 +static void tcg_out_ldst(TCGContext *s, TCGOpcode op, TCGReg val, + TCGReg base, intptr_t offset) +{ + stack_bounds_check(base, offset); + if (offset !=3D sextract32(offset, 0, 16)) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); + tcg_out_op_rrr(s, (TCG_TARGET_REG_BITS =3D=3D 32 + ? INDEX_op_add_i32 : INDEX_op_add_i64), + TCG_REG_TMP, TCG_REG_TMP, base); + base =3D TCG_REG_TMP; + offset =3D 0; + } + tcg_out_op_rrs(s, op, val, base, offset); +} + static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, intptr_t offset) { - stack_bounds_check(base, offset); switch (type) { case TCG_TYPE_I32: - tcg_out_op_rrs(s, INDEX_op_ld_i32, val, base, offset); + tcg_out_ldst(s, INDEX_op_ld_i32, val, base, offset); break; #if TCG_TARGET_REG_BITS =3D=3D 64 case TCG_TYPE_I64: - tcg_out_op_rrs(s, INDEX_op_ld_i64, val, base, offset); + tcg_out_ldst(s, INDEX_op_ld_i64, val, base, offset); break; #endif default: @@ -559,22 +495,33 @@ static void tcg_out_movi(TCGContext *s, TCGType type, { switch (type) { case TCG_TYPE_I32: - tcg_out_op_ri(s, INDEX_op_tci_movi_i32, ret, arg); - break; #if TCG_TARGET_REG_BITS =3D=3D 64 + arg =3D (int32_t)arg; + /* fall through */ case TCG_TYPE_I64: - tcg_out_op_rI(s, INDEX_op_tci_movi_i64, ret, arg); - break; #endif + break; default: g_assert_not_reached(); } + + if (arg =3D=3D sextract32(arg, 0, 20)) { + tcg_out_op_ri(s, INDEX_op_tci_movi, ret, arg); + } else { + tcg_insn_unit insn =3D 0; + + new_pool_label(s, arg, 20, s->code_ptr, 0); + insn =3D deposit32(insn, 0, 8, INDEX_op_tci_movl); + insn =3D deposit32(insn, 8, 4, ret); + tcg_out32(s, insn); + } } =20 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { const TCGHelperInfo *info; uint8_t which; + tcg_insn_unit insn =3D 0; =20 info =3D g_hash_table_lookup(helper_table, (gpointer)arg); if (info->cif->rtype =3D=3D &ffi_type_void) { @@ -586,7 +533,11 @@ static void tcg_out_call(TCGContext *s, const tcg_insn= _unit *arg) which =3D 2; } =20 - tcg_out_op_np(s, INDEX_op_call, which, info); + new_pool_l2(s, 20, s->code_ptr, 0, + (uintptr_t)info->func, (uintptr_t)info->cif); + insn =3D deposit32(insn, 0, 8, INDEX_op_call); + insn =3D deposit32(insn, 8, 4, which); + tcg_out32(s, insn); } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -644,8 +595,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, case INDEX_op_st_i32: CASE_64(st32) CASE_64(st) - stack_bounds_check(args[1], args[2]); - tcg_out_op_rrs(s, opc, args[0], args[1], args[2]); + tcg_out_ldst(s, opc, args[0], args[1], args[2]); break; =20 CASE_32_64(add) @@ -738,8 +688,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); } else { - tcg_out_op_rrrrm(s, opc, args[0], args[1], - args[2], args[3], args[4]); + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, args[4]); + tcg_out_op_rrrrr(s, opc, args[0], args[1], + args[2], args[3], TCG_REG_TMP); } break; =20 @@ -787,6 +738,11 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, return arg_ct->ct & TCG_CT_CONST; } =20 +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + memset(p, 0, sizeof(*p) * count); +} + static void tcg_target_init(TCGContext *s) { #if defined(CONFIG_DEBUG_TCG_INTERPRETER) diff --git a/tcg/tci/README b/tcg/tci/README index 9bb7d7a5d3..f72a40a395 100644 --- a/tcg/tci/README +++ b/tcg/tci/README @@ -23,10 +23,12 @@ This is what TCI (Tiny Code Interpreter) does. Like each TCG host frontend, TCI implements the code generator in tcg-target.c.inc, tcg-target.h. Both files are in directory tcg/tci. =20 -The additional file tcg/tci.c adds the interpreter. +The additional file tcg/tci.c adds the interpreter and disassembler. =20 -The bytecode consists of opcodes (same numeric values as those used by -TCG), command length and arguments of variable size and number. +The bytecode consists of opcodes (with only a few exceptions, with +the same same numeric values and semantics as used by TCG), and up +to six arguments packed into a 32-bit integer. See comments in tci.c +for details on the encoding. =20 3) Usage =20 @@ -39,11 +41,6 @@ suggest using this option. Setting it automatically woul= d need additional code in configure which must be fixed when new native TCG implementations are added. =20 -System emulation should work on any 32 or 64 bit host. -User mode emulation might work. Maybe a new linker script (*.ld) -is needed. Byte order might be wrong (on big endian hosts) -and need fixes in configure. - For hosts with native TCG, the interpreter TCI can be enabled by =20 configure --enable-tcg-interpreter @@ -118,13 +115,6 @@ u1 =3D linux-user-test works in the interpreter. These opcodes raise a runtime exception, so it is possible to see where code must be added. =20 -* The pseudo code is not optimized and still ugly. For hosts with special - alignment requirements, it needs some fixes (maybe aligned bytecode - would also improve speed for hosts which support byte alignment). - -* A better disassembler for the pseudo code would be nice (a very primitive - disassembler is included in tcg-target.c.inc). - * It might be useful to have a runtime option which selects the native TCG or TCI, so QEMU would have to include two TCGs. Today, selecting TCI is a configure option, so you need two compilations of QEMU. --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613597175; cv=none; d=zohomail.com; s=zohoarc; b=Y6AystUWgiuHYxU82+Kx/jDhdTsKOWmd0LV5xHE92z5WonvzNunpXI03d4QTBZxGwatQGdsX5VVAEiaTtw91FXtKYEw0Zi+zYuM9RCDpwm04hyAEgQNPlAIWZlSZUQrWdlaAZtHR3yA4VmxZLwE4mJyEdCznv/lCT7kG3J7YVU4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613597175; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9jHEmEI6EV8qZCeh+tCL5YyTrUMsHZff/il96+nDzSE=; b=OCxwBVaM4Ww+JuvXQpS5ZBJpA735wJVIwyiVwDBwx7ac2cddc16x6UQ93hOJYsjSeLCn6w0GLMJCdN65THfLuKsLsudQkOSiZtCzp6NaM60TMiBhoOnRYj4korPPA9+iTgyB+E0/IGyfYsdYL69xIraDpYnzpgXQQCHqYFHXXKQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161359717533127.836909108035456; Wed, 17 Feb 2021 13:26:15 -0800 (PST) Received: from localhost ([::1]:42930 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCUKs-00024k-6V for importer@patchew.org; Wed, 17 Feb 2021 16:26:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33692) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTMw-0001xV-Rf for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:24:20 -0500 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:45332) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTMt-0007l4-Oc for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:24:18 -0500 Received: by mail-pg1-x534.google.com with SMTP id p21so3554862pgl.12 for ; Wed, 17 Feb 2021 12:24:15 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9jHEmEI6EV8qZCeh+tCL5YyTrUMsHZff/il96+nDzSE=; b=Ax5oSPO3tlNDJuwVAlJIC9uJJIMl8CM9iVvH67ONoL6K4y9iKMdgRO86SDY3tEr5Jh O+QYvUYgmdBQG8nYI5wHrUr/vf6vdCShHLWkojEVNaG6u3onXaZguPgxeURuftyCkUxG v+OJvrytnueJoT9BeqQhYYIADTg8JVkCNNo/3QWxYYID9ef+ZqV6EtPli0B8CcdhtdP5 6tsX3wVC3xuKIwkBJc4r71T4mEOx42oCCWLVQg4RN7RTVXlpszFaI17x6rHIN7cg9beO 4pL3lmq3YdT+vxC5AlYE9Dt+eDUU19t/3klyCX/ygGDVxgEwIeBZHM1CYjIwy0DKBHHi PoAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9jHEmEI6EV8qZCeh+tCL5YyTrUMsHZff/il96+nDzSE=; b=QgNeYzaFKPBg6srNSPuSUzoPitsXppjs8NmZILA9vUC6ASwzDWkB3cBrhKAMdc5jVA SWjNdnl96QQNgN0zpg2XQ+tBj82Fb9wRsKMKuRxzT0Wctvcg8+DN7CqeOZ2i+3hoj1iJ ORljoP+WjpszUdzSU19b0wB0bnoobp4cRz+J91pqC9wI1aqBhE17iLyR1uxCvGY7q6Am ggA0dC4CUXaiMwKARCpGeJKR/jcqtaupPME3MV0BZit/VbGEdhsgmFoJfzJOG6L2TAPZ Qi9ak2n1jk07ZTs6gPvMOdUZVQlQSPCL4ghWDusVcm5x4fd/GL9CgWctdbLoyBmdUnoH 28UQ== X-Gm-Message-State: AOAM532dXv6G7v3SNBZt2lwbf0phfdyF2yoHSKFYewHQiylkJ/M5TDJy ZdlrLFEvaqyyLakUl4fcDoVVaKLA8G6FRA== X-Google-Smtp-Source: ABdhPJx8Q1tqWGCNLd1Thj98fIwa09P0gpl2j7T6FRhDDndIfiiYvQ100jDXhPs+NHAsHmvWE8Yhuw== X-Received: by 2002:a63:3c4e:: with SMTP id i14mr948682pgn.266.1613593454587; Wed, 17 Feb 2021 12:24:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 62/71] tcg/tci: Implement goto_ptr Date: Wed, 17 Feb 2021 12:20:27 -0800 Message-Id: <20210217202036.1724901-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This operation is critical to staying within the interpretation loop longer, which avoids the overhead of setup and teardown for many TBs. The check in tcg_prologue_init is disabled because TCI does want to use NULL to indicate exit, as opposed to branching to a real epilogue. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-con-set.h | 1 + tcg/tci/tcg-target.h | 2 +- tcg/tcg.c | 2 ++ tcg/tci.c | 19 +++++++++++++++++++ tcg/tci/tcg-target.c.inc | 16 ++++++++++++++++ 5 files changed, 39 insertions(+), 1 deletion(-) diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h index 316730f32c..ae2dc3b844 100644 --- a/tcg/tci/tcg-target-con-set.h +++ b/tcg/tci/tcg-target-con-set.h @@ -9,6 +9,7 @@ * Each operand should be a sequence of constraint letters as defined by * tcg-target-con-str.h; the constraint combination is inclusive or. */ +C_O0_I1(r) C_O0_I2(r, r) C_O0_I3(r, r, r) C_O0_I4(r, r, r, r) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index d953f2ead3..17911d3297 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -86,7 +86,7 @@ #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 -#define TCG_TARGET_HAS_goto_ptr 0 +#define TCG_TARGET_HAS_goto_ptr 1 #define TCG_TARGET_HAS_direct_jump 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 diff --git a/tcg/tcg.c b/tcg/tcg.c index 92aec0d238..ce80adcfbe 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1314,10 +1314,12 @@ void tcg_prologue_init(TCGContext *s) } #endif =20 +#ifndef CONFIG_TCG_INTERPRETER /* Assert that goto_ptr is implemented completely. */ if (TCG_TARGET_HAS_goto_ptr) { tcg_debug_assert(tcg_code_gen_epilogue !=3D NULL); } +#endif } =20 void tcg_func_start(TCGContext *s) diff --git a/tcg/tci.c b/tcg/tci.c index 76bbf440a8..c229050c66 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -69,6 +69,11 @@ static void tci_args_l(uint32_t insn, const void *tb_ptr= , void **l0) *l0 =3D diff ? (void *)tb_ptr + diff : NULL; } =20 +static void tci_args_r(uint32_t insn, TCGReg *r0) +{ + *r0 =3D extract32(insn, 8, 4); +} + static void tci_args_nl(uint32_t insn, const void *tb_ptr, uint8_t *n0, void **l1) { @@ -738,6 +743,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tb_ptr =3D *(void **)ptr; break; =20 + case INDEX_op_goto_ptr: + tci_args_r(insn, &r0); + ptr =3D (void *)regs[r0]; + if (!ptr) { + return 0; + } + tb_ptr =3D ptr; + break; + case INDEX_op_qemu_ld_i32: if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { tci_args_rrm(insn, &r0, &r1, &oi); @@ -995,6 +1009,11 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); break; =20 + case INDEX_op_goto_ptr: + tci_args_r(insn, &r0); + info->fprintf_func(info->stream, "%-12s %s", op_name, str_r(r0)); + break; + case INDEX_op_call: tci_args_nl(insn, tb_ptr, &len, &ptr); info->fprintf_func(info->stream, "%-12s %d,%p", op_name, len, ptr= ); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 0df8384be7..db29bc6e54 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -27,6 +27,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { switch (op) { + case INDEX_op_goto_ptr: + return C_O0_I1(r); + case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: @@ -263,6 +266,15 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, = void *p0) tcg_out32(s, insn); } =20 +static void tcg_out_op_r(TCGContext *s, TCGOpcode op, TCGReg r0) +{ + tcg_insn_unit insn =3D 0; + + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + tcg_out32(s, insn); +} + static void tcg_out_op_v(TCGContext *s, TCGOpcode op) { tcg_out32(s, (uint8_t)op); @@ -567,6 +579,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, set_jmp_reset_offset(s, args[0]); break; =20 + case INDEX_op_goto_ptr: + tcg_out_op_r(s, opc, args[0]); + break; + case INDEX_op_br: tcg_out_op_l(s, opc, arg_label(args[0])); break; --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613596790638981.6579568635634; Wed, 17 Feb 2021 13:19:50 -0800 (PST) Received: from localhost ([::1]:51868 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCUEf-0002GV-Hj for importer@patchew.org; Wed, 17 Feb 2021 16:19:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33776) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTN2-00021j-GG for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:24:24 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:41235) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTMv-0007l8-9f for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:24:24 -0500 Received: by mail-pl1-x62e.google.com with SMTP id a9so5914820plh.8 for ; Wed, 17 Feb 2021 12:24:16 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t8YgkJ1JSVwTBJ9tGciCHNpn3ZeG9bxQ1lhsPKyTifo=; b=ymO3OERGwGuTiHzKPjR1oRqsdy0/Zl3+UzJ/O4a3M0/XbZ3/YnbNDSwuh6ReUmP6dL DUxH+Aci70UGvExdFUOnLoGOJts1UJbGSo87Jl1krl4HwkCJYl0iHVr4si0uJ3iTz5wc l99RDO48VtRETDJld4ntcaz0bqiDyZLKUjLXLq3qc4lyLaMzRalyDb/7DForSbteO2EJ jEzSqp2ahnbRBPfQlacen2NuWiyBUz0v8MT1Y9DhdXHAFf3znk1Yz5n8m9smvVqGObuq PSTjF4E26OddzPAYGf2c14UUw++zr5Obo7ZxEipc/zol83rZ4j8igpSVRTx4xj4pIASi LAZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t8YgkJ1JSVwTBJ9tGciCHNpn3ZeG9bxQ1lhsPKyTifo=; b=JCkPBQh4m/0noYlH1ZFycXJP7JFLb1Tn3IcsPjmaQBkpQ8IstYRq7+7FjYP9DlCq55 FgRJ6VKXWto7JkH1VmOqG8IXgC43iWk2T+Ps0qwTTLlFtHhmTKDSFhk1p4uRfrfOzCWY O1GFsjIxn5CopwaLpyMhenvT/erbDxIlHuJzc9uvXbIltwqELy5l6ROxC9Hdo4V4imVs CDJJ6ZD+e5RNwnpUmU1WUuEMPL7RRsIPXeOB2BTo6MKmqWsb+kbAZ1BobEOwIhQvjtuh NLwZfHAAQwmUEBZWxN+npMK7syQkv2UDbbGJMUb5Ai+29mPf/5fZ5xjAtILUKMsFDLlg RApA== X-Gm-Message-State: AOAM533v8cwOzZaBcl7gAlYmXNLIs0X2rQrPiLbj6Ob3q7Mq3fpkhWoi vvv0qli/i76r6Elhekjc2hv13PmVjvZuYQ== X-Google-Smtp-Source: ABdhPJzpCNQ7j+qMoqrwqZpAGgofeseH8ZYuqb1fRrnn1npnkJW7te3ArsNqait2o/iLfqvMHnRO5w== X-Received: by 2002:a17:903:2292:b029:de:45c0:7005 with SMTP id b18-20020a1709032292b02900de45c07005mr718093plh.75.1613593456180; Wed, 17 Feb 2021 12:24:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 63/71] tcg/tci: Implement movcond Date: Wed, 17 Feb 2021 12:20:28 -0800 Message-Id: <20210217202036.1724901-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" When this opcode is not available in the backend, tcg middle-end will expand this as a series of 5 opcodes. So implementing this saves bytecode space. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 4 ++-- tcg/tci.c | 16 +++++++++++++++- tcg/tci/tcg-target.c.inc | 10 +++++++--- 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 17911d3297..f53773a555 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -82,7 +82,7 @@ #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_orc_i32 0 #define TCG_TARGET_HAS_rot_i32 1 -#define TCG_TARGET_HAS_movcond_i32 0 +#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 @@ -119,7 +119,7 @@ #define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_orc_i64 0 #define TCG_TARGET_HAS_rot_i64 1 -#define TCG_TARGET_HAS_movcond_i64 0 +#define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_add2_i32 0 #define TCG_TARGET_HAS_sub2_i32 0 diff --git a/tcg/tci.c b/tcg/tci.c index c229050c66..2391dd4d3b 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -169,6 +169,7 @@ static void tci_args_rrrr(uint32_t insn, *r2 =3D extract32(insn, 16, 4); *r3 =3D extract32(insn, 20, 4); } +#endif =20 static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) @@ -181,6 +182,7 @@ static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, = TCGReg *r1, *c5 =3D extract32(insn, 28, 4); } =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { @@ -421,6 +423,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] =3D tci_compare32(regs[r1], regs[r2], condition); break; + case INDEX_op_movcond_i32: + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); + tmp32 =3D tci_compare32(regs[r1], regs[r2], condition); + regs[r0] =3D regs[tmp32 ? r3 : r4]; + break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); @@ -433,6 +440,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] =3D tci_compare64(regs[r1], regs[r2], condition); break; + case INDEX_op_movcond_i64: + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); + tmp32 =3D tci_compare64(regs[r1], regs[r2], condition); + regs[r0] =3D regs[tmp32 ? r3 : r4]; + break; #endif CASE_32_64(mov) tci_args_rr(insn, &r0, &r1); @@ -1138,7 +1150,8 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) op_name, str_r(r0), str_r(r1), str_r(r2), pos, = len); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", @@ -1146,6 +1159,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) str_r(r3), str_r(r4), str_c(c)); break; =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_mulu2_i32: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index db29bc6e54..a0c458a60a 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -133,9 +133,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpco= de op) return C_O0_I4(r, r, r, r); case INDEX_op_mulu2_i32: return C_O2_I2(r, r, r, r); +#endif + + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: return C_O1_I4(r, r, r, r, r); -#endif =20 case INDEX_op_qemu_ld_i32: return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS @@ -419,6 +422,7 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, insn =3D deposit32(insn, 20, 4, r3); tcg_out32(s, insn); } +#endif =20 static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, @@ -436,6 +440,7 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode = op, tcg_out32(s, insn); } =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGReg r5) @@ -591,12 +596,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, tcg_out_op_rrrc(s, opc, args[0], args[1], args[2], args[3]); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 + CASE_32_64(movcond) case INDEX_op_setcond2_i32: tcg_out_op_rrrrrc(s, opc, args[0], args[1], args[2], args[3], args[4], args[5]); break; -#endif =20 CASE_32_64(ld8u) CASE_32_64(ld8s) --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613596832; cv=none; d=zohomail.com; s=zohoarc; b=hXA/nve6pfElMgHg6oxL575Mx771LQlo1jFyoBsPxcF/wZqot/3hnB5ioWEcQdA2G9BXnKwg7vNQz6qZ79Z/0FwVmOXjsyJ8cZuNBh4AKUejWNZOd4rzhxCC6SW+Q87B2B0stEQeZdaACy5rJ2cXQCiduWb5gjiFVdumf9DKixQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613596832; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8UhCzfaKYlwmE690TaVTdGnsli7nQ9Ath2fy3ZA2wa8=; b=Hj0VyHzgSwAw4SFj+NbaKDDUaMW5yGFQ6Ta5RQ6+t1tJbBJDkuhHiDZk9uCWdOi1Uf83wPvJjxeDRPPZnc4oFAi4rKb9db3ZNT4ifUeV1D9Yd4LtVi7vTxznpZrgzA0V2kpjgyo6Wb17lcvW/VOahYrBdl0hDg7bmLz0bkjjfXM= ARC-Authentication-Results: i=1; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8UhCzfaKYlwmE690TaVTdGnsli7nQ9Ath2fy3ZA2wa8=; b=AP3b9FxbA0Vkh8EdThmuZDPiknz3Nl/Lig36mk3YIOaZ0ATiXMcQ5AY3c8Bo7ya+30 /SBoMDyISVQXRDTOrJzWF+LqlPKlU+K4Z8ddkbi7HI8639XcBKSemww3g7DXcWy9swmF +Kp2mKpJzbfadj7VCSMduNdV7YD4OPclFSPfKw90sCKg3D86rqHRXjyMf60MF3NOMtO/ SWbQC/FWOKczJMxfaZ/MwEk8iQ4tA4+dOo+O0XrUEbJj6IT8p9N4qUqxNQHimjdO0Me5 lg8wwOoil+UsGGXCghEbJLA7jUNXqTr8q9TS4/KAgXhSYmIy+9XVtXdKGEDQ0B7A53Jr xkbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8UhCzfaKYlwmE690TaVTdGnsli7nQ9Ath2fy3ZA2wa8=; b=ib+dR3iSsRf4hzyG+gQ16Hda9J1FuV0W/tsNuI4ydrdfHggGjIH4tazNs//3J+0qaM HfLpJPZRrAfT5R78H52NaSun1gtsouxrqW9NB5aGE6dRmEaqy2zbfft00rpy1fsnh/sw vgGahF4uD6rEBw86V4Qnt940RJnvacAW8FYP+QRFeXNNLQVzLo/wN71Z7LmN1n4uVn3V ArfuPHbxZlkkskEsYgXBxnbrhGk3lZqTJJVzIifJTkp4CmSwqKo5YyIgwpX83Dr1pViv ZVFYNvQ+MN2AeWTx5XT7viJY0knqEUVdHleBWSftKJWczjZ9MyTAAUAiroSYBVc1685w o30Q== X-Gm-Message-State: AOAM532QSU/APEkBrykenpO3OZFbCJxP8uqp5jE3FwPdDUBTZ+HsrOcT ux3LTClr1faJpcJvFHrWIC9osFDo5N7E/g== X-Google-Smtp-Source: ABdhPJzB0wiV9lhQFtLuP8QRHFADFqhC+i99J/qn66sEn8rmlKhlU8ZH1PXCBhw4nGWwLXFser5yEA== X-Received: by 2002:a17:902:d48b:b029:e1:f87:265d with SMTP id c11-20020a170902d48bb02900e10f87265dmr669310plg.1.1613593457668; Wed, 17 Feb 2021 12:24:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 64/71] tcg/tci: Implement andc, orc, eqv, nand, nor Date: Wed, 17 Feb 2021 12:20:29 -0800 Message-Id: <20210217202036.1724901-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" These were already present in tcg-target.c.inc, but not in the interpreter. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 20 ++++++++++---------- tcg/tci.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 10 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index f53773a555..5945272a43 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -67,20 +67,20 @@ #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 #define TCG_TARGET_HAS_ext16u_i32 1 -#define TCG_TARGET_HAS_andc_i32 0 +#define TCG_TARGET_HAS_andc_i32 1 #define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_extract_i32 0 #define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_extract2_i32 0 -#define TCG_TARGET_HAS_eqv_i32 0 -#define TCG_TARGET_HAS_nand_i32 0 -#define TCG_TARGET_HAS_nor_i32 0 +#define TCG_TARGET_HAS_eqv_i32 1 +#define TCG_TARGET_HAS_nand_i32 1 +#define TCG_TARGET_HAS_nor_i32 1 #define TCG_TARGET_HAS_clz_i32 0 #define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_ctpop_i32 0 #define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_not_i32 1 -#define TCG_TARGET_HAS_orc_i32 0 +#define TCG_TARGET_HAS_orc_i32 1 #define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_muls2_i32 0 @@ -108,16 +108,16 @@ #define TCG_TARGET_HAS_ext8u_i64 1 #define TCG_TARGET_HAS_ext16u_i64 1 #define TCG_TARGET_HAS_ext32u_i64 1 -#define TCG_TARGET_HAS_andc_i64 0 -#define TCG_TARGET_HAS_eqv_i64 0 -#define TCG_TARGET_HAS_nand_i64 0 -#define TCG_TARGET_HAS_nor_i64 0 +#define TCG_TARGET_HAS_andc_i64 1 +#define TCG_TARGET_HAS_eqv_i64 1 +#define TCG_TARGET_HAS_nand_i64 1 +#define TCG_TARGET_HAS_nor_i64 1 #define TCG_TARGET_HAS_clz_i64 0 #define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_ctpop_i64 0 #define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_not_i64 1 -#define TCG_TARGET_HAS_orc_i64 0 +#define TCG_TARGET_HAS_orc_i64 1 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_muls2_i64 0 diff --git a/tcg/tci.c b/tcg/tci.c index 2391dd4d3b..02fad3370d 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -530,6 +530,36 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] ^ regs[r2]; break; +#if TCG_TARGET_HAS_andc_i32 || TCG_TARGET_HAS_andc_i64 + CASE_32_64(andc) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] & ~regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_orc_i32 || TCG_TARGET_HAS_orc_i64 + CASE_32_64(orc) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] | ~regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64 + CASE_32_64(eqv) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D ~(regs[r1] ^ regs[r2]); + break; +#endif +#if TCG_TARGET_HAS_nand_i32 || TCG_TARGET_HAS_nand_i64 + CASE_32_64(nand) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D ~(regs[r1] & regs[r2]); + break; +#endif +#if TCG_TARGET_HAS_nor_i32 || TCG_TARGET_HAS_nor_i64 + CASE_32_64(nor) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D ~(regs[r1] | regs[r2]); + break; +#endif =20 /* Arithmetic operations (32 bit). */ =20 @@ -1120,6 +1150,16 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + case INDEX_op_eqv_i32: + case INDEX_op_eqv_i64: + case INDEX_op_nand_i32: + case INDEX_op_nand_i64: + case INDEX_op_nor_i32: + case INDEX_op_nor_i64: case INDEX_op_div_i32: case INDEX_op_div_i64: case INDEX_op_rem_i32: --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R3Xq5mi4KWyitR5salt2lYEIY+qV+wkNAizGGObuYbw=; b=A1ND+q4F65vaNYZjdYj9bdTNS0sWiL2hTnhKQ5S6/739VPDBTuYio2Gg/Xc0AkI6Ue GzGC5WIq3CR0W60ZZKuRA7SfXc26YPAWsK1hH6cebjzaaoIHVX686rfOnruALWZUqrYl sL1T1Q9mw8yJj7Iov8bzkkH5OxDwotyDVIV0KURBWPwujhBuxSA+koDjrTB20F6HEtm4 d3PktVbQCf/LKIaXM/nnUCMTTSbBsTjdHg23Arx5FwIFLY4H8qzcXixS+1QWCVYyNZwE NfkSe0chudlZ5HT3UQk5OD6k6iI8TMhVFULFNymdq/1mnP3Ol3A1FUN2gGEQv25sAQ+j XrYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R3Xq5mi4KWyitR5salt2lYEIY+qV+wkNAizGGObuYbw=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 8 ++++---- tcg/tci.c | 42 ++++++++++++++++++++++++++++++++++++++++ tcg/tci/tcg-target.c.inc | 32 ++++++++++++++++++++++++++++++ 3 files changed, 78 insertions(+), 4 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 5945272a43..60b67b196b 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -69,8 +69,8 @@ #define TCG_TARGET_HAS_ext16u_i32 1 #define TCG_TARGET_HAS_andc_i32 1 #define TCG_TARGET_HAS_deposit_i32 1 -#define TCG_TARGET_HAS_extract_i32 0 -#define TCG_TARGET_HAS_sextract_i32 0 +#define TCG_TARGET_HAS_extract_i32 1 +#define TCG_TARGET_HAS_sextract_i32 1 #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_eqv_i32 1 #define TCG_TARGET_HAS_nand_i32 1 @@ -97,8 +97,8 @@ #define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_deposit_i64 1 -#define TCG_TARGET_HAS_extract_i64 0 -#define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_extract_i64 1 +#define TCG_TARGET_HAS_sextract_i64 1 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_rem_i64 1 diff --git a/tcg/tci.c b/tcg/tci.c index 02fad3370d..dcf8dc418f 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -122,6 +122,15 @@ static void tci_args_rrs(uint32_t insn, TCGReg *r0, TC= GReg *r1, int32_t *i2) *i2 =3D sextract32(insn, 16, 16); } =20 +static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, + uint8_t *i2, uint8_t *i3) +{ + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *i2 =3D extract32(insn, 16, 6); + *i3 =3D extract32(insn, 22, 6); +} + static void tci_args_rrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { @@ -609,6 +618,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] =3D deposit32(regs[r1], pos, len, regs[r2]); break; +#endif +#if TCG_TARGET_HAS_extract_i32 + case INDEX_op_extract_i32: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] =3D extract32(regs[r1], pos, len); + break; +#endif +#if TCG_TARGET_HAS_sextract_i32 + case INDEX_op_sextract_i32: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] =3D sextract32(regs[r1], pos, len); + break; #endif case INDEX_op_brcond_i32: tci_args_rl(insn, tb_ptr, &r0, &ptr); @@ -749,6 +770,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] =3D deposit64(regs[r1], pos, len, regs[r2]); break; +#endif +#if TCG_TARGET_HAS_extract_i64 + case INDEX_op_extract_i64: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] =3D extract64(regs[r1], pos, len); + break; +#endif +#if TCG_TARGET_HAS_sextract_i64 + case INDEX_op_sextract_i64: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] =3D sextract64(regs[r1], pos, len); + break; #endif case INDEX_op_brcond_i64: tci_args_rl(insn, tb_ptr, &r0, &ptr); @@ -1190,6 +1223,15 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) op_name, str_r(r0), str_r(r1), str_r(r2), pos, = len); break; =20 + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + case INDEX_op_sextract_i32: + case INDEX_op_sextract_i64: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + info->fprintf_func(info->stream, "%-12s %s,%s,%d,%d", + op_name, str_r(r0), str_r(r1), pos, len); + break; + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index a0c458a60a..cedd0328df 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -63,6 +63,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode= op) case INDEX_op_bswap32_i32: case INDEX_op_bswap32_i64: case INDEX_op_bswap64_i64: + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + case INDEX_op_sextract_i32: + case INDEX_op_sextract_i64: return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: @@ -352,6 +356,21 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, tcg_out32(s, insn); } =20 +static void tcg_out_op_rrbb(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, uint8_t b2, uint8_t b3) +{ + tcg_insn_unit insn =3D 0; + + tcg_debug_assert(b2 =3D=3D extract32(b2, 0, 6)); + tcg_debug_assert(b3 =3D=3D extract32(b3, 0, 6)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 6, b2); + insn =3D deposit32(insn, 22, 6, b3); + tcg_out32(s, insn); +} + static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { @@ -653,6 +672,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, } break; =20 + CASE_32_64(extract) /* Optional (TCG_TARGET_HAS_extract_*). */ + CASE_32_64(sextract) /* Optional (TCG_TARGET_HAS_sextract_*). */ + { + TCGArg pos =3D args[2], len =3D args[3]; + TCGArg max =3D tcg_op_defs[opc].flags & TCG_OPF_64BIT ? 64 : 3= 2; + + tcg_debug_assert(pos < max); + tcg_debug_assert(pos + len <=3D max); + + tcg_out_op_rrbb(s, opc, args[0], args[1], pos, len); + } + break; + CASE_32_64(brcond) tcg_out_op_rrrc(s, (opc =3D=3D INDEX_op_brcond_i32 ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 12 +++++------ tcg/tci.c | 44 ++++++++++++++++++++++++++++++++++++++++ tcg/tci/tcg-target.c.inc | 9 ++++++++ 3 files changed, 59 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 60b67b196b..59859bd8a6 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -75,9 +75,9 @@ #define TCG_TARGET_HAS_eqv_i32 1 #define TCG_TARGET_HAS_nand_i32 1 #define TCG_TARGET_HAS_nor_i32 1 -#define TCG_TARGET_HAS_clz_i32 0 -#define TCG_TARGET_HAS_ctz_i32 0 -#define TCG_TARGET_HAS_ctpop_i32 0 +#define TCG_TARGET_HAS_clz_i32 1 +#define TCG_TARGET_HAS_ctz_i32 1 +#define TCG_TARGET_HAS_ctpop_i32 1 #define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_orc_i32 1 @@ -112,9 +112,9 @@ #define TCG_TARGET_HAS_eqv_i64 1 #define TCG_TARGET_HAS_nand_i64 1 #define TCG_TARGET_HAS_nor_i64 1 -#define TCG_TARGET_HAS_clz_i64 0 -#define TCG_TARGET_HAS_ctz_i64 0 -#define TCG_TARGET_HAS_ctpop_i64 0 +#define TCG_TARGET_HAS_clz_i64 1 +#define TCG_TARGET_HAS_ctz_i64 1 +#define TCG_TARGET_HAS_ctpop_i64 1 #define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_orc_i64 1 diff --git a/tcg/tci.c b/tcg/tci.c index dcf8dc418f..068d742a80 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -588,6 +588,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint32_t)regs[r1] % (uint32_t)regs[r2]; break; +#if TCG_TARGET_HAS_clz_i32 + case INDEX_op_clz_i32: + tci_args_rrr(insn, &r0, &r1, &r2); + tmp32 =3D regs[r1]; + regs[r0] =3D tmp32 ? clz32(tmp32) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctz_i32 + case INDEX_op_ctz_i32: + tci_args_rrr(insn, &r0, &r1, &r2); + tmp32 =3D regs[r1]; + regs[r0] =3D tmp32 ? ctz32(tmp32) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctpop_i32 + case INDEX_op_ctpop_i32: + tci_args_rr(insn, &r0, &r1); + regs[r0] =3D ctpop32(regs[r1]); + break; +#endif =20 /* Shift/rotate operations (32 bit). */ =20 @@ -740,6 +760,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint64_t)regs[r1] % (uint64_t)regs[r2]; break; +#if TCG_TARGET_HAS_clz_i64 + case INDEX_op_clz_i64: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] ? clz64(regs[r1]) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctz_i64 + case INDEX_op_ctz_i64: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] ? ctz64(regs[r1]) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctpop_i64 + case INDEX_op_ctpop_i64: + tci_args_rr(insn, &r0, &r1); + regs[r0] =3D ctpop64(regs[r1]); + break; +#endif =20 /* Shift/rotate operations (64 bit). */ =20 @@ -1166,6 +1204,8 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) case INDEX_op_not_i64: case INDEX_op_neg_i32: case INDEX_op_neg_i64: + case INDEX_op_ctpop_i32: + case INDEX_op_ctpop_i64: tci_args_rr(insn, &r0, &r1); info->fprintf_func(info->stream, "%-12s %s,%s", op_name, str_r(r0), str_r(r1)); @@ -1211,6 +1251,10 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: + case INDEX_op_clz_i32: + case INDEX_op_clz_i64: + case INDEX_op_ctz_i32: + case INDEX_op_ctz_i64: tci_args_rrr(insn, &r0, &r1, &r2); info->fprintf_func(info->stream, "%-12s %s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2)); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index cedd0328df..664d715440 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -67,6 +67,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode = op) case INDEX_op_extract_i64: case INDEX_op_sextract_i32: case INDEX_op_sextract_i64: + case INDEX_op_ctpop_i32: + case INDEX_op_ctpop_i64: return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: @@ -122,6 +124,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpco= de op) case INDEX_op_setcond_i64: case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: + case INDEX_op_clz_i32: + case INDEX_op_clz_i64: + case INDEX_op_ctz_i32: + case INDEX_op_ctz_i64: return C_O1_I2(r, r, r); =20 case INDEX_op_brcond_i32: @@ -657,6 +663,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(clz) /* Optional (TCG_TARGET_HAS_clz_*). */ + CASE_32_64(ctz) /* Optional (TCG_TARGET_HAS_ctz_*). */ tcg_out_op_rrr(s, opc, args[0], args[1], args[2]); break; =20 @@ -705,6 +713,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ + CASE_32_64(ctpop) /* Optional (TCG_TARGET_HAS_ctpop_*). */ tcg_out_op_rr(s, opc, args[0], args[1]); break; =20 --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613597314; cv=none; d=zohomail.com; s=zohoarc; b=WZ4zpU6H/go2DLlcDYUGTMqZyHkUhY1Jz14T/yLQ7kUZhNQWoVifAxVSd3ePL/Pe6Rh0AL08T6njxfOvAQZHwuzFjE8kQ/+xGi5VYmjo2pmgKgejrJPaOZC3r/mBvndzOb9lpP+AeLFnB0FMeOwjyIMEhLNRPFldGsNoXZaQ3M4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613597314; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6h+sAi9+UBX8LOTQXXAtVUgZ0by5F5omnkIi0WF53fQ=; b=PRPbBChlR8eG02CPQOPyWL4VFa+E5iTl4cTkM0ya7fHONsQdsI2KoqfXKVGnqQuyKqB3F+eifP9kI9uv2EDhxUGR1paW/DTDrrMa39ZtlqbNZIwUyuxhRJx+JsR+eKDBKCC/dcv+aaMCvH/QbxxdRtRCeksXZirG3lLk9NMbT/4= ARC-Authentication-Results: i=1; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6h+sAi9+UBX8LOTQXXAtVUgZ0by5F5omnkIi0WF53fQ=; b=bNUL/Q+ekH+VJXWI9AaIOo+mUn2RrgChgTboOXpR+GFjSkH4wpAAX4K3fbBlLOPVYs YDtD6Mipk3NILbGcKFxpns413YYDp+7xoQb6UwxaQ6jWAWdeA8kCu3MzQv49rFD3dC9A z+S9S9OVdEBPZzJm3K4Cd2S55Nm6Mo0hEfbZvfeKPQZhKTGiOJGxoQWN9D9edKl6sx1u 1ru1d8llu1+AVU9U+bSplXnkYCcwUD19ZTlB3/gwTrOBKflMRmLWy2yH1GIduEOOYdx0 240ngl8vuS5aWDlb4VfJizbGIH82cao/D/xEl7gY9fAafyqxHhwvWvEaIj96lMfR+kew iZXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6h+sAi9+UBX8LOTQXXAtVUgZ0by5F5omnkIi0WF53fQ=; b=VzN3zWL+zxg1lOGrVY4HZ1Z5ismu7Sdn0xMwld3eYnXPoj93DGqyjdTw8w59yslq5z f76fV/LbKJfQuWWHwnkF0K407mQxc2Z4Fsi2YI2yeL7uuTRseBJmPRhng/9LFmGrHweN +70QCjexGkUf29yruw2fv0RUMPP6qfYPbTSbdJshHKlr8Ii8k1JPIhpgqAJzdOSnRNf7 69UHZT5aFtboKiSD9RCrgowyQ1/+hhbb3TFXEEGFpcQiwZrAm47QZsHo0TyycAxNqVql eCZryrtMBCIPDallnAG/c/LWYM1Gyy5PTUplvzAG/lczb3xRApaGt6oZdljrQAKA8VVu mx+g== X-Gm-Message-State: AOAM533/5cvGnVmk6gSoWD8i9O6fSt1V5QiVxpQiYRsYyNhVVK37nsit vheIOst29l4Lnkv6rz5S2ipQDZwUKeKJiA== X-Google-Smtp-Source: ABdhPJz+42f95yLmaFwbSbKiNQ5hcW69gf7iabTeIJ7SNCv0quQypbcCmdkY5veZQKSFahDqhebmoQ== X-Received: by 2002:a62:aa06:0:b029:1ec:ec68:474a with SMTP id e6-20020a62aa060000b02901ecec68474amr949954pff.40.1613593462034; Wed, 17 Feb 2021 12:24:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 67/71] tcg/tci: Implement mulu2, muls2 Date: Wed, 17 Feb 2021 12:20:32 -0800 Message-Id: <20210217202036.1724901-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" We already had mulu2_i32 for a 32-bit host; expand this to 64-bit hosts as well. The muls2_i32 and the 64-bit opcodes are new. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 8 ++++---- tcg/tci.c | 35 +++++++++++++++++++++++++++++------ tcg/tci/tcg-target.c.inc | 16 ++++++++++------ 3 files changed, 43 insertions(+), 16 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 59859bd8a6..71a44bbfb0 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -83,7 +83,7 @@ #define TCG_TARGET_HAS_orc_i32 1 #define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 -#define TCG_TARGET_HAS_muls2_i32 0 +#define TCG_TARGET_HAS_muls2_i32 1 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 @@ -120,13 +120,13 @@ #define TCG_TARGET_HAS_orc_i64 1 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 -#define TCG_TARGET_HAS_muls2_i64 0 +#define TCG_TARGET_HAS_muls2_i64 1 #define TCG_TARGET_HAS_add2_i32 0 #define TCG_TARGET_HAS_sub2_i32 0 -#define TCG_TARGET_HAS_mulu2_i32 0 +#define TCG_TARGET_HAS_mulu2_i32 1 #define TCG_TARGET_HAS_add2_i64 0 #define TCG_TARGET_HAS_sub2_i64 0 -#define TCG_TARGET_HAS_mulu2_i64 0 +#define TCG_TARGET_HAS_mulu2_i64 1 #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 #else diff --git a/tcg/tci.c b/tcg/tci.c index 068d742a80..d76b9f5798 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -39,7 +39,7 @@ __thread uintptr_t tci_tb_ptr; static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, uint32_t low_index, uint64_t value) { - regs[low_index] =3D value; + regs[low_index] =3D (uint32_t)value; regs[high_index] =3D value >> 32; } =20 @@ -169,7 +169,6 @@ static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, T= CGReg *r1, *r4 =3D extract32(insn, 24, 4); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) { @@ -178,7 +177,6 @@ static void tci_args_rrrr(uint32_t insn, *r2 =3D extract32(insn, 16, 4); *r3 =3D extract32(insn, 20, 4); } -#endif =20 static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) @@ -670,11 +668,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, T2 =3D tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; +#endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ +#if TCG_TARGET_HAS_mulu2_i32 case INDEX_op_mulu2_i32: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); - tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); + tmp64 =3D (uint64_t)(uint32_t)regs[r2] * (uint32_t)regs[r3]; + tci_write_reg64(regs, r1, r0, tmp64); break; -#endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ +#endif +#if TCG_TARGET_HAS_muls2_i32 + case INDEX_op_muls2_i32: + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); + tmp64 =3D (int64_t)(int32_t)regs[r2] * (int32_t)regs[r3]; + tci_write_reg64(regs, r1, r0, tmp64); + break; +#endif #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) tci_args_rr(insn, &r0, &r1); @@ -778,6 +786,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, regs[r0] =3D ctpop64(regs[r1]); break; #endif +#if TCG_TARGET_HAS_mulu2_i64 + case INDEX_op_mulu2_i64: + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); + mulu64(®s[r0], ®s[r1], regs[r2], regs[r3]); + break; +#endif +#if TCG_TARGET_HAS_muls2_i64 + case INDEX_op_muls2_i64: + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); + muls64(®s[r0], ®s[r1], regs[r2], regs[r3]); + break; +#endif =20 /* Shift/rotate operations (64 bit). */ =20 @@ -1285,14 +1305,17 @@ int print_insn_tci(bfd_vma addr, disassemble_info *= info) str_r(r3), str_r(r4), str_c(c)); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_mulu2_i32: + case INDEX_op_mulu2_i64: + case INDEX_op_muls2_i32: + case INDEX_op_muls2_i64: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3)); break; =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 664d715440..eb48633fba 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -141,10 +141,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) return C_O2_I4(r, r, r, r, r, r); case INDEX_op_brcond2_i32: return C_O0_I4(r, r, r, r); - case INDEX_op_mulu2_i32: - return C_O2_I2(r, r, r, r); #endif =20 + case INDEX_op_mulu2_i32: + case INDEX_op_mulu2_i64: + case INDEX_op_muls2_i32: + case INDEX_op_muls2_i64: + return C_O2_I2(r, r, r, r); + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: @@ -434,7 +438,6 @@ static void tcg_out_op_rrrrr(TCGContext *s, TCGOpcode o= p, TCGReg r0, tcg_out32(s, insn); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) { @@ -447,7 +450,6 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, insn =3D deposit32(insn, 20, 4, r3); tcg_out32(s, insn); } -#endif =20 static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, @@ -728,10 +730,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, args[0], args[1], args[2], args[3], args[4]); tcg_out_op_rl(s, INDEX_op_brcond_i32, TCG_REG_TMP, arg_label(args[= 5])); break; - case INDEX_op_mulu2_i32: +#endif + + CASE_32_64(mulu2) + CASE_32_64(muls2) tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); break; -#endif =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_st_i32: --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BvlzLp6n+uhbL6lJ6/SY8kpsbMrMSqUUMDmNT2MwoZ8=; b=XUYJz6c/0O36rV4s7EvLpVM14yPiIAP7hl8n/tBJDRjX9C2p/LGhvkWOPUZsrfagvE S7tPKVxiZc9OyKbIv5z4T4baTj1pzBKYeL57Km3v9da5xWFnZdoOpS2ejanoUBay9hut aTWEm4/fxt7oYv9zWt/wh0RK0cxPAnk2iZ2BlLjONft6D0gVJlksB64SkRw0dmMtSI3U tjBcmbHIh/k+47A0/y8iySqQZ4CaKhaUnblMtCznHd6OoqFTxlkSNPi3rafLk1lvtpLa 8zuVjL80fKAKEis0rn7ozku8UoRsLFffQ4wiaCxQKjk3pLRtr4kZaHv7ffDjNgMTh+fX r1vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BvlzLp6n+uhbL6lJ6/SY8kpsbMrMSqUUMDmNT2MwoZ8=; b=ly2mj4tGM7sj0EH3sPM4tg2F+LhSqPhKdtl1GLPFktp+VuwnA0lkUPQCqVxPk7mjE8 0yP37YB2LsegmNtJVR+bup3iz1NcHJPZYAya2TB7eKGZ3KeH5D0VFtVsxOWZxhd3R1Aq BF1i2kW4cLdrEyXNu2GErvoDxQHwRs4E5XBLkExqrrCjppCx90tqCXKpAKo95MAwSF+h 0FLASHuUi6spXiXvPNLjWup9Mv+Bl/AZMnDIBOyb/wfyISGt7jebjDPQ0+NTr38pNddn OnRWJw03bBqLdDoekXKsqjAefcG/oTlFuKFCoZVDJW8XcARlpOXtfwv0Sd/+cjulvR1D Ab7A== X-Gm-Message-State: AOAM531Bmly8JG53wYqzusQkw5Kx5M5xkQa0zaTHRJW/fs5pSM7mE22F DZU4hQEtFEQCy921G5OLMQnBBmKLBIR/vg== X-Google-Smtp-Source: ABdhPJzZK8YKK2q5YLf/MkAKIlGOSlDeC9Ru8XYquNL7a6IFXTWLxCOWGhKg8vDXGT6ftJffuAzB/A== X-Received: by 2002:a62:5344:0:b029:1df:c7d:3c3e with SMTP id h65-20020a6253440000b02901df0c7d3c3emr930260pfb.11.1613593463689; Wed, 17 Feb 2021 12:24:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 68/71] tcg/tci: Implement add2, sub2 Date: Wed, 17 Feb 2021 12:20:33 -0800 Message-Id: <20210217202036.1724901-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" We already had the 32-bit versions for a 32-bit host; expand this to 64-bit hosts as well. The 64-bit opcodes are new. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 8 ++++---- tcg/tci.c | 40 ++++++++++++++++++++++++++-------------- tcg/tci/tcg-target.c.inc | 15 ++++++++------- 3 files changed, 38 insertions(+), 25 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 71a44bbfb0..515b3c7a56 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -121,11 +121,11 @@ #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_muls2_i64 1 -#define TCG_TARGET_HAS_add2_i32 0 -#define TCG_TARGET_HAS_sub2_i32 0 +#define TCG_TARGET_HAS_add2_i32 1 +#define TCG_TARGET_HAS_sub2_i32 1 #define TCG_TARGET_HAS_mulu2_i32 1 -#define TCG_TARGET_HAS_add2_i64 0 -#define TCG_TARGET_HAS_sub2_i64 0 +#define TCG_TARGET_HAS_add2_i64 1 +#define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_mulu2_i64 1 #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 diff --git a/tcg/tci.c b/tcg/tci.c index d76b9f5798..0240d850cf 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -189,7 +189,6 @@ static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, = TCGReg *r1, *c5 =3D extract32(insn, 28, 4); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { @@ -200,7 +199,6 @@ static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, = TCGReg *r1, *r4 =3D extract32(insn, 24, 4); *r5 =3D extract32(insn, 28, 4); } -#endif =20 static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { @@ -351,17 +349,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, for (;;) { uint32_t insn; TCGOpcode opc; - TCGReg r0, r1, r2, r3, r4; + TCGReg r0, r1, r2, r3, r4, r5; tcg_target_ulong t1; TCGCond condition; target_ulong taddr; uint8_t pos, len; uint32_t tmp32; uint64_t tmp64; -#if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r5; uint64_t T1, T2; -#endif TCGMemOpIdx oi; int32_t ofs; void *ptr; @@ -655,20 +650,22 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tb_ptr =3D ptr; } break; -#if TCG_TARGET_REG_BITS =3D=3D 32 +#if TCG_TARGET_REG_BITS =3D=3D 32 || TCG_TARGET_HAS_add2_i32 case INDEX_op_add2_i32: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 =3D tci_uint64(regs[r3], regs[r2]); T2 =3D tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 + T2); break; +#endif +#if TCG_TARGET_REG_BITS =3D=3D 32 || TCG_TARGET_HAS_sub2_i32 case INDEX_op_sub2_i32: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 =3D tci_uint64(regs[r3], regs[r2]); T2 =3D tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; -#endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ +#endif #if TCG_TARGET_HAS_mulu2_i32 case INDEX_op_mulu2_i32: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); @@ -798,6 +795,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, muls64(®s[r0], ®s[r1], regs[r2], regs[r3]); break; #endif +#if TCG_TARGET_HAS_add2_i64 + case INDEX_op_add2_i64: + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); + T1 =3D regs[r2] + regs[r4]; + T2 =3D regs[r3] + regs[r5] + (T1 < regs[r2]); + regs[r0] =3D T1; + regs[r1] =3D T2; + break; +#endif +#if TCG_TARGET_HAS_add2_i64 + case INDEX_op_sub2_i64: + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); + T1 =3D regs[r2] - regs[r4]; + T2 =3D regs[r3] - regs[r5] - (regs[r2] < regs[r4]); + regs[r0] =3D T1; + regs[r1] =3D T2; + break; +#endif =20 /* Shift/rotate operations (64 bit). */ =20 @@ -1114,10 +1129,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) const char *op_name; uint32_t insn; TCGOpcode op; - TCGReg r0, r1, r2, r3, r4; -#if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r5; -#endif + TCGReg r0, r1, r2, r3, r4, r5; tcg_target_ulong i1; int32_t s2; TCGCond c; @@ -1315,15 +1327,15 @@ int print_insn_tci(bfd_vma addr, disassemble_info *= info) str_r(r2), str_r(r3)); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: + case INDEX_op_add2_i64: case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3), str_r(r4), str_r(r5)); break; -#endif =20 case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index eb48633fba..9b2e2c32a1 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -134,11 +134,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_brcond_i64: return C_O0_I2(r, r); =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 - /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */ case INDEX_op_add2_i32: + case INDEX_op_add2_i64: case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: return C_O2_I4(r, r, r, r, r, r); + +#if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_brcond2_i32: return C_O0_I4(r, r, r, r); #endif @@ -467,7 +469,6 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode = op, tcg_out32(s, insn); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGReg r5) @@ -483,7 +484,6 @@ static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode = op, insn =3D deposit32(insn, 28, 4, r5); tcg_out32(s, insn); } -#endif =20 static void tcg_out_ldst(TCGContext *s, TCGOpcode op, TCGReg val, TCGReg base, intptr_t offset) @@ -719,12 +719,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, tcg_out_op_rr(s, opc, args[0], args[1]); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 - case INDEX_op_add2_i32: - case INDEX_op_sub2_i32: + CASE_32_64(add2) + CASE_32_64(sub2) tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2], args[3], args[4], args[5]); break; + +#if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_brcond2_i32: tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, TCG_REG_TMP, args[0], args[1], args[2], args[3], args[4]); --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613597454635808.2011442633057; Wed, 17 Feb 2021 13:30:54 -0800 (PST) Received: from localhost ([::1]:55556 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCUPN-0007Iq-5B for importer@patchew.org; Wed, 17 Feb 2021 16:30:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33868) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTN6-0002AQ-RI for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:24:28 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:45785) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTN4-0007nu-OX for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:24:28 -0500 Received: by mail-pl1-x630.google.com with SMTP id b8so8025050plh.12 for ; Wed, 17 Feb 2021 12:24:26 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ao4OKRpDcfbemUwRIlrAeEvX8kliF+Y+aAzUNEwCXa8=; b=eyMui52Z2F1gzx2Hv36MkxyPyM2WsKbQ0ALQoEIITJ280Bw4V27wwuDom0Bl6frh+5 ZSEMPLRVR24qFQGyKxYtcyP/iZVxhWkOMw8ZzjjvWMLaXODD35un0trJecEf+A9JNlZ3 AC/QP1SjQUqsxTTTlj2qUthQZVtYtyuz9PnxusBXipFfVcUZD9SWQJxPYNPV7fsbKQWB bWpL967Jyoi0Vebd5u61zKvph2GGRwEtX7ykxqaKCc+nzqbZD6R3hH1MXAZKBCtO3CHP CnqPlaQCn/AzsFATGrjCHyk75dlLSgXrrMz3J+qHFSJftWFY5ev1R8p2RqLyWaXZoeMd RRmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ao4OKRpDcfbemUwRIlrAeEvX8kliF+Y+aAzUNEwCXa8=; b=feGR4bUHqu69/MFOfe4eHLiBAvETLSaRiSn+jzXEq53CEwrE8uLzqEJly4O5pEfnMy x3oZ5gBpan8hIqKSZisZbKVV/DgvMx6E29rt1bgH9S1LMFHJd03yyqai3FG7Mde2lQ61 BeHMnEYPNVYwIF18OkhjZQEgROMfqgw2vFuhP81xyNqyshGm2/jf6gstU8Mz3LLbRE2x 4SEGnM4YhWawkg+zkwML6xeVx2fiXLt9pfHp1MQAQHhf+ObGxdChlvWzoKPSoucNHAj1 Glx6vuTZe6WWpE/Fzc3usXwfa+IQYf9GLC+nUWjX2D/8RDcHrCW1tMP0EYdtryNQ6fPq 286w== X-Gm-Message-State: AOAM533Q8zqPA2nXFgkM431xRBXVgvLBcjojELgvCgNovp7TPPkOfcFZ XKrhbtEqD3re6GnMLbvFYsTvPx/2Y9ivgA== X-Google-Smtp-Source: ABdhPJy5EcKvFwg4eLeU9pNXoNQB96yTRg5u9xjvSOUnLQEqgoySuHTyTxo4/ju8Tr4XAOdNPnDvPA== X-Received: by 2002:a17:90b:4b02:: with SMTP id lx2mr561479pjb.178.1613593465361; Wed, 17 Feb 2021 12:24:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 69/71] tcg/tci: Split out tci_qemu_ld, tci_qemu_st Date: Wed, 17 Feb 2021 12:20:34 -0800 Message-Id: <20210217202036.1724901-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Expand the single-use macros into the new functions. Use cpu_ldsb_mmuidx_ra and cpu_ldsw_le_mmuidx_ra so that the trace event receives the correct sign flag. Signed-off-by: Richard Henderson --- tcg/tci.c | 215 +++++++++++++++++++----------------------------------- 1 file changed, 75 insertions(+), 140 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 0240d850cf..84bef41af3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -284,34 +284,77 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, T= CGCond condition) return result; } =20 -#define qemu_ld_ub \ - cpu_ldub_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_leuw \ - cpu_lduw_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_leul \ - cpu_ldl_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_leq \ - cpu_ldq_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_beuw \ - cpu_lduw_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_beul \ - cpu_ldl_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_beq \ - cpu_ldq_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_b(X) \ - cpu_stb_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_lew(X) \ - cpu_stw_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_lel(X) \ - cpu_stl_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_leq(X) \ - cpu_stq_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_bew(X) \ - cpu_stw_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_bel(X) \ - cpu_stl_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_beq(X) \ - cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr, + TCGMemOpIdx oi, const void *tb_ptr) +{ + uintptr_t ra =3D (uintptr_t)tb_ptr; + int mmu_idx =3D get_mmuidx(oi); + MemOp mop =3D get_memop(oi); + + switch (mop & (MO_BSWAP | MO_SSIZE)) { + case MO_UB: + return cpu_ldub_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_SB: + return cpu_ldsb_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_LEUW: + return cpu_lduw_le_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_BEUW: + return cpu_lduw_be_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_LESW: + return cpu_ldsw_le_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_BESW: + return cpu_ldsw_be_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_LEUL: + return cpu_ldl_le_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_BEUL: + return cpu_ldl_be_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_LESL: + return (int32_t)cpu_ldl_le_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_BESL: + return (int32_t)cpu_ldl_be_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_LEQ: + return cpu_ldq_le_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_BEQ: + return cpu_ldq_be_mmuidx_ra(env, taddr, mmu_idx, ra); + + default: + g_assert_not_reached(); + } +} + +static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t va= l, + TCGMemOpIdx oi, const void *tb_ptr) +{ + uintptr_t ra =3D (uintptr_t)tb_ptr; + int mmu_idx =3D get_mmuidx(oi); + MemOp mop =3D get_memop(oi); + + switch (mop & (MO_BSWAP | MO_SIZE)) { + case MO_UB: + cpu_stb_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + case MO_LEUW: + cpu_stw_le_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + case MO_BEUW: + cpu_stw_be_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + case MO_LEUL: + cpu_stl_le_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + case MO_BEUL: + cpu_stl_be_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + case MO_LEQ: + cpu_stq_le_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + case MO_BEQ: + cpu_stq_be_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + default: + g_assert_not_reached(); + } +} =20 #if TCG_TARGET_REG_BITS =3D=3D 64 # define CASE_32_64(x) \ @@ -908,34 +951,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr =3D tci_uint64(regs[r2], regs[r1]); } - switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { - case MO_UB: - tmp32 =3D qemu_ld_ub; - break; - case MO_SB: - tmp32 =3D (int8_t)qemu_ld_ub; - break; - case MO_LEUW: - tmp32 =3D qemu_ld_leuw; - break; - case MO_LESW: - tmp32 =3D (int16_t)qemu_ld_leuw; - break; - case MO_LEUL: - tmp32 =3D qemu_ld_leul; - break; - case MO_BEUW: - tmp32 =3D qemu_ld_beuw; - break; - case MO_BESW: - tmp32 =3D (int16_t)qemu_ld_beuw; - break; - case MO_BEUL: - tmp32 =3D qemu_ld_beul; - break; - default: - g_assert_not_reached(); - } + tmp32 =3D tci_qemu_ld(env, taddr, oi, tb_ptr); regs[r0] =3D tmp32; break; =20 @@ -951,46 +967,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, taddr =3D tci_uint64(regs[r3], regs[r2]); oi =3D regs[r4]; } - switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { - case MO_UB: - tmp64 =3D qemu_ld_ub; - break; - case MO_SB: - tmp64 =3D (int8_t)qemu_ld_ub; - break; - case MO_LEUW: - tmp64 =3D qemu_ld_leuw; - break; - case MO_LESW: - tmp64 =3D (int16_t)qemu_ld_leuw; - break; - case MO_LEUL: - tmp64 =3D qemu_ld_leul; - break; - case MO_LESL: - tmp64 =3D (int32_t)qemu_ld_leul; - break; - case MO_LEQ: - tmp64 =3D qemu_ld_leq; - break; - case MO_BEUW: - tmp64 =3D qemu_ld_beuw; - break; - case MO_BESW: - tmp64 =3D (int16_t)qemu_ld_beuw; - break; - case MO_BEUL: - tmp64 =3D qemu_ld_beul; - break; - case MO_BESL: - tmp64 =3D (int32_t)qemu_ld_beul; - break; - case MO_BEQ: - tmp64 =3D qemu_ld_beq; - break; - default: - g_assert_not_reached(); - } + tmp64 =3D tci_qemu_ld(env, taddr, oi, tb_ptr); if (TCG_TARGET_REG_BITS =3D=3D 32) { tci_write_reg64(regs, r1, r0, tmp64); } else { @@ -1007,25 +984,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, taddr =3D tci_uint64(regs[r2], regs[r1]); } tmp32 =3D regs[r0]; - switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { - case MO_UB: - qemu_st_b(tmp32); - break; - case MO_LEUW: - qemu_st_lew(tmp32); - break; - case MO_LEUL: - qemu_st_lel(tmp32); - break; - case MO_BEUW: - qemu_st_bew(tmp32); - break; - case MO_BEUL: - qemu_st_bel(tmp32); - break; - default: - g_assert_not_reached(); - } + tci_qemu_st(env, taddr, tmp32, oi, tb_ptr); break; =20 case INDEX_op_qemu_st_i64: @@ -1044,31 +1003,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchS= tate *env, } tmp64 =3D tci_uint64(regs[r1], regs[r0]); } - switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { - case MO_UB: - qemu_st_b(tmp64); - break; - case MO_LEUW: - qemu_st_lew(tmp64); - break; - case MO_LEUL: - qemu_st_lel(tmp64); - break; - case MO_LEQ: - qemu_st_leq(tmp64); - break; - case MO_BEUW: - qemu_st_bew(tmp64); - break; - case MO_BEUL: - qemu_st_bel(tmp64); - break; - case MO_BEQ: - qemu_st_beq(tmp64); - break; - default: - g_assert_not_reached(); - } + tci_qemu_st(env, taddr, tmp64, oi, tb_ptr); break; =20 case INDEX_op_mb: --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c8rHoeZKiC+7eBm3oTFadO1gEc0i538afGIZflXVo4w=; b=MePxeNbHN0QhcWIEXJzsKd74WDdoWYwDASNxSye19q6uFYly17eDZcudRSPUS5q7v2 eOfroM9yqjh2QIUShaMRmHLGPtPkxG6EpunC4CoktqPxRCZ0TLaGiV9qobZICURN1D5N JGOTE1lrpDwZoAbRWdFgYaUp3m2t1/IWklaLlgk26yzkTP+Zc9KikX0uuIIFs083o9c1 NzXov6QMbBhPrATiVVORxQQvmtrndAFoRy4QXWYdPjlhVB8F2s7wuLbcQzDocE+S6WuC 0j35Gqq1kks7uATaUbL5JayjQ0LWRZ8Lj42wNXtKqs0J2La5iRQudXFXMUg2epUbrg8+ VE9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c8rHoeZKiC+7eBm3oTFadO1gEc0i538afGIZflXVo4w=; b=a5+b1dg/QlFguy3Bk2UtNvk0Sy1RRq6CAqAjlfzpQNLx8tDETlvTQXLdEfqEYL/Zzd mMHUNCI+yjVFpl+2lC8tgSOGFJfftQIvY/t/76wlYdBaTnxAefOkacFazDWbe3XhMFSn v8IEviFcVi+LML2cf3rBAEpiTRLmyOPFxiIUe1r8E4yr4l+4hSai0pVkfX84jkJPS7jo QuHbT4ciCNOnzLSmJVEP+EIbBrbX2waTq0MLqHn+vOL3WoYQc8xawXvcXJ8HNg9QWcLM gS2Bds9Mn77Y4thGEX7D6k8g3BdxHblS2xGDgC6WQWoMkcoNL6P9DYk78esrcCuQ/J72 5eMQ== X-Gm-Message-State: AOAM532QjgH9IcMSfubJ6Mo/umf8gUBSeubM1rajGZsh6qnVsj3h1Io7 y3nvxPAsUJmwjrfGCK7uAVQ1rdxuSzeyIQ== X-Google-Smtp-Source: ABdhPJwA+VGMuSbPZaaffBxsMpK6HXMhJ8OC0lcWfKSPZ6QrZwrYZ5sCULYafcaL057nFsBSdy3OCw== X-Received: by 2002:aa7:94aa:0:b029:1eb:7783:69c5 with SMTP id a10-20020aa794aa0000b02901eb778369c5mr962723pfl.60.1613593467044; Wed, 17 Feb 2021 12:24:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 70/71] tests/tcg: Increase timeout for TCI Date: Wed, 17 Feb 2021 12:20:35 -0800 Message-Id: <20210217202036.1724901-71-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The longest test at the moment seems to be a (slower) aarch64 host, for which test-mmap takes 64 seconds. Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth --- configure | 3 +++ tests/tcg/Makefile.target | 6 ++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/configure b/configure index a79b3746d4..b8924276bc 100755 --- a/configure +++ b/configure @@ -5797,6 +5797,9 @@ fi if test "$optreset" =3D "yes" ; then echo "HAVE_OPTRESET=3Dy" >> $config_host_mak fi +if test "$tcg" =3D "enabled" -a "$tcg_interpreter" =3D "true" ; then + echo "CONFIG_TCG_INTERPRETER=3Dy" >> $config_host_mak +fi if test "$fdatasync" =3D "yes" ; then echo "CONFIG_FDATASYNC=3Dy" >> $config_host_mak fi diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target index 24d75a5801..fa5813192a 100644 --- a/tests/tcg/Makefile.target +++ b/tests/tcg/Makefile.target @@ -77,8 +77,10 @@ LDFLAGS=3D QEMU_OPTS=3D =20 =20 -# If TCG debugging is enabled things are a lot slower -ifeq ($(CONFIG_DEBUG_TCG),y) +# If TCG debugging, or TCI is enabled things are a lot slower +ifneq ($(CONFIG_TCG_INTERPRETER),) +TIMEOUT=3D90 +else ifneq ($(CONFIG_DEBUG_TCG),) TIMEOUT=3D60 else TIMEOUT=3D15 --=20 2.25.1 From nobody Thu May 16 07:12:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613597588; cv=none; d=zohomail.com; s=zohoarc; b=aNfB70LoMC8yKj3MJRHjXrk4jMh+s/bxL64b+Go5kVrnLEp+OOSsX+wZQMP8dO/sHUoBRpR2dWmeBTvBmulb+MhYCuLMhrBXMbyT1ct/+s+0aGP1wOYSxPk5kPwYglcJhjNzxo7Vdhdfj3gcnrn0S76Wl6Xl8oSQBnk99YECLq8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613597588; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sOfLAVkLgg63RmxbpsuuYlLjEnk78TrO9DvNZg7MM0M=; b=c4jp3WrK/miZBPGXXoYKM8ZVmlKK6nWcO+C+PT1oUJ+KhsUoT0T2L/xR0T/O/nmAIghSIPGNa0aHP+mwzPUAftkoAfDct/tqSyOxXr0sItLlQRjsI0/qbgLdJsCbVLPCM365nlLNeJ7fwk3Kvcr2M5v8RZx8BBPZH9MSo3+D6aA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613597588497687.8781367649964; Wed, 17 Feb 2021 13:33:08 -0800 (PST) Received: from localhost ([::1]:33590 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCURW-0001ca-Si for importer@patchew.org; Wed, 17 Feb 2021 16:33:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33896) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCTNB-0002FA-Dk for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:24:39 -0500 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:44880) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCTN8-0007qa-89 for qemu-devel@nongnu.org; Wed, 17 Feb 2021 15:24:33 -0500 Received: by mail-pf1-x430.google.com with SMTP id t29so9156473pfg.11 for ; Wed, 17 Feb 2021 12:24:29 -0800 (PST) Received: from localhost.localdomain (047-051-160-125.biz.spectrum.com. [47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sOfLAVkLgg63RmxbpsuuYlLjEnk78TrO9DvNZg7MM0M=; b=KpEDhHjJU1fEaPrRmgNhVvzuhtX94/lEiSJlVG3LnJCakS0Jm24kMlIgWWlROa9NoT eTAnhnJEi8QUAYTkDGsL1NI7z/fe5GCR5sh3K26qSUnXUbePGlotysGaNNvlZMzqdYyt zKA53XySDymb9+mcGeUib75l/KlH7a3OeAyMq2uANDviRCQOV17Ssu8IBvJo344MC3nR GRTvVS/hBC8W2x+ebQNmBMMajsiS/d1FAtQFkC37ENmaCJzzYF5+YL/6j8eXpPOTuTD6 fFODUx2p0bjiMMktV3gDLMSAkZiWcd4hLAm2fOFWEgiXuIV7t7F2umAICTwH3xQ5JYee umvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sOfLAVkLgg63RmxbpsuuYlLjEnk78TrO9DvNZg7MM0M=; b=Uo86jXponE4rZoynRUIXUPq10Vc48JEx0DqQl4WVieJ2CD1VP2hLwuZDGx7aNYTISn gyHH0sl/qZSUAYy0WibrV9rPsqSeoPiN9KWJAK5g9aD4viMMS8ykXrQJxCGlVOU2I11e c5rHon/x8KNVTC0tSKPYbxw3tsd8AvR/AshQAx0NcXHHgHmOHQvvgGdMwnLXHG0PpKmX lUt/+YxpR8LtXYjMSsKCMpMmkHqgeliGOKT2Rkie6FmwKimY/N++7VY04XXceJFnjb6m q0G///UI99tFAZK6+BB5chZ727kYFFVsdVuWSdbINvr2kXQNfyQz2NpKHQVs7zgStwQ4 RoPg== X-Gm-Message-State: AOAM533xajCXVr0cMQhpupWBxnyxb0P8IKtCVrOwW9609+BNTRGFd3aD meKJT8LxIxPOejxTYCCOC0FZTt6wHVL5Kg== X-Google-Smtp-Source: ABdhPJxsscCg3/VGNKmmXy7fGgpVJMNSORBIDUAU8/B9KrH2RXOFIsoZIGfTFJv+eposhwp4RoG5vg== X-Received: by 2002:a62:cf83:0:b029:1ec:df4e:d66a with SMTP id b125-20020a62cf830000b02901ecdf4ed66amr935172pfg.5.1613593468967; Wed, 17 Feb 2021 12:24:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 71/71] gitlab: Enable cross-i386 builds of TCI Date: Wed, 17 Feb 2021 12:20:36 -0800 Message-Id: <20210217202036.1724901-72-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) We're currently only testing TCI with a 64-bit host -- also test with a 32-bit host. Enable a selection of softmmu and user-only targets, 32-bit LE, 64-bit LE, 32-bit BE, as there are ifdefs for each. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Acked-by: Thomas Huth --- .gitlab-ci.d/crossbuilds.yml | 17 ++++++++++++++--- .../docker/dockerfiles/fedora-i386-cross.docker | 1 + 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index 66547b6683..99300f786b 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -6,7 +6,8 @@ - mkdir build - cd build - PKG_CONFIG_PATH=3D$PKG_CONFIG_PATH - ../configure --enable-werror $QEMU_CONFIGURE_OPTS --disable-user + ../configure --enable-werror $QEMU_CONFIGURE_OPTS $ACCEL_CONFIGURE_O= PTS + --disable-user --target-list-exclude=3D"arm-softmmu cris-softmmu i386-softmmu microblaze-softmmu mips-softmmu mipsel-softmmu mips64-softmmu ppc-softmmu sh4-softmmu xtensa-softmmu" @@ -27,7 +28,7 @@ - PKG_CONFIG_PATH=3D$PKG_CONFIG_PATH ../configure --enable-werror $QEMU_CONFIGURE_OPTS --disable-tools --enable-${ACCEL:-kvm} $ACCEL_CONFIGURE_OPTS - - make -j$(expr $(nproc) + 1) all check-build + - make -j$(expr $(nproc) + 1) all check-build $MAKE_CHECK_ARGS =20 .cross_user_build_job: stage: build @@ -36,7 +37,8 @@ - mkdir build - cd build - PKG_CONFIG_PATH=3D$PKG_CONFIG_PATH - ../configure --enable-werror $QEMU_CONFIGURE_OPTS --disable-system + ../configure --enable-werror $QEMU_CONFIGURE_OPTS $ACCEL_CONFIGURE_O= PTS + --disable-system - make -j$(expr $(nproc) + 1) all check-build $MAKE_CHECK_ARGS =20 cross-armel-system: @@ -81,6 +83,15 @@ cross-i386-user: IMAGE: fedora-i386-cross MAKE_CHECK_ARGS: check =20 +cross-i386-tci: + extends: .cross_accel_build_job + timeout: 60m + variables: + IMAGE: fedora-i386-cross + ACCEL: tcg-interpreter + ACCEL_CONFIGURE_OPTS: --target-list=3Di386-softmmu,i386-linux-user,aar= ch64-softmmu,aarch64-linux-user,ppc-softmmu,ppc-linux-user + MAKE_CHECK_ARGS: check + cross-mips-system: extends: .cross_system_build_job variables: diff --git a/tests/docker/dockerfiles/fedora-i386-cross.docker b/tests/dock= er/dockerfiles/fedora-i386-cross.docker index a6e411291b..aa66314c65 100644 --- a/tests/docker/dockerfiles/fedora-i386-cross.docker +++ b/tests/docker/dockerfiles/fedora-i386-cross.docker @@ -5,6 +5,7 @@ ENV PACKAGES \ findutils \ gcc \ git \ + libffi-devel.i686 \ libtasn1-devel.i686 \ libzstd-devel.i686 \ make \ --=20 2.25.1