From nobody Tue Nov 18 22:50:45 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1613515842; cv=none; d=zohomail.com; s=zohoarc; b=kl9Xkaf8lihBxZaujt4hrUlW/nOjXGqTKh71p3luPjjm8wJO/OjtG5Qz2E9p8FdIuWus+yUMzReaB1VyZ9UgUqe5SqlmQGwIYYWFcidUrtftmWUywCrwOZ/R3Hw/ckg1d6a2fa3NQJvm+0G/DirPrnPMiRXkmQ43QTeWQw0krVg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613515842; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5P6YxnXQSfQV1rvzo56pSgpKXJwdD6Qy9MoHnPSuEQ4=; b=jB46CI3SrftXXWozfcEr0YyfEXFE9FQ4wrOlJcnGvIL5ToHwKuHF5svjLqIgNhxRFbbCMGT5OBDduWXoAo1qIZ974wwPgtsIKOJoYE9LA/8zsb/CRhwZBZyHHtn4676A00GZleniUKXdtdBGe7pQnCAfxdPhsmvZgR/IJEWPVic= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613515841625244.25708498094048; Tue, 16 Feb 2021 14:50:41 -0800 (PST) Received: from localhost ([::1]:36474 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC9B2-00067T-KW for importer@patchew.org; Tue, 16 Feb 2021 17:50:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39954) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC96Y-0000vB-Jo for qemu-devel@nongnu.org; Tue, 16 Feb 2021 17:46:02 -0500 Received: from mail-ot1-x335.google.com ([2607:f8b0:4864:20::335]:34064) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC96O-0004sJ-Mu for qemu-devel@nongnu.org; Tue, 16 Feb 2021 17:46:02 -0500 Received: by mail-ot1-x335.google.com with SMTP id b16so8021262otq.1 for ; Tue, 16 Feb 2021 14:45:52 -0800 (PST) Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id b12sm32909oti.65.2021.02.16.14.45.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 14:45:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5P6YxnXQSfQV1rvzo56pSgpKXJwdD6Qy9MoHnPSuEQ4=; b=fuYoTdPF3TyE/eHtguZ4/wZ8HA1C4DYn/7l5mfB7Tb6WgT64cjPqlEcYHDZ5qFvdc4 9cRxkTboqcHV08N7fg5rpJd/wmsPP3FYxomtaxub/INKLssa73i4Q0WeyLoLWJ+Iy0ft IgPJAS/ps6fmfd23/KIIoqJRdDdo7FRoa2LR+5RMSLVj9DQImUmOK+ivk5xvey9OKHE8 AHWNr1ktsvQrpOHeWAaf5CGMULtWCNTpxpTMxjAgy2fZoYufTiHR549a7NZKRWe9Xkf4 9r4NkjgFbev/TNs/njF5faBmUY3yMDFX+SngGElQzXXKVBmljegK/jj2+XqUBWFr3eAO Sjnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5P6YxnXQSfQV1rvzo56pSgpKXJwdD6Qy9MoHnPSuEQ4=; b=PHTLmzznRwaostpbdwW13oYoVxI9rBfh8VIZj1KNsyFoQ93BCNYXijpMiTrw+3yl4d ImR4n+MWyWUXAea6OewPICNt+M7DzHi+qFBafaBa66OqZZLJ5auc226vVEDT2xxFKS5P rG928LvLixwm14Q/y35N5ln72YFiQiuc+eASik0GpoS1G5at2w3LdqR97MFf8c9OU2En cIt197wCswPRfJPFZ/geFdLpjwg8wI2fJX1ojA1B7qxlWXLYm7vCMvAETeMULjthS3z4 ySeNhTX/wOxKjsPag0nCgJGOIumnMvyi9AqF8ZrI6l7kqCOfMs8L5JaT3q4EBY8ar2UJ 2GvA== X-Gm-Message-State: AOAM533ctzTm63ofqBUl+SYjLmHQw3jE1RfPwFAAybJmK3iza5UiO8OL w5s6oGC+58lTrIt+eMvZ9oKQlw== X-Google-Smtp-Source: ABdhPJyheHAGsdO+Sj5/m5Vfn9Ni4waLeOMqRk7rCGHCCSJI4MAuG+mi4BzOOPhCIwiNGurP4Bc7UA== X-Received: by 2002:a05:6830:903:: with SMTP id v3mr15796778ott.46.1613515551561; Tue, 16 Feb 2021 14:45:51 -0800 (PST) From: Rebecca Cran To: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 1/3] target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe Date: Tue, 16 Feb 2021 15:45:41 -0700 Message-Id: <20210216224543.16142-2-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210216224543.16142-1-rebecca@nuviainc.com> References: <20210216224543.16142-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=rebecca@nuviainc.com; helo=mail-ot1-x335.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @nuviainc-com.20150623.gappssmtp.com) Content-Type: text/plain; charset="utf-8" Add support for FEAT_SSBS. SSBS (Speculative Store Bypass Safe) is an optional feature in ARMv8.0, and mandatory in ARMv8.5. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu.h | 15 +++++++- target/arm/helper.c | 37 ++++++++++++++++++++ target/arm/internals.h | 6 ++++ target/arm/translate-a64.c | 12 +++++++ 4 files changed, 69 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f240275407bc..a0a3ee7bcde9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1201,6 +1201,7 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_TE (1U << 30) /* AArch32 only */ #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ +#define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ @@ -1208,7 +1209,7 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ -#define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ +#define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ =20 #define CPTR_TCPAC (1U << 31) #define CPTR_TTA (1U << 20) @@ -1245,6 +1246,7 @@ void pmu_init(ARMCPU *cpu); #define CPSR_IL (1U << 20) #define CPSR_DIT (1U << 21) #define CPSR_PAN (1U << 22) +#define CPSR_SSBS (1U << 23) #define CPSR_J (1U << 24) #define CPSR_IT_0_1 (3U << 25) #define CPSR_Q (1U << 27) @@ -1307,6 +1309,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_A (1U << 8) #define PSTATE_D (1U << 9) #define PSTATE_BTYPE (3U << 10) +#define PSTATE_SSBS (1U << 12) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) #define PSTATE_PAN (1U << 22) @@ -3883,6 +3886,11 @@ static inline bool isar_feature_aa32_dit(const ARMIS= ARegisters *id) return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) !=3D 0; } =20 +static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) !=3D 0; +} + /* * 64-bit feature tests via id registers. */ @@ -4137,6 +4145,11 @@ static inline bool isar_feature_aa64_dit(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) !=3D 0; } =20 +static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) !=3D 0; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 0e1a3b94211c..fedcf2e739e2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4450,6 +4450,24 @@ static const ARMCPRegInfo dit_reginfo =3D { .readfn =3D aa64_dit_read, .writefn =3D aa64_dit_write }; =20 +static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_SSBS; +} + +static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate =3D (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS); +} + +static const ARMCPRegInfo ssbs_reginfo =3D { + .name =3D "SSBS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 6, + .type =3D ARM_CP_NO_RAW, .access =3D PL0_RW, + .readfn =3D aa64_ssbs_read, .writefn =3D aa64_ssbs_write +}; + static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -8244,6 +8262,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_dit, cpu)) { define_one_arm_cp_reg(cpu, &dit_reginfo); } + if (cpu_isar_feature(aa64_ssbs, cpu)) { + define_one_arm_cp_reg(cpu, &ssbs_reginfo); + } =20 if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { define_arm_cp_regs(cpu, vhe_reginfo); @@ -9463,6 +9484,14 @@ static void take_aarch32_exception(CPUARMState *env,= int new_mode, env->uncached_cpsr &=3D ~(CPSR_IL | CPSR_J); env->daif |=3D mask; =20 + if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) { + if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) { + env->uncached_cpsr |=3D CPSR_SSBS; + } else { + env->uncached_cpsr &=3D ~CPSR_SSBS; + } + } + if (new_mode =3D=3D ARM_CPU_MODE_HYP) { env->thumb =3D (env->cp15.sctlr_el[2] & SCTLR_TE) !=3D 0; env->elr_el[2] =3D env->regs[15]; @@ -9973,6 +10002,14 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *= cs) new_mode |=3D PSTATE_TCO; } =20 + if (cpu_isar_feature(aa64_ssbs, cpu)) { + if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) { + new_mode |=3D PSTATE_SSBS; + } else { + new_mode &=3D ~PSTATE_SSBS; + } + } + pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 =3D 1; aarch64_restore_sp(env, new_el); diff --git a/target/arm/internals.h b/target/arm/internals.h index b251fe44506b..d92aeb57d782 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1231,6 +1231,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64= _t features, if (isar_feature_aa32_dit(id)) { valid |=3D CPSR_DIT; } + if (isar_feature_aa32_ssbs(id)) { + valid |=3D CPSR_SSBS; + } =20 return valid; } @@ -1252,6 +1255,9 @@ static inline uint32_t aarch64_pstate_valid_mask(cons= t ARMISARegisters *id) if (isar_feature_aa64_dit(id)) { valid |=3D PSTATE_DIT; } + if (isar_feature_aa64_ssbs(id)) { + valid |=3D PSTATE_SSBS; + } if (isar_feature_aa64_mte(id)) { valid |=3D PSTATE_TCO; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1c4b8d02f3b8..4dc72736d649 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1700,6 +1700,18 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, tcg_temp_free_i32(t1); break; =20 + case 0x19: /* SSBS */ + if (!dc_isar_feature(aa64_ssbs, s)) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_SSBS); + } else { + clear_pstate_bits(PSTATE_SSBS); + } + /* Don't need to rebuild hflags since SSBS is a nop */ + break; + case 0x1a: /* DIT */ if (!dc_isar_feature(aa64_dit, s)) { goto do_unallocated; --=20 2.26.2 From nobody Tue Nov 18 22:50:45 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613515724935223.971984073425; Tue, 16 Feb 2021 14:48:44 -0800 (PST) Received: from localhost ([::1]:58840 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC999-0003h1-P7 for importer@patchew.org; Tue, 16 Feb 2021 17:48:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39922) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC96U-0000sE-Ub for qemu-devel@nongnu.org; Tue, 16 Feb 2021 17:46:00 -0500 Received: from mail-ot1-x32f.google.com ([2607:f8b0:4864:20::32f]:40301) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC96Q-0004se-9S for qemu-devel@nongnu.org; Tue, 16 Feb 2021 17:45:58 -0500 Received: by mail-ot1-x32f.google.com with SMTP id b8so5805904oti.7 for ; Tue, 16 Feb 2021 14:45:53 -0800 (PST) Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id b12sm32909oti.65.2021.02.16.14.45.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 14:45:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=97kB+nyl96mKMiXXe0WJ0gyYIf0q0XHV2YeMSKLBYDo=; b=tgSyp9fQIY/GiS8e29th3+Jda8Xjm87jKfEOil0hS70pgrRgDv/iIltSQslk76J2FS ukfy40+KPlbDMz+Nov2EYkNA9JGo7yHm1/vUjoC6IZhJhVVDr4C+zeEzPfzsBH9Oi1hc WUSrpYNRKN5jpBtlGoLH+IVo9UpbKtsF0HwNPXmmCXxh+etAj+UZxtfzgCTlibbv6epL et1o4GS7w4HxkOYacbNu0s1TKebsyq21uwky3ERISJplWxpPIMlCR+hTRXNR6G+Mvcmz PFqdF97kCEs2E/wVggknFX5Taz9Lev9Laf6x72cE7BN3k0ZgKvKEK1KYz51VJLeB+lw8 fD7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=97kB+nyl96mKMiXXe0WJ0gyYIf0q0XHV2YeMSKLBYDo=; b=HS27Rf1OxPopyN1FzGTbBJXOWg2jk2OUwRsaSNWQCpsGF9JTQ7dj5kGDoEStapWKBk Yp5/VoKBK832cYl0U+q+4isgmz1iQ9ve4uT0KMTZWN52/EGfDt+Aq6OIpLA1jKVbMze+ jR7aLGD9fmCqH4bfeJ9kR/a6OccStW1Iknmeb48zBUDFtcSA02wx9ZG/ciWV9IStB2ym 4dmwIcBS4y5qZJjg8oqpK6I1ZPKraMaXG8JLOdLc47zbvQqwPxoToUX+pu1zK72KPkpo YVEfzsQAIJGuHSEGhOcc7V0gGuY8+0roBxahGUSuqH14lWCQuMnys+bwWqGC9osDz44L lNAw== X-Gm-Message-State: AOAM5316PwToY7Xo9ccb70TIvBStirdpUEUp1T9fk4U52vFCRE4yKL9R jdpWTx9iJ6Zbfc7GsRK5NO1mrQ== X-Google-Smtp-Source: ABdhPJwkdyfi3Y5YB45ww5bqfCZVrt6qhMG5NxVlXMbYJmlQldDDz2hIZ2SIdRnubKiKQEh6kBOS5Q== X-Received: by 2002:a9d:6d85:: with SMTP id x5mr4634595otp.338.1613515553326; Tue, 16 Feb 2021 14:45:53 -0800 (PST) From: Rebecca Cran To: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 2/3] target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU Date: Tue, 16 Feb 2021 15:45:42 -0700 Message-Id: <20210216224543.16142-3-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210216224543.16142-1-rebecca@nuviainc.com> References: <20210216224543.16142-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=rebecca@nuviainc.com; helo=mail-ot1-x32f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , Richard Henderson , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c255f1bcc393..f0a9e968c9c1 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -674,6 +674,7 @@ static void aarch64_max_initfn(Object *obj) =20 t =3D cpu->isar.id_aa64pfr1; t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); + t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* * Begin with full support for MTE. This will be downgraded to MTE= =3D0 * during realize if the board provides no tag memory, much like @@ -723,6 +724,10 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_PFR0, DIT, 1); cpu->isar.id_pfr0 =3D u; =20 + u =3D cpu->isar.id_pfr2; + u =3D FIELD_DP32(u, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 =3D u; + u =3D cpu->isar.id_mmfr3; u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ cpu->isar.id_mmfr3 =3D u; --=20 2.26.2 From nobody Tue Nov 18 22:50:45 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613515691666300.26839727598417; Tue, 16 Feb 2021 14:48:11 -0800 (PST) Received: from localhost ([::1]:57072 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC98c-0002x4-Lu for importer@patchew.org; Tue, 16 Feb 2021 17:48:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39942) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC96W-0000sf-Ff for qemu-devel@nongnu.org; Tue, 16 Feb 2021 17:46:01 -0500 Received: from mail-ot1-x32e.google.com ([2607:f8b0:4864:20::32e]:42780) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC96T-0004sq-3T for qemu-devel@nongnu.org; Tue, 16 Feb 2021 17:46:00 -0500 Received: by mail-ot1-x32e.google.com with SMTP id q4so10419499otm.9 for ; Tue, 16 Feb 2021 14:45:56 -0800 (PST) Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id b12sm32909oti.65.2021.02.16.14.45.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 14:45:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4ZPSLm3yrNAClwWOzT7/VZpNZh4ixX7KNguZeQ0+66w=; b=nfOSWq5Xkj4tBIKxivwikGdBpW5vU8aqHCg1EloTco9y5Iw2XrGVoY/s6cOJa7aklH unLIHOWXiaLXqBJUZ4mb4etI2UJ7Hw0sNqEFRY2rvzYBQAHl57gFE/hioWbEulO6XtnU yxebmgW26qOfmzJSMvJXmSj/xllQUasi8rKRqQfo82OrKtz9i7KLnun2neR5OOkHEieE YhBNVostm/nGYhlRf1ron/mqH7Vw3GI2DwRHDtILVLUTVfDG0Fr3azpAtkdmrISh/Ltv AYgsZhtGmAcxVUcqA3T44RoSIYKkOW0tig2o5WJyNzEPzTfcWims37s1ERLUW9BbAdQs TRJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4ZPSLm3yrNAClwWOzT7/VZpNZh4ixX7KNguZeQ0+66w=; b=gBk8PM3KDUS8tShVJdTLv0m9/s7Z2xMcr16+bl/rA3QNrLMGY6FlBjPuY0xfkVbd76 mUNK6Jd+o1OYJrEFuE3dtUEUbbP+Ps4eiZ9i2IGGPcrz9s9w9e+sPGCmXVo/4xhsVSj9 XMCtz4W/l2LnNfhWTi7QaXXDyCtGyTb4IHT/tb/22vhg2JlTSJYZ70G6MyRD6rGKuI3e +EXKU60sa0Wr1JJmdx4XOlmNnGXvHUNP+9I/SoXfBBU6NPQMIoqddGdR5f5JEMuh3ol2 O9v/PKgj8ZuZdSqJUCnLz4H8yRwboowNV4ukh4/Lh/NNCSH2/8dDb56Z8qzRZ/IXeah9 x/lQ== X-Gm-Message-State: AOAM531VvbADP1ZXwG/b3GnixQ6kUOYRoCI8ixYs6XnVIwZbF+ixzSbG qHs5dKp4quxBZbmYdkKXUSmnPQ== X-Google-Smtp-Source: ABdhPJzDnOa4SmqKpP51gazeuFV2oxjUOkrqeL9zSMd3edw0hTGvBIS3DvVPEFDTrH9Zz3C8GRCW4g== X-Received: by 2002:a9d:861:: with SMTP id 88mr16612524oty.27.1613515556196; Tue, 16 Feb 2021 14:45:56 -0800 (PST) From: Rebecca Cran To: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 3/3] target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU Date: Tue, 16 Feb 2021 15:45:43 -0700 Message-Id: <20210216224543.16142-4-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210216224543.16142-1-rebecca@nuviainc.com> References: <20210216224543.16142-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=rebecca@nuviainc.com; helo=mail-ot1-x32e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , Richard Henderson , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Enable FEAT_SSBS for the "max" 32-bit CPU. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5cf6c056c50f..88a6b183d325 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2206,6 +2206,10 @@ static void arm_max_initfn(Object *obj) t =3D cpu->isar.id_pfr0; t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); cpu->isar.id_pfr0 =3D t; + + t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + cpu->isar.id_mfr2 =3D t; } #endif } --=20 2.26.2