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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OUdGnepARkSKCi0JQLawkwQhjAV1702z7wSnXOJ7NXU=; b=PSO8XemDHg2A79NDIPI/UM0Uy9JlBQeDo03pZJp8moPwQgSOrJj980r6YbRhyp7RLS sTcDJsUxcHZvWuROBPliTfqmJ3wywANPk0fCCh/u5g65SBqAD+QqqrQDj5/5ESRUbOxR 46hLRV5aipeVzRTceU8Cp12u2xsjcAGxKbtV5Ig2Edv1y2EfzJiuqVhlZBsqVGhBejIs N/vYaJlivGYpREHVbn/C7x7CFALDwiZWm0VaeqjL7KFGOCNif3PWb/bL0n8DVswYMToD zFiiarvav9GXWVldtSHSglyMi24TwoZPG+1/cp3P/Z1QPeRbJqzXnmsF7v5utZey34YI l36g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OUdGnepARkSKCi0JQLawkwQhjAV1702z7wSnXOJ7NXU=; b=iaXoB+lPzLqoBYsuxmo7dzHeOWsemE2Jqwy/zUc2+NItbwF9P8MuelQHQ2Z+OEhyuW +mFOcnRL89N2VDTQXmH8uDoTdbbqPMd9qhtXKyVfSRfuBSUcUzHTn7z9ti98PNiWJ9Mi JE3JFPXUaaA2xPpZfwSFr4fiuXEvaMlRiVfrHOid0RBO9s2p45m2qa9IedgJ/HXYeEke crj31bKieD/YhX1FkjsF/IOMJ2QXXAGZXMRT6htZvebJvicjccY6axrLCUrPr7VvxmQz GVmv/rxzQ4cJNb4BLdlB6KQCux5uwiCH51/JdtpMQsBfiKuBNdTrbu/djGEKXSh3gxFx 4Yww== X-Gm-Message-State: AOAM53229lTlv0xQwadI61huZYt6BUF6Z/ld+crscDuZsEai/46BXf91 4pUN3TsuB8pFkWOfjcu41oCLZcrnWhbMzA== X-Google-Smtp-Source: ABdhPJwVXFxLe67Q4U9AH4nDEqM89clycD1OW7VewC/uvaH1yeJdWYjyGB3tVLMPuGP0gOvpcsl3ng== X-Received: by 2002:a05:600c:203:: with SMTP id 3mr3092577wmi.187.1613492239037; Tue, 16 Feb 2021 08:17:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/40] linux-user/aarch64: Pass syndrome to EXC_*_ABORT Date: Tue, 16 Feb 2021 16:16:44 +0000 Message-Id: <20210216161658.29881-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson A proper syndrome is required to fill in the proper si_code. Use page_get_flags to determine permission vs translation for user-only. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-27-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/aarch64/cpu_loop.c | 24 +++++++++++++++++++++--- target/arm/tlb_helper.c | 15 +++++++++------ 2 files changed, 30 insertions(+), 9 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 42b9c15f536..4e43906e66a 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -23,6 +23,7 @@ #include "cpu_loop-common.h" #include "qemu/guest-random.h" #include "hw/semihosting/common-semi.h" +#include "target/arm/syndrome.h" =20 #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r =3D get_user_u32((x), (gaddr)); \ @@ -76,7 +77,7 @@ void cpu_loop(CPUARMState *env) { CPUState *cs =3D env_cpu(env); - int trapnr; + int trapnr, ec, fsc; abi_long ret; target_siginfo_t info; =20 @@ -117,9 +118,26 @@ void cpu_loop(CPUARMState *env) case EXCP_DATA_ABORT: info.si_signo =3D TARGET_SIGSEGV; info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; info._sifields._sigfault._addr =3D env->exception.vaddress; + + /* We should only arrive here with EC in {DATAABORT, INSNABORT= }. */ + ec =3D syn_get_ec(env->exception.syndrome); + assert(ec =3D=3D EC_DATAABORT || ec =3D=3D EC_INSNABORT); + + /* Both EC have the same format for FSC, or close enough. */ + fsc =3D extract32(env->exception.syndrome, 0, 6); + switch (fsc) { + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + info.si_code =3D TARGET_SEGV_MAPERR; + break; + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + info.si_code =3D TARGET_SEGV_ACCERR; + break; + default: + g_assert_not_reached(); + } + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_DEBUG: diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index df85079d9f0..9609333cbdf 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -154,21 +154,24 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr) { ARMCPU *cpu =3D ARM_CPU(cs); + ARMMMUFaultInfo fi =3D {}; =20 #ifdef CONFIG_USER_ONLY - cpu->env.exception.vaddress =3D address; - if (access_type =3D=3D MMU_INST_FETCH) { - cs->exception_index =3D EXCP_PREFETCH_ABORT; + int flags =3D page_get_flags(useronly_clean_ptr(address)); + if (flags & PAGE_VALID) { + fi.type =3D ARMFault_Permission; } else { - cs->exception_index =3D EXCP_DATA_ABORT; + fi.type =3D ARMFault_Translation; } - cpu_loop_exit_restore(cs, retaddr); + + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); #else hwaddr phys_addr; target_ulong page_size; int prot, ret; MemTxAttrs attrs =3D {}; - ARMMMUFaultInfo fi =3D {}; ARMCacheAttrs cacheattrs =3D {}; =20 /* --=20 2.20.1