From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613492428; cv=none; d=zohomail.com; s=zohoarc; b=eHvJZr7Gr4xJ5MApNCUrFmPFA2AuBZV255IQSuO/UiOL+xYXOaBhwiQ01Z//ub7uTnOLMGPrJpAOL+Y7iUuRR3ryTb849kXTXmEpAGCQiM10eQT0ZaLYipP8yipywU71UvC6UvrGUJFOc6jhOMIdxlxVa7OvGsZ2JjUir0alKHY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613492428; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CtmmfXvax6/vFQdcYPhQ9hSJnYjUDnJEzMjqiouGk60=; b=U9v8Th5VvyHNGepBUT3uiS0LaSCAyxswUUOzHJRcL/52c2+CvQ34+/pt9FA1hNJOIGk44BqIrv4JlhGmQC5OAij4NIuagtCmWvjkIGGXLV+46v8Vyw1CxsAgImn+PkTozDhO+qUyUARlC6N5QgY+7gqiszV0/Pms/8ByulwDwyo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613492428040734.831610887448; Tue, 16 Feb 2021 08:20:28 -0800 (PST) Received: from localhost ([::1]:34912 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC35N-000217-UX for importer@patchew.org; Tue, 16 Feb 2021 11:20:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39740) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32E-0006vY-Jf for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:10 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:41473) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC328-0002Ly-Bd for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:10 -0500 Received: by mail-wr1-x42b.google.com with SMTP id n6so13759300wrv.8 for ; Tue, 16 Feb 2021 08:17:03 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CtmmfXvax6/vFQdcYPhQ9hSJnYjUDnJEzMjqiouGk60=; b=qi+f+Zi/J9EDmxCmzdfmsKWOawjXpqWyHtGIG2mcMT33mvbXzS6gKoNHEIbM4mj60d +k6tBSZoBifhGa2hXYzyFEelT6zCd9+IkRqrTElCb6por1NSfBevPZEQBFye92LjYNyX 1qFH5sSh/vMPL9sXpK/c7uzhbBeLgJZ5/zj+97g17K44UN8HyydO8QcS0gKMfh28Wpcp i6UOr8218rsH+HgoIk6+7cfRDZv1dYa1Ibr8rFpjhHbcHOJJgWQD1aPqo8fx72loFS2c V8fNPB1cTlOix9NWSeiosf1gEi8EWCc9/BWgo/AoD+kXe21GHziexEr6ZNZmDxRc5SVR B5DA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CtmmfXvax6/vFQdcYPhQ9hSJnYjUDnJEzMjqiouGk60=; b=YD9+JPHqMEN9oSxDwUjY4KRTADFdaRHm2pk844eglj83Axw1ykADJ+3qjNiih/+znB Q+q/L+7+589Uo6YbqBrAp1TSd12TRaQY3Kn3gU3adBDVeYazY8HVvyFwBdlnx56UPD44 IBc/74YNef6sWYPRIoFf/gR99goepYZz4qrr2xY2oWbrJjXF1TUhp/gvdvbxQPRBDIE5 IBEIS+AfsLnFzPmQJHTECqoFFIyhR22JxNB+S68VHTGH78fWGmfOKvmRyUE67jyE92NP lfQ580gv25W6wDx8yoXtLvXx6TuBri/Aq1G4TT5vc4PkqQNyzYG3GwOSxhhuYCOF4Doa QGBA== X-Gm-Message-State: AOAM533ckzZxe58SpsDY/rPlDzbrmxTGjWwCRwwYkb4EIOeVoyMBbMyi tsFH+wxdov4d/1X+40pzrIYxz11H+n9Pjw== X-Google-Smtp-Source: ABdhPJx0QECcccaPdxSkfi1kSVuYjUML6ieb+ylrlhf+CtfDh9Ikdbk/FFVJdo5p2L2FsurNXqbUVQ== X-Received: by 2002:adf:fc4c:: with SMTP id e12mr25463122wrs.106.1613492221472; Tue, 16 Feb 2021 08:17:01 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/40] tcg: Introduce target-specific page data for user-only Date: Tue, 16 Feb 2021 16:16:19 +0000 Message-Id: <20210216161658.29881-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This data can be allocated by page_alloc_target_data() and released by page_set_flags(start, end, prot | PAGE_RESET). This data will be used to hold tag memory for AArch64 MTE. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu-all.h | 42 +++++++++++++++++++++++++++++++++------ accel/tcg/translate-all.c | 28 ++++++++++++++++++++++++++ linux-user/mmap.c | 4 +++- linux-user/syscall.c | 4 ++-- 4 files changed, 69 insertions(+), 9 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index babf0a8959f..6421892830c 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -256,15 +256,21 @@ extern intptr_t qemu_host_page_mask; #define PAGE_EXEC 0x0004 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) #define PAGE_VALID 0x0008 -/* original state of the write flag (used when tracking self-modifying - code */ +/* + * Original state of the write flag (used when tracking self-modifying cod= e) + */ #define PAGE_WRITE_ORG 0x0010 -/* Invalidate the TLB entry immediately, helpful for s390x - * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs= () */ -#define PAGE_WRITE_INV 0x0040 +/* + * Invalidate the TLB entry immediately, helpful for s390x + * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs= () + */ +#define PAGE_WRITE_INV 0x0020 +/* For use with page_set_flags: page is being replaced; target_data cleare= d. */ +#define PAGE_RESET 0x0040 + #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ -#define PAGE_RESERVED 0x0020 +#define PAGE_RESERVED 0x0100 #endif /* Target-specific bits that will be used via page_get_flags(). */ #define PAGE_TARGET_1 0x0080 @@ -279,6 +285,30 @@ int walk_memory_regions(void *, walk_memory_regions_fn= ); int page_get_flags(target_ulong address); void page_set_flags(target_ulong start, target_ulong end, int flags); int page_check_range(target_ulong start, target_ulong len, int flags); + +/** + * page_alloc_target_data(address, size) + * @address: guest virtual address + * @size: size of data to allocate + * + * Allocate @size bytes of out-of-band data to associate with the + * guest page at @address. If the page is not mapped, NULL will + * be returned. If there is existing data associated with @address, + * no new memory will be allocated. + * + * The memory will be freed when the guest page is deallocated, + * e.g. with the munmap system call. + */ +void *page_alloc_target_data(target_ulong address, size_t size); + +/** + * page_get_target_data(address) + * @address: guest virtual address + * + * Return any out-of-bound memory assocated with the guest page + * at @address, as per page_alloc_target_data. + */ +void *page_get_target_data(target_ulong address); #endif =20 CPUArchState *cpu_copy(CPUArchState *env); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 81d4c83f225..bba9c8e0b3e 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -114,6 +114,7 @@ typedef struct PageDesc { unsigned int code_write_count; #else unsigned long flags; + void *target_data; #endif #ifndef CONFIG_USER_ONLY QemuSpin lock; @@ -2740,6 +2741,7 @@ int page_get_flags(target_ulong address) void page_set_flags(target_ulong start, target_ulong end, int flags) { target_ulong addr, len; + bool reset_target_data; =20 /* This function should never be called with addresses outside the guest address space. If this assert fires, it probably indicates @@ -2754,6 +2756,8 @@ void page_set_flags(target_ulong start, target_ulong = end, int flags) if (flags & PAGE_WRITE) { flags |=3D PAGE_WRITE_ORG; } + reset_target_data =3D !(flags & PAGE_VALID) || (flags & PAGE_RESET); + flags &=3D ~PAGE_RESET; =20 for (addr =3D start, len =3D end - start; len !=3D 0; @@ -2767,10 +2771,34 @@ void page_set_flags(target_ulong start, target_ulon= g end, int flags) p->first_tb) { tb_invalidate_phys_page(addr, 0); } + if (reset_target_data && p->target_data) { + g_free(p->target_data); + p->target_data =3D NULL; + } p->flags =3D flags; } } =20 +void *page_get_target_data(target_ulong address) +{ + PageDesc *p =3D page_find(address >> TARGET_PAGE_BITS); + return p ? p->target_data : NULL; +} + +void *page_alloc_target_data(target_ulong address, size_t size) +{ + PageDesc *p =3D page_find(address >> TARGET_PAGE_BITS); + void *ret =3D NULL; + + if (p->flags & PAGE_VALID) { + ret =3D p->target_data; + if (!ret) { + p->target_data =3D ret =3D g_malloc0(size); + } + } + return ret; +} + int page_check_range(target_ulong start, target_ulong len, int flags) { PageDesc *p; diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 1c9faef4769..ac0624f31ac 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -599,6 +599,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, in= t target_prot, } } the_end1: + page_flags |=3D PAGE_RESET; page_set_flags(start, start + len, page_flags); the_end: trace_target_mmap_complete(start); @@ -794,7 +795,8 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong ol= d_size, new_addr =3D h2g(host_addr); prot =3D page_get_flags(old_addr); page_set_flags(old_addr, old_addr + old_size, 0); - page_set_flags(new_addr, new_addr + new_size, prot | PAGE_VALID); + page_set_flags(new_addr, new_addr + new_size, + prot | PAGE_VALID | PAGE_RESET); } tb_invalidate_phys_range(new_addr, new_addr + new_size); mmap_unlock(); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 36b09010552..0c2d660bc42 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -4643,8 +4643,8 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_en= v, raddr=3Dh2g((unsigned long)host_raddr); =20 page_set_flags(raddr, raddr + shm_info.shm_segsz, - PAGE_VALID | PAGE_READ | - ((shmflg & SHM_RDONLY)? 0 : PAGE_WRITE)); + PAGE_VALID | PAGE_RESET | PAGE_READ | + (shmflg & SHM_RDONLY ? 0 : PAGE_WRITE)); =20 for (i =3D 0; i < N_SHM_REGIONS; i++) { if (!shm_regions[i].in_use) { --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613492537; cv=none; d=zohomail.com; s=zohoarc; b=CJ8GYZvsltdf3F06sD8jR5wC7hWXAQHviRqeHLhrVZR5NJrXVyLKMjHCroaYMu5OU+9IK3atdWa1g3FHSAZeinuOCzxtT/VqF700CxPvSFYLFz9dxGwEFyfLJY8cCy37xR0htgiRUCSc4D9Pq/UhjUYT+NBdoO4gCRag9fsztBY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613492537; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tBK1n8R/KslhmMsEEVJsYPxuw4cYZfG8sn9avPhfmns=; b=OvCOZe1SOWiOM9UeReq6ET6JHFiJOPSaOBGxmCRig6O+R9+sISgJ4VXe4Hx9FQEZijSjDIoR9qg+MRvnL9+gexxOaP1llmODTa0zkO9sZAIXr6XaUj839t4KjYZBZSj7D/2NU3vOzJdlcHRk6lKTToTg4s6MQaxw+aqnibUicb4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613492536829598.8740015664118; Tue, 16 Feb 2021 08:22:16 -0800 (PST) Received: from localhost ([::1]:40118 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC378-0004n0-PS for importer@patchew.org; Tue, 16 Feb 2021 11:22:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39858) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32G-00070M-SO for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:12 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:54557) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC328-0002M3-11 for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:12 -0500 Received: by mail-wm1-x330.google.com with SMTP id w4so9549885wmi.4 for ; Tue, 16 Feb 2021 08:17:03 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=tBK1n8R/KslhmMsEEVJsYPxuw4cYZfG8sn9avPhfmns=; b=s6E0owQtttnWplm49oB+sVQUyVvAEVkOVTNAnASyQNQU/5C0d+LZ/TvCkVkw41LcFs QmbSp3lewXB+3wAHzSPkE0lQZOKgykLS6wYj23qCZl8oj3x3wq5O2zei3yISNL6XztlX ZW3DPCqirEnKaOkaxazg/3cPZpAlr8vXdHlLUC4DFiMDe0bLtGUjjT7g5I6FaSdDnMbI fxbbZeuCtlUmH47//dbAIhTBVIKhKXy/WSlnTRc3gDMErk/WWKNfTj6Olkf4kKEekiOE i8pQEeRb6eh4ptJ9s3S8UNL4UPWES5yuejXGRs4Ty5Vv0G5Wx1YRT4ByheXPD+QgUcMx PU/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tBK1n8R/KslhmMsEEVJsYPxuw4cYZfG8sn9avPhfmns=; b=CusbIslnII2KCz9so3h8ZffQIQj84Qj5vj0G5/Xf/30iC/1BBjfxghUZO+VZTOH5m+ iTtgv5SS/j8U/b/pv2ccu4xs1g0Y/xviV5M+trlqZV8cfnaltgs3nOErzOPgdZ405i1y kwTmXTAhn1/dSHrnyCHNnMXLpce8jsm9+796Vw0qJiJSO47flmswQsV3GqYyMncARZxY R8tNr/NDrSF6BcmlFMVI0vwZRmydTxB4+Vm7cfyx++ChCELFj6BmVZzleRV+fecOvhYG ZhLVA/RG5Db4nz8SQlEpKa/Es+76QHvQDNiTVa9gxD/58JOnL5j3MH4HwqEe3twWJFDH myug== X-Gm-Message-State: AOAM532RfUkuqcvw4QgAurpY12U1bRS81G5/Ny8UvQ1p2zUBn3pVU/C3 mh1qhI8Y+JoTjFYCyS7TRrwCzqN76pDRJA== X-Google-Smtp-Source: ABdhPJy4w0PHkB0pP5Tkiro6/Yj2S5D5Skwh5s+jWobkVyz68are/r42tUj2++GjSIG4AfM047CQUg== X-Received: by 2002:a05:600c:4113:: with SMTP id j19mr1301843wmi.82.1613492222076; Tue, 16 Feb 2021 08:17:02 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/40] linux-user: Introduce PAGE_ANON Date: Tue, 16 Feb 2021 16:16:20 +0000 Message-Id: <20210216161658.29881-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Record whether the backing page is anonymous, or if it has file backing. This will allow us to get close to the Linux AArch64 ABI for MTE, which allows tag memory only on ram-backed VMAs. The real ABI allows tag memory on files, when those files are on ram-backed filesystems, such as tmpfs. We will not be able to implement that in QEMU linux-user. Thankfully, anonymous memory for malloc arenas is the primary consumer of this feature, so this restricted version should still be of use. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu-all.h | 2 ++ linux-user/mmap.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 6421892830c..aedf5345449 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -267,6 +267,8 @@ extern intptr_t qemu_host_page_mask; #define PAGE_WRITE_INV 0x0020 /* For use with page_set_flags: page is being replaced; target_data cleare= d. */ #define PAGE_RESET 0x0040 +/* For linux-user, indicates that the page is MAP_ANON. */ +#define PAGE_ANON 0x0080 =20 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ diff --git a/linux-user/mmap.c b/linux-user/mmap.c index ac0624f31ac..c52b60482e1 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -599,6 +599,9 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, in= t target_prot, } } the_end1: + if (flags & MAP_ANONYMOUS) { + page_flags |=3D PAGE_ANON; + } page_flags |=3D PAGE_RESET; page_set_flags(start, start + len, page_flags); the_end: --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613492620; cv=none; d=zohomail.com; s=zohoarc; b=jLXFw9xfMR21N1UK0ogdDz4LTZW6U9QEi2oDtL0NKueaWQuxQo8soLz2EhoQaORtugww2I/dOFWzMRHODc2IPPYtLf+Vc11Y2e68NVdjs6eYUD58xtfYmPsBx7jE8tQha8zNGcFwQAGV86BIlPWbLjQuuAZOKkou0jygVyJjmnU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613492620; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=67NjhYcvT+rwa0jI1Adgmqw2qeMw5yrlbnrugtQZnJo=; b=WkYoJXtgmofVuurlX7nI0DOt3jd6tmaK32H4/b+zCeKZVOAoSwcO+yTuYaloU4mJjeMc0odunGnAQeHx5MbG30hMn5DLt9g7Cxj93Wykb5QauO851Dm1ahNKCKps4oWp0zEjhJA5BFIYnilO6IP6GRr5fiuO+dN4g5uRLk12+TQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613492620112578.9265388341282; Tue, 16 Feb 2021 08:23:40 -0800 (PST) Received: from localhost ([::1]:44252 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC38U-0006bU-Oc for importer@patchew.org; Tue, 16 Feb 2021 11:23:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39788) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32F-0006xd-IZ for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:11 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:52212) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC328-0002MD-US for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:11 -0500 Received: by mail-wm1-x333.google.com with SMTP id o82so2236276wme.1 for ; Tue, 16 Feb 2021 08:17:04 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=67NjhYcvT+rwa0jI1Adgmqw2qeMw5yrlbnrugtQZnJo=; b=qPvfc5YGo8aVTNaf/OZxFmlU/sBdERwvkio1wdem8ghltrKUuP217ndZ5UhnhMxUff VVZTK2VgNcl9mpHfKmodd9bUNjuauEvbbkZY9OABqmP5pKxoUWTEF0oLoX8v5HaxXjap 960cpkhbQZAhH224HtgHNnGuzbhKGsC1LVGw7HLghizkmIW4Gg1A/8NaqKItwJf2qdqK pULefDLhzPeevLfL585O53UX7svfjvpxKzNbBx5xyEqdyfYstCT0a9MZzyVVIZK1xAlC a/k+yVF9N034Oe9h02r9Q+TmFdek43jZbZ+5GIO7ItqXCmK/Me/C/NEVxuvMLdWoaflx PnGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=67NjhYcvT+rwa0jI1Adgmqw2qeMw5yrlbnrugtQZnJo=; b=WWaoto8SFI334ep9IFWb9OaC2U4vU8+mrZ6zCSPvagdVfRc4Wbsq/3joQ8E/GqJ5gP paaSkz86/SpXNjttFvzcrFCCVUNvA2W2hpppWeT+N52CvzvQcnDBW7Dee/268LB8f4ye 0FjbXswYYCrO0I6W2HiGOwX3uRaGZADx3oTa/AxN7Hmo+QLybePEKeevSZL08roJST2B 6YgpSyWOY/PwiHG+VCHUHD4Tn4Rur89q6jUdagfy6e1txEu+5h58nvOIIWmOyaDcGpVq bC3G8WrXKxdw0PgcczjZNVhGtxE++KedRUzyVgGvwRNPRNFJzaXlewmswS4awO+By3Wq Bx8A== X-Gm-Message-State: AOAM5321K2NPYZNqI6J3qBVTqLaNDXsHUtnM9hC6WCD8MHjd+WWBLgX1 bCZPqZNkeJdKqDfxcn1w1Pzd0ITwaDI/AA== X-Google-Smtp-Source: ABdhPJwGaulA2xxJ2481J4iKk67V9svxpi/l1ibcDe95E83d5UbKwelwnwvlYNc+rgOro9lztSY8rw== X-Received: by 2002:a1c:4d08:: with SMTP id o8mr417847wmh.47.1613492222718; Tue, 16 Feb 2021 08:17:02 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/40] exec: Use uintptr_t for guest_base Date: Tue, 16 Feb 2021 16:16:21 +0000 Message-Id: <20210216161658.29881-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson This is more descriptive than 'unsigned long'. No functional change, since these match on all linux+bsd hosts. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210212184902.1251044-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu-all.h | 2 +- bsd-user/main.c | 4 ++-- linux-user/elfload.c | 4 ++-- linux-user/main.c | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index aedf5345449..937becd320a 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -150,7 +150,7 @@ static inline void tswap64s(uint64_t *s) /* On some host systems the guest address space is reserved on the host. * This allows the guest address space to be offset to a convenient locati= on. */ -extern unsigned long guest_base; +extern uintptr_t guest_base; extern bool have_guest_base; extern unsigned long reserved_va; =20 diff --git a/bsd-user/main.c b/bsd-user/main.c index 7cc08024e36..385d35886a0 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -42,7 +42,7 @@ =20 int singlestep; unsigned long mmap_min_addr; -unsigned long guest_base; +uintptr_t guest_base; bool have_guest_base; unsigned long reserved_va; =20 @@ -970,7 +970,7 @@ int main(int argc, char **argv) g_free(target_environ); =20 if (qemu_loglevel_mask(CPU_LOG_PAGE)) { - qemu_log("guest_base 0x%lx\n", guest_base); + qemu_log("guest_base %p\n", (void *)guest_base); log_page_dump("binary load"); =20 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f5bd4076fcf..7ec9249c256 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2135,9 +2135,9 @@ static void pgb_have_guest_base(const char *image_nam= e, abi_ulong guest_loaddr, void *addr, *test; =20 if (!QEMU_IS_ALIGNED(guest_base, align)) { - fprintf(stderr, "Requested guest base 0x%lx does not satisfy " + fprintf(stderr, "Requested guest base %p does not satisfy " "host minimum alignment (0x%lx)\n", - guest_base, align); + (void *)guest_base, align); exit(EXIT_FAILURE); } =20 diff --git a/linux-user/main.c b/linux-user/main.c index 2e3c1698787..81f48ff54ed 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -59,7 +59,7 @@ static const char *cpu_model; static const char *cpu_type; static const char *seed_optarg; unsigned long mmap_min_addr; -unsigned long guest_base; +uintptr_t guest_base; bool have_guest_base; =20 /* @@ -824,7 +824,7 @@ int main(int argc, char **argv, char **envp) g_free(target_environ); =20 if (qemu_loglevel_mask(CPU_LOG_PAGE)) { - qemu_log("guest_base 0x%lx\n", guest_base); + qemu_log("guest_base %p\n", (void *)guest_base); log_page_dump("binary load"); =20 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+NAflEZcFdaRslOS7OY9WO2OvINuWrOKI1AQgGCdq5E=; b=wI0EGYdyVSTeA62Cug/wdDEegQGCGDbscjshcFZ9Pf/qpfiWl275gxmsIU+wlqI6Oa NyMq4G9tKmRUwyGCTMG8nkJ4hS4Oposrz5RLsAjeO4w+iz/LsUToM9MxvhOW3FUNJp/u dGo1Ki2OOCRtPlDlW6QE784hg9yYmGApVBIN2IhvHaIL3hmwewRdrastCRiwYmYZBnCd Sb4XeCNRuLNdJzSaAfZuWNj5lznqo71BL6x/FT5JwxAzVEDZo62s1ehfxJWuTL021pWM dUnHo+7B/5gPy81e/c+PWbq+mpjT9z9HmT0rP/275RdhgteW9imQDnFgBWIYmnzVvtWg 5U+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+NAflEZcFdaRslOS7OY9WO2OvINuWrOKI1AQgGCdq5E=; b=rqqxs8GDMm0HSB6mq6g+tIgZlZ+3HCDyTpbC/zPiijGIw9Nq2V9s20b7mjikCC1cu/ UIUHK5qHIRvA9h91O0/cjXM9gL6conTUWwEo756TPVx1Bv3VGPGGD67Bg/reVmQRx2om CZULptKtygNyMVlIxpuuRBcrk64E7uYkN/MXhLUm3KyOw16g2D2zmDuixt3bStGhBI04 juZ4AC3VM1Z+CW8smZtBCPugvGUb7FhBs+jDHRo/c6pjdor6cMtC49SUBR9lbPhnwiFS R/vT82V+HUnhgVrHwpwV00EHU3wU2OzY+xZqVNPgn5/JLuIXgLjAIfRNppWrKnnDQ0sr rYZg== X-Gm-Message-State: AOAM532yTaQTj0goCDd1pT/XhoroBLcQUo6fcXbaV55V4bfj0O/MbY6I iON4ODWJ38D4Daam591LWPVW6hTbPf25cw== X-Google-Smtp-Source: ABdhPJxSkiRGs5GA1matfQsrMwmJPkO567Qw0BY5RzEqKwBm+UvbI+mohOgnmdBCRSv63peIqJkuYQ== X-Received: by 2002:a1c:31d5:: with SMTP id x204mr3825310wmx.175.1613492223335; Tue, 16 Feb 2021 08:17:03 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/40] exec: Use uintptr_t in cpu_ldst.h Date: Tue, 16 Feb 2021 16:16:22 +0000 Message-Id: <20210216161658.29881-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson This is more descriptive than 'unsigned long'. No functional change, since these match on all linux+bsd hosts. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210212184902.1251044-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu_ldst.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index ef54cb7e1f8..3f9063aaded 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -70,14 +70,14 @@ typedef uint64_t abi_ptr; #endif =20 /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ -#define g2h(x) ((void *)((unsigned long)(abi_ptr)(x) + guest_base)) +#define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) =20 #if HOST_LONG_BITS <=3D TARGET_VIRT_ADDR_SPACE_BITS #define guest_addr_valid(x) (1) #else #define guest_addr_valid(x) ((x) <=3D GUEST_ADDR_MAX) #endif -#define h2g_valid(x) guest_addr_valid((unsigned long)(x) - guest_base) +#define h2g_valid(x) guest_addr_valid((uintptr_t)(x) - guest_base) =20 static inline int guest_range_valid(unsigned long start, unsigned long len) { @@ -85,7 +85,7 @@ static inline int guest_range_valid(unsigned long start, = unsigned long len) } =20 #define h2g_nocheck(x) ({ \ - unsigned long __ret =3D (unsigned long)(x) - guest_base; \ + uintptr_t __ret =3D (uintptr_t)(x) - guest_base; \ (abi_ptr)__ret; \ }) =20 --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613492534; cv=none; d=zohomail.com; s=zohoarc; b=SIXxDOvgJ+OZbz8kbepbIKEmDIeLkHy28ovq6rbhMfBlDGqfW4yiYIso7Jme047VoB1F1kDbKgfMJ9VlvU3rEO3s3SuIVcIhBhKKEFwh9xZ+0tfixOezs4JAGOypSrKP+CekdNkKuVSRN5JLrZ0HIjwdsJyJdFpliG5PyD0suto= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613492534; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=N6RzNwKRNkNXeNEjKTeNz1uxxUp6u5ArdzgeljJclpc=; b=JCFiBKIwnAQUNAf800okQY0t0AB9lI5qaVKwDTE79OrNsSXgBzGUSmFm+0aAuhxOaocyu/sktuwv3GHSduQjQlqbplHidn1BgJ6cJrlU3DeycGH94HHIkhc3hUWsSSzkTYHkNPpxuiQLmJaYM6tuRIkbqCTbXwKV6iFyQMY7Omc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613492533707626.1329212637187; Tue, 16 Feb 2021 08:22:13 -0800 (PST) Received: from localhost ([::1]:39712 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC375-0004cE-QL for importer@patchew.org; Tue, 16 Feb 2021 11:22:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32H-00071b-PM for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:15 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:42070) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC329-0002Ma-Cy for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:13 -0500 Received: by mail-wr1-x42d.google.com with SMTP id r21so13739793wrr.9 for ; Tue, 16 Feb 2021 08:17:04 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=N6RzNwKRNkNXeNEjKTeNz1uxxUp6u5ArdzgeljJclpc=; b=savQDzN/EaSX6fd4z31qAVrUFwI4l9TWh50jKk0lCJudSa2pRC5tqiOgY7IdgjsZoA NZXAxbJwOAE2ioV0gjf3IXOBRHsa8ckxtyEEYXLIY+D4HDmtrHZ0T8Hv1RU5uK1gLfCY xUCvsjTtJFV4NcptascvzFi2pZyH7LC9e5rZnZ596tm8pSwN3T1lFz7fi5DuQ8iqMjQG DizTfUu7HEPDVYujdjBH6UigdZYicQEMTGE9akA8v5Sgzf/Yx6RRVsqRG/ONWo004mzZ EadUSwH4pch8BxsflvENxkHYPlTXgGcIrcQA0KDJEvVzbDMnVG5R4SdxugtdB2u7zUi5 7r9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N6RzNwKRNkNXeNEjKTeNz1uxxUp6u5ArdzgeljJclpc=; b=VnCNauqGVoO4Mw3we3LRTp3OR4leQDLdXabOqWgGQP6ihuUx05QKahaJDcshl13PXN ETzNaGuP6LrqkUgdseYX/MbFXUUx9MlyqvA7FzTDMPfT1ZzgjTUfojJjDX9P6DLLSmuw RtxlGClykw5V5m6NyMh+hZo0CkB5VMk3jutrw6s0RDhC4aEsJZ/J2vcEC1Jtwc4sbThw 5S6UWFXcTwhn7Fv8uWj9P3EUVTDVl8P6cchgAyOHtxaHeHWXhKrsXtjzPnALXXFH0bsx DaENuNpLu3Gea60rRRMic9TgLUhrjo5B4KvdRMlPKKDJ5UKm1hjsB0qOp2ic1XOU8p32 4GNQ== X-Gm-Message-State: AOAM5308h+02e7fHT1IOd2NmjvlGJLIReEw+1Szo0InDSwjQbn0phaqW 57+a/C5frs7CbayfMCXDgl6FVZE5UZGSQA== X-Google-Smtp-Source: ABdhPJwPNpnL5djIPhYKX7ioZ0WvLMCJhsf/J4M0FMNk3EuHoRa0kN7tfmF0JBhLB9Sn7NnSNIVQlQ== X-Received: by 2002:adf:d1ce:: with SMTP id b14mr23963402wrd.329.1613492223877; Tue, 16 Feb 2021 08:17:03 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/40] exec: Improve types for guest_addr_valid Date: Tue, 16 Feb 2021 16:16:23 +0000 Message-Id: <20210216161658.29881-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson Return bool not int; pass abi_ulong not 'unsigned long'. All callers use abi_ulong already, so the change in type has no effect. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210212184902.1251044-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu_ldst.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 3f9063aaded..5e8878ee9b1 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -79,7 +79,7 @@ typedef uint64_t abi_ptr; #endif #define h2g_valid(x) guest_addr_valid((uintptr_t)(x) - guest_base) =20 -static inline int guest_range_valid(unsigned long start, unsigned long len) +static inline bool guest_range_valid(abi_ulong start, abi_ulong len) { return len - 1 <=3D GUEST_ADDR_MAX && start <=3D GUEST_ADDR_MAX - len = + 1; } --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613492762; cv=none; d=zohomail.com; s=zohoarc; b=ObfexI/j24SDoqifwCrpVXbnQqb+fXSYvJMSLTq+Hvn6eNzQsP2wkWIJHn/ylskUFcTU0RW76QpyM1/BUvXcluNslzoDPqQF8StSwPKhTDWoBOLLDaOfSrsSpABiB8CcudXYe1it4IRi44jEwDOB6ASQnfoRpt7vQ2Ly4IG4+sU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613492762; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Mlct+xf6atwH2F+7bny1ciUcRQbh2ZMFeBccJN2qdb0=; b=CcrGH4GR4YXWaKXI2ZrXp7R7yY7PTc0xfagOpzeQJzpVPSP9LWAHN4X2lBRJflFmYkX4yMkOz0FU5Vk4o+SMngsyfiWIqt7dqFfe4BqcWs9PXo/K+55QYsLb6Hstocxd+HgpLHrWSzNIOIm0lDiQjCL5eOrn+BCe14d+wnIo0BE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161349276178366.16948856109582; Tue, 16 Feb 2021 08:26:01 -0800 (PST) Received: from localhost ([::1]:53062 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3Am-0001tL-0H for importer@patchew.org; Tue, 16 Feb 2021 11:26:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39940) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32L-00074c-Dt for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:18 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:37577) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC329-0002Mo-SQ for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:17 -0500 Received: by mail-wm1-x32a.google.com with SMTP id m1so15025905wml.2 for ; Tue, 16 Feb 2021 08:17:05 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Mlct+xf6atwH2F+7bny1ciUcRQbh2ZMFeBccJN2qdb0=; b=wwryUxyQB3YORbNFNgoxElWOs/WYVZtvQb5minWMsik+05Iz01P8rzWkJZjTLOwpZv HrIcptxsEOxIsJkX+fut0bInhSwIQtZCgOoeZwQV4bL+6l2bvk3yxCujnbGwsHCM07aa pQ72Hd8mgaIxivU4OdWqsxWQcF3hQTO4y+Tx03dvFdvO4VtUkj9p2tf51kkWsNIsEn/r FEBMQOYJeVrD7E90kJ9vreXyV7VS45KRDUNSBkGW1wJCeXvmLk+alKz8ysmQJvXRkxSQ vrXWmbZZZ9x7gklhG+ny4DUzGmvt+asGj2szxY56wJ0AXjhrWxqiU2YeRBa9aMLjubfj EIUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Mlct+xf6atwH2F+7bny1ciUcRQbh2ZMFeBccJN2qdb0=; b=EqZjMToW6PAASLkRi5tBPSHXN6w2VTN4MD0Ae117umdbfp3p3X0VlpMxRjCq3AU3oa tebq2IcvAdkym/pN5HlrV+NVjNHCuyql1qtTI3fihrXkAuX1FKOk5KcOvF4+jE5L7PyZ KVxktfUoGRJBqeLOiAWZCJEnHua03iG87lXH350ljoA4q5aJTT67h23kanWp9sSPK940 EpI3HcXyVHG83UAu98UR0WckB6LH5Wz7Br4Pfsy90oIkUEPqLVO0OXQa4UOS+UU9eFzA aiLJKpzl875SVBmZfqkoXR5ulcOkxVjmsr9c0Z2Dve6nxzd86UmvDpmF3rJKhAIR4QCr 1OLw== X-Gm-Message-State: AOAM530l1633Pp/WOLU8C4b6qI6bSkvCtFMTe47wIqoJIOfNknUECHED cbN0mcpon9YofC8GSmhqellREZPiLLNHMg== X-Google-Smtp-Source: ABdhPJynyylOala1fK0ZUziCCZvwYxQyoBQnpTJQgm1UEVnLNILhfsgM2v4teMAnf8ukFOD2fcH2sQ== X-Received: by 2002:a7b:cb58:: with SMTP id v24mr3890690wmj.182.1613492224465; Tue, 16 Feb 2021 08:17:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/40] linux-user: Check for overflow in access_ok Date: Tue, 16 Feb 2021 16:16:24 +0000 Message-Id: <20210216161658.29881-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Verify that addr + size - 1 does not wrap around. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/qemu.h | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 17aa9921657..441ba6a78bb 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -491,12 +491,19 @@ extern unsigned long guest_stack_size; #define VERIFY_READ 0 #define VERIFY_WRITE 1 /* implies read access */ =20 -static inline int access_ok(int type, abi_ulong addr, abi_ulong size) +static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { - return guest_addr_valid(addr) && - (size =3D=3D 0 || guest_addr_valid(addr + size - 1)) && - page_check_range((target_ulong)addr, size, - (type =3D=3D VERIFY_READ) ? PAGE_READ : (PAGE_= READ | PAGE_WRITE)) =3D=3D 0; + if (!guest_addr_valid(addr)) { + return false; + } + if (size !=3D 0 && + (addr + size - 1 < addr || + !guest_addr_valid(addr + size - 1))) { + return false; + } + return page_check_range((target_ulong)addr, size, + (type =3D=3D VERIFY_READ) ? PAGE_READ : + (PAGE_READ | PAGE_WRITE)) =3D=3D 0; } =20 /* NOTE __get_user and __put_user use host pointers and don't check access. --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16134927517171011.8479549770417; Tue, 16 Feb 2021 08:25:51 -0800 (PST) Received: from localhost ([::1]:52066 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3Ab-0001Ue-Nw for importer@patchew.org; Tue, 16 Feb 2021 11:25:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40032) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32R-00077f-0r for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:24 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:42078) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32A-0002N4-TK for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:22 -0500 Received: by mail-wr1-x435.google.com with SMTP id r21so13739885wrr.9 for ; Tue, 16 Feb 2021 08:17:06 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=r54xv40YLSv8QxrOB/Rr5FE/dlpTfC1FACPhqcFCkyM=; b=ZOxHKyS/lv3w5MGir8b9dBkKM4dpiXuQ4VYJIbbHtvc1+zPh7sHEpGEY64NsARoORy AE/Vbj1MENWTHh6/lSaPiH91RYij/EvRkGM8aeFzFlJnYz8x5C3KbIt4Wwp25SJI59Fs 35QCFaraxfc0ON7kNWC16Jq+DAhbB8wtn85C7uPGNEBVqkbLOIBxcDYZ+9wBmFt4Sh6b 0KQs7PX5nHflXVpWe05uF3n1cfYjgsTH/O7ViLAl168hMJ1FJi1iOTRvBhjvtNYEki6s w+xFRwIqH3Kuc6MXBoPbUCUhTyKRhVeqRhwfYsjj4H9wfqrFk+KMTASwEZOOsYeBUdr1 mGwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r54xv40YLSv8QxrOB/Rr5FE/dlpTfC1FACPhqcFCkyM=; b=Mz23FIulHJexCNylWN95QhNwYULI33CQigj0SSwQOGff6MMcdeok5Z/XmivzpuWaP8 L28BHidWYhFm/9IBxzq0+BP35z8qX2epI8OVWLtQsr+U1vYJyCXOg3hnKN9G0Ft/TaWI tp1IVQGOofX6vd95VQpDrNv7lVmWkzx+1gwbKAfPm0VBYPLiz1KWuqjSa1MgMJMJfoK5 JheAn+6i1MdqCm/ybNrurRVIgWPKs9PF24gHtNhlH5qPDpFXiPHleT+qrrqomwFqARBX OSCheuwcLa+O4mhDEwnW1PqBOOPpSp0MT9tXCiECvT1m5Nw6Yd/NGjAWzQtaSYxdg9JC 8oUw== X-Gm-Message-State: AOAM530cyKqN0yZNDOdD1creNWHQWq5wMcxpNsiDI6sRQryQ30Z9wLpt 3V/s3J1MSHuOugUEPxeutb6rvmzUaSek7w== X-Google-Smtp-Source: ABdhPJyRKdgTX+0bjevqeCd0npCX8SNL6kCq9+ubF588L7iyHLYWtLbC9/smIljZ3Y/lITOXz2zSSQ== X-Received: by 2002:a5d:6883:: with SMTP id h3mr24142585wru.90.1613492225068; Tue, 16 Feb 2021 08:17:05 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/40] linux-user: Tidy VERIFY_READ/VERIFY_WRITE Date: Tue, 16 Feb 2021 16:16:25 +0000 Message-Id: <20210216161658.29881-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson These constants are only ever used with access_ok, and friends. Rather than translating them to PAGE_* bits, let them equal the PAGE_* bits to begin. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/qemu.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 441ba6a78bb..9251337daf2 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -488,8 +488,8 @@ extern unsigned long guest_stack_size; =20 /* user access */ =20 -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 /* implies read access */ +#define VERIFY_READ PAGE_READ +#define VERIFY_WRITE (PAGE_READ | PAGE_WRITE) =20 static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { @@ -501,9 +501,7 @@ static inline bool access_ok(int type, abi_ulong addr, = abi_ulong size) !guest_addr_valid(addr + size - 1))) { return false; } - return page_check_range((target_ulong)addr, size, - (type =3D=3D VERIFY_READ) ? PAGE_READ : - (PAGE_READ | PAGE_WRITE)) =3D=3D 0; + return page_check_range((target_ulong)addr, size, type) =3D=3D 0; } =20 /* NOTE __get_user and __put_user use host pointers and don't check access. --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613492746; cv=none; d=zohomail.com; s=zohoarc; b=G0ZzSYdPSHoUjn/IaW6a0s0oAk6jI/QoAgbHyIUdGJQG3zwWYx5LoBEqft5QTohrM/bkH3xtQtPvIt6/qf9VRdhLRMTTydFKFEI2IP2CT/8pvn5ZspH/q86xC3V/66gXSYkms4q52h3EY0RXqr83wte1CkEp3HrlhEFNH1vEozQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613492746; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KtovKvTGdkOvy7IKN3clRcQY8cM5rmonWpslYQHWQiY=; b=OjEwb2Pei4U4whCULR5bx9sF87kB9lQJgkTUfw+6E9f03EHcPgPMQmvYIsWgJ7owJWqTf/hpwf8Rw1ImLRc5f7nG4El73SGFF9Dr2mun4N6OYW4Mx/WNL72zwTnInhMKWiLwmjAhfZoRBgon5i3DEQW2VWx8wj2WDiz0iH+jdDE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613492746416828.6395216848681; Tue, 16 Feb 2021 08:25:46 -0800 (PST) Received: from localhost ([::1]:51600 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3AW-0001Il-Oz for importer@patchew.org; Tue, 16 Feb 2021 11:25:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39982) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32N-00075o-Cc for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:20 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:54082) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32B-0002NM-2X for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:19 -0500 Received: by mail-wm1-x336.google.com with SMTP id x16so1186296wmk.3 for ; Tue, 16 Feb 2021 08:17:06 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KtovKvTGdkOvy7IKN3clRcQY8cM5rmonWpslYQHWQiY=; b=xnUOCJdJmqp7Az6JvKr6mYt162i1ua0kXURL16kcb/zPRnDgAGSdakWE0d05fsD0Gl EG3xcEOO2SigmBZJX9zxMghXUzLK0XhhUOv72uuczbqzHtf5LM3yTYSjbjpT9Zwdj/S4 bkFsQ1yvpMXxo3GSbBezr5P90KW0vkSjvTX39GmDA0zcmp+YmwLJ7NhTpJytdEX15dcc TfWTpWVv7zbylWMDj5nfJFGL7K+c5VhbefsOX8us6hY4cj1q/QKxJnOkYzbX/sFK3flE fvSlHkh7dO6Fuqwa/9d/8YANxioitWWmEplLpyV1+vG4rfxQWOvdkUqacH5yo384Co1C YZxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KtovKvTGdkOvy7IKN3clRcQY8cM5rmonWpslYQHWQiY=; b=C+AGBxENaYMPzMGAHFFsodNUZtVKP04SroZYWHFP2B+Rp70HVPjiCgnPeFX4BLOq0J UFjURHoQZOOwywQsoLvtIu3JTrESyYUoGhYz2B/T815XGhS3n9072iQMUqYuioMy849Z ctCPpWM+KhqjVn7+e/26btJ0ylJnnvmphiCiWF+7l6MrQwkWD59Tj3x19s/Y9/SaUi95 C21t3HixCBvKWMWpquMkZof+cFjWtu4NQrlEMTX0pRAaMlcJBQ0+a7cUvGaqnM21I3C2 4EpFSSgxzf2rpr2Zu3/asRIE3QlBLEzVQnlsYsv7Z64wIe3GTAenT+u0MBYv3tsdlCQj qoKg== X-Gm-Message-State: AOAM533OtQAnTxctaHl5Zk6aS5L5jImJYtlMoz5nnEmSbq9pNYM0nwHu MGiGwus/Z6mlXrkESb/m3rjzLhG/Xj7zTg== X-Google-Smtp-Source: ABdhPJx/UJb1djm+b+6LkyS96EzGNtI7NtdHJo3EwSZmwON2PaKXV1UT8bqTYGJpQWHZnCo92pWZVg== X-Received: by 2002:a1c:1dcc:: with SMTP id d195mr3993473wmd.42.1613492225765; Tue, 16 Feb 2021 08:17:05 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/40] bsd-user: Tidy VERIFY_READ/VERIFY_WRITE Date: Tue, 16 Feb 2021 16:16:26 +0000 Message-Id: <20210216161658.29881-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson These constants are only ever used with access_ok, and friends. Rather than translating them to PAGE_* bits, let them equal the PAGE_* bits to begin. Reviewed-by: Warner Losh Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- bsd-user/qemu.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index f8bb1e5459d..4076adabd08 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -218,13 +218,12 @@ extern unsigned long x86_stack_size; =20 /* user access */ =20 -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 /* implies read access */ +#define VERIFY_READ PAGE_READ +#define VERIFY_WRITE (PAGE_READ | PAGE_WRITE) =20 -static inline int access_ok(int type, abi_ulong addr, abi_ulong size) +static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { - return page_check_range((target_ulong)addr, size, - (type =3D=3D VERIFY_READ) ? PAGE_READ : (PAGE_= READ | PAGE_WRITE)) =3D=3D 0; + return page_check_range((target_ulong)addr, size, type) =3D=3D 0; } =20 /* NOTE __get_user and __put_user use host pointers and don't check access= . */ --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613492606; cv=none; d=zohomail.com; s=zohoarc; b=Oq8fXHvkyw7e3q1beazT1TN9PWL1P2/NtavpXRlIFjWpSe5Ch1wCdSDBupbhFaJqudfrJ0uowtHplnQuGxNVbkGZvKNYGfNASC6VcMlaY8QIngWz/Ugd/NZCZjorIb5UhEhJlnRqozc/QO/YkaCRzjC4Ejl0HaVmPhbCA17a7u4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613492606; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eLIFGOg5HdwkmbKxogMzFAx4aIK6dBBp+2Y0jeJHbjc=; b=L5QYKMsyjS1Ix9koB6WI0R4iVtTzKvBZr433Dm2b53nmDCXV6ZYvFcBoKfdOQi4VELfFV+U5/D4lQnepZ+UHCQKFbo3TCQc664oMRh44y8fLevFfIixwAEZK4kBIW5Io2Jr+YnGZgFwzvb8rmOnN2bR5fgdV3Xzd8rmegsskFU8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613492606390567.432021467911; Tue, 16 Feb 2021 08:23:26 -0800 (PST) Received: from localhost ([::1]:43394 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC38G-0006GO-S7 for importer@patchew.org; Tue, 16 Feb 2021 11:23:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40002) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32P-00076O-00 for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:21 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:45304) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32C-0002NU-30 for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:20 -0500 Received: by mail-wr1-x42c.google.com with SMTP id v7so13748733wrr.12 for ; Tue, 16 Feb 2021 08:17:07 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=eLIFGOg5HdwkmbKxogMzFAx4aIK6dBBp+2Y0jeJHbjc=; b=EiYunK7m5qgiSn57VzBQNHrDWW51lo8jgNAbLJxqiw3bhtsAgqO5uMHPJ6+/+dxWK6 4wYW2X3A7gZDC428P7iJKNN2Sb8JpM2GVO6ArQPcm7O3mZKGNUwXilRgI5mAPStjO0MB /ECcXmIsJaVidMBGLTfVFPi8n09mehTDJ3CDib6PE4g8Ep1+2Cok1msGw4pLcAHhLtgZ aDKY22RoCiDi9M1EZhENSwcaP8iijishRAWfiha1PsibghyMj69u4ONYOijDKCBFRsmn KGn5rN6p6MW0SvN7KdGKLR/LesQPEeP1sKBGh6Muuve77tn8D5YTMUF3OMlX7WdpZ07l x63A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eLIFGOg5HdwkmbKxogMzFAx4aIK6dBBp+2Y0jeJHbjc=; b=qxx7YXeYRwMA/9LKDTCe4edM+bKRHOAj3yUmkBHZQ/60VTEdiacRJYLUEYOvGRtAoI vh07bLtg4PYIP8zzmdg/U4ZrhZis6lcE635A/HbgWhC5f0z9xu9jaChMOVOyhDEqhzO9 lyCZAdfInAvVq8CwX1e2w0JEngro2VnTnKaVj77cGO/drR3XjjEBzPlV71z4K5/E7Wsv Q7M8flElUwZVAEHQY/tU9FJyPmmrKN1mH7NyH3cI5TsY+jNQMOHY1leHAJ5akn613MIn wbb8y+YQPh/jhwU3wLx1RukYyKbjm/MEdjs0ITtrFRrjyYWCENQZomwmA86hj/rzHg45 59dQ== X-Gm-Message-State: AOAM533h+ypS4BGaC54puwPSzdI64CmmvzJFuMfSrK/RUhMLsDtvBJCd dxdVJYyw8pYjjRovu1ZVbZJ2Efor5OKwXg== X-Google-Smtp-Source: ABdhPJyZxtr9ZkroibCGoGiuK0Oo2NO9j/umbhBgjWmwyfk1iWm5EMvAoBgEYVbP+bnL64vQ1j2ftQ== X-Received: by 2002:adf:9546:: with SMTP id 64mr25387310wrs.247.1613492226365; Tue, 16 Feb 2021 08:17:06 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/40] linux-user: Do not use guest_addr_valid for h2g_valid Date: Tue, 16 Feb 2021 16:16:27 +0000 Message-Id: <20210216161658.29881-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is the only use of guest_addr_valid that does not begin with a guest address, but a host address being transformed to a guest address. We will shortly adjust guest_addr_valid to handle guest memory tags, and the host address should not be subjected to that. Move h2g_valid adjacent to the other h2g macros. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu_ldst.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 5e8878ee9b1..4e6ef3d5429 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -77,13 +77,16 @@ typedef uint64_t abi_ptr; #else #define guest_addr_valid(x) ((x) <=3D GUEST_ADDR_MAX) #endif -#define h2g_valid(x) guest_addr_valid((uintptr_t)(x) - guest_base) =20 static inline bool guest_range_valid(abi_ulong start, abi_ulong len) { return len - 1 <=3D GUEST_ADDR_MAX && start <=3D GUEST_ADDR_MAX - len = + 1; } =20 +#define h2g_valid(x) \ + (HOST_LONG_BITS <=3D TARGET_VIRT_ADDR_SPACE_BITS || \ + (uintptr_t)(x) - guest_base <=3D GUEST_ADDR_MAX) + #define h2g_nocheck(x) ({ \ uintptr_t __ret =3D (uintptr_t)(x) - guest_base; \ (abi_ptr)__ret; \ --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613492955; cv=none; d=zohomail.com; s=zohoarc; b=lT8GGb6RGJziu45IJOPhW+TwC1of4ya648SmrYUK9tRHzypUdP+3lVY1K7ZgEuxV8iUDY7uOa6f/GKzZh4W9Dj5Rwvja++6nmyaGkjKXc+6wzbKqUKh9SvEMKtxxkOIDKcPmC+YBt0bLGjrqrTRuiGFqYIYFq2PFBbnUYwgqqVA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613492955; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tJYREiEwDxpVe67h98x1We/4+RbYF4snD5TK+jsNzDU=; b=L0oZPKRIltVWf/FmZSP9XKfdK6OLWYvEt0SuQijRGNhLgf4Fi8stxm63jlTCJubp0GqVnotJtHrjC0eCsUpjkFNRMbUOiEW9Ukzawpm6V3aOsXSh+/lE4cBVqwBUHNgybDOFe+jmZcaVvt/ROmV2WPQGPosUDO/FmvoSpeS2aV4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613492955239400.46163929153136; Tue, 16 Feb 2021 08:29:15 -0800 (PST) Received: from localhost ([::1]:33342 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3Dt-0005Wr-AG for importer@patchew.org; Tue, 16 Feb 2021 11:29:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40046) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32R-00078G-SC for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:24 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:53114) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32C-0002Nh-CH for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:23 -0500 Received: by mail-wm1-x336.google.com with SMTP id l17so9578795wmq.2 for ; Tue, 16 Feb 2021 08:17:07 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=tJYREiEwDxpVe67h98x1We/4+RbYF4snD5TK+jsNzDU=; b=PAsxD+68PmDbV+rVh4t8l5yttLhmWueHh1Ekx6CpHORu2B8z1YsJmqJ0cDqcjQEDEJ ll5RcOZvks19hdmCdAR9T0SfxBBzYdJEEawJjezXtWVJQGWXwX+9G9O3yH9tiQZ56wa5 xjkgHDaB9w2Zf60SrNFccVx365YMsX9lkRcK0TFv1lOnECLH9N6lYP1d/pFXTDfGWIh8 TGr8i5YRPuNBR2KANoiiA2Gsw3ipxjMhJhAOC+NIm70M+zzrXudSE9P09W+Ygt03ZABw bGg+LPZ4P+VuRvrY+kXLVwlXY+wg38URn/Er+zRQ4B4cXOUIv/TrxPN/rWXguuGn2HQK u6Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tJYREiEwDxpVe67h98x1We/4+RbYF4snD5TK+jsNzDU=; b=j/LkY4HJWtmy3uumEvALx2YJf6TNARbtB1ggNrTsg/FJZA9qjdjXJVEK1XyD+rRxiK m4MEaY5bsvLedehwA2cWi0SAgsC2G3CuhBXBsPEBEhHYZSOkigvvWcT5usGHPqddEeLc 9OOYnSDa3Cg5ssfPHCw9cewcew5G5yryfGLkC8+bGBHqkTct0DlKBzLyLBFJsQ2WeOsp OcX8WiMqaxOCy9EWSy1BRk8CyueD6foBZ21xHY+vZ7M+VM8llH3/6EHA7hirprFB/qDe LUP67wVSDEuqkbFCHpOKXZkzCXEZX9mLeGY3cltnSp5nm8HK5VMT3Sx4rGGSlTaIZsOG GfnQ== X-Gm-Message-State: AOAM531ZMvPElsreWpCqxXWgy/BiCevLo1raiBT3pdEWMr5aKeoxx1Ix 5haav6bpK0kJOPTvim6VZVX1WtpFPcIK9g== X-Google-Smtp-Source: ABdhPJxFpSGP6TQ4iZWSQlKAGIX6+lg7bnSRKF7bpoDOXkUkYhh/z7Y5amrn7UHvyHVQJV0lDoiULA== X-Received: by 2002:a7b:c341:: with SMTP id l1mr3732159wmj.182.1613492226949; Tue, 16 Feb 2021 08:17:06 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/40] linux-user: Fix guest_addr_valid vs reserved_va Date: Tue, 16 Feb 2021 16:16:28 +0000 Message-Id: <20210216161658.29881-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We must always use GUEST_ADDR_MAX, because even 32-bit hosts can use -R to restrict the memory address of the guest. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu_ldst.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 4e6ef3d5429..e62f4fba001 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -72,11 +72,10 @@ typedef uint64_t abi_ptr; /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ #define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) =20 -#if HOST_LONG_BITS <=3D TARGET_VIRT_ADDR_SPACE_BITS -#define guest_addr_valid(x) (1) -#else -#define guest_addr_valid(x) ((x) <=3D GUEST_ADDR_MAX) -#endif +static inline bool guest_addr_valid(abi_ulong x) +{ + return x <=3D GUEST_ADDR_MAX; +} =20 static inline bool guest_range_valid(abi_ulong start, abi_ulong len) { --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613492712217934.9377306950317; Tue, 16 Feb 2021 08:25:12 -0800 (PST) Received: from localhost ([::1]:48274 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC39w-0008LB-PA for importer@patchew.org; Tue, 16 Feb 2021 11:25:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40080) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32U-0007CK-0L for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:26 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:40448) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32D-0002Nw-0a for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:25 -0500 Received: by mail-wr1-x433.google.com with SMTP id v14so13772300wro.7 for ; Tue, 16 Feb 2021 08:17:08 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Yx6GjGifPHZR5LcFBsAiUTfVfcMj2IHIVadIskasFHE=; b=tasx1bAQO/VJ/uXq0eiuZUfnLBeqxjhcfxUfZmGnRmSdOUQyo/FbYMbAOGzexDEn4/ kSyGDgK8iYI/0dIFx1fBAZ99qqPpHXTp1CZIk0Q5mDxgkSXcoo1IlNVgU/y3JKr3ciwG 4mmEn094NmAlthXWnhTY3nPGNqDKuHVyGQ2ed8eGyGS/L6dwHaJgt4tUx54VjdgGDmsI wuPXZ0ULa+z3/0O+vuA8UOTyJL+xSW7p4lI2LRfi/5i+117W8g722BkY+kSpKvxi5sYH xQoJRR3NvMq6TyarAMCBmBkDVHG0Egn/dH9efC/Gq/cwcIHaWgvfdcWkpHEr4QxbFLLb kqGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Yx6GjGifPHZR5LcFBsAiUTfVfcMj2IHIVadIskasFHE=; b=gMEIAQbo49uBnb6yKEiR2CS4D1Xw5A6zdvsy+O/fNuGBcbXTKlLDRvOL/6uBT/V7XZ EE4sPlGL+heDIG0ykPDx8K/TtlNHjpHmQuXxUANmXBjw4vVXsrYawlT5iNdb3H/a0tFb M2wuuEnxYl7vna03o0vBZuwv/y1go3H+ychYA73Ui0Yx+dOHH0AwC3ssWwvqiPtGzedu H2zExPrMJhMYfmReII+d/9mQ+eEj2E+MBYz1XNkC9cZXQ6k8pK/AMgob6tR3s5mLdahu 0mHy3vy8dD4I452Jop3bnT7fN6IvO78jtKXRT9UagyGLnMgyZC1n7k7v/pk6OpozsZCe iHKQ== X-Gm-Message-State: AOAM530yKl5GQvqn7t/H6GvEbufkKLvCo62t7hJqvHEyY3d245Lseasi PYyC8bFEWF+JY/f8SMd8P2GT1tq6oTqMpQ== X-Google-Smtp-Source: ABdhPJwWk7wNW2T1T+ExEkGCXjDlKvaawuLWlptPZt+g/nLbil0DTSbnT0iX5OjWav2Y7ZedMinUog== X-Received: by 2002:adf:e94c:: with SMTP id m12mr25315049wrn.146.1613492227544; Tue, 16 Feb 2021 08:17:07 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/40] exec: Introduce cpu_untagged_addr Date: Tue, 16 Feb 2021 16:16:29 +0000 Message-Id: <20210216161658.29881-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Provide an identity fallback for target that do not use tagged addresses. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu_ldst.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index e62f4fba001..d9dc1de414a 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -69,6 +69,13 @@ typedef uint64_t abi_ptr; #define TARGET_ABI_FMT_ptr "%"PRIx64 #endif =20 +#ifndef TARGET_TAGGED_ADDRESSES +static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x) +{ + return x; +} +#endif + /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ #define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) =20 --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613492946082877.1723284232152; Tue, 16 Feb 2021 08:29:06 -0800 (PST) Received: from localhost ([::1]:60444 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3Dj-00054i-9r for importer@patchew.org; Tue, 16 Feb 2021 11:29:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40260) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32d-0007a2-DY for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:35 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:42079) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32E-0002OW-Jj for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:35 -0500 Received: by mail-wr1-x435.google.com with SMTP id r21so13740194wrr.9 for ; Tue, 16 Feb 2021 08:17:10 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=kbRIvgMCJv2MfoVwhR7j8Y+Gi0EkYODCYNxvSWd9s0w=; b=j+WTSDuXJyPdTAPlDpHgM9rfOB3HJ5lpEXUsFR6dMl9ua64HIV5vTpg/9fX9BDX0qs o9Rg1EWbbXLamDmV9ICx4K+Z1XGBtllyuDufFYJspdhN8TvHOEvBC0J/kUUqFJ1kmuZ0 wXK6DW2quozbJBt2d1U31EVbNDF3bcsL7RMdH1VOxU0n1i9VPL+eTxwLiiVJ4AcUGqjV wCNPq7DyzHy0fGUULqs+BDfnIpiAxNwHLvUkA78e9xdIMkQbB5ghD+hgjFOCUwS/e0C0 KAu2hy3e5eKeAbnpUQxbLJ6+h1Hm6qak7XfPYyKNGRWiHI1mv2F0ueyqrt/SkX9NH1xl 0rcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kbRIvgMCJv2MfoVwhR7j8Y+Gi0EkYODCYNxvSWd9s0w=; b=jFTydcoGiUz42DpSTm5sb71HU46yGu0XL0tyhww7sDOfxDYVrEBGG+BZTCNOMxK+jf rSt8Sx0/f/5FvoR5xOwy25bTGHuyeBBPvJXkHKodkS7AIrsN/cZFn4Uj1+JEMRnn9iKq SZxE1soPiEM0/DUrv6Y7KlfMeqpxa7VL9T8PLCxdCrtXsX2iSubcXJiB0VCd+eIPT829 ffIxX7tcmT9OsUkm2bNxbQL2om4d8JNliTAyKsBzkZILoGcczlok4YSS7CB5vIaLGRpj SLaZ1FLodVh/lmUY1qBSYxF0TwP/YKzPJRZZPUqIt7vQTjgxT89SjNTiaY+85EhSTZnk QCdA== X-Gm-Message-State: AOAM531OV3qbkhnQo4GHD2Gr4FrbbOrGVsMo+T9mi4uMA0BKJNAn09cy kmLF6ufeX8l4j9d1xBBGNeaIho22fYqFYA== X-Google-Smtp-Source: ABdhPJyZVJs0+Zy1OrhGnDmOwiBTYO0/M+AoFCa0Ff6U4liI088qY6IhVPSohewW8IEjTAbHlkzSww== X-Received: by 2002:a05:6000:4e:: with SMTP id k14mr24356764wrx.281.1613492228921; Tue, 16 Feb 2021 08:17:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/40] exec: Use cpu_untagged_addr in g2h; split out g2h_untagged Date: Tue, 16 Feb 2021 16:16:30 +0000 Message-Id: <20210216161658.29881-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use g2h_untagged in contexts that have no cpu, e.g. the binary loaders that operate before the primary cpu is created. As a colollary, target_mmap and friends must use untagged addresses, since they are used by the loaders. Use g2h_untagged on values returned from target_mmap, as the kernel never applies a tag itself. Use g2h_untagged on all pc values. The only current user of tags, aarch64, removes tags from code addresses upon branch, so "pc" is always untagged. Use g2h with the cpu context on hand wherever possible. Use g2h_untagged in lock_user, which will be updated soon. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- bsd-user/qemu.h | 8 ++-- include/exec/cpu_ldst.h | 12 +++++- include/exec/exec-all.h | 2 +- linux-user/qemu.h | 6 +-- accel/tcg/translate-all.c | 4 +- accel/tcg/user-exec.c | 48 ++++++++++++------------ bsd-user/elfload.c | 2 +- bsd-user/main.c | 4 +- bsd-user/mmap.c | 23 ++++++------ linux-user/elfload.c | 12 +++--- linux-user/flatload.c | 2 +- linux-user/hppa/cpu_loop.c | 31 ++++++++-------- linux-user/i386/cpu_loop.c | 4 +- linux-user/mmap.c | 45 +++++++++++----------- linux-user/ppc/signal.c | 4 +- linux-user/syscall.c | 72 +++++++++++++++++++----------------- target/arm/helper-a64.c | 4 +- target/hppa/op_helper.c | 2 +- target/i386/tcg/mem_helper.c | 2 +- target/s390x/mem_helper.c | 4 +- 20 files changed, 154 insertions(+), 137 deletions(-) diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index 4076adabd08..d2bcaab7413 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -356,13 +356,13 @@ static inline void *lock_user(int type, abi_ulong gue= st_addr, long len, int copy void *addr; addr =3D g_malloc(len); if (copy) - memcpy(addr, g2h(guest_addr), len); + memcpy(addr, g2h_untagged(guest_addr), len); else memset(addr, 0, len); return addr; } #else - return g2h(guest_addr); + return g2h_untagged(guest_addr); #endif } =20 @@ -376,10 +376,10 @@ static inline void unlock_user(void *host_ptr, abi_ul= ong guest_addr, #ifdef DEBUG_REMAP if (!host_ptr) return; - if (host_ptr =3D=3D g2h(guest_addr)) + if (host_ptr =3D=3D g2h_untagged(guest_addr)) return; if (len > 0) - memcpy(g2h(guest_addr), host_ptr, len); + memcpy(g2h_untagged(guest_addr), host_ptr, len); g_free(host_ptr); #endif } diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index d9dc1de414a..c54069e3cd0 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -77,7 +77,15 @@ static inline abi_ptr cpu_untagged_addr(CPUState *cs, ab= i_ptr x) #endif =20 /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ -#define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) +static inline void *g2h_untagged(abi_ptr x) +{ + return (void *)((uintptr_t)(x) + guest_base); +} + +static inline void *g2h(CPUState *cs, abi_ptr x) +{ + return g2h_untagged(cpu_untagged_addr(cs, x)); +} =20 static inline bool guest_addr_valid(abi_ulong x) { @@ -448,7 +456,7 @@ static inline int cpu_ldsw_code(CPUArchState *env, abi_= ptr addr) static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, MMUAccessType access_type, int mmu_i= dx) { - return g2h(addr); + return g2h(env_cpu(env), addr); } #else void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f933c74c446..d30c7a84f6a 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -616,7 +616,7 @@ static inline tb_page_addr_t get_page_addr_code_hostp(C= PUArchState *env, void **hostp) { if (hostp) { - *hostp =3D g2h(addr); + *hostp =3D g2h_untagged(addr); } return addr; } diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 9251337daf2..9fbc5edc4bd 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -652,7 +652,7 @@ static inline void *lock_user(int type, abi_ulong guest= _addr, long len, int copy return addr; } #else - return g2h(guest_addr); + return g2h_untagged(guest_addr); #endif } =20 @@ -666,10 +666,10 @@ static inline void unlock_user(void *host_ptr, abi_ul= ong guest_addr, #ifdef DEBUG_REMAP if (!host_ptr) return; - if (host_ptr =3D=3D g2h(guest_addr)) + if (host_ptr =3D=3D g2h_untagged(guest_addr)) return; if (len > 0) - memcpy(g2h(guest_addr), host_ptr, len); + memcpy(g2h_untagged(guest_addr), host_ptr, len); g_free(host_ptr); #endif } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bba9c8e0b3e..2c34adccce5 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1762,7 +1762,7 @@ static inline void tb_page_add(PageDesc *p, Translati= onBlock *tb, prot |=3D p2->flags; p2->flags &=3D ~PAGE_WRITE; } - mprotect(g2h(page_addr), qemu_host_page_size, + mprotect(g2h_untagged(page_addr), qemu_host_page_size, (prot & PAGE_BITS) & ~PAGE_WRITE); if (DEBUG_TB_INVALIDATE_GATE) { printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_= addr); @@ -2912,7 +2912,7 @@ int page_unprotect(target_ulong address, uintptr_t pc) } #endif } - mprotect((void *)g2h(host_start), qemu_host_page_size, + mprotect((void *)g2h_untagged(host_start), qemu_host_page_size, prot & PAGE_BITS); } mmap_unlock(); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 0b6f56ca407..fa1847b2a61 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -234,7 +234,7 @@ int probe_access_flags(CPUArchState *env, target_ulong = addr, int flags; =20 flags =3D probe_access_internal(env, addr, 0, access_type, nonfault, r= a); - *phost =3D flags ? NULL : g2h(addr); + *phost =3D flags ? NULL : g2h(env_cpu(env), addr); return flags; } =20 @@ -247,7 +247,7 @@ void *probe_access(CPUArchState *env, target_ulong addr= , int size, flags =3D probe_access_internal(env, addr, size, access_type, false, r= a); g_assert(flags =3D=3D 0); =20 - return size ? g2h(addr) : NULL; + return size ? g2h(env_cpu(env), addr) : NULL; } =20 #if defined(__i386__) @@ -842,7 +842,7 @@ uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo =3D trace_mem_get_info(MO_UB, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldub_p(g2h(ptr)); + ret =3D ldub_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -853,7 +853,7 @@ int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo =3D trace_mem_get_info(MO_SB, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldsb_p(g2h(ptr)); + ret =3D ldsb_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -864,7 +864,7 @@ uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr pt= r) uint16_t meminfo =3D trace_mem_get_info(MO_BEUW, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D lduw_be_p(g2h(ptr)); + ret =3D lduw_be_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -875,7 +875,7 @@ int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo =3D trace_mem_get_info(MO_BESW, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldsw_be_p(g2h(ptr)); + ret =3D ldsw_be_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -886,7 +886,7 @@ uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo =3D trace_mem_get_info(MO_BEUL, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldl_be_p(g2h(ptr)); + ret =3D ldl_be_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -897,7 +897,7 @@ uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo =3D trace_mem_get_info(MO_BEQ, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldq_be_p(g2h(ptr)); + ret =3D ldq_be_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -908,7 +908,7 @@ uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr pt= r) uint16_t meminfo =3D trace_mem_get_info(MO_LEUW, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D lduw_le_p(g2h(ptr)); + ret =3D lduw_le_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -919,7 +919,7 @@ int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo =3D trace_mem_get_info(MO_LESW, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldsw_le_p(g2h(ptr)); + ret =3D ldsw_le_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -930,7 +930,7 @@ uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo =3D trace_mem_get_info(MO_LEUL, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldl_le_p(g2h(ptr)); + ret =3D ldl_le_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -941,7 +941,7 @@ uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo =3D trace_mem_get_info(MO_LEQ, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldq_le_p(g2h(ptr)); + ret =3D ldq_le_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -1051,7 +1051,7 @@ void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uin= t32_t val) uint16_t meminfo =3D trace_mem_get_info(MO_UB, MMU_USER_IDX, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - stb_p(g2h(ptr), val); + stb_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } =20 @@ -1060,7 +1060,7 @@ void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) uint16_t meminfo =3D trace_mem_get_info(MO_BEUW, MMU_USER_IDX, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - stw_be_p(g2h(ptr), val); + stw_be_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } =20 @@ -1069,7 +1069,7 @@ void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) uint16_t meminfo =3D trace_mem_get_info(MO_BEUL, MMU_USER_IDX, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - stl_be_p(g2h(ptr), val); + stl_be_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } =20 @@ -1078,7 +1078,7 @@ void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, = uint64_t val) uint16_t meminfo =3D trace_mem_get_info(MO_BEQ, MMU_USER_IDX, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - stq_be_p(g2h(ptr), val); + stq_be_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } =20 @@ -1087,7 +1087,7 @@ void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) uint16_t meminfo =3D trace_mem_get_info(MO_LEUW, MMU_USER_IDX, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - stw_le_p(g2h(ptr), val); + stw_le_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } =20 @@ -1096,7 +1096,7 @@ void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) uint16_t meminfo =3D trace_mem_get_info(MO_LEUL, MMU_USER_IDX, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - stl_le_p(g2h(ptr), val); + stl_le_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } =20 @@ -1105,7 +1105,7 @@ void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, = uint64_t val) uint16_t meminfo =3D trace_mem_get_info(MO_LEQ, MMU_USER_IDX, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - stq_le_p(g2h(ptr), val); + stq_le_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } =20 @@ -1170,7 +1170,7 @@ uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr) uint32_t ret; =20 set_helper_retaddr(1); - ret =3D ldub_p(g2h(ptr)); + ret =3D ldub_p(g2h_untagged(ptr)); clear_helper_retaddr(); return ret; } @@ -1180,7 +1180,7 @@ uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr ptr) uint32_t ret; =20 set_helper_retaddr(1); - ret =3D lduw_p(g2h(ptr)); + ret =3D lduw_p(g2h_untagged(ptr)); clear_helper_retaddr(); return ret; } @@ -1190,7 +1190,7 @@ uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr ptr) uint32_t ret; =20 set_helper_retaddr(1); - ret =3D ldl_p(g2h(ptr)); + ret =3D ldl_p(g2h_untagged(ptr)); clear_helper_retaddr(); return ret; } @@ -1200,7 +1200,7 @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr) uint64_t ret; =20 set_helper_retaddr(1); - ret =3D ldq_p(g2h(ptr)); + ret =3D ldq_p(g2h_untagged(ptr)); clear_helper_retaddr(); return ret; } @@ -1213,7 +1213,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, if (unlikely(addr & (size - 1))) { cpu_loop_exit_atomic(env_cpu(env), retaddr); } - void *ret =3D g2h(addr); + void *ret =3D g2h(env_cpu(env), addr); set_helper_retaddr(retaddr); return ret; } diff --git a/bsd-user/elfload.c b/bsd-user/elfload.c index 32378af7b2e..5f4d824d78f 100644 --- a/bsd-user/elfload.c +++ b/bsd-user/elfload.c @@ -737,7 +737,7 @@ static void padzero(abi_ulong elf_bss, abi_ulong last_b= ss) end_addr1 =3D REAL_HOST_PAGE_ALIGN(elf_bss); end_addr =3D HOST_PAGE_ALIGN(elf_bss); if (end_addr1 < end_addr) { - mmap((void *)g2h(end_addr1), end_addr - end_addr1, + mmap((void *)g2h_untagged(end_addr1), end_addr - end_addr1, PROT_READ|PROT_WRITE|PROT_EXEC, MAP_FIXED|MAP_PRIVATE|MAP_ANON, -1, 0); } diff --git a/bsd-user/main.c b/bsd-user/main.c index 385d35886a0..798aba512c1 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -1055,7 +1055,7 @@ int main(int argc, char **argv) env->idt.base =3D target_mmap(0, sizeof(uint64_t) * (env->idt.limit + = 1), PROT_READ|PROT_WRITE, MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); - idt_table =3D g2h(env->idt.base); + idt_table =3D g2h_untagged(env->idt.base); set_idt(0, 0); set_idt(1, 0); set_idt(2, 0); @@ -1085,7 +1085,7 @@ int main(int argc, char **argv) PROT_READ|PROT_WRITE, MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); env->gdt.limit =3D sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; - gdt_table =3D g2h(env->gdt.base); + gdt_table =3D g2h_untagged(env->gdt.base); #ifdef TARGET_ABI32 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | diff --git a/bsd-user/mmap.c b/bsd-user/mmap.c index 17f4cd80aa1..01ec8080038 100644 --- a/bsd-user/mmap.c +++ b/bsd-user/mmap.c @@ -102,7 +102,8 @@ int target_mprotect(abi_ulong start, abi_ulong len, int= prot) } end =3D host_end; } - ret =3D mprotect(g2h(host_start), qemu_host_page_size, prot1 & PAG= E_BITS); + ret =3D mprotect(g2h_untagged(host_start), + qemu_host_page_size, prot1 & PAGE_BITS); if (ret !=3D 0) goto error; host_start +=3D qemu_host_page_size; @@ -112,8 +113,8 @@ int target_mprotect(abi_ulong start, abi_ulong len, int= prot) for(addr =3D end; addr < host_end; addr +=3D TARGET_PAGE_SIZE) { prot1 |=3D page_get_flags(addr); } - ret =3D mprotect(g2h(host_end - qemu_host_page_size), qemu_host_pa= ge_size, - prot1 & PAGE_BITS); + ret =3D mprotect(g2h_untagged(host_end - qemu_host_page_size), + qemu_host_page_size, prot1 & PAGE_BITS); if (ret !=3D 0) goto error; host_end -=3D qemu_host_page_size; @@ -121,7 +122,7 @@ int target_mprotect(abi_ulong start, abi_ulong len, int= prot) =20 /* handle the pages in the middle */ if (host_start < host_end) { - ret =3D mprotect(g2h(host_start), host_end - host_start, prot); + ret =3D mprotect(g2h_untagged(host_start), host_end - host_start, = prot); if (ret !=3D 0) goto error; } @@ -143,7 +144,7 @@ static int mmap_frag(abi_ulong real_start, int prot1, prot_new; =20 real_end =3D real_start + qemu_host_page_size; - host_start =3D g2h(real_start); + host_start =3D g2h_untagged(real_start); =20 /* get the protection of the target pages outside the mapping */ prot1 =3D 0; @@ -175,7 +176,7 @@ static int mmap_frag(abi_ulong real_start, mprotect(host_start, qemu_host_page_size, prot1 | PROT_WRITE); =20 /* read the corresponding file data */ - pread(fd, g2h(start), end - start, offset); + pread(fd, g2h_untagged(start), end - start, offset); =20 /* put final protection */ if (prot_new !=3D (prot1 | PROT_WRITE)) @@ -300,7 +301,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, in= t prot, /* Note: we prefer to control the mapping address. It is especially important if qemu_host_page_size > qemu_real_host_page_size */ - p =3D mmap(g2h(mmap_start), + p =3D mmap(g2h_untagged(mmap_start), host_len, prot, flags | MAP_FIXED, fd, host_offset); if (p =3D=3D MAP_FAILED) goto fail; @@ -344,7 +345,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, in= t prot, -1, 0); if (retaddr =3D=3D -1) goto fail; - pread(fd, g2h(start), len, offset); + pread(fd, g2h_untagged(start), len, offset); if (!(prot & PROT_WRITE)) { ret =3D target_mprotect(start, len, prot); if (ret !=3D 0) { @@ -390,7 +391,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, in= t prot, offset1 =3D 0; else offset1 =3D offset + real_start - start; - p =3D mmap(g2h(real_start), real_end - real_start, + p =3D mmap(g2h_untagged(real_start), real_end - real_start, prot, flags, fd, offset1); if (p =3D=3D MAP_FAILED) goto fail; @@ -456,7 +457,7 @@ int target_munmap(abi_ulong start, abi_ulong len) ret =3D 0; /* unmap what we can */ if (real_start < real_end) { - ret =3D munmap(g2h(real_start), real_end - real_start); + ret =3D munmap(g2h_untagged(real_start), real_end - real_start); } =20 if (ret =3D=3D 0) @@ -479,5 +480,5 @@ int target_msync(abi_ulong start, abi_ulong len, int fl= ags) return 0; =20 start &=3D qemu_host_page_mask; - return msync(g2h(start), end - start, flags); + return msync(g2h_untagged(start), end - start, flags); } diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 7ec9249c256..902be3ff117 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -389,7 +389,7 @@ enum { =20 static bool init_guest_commpage(void) { - void *want =3D g2h(ARM_COMMPAGE & -qemu_host_page_size); + void *want =3D g2h_untagged(ARM_COMMPAGE & -qemu_host_page_size); void *addr =3D mmap(want, qemu_host_page_size, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE | MAP_FIXED, -1, 0); =20 @@ -402,7 +402,7 @@ static bool init_guest_commpage(void) } =20 /* Set kernel helper versions; rest of page is 0. */ - __put_user(5, (uint32_t *)g2h(0xffff0ffcu)); + __put_user(5, (uint32_t *)g2h_untagged(0xffff0ffcu)); =20 if (mprotect(addr, qemu_host_page_size, PROT_READ)) { perror("Protecting guest commpage"); @@ -1872,8 +1872,8 @@ static void zero_bss(abi_ulong elf_bss, abi_ulong las= t_bss, int prot) here is still actually needed. For now, continue with it, but merge it with the "normal" mmap that would allocate the bss. */ =20 - host_start =3D (uintptr_t) g2h(elf_bss); - host_end =3D (uintptr_t) g2h(last_bss); + host_start =3D (uintptr_t) g2h_untagged(elf_bss); + host_end =3D (uintptr_t) g2h_untagged(last_bss); host_map_start =3D REAL_HOST_PAGE_ALIGN(host_start); =20 if (host_map_start < host_end) { @@ -2171,7 +2171,7 @@ static void pgb_have_guest_base(const char *image_nam= e, abi_ulong guest_loaddr, } =20 /* Reserve the address space for the binary, or reserved_va. */ - test =3D g2h(guest_loaddr); + test =3D g2h_untagged(guest_loaddr); addr =3D mmap(test, guest_hiaddr - guest_loaddr, PROT_NONE, flags, -1,= 0); if (test !=3D addr) { pgb_fail_in_use(image_name); @@ -2393,7 +2393,7 @@ static void pgb_reserved_va(const char *image_name, a= bi_ulong guest_loaddr, =20 /* Reserve the memory on the host. */ assert(guest_base !=3D 0); - test =3D g2h(0); + test =3D g2h_untagged(0); addr =3D mmap(test, reserved_va, PROT_NONE, flags, -1, 0); if (addr =3D=3D MAP_FAILED || addr !=3D test) { error_report("Unable to reserve 0x%lx bytes of virtual address " diff --git a/linux-user/flatload.c b/linux-user/flatload.c index 14d2999d153..3e5594cf894 100644 --- a/linux-user/flatload.c +++ b/linux-user/flatload.c @@ -668,7 +668,7 @@ static int load_flat_file(struct linux_binprm * bprm, } =20 /* zero the BSS. */ - memset(g2h(datapos + data_len), 0, bss_len); + memset(g2h_untagged(datapos + data_len), 0, bss_len); =20 return 0; } diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index d7e1ec77220..944511bbe43 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -23,6 +23,7 @@ =20 static abi_ulong hppa_lws(CPUHPPAState *env) { + CPUState *cs =3D env_cpu(env); uint32_t which =3D env->gr[20]; abi_ulong addr =3D env->gr[26]; abi_ulong old =3D env->gr[25]; @@ -39,7 +40,7 @@ static abi_ulong hppa_lws(CPUHPPAState *env) } old =3D tswap32(old); new =3D tswap32(new); - ret =3D qatomic_cmpxchg((uint32_t *)g2h(addr), old, new); + ret =3D qatomic_cmpxchg((uint32_t *)g2h(cs, addr), old, new); ret =3D tswap32(ret); break; =20 @@ -58,38 +59,38 @@ static abi_ulong hppa_lws(CPUHPPAState *env) can be host-endian as well. */ switch (size) { case 0: - old =3D *(uint8_t *)g2h(old); - new =3D *(uint8_t *)g2h(new); - ret =3D qatomic_cmpxchg((uint8_t *)g2h(addr), old, new); + old =3D *(uint8_t *)g2h(cs, old); + new =3D *(uint8_t *)g2h(cs, new); + ret =3D qatomic_cmpxchg((uint8_t *)g2h(cs, addr), old, new); ret =3D ret !=3D old; break; case 1: - old =3D *(uint16_t *)g2h(old); - new =3D *(uint16_t *)g2h(new); - ret =3D qatomic_cmpxchg((uint16_t *)g2h(addr), old, new); + old =3D *(uint16_t *)g2h(cs, old); + new =3D *(uint16_t *)g2h(cs, new); + ret =3D qatomic_cmpxchg((uint16_t *)g2h(cs, addr), old, new); ret =3D ret !=3D old; break; case 2: - old =3D *(uint32_t *)g2h(old); - new =3D *(uint32_t *)g2h(new); - ret =3D qatomic_cmpxchg((uint32_t *)g2h(addr), old, new); + old =3D *(uint32_t *)g2h(cs, old); + new =3D *(uint32_t *)g2h(cs, new); + ret =3D qatomic_cmpxchg((uint32_t *)g2h(cs, addr), old, new); ret =3D ret !=3D old; break; case 3: { uint64_t o64, n64, r64; - o64 =3D *(uint64_t *)g2h(old); - n64 =3D *(uint64_t *)g2h(new); + o64 =3D *(uint64_t *)g2h(cs, old); + n64 =3D *(uint64_t *)g2h(cs, new); #ifdef CONFIG_ATOMIC64 - r64 =3D qatomic_cmpxchg__nocheck((uint64_t *)g2h(addr), + r64 =3D qatomic_cmpxchg__nocheck((uint64_t *)g2h(cs, addr), o64, n64); ret =3D r64 !=3D o64; #else start_exclusive(); - r64 =3D *(uint64_t *)g2h(addr); + r64 =3D *(uint64_t *)g2h(cs, addr); ret =3D 1; if (r64 =3D=3D o64) { - *(uint64_t *)g2h(addr) =3D n64; + *(uint64_t *)g2h(cs, addr) =3D n64; ret =3D 0; } end_exclusive(); diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index 70cde417e60..19c8a18cd30 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -379,7 +379,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) env->idt.base =3D target_mmap(0, sizeof(uint64_t) * (env->idt.limit + = 1), PROT_READ|PROT_WRITE, MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); - idt_table =3D g2h(env->idt.base); + idt_table =3D g2h_untagged(env->idt.base); set_idt(0, 0); set_idt(1, 0); set_idt(2, 0); @@ -409,7 +409,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) PROT_READ|PROT_WRITE, MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); env->gdt.limit =3D sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; - gdt_table =3D g2h(env->gdt.base); + gdt_table =3D g2h_untagged(env->gdt.base); #ifdef TARGET_ABI32 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | diff --git a/linux-user/mmap.c b/linux-user/mmap.c index c52b60482e1..6decfec68a9 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -141,7 +141,7 @@ int target_mprotect(abi_ulong start, abi_ulong len, int= target_prot) } end =3D host_end; } - ret =3D mprotect(g2h(host_start), qemu_host_page_size, + ret =3D mprotect(g2h_untagged(host_start), qemu_host_page_size, prot1 & PAGE_BITS); if (ret !=3D 0) { goto error; @@ -153,7 +153,7 @@ int target_mprotect(abi_ulong start, abi_ulong len, int= target_prot) for (addr =3D end; addr < host_end; addr +=3D TARGET_PAGE_SIZE) { prot1 |=3D page_get_flags(addr); } - ret =3D mprotect(g2h(host_end - qemu_host_page_size), + ret =3D mprotect(g2h_untagged(host_end - qemu_host_page_size), qemu_host_page_size, prot1 & PAGE_BITS); if (ret !=3D 0) { goto error; @@ -163,7 +163,8 @@ int target_mprotect(abi_ulong start, abi_ulong len, int= target_prot) =20 /* handle the pages in the middle */ if (host_start < host_end) { - ret =3D mprotect(g2h(host_start), host_end - host_start, host_prot= ); + ret =3D mprotect(g2h_untagged(host_start), + host_end - host_start, host_prot); if (ret !=3D 0) { goto error; } @@ -186,7 +187,7 @@ static int mmap_frag(abi_ulong real_start, int prot1, prot_new; =20 real_end =3D real_start + qemu_host_page_size; - host_start =3D g2h(real_start); + host_start =3D g2h_untagged(real_start); =20 /* get the protection of the target pages outside the mapping */ prot1 =3D 0; @@ -218,7 +219,7 @@ static int mmap_frag(abi_ulong real_start, mprotect(host_start, qemu_host_page_size, prot1 | PROT_WRITE); =20 /* read the corresponding file data */ - if (pread(fd, g2h(start), end - start, offset) =3D=3D -1) + if (pread(fd, g2h_untagged(start), end - start, offset) =3D=3D -1) return -1; =20 /* put final protection */ @@ -229,7 +230,7 @@ static int mmap_frag(abi_ulong real_start, mprotect(host_start, qemu_host_page_size, prot_new); } if (prot_new & PROT_WRITE) { - memset(g2h(start), 0, end - start); + memset(g2h_untagged(start), 0, end - start); } } return 0; @@ -338,7 +339,7 @@ abi_ulong mmap_find_vma(abi_ulong start, abi_ulong size= , abi_ulong align) * - mremap() with MREMAP_FIXED flag * - shmat() with SHM_REMAP flag */ - ptr =3D mmap(g2h(addr), size, PROT_NONE, + ptr =3D mmap(g2h_untagged(addr), size, PROT_NONE, MAP_ANONYMOUS|MAP_PRIVATE|MAP_NORESERVE, -1, 0); =20 /* ENOMEM, if host address space has no memory */ @@ -497,7 +498,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, in= t target_prot, /* Note: we prefer to control the mapping address. It is especially important if qemu_host_page_size > qemu_real_host_page_size */ - p =3D mmap(g2h(start), host_len, host_prot, + p =3D mmap(g2h_untagged(start), host_len, host_prot, flags | MAP_FIXED | MAP_ANONYMOUS, -1, 0); if (p =3D=3D MAP_FAILED) { goto fail; @@ -505,10 +506,10 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, = int target_prot, /* update start so that it points to the file position at 'offset'= */ host_start =3D (unsigned long)p; if (!(flags & MAP_ANONYMOUS)) { - p =3D mmap(g2h(start), len, host_prot, + p =3D mmap(g2h_untagged(start), len, host_prot, flags | MAP_FIXED, fd, host_offset); if (p =3D=3D MAP_FAILED) { - munmap(g2h(start), host_len); + munmap(g2h_untagged(start), host_len); goto fail; } host_start +=3D offset - host_offset; @@ -548,7 +549,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, in= t target_prot, -1, 0); if (retaddr =3D=3D -1) goto fail; - if (pread(fd, g2h(start), len, offset) =3D=3D -1) + if (pread(fd, g2h_untagged(start), len, offset) =3D=3D -1) goto fail; if (!(host_prot & PROT_WRITE)) { ret =3D target_mprotect(start, len, target_prot); @@ -592,7 +593,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, in= t target_prot, offset1 =3D 0; else offset1 =3D offset + real_start - start; - p =3D mmap(g2h(real_start), real_end - real_start, + p =3D mmap(g2h_untagged(real_start), real_end - real_start, host_prot, flags, fd, offset1); if (p =3D=3D MAP_FAILED) goto fail; @@ -652,7 +653,7 @@ static void mmap_reserve(abi_ulong start, abi_ulong siz= e) real_end -=3D qemu_host_page_size; } if (real_start !=3D real_end) { - mmap(g2h(real_start), real_end - real_start, PROT_NONE, + mmap(g2h_untagged(real_start), real_end - real_start, PROT_NONE, MAP_FIXED | MAP_ANONYMOUS | MAP_PRIVATE | MAP_NORESERVE, -1, 0); } @@ -707,7 +708,7 @@ int target_munmap(abi_ulong start, abi_ulong len) if (reserved_va) { mmap_reserve(real_start, real_end - real_start); } else { - ret =3D munmap(g2h(real_start), real_end - real_start); + ret =3D munmap(g2h_untagged(real_start), real_end - real_start= ); } } =20 @@ -738,8 +739,8 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong ol= d_size, mmap_lock(); =20 if (flags & MREMAP_FIXED) { - host_addr =3D mremap(g2h(old_addr), old_size, new_size, - flags, g2h(new_addr)); + host_addr =3D mremap(g2h_untagged(old_addr), old_size, new_size, + flags, g2h_untagged(new_addr)); =20 if (reserved_va && host_addr !=3D MAP_FAILED) { /* If new and old addresses overlap then the above mremap will @@ -755,8 +756,9 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong ol= d_size, errno =3D ENOMEM; host_addr =3D MAP_FAILED; } else { - host_addr =3D mremap(g2h(old_addr), old_size, new_size, - flags | MREMAP_FIXED, g2h(mmap_start)); + host_addr =3D mremap(g2h_untagged(old_addr), old_size, new_siz= e, + flags | MREMAP_FIXED, + g2h_untagged(mmap_start)); if (reserved_va) { mmap_reserve(old_addr, old_size); } @@ -772,14 +774,15 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong = old_size, } } if (prot =3D=3D 0) { - host_addr =3D mremap(g2h(old_addr), old_size, new_size, flags); + host_addr =3D mremap(g2h_untagged(old_addr), + old_size, new_size, flags); =20 if (host_addr !=3D MAP_FAILED) { /* Check if address fits target address space */ if (!guest_range_valid(h2g(host_addr), new_size)) { /* Revert mremap() changes */ - host_addr =3D mremap(g2h(old_addr), new_size, old_size, - flags); + host_addr =3D mremap(g2h_untagged(old_addr), + new_size, old_size, flags); errno =3D ENOMEM; host_addr =3D MAP_FAILED; } else if (reserved_va && old_size > new_size) { diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c index 20a02c197cb..b78613f7c86 100644 --- a/linux-user/ppc/signal.c +++ b/linux-user/ppc/signal.c @@ -365,7 +365,7 @@ static void restore_user_regs(CPUPPCState *env, uint64_t v_addr; /* 64-bit needs to recover the pointer to the vectors from the fra= me */ __get_user(v_addr, &frame->v_regs); - v_regs =3D g2h(v_addr); + v_regs =3D g2h(env_cpu(env), v_addr); #else v_regs =3D (ppc_avr_t *)frame->mc_vregs.altivec; #endif @@ -552,7 +552,7 @@ void setup_rt_frame(int sig, struct target_sigaction *k= a, if (get_ppc64_abi(image) < 2) { /* ELFv1 PPC64 function pointers are pointers to OPD entries. */ struct target_func_ptr *handler =3D - (struct target_func_ptr *)g2h(ka->_sa_handler); + (struct target_func_ptr *)g2h(env_cpu(env), ka->_sa_handler); env->nip =3D tswapl(handler->entry); env->gpr[2] =3D tswapl(handler->toc); } else { diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 0c2d660bc42..e7fd99f1acc 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -912,7 +912,7 @@ abi_long do_brk(abi_ulong new_brk) /* Heap contents are initialized to zero, as for anonymous * mapped pages. */ if (new_brk > target_brk) { - memset(g2h(target_brk), 0, new_brk - target_brk); + memset(g2h_untagged(target_brk), 0, new_brk - target_brk); } target_brk =3D new_brk; DEBUGF_BRK(TARGET_ABI_FMT_lx " (new_brk <=3D brk_page)\n", target_= brk); @@ -938,7 +938,7 @@ abi_long do_brk(abi_ulong new_brk) * come from the remaining part of the previous page: it may * contains garbage data due to a previous heap usage (grown * then shrunken). */ - memset(g2h(target_brk), 0, brk_page - target_brk); + memset(g2h_untagged(target_brk), 0, brk_page - target_brk); =20 target_brk =3D new_brk; brk_page =3D HOST_PAGE_ALIGN(target_brk); @@ -4622,7 +4622,7 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_en= v, mmap_lock(); =20 if (shmaddr) - host_raddr =3D shmat(shmid, (void *)g2h(shmaddr), shmflg); + host_raddr =3D shmat(shmid, (void *)g2h_untagged(shmaddr), shmflg); else { abi_ulong mmap_start; =20 @@ -4633,7 +4633,8 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_en= v, errno =3D ENOMEM; host_raddr =3D (void *)-1; } else - host_raddr =3D shmat(shmid, g2h(mmap_start), shmflg | SHM_REMA= P); + host_raddr =3D shmat(shmid, g2h_untagged(mmap_start), + shmflg | SHM_REMAP); } =20 if (host_raddr =3D=3D (void *)-1) { @@ -4674,7 +4675,7 @@ static inline abi_long do_shmdt(abi_ulong shmaddr) break; } } - rv =3D get_errno(shmdt(g2h(shmaddr))); + rv =3D get_errno(shmdt(g2h_untagged(shmaddr))); =20 mmap_unlock(); =20 @@ -6145,10 +6146,10 @@ static abi_long write_ldt(CPUX86State *env, MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); if (env->ldt.base =3D=3D -1) return -TARGET_ENOMEM; - memset(g2h(env->ldt.base), 0, + memset(g2h_untagged(env->ldt.base), 0, TARGET_LDT_ENTRIES * TARGET_LDT_ENTRY_SIZE); env->ldt.limit =3D 0xffff; - ldt_table =3D g2h(env->ldt.base); + ldt_table =3D g2h_untagged(env->ldt.base); } =20 /* NOTE: same code as Linux kernel */ @@ -6216,7 +6217,7 @@ static abi_long do_modify_ldt(CPUX86State *env, int f= unc, abi_ulong ptr, #if defined(TARGET_ABI32) abi_long do_set_thread_area(CPUX86State *env, abi_ulong ptr) { - uint64_t *gdt_table =3D g2h(env->gdt.base); + uint64_t *gdt_table =3D g2h_untagged(env->gdt.base); struct target_modify_ldt_ldt_s ldt_info; struct target_modify_ldt_ldt_s *target_ldt_info; int seg_32bit, contents, read_exec_only, limit_in_pages; @@ -6302,7 +6303,7 @@ install: static abi_long do_get_thread_area(CPUX86State *env, abi_ulong ptr) { struct target_modify_ldt_ldt_s *target_ldt_info; - uint64_t *gdt_table =3D g2h(env->gdt.base); + uint64_t *gdt_table =3D g2h_untagged(env->gdt.base); uint32_t base_addr, limit, flags; int seg_32bit, contents, read_exec_only, limit_in_pages, idx; int seg_not_present, useable, lm; @@ -7597,8 +7598,8 @@ static int do_safe_futex(int *uaddr, int op, int val, tricky. However they're probably useless because guest atomic operations won't work either. */ #if defined(TARGET_NR_futex) -static int do_futex(target_ulong uaddr, int op, int val, target_ulong time= out, - target_ulong uaddr2, int val3) +static int do_futex(CPUState *cpu, target_ulong uaddr, int op, int val, + target_ulong timeout, target_ulong uaddr2, int val3) { struct timespec ts, *pts; int base_op; @@ -7619,11 +7620,14 @@ static int do_futex(target_ulong uaddr, int op, int= val, target_ulong timeout, } else { pts =3D NULL; } - return do_safe_futex(g2h(uaddr), op, tswap32(val), pts, NULL, val3= ); + return do_safe_futex(g2h(cpu, uaddr), + op, tswap32(val), pts, NULL, val3); case FUTEX_WAKE: - return do_safe_futex(g2h(uaddr), op, val, NULL, NULL, 0); + return do_safe_futex(g2h(cpu, uaddr), + op, val, NULL, NULL, 0); case FUTEX_FD: - return do_safe_futex(g2h(uaddr), op, val, NULL, NULL, 0); + return do_safe_futex(g2h(cpu, uaddr), + op, val, NULL, NULL, 0); case FUTEX_REQUEUE: case FUTEX_CMP_REQUEUE: case FUTEX_WAKE_OP: @@ -7633,10 +7637,9 @@ static int do_futex(target_ulong uaddr, int op, int = val, target_ulong timeout, to satisfy the compiler. We do not need to tswap TIMEOUT since it's not compared to guest memory. */ pts =3D (struct timespec *)(uintptr_t) timeout; - return do_safe_futex(g2h(uaddr), op, val, pts, g2h(uaddr2), + return do_safe_futex(g2h(cpu, uaddr), op, val, pts, g2h(cpu, uaddr= 2), (base_op =3D=3D FUTEX_CMP_REQUEUE - ? tswap32(val3) - : val3)); + ? tswap32(val3) : val3)); default: return -TARGET_ENOSYS; } @@ -7644,7 +7647,8 @@ static int do_futex(target_ulong uaddr, int op, int v= al, target_ulong timeout, #endif =20 #if defined(TARGET_NR_futex_time64) -static int do_futex_time64(target_ulong uaddr, int op, int val, target_ulo= ng timeout, +static int do_futex_time64(CPUState *cpu, target_ulong uaddr, int op, + int val, target_ulong timeout, target_ulong uaddr2, int val3) { struct timespec ts, *pts; @@ -7668,11 +7672,12 @@ static int do_futex_time64(target_ulong uaddr, int = op, int val, target_ulong tim } else { pts =3D NULL; } - return do_safe_futex(g2h(uaddr), op, tswap32(val), pts, NULL, val3= ); + return do_safe_futex(g2h(cpu, uaddr), op, + tswap32(val), pts, NULL, val3); case FUTEX_WAKE: - return do_safe_futex(g2h(uaddr), op, val, NULL, NULL, 0); + return do_safe_futex(g2h(cpu, uaddr), op, val, NULL, NULL, 0); case FUTEX_FD: - return do_safe_futex(g2h(uaddr), op, val, NULL, NULL, 0); + return do_safe_futex(g2h(cpu, uaddr), op, val, NULL, NULL, 0); case FUTEX_REQUEUE: case FUTEX_CMP_REQUEUE: case FUTEX_WAKE_OP: @@ -7682,10 +7687,9 @@ static int do_futex_time64(target_ulong uaddr, int o= p, int val, target_ulong tim to satisfy the compiler. We do not need to tswap TIMEOUT since it's not compared to guest memory. */ pts =3D (struct timespec *)(uintptr_t) timeout; - return do_safe_futex(g2h(uaddr), op, val, pts, g2h(uaddr2), + return do_safe_futex(g2h(cpu, uaddr), op, val, pts, g2h(cpu, uaddr= 2), (base_op =3D=3D FUTEX_CMP_REQUEUE - ? tswap32(val3) - : val3)); + ? tswap32(val3) : val3)); default: return -TARGET_ENOSYS; } @@ -7860,7 +7864,7 @@ static int open_self_maps(void *cpu_env, int fd) const char *path; =20 max =3D h2g_valid(max - 1) ? - max : (uintptr_t) g2h(GUEST_ADDR_MAX) + 1; + max : (uintptr_t) g2h_untagged(GUEST_ADDR_MAX) + 1; =20 if (page_check_range(h2g(min), max - min, flags) =3D=3D -1) { continue; @@ -8277,8 +8281,8 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, =20 if (ts->child_tidptr) { put_user_u32(0, ts->child_tidptr); - do_sys_futex(g2h(ts->child_tidptr), FUTEX_WAKE, INT_MAX, - NULL, NULL, 0); + do_sys_futex(g2h(cpu, ts->child_tidptr), + FUTEX_WAKE, INT_MAX, NULL, NULL, 0); } thread_cpu =3D NULL; g_free(ts); @@ -8643,7 +8647,7 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, if (!arg5) { ret =3D mount(p, p2, p3, (unsigned long)arg4, NULL); } else { - ret =3D mount(p, p2, p3, (unsigned long)arg4, g2h(arg5)); + ret =3D mount(p, p2, p3, (unsigned long)arg4, g2h(cpu, arg= 5)); } ret =3D get_errno(ret); =20 @@ -9738,15 +9742,15 @@ static abi_long do_syscall1(void *cpu_env, int num,= abi_long arg1, /* ??? msync/mlock/munlock are broken for softmmu. */ #ifdef TARGET_NR_msync case TARGET_NR_msync: - return get_errno(msync(g2h(arg1), arg2, arg3)); + return get_errno(msync(g2h(cpu, arg1), arg2, arg3)); #endif #ifdef TARGET_NR_mlock case TARGET_NR_mlock: - return get_errno(mlock(g2h(arg1), arg2)); + return get_errno(mlock(g2h(cpu, arg1), arg2)); #endif #ifdef TARGET_NR_munlock case TARGET_NR_munlock: - return get_errno(munlock(g2h(arg1), arg2)); + return get_errno(munlock(g2h(cpu, arg1), arg2)); #endif #ifdef TARGET_NR_mlockall case TARGET_NR_mlockall: @@ -12237,7 +12241,7 @@ static abi_long do_syscall1(void *cpu_env, int num,= abi_long arg1, =20 #if defined(TARGET_NR_set_tid_address) && defined(__NR_set_tid_address) case TARGET_NR_set_tid_address: - return get_errno(set_tid_address((int *)g2h(arg1))); + return get_errno(set_tid_address((int *)g2h(cpu, arg1))); #endif =20 case TARGET_NR_tkill: @@ -12324,11 +12328,11 @@ static abi_long do_syscall1(void *cpu_env, int nu= m, abi_long arg1, #endif #ifdef TARGET_NR_futex case TARGET_NR_futex: - return do_futex(arg1, arg2, arg3, arg4, arg5, arg6); + return do_futex(cpu, arg1, arg2, arg3, arg4, arg5, arg6); #endif #ifdef TARGET_NR_futex_time64 case TARGET_NR_futex_time64: - return do_futex_time64(arg1, arg2, arg3, arg4, arg5, arg6); + return do_futex_time64(cpu, arg1, arg2, arg3, arg4, arg5, arg6); #endif #if defined(TARGET_NR_inotify_init) && defined(__NR_inotify_init) case TARGET_NR_inotify_init: diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index ae611d73c2c..7f56c78fa6c 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -542,7 +542,7 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, = uint64_t addr, =20 #ifdef CONFIG_USER_ONLY /* ??? Enforce alignment. */ - uint64_t *haddr =3D g2h(addr); + uint64_t *haddr =3D g2h(env_cpu(env), addr); =20 set_helper_retaddr(ra); o0 =3D ldq_le_p(haddr + 0); @@ -612,7 +612,7 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, = uint64_t addr, =20 #ifdef CONFIG_USER_ONLY /* ??? Enforce alignment. */ - uint64_t *haddr =3D g2h(addr); + uint64_t *haddr =3D g2h(env_cpu(env), addr); =20 set_helper_retaddr(ra); o1 =3D ldq_be_p(haddr + 0); diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 7ae31e1a154..96d9391c399 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -63,7 +63,7 @@ static void atomic_store_3(CPUHPPAState *env, target_ulon= g addr, uint32_t val, #ifdef CONFIG_USER_ONLY uint32_t old, new, cmp; =20 - uint32_t *haddr =3D g2h(addr - 1); + uint32_t *haddr =3D g2h(env_cpu(env), addr - 1); old =3D *haddr; while (1) { new =3D (old & ~mask) | (val & mask); diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index e5cd2de1bff..591f512bffe 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -66,7 +66,7 @@ void helper_cmpxchg8b(CPUX86State *env, target_ulong a0) =20 #ifdef CONFIG_USER_ONLY { - uint64_t *haddr =3D g2h(a0); + uint64_t *haddr =3D g2h(env_cpu(env), a0); cmpv =3D cpu_to_le64(cmpv); newv =3D cpu_to_le64(newv); oldv =3D qatomic_cmpxchg__nocheck(haddr, cmpv, newv); diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 1901e9dfc7c..25cfede806a 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1780,7 +1780,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, =20 if (parallel) { #ifdef CONFIG_USER_ONLY - uint32_t *haddr =3D g2h(a1); + uint32_t *haddr =3D g2h(env_cpu(env), a1); ov =3D qatomic_cmpxchg__nocheck(haddr, cv, nv); #else TCGMemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mem_= idx); @@ -1804,7 +1804,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, if (parallel) { #ifdef CONFIG_ATOMIC64 # ifdef CONFIG_USER_ONLY - uint64_t *haddr =3D g2h(a1); + uint64_t *haddr =3D g2h(env_cpu(env), a1); ov =3D qatomic_cmpxchg__nocheck(haddr, cv, nv); # else TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN, mem_i= dx); --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613492946423839.4627750812429; Tue, 16 Feb 2021 08:29:06 -0800 (PST) Received: from localhost ([::1]:60682 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3Dk-0005Au-Be for importer@patchew.org; Tue, 16 Feb 2021 11:29:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40318) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32g-0007iC-IS for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:38 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:37319) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32F-0002On-8u for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:38 -0500 Received: by mail-wr1-x42e.google.com with SMTP id v15so13788529wrx.4 for ; Tue, 16 Feb 2021 08:17:10 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=JjY315MInI4vG0RSnDggioNC4B0M+dGQT3MUTReQ2S0=; b=X2ZEJMcYZoE1ZEyiNWQiUTG/08jLqDUnYIpMVbilxqCPLhlQ8m6YVwrVEveV16Yvb7 X+B0VRqs+hoifrwbYSz5ZfxhPlT3ucUqc5C2L1VU+0rA3KWg47bD+IzveJQBHXQrtRwI 2Jq2yPjM560u+n9O+xmnOSpHsK1yrwYLiJ902HclMz3KhtZDm6iEcrpfgFZwBZOt0mjU lI3uKOrFJSVeqhjIZYCJtfM52VcgjA/OaTtXKzoe/2461e8s83a+tI6IvksFwWDhGLpi lKCqBDr5/E5xjg/8MgoNlV+cy/UsGwO/EWTv/uQT5z1VwqXFE7KzDiHtgJC9333LUHqV VHwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JjY315MInI4vG0RSnDggioNC4B0M+dGQT3MUTReQ2S0=; b=DiNHMYUgqjyCBmGzt3omwJGsA1UZvenU1UNvwOK77fA4tzryMC+B1SBXMlb1D6Rxzd OfdNKMmssYwOKD9dZ0TBLQkA+HvBljnqRjeWPIIHkDdIhW4wXFFen0bAo+Gi2D4HfxaB u72jooPwAlzhqaInSCzKEzv20pzmzcDCOjDhGMLWEy5tqWTmvIgVdXMMMtj2nf5eQJk2 2DA47X8WdFDLD2AxfDe9Hnkb8QiSQ4ChQZTM1ngw/y/LJIKmL6dy3g8UhtFs72dKS0CD FV3L06foXX+7Rx4DCo60Q7UrvpL033+Nm3lRva/V9Swl3Pr/Nium/0/bsK4bTNfBBX+Q 6W8Q== X-Gm-Message-State: AOAM5331Bq5qWmQtCmTCaFBh1lD0Waa3YbEckiM3Oqw1Pj2qZ7uY8AD4 rB2gLag7uyy/gRka53g9DawkygP7JWWXFg== X-Google-Smtp-Source: ABdhPJwm/8Se3dvnTJdAhJmxgZ8GpETQs+EDSZ+fAbcKwe0w2vNL57hr7LMPzu3fNUMItBLff9h4zw== X-Received: by 2002:a5d:558b:: with SMTP id i11mr24898135wrv.125.1613492229707; Tue, 16 Feb 2021 08:17:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/40] linux-user: Explicitly untag memory management syscalls Date: Tue, 16 Feb 2021 16:16:31 +0000 Message-Id: <20210216161658.29881-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We define target_mmap et al as untagged, so that they can be used from the binary loaders. Explicitly call cpu_untagged_addr for munmap, mprotect, mremap syscall entry points. Add a few comments for the syscalls that are exempted by the kernel's tagged-address-abi.rst. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/syscall.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index e7fd99f1acc..d5badd753e3 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -894,6 +894,8 @@ abi_long do_brk(abi_ulong new_brk) abi_long mapped_addr; abi_ulong new_alloc_size; =20 + /* brk pointers are always untagged */ + DEBUGF_BRK("do_brk(" TARGET_ABI_FMT_lx ") -> ", new_brk); =20 if (!new_brk) { @@ -4599,6 +4601,8 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_en= v, int i,ret; abi_ulong shmlba; =20 + /* shmat pointers are always untagged */ + /* find out the length of the shared memory segment */ ret =3D get_errno(shmctl(shmid, IPC_STAT, &shm_info)); if (is_error(ret)) { @@ -4666,6 +4670,8 @@ static inline abi_long do_shmdt(abi_ulong shmaddr) int i; abi_long rv; =20 + /* shmdt pointers are always untagged */ + mmap_lock(); =20 for (i =3D 0; i < N_SHM_REGIONS; ++i) { @@ -9703,6 +9709,7 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, v5, v6)); } #else + /* mmap pointers are always untagged */ ret =3D get_errno(target_mmap(arg1, arg2, arg3, target_to_host_bitmask(arg4, mmap_flag= s_tbl), arg5, @@ -9721,8 +9728,10 @@ static abi_long do_syscall1(void *cpu_env, int num, = abi_long arg1, return get_errno(ret); #endif case TARGET_NR_munmap: + arg1 =3D cpu_untagged_addr(cpu, arg1); return get_errno(target_munmap(arg1, arg2)); case TARGET_NR_mprotect: + arg1 =3D cpu_untagged_addr(cpu, arg1); { TaskState *ts =3D cpu->opaque; /* Special hack to detect libc making the stack executable. */ @@ -9737,6 +9746,8 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, return get_errno(target_mprotect(arg1, arg2, arg3)); #ifdef TARGET_NR_mremap case TARGET_NR_mremap: + arg1 =3D cpu_untagged_addr(cpu, arg1); + /* mremap new_addr (arg5) is always untagged */ return get_errno(target_mremap(arg1, arg2, arg3, arg4, arg5)); #endif /* ??? msync/mlock/munlock are broken for softmmu. */ --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613492843; cv=none; d=zohomail.com; s=zohoarc; b=OmY8kanAoKCgKc2V6mzCIOWhHl99dVFcw3LXisXD9EHQQkwkVMmwcjml4qNtF08P+GQiQ7K6pmc8vfSeyR8CUivwaOPR9h0dRoNwNYEWLckacXb04E77tlU3D7/qDUCeVti1RYZWfcx3gE0Dzhlj1+6wresFaJWVxtDwAwoZ/Is= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613492843; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6C9LXCdHBjO1xQ9UNLXYukrE+VL/m5JY39MhpMQnyLY=; b=L3IPY4cXIDeum+mLr7oECqW9q1AS0XcGikOoGep2g8ejEVjhFDK2uCZ2bzZ8Bb7j3vd8lKhgMDerK2tQzwxHra8wSZ/ZnwyObYtT3jg7wJEuUbMBZYIIANBH2t6BWUs2FWuNLN6yVcimMXY4fMEeV25q/Qwb9IHEtvVyl+/tdwE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613492843059675.6771852423046; Tue, 16 Feb 2021 08:27:23 -0800 (PST) Received: from localhost ([::1]:56830 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3C4-0003ZG-D7 for importer@patchew.org; Tue, 16 Feb 2021 11:27:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40426) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32m-0007x2-Es for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:44 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:38952) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32G-0002PJ-1m for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:44 -0500 Received: by mail-wr1-x42a.google.com with SMTP id v1so13778811wrd.6 for ; Tue, 16 Feb 2021 08:17:11 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6C9LXCdHBjO1xQ9UNLXYukrE+VL/m5JY39MhpMQnyLY=; b=elEMITV2ni7ifMHiY099V9zlN5tNnng1zBQiz+CDdI/Jn8mVpxYV7BdMSh4BEoW/hO Zstl/pdFVpTbilbUEnxEjRsCz/FuFHTYNPsNUgQq+ukTyPiq5iKSG/Vit7J4/7vhlWGN 1sZNCWn6CTI3occkzc7NiCCV6FwIR2biM6nmdEJxE+nGwRwNQE2AROedVCAp4KVD8NOk LDFDWISZdRk2cpa7LAs1P4W3orYWiaep7VB3/oszlQJVFJY4h7jW6Y7i10XIDqeiiuJ5 Uzxh4PT07W2wNkx2F2sV5Lpc2/dAxoY3lxYfQvTR9CHzXUqraltRvV1i3rjbC7NPB7Ut yjfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6C9LXCdHBjO1xQ9UNLXYukrE+VL/m5JY39MhpMQnyLY=; b=m+9MHyFuLdgzPS9X7V9hoMENO6yw0jxf4mR0h0MJ5sfQCl6yUxRq77nDV0s4/OlBfT lvBsJpBGbydqOdt4MYPzCh2YLYDhJwEkKqIir/Kp3GE3uEH4lj2D7UyNUaq7E7S9A3Ry HPq4abFE++BGzXO9xz9x24TsfSsse9yWL3QzvA6BXsWTo8Ve9UfMpG/IeBbKG1BS0BeP xw8T+yONjp8Qy3EwovOvJ/sFF9CiYCutn87Tf+au3ELWsaKZYBw9OYivIhre/tfUshGk IDxiAYz+Oe7Ea0pvjY9gUIL4Lpypg9tawBCbbnqfNk80Iiexdpqnpo4PBQaUMa2UeGNf MU/A== X-Gm-Message-State: AOAM533tVxUs+REXOag4r5yNkBQQ33OFG9eQ79QpHv+a1VcJQaYQwE05 47aukdEsvcsuOJEYv/EMauVpfv+meB4T3g== X-Google-Smtp-Source: ABdhPJzlG7Dzhv8MkteAwCeFr3dm5LWwjXQzlwdysCAIAD07qE+5dUJ1HMGpWKVO+XNgWK0iPyOuMQ== X-Received: by 2002:a5d:40c3:: with SMTP id b3mr24895380wrq.102.1613492230290; Tue, 16 Feb 2021 08:17:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/40] linux-user: Use guest_range_valid in access_ok Date: Tue, 16 Feb 2021 16:16:32 +0000 Message-Id: <20210216161658.29881-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We're currently open-coding the range check in access_ok; use guest_range_valid when size !=3D 0. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/qemu.h | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 9fbc5edc4bd..ba122a79039 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -493,12 +493,9 @@ extern unsigned long guest_stack_size; =20 static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { - if (!guest_addr_valid(addr)) { - return false; - } - if (size !=3D 0 && - (addr + size - 1 < addr || - !guest_addr_valid(addr + size - 1))) { + if (size =3D=3D 0 + ? !guest_addr_valid(addr) + : !guest_range_valid(addr, size)) { return false; } return page_check_range((target_ulong)addr, size, type) =3D=3D 0; --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613493286484630.0362279430688; Tue, 16 Feb 2021 08:34:46 -0800 (PST) Received: from localhost ([::1]:41734 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3JE-00016D-9S for importer@patchew.org; Tue, 16 Feb 2021 11:34:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40500) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32q-00088N-QJ for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:48 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:35554) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32G-0002Pq-OS for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:48 -0500 Received: by mail-wm1-x335.google.com with SMTP id n10so15029508wmq.0 for ; Tue, 16 Feb 2021 08:17:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=QZdYzSFH8t+vQqqw69mWNqxMXUzyV4/x8cSvRzxUxII=; b=csE0LE6grciJfWA/vPEyAKDEj0s4ljsrev+4RPIt+C3fHlckPEHFBFYbwKbuFama91 n89Vj6E/GC5YkTPOGj+huTgO2SWzPsF33V+xJlLh2LA18A2/AAsLX2nef5P8BOFeS1Z9 I3+tzsaWHTP2P7mRjKD3bTOqVlONTB6XRYTFRLyMqnmDztXCZcQXrMbaXDvmp5hcI7zM I7Ql6Vq7J2Fqog6GR96btoLL21AfaX6Mh+d5hsdBjZgtrAQX3FiQ+1N16JoSPCxXmA+R mQI5VBLf77smswSbHQ9DhYWIqGX0Orhh80NuOSwQG0tpnpWhp8WXAXTUwLxhOXus8tf1 t9zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QZdYzSFH8t+vQqqw69mWNqxMXUzyV4/x8cSvRzxUxII=; b=hPaYx8EtRBUnUYB4n4F8BYyQVRQUbkVGgACSrgi6t1EGFIH0VRTCM1PxrlWoDhbP84 HMwiPMjqPqZOVNJarMn7PfkuUHADGzAC4zK/Xz5SxHUU3X9Etl7nN0kRSbKObnpo+0uL kreCDM4M7TLD0Cu58D3zBpEQqW5YhFJLIoQg1G18cSoWCPA8joYjk5XK54dXzG+TW6bH 4WsXotJvojF8i7bjia3VNYCDkm20/pKIzLLljFXrmSjwGhC2SDfubzdY4c4WObZ1PtPk uFSIAqaGt1pE60GSrZ+RJuyHyG5DQujQwqOsbjQD99e+9BX/A2sY8JUnSXN1WmO28kEZ 5kUg== X-Gm-Message-State: AOAM533vu1phDHo4vgnkzlQ3llWNgTyBvtCORVZH8pSyH5LAyGQNdzkO JtnNY9tBpvISKaGSd12wwtElUsig5DMd3g== X-Google-Smtp-Source: ABdhPJzwerBzWskBHsNoeCXZC2YzKrfDSVB/Wons/R1a4JEis7f7ryctV/Q4hdYLW7QxavNSIm8xJw== X-Received: by 2002:a7b:c4d7:: with SMTP id g23mr1858667wmk.106.1613492231272; Tue, 16 Feb 2021 08:17:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/40] exec: Rename guest_{addr,range}_valid to *_untagged Date: Tue, 16 Feb 2021 16:16:33 +0000 Message-Id: <20210216161658.29881-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson The places that use these are better off using untagged addresses, so do not provide a tagged versions. Rename to make it clear about the address type. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu_ldst.h | 4 ++-- linux-user/qemu.h | 4 ++-- accel/tcg/user-exec.c | 3 ++- linux-user/mmap.c | 14 +++++++------- linux-user/syscall.c | 2 +- 5 files changed, 14 insertions(+), 13 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index c54069e3cd0..ce6ce826182 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -87,12 +87,12 @@ static inline void *g2h(CPUState *cs, abi_ptr x) return g2h_untagged(cpu_untagged_addr(cs, x)); } =20 -static inline bool guest_addr_valid(abi_ulong x) +static inline bool guest_addr_valid_untagged(abi_ulong x) { return x <=3D GUEST_ADDR_MAX; } =20 -static inline bool guest_range_valid(abi_ulong start, abi_ulong len) +static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong l= en) { return len - 1 <=3D GUEST_ADDR_MAX && start <=3D GUEST_ADDR_MAX - len = + 1; } diff --git a/linux-user/qemu.h b/linux-user/qemu.h index ba122a79039..b3ccffbf0fa 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -494,8 +494,8 @@ extern unsigned long guest_stack_size; static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { if (size =3D=3D 0 - ? !guest_addr_valid(addr) - : !guest_range_valid(addr, size)) { + ? !guest_addr_valid_untagged(addr) + : !guest_range_valid_untagged(addr, size)) { return false; } return page_check_range((target_ulong)addr, size, type) =3D=3D 0; diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index fa1847b2a61..0d8cc27b213 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -213,7 +213,8 @@ static int probe_access_internal(CPUArchState *env, tar= get_ulong addr, g_assert_not_reached(); } =20 - if (!guest_addr_valid(addr) || page_check_range(addr, 1, flags) < 0) { + if (!guest_addr_valid_untagged(addr) || + page_check_range(addr, 1, flags) < 0) { if (nonfault) { return TLB_INVALID_MASK; } else { diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 6decfec68a9..9fe0c634e24 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -119,7 +119,7 @@ int target_mprotect(abi_ulong start, abi_ulong len, int= target_prot) } len =3D TARGET_PAGE_ALIGN(len); end =3D start + len; - if (!guest_range_valid(start, len)) { + if (!guest_range_valid_untagged(start, len)) { return -TARGET_ENOMEM; } if (len =3D=3D 0) { @@ -528,7 +528,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, in= t target_prot, * It can fail only on 64-bit host with 32-bit target. * On any other target/host host mmap() handles this error correct= ly. */ - if (end < start || !guest_range_valid(start, len)) { + if (end < start || !guest_range_valid_untagged(start, len)) { errno =3D ENOMEM; goto fail; } @@ -669,7 +669,7 @@ int target_munmap(abi_ulong start, abi_ulong len) if (start & ~TARGET_PAGE_MASK) return -TARGET_EINVAL; len =3D TARGET_PAGE_ALIGN(len); - if (len =3D=3D 0 || !guest_range_valid(start, len)) { + if (len =3D=3D 0 || !guest_range_valid_untagged(start, len)) { return -TARGET_EINVAL; } =20 @@ -727,11 +727,11 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong = old_size, int prot; void *host_addr; =20 - if (!guest_range_valid(old_addr, old_size) || + if (!guest_range_valid_untagged(old_addr, old_size) || ((flags & MREMAP_FIXED) && - !guest_range_valid(new_addr, new_size)) || + !guest_range_valid_untagged(new_addr, new_size)) || ((flags & MREMAP_MAYMOVE) =3D=3D 0 && - !guest_range_valid(old_addr, new_size))) { + !guest_range_valid_untagged(old_addr, new_size))) { errno =3D ENOMEM; return -1; } @@ -779,7 +779,7 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong ol= d_size, =20 if (host_addr !=3D MAP_FAILED) { /* Check if address fits target address space */ - if (!guest_range_valid(h2g(host_addr), new_size)) { + if (!guest_range_valid_untagged(h2g(host_addr), new_size))= { /* Revert mremap() changes */ host_addr =3D mremap(g2h_untagged(old_addr), new_size, old_size, flags); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index d5badd753e3..53529e4004c 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -4619,7 +4619,7 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_en= v, return -TARGET_EINVAL; } } - if (!guest_range_valid(shmaddr, shm_info.shm_segsz)) { + if (!guest_range_valid_untagged(shmaddr, shm_info.shm_segsz)) { return -TARGET_EINVAL; } =20 --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613493261938786.2941782201532; Tue, 16 Feb 2021 08:34:21 -0800 (PST) Received: from localhost ([::1]:41014 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3Ip-0000iF-K2 for importer@patchew.org; Tue, 16 Feb 2021 11:34:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40518) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32s-0008Be-63 for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:50 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:37918) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32H-0002QN-7r for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:49 -0500 Received: by mail-wr1-x42a.google.com with SMTP id b3so13779447wrj.5 for ; Tue, 16 Feb 2021 08:17:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oOzT7sOzTR42HbW+vtiKP9qod26e6MefuWrn5uRr7O8=; b=PqA3VTobA2mXBwuPZmASvILebCTcpUuLAmR1HYBvFwDgg/J90eWJ3a76iNO4u8UUw3 VBGiDRQ9Dmcyp+A3/pVM+3FYF6KI1mSHNslo1mwDKgRO+WDLsIYk69KYnAwhvd2LhYQa 5zg+NiOPUp+hciDtQPCEu7RZO43lZ0RT4ooHFLxhpGkgKEc+uKSozB2+hS2vS7+vrMmC AY6JpRGQcAmlMWWshG5ffBMyC4OUjF1zdWzNywRIEoQ9uE/2VkeDUCvn8pV3RaI532ry 3MoCBBmOvooR5xIkox5NVVFHXB3rTgX+62+zbAjmQtcO07TlJXonPNoy2Dw/V9KSTe+C ZkwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oOzT7sOzTR42HbW+vtiKP9qod26e6MefuWrn5uRr7O8=; b=Qb4EGGqx2X9IEuDNFqBKfIh3wkpf0URCIYizVVG491l5wqcQRLN3A1JxDn7IQTO8Rd hiGnraGPnXJFYn5oPze2Zl9V36a3QECDOMFg3E59ucrVqzF/uAjQP1UcC8Ndvd+kz60H s7wXfmEr+QrYAWG0MsAPcVYRlwAnmVk+cITqQ/DQQQjeq6aVdHmipdv039A1bwcyxuNd 8ETryAZQnSPIFM2dyIuidJBjzp2ZjO39CbTnkzFQFWMIN16XqPf3E9giDOg7eExUA+aR i4xLMF6qEp4wbLN3px74RHe0bIG8q0b72hGaDhvtBn7E0INR/tFtHfTXyZUhWkJKV9uT j+Qw== X-Gm-Message-State: AOAM531FlyFyMrqWGMIGU1muY12OygN2ayPqEmVBClghlNKH0YPRvf5f BOCD59TY9wZSvNpuaeRUQWN2O3pctoxd3A== X-Google-Smtp-Source: ABdhPJytGbfUZG7DQNKlGepozdu+Rk5wjTBYSvYEC8AitbDdHEjBWa2K74utjsuqj/oO4JPbMA78Yg== X-Received: by 2002:adf:eac6:: with SMTP id o6mr23982189wrn.172.1613492232000; Tue, 16 Feb 2021 08:17:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/40] linux-user: Use cpu_untagged_addr in access_ok; split out *_untagged Date: Tue, 16 Feb 2021 16:16:34 +0000 Message-Id: <20210216161658.29881-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Provide both tagged and untagged versions of access_ok. In a few places use thread_cpu, as the user is several callees removed from do_syscall1. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/qemu.h | 11 +++++++++-- linux-user/elfload.c | 2 +- linux-user/hppa/cpu_loop.c | 8 ++++---- linux-user/i386/cpu_loop.c | 2 +- linux-user/i386/signal.c | 5 +++-- linux-user/syscall.c | 9 ++++++--- 6 files changed, 24 insertions(+), 13 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index b3ccffbf0fa..82eabb73f80 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -491,7 +491,7 @@ extern unsigned long guest_stack_size; #define VERIFY_READ PAGE_READ #define VERIFY_WRITE (PAGE_READ | PAGE_WRITE) =20 -static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) +static inline bool access_ok_untagged(int type, abi_ulong addr, abi_ulong = size) { if (size =3D=3D 0 ? !guest_addr_valid_untagged(addr) @@ -501,6 +501,12 @@ static inline bool access_ok(int type, abi_ulong addr,= abi_ulong size) return page_check_range((target_ulong)addr, size, type) =3D=3D 0; } =20 +static inline bool access_ok(CPUState *cpu, int type, + abi_ulong addr, abi_ulong size) +{ + return access_ok_untagged(type, cpu_untagged_addr(cpu, addr), size); +} + /* NOTE __get_user and __put_user use host pointers and don't check access. These are usually used to access struct data members once the struct has been locked - usually with lock_user_struct. */ @@ -636,8 +642,9 @@ abi_long copy_to_user(abi_ulong gaddr, void *hptr, size= _t len); host area will have the same contents as the guest. */ static inline void *lock_user(int type, abi_ulong guest_addr, long len, in= t copy) { - if (!access_ok(type, guest_addr, len)) + if (!access_ok_untagged(type, guest_addr, len)) { return NULL; + } #ifdef DEBUG_REMAP { void *addr; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 902be3ff117..73d750c8091 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -3510,7 +3510,7 @@ static int vma_get_mapping_count(const struct mm_stru= ct *mm) static abi_ulong vma_dump_size(const struct vm_area_struct *vma) { /* if we cannot even read the first page, skip it */ - if (!access_ok(VERIFY_READ, vma->vma_start, TARGET_PAGE_SIZE)) + if (!access_ok_untagged(VERIFY_READ, vma->vma_start, TARGET_PAGE_SIZE)) return (0); =20 /* diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 944511bbe43..3aaaf3337cb 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -35,7 +35,7 @@ static abi_ulong hppa_lws(CPUHPPAState *env) return -TARGET_ENOSYS; =20 case 0: /* elf32 atomic 32bit cmpxchg */ - if ((addr & 3) || !access_ok(VERIFY_WRITE, addr, 4)) { + if ((addr & 3) || !access_ok(cs, VERIFY_WRITE, addr, 4)) { return -TARGET_EFAULT; } old =3D tswap32(old); @@ -50,9 +50,9 @@ static abi_ulong hppa_lws(CPUHPPAState *env) return -TARGET_ENOSYS; } if (((addr | old | new) & ((1 << size) - 1)) - || !access_ok(VERIFY_WRITE, addr, 1 << size) - || !access_ok(VERIFY_READ, old, 1 << size) - || !access_ok(VERIFY_READ, new, 1 << size)) { + || !access_ok(cs, VERIFY_WRITE, addr, 1 << size) + || !access_ok(cs, VERIFY_READ, old, 1 << size) + || !access_ok(cs, VERIFY_READ, new, 1 << size)) { return -TARGET_EFAULT; } /* Note that below we use host-endian loads so that the cmpxchg diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index 19c8a18cd30..f813e87294a 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -99,7 +99,7 @@ static bool write_ok_or_segv(CPUX86State *env, abi_ptr ad= dr, size_t len) * For all the vsyscalls, NULL means "don't write anything" not * "write it at address 0". */ - if (addr =3D=3D 0 || access_ok(VERIFY_WRITE, addr, len)) { + if (addr =3D=3D 0 || access_ok(env_cpu(env), VERIFY_WRITE, addr, len))= { return true; } =20 diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c index 97a39204cc2..9320e1d4726 100644 --- a/linux-user/i386/signal.c +++ b/linux-user/i386/signal.c @@ -513,9 +513,10 @@ restore_sigcontext(CPUX86State *env, struct target_sig= context *sc) =20 fpstate_addr =3D tswapl(sc->fpstate); if (fpstate_addr !=3D 0) { - if (!access_ok(VERIFY_READ, fpstate_addr, - sizeof(struct target_fpstate))) + if (!access_ok(env_cpu(env), VERIFY_READ, fpstate_addr, + sizeof(struct target_fpstate))) { goto badframe; + } #ifndef TARGET_X86_64 cpu_x86_frstor(env, fpstate_addr, 1); #else diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 53529e4004c..3d0411da57e 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -3526,8 +3526,9 @@ static abi_long do_accept4(int fd, abi_ulong target_a= ddr, return -TARGET_EINVAL; } =20 - if (!access_ok(VERIFY_WRITE, target_addr, addrlen)) + if (!access_ok(thread_cpu, VERIFY_WRITE, target_addr, addrlen)) { return -TARGET_EFAULT; + } =20 addr =3D alloca(addrlen); =20 @@ -3557,8 +3558,9 @@ static abi_long do_getpeername(int fd, abi_ulong targ= et_addr, return -TARGET_EINVAL; } =20 - if (!access_ok(VERIFY_WRITE, target_addr, addrlen)) + if (!access_ok(thread_cpu, VERIFY_WRITE, target_addr, addrlen)) { return -TARGET_EFAULT; + } =20 addr =3D alloca(addrlen); =20 @@ -3588,8 +3590,9 @@ static abi_long do_getsockname(int fd, abi_ulong targ= et_addr, return -TARGET_EINVAL; } =20 - if (!access_ok(VERIFY_WRITE, target_addr, addrlen)) + if (!access_ok(thread_cpu, VERIFY_WRITE, target_addr, addrlen)) { return -TARGET_EFAULT; + } =20 addr =3D alloca(addrlen); =20 --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613493261796362.38959766172115; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=iEBIv7+OwI51woRY737KKllG0LWlaFF7AMx5WRjtclo=; b=nVvnUNNLun7cMAnTt0gMfqH86lfTela6X6GN859srQKdCMnDVfFLR1ArPtxHTHhjv2 RAH7WaVTiR9sI50XAxNZQsstQLFyS/hN3znLckra13lB5amMZ4HNl3BK7Iqd1tNbLp7B uB0aEWWx2GVBIBaa/v7Y4w8sP4kKX8rL7YFJFAmqFwDWBCDCRzHg8oiiVPcPf9wtB5s9 Y6A2tqwW5MdxlUzOXmmHWNGytKc2PmxCg01g31+1CxplV1vyDsAMCUYYl7BR74gvg4WW RhpHvfclTqPlAMP9B9oqxsQfsA8q3kJG6twuewufftl9j8NC35R0MhuoGb+Wz71MNDTb E1lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iEBIv7+OwI51woRY737KKllG0LWlaFF7AMx5WRjtclo=; b=KvkUwFtjFnIyCW15zBmuxNEPLmr6X2tcOJle/h5OS50YlhUfR5CR3XAFiKoKPS5vCW n22P9A4z2ntX+S5PzrJ/FxyuvJJEaw4aWePp1fMKaveggTI1D3L3D2uS9YVsJMShAzIX RoHEBvURLE+GGfvIqmXT3p33DNEVzG6M8NmMqhVIxONh5K6N6x2ILTs0C/ng2lE4yaPC JiNVjLh0+abYZBvqBPaDTM9h0fSqCMUQtGTdIIsWs+CKzRiqUIo+k0y/SfQ+pwENQWrd heA44eLyzOPkzQl5wg9J8YO3o8cBDrGh1McEFQ0mrJTf12ATfJfpkRdlsz4sAAMB7Pft 8KvA== X-Gm-Message-State: AOAM53049Gn5kYK4InO9F3k1w3JXEOdlAXZsa1RMMxIdp8r7gi738mpN wqROvsZ5IOx+oJh8SyDjSnFsVkPnDVM/jg== X-Google-Smtp-Source: ABdhPJwTbfZ+86ff0fSRc7ko9iaGo6TRktDqjH9pPNMIQrsrTnQoujro1hq54LmaJLtKEAc/Rg2mGw== X-Received: by 2002:a1c:20c7:: with SMTP id g190mr3749424wmg.156.1613492232687; Tue, 16 Feb 2021 08:17:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/40] linux-user: Move lock_user et al out of line Date: Tue, 16 Feb 2021 16:16:35 +0000 Message-Id: <20210216161658.29881-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson These functions are not small, except for unlock_user without debugging enabled. Move them out of line, and add missing braces on the way. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210212184902.1251044-18-richard.henderson@linaro.org [PMM: fixed the sense of an ifdef test in qemu.h] Signed-off-by: Peter Maydell --- linux-user/qemu.h | 47 +++++++------------------------------------- linux-user/uaccess.c | 46 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+), 40 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 82eabb73f80..971af97a2fb 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -640,57 +640,24 @@ abi_long copy_to_user(abi_ulong gaddr, void *hptr, si= ze_t len); =20 /* Lock an area of guest memory into the host. If copy is true then the host area will have the same contents as the guest. */ -static inline void *lock_user(int type, abi_ulong guest_addr, long len, in= t copy) -{ - if (!access_ok_untagged(type, guest_addr, len)) { - return NULL; - } -#ifdef DEBUG_REMAP - { - void *addr; - addr =3D g_malloc(len); - if (copy) - memcpy(addr, g2h(guest_addr), len); - else - memset(addr, 0, len); - return addr; - } -#else - return g2h_untagged(guest_addr); -#endif -} +void *lock_user(int type, abi_ulong guest_addr, long len, int copy); =20 /* Unlock an area of guest memory. The first LEN bytes must be flushed back to guest memory. host_ptr =3D NULL is explicitly allowed and does nothing. */ -static inline void unlock_user(void *host_ptr, abi_ulong guest_addr, - long len) -{ - -#ifdef DEBUG_REMAP - if (!host_ptr) - return; - if (host_ptr =3D=3D g2h_untagged(guest_addr)) - return; - if (len > 0) - memcpy(g2h_untagged(guest_addr), host_ptr, len); - g_free(host_ptr); +#ifndef DEBUG_REMAP +static inline void unlock_user(void *host_ptr, abi_ulong guest_addr, long = len) +{ } +#else +void unlock_user(void *host_ptr, abi_ulong guest_addr, long len); #endif -} =20 /* Return the length of a string in target memory or -TARGET_EFAULT if access error. */ abi_long target_strlen(abi_ulong gaddr); =20 /* Like lock_user but for null terminated strings. */ -static inline void *lock_user_string(abi_ulong guest_addr) -{ - abi_long len; - len =3D target_strlen(guest_addr); - if (len < 0) - return NULL; - return lock_user(VERIFY_READ, guest_addr, (long)(len + 1), 1); -} +void *lock_user_string(abi_ulong guest_addr); =20 /* Helper macros for locking/unlocking a target struct. */ #define lock_user_struct(type, host_ptr, guest_addr, copy) \ diff --git a/linux-user/uaccess.c b/linux-user/uaccess.c index e215ecc2a60..bba012ed159 100644 --- a/linux-user/uaccess.c +++ b/linux-user/uaccess.c @@ -4,6 +4,52 @@ =20 #include "qemu.h" =20 +void *lock_user(int type, abi_ulong guest_addr, long len, int copy) +{ + if (!access_ok_untagged(type, guest_addr, len)) { + return NULL; + } +#ifdef DEBUG_REMAP + { + void *addr; + addr =3D g_malloc(len); + if (copy) { + memcpy(addr, g2h(guest_addr), len); + } else { + memset(addr, 0, len); + } + return addr; + } +#else + return g2h_untagged(guest_addr); +#endif +} + +#ifdef DEBUG_REMAP +void unlock_user(void *host_ptr, abi_ulong guest_addr, long len); +{ + if (!host_ptr) { + return; + } + if (host_ptr =3D=3D g2h_untagged(guest_addr)) { + return; + } + if (len > 0) { + memcpy(g2h_untagged(guest_addr), host_ptr, len); + } + g_free(host_ptr); +} +#endif + +void *lock_user_string(abi_ulong guest_addr) +{ + abi_long len =3D target_strlen(guest_addr); + if (len < 0) { + return NULL; + } + return lock_user(VERIFY_READ, guest_addr, (long)(len + 1), 1); +} + /* copy_from_user() and copy_to_user() are usually used to copy data * buffers between the target and host. These internally perform * locking/unlocking of the memory. --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613493564; cv=none; d=zohomail.com; s=zohoarc; b=ejuNGf2oZloeGTmsLVj9nzJI0rDYjm69aRii+FfsoVx/bO640uNyJKft+voDr9Wi1Oauuo/GnMqjhyYzaaKbzymtsrMR6GmuCgWBzNjD+fHXDq4l0t2z7IGjpCQeWbxaM+CXiaGHinM9C1dFeqRr8CisCuXXf1kFxDGz/cBFXF4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613493564; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5JWfwKowe7rah/3Vj4T/sMmaK9HUgrKB3BjWRcVxMcw=; b=WHdVk0I0d4vZBBnd/VRauSfc7+3qmPmzRDmlllDPhLuAxW+a9xbnlt50ulxvE1UH+LhEz7izDkXC221Yd3eg+quPxOgkuMYTIY/nd+prp639d6s12vF+xP+mqzrsP8bIzFEeE72efHI9bzrwW1jmUifDs9QOAOJW0X857Lghs8Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613493563568588.0889385611416; Tue, 16 Feb 2021 08:39:23 -0800 (PST) Received: from localhost ([::1]:52494 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3Ng-00061e-PM for importer@patchew.org; Tue, 16 Feb 2021 11:39:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40572) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32v-0008Ht-Im for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:53 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:39893) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32J-0002RR-Aa for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:53 -0500 Received: by mail-wm1-x32d.google.com with SMTP id v62so5490617wmg.4 for ; Tue, 16 Feb 2021 08:17:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5JWfwKowe7rah/3Vj4T/sMmaK9HUgrKB3BjWRcVxMcw=; b=DuB8HQfSsz7qSwT47EVWeBnojAgzlhbJ3VEAY5sg6Xc3moqp5XC64DgHI38O2tsqQF OcY3GBAuBeabkBQBL9kW5yhjz1ZMGElDw22yTyE0WwDyEeDG3kJNUJ4njVoHTG7gRWhj ijVMCicQUGbn29M8nJKMJJPIc1/Fvk3Hm2AgUpUkAEJqKiWYRNg7kI/YpGQrME41h7xi vxXDt7E6Zf4KwoZgcL6nHj46K8I4aDRL+FzHH+pmICNP0wmKFZt1sqcLuL5UpActWRjM 0gDGSubPdBzkcV5/HGoUbVyEO5FoVaR+yhwWAIHyEBofL56XTD/nJyQF3FqJMVk/fsKZ dcTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5JWfwKowe7rah/3Vj4T/sMmaK9HUgrKB3BjWRcVxMcw=; b=UM4SZnbHNxy3wVa0TYNF2pvIWdXv95OGyJtAm9TxqWWCUyJr8ARSrS6qpl7TARnHbo QU4vTrb2wEbfNAeQwR7K0Yk62rIFb5QecFmz4AY35cDv0biBOQm5SZv5H2AijOeP0MG8 tZ0t8TBITzhvjuN1rTaR6foR1c4x96AT17luTisWrB8U0kGkk1X+yIVAabu5I46QDU/6 hPLHPEFhZVJbakhZ2H+5ePSIPjJ4J3N1k76ipWwUfBw3ODigaTN8bXxKa7PUE24KcR41 ENpD02frjRQTqbFwTAIrn8X6Yc+MEh2QTGxeiwSh1HxFY6XaAf+JJMbnPEPEO+MmixVX purQ== X-Gm-Message-State: AOAM532uw4a4fUyvohEAa/zWOLnJlwaWfSkgZUbVTsqgS5MpDIIK1sBk c/LCqQfcFrluOT8CG5+UYK9fxzoofUGIVg== X-Google-Smtp-Source: ABdhPJy3fMoc4pwlQQwblOIeb1KLL2i9C19+Yeuz1C6oSZNmU5tYYnBkabMKj2GrWNiu1J/TxCAkjg== X-Received: by 2002:a1c:6387:: with SMTP id x129mr3934170wmb.84.1613492233458; Tue, 16 Feb 2021 08:17:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/40] linux-user: Fix types in uaccess.c Date: Tue, 16 Feb 2021 16:16:36 +0000 Message-Id: <20210216161658.29881-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson For copy_*_user, only 0 and -TARGET_EFAULT are returned; no need to involve abi_long. Use size_t for lengths. Use bool for the lock_user copy argument. Use ssize_t for target_strlen, because we can't overflow the host memory space. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210212184902.1251044-19-richard.henderson@linaro.org [PMM: moved fix for ifdef error to previous commit] Signed-off-by: Peter Maydell --- linux-user/qemu.h | 12 +++++------- linux-user/uaccess.c | 45 ++++++++++++++++++++++---------------------- 2 files changed, 28 insertions(+), 29 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 971af97a2fb..d25a5dafc0f 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -7,8 +7,6 @@ #include "exec/cpu_ldst.h" =20 #undef DEBUG_REMAP -#ifdef DEBUG_REMAP -#endif /* DEBUG_REMAP */ =20 #include "exec/user/abitypes.h" =20 @@ -629,8 +627,8 @@ static inline bool access_ok(CPUState *cpu, int type, * buffers between the target and host. These internally perform * locking/unlocking of the memory. */ -abi_long copy_from_user(void *hptr, abi_ulong gaddr, size_t len); -abi_long copy_to_user(abi_ulong gaddr, void *hptr, size_t len); +int copy_from_user(void *hptr, abi_ulong gaddr, size_t len); +int copy_to_user(abi_ulong gaddr, void *hptr, size_t len); =20 /* Functions for accessing guest memory. The tget and tput functions read/write single values, byteswapping as necessary. The lock_user fun= ction @@ -640,13 +638,13 @@ abi_long copy_to_user(abi_ulong gaddr, void *hptr, si= ze_t len); =20 /* Lock an area of guest memory into the host. If copy is true then the host area will have the same contents as the guest. */ -void *lock_user(int type, abi_ulong guest_addr, long len, int copy); +void *lock_user(int type, abi_ulong guest_addr, size_t len, bool copy); =20 /* Unlock an area of guest memory. The first LEN bytes must be flushed back to guest memory. host_ptr =3D NULL is explicitly allowed and does nothing. */ #ifndef DEBUG_REMAP -static inline void unlock_user(void *host_ptr, abi_ulong guest_addr, long = len) +static inline void unlock_user(void *host_ptr, abi_ulong guest_addr, size_= t len) { } #else void unlock_user(void *host_ptr, abi_ulong guest_addr, long len); @@ -654,7 +652,7 @@ void unlock_user(void *host_ptr, abi_ulong guest_addr, = long len); =20 /* Return the length of a string in target memory or -TARGET_EFAULT if access error. */ -abi_long target_strlen(abi_ulong gaddr); +ssize_t target_strlen(abi_ulong gaddr); =20 /* Like lock_user but for null terminated strings. */ void *lock_user_string(abi_ulong guest_addr); diff --git a/linux-user/uaccess.c b/linux-user/uaccess.c index bba012ed159..76af6a92b11 100644 --- a/linux-user/uaccess.c +++ b/linux-user/uaccess.c @@ -4,7 +4,7 @@ =20 #include "qemu.h" =20 -void *lock_user(int type, abi_ulong guest_addr, long len, int copy) +void *lock_user(int type, abi_ulong guest_addr, size_t len, bool copy) { if (!access_ok_untagged(type, guest_addr, len)) { return NULL; @@ -26,7 +26,7 @@ void *lock_user(int type, abi_ulong guest_addr, long len,= int copy) } =20 #ifdef DEBUG_REMAP -void unlock_user(void *host_ptr, abi_ulong guest_addr, long len); +void unlock_user(void *host_ptr, abi_ulong guest_addr, size_t len); { if (!host_ptr) { return; @@ -34,7 +34,7 @@ void unlock_user(void *host_ptr, abi_ulong guest_addr, lo= ng len); if (host_ptr =3D=3D g2h_untagged(guest_addr)) { return; } - if (len > 0) { + if (len !=3D 0) { memcpy(g2h_untagged(guest_addr), host_ptr, len); } g_free(host_ptr); @@ -43,53 +43,53 @@ void unlock_user(void *host_ptr, abi_ulong guest_addr, = long len); =20 void *lock_user_string(abi_ulong guest_addr) { - abi_long len =3D target_strlen(guest_addr); + ssize_t len =3D target_strlen(guest_addr); if (len < 0) { return NULL; } - return lock_user(VERIFY_READ, guest_addr, (long)(len + 1), 1); + return lock_user(VERIFY_READ, guest_addr, (size_t)len + 1, 1); } =20 /* copy_from_user() and copy_to_user() are usually used to copy data * buffers between the target and host. These internally perform * locking/unlocking of the memory. */ -abi_long copy_from_user(void *hptr, abi_ulong gaddr, size_t len) +int copy_from_user(void *hptr, abi_ulong gaddr, size_t len) { - abi_long ret =3D 0; - void *ghptr; + int ret =3D 0; + void *ghptr =3D lock_user(VERIFY_READ, gaddr, len, 1); =20 - if ((ghptr =3D lock_user(VERIFY_READ, gaddr, len, 1))) { + if (ghptr) { memcpy(hptr, ghptr, len); unlock_user(ghptr, gaddr, 0); - } else + } else { ret =3D -TARGET_EFAULT; - + } return ret; } =20 - -abi_long copy_to_user(abi_ulong gaddr, void *hptr, size_t len) +int copy_to_user(abi_ulong gaddr, void *hptr, size_t len) { - abi_long ret =3D 0; - void *ghptr; + int ret =3D 0; + void *ghptr =3D lock_user(VERIFY_WRITE, gaddr, len, 0); =20 - if ((ghptr =3D lock_user(VERIFY_WRITE, gaddr, len, 0))) { + if (ghptr) { memcpy(ghptr, hptr, len); unlock_user(ghptr, gaddr, len); - } else + } else { ret =3D -TARGET_EFAULT; + } =20 return ret; } =20 /* Return the length of a string in target memory or -TARGET_EFAULT if access error */ -abi_long target_strlen(abi_ulong guest_addr1) +ssize_t target_strlen(abi_ulong guest_addr1) { uint8_t *ptr; abi_ulong guest_addr; - int max_len, len; + size_t max_len, len; =20 guest_addr =3D guest_addr1; for(;;) { @@ -101,11 +101,12 @@ abi_long target_strlen(abi_ulong guest_addr1) unlock_user(ptr, guest_addr, 0); guest_addr +=3D len; /* we don't allow wrapping or integer overflow */ - if (guest_addr =3D=3D 0 ||=20 - (guest_addr - guest_addr1) > 0x7fffffff) + if (guest_addr =3D=3D 0 || (guest_addr - guest_addr1) > 0x7fffffff= ) { return -TARGET_EFAULT; - if (len !=3D max_len) + } + if (len !=3D max_len) { break; + } } return guest_addr - guest_addr1; } --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613493491; cv=none; d=zohomail.com; s=zohoarc; b=d2QM0GrMYBeu+NnevzPOmY2EqILxgKH/q2MdOnLB5ibRy+wb/Ahn9rcOw1OLXGsaFifZHCNnmM/hfVCJ148+hmFmkbUo/yIdCx8fGyJi7N54CkNRoMKfQfd/AaUVQPGVs+p37ZaakBztn2DoWuw5EHS3RIt34l9I6ZoQlpDDru8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613493491; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UlcX36l+UoGhghkEb4MsmEOls0sHOtriGCkjp38bShg=; b=NnCrgCfN89G7PXNAy58nOE8I+Btg5/K2RojTVRLtgA4CIYGe0hw5zKcPv9paq2G8CKfYJcrehsFlq350RDEYk3RxL63lba/24p/LdYyrC41/f+7nCQuC1aDgSB/Pr13Z34esc7j5f0rnHU5iK33TVokaygo+0CxoUAxaq1tffHU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613493491467145.67316718928953; Tue, 16 Feb 2021 08:38:11 -0800 (PST) Received: from localhost ([::1]:49666 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3MW-0004ob-Db for importer@patchew.org; Tue, 16 Feb 2021 11:38:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40606) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32x-0008MR-8y for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:55 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:53114) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32J-0002S6-FC for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:54 -0500 Received: by mail-wm1-x335.google.com with SMTP id l17so9579098wmq.2 for ; Tue, 16 Feb 2021 08:17:15 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=UlcX36l+UoGhghkEb4MsmEOls0sHOtriGCkjp38bShg=; b=uG5UhkLlR6GOWM2yTL1SCAFzKW9489baz9/1luIKIuO42M7wMzUszR1RED+0F3yMiv 13qvUdD9anKEHcwxk9fkPUbGK/Z1BZBJLWEPN4chwH8LDnGfTgTygNwfX6KEweGAflII 42rpMAicO2cjK6wdDoK+OQfa/rbLMnSY0aLdmBjkxeQrZQ8bJJZeKGnHPMJKA05gJ/Ze yKCkV1yyPfkzbNEnwAN6OT0uwJhFEi+1ZFJ6RPxaftlMccQURGn7zjniJVW5mFnLlxSS 6kjm7GRFTPwJgCKPZKQth789a5AwctbhR7v+cIyg9lMWXrxvgIodkoSVo67wuEERg/X7 jKEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UlcX36l+UoGhghkEb4MsmEOls0sHOtriGCkjp38bShg=; b=j5O07mpSU91yab9nDV5dng9bLUiGS5mnBEXgDrherGbq/iXx1l9xrbk0nnPAVE1sgM Yy9YQRb+EgK8c29VNmJTOjOtKCuiT2QE5N/GwCNyGI41QjGZPQsH6btqWSp7hnmAuiO5 owuhdaRefweaFOuL+dnBRtvn4sj9CFDumdamEJhRQp+/YLQbaLMXwm/mlNcuMU+CVdBt aqEdRsCuETKlYGhECG5gHOvRt4UbO3cPgF3KaFvEKR6tCbJ6fjUqRMfNVJnWBTloqlcG ODQjSO5gkDlRO3mikmJuqq+narsuW/BMBUcOpj+JhkAsrbFAYPH70VKnL56TWMs6a13P ONqA== X-Gm-Message-State: AOAM531Ez4YFaoOyvfCNJZImmyN2dweqR8kM3Ck4fyJmYnUF+KMSKbKE JHPfak8FzOAzc4Hrzwcjc3WMT6Zl3TJg9g== X-Google-Smtp-Source: ABdhPJzGW66RNtInjYWOJaj5WGJyC3OKmckOLZUi0IDNrZYRsEJ66A47B5HZsju1zBC/Rm18z/CkYA== X-Received: by 2002:a7b:c206:: with SMTP id x6mr4067714wmi.48.1613492234075; Tue, 16 Feb 2021 08:17:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/40] linux-user: Handle tags in lock_user/unlock_user Date: Tue, 16 Feb 2021 16:16:37 +0000 Message-Id: <20210216161658.29881-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Resolve the untagged address once, using thread_cpu. Tidy the DEBUG_REMAP code using glib routines. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/uaccess.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/linux-user/uaccess.c b/linux-user/uaccess.c index 76af6a92b11..c6969130163 100644 --- a/linux-user/uaccess.c +++ b/linux-user/uaccess.c @@ -6,36 +6,37 @@ =20 void *lock_user(int type, abi_ulong guest_addr, size_t len, bool copy) { + void *host_addr; + + guest_addr =3D cpu_untagged_addr(thread_cpu, guest_addr); if (!access_ok_untagged(type, guest_addr, len)) { return NULL; } + host_addr =3D g2h_untagged(guest_addr); #ifdef DEBUG_REMAP - { - void *addr; - addr =3D g_malloc(len); - if (copy) { - memcpy(addr, g2h(guest_addr), len); - } else { - memset(addr, 0, len); - } - return addr; + if (copy) { + host_addr =3D g_memdup(host_addr, len); + } else { + host_addr =3D g_malloc0(len); } -#else - return g2h_untagged(guest_addr); #endif + return host_addr; } =20 #ifdef DEBUG_REMAP void unlock_user(void *host_ptr, abi_ulong guest_addr, size_t len); { + void *host_ptr_conv; + if (!host_ptr) { return; } - if (host_ptr =3D=3D g2h_untagged(guest_addr)) { + host_ptr_conv =3D g2h(thread_cpu, guest_addr); + if (host_ptr =3D=3D host_ptr_conv) { return; } if (len !=3D 0) { - memcpy(g2h_untagged(guest_addr), host_ptr, len); + memcpy(host_ptr_conv, host_ptr, len); } g_free(host_ptr); } --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613493685618169.86115146313045; Tue, 16 Feb 2021 08:41:25 -0800 (PST) Received: from localhost ([::1]:60894 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3Pf-0001ER-Ie for importer@patchew.org; Tue, 16 Feb 2021 11:41:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40626) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32y-0008P4-B1 for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:56 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:53104) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32K-0002ST-RX for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:56 -0500 Received: by mail-wm1-x32a.google.com with SMTP id l17so9579124wmq.2 for ; Tue, 16 Feb 2021 08:17:15 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=AD1krlDqnM6rLdWUu4MwKPyX4G+2IEAL1chH6nZXmXQ=; b=W1ljKUSnlySNmVgRsmY7Q6aVipcoya3jSuGLRubjIqvfjM2NoJVm+MMRK3krjDP4B2 n4b6jkSBQTayc9WFUo2P8DzLinYX5iWg0xmeuhfWnyKr4yZAt3qpND7KtsXeBuIV2hTb Nrpz/hQFMnCr9L47C5rdV8cIqJlF9wml1imzINGUMY9q6RSo0BbfJXY63GBIio8Nxd7S wfux59JRdEaQQuUlU9V3UQuoxbyip8iH2Zst9WGG/4eLTpAjOZPq9SzdSH4o1Nen9bGy U4J3xKd732+EXBbBrl5qFjBgi3SR79L82ZtF3nHQ9EUW3bJF97SZwDhSI9txUtU1a0Fn 9B5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AD1krlDqnM6rLdWUu4MwKPyX4G+2IEAL1chH6nZXmXQ=; b=RxfdGIjOv7G1CoYHlInVE033iWZHD/47lkWdP5klKLl3JTsoHIEvYwn3syhJYsMIqy sYmY3mHXKOmHrtoK2sGvx57L6v6pa9TmS+FDsf+xKdAlm6rh75xuMN7ovJ+1l7xkN8Zx BnumSFy2EiHiuXzGvk4ip662pBaPOGX222GpIz9OD2XGc4lvQz6OwTZiO7KtQSuZw04j qg99i/7NJslviPcOYqMQfYGWss/cN1IXdTFdspQ8++TkwAEYwJBKGcWizsbDLF7I3FAs rI2WSrSshYEnWNz651av4qKmZlFfz4PzLrZMkYzjufd1euyXeIXHp3ckuBuio6+sgtP+ fqJw== X-Gm-Message-State: AOAM532G1uewEsLf0Esxo5D9ixBPYB8agu9s4yR4IGe+HDVzwFSY7NDs okWtnBaaXhYFBKU6alNpOpGz/rvssXe0Sw== X-Google-Smtp-Source: ABdhPJzBJVAPxdvvvd4Xs66e95I2ntl0b9Zk7aXyzrPZbM0BsUW1HsvDSbCQg0Yi/o1BtsDBSEq06A== X-Received: by 2002:a1c:c904:: with SMTP id f4mr3962033wmb.14.1613492234692; Tue, 16 Feb 2021 08:17:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/40] linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE Date: Tue, 16 Feb 2021 16:16:38 +0000 Message-Id: <20210216161658.29881-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is the prctl bit that controls whether syscalls accept tagged addresses. See Documentation/arm64/tagged-address-abi.rst in the linux kernel. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/aarch64/target_syscall.h | 4 ++++ target/arm/cpu-param.h | 3 +++ target/arm/cpu.h | 31 +++++++++++++++++++++++++++++ linux-user/syscall.c | 24 ++++++++++++++++++++++ 4 files changed, 62 insertions(+) diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/targe= t_syscall.h index 3194e6b0093..820601dfcc8 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -30,4 +30,8 @@ struct target_pt_regs { # define TARGET_PR_PAC_APDBKEY (1 << 3) # define TARGET_PR_PAC_APGAKEY (1 << 4) =20 +#define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 +#define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 +# define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) + #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 00e7d9e9377..7f38d33b8ea 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -20,6 +20,9 @@ =20 #ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 12 +# ifdef TARGET_AARCH64 +# define TARGET_TAGGED_ADDRESSES +# endif #else /* * ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f240275407b..72a0819eb8c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -721,6 +721,11 @@ typedef struct CPUARMState { const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ void *gicv3state; + +#ifdef TARGET_TAGGED_ADDRESSES + /* Linux syscall tagged address support */ + bool tagged_addr_enable; +#endif } CPUARMState; =20 static inline void set_feature(CPUARMState *env, int feature) @@ -3604,6 +3609,32 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTx= Attrs *x) */ #define PAGE_BTI PAGE_TARGET_1 =20 +#ifdef TARGET_TAGGED_ADDRESSES +/** + * cpu_untagged_addr: + * @cs: CPU context + * @x: tagged address + * + * Remove any address tag from @x. This is explicitly related to the + * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. + * + * There should be a better place to put this, but we need this in + * include/exec/cpu_ldst.h, and not some place linux-user specific. + */ +static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + if (cpu->env.tagged_addr_enable) { + /* + * TBI is enabled for userspace but not kernelspace addresses. + * Only clear the tag if bit 55 is clear. + */ + x &=3D sextract64(x, 0, 56); + } + return x; +} +#endif + /* * Naming convention for isar_feature functions: * Functions which test 32-bit ID registers should have _aa32_ in diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 3d0411da57e..cf0b39461b6 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10993,6 +10993,30 @@ static abi_long do_syscall1(void *cpu_env, int num= , abi_long arg1, } } return -TARGET_EINVAL; + case TARGET_PR_SET_TAGGED_ADDR_CTRL: + { + abi_ulong valid_mask =3D TARGET_PR_TAGGED_ADDR_ENABLE; + CPUARMState *env =3D cpu_env; + + if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + env->tagged_addr_enable =3D arg2 & TARGET_PR_TAGGED_ADDR_E= NABLE; + return 0; + } + case TARGET_PR_GET_TAGGED_ADDR_CTRL: + { + abi_long ret =3D 0; + CPUARMState *env =3D cpu_env; + + if (arg2 || arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + if (env->tagged_addr_enable) { + ret |=3D TARGET_PR_TAGGED_ADDR_ENABLE; + } + return ret; + } #endif /* AARCH64 */ case PR_GET_SECCOMP: case PR_SET_SECCOMP: --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613493044; cv=none; d=zohomail.com; s=zohoarc; b=WS00ML81G/TcZhTJ/eFFaFtNFthKFUA2O8IxXCKvFNb7dLALNLozXlwkM1rPUCoKaqmy1qz0Vbx/yPrPt+Ogg+03rAncTZw25djdHDulierhGfn+IJc1oYlaHBbRFoGLCAuSE8ZG1VTuTB19UKcQ09VRU4jR4ORc/Ay8n2nhCt0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613493044; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ckxco/GpoGbL9O6IOcZGdqxDa2S9tI7HW6zzAnINujg=; b=nUbCpVlFG3sQAqMGeRsxFxkr0IJmI6LCdI2aTFzQlUlUubMXiIjZYvqsssHRjHsCwPJS+CzIPJtEpDQe5HrlJHoZl2/n3lhLAkkPIsw5i4crJ1KlczO2vXP1l1g4dwiBdQd7EV54a6ME4VU23Kya/zE3/TZ1xsm1Lurc9Qr3KbQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613493043839784.7200307356063; Tue, 16 Feb 2021 08:30:43 -0800 (PST) Received: from localhost ([::1]:36960 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3FJ-00076l-O5 for importer@patchew.org; Tue, 16 Feb 2021 11:30:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40634) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32y-0008Pp-Js for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:56 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:46714) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32K-0002Su-Vv for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:56 -0500 Received: by mail-wr1-x42a.google.com with SMTP id t15so13725972wrx.13 for ; Tue, 16 Feb 2021 08:17:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ckxco/GpoGbL9O6IOcZGdqxDa2S9tI7HW6zzAnINujg=; b=eTGKQi9VXjNWEHDeT55ah7E7SfOJ/EOhOH7g5sf5lgWxwfuouidVD+dPs0dBP04Wpe uiyUulUfZy4dq0+i0bXeeFfub2rh9CLAS8P3PESqe7dqVRyvR0vpSAUQr2pLb5ZywTsy YvcSkwzeUonO4YRj1w7xIrRMgvVmhaQEl+yEyTXIUspPaBnUceZtQ+OEveAerGDCNiMq fkae8MePicvkNtnx4qBBrDDCCs4pnsYoPpURMqXl2ulQF0nhRnBeBksidAxdvnbIcxmW D/O8+AEULrT5Yz8Vd7/CzwAzwVdPGVW/O0sfS4PLJwMdAnaywCBzpXQo7/EOBNdkBZJP aL3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ckxco/GpoGbL9O6IOcZGdqxDa2S9tI7HW6zzAnINujg=; b=cbHmvUeKbvTcH7OjC6EJSG4b5v4N3POWeE+dJM/KZyMx+G3DHan90DyCZS7pbB88Rx Rfzcugq8cQfhOT70ckV/b2QajHwLneYiYoCN/2fKDzFmcCkL/QbV+Jq7DRgvZPB23UCW yaXW1VYMRxbhjwYI608ih8L0/somn3t5CjtrV3IwBabLaaA4qDLgYxoraE2jBbxXUk2a eN2Dtc0KRXjmX9JuV5Vdx0bf9Ru8KueaN3qUevnMv4dMuT4P6eU96cpqGpTJbcgIZmWT EBWhCuZwXQSjbluTOsNwT6s19ndk1O3FSXcxl2yi0a8ksAPWkX6/eQS9Biz2wJcnsoR6 Q7FQ== X-Gm-Message-State: AOAM531YAlDTleqMoNB1Cmd0cm3iv8UxY9pVEhDd14GZlVajP5++zGpN JJ6To6BNTyjjovLmZcRVVHIRn3OVBwmXCA== X-Google-Smtp-Source: ABdhPJwq33UzXaItl2IWf6uvFAja1Y/ej8fP4ugag/XEAPNW4HJMFv4udhc1DOiWlj6C6SFcnf+d8w== X-Received: by 2002:adf:d1ce:: with SMTP id b14mr23964256wrd.329.1613492235317; Tue, 16 Feb 2021 08:17:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/40] target/arm: Improve gen_top_byte_ignore Date: Tue, 16 Feb 2021 16:16:39 +0000 Message-Id: <20210216161658.29881-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use simple arithmetic instead of a conditional move when tbi0 !=3D tbi1. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1c4b8d02f3b..b23a8975d54 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -183,17 +183,20 @@ static void gen_top_byte_ignore(DisasContext *s, TCGv= _i64 dst, /* Sign-extend from bit 55. */ tcg_gen_sextract_i64(dst, src, 0, 56); =20 - if (tbi !=3D 3) { - TCGv_i64 tcg_zero =3D tcg_const_i64(0); - - /* - * The two TBI bits differ. - * If tbi0, then !tbi1: only use the extension if positive. - * if !tbi0, then tbi1: only use the extension if negative. - */ - tcg_gen_movcond_i64(tbi =3D=3D 1 ? TCG_COND_GE : TCG_COND_LT, - dst, dst, tcg_zero, dst, src); - tcg_temp_free_i64(tcg_zero); + switch (tbi) { + case 1: + /* tbi0 but !tbi1: only use the extension if positive */ + tcg_gen_and_i64(dst, dst, src); + break; + case 2: + /* !tbi0 but tbi1: only use the extension if negative */ + tcg_gen_or_i64(dst, dst, src); + break; + case 3: + /* tbi0 and tbi1: always use the extension */ + break; + default: + g_assert_not_reached(); } } } --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613493396; cv=none; d=zohomail.com; s=zohoarc; b=HDlct6Ti8hI0xjkYYGay9Lt4W+0HY5MucKm5pKDX8h3vr9CuvTXddMQsPBR26VJKJS1FT48dmVEdyrmsmhHmRXAHlo10/NmuJ9IoV8ipfjcD4SLzFJ5cTZsukDWgBj4BZ8sRxdsYzL0OycvIskln+3XaiURJ16Xs/2x7RLrT8oc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613493396; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aBQbZtjh6qoRiTLl0J95xhpcxji8rRRUHNr03avILCc=; b=a+jio44hzAjQ5KXBYDsrhkZX6Mb6KLkOfxgL4p312hysBvKn0yG28Ri3KhAo9zew/2aLe5yW37JlZdI7hfskdOhjOFQxFtEB5Z3eY9ph3J1sMEs3zWRxMnp0/ksblTkmCsCquphaaa7iFro13dB5pTfJQ7+9sN/cjrPy6fMvek4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613493396533555.9612927088585; Tue, 16 Feb 2021 08:36:36 -0800 (PST) Received: from localhost ([::1]:45420 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3Kz-0002pZ-VQ for importer@patchew.org; Tue, 16 Feb 2021 11:36:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40656) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC32z-0008TO-Um for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:57 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:34325) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32L-0002T9-Cr for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:57 -0500 Received: by mail-wr1-x429.google.com with SMTP id n4so10809533wrx.1 for ; Tue, 16 Feb 2021 08:17:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=aBQbZtjh6qoRiTLl0J95xhpcxji8rRRUHNr03avILCc=; b=tHmAbL/dO8y84yaT9eFb/OJXY0cEOAFr7GCo162UBCEzkOLX0Y8Au3ejI0FW+uiFq6 0tTQrL1Yi/WZnjNNg1i8eaCKLK/dckxu+H4rO8UX646AJ7wnWJLKJOAY+ekz2ioVGjt2 BP4i1mgR/6qGYOS8yEjtnpcwWN+dnjrNIbfWyjs2ggBo45IwYv9hNXS2Ulo3GT3rXlAK uWAlkaNewC1947gX0V11j7qSe94/dJP2DaMRn5NexFejl8QBb/yGPHlFl4bVB93x46oO xCvPOMctBA8B5iHYtRU1J2A2OsIRpFvCotL+TgGyziS2iKI1vKJMMFY+73mnkBsPFII1 FgjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aBQbZtjh6qoRiTLl0J95xhpcxji8rRRUHNr03avILCc=; b=F45EH0iltz8lMcjIoOCRC8uvyfL5j8js2V0weuK/KRSPhSYwMVWHRwfWC6b3xXIcTC X1Hhvw4NW48fs+MvnIeVgfTIckKZBReDT2LzaUO9XhGfZuztbSYcRrSG16CEi0iUb8MO klrK0S04fAns3q+YUqELp49CbSBoS5CLbwPCaGE1l2NzW2URumQoggKCjBh7EwDx9Ltv Lu4sVmIk6nn9/iVNKKp0A7iFu5AJQ6+EXywnZwcaScrli8AHZWSAALQgl39fcwg/cw2q nLzARDTNz4EfOQvq06FUjZ/6Gp/AqJDTT380Kyb51/Bv/rB8jDLySx9eqf9dog0W2kok QpnA== X-Gm-Message-State: AOAM533ijVfnbXzOfIINdPWHqbijssa9uZSkgmdhGey+2sqC2QHDojxV tQksmrCiyJ1PLSnWMxgICm7Qu4NzO9HIJg== X-Google-Smtp-Source: ABdhPJyQJdAGcd9/iEDtcfdd570OS3obC/vXaXe446eYDU1NxYKnnOPZif5N0P2+ajAc2JBeWLQ7sA== X-Received: by 2002:adf:fb91:: with SMTP id a17mr24233214wrr.93.1613492235941; Tue, 16 Feb 2021 08:17:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/40] target/arm: Use the proper TBI settings for linux-user Date: Tue, 16 Feb 2021 16:16:40 +0000 Message-Id: <20210216161658.29881-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We were fudging TBI1 enabled to speed up the generated code. Now that we've improved the code generation, remove this. Also, tidy the comment to reflect the current code. The pauth test was testing a kernel address (-1) and making incorrect assumptions about TBI1; stick to userland addresses. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 4 ++-- target/arm/cpu.c | 10 +++------- tests/tcg/aarch64/pauth-2.c | 1 - 3 files changed, 5 insertions(+), 10 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index b251fe44506..112bbb14f07 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1425,9 +1425,9 @@ static inline bool tcma_check(uint32_t desc, int bit5= 5, int ptr_tag) */ static inline uint64_t useronly_clean_ptr(uint64_t ptr) { - /* TBI is known to be enabled. */ #ifdef CONFIG_USER_ONLY - ptr =3D sextract64(ptr, 0, 56); + /* TBI0 is known to be enabled, while TBI1 is disabled. */ + ptr &=3D sextract64(ptr, 0, 56); #endif return ptr; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5cf6c056c50..70cfcbc9181 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -205,14 +205,10 @@ static void arm_cpu_reset(DeviceState *dev) env->vfp.zcr_el[1] =3D MIN(cpu->sve_max_vq - 1, 3); } /* - * Enable TBI0 and TBI1. While the real kernel only enables TBI0, - * turning on both here will produce smaller code and otherwise - * make no difference to the user-level emulation. - * - * In sve_probe_page, we assume that this is set. - * Do not modify this without other changes. + * Enable TBI0 but not TBI1. + * Note that this must match useronly_clean_ptr. */ - env->cp15.tcr_el[1].raw_tcr =3D (3ULL << 37); + env->cp15.tcr_el[1].raw_tcr =3D (1ULL << 37); #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { diff --git a/tests/tcg/aarch64/pauth-2.c b/tests/tcg/aarch64/pauth-2.c index 9bba0beb639..978652ede3a 100644 --- a/tests/tcg/aarch64/pauth-2.c +++ b/tests/tcg/aarch64/pauth-2.c @@ -53,7 +53,6 @@ void do_test(uint64_t value) int main() { do_test(0); - do_test(-1); do_test(0xda004acedeadbeefull); return 0; } --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613493497; cv=none; d=zohomail.com; s=zohoarc; b=dKkflUc7n23pSca6iwPe2y/i6yK2P66dUe9POISbB8Kbks4aqgFOFZrVm0FJQmXOuxpG2Dn2/KY7C1oSMwLQGxJDPWdde8FP8PXzUJ6MVC3v45zN5Co87vcr6wkVEYyy/n7r/k7H3rZOFSc8ADO21ypCGzG+KR1jgDqrC3LcHrg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613493497; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DEZrFxnmtYoUbk6wmXZjoAUzhwwl0K4+E7EsDRLKJrQ=; b=AIej7DjHcsOhki+OKz70s/KBmHOa+Yp9uZdLYSXfvGsAzq7LDBYxfsXrPwbP+CvTDMeK3REck2ianfBplt60fQJpQTjDiLCijOlAMRR8YHhPGIKnMXgOsBFo3RZsXhlCEcDSSeDt55JddgLk7lPNocKv48W1sP7HloRBISEOrBU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613493496597648.9403153445893; Tue, 16 Feb 2021 08:38:16 -0800 (PST) Received: from localhost ([::1]:50288 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3Mc-00054V-2g for importer@patchew.org; Tue, 16 Feb 2021 11:38:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40704) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC332-00008i-Bg for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:00 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:46721) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32N-0002Ta-54 for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:00 -0500 Received: by mail-wr1-x431.google.com with SMTP id t15so13726117wrx.13 for ; Tue, 16 Feb 2021 08:17:18 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DEZrFxnmtYoUbk6wmXZjoAUzhwwl0K4+E7EsDRLKJrQ=; b=WU8/Til7azW7UT30YRGoVXOrB7WrSV09SL2v9Kyspe7jeICzZJ2UUW9OSPrK7KquV+ +3imfChyIKwRvUY9712zHBqI4vO0utwjnesr1AKydKZYgUp9sPhvDJqI3toMTUQfsuNy gc2JiJQ5vgCbTvPSq/6f1OB9j5DKK7SsG/Q6CGt69tkF1Q5heOxTChgX5TiuM6pvtCNC k1tMQznaseUZC/jszvt3tabZwbdW17BgTAyiABZq9F7FhmQb+7Vlh2wYYjpmKLtTSyj1 f9nxtsjweN4nWz6E1rU8nMH3BT/cjMG770ndjfACwoS3PKt0e6lTO7thkP3pjjm5jYXC Lq0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DEZrFxnmtYoUbk6wmXZjoAUzhwwl0K4+E7EsDRLKJrQ=; b=I119yKpUimIaj6WWDioFZXq2ByFT+gucNLd0ZdjFiJm1D4Bo0GZ94beCF2EAOSYkkB Nu8Xm2qZELMq/7nl8lnzoILriaSGWz7WH7G3HKt/N7vx+TYXU90Vz5MazkBadCItIchj BCTATGJo6/tNRYefHh9bvtMvZsNrRWcpz82tunRPGbUU2hrQYrXQQwv9io/8ffQIkVfk knGpN5nzSAgix64elu81c54DZNMHcfUeJRznrj51jpANWgX44SJF8cOcIpvfIT/tFoos bb5EoKWLw42QoSIHqtvZvQ5beJD9qqCHH25zRCZA2whWKu32nxMg1A7Spzmq+uwzFP7u Jl/g== X-Gm-Message-State: AOAM530tNoHadFvlYoghOnCxvEVqMhSnIWBt51x4+jZNt6OXu/XiUtSc mx/T2IwbwMWWZJhl7Gyl3vvv3tWIPAIh3g== X-Google-Smtp-Source: ABdhPJxR8n9E2iO2+NRYB3W745hV630Lf5bDsqL/M/JbpgOUE408mjgpHxoNVf5fNAnHmcCvrqDcAA== X-Received: by 2002:adf:edc8:: with SMTP id v8mr24405947wro.330.1613492236606; Tue, 16 Feb 2021 08:17:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/40] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG Date: Tue, 16 Feb 2021 16:16:41 +0000 Message-Id: <20210216161658.29881-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson These prctl fields are required for the function of MTE. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/aarch64/target_syscall.h | 9 ++++++ linux-user/syscall.c | 43 +++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/targe= t_syscall.h index 820601dfcc8..76f6c3391d3 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -33,5 +33,14 @@ struct target_pt_regs { #define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 #define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 # define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) +/* MTE tag check fault modes */ +# define TARGET_PR_MTE_TCF_SHIFT 1 +# define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT) +# define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT) +# define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT) +# define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT) +/* MTE tag inclusion mask */ +# define TARGET_PR_MTE_TAG_SHIFT 3 +# define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIF= T) =20 #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index cf0b39461b6..389ec097647 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10997,17 +10997,53 @@ static abi_long do_syscall1(void *cpu_env, int nu= m, abi_long arg1, { abi_ulong valid_mask =3D TARGET_PR_TAGGED_ADDR_ENABLE; CPUARMState *env =3D cpu_env; + ARMCPU *cpu =3D env_archcpu(env); + + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |=3D TARGET_PR_MTE_TCF_MASK; + valid_mask |=3D TARGET_PR_MTE_TAG_MASK; + } =20 if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) { return -TARGET_EINVAL; } env->tagged_addr_enable =3D arg2 & TARGET_PR_TAGGED_ADDR_E= NABLE; + + if (cpu_isar_feature(aa64_mte, cpu)) { + switch (arg2 & TARGET_PR_MTE_TCF_MASK) { + case TARGET_PR_MTE_TCF_NONE: + case TARGET_PR_MTE_TCF_SYNC: + case TARGET_PR_MTE_TCF_ASYNC: + break; + default: + return -EINVAL; + } + + /* + * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. + * Note that the syscall values are consistent with hw. + */ + env->cp15.sctlr_el[1] =3D + deposit64(env->cp15.sctlr_el[1], 38, 2, + arg2 >> TARGET_PR_MTE_TCF_SHIFT); + + /* + * Write PR_MTE_TAG to GCR_EL1[Exclude]. + * Note that the syscall uses an include mask, + * and hardware uses an exclude mask -- invert. + */ + env->cp15.gcr_el1 =3D + deposit64(env->cp15.gcr_el1, 0, 16, + ~arg2 >> TARGET_PR_MTE_TAG_SHIFT); + arm_rebuild_hflags(env); + } return 0; } case TARGET_PR_GET_TAGGED_ADDR_CTRL: { abi_long ret =3D 0; CPUARMState *env =3D cpu_env; + ARMCPU *cpu =3D env_archcpu(env); =20 if (arg2 || arg3 || arg4 || arg5) { return -TARGET_EINVAL; @@ -11015,6 +11051,13 @@ static abi_long do_syscall1(void *cpu_env, int num= , abi_long arg1, if (env->tagged_addr_enable) { ret |=3D TARGET_PR_TAGGED_ADDR_ENABLE; } + if (cpu_isar_feature(aa64_mte, cpu)) { + /* See above. */ + ret |=3D (extract64(env->cp15.sctlr_el[1], 38, 2) + << TARGET_PR_MTE_TCF_SHIFT); + ret =3D deposit64(ret, TARGET_PR_MTE_TAG_SHIFT, 16, + ~env->cp15.gcr_el1); + } return ret; } #endif /* AARCH64 */ --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613493643965987.7704188360617; Tue, 16 Feb 2021 08:40:43 -0800 (PST) Received: from localhost ([::1]:57996 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3Oz-0008O2-Sp for importer@patchew.org; Tue, 16 Feb 2021 11:40:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40680) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC331-00005G-88 for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:59 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:54565) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32N-0002Tj-4c for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:17:58 -0500 Received: by mail-wm1-x336.google.com with SMTP id w4so9550489wmi.4 for ; Tue, 16 Feb 2021 08:17:18 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=mtFt4GTnUFYUkbwP0dxAxUN2Lj3X7xcqbst4yTE9EcI=; b=I348R5gol5UeZMYGaEcOIeQoDnLiQ9SgpXNY8F54dTSagw32YcIo2aIalXD03S90M6 lLdCsbJtaELT1fwTbYK7xZygdBDrb6q2++AlxYgLx36DUTiVgd8TGN7S4335moQrJAP0 lg44Lby+ZIP7LpRUEH59345MzlmHnJraRiLhHgOeGry8q5xiIc+u9sagArnzd16OATWr lASL1DqhL0MmPV/D9tP5GaGEXGCWQEfuDPpvScnNLPTyjHWG1QRFF6EH6AiNWurwaNcp qtbaLf2CerlhFLDCrUQOtJovZvc7ULyavqq4Uo+vunPFbCN0AWBQYP9EoG+7aJGgfXlo ykaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mtFt4GTnUFYUkbwP0dxAxUN2Lj3X7xcqbst4yTE9EcI=; b=CEUx6IxSUt5tmYMpd53r+k7MRS1WngDVWLTSrw81vrP0DULFYKh0ix5o69r6lt4Vkk WL2yFXX4zxONFpUYgM4f9AHKAbTHZvZ9pfT6izblfj9C8tNcdBIUUiCkcSL4tbiMERwz 0VdvxWEE4vrhK+bM4PGFduRJ0ILHuEMobiE2LgE3Su0jPUAjzhIxaWEVoKAl6XfIUVxg yiIgGmPneTYWpyBMAOKuTwkgKpGi7ezHaykUsKbYdVKc84C664qyF2thI6kHX6PAggAk vBOuOP3g5+EozWl7L9b9SjeZcm+updzrU6v4JfPLyvMBkDo5SP7G3m6tqCIgp91PxU3/ BLBw== X-Gm-Message-State: AOAM531MyMoXe+2e3fZnZXDk/AS7hQ/sgAz0b3AQI2puxlP16jIb/1kS ZXOeyDrHbZX8MtfkBDrUFT12ryDmL7Unvg== X-Google-Smtp-Source: ABdhPJzc+kL0Rwk8ZvjyQpDHp3NjE989Uxq291ZNCBpiYWbl8Y9SeoYexj9R83yVagsREWW3ENyZvg== X-Received: by 2002:a05:600c:4c11:: with SMTP id d17mr3917521wmp.86.1613492237364; Tue, 16 Feb 2021 08:17:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/40] linux-user/aarch64: Implement PROT_MTE Date: Tue, 16 Feb 2021 16:16:42 +0000 Message-Id: <20210216161658.29881-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Remember the PROT_MTE bit as PAGE_MTE/PAGE_TARGET_2. Otherwise this does not yet have effect. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu-all.h | 1 + linux-user/syscall_defs.h | 1 + target/arm/cpu.h | 1 + linux-user/mmap.c | 22 ++++++++++++++-------- 4 files changed, 17 insertions(+), 8 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 937becd320a..76443eb11d5 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -276,6 +276,7 @@ extern intptr_t qemu_host_page_mask; #endif /* Target-specific bits that will be used via page_get_flags(). */ #define PAGE_TARGET_1 0x0080 +#define PAGE_TARGET_2 0x0200 =20 #if defined(CONFIG_USER_ONLY) void page_dump(FILE *f); diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index f98c1c1c8de..46a960fccb4 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -1311,6 +1311,7 @@ struct target_winsize { =20 #ifdef TARGET_AARCH64 #define TARGET_PROT_BTI 0x10 +#define TARGET_PROT_MTE 0x20 #endif =20 /* Common */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 72a0819eb8c..efa1618c4d5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3608,6 +3608,7 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxA= ttrs *x) * AArch64 usage of the PAGE_TARGET_* bits for linux-user. */ #define PAGE_BTI PAGE_TARGET_1 +#define PAGE_MTE PAGE_TARGET_2 =20 #ifdef TARGET_TAGGED_ADDRESSES /** diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 9fe0c634e24..7e3b2450368 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -84,18 +84,24 @@ static int validate_prot_to_pageflags(int *host_prot, i= nt prot) | (prot & PROT_EXEC ? PROT_READ : 0); =20 #ifdef TARGET_AARCH64 - /* - * The PROT_BTI bit is only accepted if the cpu supports the feature. - * Since this is the unusual case, don't bother checking unless - * the bit has been requested. If set and valid, record the bit - * within QEMU's page_flags. - */ - if (prot & TARGET_PROT_BTI) { + { ARMCPU *cpu =3D ARM_CPU(thread_cpu); - if (cpu_isar_feature(aa64_bti, cpu)) { + + /* + * The PROT_BTI bit is only accepted if the cpu supports the featu= re. + * Since this is the unusual case, don't bother checking unless + * the bit has been requested. If set and valid, record the bit + * within QEMU's page_flags. + */ + if ((prot & TARGET_PROT_BTI) && cpu_isar_feature(aa64_bti, cpu)) { valid |=3D TARGET_PROT_BTI; page_flags |=3D PAGE_BTI; } + /* Similarly for the PROT_MTE bit. */ + if ((prot & TARGET_PROT_MTE) && cpu_isar_feature(aa64_mte, cpu)) { + valid |=3D TARGET_PROT_MTE; + page_flags |=3D PAGE_MTE; + } } #endif =20 --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613494169; cv=none; d=zohomail.com; s=zohoarc; b=mtMBudAOCV3TzYDOd5KPmeVUsTzVWgEbtlhdLxUYsSy9r1ofIix1OvqbIwot3Gre6+lxpwqBPbex6KkCsbiZgdS5cjTVoFDKy7YT2iriwK+SndhdttYHOZLL0SzXcR+PntL17uN2cTQxpZAB+2ktwRemnIaoNP0qxIsMc2t8N2M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613494169; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZUSo2jjHuXXgbxp39YYuUnEbEqEz+hH8ovEI7pwKvQI=; b=D/oM/qgo5PcVbT9WybmR3mchJreJSLuCDJgIj0U/hYspsy4NRU4XXuNXUL8dx27Q1A1V8jqNUw3LxVyaudabLO1Iy+VXvJSFJIWfm9ncgSc7djMRgDBtava+tvHJPCCtIi2TLCBhqmI8PN7A24hNXrQFx77WH544JTsnsusCaGs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613494168978376.6087380397297; Tue, 16 Feb 2021 08:49:28 -0800 (PST) Received: from localhost ([::1]:50042 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3XT-0000Ml-M6 for importer@patchew.org; Tue, 16 Feb 2021 11:49:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40770) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC335-0000FN-Tg for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:04 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:43295) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32O-0002U0-OX for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:03 -0500 Received: by mail-wr1-x42e.google.com with SMTP id n8so13750929wrm.10 for ; Tue, 16 Feb 2021 08:17:19 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZUSo2jjHuXXgbxp39YYuUnEbEqEz+hH8ovEI7pwKvQI=; b=t+urG8CAsUAQBEQXKw0pIS9IeiVZ7zT2akPVhybh8PCXc43h4tTvUAhtDyISYJwK0X 6uq1pd8i54ydAITwgrc1tIqYMLQ5JcoKajZrVRvPwrHY2+3JCNmO0T6wIPHrelge4a/B 02/FEaWdriw2d1VT1fsEEc5X2vTxC+HiaXFCuKQrDj/fG1rigK8KoEwGgxOhkmZyW8uG sF/BvxmOPtmXe4jIknegyTJqMgV8HKmCbCK3zylXFx7tVQj9cDM02IxrwJ/QTFC56mGZ SzM32uPQ04g0JNr/L8TAD1ETcS6j9yr+W7Dz8zZM2mX3fOPSbW29p7FDsML/bbR7bxe1 xq/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZUSo2jjHuXXgbxp39YYuUnEbEqEz+hH8ovEI7pwKvQI=; b=r1rWym/++36PvU3nSzgOC4bQIRpNWcHzrC7Pd3SqJe8guf7dWE5Iz3kKxRlVRvbSO1 g0qnmWl/ecPr2QIvYaA/4sKXs280w7Tgk7HRUZR2DW6KIRWnC0Gvky9ivX7U9gCXfMvG BuFwB9appMbhk5Kw5bpvBaMV+VxF4P/1e3ffqdntQKL6HKJDHa3VnpeJoisGWbbnHEBH wmaZLnKTgel3GTQU+Lt+WE1x2/f+4v4S2ONN1QN/IG4Siz4bEa+qOkDbkWpZBDN5h02N JmxVjEISMHNYj/zPxqIfWaC++L1HoNLjzDFiQLZt6bLqwwEQVPm+9cPgYO98ZO12mmLe ZCFg== X-Gm-Message-State: AOAM531CwzewfkdSaOL0PiE9Id2+bQiaODjByDPjgBFlPqnZELAd5+81 C7foXrnfghu0U58yz2If+sBkrN39E7FUTA== X-Google-Smtp-Source: ABdhPJzN4owSYAvB5XU4JvBMtk1/gEQLxPXUnL9BjZbEPX2dN7kXSEvx2Af8Kqn9n/aInKEdM42nxw== X-Received: by 2002:a5d:4903:: with SMTP id x3mr19967726wrq.95.1613492238299; Tue, 16 Feb 2021 08:17:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/40] target/arm: Split out syndrome.h from internals.h Date: Tue, 16 Feb 2021 16:16:43 +0000 Message-Id: <20210216161658.29881-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson Move everything related to syndromes to a new file, which can be shared with linux-user. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210212184902.1251044-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 245 +----------------------------------- target/arm/syndrome.h | 273 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 274 insertions(+), 244 deletions(-) create mode 100644 target/arm/syndrome.h diff --git a/target/arm/internals.h b/target/arm/internals.h index 112bbb14f07..c38d5410175 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -26,6 +26,7 @@ #define TARGET_ARM_INTERNALS_H =20 #include "hw/registerfields.h" +#include "syndrome.h" =20 /* register banks for CPU modes */ #define BANK_USRSYS 0 @@ -262,250 +263,6 @@ static inline bool extended_addresses_enabled(CPUARMS= tate *env) (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EA= E)); } =20 -/* Valid Syndrome Register EC field values */ -enum arm_exception_class { - EC_UNCATEGORIZED =3D 0x00, - EC_WFX_TRAP =3D 0x01, - EC_CP15RTTRAP =3D 0x03, - EC_CP15RRTTRAP =3D 0x04, - EC_CP14RTTRAP =3D 0x05, - EC_CP14DTTRAP =3D 0x06, - EC_ADVSIMDFPACCESSTRAP =3D 0x07, - EC_FPIDTRAP =3D 0x08, - EC_PACTRAP =3D 0x09, - EC_CP14RRTTRAP =3D 0x0c, - EC_BTITRAP =3D 0x0d, - EC_ILLEGALSTATE =3D 0x0e, - EC_AA32_SVC =3D 0x11, - EC_AA32_HVC =3D 0x12, - EC_AA32_SMC =3D 0x13, - EC_AA64_SVC =3D 0x15, - EC_AA64_HVC =3D 0x16, - EC_AA64_SMC =3D 0x17, - EC_SYSTEMREGISTERTRAP =3D 0x18, - EC_SVEACCESSTRAP =3D 0x19, - EC_INSNABORT =3D 0x20, - EC_INSNABORT_SAME_EL =3D 0x21, - EC_PCALIGNMENT =3D 0x22, - EC_DATAABORT =3D 0x24, - EC_DATAABORT_SAME_EL =3D 0x25, - EC_SPALIGNMENT =3D 0x26, - EC_AA32_FPTRAP =3D 0x28, - EC_AA64_FPTRAP =3D 0x2c, - EC_SERROR =3D 0x2f, - EC_BREAKPOINT =3D 0x30, - EC_BREAKPOINT_SAME_EL =3D 0x31, - EC_SOFTWARESTEP =3D 0x32, - EC_SOFTWARESTEP_SAME_EL =3D 0x33, - EC_WATCHPOINT =3D 0x34, - EC_WATCHPOINT_SAME_EL =3D 0x35, - EC_AA32_BKPT =3D 0x38, - EC_VECTORCATCH =3D 0x3a, - EC_AA64_BKPT =3D 0x3c, -}; - -#define ARM_EL_EC_SHIFT 26 -#define ARM_EL_IL_SHIFT 25 -#define ARM_EL_ISV_SHIFT 24 -#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) -#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) - -static inline uint32_t syn_get_ec(uint32_t syn) -{ - return syn >> ARM_EL_EC_SHIFT; -} - -/* Utility functions for constructing various kinds of syndrome value. - * Note that in general we follow the AArch64 syndrome values; in a - * few cases the value in HSR for exceptions taken to AArch32 Hyp - * mode differs slightly, and we fix this up when populating HSR in - * arm_cpu_do_interrupt_aarch32_hyp(). - * The exception is FP/SIMD access traps -- these report extra information - * when taking an exception to AArch32. For those we include the extra cop= roc - * and TA fields, and mask them out when taking the exception to AArch64. - */ -static inline uint32_t syn_uncategorized(void) -{ - return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; -} - -static inline uint32_t syn_aa64_svc(uint32_t imm16) -{ - return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa64_hvc(uint32_t imm16) -{ - return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa64_smc(uint32_t imm16) -{ - return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) -{ - return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) - | (is_16bit ? 0 : ARM_EL_IL); -} - -static inline uint32_t syn_aa32_hvc(uint32_t imm16) -{ - return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa32_smc(void) -{ - return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; -} - -static inline uint32_t syn_aa64_bkpt(uint32_t imm16) -{ - return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff= ); -} - -static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) -{ - return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) - | (is_16bit ? 0 : ARM_EL_IL); -} - -static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, - int crn, int crm, int rt, - int isread) -{ - return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL - | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) - | (crm << 1) | isread; -} - -static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int op= c2, - int crn, int crm, int rt, int isre= ad, - bool is_16bit) -{ - return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) - | (crn << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int op= c2, - int crn, int crm, int rt, int isre= ad, - bool is_16bit) -{ - return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) - | (crn << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int c= rm, - int rt, int rt2, int isread, - bool is_16bit) -{ - return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc1 << 16) - | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int c= rm, - int rt, int rt2, int isread, - bool is_16bit) -{ - return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc1 << 16) - | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) -{ - /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA =3D=3D 0 coproc =3D= =3D 0xa */ - return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | 0xa; -} - -static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bi= t) -{ - /* AArch32 SIMD trap: TA =3D=3D 1 coproc =3D=3D 0 */ - return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (1 << 5); -} - -static inline uint32_t syn_sve_access_trap(void) -{ - return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; -} - -static inline uint32_t syn_pactrap(void) -{ - return EC_PACTRAP << ARM_EL_EC_SHIFT; -} - -static inline uint32_t syn_btitrap(int btype) -{ - return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; -} - -static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int = fsc) -{ - return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; -} - -static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, - int ea, int cm, int s1ptw, - int wnr, int fsc) -{ - return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL - | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) - | (wnr << 6) | fsc; -} - -static inline uint32_t syn_data_abort_with_iss(int same_el, - int sas, int sse, int srt, - int sf, int ar, - int ea, int cm, int s1ptw, - int wnr, int fsc, - bool is_16bit) -{ - return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) - | (sf << 15) | (ar << 14) - | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; -} - -static inline uint32_t syn_swstep(int same_el, int isv, int ex) -{ - return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SH= IFT) - | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; -} - -static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) -{ - return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIF= T) - | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; -} - -static inline uint32_t syn_breakpoint(int same_el) -{ - return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIF= T) - | ARM_EL_IL | 0x22; -} - -static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) -{ - return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | - (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | - (cv << 24) | (cond << 20) | ti; -} - /* Update a QEMU watchpoint based on the information the guest has set in = the * DBGWCR_EL1 and DBGWVR_EL1 registers. */ diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h new file mode 100644 index 00000000000..39a31260f2d --- /dev/null +++ b/target/arm/syndrome.h @@ -0,0 +1,273 @@ +/* + * QEMU ARM CPU -- syndrome functions and types + * + * Copyright (c) 2014 Linaro Ltd + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + * + * This header defines functions, types, etc which need to be shared + * between different source files within target/arm/ but which are + * private to it and not required by the rest of QEMU. + */ + +#ifndef TARGET_ARM_SYNDROME_H +#define TARGET_ARM_SYNDROME_H + +/* Valid Syndrome Register EC field values */ +enum arm_exception_class { + EC_UNCATEGORIZED =3D 0x00, + EC_WFX_TRAP =3D 0x01, + EC_CP15RTTRAP =3D 0x03, + EC_CP15RRTTRAP =3D 0x04, + EC_CP14RTTRAP =3D 0x05, + EC_CP14DTTRAP =3D 0x06, + EC_ADVSIMDFPACCESSTRAP =3D 0x07, + EC_FPIDTRAP =3D 0x08, + EC_PACTRAP =3D 0x09, + EC_CP14RRTTRAP =3D 0x0c, + EC_BTITRAP =3D 0x0d, + EC_ILLEGALSTATE =3D 0x0e, + EC_AA32_SVC =3D 0x11, + EC_AA32_HVC =3D 0x12, + EC_AA32_SMC =3D 0x13, + EC_AA64_SVC =3D 0x15, + EC_AA64_HVC =3D 0x16, + EC_AA64_SMC =3D 0x17, + EC_SYSTEMREGISTERTRAP =3D 0x18, + EC_SVEACCESSTRAP =3D 0x19, + EC_INSNABORT =3D 0x20, + EC_INSNABORT_SAME_EL =3D 0x21, + EC_PCALIGNMENT =3D 0x22, + EC_DATAABORT =3D 0x24, + EC_DATAABORT_SAME_EL =3D 0x25, + EC_SPALIGNMENT =3D 0x26, + EC_AA32_FPTRAP =3D 0x28, + EC_AA64_FPTRAP =3D 0x2c, + EC_SERROR =3D 0x2f, + EC_BREAKPOINT =3D 0x30, + EC_BREAKPOINT_SAME_EL =3D 0x31, + EC_SOFTWARESTEP =3D 0x32, + EC_SOFTWARESTEP_SAME_EL =3D 0x33, + EC_WATCHPOINT =3D 0x34, + EC_WATCHPOINT_SAME_EL =3D 0x35, + EC_AA32_BKPT =3D 0x38, + EC_VECTORCATCH =3D 0x3a, + EC_AA64_BKPT =3D 0x3c, +}; + +#define ARM_EL_EC_SHIFT 26 +#define ARM_EL_IL_SHIFT 25 +#define ARM_EL_ISV_SHIFT 24 +#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) +#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) + +static inline uint32_t syn_get_ec(uint32_t syn) +{ + return syn >> ARM_EL_EC_SHIFT; +} + +/* + * Utility functions for constructing various kinds of syndrome value. + * Note that in general we follow the AArch64 syndrome values; in a + * few cases the value in HSR for exceptions taken to AArch32 Hyp + * mode differs slightly, and we fix this up when populating HSR in + * arm_cpu_do_interrupt_aarch32_hyp(). + * The exception is FP/SIMD access traps -- these report extra information + * when taking an exception to AArch32. For those we include the extra cop= roc + * and TA fields, and mask them out when taking the exception to AArch64. + */ +static inline uint32_t syn_uncategorized(void) +{ + return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + +static inline uint32_t syn_aa64_svc(uint32_t imm16) +{ + return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa64_hvc(uint32_t imm16) +{ + return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa64_smc(uint32_t imm16) +{ + return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) +{ + return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) + | (is_16bit ? 0 : ARM_EL_IL); +} + +static inline uint32_t syn_aa32_hvc(uint32_t imm16) +{ + return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa32_smc(void) +{ + return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + +static inline uint32_t syn_aa64_bkpt(uint32_t imm16) +{ + return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff= ); +} + +static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) +{ + return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) + | (is_16bit ? 0 : ARM_EL_IL); +} + +static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, + int crn, int crm, int rt, + int isread) +{ + return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL + | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) + | (crm << 1) | isread; +} + +static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int op= c2, + int crn, int crm, int rt, int isre= ad, + bool is_16bit) +{ + return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) + | (crn << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int op= c2, + int crn, int crm, int rt, int isre= ad, + bool is_16bit) +{ + return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) + | (crn << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int c= rm, + int rt, int rt2, int isread, + bool is_16bit) +{ + return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc1 << 16) + | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int c= rm, + int rt, int rt2, int isread, + bool is_16bit) +{ + return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc1 << 16) + | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) +{ + /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA =3D=3D 0 coproc =3D= =3D 0xa */ + return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | 0xa; +} + +static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bi= t) +{ + /* AArch32 SIMD trap: TA =3D=3D 1 coproc =3D=3D 0 */ + return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (1 << 5); +} + +static inline uint32_t syn_sve_access_trap(void) +{ + return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; +} + +static inline uint32_t syn_pactrap(void) +{ + return EC_PACTRAP << ARM_EL_EC_SHIFT; +} + +static inline uint32_t syn_btitrap(int btype) +{ + return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; +} + +static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int = fsc) +{ + return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; +} + +static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, + int ea, int cm, int s1ptw, + int wnr, int fsc) +{ + return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL + | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) + | (wnr << 6) | fsc; +} + +static inline uint32_t syn_data_abort_with_iss(int same_el, + int sas, int sse, int srt, + int sf, int ar, + int ea, int cm, int s1ptw, + int wnr, int fsc, + bool is_16bit) +{ + return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) + | (sf << 15) | (ar << 14) + | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; +} + +static inline uint32_t syn_swstep(int same_el, int isv, int ex) +{ + return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SH= IFT) + | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; +} + +static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) +{ + return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIF= T) + | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; +} + +static inline uint32_t syn_breakpoint(int same_el) +{ + return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIF= T) + | ARM_EL_IL | 0x22; +} + +static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) +{ + return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | + (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | + (cv << 24) | (cond << 20) | ti; +} + +#endif /* TARGET_ARM_SYNDROME_H */ --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613493580; cv=none; d=zohomail.com; s=zohoarc; b=cveMDl2mfjlih3p8oU+zrwPX/rnLquQT9VaNY4hJZDBy7w/eMTDbY3+71nNn2C6aqxlhH/h6XV9b0AahE/UEHRHI4Fq8UXog1iuWYYUp4DluhUvD4Uf5F0k2g4Kgee20PWsu7MhtA12LdaRgSW2jIJZDDzodgaxadB8A6K8u6jo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613493580; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OUdGnepARkSKCi0JQLawkwQhjAV1702z7wSnXOJ7NXU=; b=XRGJ8d1HJFe7jgDAUD0L1R0D0Y9N3B7JeM3rlUD7Rob68g/SlPYNT3QDDqAacn3AdY4MMe9g09FT3tnW+jPLFy92WBo7vWYi9GErnz4z0Xgfrsi+WQv/EUThdsuK1knWIp6rcY+u1463d1KmguFKZSOM8jiA4TqlJm3qFdycE38= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613493579758469.3024861041264; Tue, 16 Feb 2021 08:39:39 -0800 (PST) Received: from localhost ([::1]:53852 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3Nx-0006ad-Nr for importer@patchew.org; Tue, 16 Feb 2021 11:39:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40734) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC333-0000D9-JS for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:01 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:39896) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32O-0002UC-Of for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:01 -0500 Received: by mail-wm1-x32f.google.com with SMTP id v62so5490893wmg.4 for ; Tue, 16 Feb 2021 08:17:19 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OUdGnepARkSKCi0JQLawkwQhjAV1702z7wSnXOJ7NXU=; b=PSO8XemDHg2A79NDIPI/UM0Uy9JlBQeDo03pZJp8moPwQgSOrJj980r6YbRhyp7RLS sTcDJsUxcHZvWuROBPliTfqmJ3wywANPk0fCCh/u5g65SBqAD+QqqrQDj5/5ESRUbOxR 46hLRV5aipeVzRTceU8Cp12u2xsjcAGxKbtV5Ig2Edv1y2EfzJiuqVhlZBsqVGhBejIs N/vYaJlivGYpREHVbn/C7x7CFALDwiZWm0VaeqjL7KFGOCNif3PWb/bL0n8DVswYMToD zFiiarvav9GXWVldtSHSglyMi24TwoZPG+1/cp3P/Z1QPeRbJqzXnmsF7v5utZey34YI l36g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OUdGnepARkSKCi0JQLawkwQhjAV1702z7wSnXOJ7NXU=; b=iaXoB+lPzLqoBYsuxmo7dzHeOWsemE2Jqwy/zUc2+NItbwF9P8MuelQHQ2Z+OEhyuW +mFOcnRL89N2VDTQXmH8uDoTdbbqPMd9qhtXKyVfSRfuBSUcUzHTn7z9ti98PNiWJ9Mi JE3JFPXUaaA2xPpZfwSFr4fiuXEvaMlRiVfrHOid0RBO9s2p45m2qa9IedgJ/HXYeEke crj31bKieD/YhX1FkjsF/IOMJ2QXXAGZXMRT6htZvebJvicjccY6axrLCUrPr7VvxmQz GVmv/rxzQ4cJNb4BLdlB6KQCux5uwiCH51/JdtpMQsBfiKuBNdTrbu/djGEKXSh3gxFx 4Yww== X-Gm-Message-State: AOAM53229lTlv0xQwadI61huZYt6BUF6Z/ld+crscDuZsEai/46BXf91 4pUN3TsuB8pFkWOfjcu41oCLZcrnWhbMzA== X-Google-Smtp-Source: ABdhPJwVXFxLe67Q4U9AH4nDEqM89clycD1OW7VewC/uvaH1yeJdWYjyGB3tVLMPuGP0gOvpcsl3ng== X-Received: by 2002:a05:600c:203:: with SMTP id 3mr3092577wmi.187.1613492239037; Tue, 16 Feb 2021 08:17:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/40] linux-user/aarch64: Pass syndrome to EXC_*_ABORT Date: Tue, 16 Feb 2021 16:16:44 +0000 Message-Id: <20210216161658.29881-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson A proper syndrome is required to fill in the proper si_code. Use page_get_flags to determine permission vs translation for user-only. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-27-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/aarch64/cpu_loop.c | 24 +++++++++++++++++++++--- target/arm/tlb_helper.c | 15 +++++++++------ 2 files changed, 30 insertions(+), 9 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 42b9c15f536..4e43906e66a 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -23,6 +23,7 @@ #include "cpu_loop-common.h" #include "qemu/guest-random.h" #include "hw/semihosting/common-semi.h" +#include "target/arm/syndrome.h" =20 #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r =3D get_user_u32((x), (gaddr)); \ @@ -76,7 +77,7 @@ void cpu_loop(CPUARMState *env) { CPUState *cs =3D env_cpu(env); - int trapnr; + int trapnr, ec, fsc; abi_long ret; target_siginfo_t info; =20 @@ -117,9 +118,26 @@ void cpu_loop(CPUARMState *env) case EXCP_DATA_ABORT: info.si_signo =3D TARGET_SIGSEGV; info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; info._sifields._sigfault._addr =3D env->exception.vaddress; + + /* We should only arrive here with EC in {DATAABORT, INSNABORT= }. */ + ec =3D syn_get_ec(env->exception.syndrome); + assert(ec =3D=3D EC_DATAABORT || ec =3D=3D EC_INSNABORT); + + /* Both EC have the same format for FSC, or close enough. */ + fsc =3D extract32(env->exception.syndrome, 0, 6); + switch (fsc) { + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + info.si_code =3D TARGET_SEGV_MAPERR; + break; + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + info.si_code =3D TARGET_SEGV_ACCERR; + break; + default: + g_assert_not_reached(); + } + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_DEBUG: diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index df85079d9f0..9609333cbdf 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -154,21 +154,24 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr) { ARMCPU *cpu =3D ARM_CPU(cs); + ARMMMUFaultInfo fi =3D {}; =20 #ifdef CONFIG_USER_ONLY - cpu->env.exception.vaddress =3D address; - if (access_type =3D=3D MMU_INST_FETCH) { - cs->exception_index =3D EXCP_PREFETCH_ABORT; + int flags =3D page_get_flags(useronly_clean_ptr(address)); + if (flags & PAGE_VALID) { + fi.type =3D ARMFault_Permission; } else { - cs->exception_index =3D EXCP_DATA_ABORT; + fi.type =3D ARMFault_Translation; } - cpu_loop_exit_restore(cs, retaddr); + + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); #else hwaddr phys_addr; target_ulong page_size; int prot, ret; MemTxAttrs attrs =3D {}; - ARMMMUFaultInfo fi =3D {}; ARMCacheAttrs cacheattrs =3D {}; =20 /* --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613493816744301.63762910354296; Tue, 16 Feb 2021 08:43:36 -0800 (PST) Received: from localhost ([::1]:38210 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3Rm-0003fT-D7 for importer@patchew.org; Tue, 16 Feb 2021 11:43:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC334-0000Er-HR for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:02 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:34336) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32Q-0002Ue-3U for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:02 -0500 Received: by mail-wr1-x434.google.com with SMTP id n4so10809809wrx.1 for ; Tue, 16 Feb 2021 08:17:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-28-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/aarch64/target_signal.h | 2 ++ linux-user/aarch64/cpu_loop.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target= _signal.h index ddd73169f0f..777fb667fea 100644 --- a/linux-user/aarch64/target_signal.h +++ b/linux-user/aarch64/target_signal.h @@ -21,5 +21,7 @@ typedef struct target_sigaltstack { =20 #include "../generic/signal.h" =20 +#define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */ + #define TARGET_ARCH_HAS_SETUP_FRAME #endif /* AARCH64_TARGET_SIGNAL_H */ diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 4e43906e66a..b6a2e65593f 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -134,6 +134,9 @@ void cpu_loop(CPUARMState *env) case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ info.si_code =3D TARGET_SEGV_ACCERR; break; + case 0x11: /* Synchronous Tag Check Fault */ + info.si_code =3D TARGET_SEGV_MTESERR; + break; default: g_assert_not_reached(); } --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613494072; cv=none; d=zohomail.com; s=zohoarc; b=V4SrQHYCVGx3NRDITphO51gbXZFst3H/9m8ZOs/1f1HXgJlEpsQ1WkZ3txSoPOfC2miLvGl1sRTBCoQAkWFYDpICkMNdRSgeVaetrOtNFEtnBD29OaGNB70LOsB0KDDNdxZwubMVxokuav4/cB4oOpwC7RoJ0goZgYX3h0GaRvA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613494072; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9QV6dxD/KPvoWsDk194HBYNrAPYe1/TdmLXa1Hr0QMw=; b=nQdb1btjKhndLubQXyA398cMP871k8C/JXSRZS3c/qrqHatRqmruqqydUF27XKOZRg BQ/WaBnuWR45jeVkehpnxNJKbJzzyMokZvpNW3Im/Ca/GSXlRfDpRuDEgXcwjgtR/MZv 50PD6PlbKvc+zwwBTkohTaLpmCcZge8Hai2SzAL5gY8wkfK4spXx9To9fvd9FWg2SmRA i7Z1oKpmbX06w3cK8MOliDUaGHKc9dPlE7lGeRY63TSS1eeX5NF7EExRkD8PG3M7hjHA 6cc4BWbBT9gF0VqQ9YADmP6a+jq7h0dgz4S5vBw8u++RB+ur7uDCvHj34cUXTnxml7h0 9U/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9QV6dxD/KPvoWsDk194HBYNrAPYe1/TdmLXa1Hr0QMw=; b=i8ecZmL+cbzCKGEpSuXAubR7V1yTAe81JsXtRzLKnAstFiHnfQIho6Zuot/XWsbTvT Qp9G2qqgw514GKI1k+880CwdG4+wtIkyj/cJQPAabw+yVo2pe2gGn2ygmcYGVs1rXu1K VHasO0DADdhpN0vwSvrrHZbgAdI5F6qipYXTcMs0cWhVeUv+QwinVwghYtYO8NdVODq8 zXhFlSNtNZ89bMZpNA+A4q01fktQzfaNmnzcdkauJHTZO4lhWc8vxNtxvhugNlRyulQR e8b64NJ/AZPLr5/dYMxuMYEtQakIcotmBbW2vcoThSXtsDC5IuA0aN4daIE+CTZxI5/A jCpA== X-Gm-Message-State: AOAM530Di+jgTJm2d70OchJJBqfuPBwZYXpokHoQftbSflF3Y7aw39vq r53RCy+WUj++llbaVZSZjBsLUBqQ23tx/g== X-Google-Smtp-Source: ABdhPJwAsRowfehofWI34AeQIPeS5f/ZOQd3KVIKfYkFQj5ZkhXG7fL19L7coYJ4zQ/xzgK/J45HiA== X-Received: by 2002:a05:600c:4113:: with SMTP id j19mr1303011wmi.82.1613492240237; Tue, 16 Feb 2021 08:17:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/40] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error Date: Tue, 16 Feb 2021 16:16:46 +0000 Message-Id: <20210216161658.29881-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson The real kernel collects _TIF_MTE_ASYNC_FAULT into the current thread's state on any kernel entry (interrupt, exception etc), and then delivers the signal in advance of resuming the thread. This means that while the signal won't be delivered immediately, it will not be delayed forever -- at minimum it will be delivered after the next clock interrupt. We don't have a clock interrupt in linux-user, so we issue a cpu_kick to signal a return to the main loop at the end of the current TB. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/aarch64/target_signal.h | 1 + linux-user/aarch64/cpu_loop.c | 11 +++++++++++ target/arm/mte_helper.c | 10 ++++++++++ 3 files changed, 22 insertions(+) diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target= _signal.h index 777fb667fea..18013e1b235 100644 --- a/linux-user/aarch64/target_signal.h +++ b/linux-user/aarch64/target_signal.h @@ -21,6 +21,7 @@ typedef struct target_sigaltstack { =20 #include "../generic/signal.h" =20 +#define TARGET_SEGV_MTEAERR 8 /* Asynchronous ARM MTE error */ #define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */ =20 #define TARGET_ARCH_HAS_SETUP_FRAME diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index b6a2e65593f..7c42f657068 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -164,6 +164,17 @@ void cpu_loop(CPUARMState *env) EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\= n", trapnr); abort(); } + + /* Check for MTE asynchronous faults */ + if (unlikely(env->cp15.tfsr_el[0])) { + env->cp15.tfsr_el[0] =3D 0; + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info._sifields._sigfault._addr =3D 0; + info.si_code =3D TARGET_SEGV_MTEAERR; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + process_pending_signals(env); /* Exception return on AArch64 always clears the exclusive monitor, * so any return to running guest code implies this. diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 153bd1e9df8..d55f8d1e1ed 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -565,6 +565,16 @@ static void mte_check_fail(CPUARMState *env, uint32_t = desc, select =3D 0; } env->cp15.tfsr_el[el] |=3D 1 << select; +#ifdef CONFIG_USER_ONLY + /* + * Stand in for a timer irq, setting _TIF_MTE_ASYNC_FAULT, + * which then sends a SIGSEGV when the thread is next scheduled. + * This cpu will return to the main loop at the end of the TB, + * which is rather sooner than "normal". But the alternative + * is waiting until the next syscall. + */ + qemu_cpu_kick(env_cpu(env)); +#endif break; =20 default: --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613493879; cv=none; d=zohomail.com; s=zohoarc; b=EnWthxMc1l7VRiFedc8KVG/HQI1k4n9gaD+juywG6pQijLpbPASJdkvIf/tEXetf0X0hjG05cNIiwCu8eN7K4bCBBZRsCIXMLqAnwFHjlhIgEUkIPIQK3aW81vQW6rFWz2iNi0SpWozmKbArAR7bCIog8Q4MnC4WU0kNacZlymk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613493879; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9e9V0n7IBTjs6YDR/+9PeRgafaFDEAzf50hk1SqmPEc=; b=gfGYiHUSCo164zmx26llWTRaFga2NqJuhdyEyrZMas6Y/q+Uu6Vsf1Te74KZbcPBNdEOP7XdDEI74Y4Htq9vODlNJZgPB5SrSOjpAWSF7GmVU8nX5W5t1JKS4kpt7eeJnDfXQe8ESJiqsNPQ8Bv1r0s2VjSEnTeRwIypc2rXCkE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613493879424468.3344505011693; Tue, 16 Feb 2021 08:44:39 -0800 (PST) Received: from localhost ([::1]:41258 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3Sn-0004v4-49 for importer@patchew.org; Tue, 16 Feb 2021 11:44:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40764) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC335-0000F6-H7 for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:03 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:46717) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32Q-0002VD-N9 for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:03 -0500 Received: by mail-wr1-x42c.google.com with SMTP id t15so13726385wrx.13 for ; Tue, 16 Feb 2021 08:17:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9e9V0n7IBTjs6YDR/+9PeRgafaFDEAzf50hk1SqmPEc=; b=OdeUMejCWJeQJmIAdfr4Tv6usTEV6btq3mssO6Z+IphcpRWSQJT0x3WgNgSl6oBPDH D/egZWClbLWYqcJlx3wrWM5CyZykVjvITGVeiCze06wnq9sQDLMgVL0dWSTXABPFoCQX JaQ/bLoh7YenLY3jRVk0DI8vVL+GiOQ8aJyky1w3DGdRY9O6WzfblLTXd5PvyMrWaNKm y8v9HKVV2zayO4QdZy6HIF0qu3CBS2LZtpRD4KhknCECJRTHvWyalUOyckItYOOOK/9B ESx+iiSs8r0W5tTnNlNDmYpYhGAZG4BL03Wi2L+BsaD6dP8wI944sVL1hYuU1h9JH6OZ bIeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9e9V0n7IBTjs6YDR/+9PeRgafaFDEAzf50hk1SqmPEc=; b=PPcHDY1K5VajcwJ2Q+j0AVXoqRtpTcrFD85jOShy0sjYUJakk871Stxm0Wu90KvlW2 yhnNdOO1npthiR+qvxl421qo8AK10Yjm7BPkuUM3qxeM1e6f6lIJosaVGjtRD7gou5S4 rGX7kjkhDC0KEAFioQQgErgS9BtbfekeC9pBzK0cg80VImlGSWLQfw2xHf2RqPsGPs5s unq1PTu5SMyQhKZJs6mrIlKhTdBIeab7zn7jxNIbmnQlTDLwD62k5sbPiLGno/E+vB+i ao9dtHda/RgLoJpaV36XMmbb/13G2r5DTWdzp59+0DG1h/gDfN7d35kx1tfT/OfGeqK3 zs9g== X-Gm-Message-State: AOAM530JQOPiSA0gZzK5hCZK1rXtmel5dAWoyne3iBW0GIQb2S42YCI3 Tk4fqUDnyIT4t/coxgJPdTv1wH38BDMhvQ== X-Google-Smtp-Source: ABdhPJybfaz7o0uE6pIU88PK0KikuaYxgQ17FbuIHYdAyX0itpCUUsqVcch6Ta+e9kocCMPzPDFvdQ== X-Received: by 2002:adf:fc86:: with SMTP id g6mr24271849wrr.20.1613492240788; Tue, 16 Feb 2021 08:17:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/40] target/arm: Add allocation tag storage for user mode Date: Tue, 16 Feb 2021 16:16:47 +0000 Message-Id: <20210216161658.29881-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use the now-saved PAGE_ANON and PAGE_MTE bits, and the per-page saved data. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-30-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/mte_helper.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index d55f8d1e1ed..1c569336eae 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -78,8 +78,33 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int= ptr_mmu_idx, int tag_size, uintptr_t ra) { #ifdef CONFIG_USER_ONLY - /* Tag storage not implemented. */ - return NULL; + uint64_t clean_ptr =3D useronly_clean_ptr(ptr); + int flags =3D page_get_flags(clean_ptr); + uint8_t *tags; + uintptr_t index; + + if (!(flags & (ptr_access =3D=3D MMU_DATA_STORE ? PAGE_WRITE : PAGE_RE= AD))) { + /* SIGSEGV */ + arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access, + ptr_mmu_idx, false, ra); + g_assert_not_reached(); + } + + /* Require both MAP_ANON and PROT_MTE for the page. */ + if (!(flags & PAGE_ANON) || !(flags & PAGE_MTE)) { + return NULL; + } + + tags =3D page_get_target_data(clean_ptr); + if (tags =3D=3D NULL) { + size_t alloc_size =3D TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); + tags =3D page_alloc_target_data(clean_ptr, alloc_size); + assert(tags !=3D NULL); + } + + index =3D extract32(ptr, LOG2_TAG_GRANULE + 1, + TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); + return tags + index; #else uintptr_t index; CPUIOTLBEntry *iotlbentry; --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161349434857777.42289196194906; Tue, 16 Feb 2021 08:52:28 -0800 (PST) Received: from localhost ([::1]:58702 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3aM-0004AG-CH for importer@patchew.org; Tue, 16 Feb 2021 11:52:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40778) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC336-0000FU-5x for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:04 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:40444) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32Q-0002Vz-Nu for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:03 -0500 Received: by mail-wr1-x42d.google.com with SMTP id v14so13773324wro.7 for ; Tue, 16 Feb 2021 08:17:22 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-31-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 70cfcbc9181..b8bc89e71fc 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -209,6 +209,21 @@ static void arm_cpu_reset(DeviceState *dev) * Note that this must match useronly_clean_ptr. */ env->cp15.tcr_el[1].raw_tcr =3D (1ULL << 37); + + /* Enable MTE */ + if (cpu_isar_feature(aa64_mte, cpu)) { + /* Enable tag access, but leave TCF0 as No Effect (0). */ + env->cp15.sctlr_el[1] |=3D SCTLR_ATA0; + /* + * Exclude all tags, so that tag 0 is always used. + * This corresponds to Linux current->thread.gcr_incl =3D 0. + * + * Set RRND, so that helper_irg() will generate a seed later. + * Here in cpu_reset(), the crypto subsystem has not yet been + * initialized. + */ + env->cp15.gcr_el1 =3D 0x1ffff; + } #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613494598; cv=none; d=zohomail.com; s=zohoarc; b=mS/hTuDO9iour1wb4vmLsS7w7IA7NyBoX9zDkQsXJzK6mTLjEckj+ufJKojtQoBRqrv/y5TspfwqPoqP8nqc8ombwEv/HDNb2AGutB+ONZEG/Rn7ricCXKmdLMWRz+xEbMH7VO5Cd2YLkCGxVUKt0QIZTuOI89k614bTrep9Zpc= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210212184902.1251044-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- tests/tcg/aarch64/mte.h | 60 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/mte-1.c | 28 +++++++++++++++ tests/tcg/aarch64/mte-2.c | 45 +++++++++++++++++++++++ tests/tcg/aarch64/mte-3.c | 51 ++++++++++++++++++++++++++ tests/tcg/aarch64/mte-4.c | 45 +++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 6 ++++ tests/tcg/configure.sh | 4 +++ 7 files changed, 239 insertions(+) create mode 100644 tests/tcg/aarch64/mte.h create mode 100644 tests/tcg/aarch64/mte-1.c create mode 100644 tests/tcg/aarch64/mte-2.c create mode 100644 tests/tcg/aarch64/mte-3.c create mode 100644 tests/tcg/aarch64/mte-4.c diff --git a/tests/tcg/aarch64/mte.h b/tests/tcg/aarch64/mte.h new file mode 100644 index 00000000000..141cef522ce --- /dev/null +++ b/tests/tcg/aarch64/mte.h @@ -0,0 +1,60 @@ +/* + * Linux kernel fallback API definitions for MTE and test helpers. + * + * Copyright (c) 2021 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef PR_SET_TAGGED_ADDR_CTRL +# define PR_SET_TAGGED_ADDR_CTRL 55 +#endif +#ifndef PR_TAGGED_ADDR_ENABLE +# define PR_TAGGED_ADDR_ENABLE (1UL << 0) +#endif +#ifndef PR_MTE_TCF_SHIFT +# define PR_MTE_TCF_SHIFT 1 +# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TAG_SHIFT 3 +#endif + +#ifndef PROT_MTE +# define PROT_MTE 0x20 +#endif + +#ifndef SEGV_MTEAERR +# define SEGV_MTEAERR 8 +# define SEGV_MTESERR 9 +#endif + +static void enable_mte(int tcf) +{ + int r =3D prctl(PR_SET_TAGGED_ADDR_CTRL, + PR_TAGGED_ADDR_ENABLE | tcf | (0xfffe << PR_MTE_TAG_SHIF= T), + 0, 0, 0); + if (r < 0) { + perror("PR_SET_TAGGED_ADDR_CTRL"); + exit(2); + } +} + +static void *alloc_mte_mem(size_t size) +{ + void *p =3D mmap(NULL, size, PROT_READ | PROT_WRITE | PROT_MTE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (p =3D=3D MAP_FAILED) { + perror("mmap PROT_MTE"); + exit(2); + } + return p; +} diff --git a/tests/tcg/aarch64/mte-1.c b/tests/tcg/aarch64/mte-1.c new file mode 100644 index 00000000000..88dcd617add --- /dev/null +++ b/tests/tcg/aarch64/mte-1.c @@ -0,0 +1,28 @@ +/* + * Memory tagging, basic pass cases. + * + * Copyright (c) 2021 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "mte.h" + +int main(int ac, char **av) +{ + int *p0, *p1, *p2; + long c; + + enable_mte(PR_MTE_TCF_NONE); + p0 =3D alloc_mte_mem(sizeof(*p0)); + + asm("irg %0,%1,%2" : "=3Dr"(p1) : "r"(p0), "r"(1)); + assert(p1 !=3D p0); + asm("subp %0,%1,%2" : "=3Dr"(c) : "r"(p0), "r"(p1)); + assert(c =3D=3D 0); + + asm("stg %0, [%0]" : : "r"(p1)); + asm("ldg %0, [%1]" : "=3Dr"(p2) : "r"(p0), "0"(p0)); + assert(p1 =3D=3D p2); + + return 0; +} diff --git a/tests/tcg/aarch64/mte-2.c b/tests/tcg/aarch64/mte-2.c new file mode 100644 index 00000000000..a62278276a4 --- /dev/null +++ b/tests/tcg/aarch64/mte-2.c @@ -0,0 +1,45 @@ +/* + * Memory tagging, basic fail cases, synchronous signals. + * + * Copyright (c) 2021 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "mte.h" + +void pass(int sig, siginfo_t *info, void *uc) +{ + assert(info->si_code =3D=3D SEGV_MTESERR); + exit(0); +} + +int main(int ac, char **av) +{ + struct sigaction sa; + int *p0, *p1, *p2; + long excl =3D 1; + + enable_mte(PR_MTE_TCF_SYNC); + p0 =3D alloc_mte_mem(sizeof(*p0)); + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=3Dr"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl !=3D 1); + asm("irg %0,%1,%2" : "=3Dr"(p2) : "r"(p0), "r"(excl)); + assert(p1 !=3D p2); + + /* Store the tag from the first pointer. */ + asm("stg %0, [%0]" : : "r"(p1)); + + *p1 =3D 0; + + memset(&sa, 0, sizeof(sa)); + sa.sa_sigaction =3D pass; + sa.sa_flags =3D SA_SIGINFO; + sigaction(SIGSEGV, &sa, NULL); + + *p2 =3D 0; + + abort(); +} diff --git a/tests/tcg/aarch64/mte-3.c b/tests/tcg/aarch64/mte-3.c new file mode 100644 index 00000000000..424ea685c2b --- /dev/null +++ b/tests/tcg/aarch64/mte-3.c @@ -0,0 +1,51 @@ +/* + * Memory tagging, basic fail cases, asynchronous signals. + * + * Copyright (c) 2021 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "mte.h" + +void pass(int sig, siginfo_t *info, void *uc) +{ + assert(info->si_code =3D=3D SEGV_MTEAERR); + exit(0); +} + +int main(int ac, char **av) +{ + struct sigaction sa; + long *p0, *p1, *p2; + long excl =3D 1; + + enable_mte(PR_MTE_TCF_ASYNC); + p0 =3D alloc_mte_mem(sizeof(*p0)); + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=3Dr"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl !=3D 1); + asm("irg %0,%1,%2" : "=3Dr"(p2) : "r"(p0), "r"(excl)); + assert(p1 !=3D p2); + + /* Store the tag from the first pointer. */ + asm("stg %0, [%0]" : : "r"(p1)); + + *p1 =3D 0; + + memset(&sa, 0, sizeof(sa)); + sa.sa_sigaction =3D pass; + sa.sa_flags =3D SA_SIGINFO; + sigaction(SIGSEGV, &sa, NULL); + + /* + * Signal for async error will happen eventually. + * For a real kernel this should be after the next IRQ (e.g. timer). + * For qemu linux-user, we kick the cpu and exit at the next TB. + * In either case, loop until this happens (or killed by timeout). + * For extra sauce, yield, producing EXCP_YIELD to cpu_loop(). + */ + asm("str %0, [%0]; yield" : : "r"(p2)); + while (1); +} diff --git a/tests/tcg/aarch64/mte-4.c b/tests/tcg/aarch64/mte-4.c new file mode 100644 index 00000000000..a8cc9f59841 --- /dev/null +++ b/tests/tcg/aarch64/mte-4.c @@ -0,0 +1,45 @@ +/* + * Memory tagging, re-reading tag checks. + * + * Copyright (c) 2021 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "mte.h" + +void __attribute__((noinline)) tagset(void *p, size_t size) +{ + size_t i; + for (i =3D 0; i < size; i +=3D 16) { + asm("stg %0, [%0]" : : "r"(p + i)); + } +} + +void __attribute__((noinline)) tagcheck(void *p, size_t size) +{ + size_t i; + void *c; + + for (i =3D 0; i < size; i +=3D 16) { + asm("ldg %0, [%1]" : "=3Dr"(c) : "r"(p + i), "0"(p)); + assert(c =3D=3D p); + } +} + +int main(int ac, char **av) +{ + size_t size =3D getpagesize() * 4; + long excl =3D 1; + int *p0, *p1; + + enable_mte(PR_MTE_TCF_ASYNC); + p0 =3D alloc_mte_mem(size); + + /* Tag the pointer. */ + asm("irg %0,%1,%2" : "=3Dr"(p1) : "r"(p0), "r"(excl)); + + tagset(p1, size); + tagcheck(p1, size); + + return 0; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index d7d33e293c0..bf53ad00870 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -35,6 +35,12 @@ endif # bti-2 tests PROT_BTI, so no special compiler support required. AARCH64_TESTS +=3D bti-2 =20 +# MTE Tests +ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_MTE),) +AARCH64_TESTS +=3D mte-1 mte-2 mte-3 mte-4 +mte-%: CFLAGS +=3D -march=3Darmv8.5-a+memtag +endif + # Semihosting smoke test for linux-user AARCH64_TESTS +=3D semihosting run-semihosting: semihosting diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index e1b70e25f23..ba8ac9a93e9 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -244,6 +244,10 @@ for target in $target_list; do -mbranch-protection=3Dstandard -o $TMPE $TMPC; then echo "CROSS_CC_HAS_ARMV8_BTI=3Dy" >> $config_target_mak fi + if do_compiler "$target_compiler" $target_compiler_cflags \ + -march=3Darmv8.5-a+memtag -o $TMPE $TMPC; then + echo "CROSS_CC_HAS_ARMV8_MTE=3Dy" >> $config_target_mak + fi ;; esac =20 --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613493735305148.8075647252781; Tue, 16 Feb 2021 08:42:15 -0800 (PST) Received: from localhost ([::1]:34236 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3QT-0001sq-1e for importer@patchew.org; Tue, 16 Feb 2021 11:42:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40868) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC33G-0000HO-I0 for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:15 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:37321) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32S-0002X3-Tw for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:11 -0500 Received: by mail-wr1-x42e.google.com with SMTP id v15so13789592wrx.4 for ; Tue, 16 Feb 2021 08:17:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CHzSelrqiJpml+/7oW4ipaAhal6n0PwtZseSIYjMtLw=; b=U4nOa8xPGUd9Y0o0zKQP+dpj7+++fLBQzeNOdvyUWdCa1BJp0iAIwllEHlvjPmiqLv lbkI+kroTcFVTAdVEbv3JaVErn20MKbsrBAJeHRibwBAUx2Jq8luNk99aft3yTfTbnfS w9uGffZAzOS0rggSMoPFd4G3C3/mKStI4DOvWxwFcC7vCf9O9xjr4A87WaNY+Dy+5E3s 2BCVoJCerpvDsTBy4qiSU8ey/Dy6obiEwUytxbrm18/ruTMjkeV1tGYw5Dd1i0UVqqZr 5yitwPXQcfImo28P9fSfSnNswBuOYpEUo7AErwRVLt7YEfJN5J/yI0NZn5L/0yk1i6hw jhyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CHzSelrqiJpml+/7oW4ipaAhal6n0PwtZseSIYjMtLw=; b=cUZ2afRW9biPA7BlAjS7AgVtCHg3vJmtKNt8j8plZTYN8B9N4bP/Zhjjtl8yHFYhkA 2cLdTjcNNHNdDzQo2UwPIy9DrBDLdW4f8+V3D2LUW8iV+MMs0RdH9Nzu8w4cCF1YQ43m S/TpWsLvWaPkoD5vcwsFIkfFLQdfeov35Hqh7BmlQoVSP+0fbi6gO0zYmTQAwv87vovz OpuS6nJOMYEmSzoW0WRW9I0ld8Ui8pjboXccwlqN9YtqR8NJNgZFSPJT5K0l+JXbbkUm k3mB3fsAVSkd7i03j2AR8lMrL+bWpMQmd66z3Knx5/m+7YBI0r2B6Q3V9JQAJDE+OiTE z3Wg== X-Gm-Message-State: AOAM532b6CZvrsmxq6Z3BFOGUw5H32ZoGgBgZBo8rZxgpNLm89wI2YpC SihkLS05bUp3ZMjcIO5pkdRo94E5b2Sjlw== X-Google-Smtp-Source: ABdhPJzGOxpVKOr9bD3M2hMD4uTYsvfHMeWk1Ebq5pcif0yqn+0OhHiSQA9BxZOc3YSqzkzOjOVQbA== X-Received: by 2002:a5d:5248:: with SMTP id k8mr24406300wrc.17.1613492243545; Tue, 16 Feb 2021 08:17:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/40] hw/i2c: Implement NPCM7XX SMBus Module Single Mode Date: Tue, 16 Feb 2021 16:16:50 +0000 Message-Id: <20210216161658.29881-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Hao Wu This commit implements the single-byte mode of the SMBus. Each Nuvoton SoC has 16 System Management Bus (SMBus). These buses compliant with SMBus and I2C protocol. This patch implements the single-byte mode of the SMBus. In this mode, the user sends or receives a byte each time. The SMBus device transmits it to the underlying i2c device and sends an interrupt back to the QEMU guest. Reviewed-by: Doug Evans Reviewed-by: Tyrong Ting Signed-off-by: Hao Wu Reviewed-by: Corey Minyard Message-id: 20210210220426.3577804-2-wuhaotsh@google.com Acked-by: Corey Minyard Signed-off-by: Peter Maydell --- docs/system/arm/nuvoton.rst | 2 +- include/hw/arm/npcm7xx.h | 2 + include/hw/i2c/npcm7xx_smbus.h | 88 ++++ hw/arm/npcm7xx.c | 68 ++- hw/i2c/npcm7xx_smbus.c | 783 +++++++++++++++++++++++++++++++++ hw/i2c/meson.build | 1 + hw/i2c/trace-events | 11 + 7 files changed, 938 insertions(+), 17 deletions(-) create mode 100644 include/hw/i2c/npcm7xx_smbus.h create mode 100644 hw/i2c/npcm7xx_smbus.c diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index a1786342e21..34fc799b2df 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -43,6 +43,7 @@ Supported devices * GPIO controller * Analog to Digital Converter (ADC) * Pulse Width Modulation (PWM) + * SMBus controller (SMBF) =20 Missing devices --------------- @@ -58,7 +59,6 @@ Missing devices =20 * Ethernet controllers (GMAC and EMC) * USB device (USBD) - * SMBus controller (SMBF) * Peripheral SPI controller (PSPI) * SD/MMC host * PECI interface diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index f6227aa8aa8..cea1bd1f620 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -20,6 +20,7 @@ #include "hw/adc/npcm7xx_adc.h" #include "hw/cpu/a9mpcore.h" #include "hw/gpio/npcm7xx_gpio.h" +#include "hw/i2c/npcm7xx_smbus.h" #include "hw/mem/npcm7xx_mc.h" #include "hw/misc/npcm7xx_clk.h" #include "hw/misc/npcm7xx_gcr.h" @@ -85,6 +86,7 @@ typedef struct NPCM7xxState { NPCM7xxMCState mc; NPCM7xxRNGState rng; NPCM7xxGPIOState gpio[8]; + NPCM7xxSMBusState smbus[16]; EHCISysBusState ehci; OHCISysBusState ohci; NPCM7xxFIUState fiu[2]; diff --git a/include/hw/i2c/npcm7xx_smbus.h b/include/hw/i2c/npcm7xx_smbus.h new file mode 100644 index 00000000000..b9761a69932 --- /dev/null +++ b/include/hw/i2c/npcm7xx_smbus.h @@ -0,0 +1,88 @@ +/* + * Nuvoton NPCM7xx SMBus Module. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ +#ifndef NPCM7XX_SMBUS_H +#define NPCM7XX_SMBUS_H + +#include "exec/memory.h" +#include "hw/i2c/i2c.h" +#include "hw/irq.h" +#include "hw/sysbus.h" + +/* + * Number of addresses this module contains. Do not change this without + * incrementing the version_id in the vmstate. + */ +#define NPCM7XX_SMBUS_NR_ADDRS 10 + +typedef enum NPCM7xxSMBusStatus { + NPCM7XX_SMBUS_STATUS_IDLE, + NPCM7XX_SMBUS_STATUS_SENDING, + NPCM7XX_SMBUS_STATUS_RECEIVING, + NPCM7XX_SMBUS_STATUS_NEGACK, + NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE, + NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK, +} NPCM7xxSMBusStatus; + +/* + * struct NPCM7xxSMBusState - System Management Bus device state. + * @bus: The underlying I2C Bus. + * @irq: GIC interrupt line to fire on events (if enabled). + * @sda: The serial data register. + * @st: The status register. + * @cst: The control status register. + * @cst2: The control status register 2. + * @cst3: The control status register 3. + * @ctl1: The control register 1. + * @ctl2: The control register 2. + * @ctl3: The control register 3. + * @ctl4: The control register 4. + * @ctl5: The control register 5. + * @addr: The SMBus module's own addresses on the I2C bus. + * @scllt: The SCL low time register. + * @sclht: The SCL high time register. + * @status: The current status of the SMBus. + */ +typedef struct NPCM7xxSMBusState { + SysBusDevice parent; + + MemoryRegion iomem; + + I2CBus *bus; + qemu_irq irq; + + uint8_t sda; + uint8_t st; + uint8_t cst; + uint8_t cst2; + uint8_t cst3; + uint8_t ctl1; + uint8_t ctl2; + uint8_t ctl3; + uint8_t ctl4; + uint8_t ctl5; + uint8_t addr[NPCM7XX_SMBUS_NR_ADDRS]; + + uint8_t scllt; + uint8_t sclht; + + NPCM7xxSMBusStatus status; +} NPCM7xxSMBusState; + +#define TYPE_NPCM7XX_SMBUS "npcm7xx-smbus" +#define NPCM7XX_SMBUS(obj) OBJECT_CHECK(NPCM7xxSMBusState, (obj), \ + TYPE_NPCM7XX_SMBUS) + +#endif /* NPCM7XX_SMBUS_H */ diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index d1fe9bd1df6..f8950f94708 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -102,6 +102,22 @@ enum NPCM7xxInterrupt { NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ NPCM7XX_EHCI_IRQ =3D 61, NPCM7XX_OHCI_IRQ =3D 62, + NPCM7XX_SMBUS0_IRQ =3D 64, + NPCM7XX_SMBUS1_IRQ, + NPCM7XX_SMBUS2_IRQ, + NPCM7XX_SMBUS3_IRQ, + NPCM7XX_SMBUS4_IRQ, + NPCM7XX_SMBUS5_IRQ, + NPCM7XX_SMBUS6_IRQ, + NPCM7XX_SMBUS7_IRQ, + NPCM7XX_SMBUS8_IRQ, + NPCM7XX_SMBUS9_IRQ, + NPCM7XX_SMBUS10_IRQ, + NPCM7XX_SMBUS11_IRQ, + NPCM7XX_SMBUS12_IRQ, + NPCM7XX_SMBUS13_IRQ, + NPCM7XX_SMBUS14_IRQ, + NPCM7XX_SMBUS15_IRQ, NPCM7XX_PWM0_IRQ =3D 93, /* PWM module 0 */ NPCM7XX_PWM1_IRQ, /* PWM module 1 */ NPCM7XX_GPIO0_IRQ =3D 116, @@ -152,6 +168,26 @@ static const hwaddr npcm7xx_pwm_addr[] =3D { 0xf0104000, }; =20 +/* Direct memory-mapped access to each SMBus Module. */ +static const hwaddr npcm7xx_smbus_addr[] =3D { + 0xf0080000, + 0xf0081000, + 0xf0082000, + 0xf0083000, + 0xf0084000, + 0xf0085000, + 0xf0086000, + 0xf0087000, + 0xf0088000, + 0xf0089000, + 0xf008a000, + 0xf008b000, + 0xf008c000, + 0xf008d000, + 0xf008e000, + 0xf008f000, +}; + static const struct { hwaddr regs_addr; uint32_t unconnected_pins; @@ -353,6 +389,11 @@ static void npcm7xx_init(Object *obj) object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_= GPIO); } =20 + for (i =3D 0; i < ARRAY_SIZE(s->smbus); i++) { + object_initialize_child(obj, "smbus[*]", &s->smbus[i], + TYPE_NPCM7XX_SMBUS); + } + object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI); object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI); =20 @@ -509,6 +550,17 @@ static void npcm7xx_realize(DeviceState *dev, Error **= errp) npcm7xx_irq(s, NPCM7XX_GPIO0_IRQ + i)); } =20 + /* SMBus modules. Cannot fail. */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_smbus_addr) !=3D ARRAY_SIZE(s->sm= bus)); + for (i =3D 0; i < ARRAY_SIZE(s->smbus); i++) { + Object *obj =3D OBJECT(&s->smbus[i]); + + sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_smbus_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, + npcm7xx_irq(s, NPCM7XX_SMBUS0_IRQ + i)); + } + /* USB Host */ object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true, &error_abort); @@ -576,22 +628,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **= errp) create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * = KiB); create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * = KiB); create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * = KiB); - create_unimplemented_device("npcm7xx.smbus[0]", 0xf0080000, 4 * = KiB); - create_unimplemented_device("npcm7xx.smbus[1]", 0xf0081000, 4 * = KiB); - create_unimplemented_device("npcm7xx.smbus[2]", 0xf0082000, 4 * = KiB); - create_unimplemented_device("npcm7xx.smbus[3]", 0xf0083000, 4 * = KiB); - create_unimplemented_device("npcm7xx.smbus[4]", 0xf0084000, 4 * = KiB); - create_unimplemented_device("npcm7xx.smbus[5]", 0xf0085000, 4 * = KiB); - create_unimplemented_device("npcm7xx.smbus[6]", 0xf0086000, 4 * = KiB); - create_unimplemented_device("npcm7xx.smbus[7]", 0xf0087000, 4 * = KiB); - create_unimplemented_device("npcm7xx.smbus[8]", 0xf0088000, 4 * = KiB); - create_unimplemented_device("npcm7xx.smbus[9]", 0xf0089000, 4 * = KiB); - create_unimplemented_device("npcm7xx.smbus[10]", 0xf008a000, 4 * = KiB); - create_unimplemented_device("npcm7xx.smbus[11]", 0xf008b000, 4 * = KiB); - create_unimplemented_device("npcm7xx.smbus[12]", 0xf008c000, 4 * = KiB); - create_unimplemented_device("npcm7xx.smbus[13]", 0xf008d000, 4 * = KiB); - create_unimplemented_device("npcm7xx.smbus[14]", 0xf008e000, 4 * = KiB); - create_unimplemented_device("npcm7xx.smbus[15]", 0xf008f000, 4 * = KiB); create_unimplemented_device("npcm7xx.espi", 0xf009f000, 4 * = KiB); create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * = KiB); create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * = KiB); diff --git a/hw/i2c/npcm7xx_smbus.c b/hw/i2c/npcm7xx_smbus.c new file mode 100644 index 00000000000..a465740623f --- /dev/null +++ b/hw/i2c/npcm7xx_smbus.c @@ -0,0 +1,783 @@ +/* + * Nuvoton NPCM7xx SMBus Module. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" + +#include "hw/i2c/npcm7xx_smbus.h" +#include "migration/vmstate.h" +#include "qemu/bitops.h" +#include "qemu/guest-random.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/units.h" + +#include "trace.h" + +enum NPCM7xxSMBusCommonRegister { + NPCM7XX_SMB_SDA =3D 0x0, + NPCM7XX_SMB_ST =3D 0x2, + NPCM7XX_SMB_CST =3D 0x4, + NPCM7XX_SMB_CTL1 =3D 0x6, + NPCM7XX_SMB_ADDR1 =3D 0x8, + NPCM7XX_SMB_CTL2 =3D 0xa, + NPCM7XX_SMB_ADDR2 =3D 0xc, + NPCM7XX_SMB_CTL3 =3D 0xe, + NPCM7XX_SMB_CST2 =3D 0x18, + NPCM7XX_SMB_CST3 =3D 0x19, + NPCM7XX_SMB_VER =3D 0x1f, +}; + +enum NPCM7xxSMBusBank0Register { + NPCM7XX_SMB_ADDR3 =3D 0x10, + NPCM7XX_SMB_ADDR7 =3D 0x11, + NPCM7XX_SMB_ADDR4 =3D 0x12, + NPCM7XX_SMB_ADDR8 =3D 0x13, + NPCM7XX_SMB_ADDR5 =3D 0x14, + NPCM7XX_SMB_ADDR9 =3D 0x15, + NPCM7XX_SMB_ADDR6 =3D 0x16, + NPCM7XX_SMB_ADDR10 =3D 0x17, + NPCM7XX_SMB_CTL4 =3D 0x1a, + NPCM7XX_SMB_CTL5 =3D 0x1b, + NPCM7XX_SMB_SCLLT =3D 0x1c, + NPCM7XX_SMB_FIF_CTL =3D 0x1d, + NPCM7XX_SMB_SCLHT =3D 0x1e, +}; + +enum NPCM7xxSMBusBank1Register { + NPCM7XX_SMB_FIF_CTS =3D 0x10, + NPCM7XX_SMB_FAIR_PER =3D 0x11, + NPCM7XX_SMB_TXF_CTL =3D 0x12, + NPCM7XX_SMB_T_OUT =3D 0x14, + NPCM7XX_SMB_TXF_STS =3D 0x1a, + NPCM7XX_SMB_RXF_STS =3D 0x1c, + NPCM7XX_SMB_RXF_CTL =3D 0x1e, +}; + +/* ST fields */ +#define NPCM7XX_SMBST_STP BIT(7) +#define NPCM7XX_SMBST_SDAST BIT(6) +#define NPCM7XX_SMBST_BER BIT(5) +#define NPCM7XX_SMBST_NEGACK BIT(4) +#define NPCM7XX_SMBST_STASTR BIT(3) +#define NPCM7XX_SMBST_NMATCH BIT(2) +#define NPCM7XX_SMBST_MODE BIT(1) +#define NPCM7XX_SMBST_XMIT BIT(0) + +/* CST fields */ +#define NPCM7XX_SMBCST_ARPMATCH BIT(7) +#define NPCM7XX_SMBCST_MATCHAF BIT(6) +#define NPCM7XX_SMBCST_TGSCL BIT(5) +#define NPCM7XX_SMBCST_TSDA BIT(4) +#define NPCM7XX_SMBCST_GCMATCH BIT(3) +#define NPCM7XX_SMBCST_MATCH BIT(2) +#define NPCM7XX_SMBCST_BB BIT(1) +#define NPCM7XX_SMBCST_BUSY BIT(0) + +/* CST2 fields */ +#define NPCM7XX_SMBCST2_INTSTS BIT(7) +#define NPCM7XX_SMBCST2_MATCH7F BIT(6) +#define NPCM7XX_SMBCST2_MATCH6F BIT(5) +#define NPCM7XX_SMBCST2_MATCH5F BIT(4) +#define NPCM7XX_SMBCST2_MATCH4F BIT(3) +#define NPCM7XX_SMBCST2_MATCH3F BIT(2) +#define NPCM7XX_SMBCST2_MATCH2F BIT(1) +#define NPCM7XX_SMBCST2_MATCH1F BIT(0) + +/* CST3 fields */ +#define NPCM7XX_SMBCST3_EO_BUSY BIT(7) +#define NPCM7XX_SMBCST3_MATCH10F BIT(2) +#define NPCM7XX_SMBCST3_MATCH9F BIT(1) +#define NPCM7XX_SMBCST3_MATCH8F BIT(0) + +/* CTL1 fields */ +#define NPCM7XX_SMBCTL1_STASTRE BIT(7) +#define NPCM7XX_SMBCTL1_NMINTE BIT(6) +#define NPCM7XX_SMBCTL1_GCMEN BIT(5) +#define NPCM7XX_SMBCTL1_ACK BIT(4) +#define NPCM7XX_SMBCTL1_EOBINTE BIT(3) +#define NPCM7XX_SMBCTL1_INTEN BIT(2) +#define NPCM7XX_SMBCTL1_STOP BIT(1) +#define NPCM7XX_SMBCTL1_START BIT(0) + +/* CTL2 fields */ +#define NPCM7XX_SMBCTL2_SCLFRQ(rv) extract8((rv), 1, 6) +#define NPCM7XX_SMBCTL2_ENABLE BIT(0) + +/* CTL3 fields */ +#define NPCM7XX_SMBCTL3_SCL_LVL BIT(7) +#define NPCM7XX_SMBCTL3_SDA_LVL BIT(6) +#define NPCM7XX_SMBCTL3_BNK_SEL BIT(5) +#define NPCM7XX_SMBCTL3_400K_MODE BIT(4) +#define NPCM7XX_SMBCTL3_IDL_START BIT(3) +#define NPCM7XX_SMBCTL3_ARPMEN BIT(2) +#define NPCM7XX_SMBCTL3_SCLFRQ(rv) extract8((rv), 0, 2) + +/* ADDR fields */ +#define NPCM7XX_ADDR_EN BIT(7) +#define NPCM7XX_ADDR_A(rv) extract8((rv), 0, 6) + +#define KEEP_OLD_BIT(o, n, b) (((n) & (~(b))) | ((o) & (b))) +#define WRITE_ONE_CLEAR(o, n, b) ((n) & (b) ? (o) & (~(b)) : (o)) + +#define NPCM7XX_SMBUS_ENABLED(s) ((s)->ctl2 & NPCM7XX_SMBCTL2_ENABLE) + +/* VERSION fields values, read-only. */ +#define NPCM7XX_SMBUS_VERSION_NUMBER 1 +#define NPCM7XX_SMBUS_VERSION_FIFO_SUPPORTED 0 + +/* Reset values */ +#define NPCM7XX_SMB_ST_INIT_VAL 0x00 +#define NPCM7XX_SMB_CST_INIT_VAL 0x10 +#define NPCM7XX_SMB_CST2_INIT_VAL 0x00 +#define NPCM7XX_SMB_CST3_INIT_VAL 0x00 +#define NPCM7XX_SMB_CTL1_INIT_VAL 0x00 +#define NPCM7XX_SMB_CTL2_INIT_VAL 0x00 +#define NPCM7XX_SMB_CTL3_INIT_VAL 0xc0 +#define NPCM7XX_SMB_CTL4_INIT_VAL 0x07 +#define NPCM7XX_SMB_CTL5_INIT_VAL 0x00 +#define NPCM7XX_SMB_ADDR_INIT_VAL 0x00 +#define NPCM7XX_SMB_SCLLT_INIT_VAL 0x00 +#define NPCM7XX_SMB_SCLHT_INIT_VAL 0x00 + +static uint8_t npcm7xx_smbus_get_version(void) +{ + return NPCM7XX_SMBUS_VERSION_FIFO_SUPPORTED << 7 | + NPCM7XX_SMBUS_VERSION_NUMBER; +} + +static void npcm7xx_smbus_update_irq(NPCM7xxSMBusState *s) +{ + int level; + + if (s->ctl1 & NPCM7XX_SMBCTL1_INTEN) { + level =3D !!((s->ctl1 & NPCM7XX_SMBCTL1_NMINTE && + s->st & NPCM7XX_SMBST_NMATCH) || + (s->st & NPCM7XX_SMBST_BER) || + (s->st & NPCM7XX_SMBST_NEGACK) || + (s->st & NPCM7XX_SMBST_SDAST) || + (s->ctl1 & NPCM7XX_SMBCTL1_STASTRE && + s->st & NPCM7XX_SMBST_SDAST) || + (s->ctl1 & NPCM7XX_SMBCTL1_EOBINTE && + s->cst3 & NPCM7XX_SMBCST3_EO_BUSY)); + + if (level) { + s->cst2 |=3D NPCM7XX_SMBCST2_INTSTS; + } else { + s->cst2 &=3D ~NPCM7XX_SMBCST2_INTSTS; + } + qemu_set_irq(s->irq, level); + } +} + +static void npcm7xx_smbus_nack(NPCM7xxSMBusState *s) +{ + s->st &=3D ~NPCM7XX_SMBST_SDAST; + s->st |=3D NPCM7XX_SMBST_NEGACK; + s->status =3D NPCM7XX_SMBUS_STATUS_NEGACK; +} + +static void npcm7xx_smbus_send_byte(NPCM7xxSMBusState *s, uint8_t value) +{ + int rv =3D i2c_send(s->bus, value); + + if (rv) { + npcm7xx_smbus_nack(s); + } else { + s->st |=3D NPCM7XX_SMBST_SDAST; + } + trace_npcm7xx_smbus_send_byte((DEVICE(s)->canonical_path), value, !rv); + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_recv_byte(NPCM7xxSMBusState *s) +{ + s->sda =3D i2c_recv(s->bus); + s->st |=3D NPCM7XX_SMBST_SDAST; + if (s->st & NPCM7XX_SMBCTL1_ACK) { + trace_npcm7xx_smbus_nack(DEVICE(s)->canonical_path); + i2c_nack(s->bus); + s->st &=3D NPCM7XX_SMBCTL1_ACK; + } + trace_npcm7xx_smbus_recv_byte((DEVICE(s)->canonical_path), s->sda); + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_start(NPCM7xxSMBusState *s) +{ + /* + * We can start the bus if one of these is true: + * 1. The bus is idle (so we can request it) + * 2. We are the occupier (it's a repeated start condition.) + */ + int available =3D !i2c_bus_busy(s->bus) || + s->status !=3D NPCM7XX_SMBUS_STATUS_IDLE; + + if (available) { + s->st |=3D NPCM7XX_SMBST_MODE | NPCM7XX_SMBST_XMIT | NPCM7XX_SMBST= _SDAST; + s->cst |=3D NPCM7XX_SMBCST_BUSY; + } else { + s->st &=3D ~NPCM7XX_SMBST_MODE; + s->cst &=3D ~NPCM7XX_SMBCST_BUSY; + s->st |=3D NPCM7XX_SMBST_BER; + } + + trace_npcm7xx_smbus_start(DEVICE(s)->canonical_path, available); + s->cst |=3D NPCM7XX_SMBCST_BB; + s->status =3D NPCM7XX_SMBUS_STATUS_IDLE; + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_send_address(NPCM7xxSMBusState *s, uint8_t value) +{ + int recv; + int rv; + + recv =3D value & BIT(0); + rv =3D i2c_start_transfer(s->bus, value >> 1, recv); + trace_npcm7xx_smbus_send_address(DEVICE(s)->canonical_path, + value >> 1, recv, !rv); + if (rv) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: requesting i2c bus for 0x%02x failed: %d\n", + DEVICE(s)->canonical_path, value, rv); + /* Failed to start transfer. NACK to reject.*/ + if (recv) { + s->st &=3D ~NPCM7XX_SMBST_XMIT; + } else { + s->st |=3D NPCM7XX_SMBST_XMIT; + } + npcm7xx_smbus_nack(s); + npcm7xx_smbus_update_irq(s); + return; + } + + s->st &=3D ~NPCM7XX_SMBST_NEGACK; + if (recv) { + s->status =3D NPCM7XX_SMBUS_STATUS_RECEIVING; + s->st &=3D ~NPCM7XX_SMBST_XMIT; + } else { + s->status =3D NPCM7XX_SMBUS_STATUS_SENDING; + s->st |=3D NPCM7XX_SMBST_XMIT; + } + + if (s->ctl1 & NPCM7XX_SMBCTL1_STASTRE) { + s->st |=3D NPCM7XX_SMBST_STASTR; + if (!recv) { + s->st |=3D NPCM7XX_SMBST_SDAST; + } + } else if (recv) { + npcm7xx_smbus_recv_byte(s); + } + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_execute_stop(NPCM7xxSMBusState *s) +{ + i2c_end_transfer(s->bus); + s->st =3D 0; + s->cst =3D 0; + s->status =3D NPCM7XX_SMBUS_STATUS_IDLE; + s->cst3 |=3D NPCM7XX_SMBCST3_EO_BUSY; + trace_npcm7xx_smbus_stop(DEVICE(s)->canonical_path); + npcm7xx_smbus_update_irq(s); +} + + +static void npcm7xx_smbus_stop(NPCM7xxSMBusState *s) +{ + if (s->st & NPCM7XX_SMBST_MODE) { + switch (s->status) { + case NPCM7XX_SMBUS_STATUS_RECEIVING: + case NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE: + s->status =3D NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE; + break; + + case NPCM7XX_SMBUS_STATUS_NEGACK: + s->status =3D NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK; + break; + + default: + npcm7xx_smbus_execute_stop(s); + break; + } + } +} + +static uint8_t npcm7xx_smbus_read_sda(NPCM7xxSMBusState *s) +{ + uint8_t value =3D s->sda; + + switch (s->status) { + case NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE: + npcm7xx_smbus_execute_stop(s); + break; + + case NPCM7XX_SMBUS_STATUS_RECEIVING: + npcm7xx_smbus_recv_byte(s); + break; + + default: + /* Do nothing */ + break; + } + + return value; +} + +static void npcm7xx_smbus_write_sda(NPCM7xxSMBusState *s, uint8_t value) +{ + s->sda =3D value; + if (s->st & NPCM7XX_SMBST_MODE) { + switch (s->status) { + case NPCM7XX_SMBUS_STATUS_IDLE: + npcm7xx_smbus_send_address(s, value); + break; + case NPCM7XX_SMBUS_STATUS_SENDING: + npcm7xx_smbus_send_byte(s, value); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to SDA in invalid status %d: %u\n", + DEVICE(s)->canonical_path, s->status, value); + break; + } + } +} + +static void npcm7xx_smbus_write_st(NPCM7xxSMBusState *s, uint8_t value) +{ + s->st =3D WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_STP); + s->st =3D WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_BER); + s->st =3D WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_STASTR); + s->st =3D WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_NMATCH); + + if (value & NPCM7XX_SMBST_NEGACK) { + s->st &=3D ~NPCM7XX_SMBST_NEGACK; + if (s->status =3D=3D NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK) { + npcm7xx_smbus_execute_stop(s); + } + } + + if (value & NPCM7XX_SMBST_STASTR && + s->status =3D=3D NPCM7XX_SMBUS_STATUS_RECEIVING) { + npcm7xx_smbus_recv_byte(s); + } + + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_write_cst(NPCM7xxSMBusState *s, uint8_t value) +{ + uint8_t new_value =3D s->cst; + + s->cst =3D WRITE_ONE_CLEAR(new_value, value, NPCM7XX_SMBCST_BB); + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_write_cst3(NPCM7xxSMBusState *s, uint8_t value) +{ + s->cst3 =3D WRITE_ONE_CLEAR(s->cst3, value, NPCM7XX_SMBCST3_EO_BUSY); + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_write_ctl1(NPCM7xxSMBusState *s, uint8_t value) +{ + s->ctl1 =3D KEEP_OLD_BIT(s->ctl1, value, + NPCM7XX_SMBCTL1_START | NPCM7XX_SMBCTL1_STOP | NPCM7XX_SMBCTL1= _ACK); + + if (value & NPCM7XX_SMBCTL1_START) { + npcm7xx_smbus_start(s); + } + + if (value & NPCM7XX_SMBCTL1_STOP) { + npcm7xx_smbus_stop(s); + } + + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_write_ctl2(NPCM7xxSMBusState *s, uint8_t value) +{ + s->ctl2 =3D value; + + if (!NPCM7XX_SMBUS_ENABLED(s)) { + /* Disable this SMBus module. */ + s->ctl1 =3D 0; + s->st =3D 0; + s->cst3 =3D s->cst3 & (~NPCM7XX_SMBCST3_EO_BUSY); + s->cst =3D 0; + } +} + +static void npcm7xx_smbus_write_ctl3(NPCM7xxSMBusState *s, uint8_t value) +{ + uint8_t old_ctl3 =3D s->ctl3; + + /* Write to SDA and SCL bits are ignored. */ + s->ctl3 =3D KEEP_OLD_BIT(old_ctl3, value, + NPCM7XX_SMBCTL3_SCL_LVL | NPCM7XX_SMBCTL3_SDA_= LVL); +} + +static uint64_t npcm7xx_smbus_read(void *opaque, hwaddr offset, unsigned s= ize) +{ + NPCM7xxSMBusState *s =3D opaque; + uint64_t value =3D 0; + uint8_t bank =3D s->ctl3 & NPCM7XX_SMBCTL3_BNK_SEL; + + /* The order of the registers are their order in memory. */ + switch (offset) { + case NPCM7XX_SMB_SDA: + value =3D npcm7xx_smbus_read_sda(s); + break; + + case NPCM7XX_SMB_ST: + value =3D s->st; + break; + + case NPCM7XX_SMB_CST: + value =3D s->cst; + break; + + case NPCM7XX_SMB_CTL1: + value =3D s->ctl1; + break; + + case NPCM7XX_SMB_ADDR1: + value =3D s->addr[0]; + break; + + case NPCM7XX_SMB_CTL2: + value =3D s->ctl2; + break; + + case NPCM7XX_SMB_ADDR2: + value =3D s->addr[1]; + break; + + case NPCM7XX_SMB_CTL3: + value =3D s->ctl3; + break; + + case NPCM7XX_SMB_CST2: + value =3D s->cst2; + break; + + case NPCM7XX_SMB_CST3: + value =3D s->cst3; + break; + + case NPCM7XX_SMB_VER: + value =3D npcm7xx_smbus_get_version(); + break; + + /* This register is either invalid or banked at this point. */ + default: + if (bank) { + /* Bank 1 */ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: read from invalid offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + } else { + /* Bank 0 */ + switch (offset) { + case NPCM7XX_SMB_ADDR3: + value =3D s->addr[2]; + break; + + case NPCM7XX_SMB_ADDR7: + value =3D s->addr[6]; + break; + + case NPCM7XX_SMB_ADDR4: + value =3D s->addr[3]; + break; + + case NPCM7XX_SMB_ADDR8: + value =3D s->addr[7]; + break; + + case NPCM7XX_SMB_ADDR5: + value =3D s->addr[4]; + break; + + case NPCM7XX_SMB_ADDR9: + value =3D s->addr[8]; + break; + + case NPCM7XX_SMB_ADDR6: + value =3D s->addr[5]; + break; + + case NPCM7XX_SMB_ADDR10: + value =3D s->addr[9]; + break; + + case NPCM7XX_SMB_CTL4: + value =3D s->ctl4; + break; + + case NPCM7XX_SMB_CTL5: + value =3D s->ctl5; + break; + + case NPCM7XX_SMB_SCLLT: + value =3D s->scllt; + break; + + case NPCM7XX_SMB_SCLHT: + value =3D s->sclht; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: read from invalid offset 0x%" HWADDR_PRIx "\n= ", + DEVICE(s)->canonical_path, offset); + break; + } + } + break; + } + + trace_npcm7xx_smbus_read(DEVICE(s)->canonical_path, offset, value, siz= e); + + return value; +} + +static void npcm7xx_smbus_write(void *opaque, hwaddr offset, uint64_t valu= e, + unsigned size) +{ + NPCM7xxSMBusState *s =3D opaque; + uint8_t bank =3D s->ctl3 & NPCM7XX_SMBCTL3_BNK_SEL; + + trace_npcm7xx_smbus_write(DEVICE(s)->canonical_path, offset, value, si= ze); + + /* The order of the registers are their order in memory. */ + switch (offset) { + case NPCM7XX_SMB_SDA: + npcm7xx_smbus_write_sda(s, value); + break; + + case NPCM7XX_SMB_ST: + npcm7xx_smbus_write_st(s, value); + break; + + case NPCM7XX_SMB_CST: + npcm7xx_smbus_write_cst(s, value); + break; + + case NPCM7XX_SMB_CTL1: + npcm7xx_smbus_write_ctl1(s, value); + break; + + case NPCM7XX_SMB_ADDR1: + s->addr[0] =3D value; + break; + + case NPCM7XX_SMB_CTL2: + npcm7xx_smbus_write_ctl2(s, value); + break; + + case NPCM7XX_SMB_ADDR2: + s->addr[1] =3D value; + break; + + case NPCM7XX_SMB_CTL3: + npcm7xx_smbus_write_ctl3(s, value); + break; + + case NPCM7XX_SMB_CST2: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to read-only reg: offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + break; + + case NPCM7XX_SMB_CST3: + npcm7xx_smbus_write_cst3(s, value); + break; + + case NPCM7XX_SMB_VER: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to read-only reg: offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + break; + + /* This register is either invalid or banked at this point. */ + default: + if (bank) { + /* Bank 1 */ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + } else { + /* Bank 0 */ + switch (offset) { + case NPCM7XX_SMB_ADDR3: + s->addr[2] =3D value; + break; + + case NPCM7XX_SMB_ADDR7: + s->addr[6] =3D value; + break; + + case NPCM7XX_SMB_ADDR4: + s->addr[3] =3D value; + break; + + case NPCM7XX_SMB_ADDR8: + s->addr[7] =3D value; + break; + + case NPCM7XX_SMB_ADDR5: + s->addr[4] =3D value; + break; + + case NPCM7XX_SMB_ADDR9: + s->addr[8] =3D value; + break; + + case NPCM7XX_SMB_ADDR6: + s->addr[5] =3D value; + break; + + case NPCM7XX_SMB_ADDR10: + s->addr[9] =3D value; + break; + + case NPCM7XX_SMB_CTL4: + s->ctl4 =3D value; + break; + + case NPCM7XX_SMB_CTL5: + s->ctl5 =3D value; + break; + + case NPCM7XX_SMB_SCLLT: + s->scllt =3D value; + break; + + case NPCM7XX_SMB_SCLHT: + s->sclht =3D value; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + break; + } + } + break; + } +} + +static const MemoryRegionOps npcm7xx_smbus_ops =3D { + .read =3D npcm7xx_smbus_read, + .write =3D npcm7xx_smbus_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + .unaligned =3D false, + }, +}; + +static void npcm7xx_smbus_enter_reset(Object *obj, ResetType type) +{ + NPCM7xxSMBusState *s =3D NPCM7XX_SMBUS(obj); + + s->st =3D NPCM7XX_SMB_ST_INIT_VAL; + s->cst =3D NPCM7XX_SMB_CST_INIT_VAL; + s->cst2 =3D NPCM7XX_SMB_CST2_INIT_VAL; + s->cst3 =3D NPCM7XX_SMB_CST3_INIT_VAL; + s->ctl1 =3D NPCM7XX_SMB_CTL1_INIT_VAL; + s->ctl2 =3D NPCM7XX_SMB_CTL2_INIT_VAL; + s->ctl3 =3D NPCM7XX_SMB_CTL3_INIT_VAL; + s->ctl4 =3D NPCM7XX_SMB_CTL4_INIT_VAL; + s->ctl5 =3D NPCM7XX_SMB_CTL5_INIT_VAL; + + for (int i =3D 0; i < NPCM7XX_SMBUS_NR_ADDRS; ++i) { + s->addr[i] =3D NPCM7XX_SMB_ADDR_INIT_VAL; + } + s->scllt =3D NPCM7XX_SMB_SCLLT_INIT_VAL; + s->sclht =3D NPCM7XX_SMB_SCLHT_INIT_VAL; + + s->status =3D NPCM7XX_SMBUS_STATUS_IDLE; +} + +static void npcm7xx_smbus_hold_reset(Object *obj) +{ + NPCM7xxSMBusState *s =3D NPCM7XX_SMBUS(obj); + + qemu_irq_lower(s->irq); +} + +static void npcm7xx_smbus_init(Object *obj) +{ + NPCM7xxSMBusState *s =3D NPCM7XX_SMBUS(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + sysbus_init_irq(sbd, &s->irq); + memory_region_init_io(&s->iomem, obj, &npcm7xx_smbus_ops, s, + "regs", 4 * KiB); + sysbus_init_mmio(sbd, &s->iomem); + + s->bus =3D i2c_init_bus(DEVICE(s), "i2c-bus"); + s->status =3D NPCM7XX_SMBUS_STATUS_IDLE; +} + +static const VMStateDescription vmstate_npcm7xx_smbus =3D { + .name =3D "npcm7xx-smbus", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8(sda, NPCM7xxSMBusState), + VMSTATE_UINT8(st, NPCM7xxSMBusState), + VMSTATE_UINT8(cst, NPCM7xxSMBusState), + VMSTATE_UINT8(cst2, NPCM7xxSMBusState), + VMSTATE_UINT8(cst3, NPCM7xxSMBusState), + VMSTATE_UINT8(ctl1, NPCM7xxSMBusState), + VMSTATE_UINT8(ctl2, NPCM7xxSMBusState), + VMSTATE_UINT8(ctl3, NPCM7xxSMBusState), + VMSTATE_UINT8(ctl4, NPCM7xxSMBusState), + VMSTATE_UINT8(ctl5, NPCM7xxSMBusState), + VMSTATE_UINT8_ARRAY(addr, NPCM7xxSMBusState, NPCM7XX_SMBUS_NR_ADDR= S), + VMSTATE_UINT8(scllt, NPCM7xxSMBusState), + VMSTATE_UINT8(sclht, NPCM7xxSMBusState), + VMSTATE_END_OF_LIST(), + }, +}; + +static void npcm7xx_smbus_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "NPCM7xx System Management Bus"; + dc->vmsd =3D &vmstate_npcm7xx_smbus; + rc->phases.enter =3D npcm7xx_smbus_enter_reset; + rc->phases.hold =3D npcm7xx_smbus_hold_reset; +} + +static const TypeInfo npcm7xx_smbus_types[] =3D { + { + .name =3D TYPE_NPCM7XX_SMBUS, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NPCM7xxSMBusState), + .class_init =3D npcm7xx_smbus_class_init, + .instance_init =3D npcm7xx_smbus_init, + }, +}; +DEFINE_TYPES(npcm7xx_smbus_types); diff --git a/hw/i2c/meson.build b/hw/i2c/meson.build index 3a511539ad2..cdcd694a7fb 100644 --- a/hw/i2c/meson.build +++ b/hw/i2c/meson.build @@ -9,6 +9,7 @@ i2c_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos42= 10_i2c.c')) i2c_ss.add(when: 'CONFIG_IMX_I2C', if_true: files('imx_i2c.c')) i2c_ss.add(when: 'CONFIG_MPC_I2C', if_true: files('mpc_i2c.c')) i2c_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('microbit_i2c.c')) +i2c_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_smbus.c')) i2c_ss.add(when: 'CONFIG_SMBUS_EEPROM', if_true: files('smbus_eeprom.c')) i2c_ss.add(when: 'CONFIG_VERSATILE_I2C', if_true: files('versatile_i2c.c')) i2c_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_i2c.c')) diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events index 08db8fa6892..c3bb70ad045 100644 --- a/hw/i2c/trace-events +++ b/hw/i2c/trace-events @@ -14,3 +14,14 @@ aspeed_i2c_bus_read(uint32_t busid, uint64_t offset, uns= igned size, uint64_t val aspeed_i2c_bus_write(uint32_t busid, uint64_t offset, unsigned size, uint6= 4_t value) "bus[%d]: To 0x%" PRIx64 " of size %u: 0x%" PRIx64 aspeed_i2c_bus_send(const char *mode, int i, int count, uint8_t byte) "%s = send %d/%d 0x%02x" aspeed_i2c_bus_recv(const char *mode, int i, int count, uint8_t byte) "%s = recv %d/%d 0x%02x" + +# npcm7xx_smbus.c + +npcm7xx_smbus_read(const char *id, uint64_t offset, uint64_t value, unsign= ed size) "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" +npcm7xx_smbus_write(const char *id, uint64_t offset, uint64_t value, unsig= ned size) "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" +npcm7xx_smbus_start(const char *id, int success) "%s starting, success: %d" +npcm7xx_smbus_send_address(const char *id, uint8_t addr, int recv, int suc= cess) "%s sending address: 0x%02x, recv: %d, success: %d" +npcm7xx_smbus_send_byte(const char *id, uint8_t value, int success) "%s se= nd byte: 0x%02x, success: %d" +npcm7xx_smbus_recv_byte(const char *id, uint8_t value) "%s recv byte: 0x%0= 2x" +npcm7xx_smbus_stop(const char *id) "%s stopping" +npcm7xx_smbus_nack(const char *id) "%s nacking" --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Btazgn6Y5qOJThEGpbN02VT8W+WTRqqeVzuGqS4pkq4=; b=BjRZymBBtatqlwFC74+hFiPlNrd+PcGe/VT7oDFnQsaNSmm2uroAaHvWekMfgWzeWP qbFtB24rbyle57rdPxnB84OsRWtGOKz5gVvJhmM3obH7lEUKIOG2aAR4bsN4TOcTSIo4 l4G5gwhBOZW92MX8j6/lLiZgfB7wwAy35Jgn90GP7lsS22fdg17XNQOsfFMsgMRgMyAv VWrYlLR6ETBLr7LWc65vBZMBNgzlidNoRA93NIYYLEvqTUhO3ue95v0aBE4bpLimbow/ UIsj00sVagjvHCTKgG2DgcmnRbGFoyqVFngBs/JuKG2YQU4VvOsN83/XxfuvUG51MfVK qslg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Btazgn6Y5qOJThEGpbN02VT8W+WTRqqeVzuGqS4pkq4=; b=JxWemZPe/y4OPu+jKqVTWZ7aDPxccNgQ7cgt0N8yY5mK7tz4vsoZfhvGqWSH9LAH5N 38bbQrCeDDk1oeO4GgShiNKtU7ol0yRtClAIolan/+oBEJLAbbHMdMuHraFy5FXW74f8 akaZpiMSus6Sl2y0s+himqKpGwlR+ZMG4kPtsjT0omphiwbUPJicWdTbnWbHQSgG3/De aDJExZFM72PTq8veuGcy7EJNXyOO2Fh2TZ4ymGP4lJUS8LTWn7l7IfC09z298+9IxFD3 MzXDh6i6rGUl4kqTu6FcXJLMJ8yon85NL+cGdYgYhqsDFCj/oweEDxnh2mZvbHRUPv4+ jTqw== X-Gm-Message-State: AOAM532EXBn6uT8dAdS4vLQdydIReOKg2aG7fiCPLilhGknFtTAcGaNN Q2Me8S48ovToxBgRhMzrnLfXTYQul9n2rQ== X-Google-Smtp-Source: ABdhPJztYQJD5E8HWiqeLlIaL2Dbzw5ZlG0v0iVgrKDrtBOm+JMO69uo8Gs72+13BMwwT9ykP2b2Gg== X-Received: by 2002:a5d:6881:: with SMTP id h1mr24260349wru.384.1613492244145; Tue, 16 Feb 2021 08:17:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/40] hw/arm: Add I2C sensors for NPCM750 eval board Date: Tue, 16 Feb 2021 16:16:51 +0000 Message-Id: <20210216161658.29881-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Hao Wu Add I2C temperature sensors for NPCM750 eval board. Reviewed-by: Doug Evans Reviewed-by: Tyrong Ting Signed-off-by: Hao Wu Reviewed-by: Peter Maydell Message-id: 20210210220426.3577804-3-wuhaotsh@google.com Signed-off-by: Peter Maydell --- hw/arm/npcm7xx_boards.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 3fdd5cab01d..47a215bd015 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -98,6 +98,24 @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *ma= chine, return NPCM7XX(obj); } =20 +static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, uint32_t num) +{ + g_assert(num < ARRAY_SIZE(soc->smbus)); + return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus")= ); +} + +static void npcm750_evb_i2c_init(NPCM7xxState *soc) +{ + /* lm75 temperature sensor on SVB, tmp105 is compatible */ + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 0), "tmp105", 0x48); + /* lm75 temperature sensor on EB, tmp105 is compatible */ + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x48); + /* tmp100 temperature sensor on EB, tmp105 is compatible */ + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x48); + /* tmp100 temperature sensor on SVB, tmp105 is compatible */ + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), "tmp105", 0x48); +} + static void npcm750_evb_init(MachineState *machine) { NPCM7xxState *soc; @@ -108,6 +126,7 @@ static void npcm750_evb_init(MachineState *machine) =20 npcm7xx_load_bootrom(machine, soc); npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0,= 0)); + npcm750_evb_i2c_init(soc); npcm7xx_load_kernel(machine, soc); } =20 --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613493652; cv=none; d=zohomail.com; s=zohoarc; b=iBJ0q7ca3+t1dnH3zKzClxmIUjquVvv1P9MfNY/0GcqX/GG0DaJZdNrhyBmi6p/zGPzaiiwLndnPAawwRT7NMdtXvSY8Ovi9CZ3BFUj1bRZRZL+mO0oR3OmlLztSPBvZAUy7s6HSIrgc0ZmADYREuw2ta7Qs+fKE8uWrSScpqH8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613493652; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0UrAqxs2CL5jokH0yLA3JrB6tz+n6Z0MaeUkxlhcczE=; b=IFY76CUchF5wCTXvgH6/f64IbDhepzmMRWJRrGHXN+f2bGjkn3kwSyAQ+rAFIQlhjeRa9968RDK6I8qowNMhgewV4iLIizBXoxWzzZBQ1C1ZzDBDg08GIvMMsnkJGuvaJiy5Cy1siY2sAWc5KTEX0ZSsZaJqI/4spW0SZ0YTK9o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613493651600280.6807838999289; Tue, 16 Feb 2021 08:40:51 -0800 (PST) Received: from localhost ([::1]:58724 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3P7-0000FN-DA for importer@patchew.org; Tue, 16 Feb 2021 11:40:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40852) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC33D-0000H1-Uv for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:13 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:40443) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32U-0002XO-Ce for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:09 -0500 Received: by mail-wr1-x42b.google.com with SMTP id v14so13773608wro.7 for ; Tue, 16 Feb 2021 08:17:25 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0UrAqxs2CL5jokH0yLA3JrB6tz+n6Z0MaeUkxlhcczE=; b=L64zyvdwvDOnH5Se4CNDj6I7lec/kyDnch2e/M1oukXU+uyJIwIuuPXgj1mMs2qspK bLSJ8eYr3Dl9A5ZbnpHmFw0p/vKrvX+V2vNNawIXdr/CU+lIVPh6vi6i3MNPtx3qPiPt McwMjmnoQ47PwxvUuWivNi/lKa6VbOKdM6AEAQX9TISkaRudWS/y1662360FGm8fquLf X4/+p+oAZ6EVn1a0QkWPqH9uO2afjrEgUOuRV2O8K0y1oSjSJZPsqKiEcGBa3hM2tmSt X3zDY8czrZHQy4QC4bcIXhnFT+sRe8lbdR6O/6lEj7bF2H2Iezn5OA5VEQsjOnLb3Zpe 1QLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0UrAqxs2CL5jokH0yLA3JrB6tz+n6Z0MaeUkxlhcczE=; b=rh5AGAsqQV3WyWSCr13DQecLZO2DRhY13CLxo1o1HF207Eooa5fkM6AS3DU5eMK8D9 Bz4T1PBS99aznXKrEu1WkzF1oY9YX1bEpbtDZFcJEDQXfdAIlgMuH3sLDYaepDHJhYIy K7pmFdttEUhpdEhepWKaiL407AOWxk38jfiiGWyEQAK1D/BjZy8LCInaSCled2OZj0Z3 iP7dEbB1tyspVRGLO9Ka6e4OosJaxrYcwIVOV+6MUmvHDNhyi8OVSWCIaIqM33JwBszK A/IjFrDvcyGXAIY23mJycNm84uhjxiTcGqvr79Lt+TAL8lIg4yE5wIX9TKyU2OffdMNO E0Rw== X-Gm-Message-State: AOAM53077EH3S+9yStNVT1jl7ObJ5GVDKyoDbxTK+xUFrRG8g9TvDIRR UCSmLX5wbaaXbDvhKcSOrfak2wB++IlY4g== X-Google-Smtp-Source: ABdhPJytiIuxr/FWY/lkv4WMKYjAt8PVnEtGpz9x6tU1pMKrqp9XlK5FbScyUb/E1yNTdLfM1Dnu9A== X-Received: by 2002:a05:6000:1547:: with SMTP id 7mr24697509wry.301.1613492244903; Tue, 16 Feb 2021 08:17:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/40] hw/arm: Add I2C sensors and EEPROM for GSJ machine Date: Tue, 16 Feb 2021 16:16:52 +0000 Message-Id: <20210216161658.29881-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Hao Wu Add AT24 EEPROM and temperature sensors for GSJ machine. Reviewed-by: Doug Evans Reviewed-by: Tyrong Ting Signed-off-by: Hao Wu Message-id: 20210210220426.3577804-4-wuhaotsh@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/npcm7xx_boards.c | 27 +++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + 2 files changed, 28 insertions(+) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 47a215bd015..fbf6ce8e028 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -19,6 +19,7 @@ #include "exec/address-spaces.h" #include "hw/arm/npcm7xx.h" #include "hw/core/cpu.h" +#include "hw/i2c/smbus_eeprom.h" #include "hw/loader.h" #include "hw/qdev-properties.h" #include "qapi/error.h" @@ -104,6 +105,17 @@ static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, = uint32_t num) return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus")= ); } =20 +static void at24c_eeprom_init(NPCM7xxState *soc, int bus, uint8_t addr, + uint32_t rsize) +{ + I2CBus *i2c_bus =3D npcm7xx_i2c_get_bus(soc, bus); + I2CSlave *i2c_dev =3D i2c_slave_new("at24c-eeprom", addr); + DeviceState *dev =3D DEVICE(i2c_dev); + + qdev_prop_set_uint32(dev, "rom-size", rsize); + i2c_slave_realize_and_unref(i2c_dev, i2c_bus, &error_abort); +} + static void npcm750_evb_i2c_init(NPCM7xxState *soc) { /* lm75 temperature sensor on SVB, tmp105 is compatible */ @@ -116,6 +128,20 @@ static void npcm750_evb_i2c_init(NPCM7xxState *soc) i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), "tmp105", 0x48); } =20 +static void quanta_gsj_i2c_init(NPCM7xxState *soc) +{ + /* GSJ machine have 4 max31725 temperature sensors, tmp105 is compatib= le. */ + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x5c); + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x5c); + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), "tmp105", 0x5c); + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), "tmp105", 0x5c); + + at24c_eeprom_init(soc, 9, 0x55, 8192); + at24c_eeprom_init(soc, 10, 0x55, 8192); + + /* TODO: Add additional i2c devices. */ +} + static void npcm750_evb_init(MachineState *machine) { NPCM7xxState *soc; @@ -141,6 +167,7 @@ static void quanta_gsj_init(MachineState *machine) npcm7xx_load_bootrom(machine, soc); npcm7xx_connect_flash(&soc->fiu[0], 0, "mx25l25635e", drive_get(IF_MTD, 0, 0)); + quanta_gsj_i2c_init(soc); npcm7xx_load_kernel(machine, soc); } =20 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index be017b997ab..4e6f4ffe90c 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -370,6 +370,7 @@ config NPCM7XX bool select A9MPCORE select ARM_GIC + select AT24C # EEPROM select PL310 # cache controller select SERIAL select SSI --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613493824; cv=none; d=zohomail.com; s=zohoarc; b=SNX0f+7EXHmdartrN61R6jRiwq1qanKEyjRiqFTm2p8PFudrMSif8yfkOIcS7QYUAIYLYPLtfcnApqD3qZvEM035AbSKit6el9kP6gxf/Opr4Uh91rfg6VbZ+flHSUGvJslYIM0o+jyukl9KRicT0Nt3kWzyvyEMy29qJc+u8Y4= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=pMI4eDmB1JYAvkmgbr4DP4EX5TPT7dcwmnzdAUEo+A4=; b=w8hoMc9h/R6etYgdIRPfk7jqPCsVoBT6efmjc8X4LuRJsdHrWDSJxoc9y7Yov4Rm/F UzzfiCxombl1ROypcgt9Hh6nubwZ32TvfxU4LkclMxuzTLY5MCJwNi3sfZ1N4mXSV4Fh meaP/rX5EeTYyDr4LVpmQ3ebRgLDAmVPF9RdFaD1g/RuQwfg/BwrC08LiHXIpGLDuJhM yDtFiG+ISd/BTZGRqE8Ra1id/4XDgasBb63wZaPhOkyQJVGnRRyGdPdQmTASjnM5p9TT cJAi/2PNqXHhh0o+VM179W7MlVUGqc2oKo0VBtHZHHCATHP7XNmjwypRvlABkB5G7UcF QhSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pMI4eDmB1JYAvkmgbr4DP4EX5TPT7dcwmnzdAUEo+A4=; b=n4aZI3Ill0UdeVv2oWj4ymEDCziQvno3QfpT/NiLt0QocRHKYQ6tCPgJYM5ynnc9EM H92M3ktlCMeX2SbxLh2+3667cj6PUxxMUtneZxfaglzIGx6stk/vzENRQBZSPYHqmd0N RQm/xsPVWjPzXOIf/mfgc4Yn503Mdy4FdGncH8TnHlPWh9rlGHp/Gl72B3QDVDiahZMx /rThejyKXrSuzvSSSdqq8ZdQB3Lm8Te1S7uAnLd6IMJ3zakUczrE88k06SPTCgonFHSq kx9hVMzQS6ijls5dDi90uZU5IeW14OMnYoM8FrfnLguKErqcHOCorN4LMQA0nhytD5AY B/aw== X-Gm-Message-State: AOAM532PFs5k6gMm9i9K48Z7xi4gKAWCbzLW78dG5dLkXSmK2sIxO6B4 B4hcCWzhj6f+ALZAQuOZQEhLODBNw9E71w== X-Google-Smtp-Source: ABdhPJzDBh7s2BQbngm6BZSMW0pa0OwdCwt+PBS27jhc2oWqOTRQ0IysLpvizmOQIUj/ETU10U4ufw== X-Received: by 2002:a05:600c:4894:: with SMTP id j20mr4029772wmp.152.1613492245782; Tue, 16 Feb 2021 08:17:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/40] hw/i2c: Add a QTest for NPCM7XX SMBus Device Date: Tue, 16 Feb 2021 16:16:53 +0000 Message-Id: <20210216161658.29881-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Hao Wu This patch adds a QTest for NPCM7XX SMBus's single byte mode. It sends a byte to a device in the evaluation board, and verify the retrieved value is equivalent to the sent value. Reviewed-by: Doug Evans Reviewed-by: Tyrong Ting Signed-off-by: Hao Wu Reviewed-by: Peter Maydell Message-id: 20210210220426.3577804-5-wuhaotsh@google.com Signed-off-by: Peter Maydell --- tests/qtest/npcm7xx_smbus-test.c | 352 +++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 2 files changed, 353 insertions(+) create mode 100644 tests/qtest/npcm7xx_smbus-test.c diff --git a/tests/qtest/npcm7xx_smbus-test.c b/tests/qtest/npcm7xx_smbus-t= est.c new file mode 100644 index 00000000000..4594b107df1 --- /dev/null +++ b/tests/qtest/npcm7xx_smbus-test.c @@ -0,0 +1,352 @@ +/* + * QTests for Nuvoton NPCM7xx SMBus Modules. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "libqos/i2c.h" +#include "libqos/libqtest.h" +#include "hw/misc/tmp105_regs.h" + +#define NR_SMBUS_DEVICES 16 +#define SMBUS_ADDR(x) (0xf0080000 + 0x1000 * (x)) +#define SMBUS_IRQ(x) (64 + (x)) + +#define EVB_DEVICE_ADDR 0x48 +#define INVALID_DEVICE_ADDR 0x01 + +const int evb_bus_list[] =3D {0, 1, 2, 6}; + +/* Offsets */ +enum CommonRegister { + OFFSET_SDA =3D 0x0, + OFFSET_ST =3D 0x2, + OFFSET_CST =3D 0x4, + OFFSET_CTL1 =3D 0x6, + OFFSET_ADDR1 =3D 0x8, + OFFSET_CTL2 =3D 0xa, + OFFSET_ADDR2 =3D 0xc, + OFFSET_CTL3 =3D 0xe, + OFFSET_CST2 =3D 0x18, + OFFSET_CST3 =3D 0x19, +}; + +enum NPCM7xxSMBusBank0Register { + OFFSET_ADDR3 =3D 0x10, + OFFSET_ADDR7 =3D 0x11, + OFFSET_ADDR4 =3D 0x12, + OFFSET_ADDR8 =3D 0x13, + OFFSET_ADDR5 =3D 0x14, + OFFSET_ADDR9 =3D 0x15, + OFFSET_ADDR6 =3D 0x16, + OFFSET_ADDR10 =3D 0x17, + OFFSET_CTL4 =3D 0x1a, + OFFSET_CTL5 =3D 0x1b, + OFFSET_SCLLT =3D 0x1c, + OFFSET_FIF_CTL =3D 0x1d, + OFFSET_SCLHT =3D 0x1e, +}; + +enum NPCM7xxSMBusBank1Register { + OFFSET_FIF_CTS =3D 0x10, + OFFSET_FAIR_PER =3D 0x11, + OFFSET_TXF_CTL =3D 0x12, + OFFSET_T_OUT =3D 0x14, + OFFSET_TXF_STS =3D 0x1a, + OFFSET_RXF_STS =3D 0x1c, + OFFSET_RXF_CTL =3D 0x1e, +}; + +/* ST fields */ +#define ST_STP BIT(7) +#define ST_SDAST BIT(6) +#define ST_BER BIT(5) +#define ST_NEGACK BIT(4) +#define ST_STASTR BIT(3) +#define ST_NMATCH BIT(2) +#define ST_MODE BIT(1) +#define ST_XMIT BIT(0) + +/* CST fields */ +#define CST_ARPMATCH BIT(7) +#define CST_MATCHAF BIT(6) +#define CST_TGSCL BIT(5) +#define CST_TSDA BIT(4) +#define CST_GCMATCH BIT(3) +#define CST_MATCH BIT(2) +#define CST_BB BIT(1) +#define CST_BUSY BIT(0) + +/* CST2 fields */ +#define CST2_INSTTS BIT(7) +#define CST2_MATCH7F BIT(6) +#define CST2_MATCH6F BIT(5) +#define CST2_MATCH5F BIT(4) +#define CST2_MATCH4F BIT(3) +#define CST2_MATCH3F BIT(2) +#define CST2_MATCH2F BIT(1) +#define CST2_MATCH1F BIT(0) + +/* CST3 fields */ +#define CST3_EO_BUSY BIT(7) +#define CST3_MATCH10F BIT(2) +#define CST3_MATCH9F BIT(1) +#define CST3_MATCH8F BIT(0) + +/* CTL1 fields */ +#define CTL1_STASTRE BIT(7) +#define CTL1_NMINTE BIT(6) +#define CTL1_GCMEN BIT(5) +#define CTL1_ACK BIT(4) +#define CTL1_EOBINTE BIT(3) +#define CTL1_INTEN BIT(2) +#define CTL1_STOP BIT(1) +#define CTL1_START BIT(0) + +/* CTL2 fields */ +#define CTL2_SCLFRQ(rv) extract8((rv), 1, 6) +#define CTL2_ENABLE BIT(0) + +/* CTL3 fields */ +#define CTL3_SCL_LVL BIT(7) +#define CTL3_SDA_LVL BIT(6) +#define CTL3_BNK_SEL BIT(5) +#define CTL3_400K_MODE BIT(4) +#define CTL3_IDL_START BIT(3) +#define CTL3_ARPMEN BIT(2) +#define CTL3_SCLFRQ(rv) extract8((rv), 0, 2) + +/* ADDR fields */ +#define ADDR_EN BIT(7) +#define ADDR_A(rv) extract8((rv), 0, 6) + + +static void check_running(QTestState *qts, uint64_t base_addr) +{ + g_assert_true(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BUSY); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BB); +} + +static void check_stopped(QTestState *qts, uint64_t base_addr) +{ + uint8_t cst3; + + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), =3D=3D, 0); + g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BUSY); + g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BB); + + cst3 =3D qtest_readb(qts, base_addr + OFFSET_CST3); + g_assert_true(cst3 & CST3_EO_BUSY); + qtest_writeb(qts, base_addr + OFFSET_CST3, cst3); + cst3 =3D qtest_readb(qts, base_addr + OFFSET_CST3); + g_assert_false(cst3 & CST3_EO_BUSY); +} + +static void enable_bus(QTestState *qts, uint64_t base_addr) +{ + uint8_t ctl2 =3D qtest_readb(qts, base_addr + OFFSET_CTL2); + + ctl2 |=3D CTL2_ENABLE; + qtest_writeb(qts, base_addr + OFFSET_CTL2, ctl2); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_CTL2) & CTL2_ENABLE); +} + +static void disable_bus(QTestState *qts, uint64_t base_addr) +{ + uint8_t ctl2 =3D qtest_readb(qts, base_addr + OFFSET_CTL2); + + ctl2 &=3D ~CTL2_ENABLE; + qtest_writeb(qts, base_addr + OFFSET_CTL2, ctl2); + g_assert_false(qtest_readb(qts, base_addr + OFFSET_CTL2) & CTL2_ENABLE= ); +} + +static void start_transfer(QTestState *qts, uint64_t base_addr) +{ + uint8_t ctl1; + + ctl1 =3D CTL1_START | CTL1_INTEN | CTL1_STASTRE; + qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_CTL1), =3D=3D, + CTL1_INTEN | CTL1_STASTRE | CTL1_INTEN); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), =3D=3D, + ST_MODE | ST_XMIT | ST_SDAST); + check_running(qts, base_addr); +} + +static void stop_transfer(QTestState *qts, uint64_t base_addr) +{ + uint8_t ctl1 =3D qtest_readb(qts, base_addr + OFFSET_CTL1); + + ctl1 &=3D ~(CTL1_START | CTL1_ACK); + ctl1 |=3D CTL1_STOP | CTL1_INTEN | CTL1_EOBINTE; + qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); + ctl1 =3D qtest_readb(qts, base_addr + OFFSET_CTL1); + g_assert_false(ctl1 & CTL1_STOP); +} + +static void send_byte(QTestState *qts, uint64_t base_addr, uint8_t byte) +{ + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), =3D=3D, + ST_MODE | ST_XMIT | ST_SDAST); + qtest_writeb(qts, base_addr + OFFSET_SDA, byte); +} + +static uint8_t recv_byte(QTestState *qts, uint64_t base_addr) +{ + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), =3D=3D, + ST_MODE | ST_SDAST); + return qtest_readb(qts, base_addr + OFFSET_SDA); +} + +static void send_address(QTestState *qts, uint64_t base_addr, uint8_t addr, + bool recv, bool valid) +{ + uint8_t encoded_addr =3D (addr << 1) | (recv ? 1 : 0); + uint8_t st; + + qtest_writeb(qts, base_addr + OFFSET_SDA, encoded_addr); + st =3D qtest_readb(qts, base_addr + OFFSET_ST); + + if (valid) { + if (recv) { + g_assert_cmphex(st, =3D=3D, ST_MODE | ST_SDAST | ST_STASTR); + } else { + g_assert_cmphex(st, =3D=3D, ST_MODE | ST_XMIT | ST_SDAST | ST_= STASTR); + } + + qtest_writeb(qts, base_addr + OFFSET_ST, ST_STASTR); + st =3D qtest_readb(qts, base_addr + OFFSET_ST); + if (recv) { + g_assert_cmphex(st, =3D=3D, ST_MODE | ST_SDAST); + } else { + g_assert_cmphex(st, =3D=3D, ST_MODE | ST_XMIT | ST_SDAST); + } + } else { + if (recv) { + g_assert_cmphex(st, =3D=3D, ST_MODE | ST_NEGACK); + } else { + g_assert_cmphex(st, =3D=3D, ST_MODE | ST_XMIT | ST_NEGACK); + } + } +} + +static void send_nack(QTestState *qts, uint64_t base_addr) +{ + uint8_t ctl1 =3D qtest_readb(qts, base_addr + OFFSET_CTL1); + + ctl1 &=3D ~(CTL1_START | CTL1_STOP); + ctl1 |=3D CTL1_ACK | CTL1_INTEN; + qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); +} + +/* Check the SMBus's status is set correctly when disabled. */ +static void test_disable_bus(gconstpointer data) +{ + intptr_t index =3D (intptr_t)data; + uint64_t base_addr =3D SMBUS_ADDR(index); + QTestState *qts =3D qtest_init("-machine npcm750-evb"); + + disable_bus(qts, base_addr); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_CTL1), =3D=3D, 0); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), =3D=3D, 0); + g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST3) & CST3_EO_BUS= Y); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_CST), =3D=3D, 0); + qtest_quit(qts); +} + +/* Check the SMBus returns a NACK for an invalid address. */ +static void test_invalid_addr(gconstpointer data) +{ + intptr_t index =3D (intptr_t)data; + uint64_t base_addr =3D SMBUS_ADDR(index); + int irq =3D SMBUS_IRQ(index); + QTestState *qts =3D qtest_init("-machine npcm750-evb"); + + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + enable_bus(qts, base_addr); + g_assert_false(qtest_get_irq(qts, irq)); + start_transfer(qts, base_addr); + send_address(qts, base_addr, INVALID_DEVICE_ADDR, false, false); + g_assert_true(qtest_get_irq(qts, irq)); + stop_transfer(qts, base_addr); + check_running(qts, base_addr); + qtest_writeb(qts, base_addr + OFFSET_ST, ST_NEGACK); + g_assert_false(qtest_readb(qts, base_addr + OFFSET_ST) & ST_NEGACK); + check_stopped(qts, base_addr); + qtest_quit(qts); +} + +/* Check the SMBus can send and receive bytes to a device in single mode. = */ +static void test_single_mode(gconstpointer data) +{ + intptr_t index =3D (intptr_t)data; + uint64_t base_addr =3D SMBUS_ADDR(index); + int irq =3D SMBUS_IRQ(index); + uint8_t value =3D 0x60; + QTestState *qts =3D qtest_init("-machine npcm750-evb"); + + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + enable_bus(qts, base_addr); + + /* Sending */ + g_assert_false(qtest_get_irq(qts, irq)); + start_transfer(qts, base_addr); + g_assert_true(qtest_get_irq(qts, irq)); + send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true); + send_byte(qts, base_addr, TMP105_REG_CONFIG); + send_byte(qts, base_addr, value); + stop_transfer(qts, base_addr); + check_stopped(qts, base_addr); + + /* Receiving */ + start_transfer(qts, base_addr); + send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true); + send_byte(qts, base_addr, TMP105_REG_CONFIG); + start_transfer(qts, base_addr); + send_address(qts, base_addr, EVB_DEVICE_ADDR, true, true); + send_nack(qts, base_addr); + stop_transfer(qts, base_addr); + check_running(qts, base_addr); + g_assert_cmphex(recv_byte(qts, base_addr), =3D=3D, value); + check_stopped(qts, base_addr); + qtest_quit(qts); +} + +static void smbus_add_test(const char *name, int index, GTestDataFunc fn) +{ + g_autofree char *full_name =3D g_strdup_printf( + "npcm7xx_smbus[%d]/%s", index, name); + qtest_add_data_func(full_name, (void *)(intptr_t)index, fn); +} +#define add_test(name, td) smbus_add_test(#name, td, test_##name) + +int main(int argc, char **argv) +{ + int i; + + g_test_init(&argc, &argv, NULL); + g_test_set_nonfatal_assertions(); + + for (i =3D 0; i < NR_SMBUS_DEVICES; ++i) { + add_test(disable_bus, i); + add_test(invalid_addr, i); + } + + for (i =3D 0; i < ARRAY_SIZE(evb_bus_list); ++i) { + add_test(single_mode, evb_bus_list[i]); + } + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index c83bc211b6a..ba6ecaed325 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -139,6 +139,7 @@ qtests_npcm7xx =3D \ 'npcm7xx_gpio-test', 'npcm7xx_pwm-test', 'npcm7xx_rng-test', + 'npcm7xx_smbus-test', 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] qtests_arm =3D \ --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=gXo9vPoaGS+Kt0SAuDUqe7xzg+ZPyuQ7xrZkIvCpO/M=; b=G0+j+4QzJZx68BTqrVZf51Keb6+oy0jz7sH9gewwKZTCO7z60RVxro/UkVHdlAIqk9 gc4AejfNzBNpDjC4IwJxAsICadphsMDEkxOumgAz/ycLnV3i29RIwKRUbewEYuJodmB4 Ohxg3KR2C0LbprF29gzjOIKKVv791olvE8T3AB8jmhbwhYX/vYRk1dJM4lfUfCy59HDK Es6ozlcUoa2j/0YLS/PURib3VgSD+OLbRRNFL9qXZIkHqljuuTF52fwi0OtOA97Mnz4D PryLG5MPrdb+CKrtdqNZkHcoD8U2Ox9lPjnvFt/vEA6HiueIVjxtkI2G0D7xXx6lsAiN 070w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gXo9vPoaGS+Kt0SAuDUqe7xzg+ZPyuQ7xrZkIvCpO/M=; b=p5zcA7DPSCjEnfswpn90DVGy4Wjk10Gq4OgfksOc0q/4BRtchDn0c1bVDknZ59758s oLYw0ghQKTiA7eQ8qJqfZ9Kv5aVE07koOzdyz8MT1BdvS5y77HGnpse8jc9/kWsXExsA lXVOOyPrvIR7JHBpmelpNzHKZPX8xS4xa8slXt83EDa12EhkN9oulkTQQtPAnGI5IaU9 JPwzlSCwoGYjQqXOlguzDE/CLWlQmJWwT3oCasHb2MC/3EzhNIqKKYjraNySwGDqhVGr URARK4RXduPp6gAk+GZIMfeV/w24YsAW0Vnm0EWCTt6R2POqyxEt6oJG2OLfzpS6XuZJ FKJQ== X-Gm-Message-State: AOAM531VW2zLkq8q4KtHFunYn1bSJUVUOOdDpKEqUD8TPpL7JwyqcMD0 lwGZ2gTonGIkO1wcFd29Qik1w9wOI8Enug== X-Google-Smtp-Source: ABdhPJyJnLjYNu9fSXgB4ZjgjoIE/Ewuvfq/HDQH3c761z4D8WJixFK8XP5PmnmglcL0ielob4sT7w== X-Received: by 2002:a5d:6883:: with SMTP id h3mr24144242wru.90.1613492246866; Tue, 16 Feb 2021 08:17:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/40] hw/i2c: Implement NPCM7XX SMBus Module FIFO Mode Date: Tue, 16 Feb 2021 16:16:54 +0000 Message-Id: <20210216161658.29881-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Hao Wu This patch implements the FIFO mode of the SMBus module. In FIFO, the user transmits or receives at most 16 bytes at a time. The FIFO mode allows the module to transmit large amount of data faster than single byte mode. Since we only added the device in a patch that is only a few commits away in the same patch set. We do not increase the VMstate version number in this special case. Reviewed-by: Doug Evans Reviewed-by: Tyrong Ting Signed-off-by: Hao Wu Reviewed-by: Corey Minyard Message-id: 20210210220426.3577804-6-wuhaotsh@google.com Acked-by: Corey Minyard Signed-off-by: Peter Maydell --- include/hw/i2c/npcm7xx_smbus.h | 25 +++ hw/i2c/npcm7xx_smbus.c | 342 +++++++++++++++++++++++++++++-- tests/qtest/npcm7xx_smbus-test.c | 149 +++++++++++++- hw/i2c/trace-events | 1 + 4 files changed, 501 insertions(+), 16 deletions(-) diff --git a/include/hw/i2c/npcm7xx_smbus.h b/include/hw/i2c/npcm7xx_smbus.h index b9761a69932..7d59ee917eb 100644 --- a/include/hw/i2c/npcm7xx_smbus.h +++ b/include/hw/i2c/npcm7xx_smbus.h @@ -27,6 +27,9 @@ */ #define NPCM7XX_SMBUS_NR_ADDRS 10 =20 +/* Size of the FIFO buffer. */ +#define NPCM7XX_SMBUS_FIFO_SIZE 16 + typedef enum NPCM7xxSMBusStatus { NPCM7XX_SMBUS_STATUS_IDLE, NPCM7XX_SMBUS_STATUS_SENDING, @@ -53,6 +56,16 @@ typedef enum NPCM7xxSMBusStatus { * @addr: The SMBus module's own addresses on the I2C bus. * @scllt: The SCL low time register. * @sclht: The SCL high time register. + * @fif_ctl: The FIFO control register. + * @fif_cts: The FIFO control status register. + * @fair_per: The fair preriod register. + * @txf_ctl: The transmit FIFO control register. + * @t_out: The SMBus timeout register. + * @txf_sts: The transmit FIFO status register. + * @rxf_sts: The receive FIFO status register. + * @rxf_ctl: The receive FIFO control register. + * @rx_fifo: The FIFO buffer for receiving in FIFO mode. + * @rx_cur: The current position of rx_fifo. * @status: The current status of the SMBus. */ typedef struct NPCM7xxSMBusState { @@ -78,6 +91,18 @@ typedef struct NPCM7xxSMBusState { uint8_t scllt; uint8_t sclht; =20 + uint8_t fif_ctl; + uint8_t fif_cts; + uint8_t fair_per; + uint8_t txf_ctl; + uint8_t t_out; + uint8_t txf_sts; + uint8_t rxf_sts; + uint8_t rxf_ctl; + + uint8_t rx_fifo[NPCM7XX_SMBUS_FIFO_SIZE]; + uint8_t rx_cur; + NPCM7xxSMBusStatus status; } NPCM7xxSMBusState; =20 diff --git a/hw/i2c/npcm7xx_smbus.c b/hw/i2c/npcm7xx_smbus.c index a465740623f..6b2f9e1aaad 100644 --- a/hw/i2c/npcm7xx_smbus.c +++ b/hw/i2c/npcm7xx_smbus.c @@ -129,14 +129,45 @@ enum NPCM7xxSMBusBank1Register { #define NPCM7XX_ADDR_EN BIT(7) #define NPCM7XX_ADDR_A(rv) extract8((rv), 0, 6) =20 +/* FIFO Mode Register Fields */ +/* FIF_CTL fields */ +#define NPCM7XX_SMBFIF_CTL_FIFO_EN BIT(4) +#define NPCM7XX_SMBFIF_CTL_FAIR_RDY_IE BIT(2) +#define NPCM7XX_SMBFIF_CTL_FAIR_RDY BIT(1) +#define NPCM7XX_SMBFIF_CTL_FAIR_BUSY BIT(0) +/* FIF_CTS fields */ +#define NPCM7XX_SMBFIF_CTS_STR BIT(7) +#define NPCM7XX_SMBFIF_CTS_CLR_FIFO BIT(6) +#define NPCM7XX_SMBFIF_CTS_RFTE_IE BIT(3) +#define NPCM7XX_SMBFIF_CTS_RXF_TXE BIT(1) +/* TXF_CTL fields */ +#define NPCM7XX_SMBTXF_CTL_THR_TXIE BIT(6) +#define NPCM7XX_SMBTXF_CTL_TX_THR(rv) extract8((rv), 0, 5) +/* T_OUT fields */ +#define NPCM7XX_SMBT_OUT_ST BIT(7) +#define NPCM7XX_SMBT_OUT_IE BIT(6) +#define NPCM7XX_SMBT_OUT_CLKDIV(rv) extract8((rv), 0, 6) +/* TXF_STS fields */ +#define NPCM7XX_SMBTXF_STS_TX_THST BIT(6) +#define NPCM7XX_SMBTXF_STS_TX_BYTES(rv) extract8((rv), 0, 5) +/* RXF_STS fields */ +#define NPCM7XX_SMBRXF_STS_RX_THST BIT(6) +#define NPCM7XX_SMBRXF_STS_RX_BYTES(rv) extract8((rv), 0, 5) +/* RXF_CTL fields */ +#define NPCM7XX_SMBRXF_CTL_THR_RXIE BIT(6) +#define NPCM7XX_SMBRXF_CTL_LAST BIT(5) +#define NPCM7XX_SMBRXF_CTL_RX_THR(rv) extract8((rv), 0, 5) + #define KEEP_OLD_BIT(o, n, b) (((n) & (~(b))) | ((o) & (b))) #define WRITE_ONE_CLEAR(o, n, b) ((n) & (b) ? (o) & (~(b)) : (o)) =20 #define NPCM7XX_SMBUS_ENABLED(s) ((s)->ctl2 & NPCM7XX_SMBCTL2_ENABLE) +#define NPCM7XX_SMBUS_FIFO_ENABLED(s) ((s)->fif_ctl & \ + NPCM7XX_SMBFIF_CTL_FIFO_EN) =20 /* VERSION fields values, read-only. */ #define NPCM7XX_SMBUS_VERSION_NUMBER 1 -#define NPCM7XX_SMBUS_VERSION_FIFO_SUPPORTED 0 +#define NPCM7XX_SMBUS_VERSION_FIFO_SUPPORTED 1 =20 /* Reset values */ #define NPCM7XX_SMB_ST_INIT_VAL 0x00 @@ -151,6 +182,14 @@ enum NPCM7xxSMBusBank1Register { #define NPCM7XX_SMB_ADDR_INIT_VAL 0x00 #define NPCM7XX_SMB_SCLLT_INIT_VAL 0x00 #define NPCM7XX_SMB_SCLHT_INIT_VAL 0x00 +#define NPCM7XX_SMB_FIF_CTL_INIT_VAL 0x00 +#define NPCM7XX_SMB_FIF_CTS_INIT_VAL 0x00 +#define NPCM7XX_SMB_FAIR_PER_INIT_VAL 0x00 +#define NPCM7XX_SMB_TXF_CTL_INIT_VAL 0x00 +#define NPCM7XX_SMB_T_OUT_INIT_VAL 0x3f +#define NPCM7XX_SMB_TXF_STS_INIT_VAL 0x00 +#define NPCM7XX_SMB_RXF_STS_INIT_VAL 0x00 +#define NPCM7XX_SMB_RXF_CTL_INIT_VAL 0x01 =20 static uint8_t npcm7xx_smbus_get_version(void) { @@ -171,7 +210,13 @@ static void npcm7xx_smbus_update_irq(NPCM7xxSMBusState= *s) (s->ctl1 & NPCM7XX_SMBCTL1_STASTRE && s->st & NPCM7XX_SMBST_SDAST) || (s->ctl1 & NPCM7XX_SMBCTL1_EOBINTE && - s->cst3 & NPCM7XX_SMBCST3_EO_BUSY)); + s->cst3 & NPCM7XX_SMBCST3_EO_BUSY) || + (s->rxf_ctl & NPCM7XX_SMBRXF_CTL_THR_RXIE && + s->rxf_sts & NPCM7XX_SMBRXF_STS_RX_THST) || + (s->txf_ctl & NPCM7XX_SMBTXF_CTL_THR_TXIE && + s->txf_sts & NPCM7XX_SMBTXF_STS_TX_THST) || + (s->fif_cts & NPCM7XX_SMBFIF_CTS_RFTE_IE && + s->fif_cts & NPCM7XX_SMBFIF_CTS_RXF_TXE)); =20 if (level) { s->cst2 |=3D NPCM7XX_SMBCST2_INTSTS; @@ -189,6 +234,13 @@ static void npcm7xx_smbus_nack(NPCM7xxSMBusState *s) s->status =3D NPCM7XX_SMBUS_STATUS_NEGACK; } =20 +static void npcm7xx_smbus_clear_buffer(NPCM7xxSMBusState *s) +{ + s->fif_cts &=3D ~NPCM7XX_SMBFIF_CTS_RXF_TXE; + s->txf_sts =3D 0; + s->rxf_sts =3D 0; +} + static void npcm7xx_smbus_send_byte(NPCM7xxSMBusState *s, uint8_t value) { int rv =3D i2c_send(s->bus, value); @@ -197,6 +249,15 @@ static void npcm7xx_smbus_send_byte(NPCM7xxSMBusState = *s, uint8_t value) npcm7xx_smbus_nack(s); } else { s->st |=3D NPCM7XX_SMBST_SDAST; + if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + s->fif_cts |=3D NPCM7XX_SMBFIF_CTS_RXF_TXE; + if (NPCM7XX_SMBTXF_STS_TX_BYTES(s->txf_sts) =3D=3D + NPCM7XX_SMBTXF_CTL_TX_THR(s->txf_ctl)) { + s->txf_sts =3D NPCM7XX_SMBTXF_STS_TX_THST; + } else { + s->txf_sts =3D 0; + } + } } trace_npcm7xx_smbus_send_byte((DEVICE(s)->canonical_path), value, !rv); npcm7xx_smbus_update_irq(s); @@ -215,6 +276,67 @@ static void npcm7xx_smbus_recv_byte(NPCM7xxSMBusState = *s) npcm7xx_smbus_update_irq(s); } =20 +static void npcm7xx_smbus_recv_fifo(NPCM7xxSMBusState *s) +{ + uint8_t expected_bytes =3D NPCM7XX_SMBRXF_CTL_RX_THR(s->rxf_ctl); + uint8_t received_bytes =3D NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts); + uint8_t pos; + + if (received_bytes =3D=3D expected_bytes) { + return; + } + + while (received_bytes < expected_bytes && + received_bytes < NPCM7XX_SMBUS_FIFO_SIZE) { + pos =3D (s->rx_cur + received_bytes) % NPCM7XX_SMBUS_FIFO_SIZE; + s->rx_fifo[pos] =3D i2c_recv(s->bus); + trace_npcm7xx_smbus_recv_byte((DEVICE(s)->canonical_path), + s->rx_fifo[pos]); + ++received_bytes; + } + + trace_npcm7xx_smbus_recv_fifo((DEVICE(s)->canonical_path), + received_bytes, expected_bytes); + s->rxf_sts =3D received_bytes; + if (unlikely(received_bytes < expected_bytes)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid rx_thr value: 0x%02x\n", + DEVICE(s)->canonical_path, expected_bytes); + return; + } + + s->rxf_sts |=3D NPCM7XX_SMBRXF_STS_RX_THST; + if (s->rxf_ctl & NPCM7XX_SMBRXF_CTL_LAST) { + trace_npcm7xx_smbus_nack(DEVICE(s)->canonical_path); + i2c_nack(s->bus); + s->rxf_ctl &=3D ~NPCM7XX_SMBRXF_CTL_LAST; + } + if (received_bytes =3D=3D NPCM7XX_SMBUS_FIFO_SIZE) { + s->st |=3D NPCM7XX_SMBST_SDAST; + s->fif_cts |=3D NPCM7XX_SMBFIF_CTS_RXF_TXE; + } else if (!(s->rxf_ctl & NPCM7XX_SMBRXF_CTL_THR_RXIE)) { + s->st |=3D NPCM7XX_SMBST_SDAST; + } else { + s->st &=3D ~NPCM7XX_SMBST_SDAST; + } + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_read_byte_fifo(NPCM7xxSMBusState *s) +{ + uint8_t received_bytes =3D NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts); + + if (received_bytes =3D=3D 0) { + npcm7xx_smbus_recv_fifo(s); + return; + } + + s->sda =3D s->rx_fifo[s->rx_cur]; + s->rx_cur =3D (s->rx_cur + 1u) % NPCM7XX_SMBUS_FIFO_SIZE; + --s->rxf_sts; + npcm7xx_smbus_update_irq(s); +} + static void npcm7xx_smbus_start(NPCM7xxSMBusState *s) { /* @@ -228,6 +350,9 @@ static void npcm7xx_smbus_start(NPCM7xxSMBusState *s) if (available) { s->st |=3D NPCM7XX_SMBST_MODE | NPCM7XX_SMBST_XMIT | NPCM7XX_SMBST= _SDAST; s->cst |=3D NPCM7XX_SMBCST_BUSY; + if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + s->fif_cts |=3D NPCM7XX_SMBFIF_CTS_RXF_TXE; + } } else { s->st &=3D ~NPCM7XX_SMBST_MODE; s->cst &=3D ~NPCM7XX_SMBCST_BUSY; @@ -279,7 +404,15 @@ static void npcm7xx_smbus_send_address(NPCM7xxSMBusSta= te *s, uint8_t value) s->st |=3D NPCM7XX_SMBST_SDAST; } } else if (recv) { - npcm7xx_smbus_recv_byte(s); + s->st |=3D NPCM7XX_SMBST_SDAST; + if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + npcm7xx_smbus_recv_fifo(s); + } else { + npcm7xx_smbus_recv_byte(s); + } + } else if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + s->st |=3D NPCM7XX_SMBST_SDAST; + s->fif_cts |=3D NPCM7XX_SMBFIF_CTS_RXF_TXE; } npcm7xx_smbus_update_irq(s); } @@ -322,11 +455,31 @@ static uint8_t npcm7xx_smbus_read_sda(NPCM7xxSMBusSta= te *s) =20 switch (s->status) { case NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE: - npcm7xx_smbus_execute_stop(s); + if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + if (NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts) <=3D 1) { + npcm7xx_smbus_execute_stop(s); + } + if (NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts) =3D=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: read to SDA with an empty rx-fifo buffe= r, " + "result undefined: %u\n", + DEVICE(s)->canonical_path, s->sda); + break; + } + npcm7xx_smbus_read_byte_fifo(s); + value =3D s->sda; + } else { + npcm7xx_smbus_execute_stop(s); + } break; =20 case NPCM7XX_SMBUS_STATUS_RECEIVING: - npcm7xx_smbus_recv_byte(s); + if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + npcm7xx_smbus_read_byte_fifo(s); + value =3D s->sda; + } else { + npcm7xx_smbus_recv_byte(s); + } break; =20 default: @@ -372,8 +525,12 @@ static void npcm7xx_smbus_write_st(NPCM7xxSMBusState *= s, uint8_t value) } =20 if (value & NPCM7XX_SMBST_STASTR && - s->status =3D=3D NPCM7XX_SMBUS_STATUS_RECEIVING) { - npcm7xx_smbus_recv_byte(s); + s->status =3D=3D NPCM7XX_SMBUS_STATUS_RECEIVING) { + if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + npcm7xx_smbus_recv_fifo(s); + } else { + npcm7xx_smbus_recv_byte(s); + } } =20 npcm7xx_smbus_update_irq(s); @@ -419,6 +576,7 @@ static void npcm7xx_smbus_write_ctl2(NPCM7xxSMBusState = *s, uint8_t value) s->st =3D 0; s->cst3 =3D s->cst3 & (~NPCM7XX_SMBCST3_EO_BUSY); s->cst =3D 0; + npcm7xx_smbus_clear_buffer(s); } } =20 @@ -431,6 +589,70 @@ static void npcm7xx_smbus_write_ctl3(NPCM7xxSMBusState= *s, uint8_t value) NPCM7XX_SMBCTL3_SCL_LVL | NPCM7XX_SMBCTL3_SDA_= LVL); } =20 +static void npcm7xx_smbus_write_fif_ctl(NPCM7xxSMBusState *s, uint8_t valu= e) +{ + uint8_t new_ctl =3D value; + + new_ctl =3D KEEP_OLD_BIT(s->fif_ctl, new_ctl, NPCM7XX_SMBFIF_CTL_FAIR_= RDY); + new_ctl =3D WRITE_ONE_CLEAR(new_ctl, value, NPCM7XX_SMBFIF_CTL_FAIR_RD= Y); + new_ctl =3D KEEP_OLD_BIT(s->fif_ctl, new_ctl, NPCM7XX_SMBFIF_CTL_FAIR_= BUSY); + s->fif_ctl =3D new_ctl; +} + +static void npcm7xx_smbus_write_fif_cts(NPCM7xxSMBusState *s, uint8_t valu= e) +{ + s->fif_cts =3D WRITE_ONE_CLEAR(s->fif_cts, value, NPCM7XX_SMBFIF_CTS_S= TR); + s->fif_cts =3D WRITE_ONE_CLEAR(s->fif_cts, value, NPCM7XX_SMBFIF_CTS_R= XF_TXE); + s->fif_cts =3D KEEP_OLD_BIT(value, s->fif_cts, NPCM7XX_SMBFIF_CTS_RFTE= _IE); + + if (value & NPCM7XX_SMBFIF_CTS_CLR_FIFO) { + npcm7xx_smbus_clear_buffer(s); + } +} + +static void npcm7xx_smbus_write_txf_ctl(NPCM7xxSMBusState *s, uint8_t valu= e) +{ + s->txf_ctl =3D value; +} + +static void npcm7xx_smbus_write_t_out(NPCM7xxSMBusState *s, uint8_t value) +{ + uint8_t new_t_out =3D value; + + if ((value & NPCM7XX_SMBT_OUT_ST) || (!(s->t_out & NPCM7XX_SMBT_OUT_ST= ))) { + new_t_out &=3D ~NPCM7XX_SMBT_OUT_ST; + } else { + new_t_out |=3D NPCM7XX_SMBT_OUT_ST; + } + + s->t_out =3D new_t_out; +} + +static void npcm7xx_smbus_write_txf_sts(NPCM7xxSMBusState *s, uint8_t valu= e) +{ + s->txf_sts =3D WRITE_ONE_CLEAR(s->txf_sts, value, NPCM7XX_SMBTXF_STS_T= X_THST); +} + +static void npcm7xx_smbus_write_rxf_sts(NPCM7xxSMBusState *s, uint8_t valu= e) +{ + if (value & NPCM7XX_SMBRXF_STS_RX_THST) { + s->rxf_sts &=3D ~NPCM7XX_SMBRXF_STS_RX_THST; + if (s->status =3D=3D NPCM7XX_SMBUS_STATUS_RECEIVING) { + npcm7xx_smbus_recv_fifo(s); + } + } +} + +static void npcm7xx_smbus_write_rxf_ctl(NPCM7xxSMBusState *s, uint8_t valu= e) +{ + uint8_t new_ctl =3D value; + + if (!(value & NPCM7XX_SMBRXF_CTL_LAST)) { + new_ctl =3D KEEP_OLD_BIT(s->rxf_ctl, new_ctl, NPCM7XX_SMBRXF_CTL_L= AST); + } + s->rxf_ctl =3D new_ctl; +} + static uint64_t npcm7xx_smbus_read(void *opaque, hwaddr offset, unsigned s= ize) { NPCM7xxSMBusState *s =3D opaque; @@ -487,9 +709,41 @@ static uint64_t npcm7xx_smbus_read(void *opaque, hwadd= r offset, unsigned size) default: if (bank) { /* Bank 1 */ - qemu_log_mask(LOG_GUEST_ERROR, - "%s: read from invalid offset 0x%" HWADDR_PRIx "\n", - DEVICE(s)->canonical_path, offset); + switch (offset) { + case NPCM7XX_SMB_FIF_CTS: + value =3D s->fif_cts; + break; + + case NPCM7XX_SMB_FAIR_PER: + value =3D s->fair_per; + break; + + case NPCM7XX_SMB_TXF_CTL: + value =3D s->txf_ctl; + break; + + case NPCM7XX_SMB_T_OUT: + value =3D s->t_out; + break; + + case NPCM7XX_SMB_TXF_STS: + value =3D s->txf_sts; + break; + + case NPCM7XX_SMB_RXF_STS: + value =3D s->rxf_sts; + break; + + case NPCM7XX_SMB_RXF_CTL: + value =3D s->rxf_ctl; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: read from invalid offset 0x%" HWADDR_PRIx "\n= ", + DEVICE(s)->canonical_path, offset); + break; + } } else { /* Bank 0 */ switch (offset) { @@ -537,6 +791,10 @@ static uint64_t npcm7xx_smbus_read(void *opaque, hwadd= r offset, unsigned size) value =3D s->scllt; break; =20 + case NPCM7XX_SMB_FIF_CTL: + value =3D s->fif_ctl; + break; + case NPCM7XX_SMB_SCLHT: value =3D s->sclht; break; @@ -618,9 +876,41 @@ static void npcm7xx_smbus_write(void *opaque, hwaddr o= ffset, uint64_t value, default: if (bank) { /* Bank 1 */ - qemu_log_mask(LOG_GUEST_ERROR, - "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", - DEVICE(s)->canonical_path, offset); + switch (offset) { + case NPCM7XX_SMB_FIF_CTS: + npcm7xx_smbus_write_fif_cts(s, value); + break; + + case NPCM7XX_SMB_FAIR_PER: + s->fair_per =3D value; + break; + + case NPCM7XX_SMB_TXF_CTL: + npcm7xx_smbus_write_txf_ctl(s, value); + break; + + case NPCM7XX_SMB_T_OUT: + npcm7xx_smbus_write_t_out(s, value); + break; + + case NPCM7XX_SMB_TXF_STS: + npcm7xx_smbus_write_txf_sts(s, value); + break; + + case NPCM7XX_SMB_RXF_STS: + npcm7xx_smbus_write_rxf_sts(s, value); + break; + + case NPCM7XX_SMB_RXF_CTL: + npcm7xx_smbus_write_rxf_ctl(s, value); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + break; + } } else { /* Bank 0 */ switch (offset) { @@ -668,6 +958,10 @@ static void npcm7xx_smbus_write(void *opaque, hwaddr o= ffset, uint64_t value, s->scllt =3D value; break; =20 + case NPCM7XX_SMB_FIF_CTL: + npcm7xx_smbus_write_fif_ctl(s, value); + break; + case NPCM7XX_SMB_SCLHT: s->sclht =3D value; break; @@ -714,7 +1008,18 @@ static void npcm7xx_smbus_enter_reset(Object *obj, Re= setType type) s->scllt =3D NPCM7XX_SMB_SCLLT_INIT_VAL; s->sclht =3D NPCM7XX_SMB_SCLHT_INIT_VAL; =20 + s->fif_ctl =3D NPCM7XX_SMB_FIF_CTL_INIT_VAL; + s->fif_cts =3D NPCM7XX_SMB_FIF_CTS_INIT_VAL; + s->fair_per =3D NPCM7XX_SMB_FAIR_PER_INIT_VAL; + s->txf_ctl =3D NPCM7XX_SMB_TXF_CTL_INIT_VAL; + s->t_out =3D NPCM7XX_SMB_T_OUT_INIT_VAL; + s->txf_sts =3D NPCM7XX_SMB_TXF_STS_INIT_VAL; + s->rxf_sts =3D NPCM7XX_SMB_RXF_STS_INIT_VAL; + s->rxf_ctl =3D NPCM7XX_SMB_RXF_CTL_INIT_VAL; + + npcm7xx_smbus_clear_buffer(s); s->status =3D NPCM7XX_SMBUS_STATUS_IDLE; + s->rx_cur =3D 0; } =20 static void npcm7xx_smbus_hold_reset(Object *obj) @@ -756,6 +1061,17 @@ static const VMStateDescription vmstate_npcm7xx_smbus= =3D { VMSTATE_UINT8_ARRAY(addr, NPCM7xxSMBusState, NPCM7XX_SMBUS_NR_ADDR= S), VMSTATE_UINT8(scllt, NPCM7xxSMBusState), VMSTATE_UINT8(sclht, NPCM7xxSMBusState), + VMSTATE_UINT8(fif_ctl, NPCM7xxSMBusState), + VMSTATE_UINT8(fif_cts, NPCM7xxSMBusState), + VMSTATE_UINT8(fair_per, NPCM7xxSMBusState), + VMSTATE_UINT8(txf_ctl, NPCM7xxSMBusState), + VMSTATE_UINT8(t_out, NPCM7xxSMBusState), + VMSTATE_UINT8(txf_sts, NPCM7xxSMBusState), + VMSTATE_UINT8(rxf_sts, NPCM7xxSMBusState), + VMSTATE_UINT8(rxf_ctl, NPCM7xxSMBusState), + VMSTATE_UINT8_ARRAY(rx_fifo, NPCM7xxSMBusState, + NPCM7XX_SMBUS_FIFO_SIZE), + VMSTATE_UINT8(rx_cur, NPCM7xxSMBusState), VMSTATE_END_OF_LIST(), }, }; diff --git a/tests/qtest/npcm7xx_smbus-test.c b/tests/qtest/npcm7xx_smbus-t= est.c index 4594b107df1..4f9f493872a 100644 --- a/tests/qtest/npcm7xx_smbus-test.c +++ b/tests/qtest/npcm7xx_smbus-test.c @@ -132,6 +132,44 @@ enum NPCM7xxSMBusBank1Register { #define ADDR_EN BIT(7) #define ADDR_A(rv) extract8((rv), 0, 6) =20 +/* FIF_CTL fields */ +#define FIF_CTL_FIFO_EN BIT(4) + +/* FIF_CTS fields */ +#define FIF_CTS_CLR_FIFO BIT(6) +#define FIF_CTS_RFTE_IE BIT(3) +#define FIF_CTS_RXF_TXE BIT(1) + +/* TXF_CTL fields */ +#define TXF_CTL_THR_TXIE BIT(6) +#define TXF_CTL_TX_THR(rv) extract8((rv), 0, 5) + +/* TXF_STS fields */ +#define TXF_STS_TX_THST BIT(6) +#define TXF_STS_TX_BYTES(rv) extract8((rv), 0, 5) + +/* RXF_CTL fields */ +#define RXF_CTL_THR_RXIE BIT(6) +#define RXF_CTL_LAST BIT(5) +#define RXF_CTL_RX_THR(rv) extract8((rv), 0, 5) + +/* RXF_STS fields */ +#define RXF_STS_RX_THST BIT(6) +#define RXF_STS_RX_BYTES(rv) extract8((rv), 0, 5) + + +static void choose_bank(QTestState *qts, uint64_t base_addr, uint8_t bank) +{ + uint8_t ctl3 =3D qtest_readb(qts, base_addr + OFFSET_CTL3); + + if (bank) { + ctl3 |=3D CTL3_BNK_SEL; + } else { + ctl3 &=3D ~CTL3_BNK_SEL; + } + + qtest_writeb(qts, base_addr + OFFSET_CTL3, ctl3); +} =20 static void check_running(QTestState *qts, uint64_t base_addr) { @@ -203,10 +241,33 @@ static void send_byte(QTestState *qts, uint64_t base_= addr, uint8_t byte) qtest_writeb(qts, base_addr + OFFSET_SDA, byte); } =20 +static bool check_recv(QTestState *qts, uint64_t base_addr) +{ + uint8_t st, fif_ctl, rxf_ctl, rxf_sts; + bool fifo; + + st =3D qtest_readb(qts, base_addr + OFFSET_ST); + choose_bank(qts, base_addr, 0); + fif_ctl =3D qtest_readb(qts, base_addr + OFFSET_FIF_CTL); + fifo =3D fif_ctl & FIF_CTL_FIFO_EN; + if (!fifo) { + return st =3D=3D (ST_MODE | ST_SDAST); + } + + choose_bank(qts, base_addr, 1); + rxf_ctl =3D qtest_readb(qts, base_addr + OFFSET_RXF_CTL); + rxf_sts =3D qtest_readb(qts, base_addr + OFFSET_RXF_STS); + + if ((rxf_ctl & RXF_CTL_THR_RXIE) && RXF_STS_RX_BYTES(rxf_sts) < 16) { + return st =3D=3D ST_MODE; + } else { + return st =3D=3D (ST_MODE | ST_SDAST); + } +} + static uint8_t recv_byte(QTestState *qts, uint64_t base_addr) { - g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), =3D=3D, - ST_MODE | ST_SDAST); + g_assert_true(check_recv(qts, base_addr)); return qtest_readb(qts, base_addr + OFFSET_SDA); } =20 @@ -229,7 +290,7 @@ static void send_address(QTestState *qts, uint64_t base= _addr, uint8_t addr, qtest_writeb(qts, base_addr + OFFSET_ST, ST_STASTR); st =3D qtest_readb(qts, base_addr + OFFSET_ST); if (recv) { - g_assert_cmphex(st, =3D=3D, ST_MODE | ST_SDAST); + g_assert_true(check_recv(qts, base_addr)); } else { g_assert_cmphex(st, =3D=3D, ST_MODE | ST_XMIT | ST_SDAST); } @@ -251,6 +312,29 @@ static void send_nack(QTestState *qts, uint64_t base_a= ddr) qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); } =20 +static void start_fifo_mode(QTestState *qts, uint64_t base_addr) +{ + choose_bank(qts, base_addr, 0); + qtest_writeb(qts, base_addr + OFFSET_FIF_CTL, FIF_CTL_FIFO_EN); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_FIF_CTL) & + FIF_CTL_FIFO_EN); + choose_bank(qts, base_addr, 1); + qtest_writeb(qts, base_addr + OFFSET_FIF_CTS, + FIF_CTS_CLR_FIFO | FIF_CTS_RFTE_IE); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_FIF_CTS), =3D=3D, + FIF_CTS_RFTE_IE); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_TXF_STS), =3D=3D, = 0); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_RXF_STS), =3D=3D, = 0); +} + +static void start_recv_fifo(QTestState *qts, uint64_t base_addr, uint8_t b= ytes) +{ + choose_bank(qts, base_addr, 1); + qtest_writeb(qts, base_addr + OFFSET_TXF_CTL, 0); + qtest_writeb(qts, base_addr + OFFSET_RXF_CTL, + RXF_CTL_THR_RXIE | RXF_CTL_LAST | bytes); +} + /* Check the SMBus's status is set correctly when disabled. */ static void test_disable_bus(gconstpointer data) { @@ -324,6 +408,64 @@ static void test_single_mode(gconstpointer data) qtest_quit(qts); } =20 +/* Check the SMBus can send and receive bytes in FIFO mode. */ +static void test_fifo_mode(gconstpointer data) +{ + intptr_t index =3D (intptr_t)data; + uint64_t base_addr =3D SMBUS_ADDR(index); + int irq =3D SMBUS_IRQ(index); + uint8_t value =3D 0x60; + QTestState *qts =3D qtest_init("-machine npcm750-evb"); + + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + enable_bus(qts, base_addr); + start_fifo_mode(qts, base_addr); + g_assert_false(qtest_get_irq(qts, irq)); + + /* Sending */ + start_transfer(qts, base_addr); + send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true); + choose_bank(qts, base_addr, 1); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_FIF_CTS) & + FIF_CTS_RXF_TXE); + qtest_writeb(qts, base_addr + OFFSET_TXF_CTL, TXF_CTL_THR_TXIE); + send_byte(qts, base_addr, TMP105_REG_CONFIG); + send_byte(qts, base_addr, value); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_FIF_CTS) & + FIF_CTS_RXF_TXE); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_TXF_STS) & + TXF_STS_TX_THST); + g_assert_cmpuint(TXF_STS_TX_BYTES( + qtest_readb(qts, base_addr + OFFSET_TXF_STS)), =3D= =3D, 0); + g_assert_true(qtest_get_irq(qts, irq)); + stop_transfer(qts, base_addr); + check_stopped(qts, base_addr); + + /* Receiving */ + start_fifo_mode(qts, base_addr); + start_transfer(qts, base_addr); + send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true); + send_byte(qts, base_addr, TMP105_REG_CONFIG); + start_transfer(qts, base_addr); + qtest_writeb(qts, base_addr + OFFSET_FIF_CTS, FIF_CTS_RXF_TXE); + start_recv_fifo(qts, base_addr, 1); + send_address(qts, base_addr, EVB_DEVICE_ADDR, true, true); + g_assert_false(qtest_readb(qts, base_addr + OFFSET_FIF_CTS) & + FIF_CTS_RXF_TXE); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_RXF_STS) & + RXF_STS_RX_THST); + g_assert_cmpuint(RXF_STS_RX_BYTES( + qtest_readb(qts, base_addr + OFFSET_RXF_STS)), =3D= =3D, 1); + send_nack(qts, base_addr); + stop_transfer(qts, base_addr); + check_running(qts, base_addr); + g_assert_cmphex(recv_byte(qts, base_addr), =3D=3D, value); + g_assert_cmpuint(RXF_STS_RX_BYTES( + qtest_readb(qts, base_addr + OFFSET_RXF_STS)), =3D= =3D, 0); + check_stopped(qts, base_addr); + qtest_quit(qts); +} + static void smbus_add_test(const char *name, int index, GTestDataFunc fn) { g_autofree char *full_name =3D g_strdup_printf( @@ -346,6 +488,7 @@ int main(int argc, char **argv) =20 for (i =3D 0; i < ARRAY_SIZE(evb_bus_list); ++i) { add_test(single_mode, evb_bus_list[i]); + add_test(fifo_mode, evb_bus_list[i]); } =20 return g_test_run(); diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events index c3bb70ad045..82fe6f965f4 100644 --- a/hw/i2c/trace-events +++ b/hw/i2c/trace-events @@ -25,3 +25,4 @@ npcm7xx_smbus_send_byte(const char *id, uint8_t value, in= t success) "%s send byt npcm7xx_smbus_recv_byte(const char *id, uint8_t value) "%s recv byte: 0x%0= 2x" npcm7xx_smbus_stop(const char *id) "%s stopping" npcm7xx_smbus_nack(const char *id) "%s nacking" +npcm7xx_smbus_recv_fifo(const char *id, uint8_t received, uint8_t expected= ) "%s recv fifo: received %u, expected %u" --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=o04V8OAF/AbV4swogzM64bdrvlvxNjU/Edl1NkQw/Ms=; b=UEBzzyNtVelHkyUfVzxpZnDHF4AqGTk9LGheHxfPQ3Wqzg43aLmXE8im8uQgwKVHCu oQS1jVDA8MVsLGXK7pQJSGQGzbbOtZUIYzPGutN2lkxyPBoFf6/R2HnXvXoUQOQfNZla HYXzB3HY2AwqoM3sX25mfpH8ZB1wVoid2pkusFValhWB9RkjP/08pZKEMQeQaOjH9UeG JtZ9hs8ZnlqT67qymYawnPzK6l++lZ551VndhMebT7l/fazj2dmc0gvlWiNg6+8xPHBC BHQvWi7wIj9WBXljRqVcxJSu/oiX0wMI4rKzDj79vrDWz1fEBLI3fkO9ff+I2y/bkqng zOXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o04V8OAF/AbV4swogzM64bdrvlvxNjU/Edl1NkQw/Ms=; b=fDcU/1+9JLQEcO73w0hDXdyjrKOGmgL67nImNauU7ITM420NIXjfy0bm3Lb/N7/IMs +MddTAM7BPnrBtj3o3Vs3j9frcTgy0un/zCkwcS8SxIpDy+lpIdg5q6zaOiQqlUiYdIt 1tUmrA6C2uFbnbn3gTGGnYEsa/+F1kqY2s5A1Dm+TxnvMvllXZQ9vqnGeQCpC3hbAan0 WanolZ+KswBNgLMAyAfXE2zFunvcb+TESZkzBFXHhKlrMs7UjMwZK3JBZZWfx90GJWzp 4i81uL5xc2gc2AQ56OR8Ju5m6tKIuoGiiFEPGdi8eM8/n0+ygMm8uoyb3ULSLwp6knVh MuDg== X-Gm-Message-State: AOAM530lp6dTFtqmr1wCBlxgb4Y9h12L6/II4G2SIoqlXi2dp5Dd6SAc AzN46haQ6x3Eyw2zvXZ56rrY0jwanDSWJQ== X-Google-Smtp-Source: ABdhPJxiY9UvgprIcw8TgijxPyHEnIcXmFJHROASnroIqT+MNoG1qfMadhcJE1uiNuOf3jtCNyifeQ== X-Received: by 2002:adf:9546:: with SMTP id 64mr25388994wrs.247.1613492247524; Tue, 16 Feb 2021 08:17:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/40] MAINTAINERS: add myself maintainer for the clock framework Date: Tue, 16 Feb 2021 16:16:55 +0000 Message-Id: <20210216161658.29881-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Luc Michel Also add Damien as a reviewer. Signed-off-by: Luc Michel Acked-by: Damien Hedde Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210211085318.2507-1-luc@lmichel.fr Signed-off-by: Peter Maydell --- MAINTAINERS | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8201f12271b..68ee2717926 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2855,6 +2855,17 @@ F: pc-bios/opensbi-* F: .gitlab-ci.d/opensbi.yml F: .gitlab-ci.d/opensbi/ =20 +Clock framework +M: Luc Michel +R: Damien Hedde +S: Maintained +F: include/hw/clock.h +F: include/hw/qdev-clock.h +F: hw/core/clock.c +F: hw/core/clock-vmstate.c +F: hw/core/qdev-clock.c +F: docs/devel/clocks.rst + Usermode Emulation ------------------ Overall usermode emulation --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613494383679321.225742037769; Tue, 16 Feb 2021 08:53:03 -0800 (PST) Received: from localhost ([::1]:60614 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3av-0004yk-Sm for importer@patchew.org; Tue, 16 Feb 2021 11:53:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41002) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC33T-0000YV-4o for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:27 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:38954) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32Y-0002Z5-C6 for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:26 -0500 Received: by mail-wr1-x429.google.com with SMTP id v1so13780416wrd.6 for ; Tue, 16 Feb 2021 08:17:29 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bfU+AGoaB/3f4C3ROicmkkQgxo7JYiTLQwrmJhg6mXE=; b=uP2Z4525ISXBsjO9WVVFbBZZtaiebKqgZpQPfnGO0TqzsRJNe+++rjQNdDoRkx7W2X 9W1LE5FBhn1jyPYkD8N9hWmMZpHZI9YJVCEeFRfOVC2aPVpqr40/ynTxkCFeqClJxmZ5 NFJvvi0OZOOFAMy0p7oapbVG6bKfv9Lf8DDNQJNLr8FgHWMzKu7Pv+6jEjdqEll/i8Jd t+israhSll5UwhZHVj0pyGWeRuKeo9gRCyRF9Xb3G0xmBbERUHSZukMPpEGl3Zv+2T+C BsZ2mIugyLpb4oaVD2emSuiT3la2kXhiPlugptedgdrhgaMqBBIK7Ee+gJ79Htc55fuT 8agw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bfU+AGoaB/3f4C3ROicmkkQgxo7JYiTLQwrmJhg6mXE=; b=UfKVJgZogY85CR92zUQjqcV5/I7Yc7CAY5YqrHZzPHBt0ORJfLTKQ1tbb99igacnyp gatoNtubdmGiyMBGa2D+mMDTqa0KPCevhut7kNkmemWm4cdOTwIT0BDFv/bRXrOne79O 7ecbWLJ31qnxr7Ou1K5gUmR2UGitGM9zYlfCpKbmwL0fwmynjQ77a85v6niQb7+Hz4wW lLlt25ahvcFOpX/WmEfBsJNl2m0g9hcv87qM81xVDpIPMRxxP0ShaH0DN7Sudwz8yFu1 LKHTJuv6eWadF4JVo4isKLDnjXcy8g/myrfR6LA70QctWN669aeDoth8BH6yWrJGJk5y Zw9A== X-Gm-Message-State: AOAM531ccyQgvwiutC3YPYsJT/TUwwkriolqJjdj29EM5wLPds0Sm85X IO8w/yFEVGHSnRiISLkn3MfNvboIkcub6g== X-Google-Smtp-Source: ABdhPJw40+7qBxQIbGrNzqNQQqUaUwSlBdFtB3k1yLBCRnPJPc1nli3NHZLj1FIQFJ2dNT66Bvmeqg== X-Received: by 2002:adf:c785:: with SMTP id l5mr18393763wrg.234.1613492248805; Tue, 16 Feb 2021 08:17:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/40] hw/net: Add npcm7xx emc model Date: Tue, 16 Feb 2021 16:16:56 +0000 Message-Id: <20210216161658.29881-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Doug Evans This is a 10/100 ethernet device that has several features. Only the ones needed by the Linux driver have been implemented. See npcm7xx_emc.c for a list of unimplemented features. Reviewed-by: Hao Wu Reviewed-by: Avi Fishman Reviewed-by: Peter Maydell Signed-off-by: Doug Evans Message-id: 20210213002520.1374134-2-dje@google.com Signed-off-by: Peter Maydell --- include/hw/net/npcm7xx_emc.h | 286 ++++++++++++ hw/net/npcm7xx_emc.c | 857 +++++++++++++++++++++++++++++++++++ hw/net/meson.build | 1 + hw/net/trace-events | 17 + 4 files changed, 1161 insertions(+) create mode 100644 include/hw/net/npcm7xx_emc.h create mode 100644 hw/net/npcm7xx_emc.c diff --git a/include/hw/net/npcm7xx_emc.h b/include/hw/net/npcm7xx_emc.h new file mode 100644 index 00000000000..eac7f298167 --- /dev/null +++ b/include/hw/net/npcm7xx_emc.h @@ -0,0 +1,286 @@ +/* + * Nuvoton NPCM7xx EMC Module + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef NPCM7XX_EMC_H +#define NPCM7XX_EMC_H + +#include "hw/irq.h" +#include "hw/sysbus.h" +#include "net/net.h" + +/* 32-bit register indices. */ +enum NPCM7xxPWMRegister { + /* Control registers. */ + REG_CAMCMR, + REG_CAMEN, + + /* There are 16 CAMn[ML] registers. */ + REG_CAMM_BASE, + REG_CAML_BASE, + REG_CAMML_LAST =3D 0x21, + + REG_TXDLSA =3D 0x22, + REG_RXDLSA, + REG_MCMDR, + REG_MIID, + REG_MIIDA, + REG_FFTCR, + REG_TSDR, + REG_RSDR, + REG_DMARFC, + REG_MIEN, + + /* Status registers. */ + REG_MISTA, + REG_MGSTA, + REG_MPCNT, + REG_MRPC, + REG_MRPCC, + REG_MREPC, + REG_DMARFS, + REG_CTXDSA, + REG_CTXBSA, + REG_CRXDSA, + REG_CRXBSA, + + NPCM7XX_NUM_EMC_REGS, +}; + +/* REG_CAMCMR fields */ +/* Enable CAM Compare */ +#define REG_CAMCMR_ECMP (1 << 4) +/* Complement CAM Compare */ +#define REG_CAMCMR_CCAM (1 << 3) +/* Accept Broadcast Packet */ +#define REG_CAMCMR_ABP (1 << 2) +/* Accept Multicast Packet */ +#define REG_CAMCMR_AMP (1 << 1) +/* Accept Unicast Packet */ +#define REG_CAMCMR_AUP (1 << 0) + +/* REG_MCMDR fields */ +/* Software Reset */ +#define REG_MCMDR_SWR (1 << 24) +/* Internal Loopback Select */ +#define REG_MCMDR_LBK (1 << 21) +/* Operation Mode Select */ +#define REG_MCMDR_OPMOD (1 << 20) +/* Enable MDC Clock Generation */ +#define REG_MCMDR_ENMDC (1 << 19) +/* Full-Duplex Mode Select */ +#define REG_MCMDR_FDUP (1 << 18) +/* Enable SQE Checking */ +#define REG_MCMDR_ENSEQ (1 << 17) +/* Send PAUSE Frame */ +#define REG_MCMDR_SDPZ (1 << 16) +/* No Defer */ +#define REG_MCMDR_NDEF (1 << 9) +/* Frame Transmission On */ +#define REG_MCMDR_TXON (1 << 8) +/* Strip CRC Checksum */ +#define REG_MCMDR_SPCRC (1 << 5) +/* Accept CRC Error Packet */ +#define REG_MCMDR_AEP (1 << 4) +/* Accept Control Packet */ +#define REG_MCMDR_ACP (1 << 3) +/* Accept Runt Packet */ +#define REG_MCMDR_ARP (1 << 2) +/* Accept Long Packet */ +#define REG_MCMDR_ALP (1 << 1) +/* Frame Reception On */ +#define REG_MCMDR_RXON (1 << 0) + +/* REG_MIEN fields */ +/* Enable Transmit Descriptor Unavailable Interrupt */ +#define REG_MIEN_ENTDU (1 << 23) +/* Enable Transmit Completion Interrupt */ +#define REG_MIEN_ENTXCP (1 << 18) +/* Enable Transmit Interrupt */ +#define REG_MIEN_ENTXINTR (1 << 16) +/* Enable Receive Descriptor Unavailable Interrupt */ +#define REG_MIEN_ENRDU (1 << 10) +/* Enable Receive Good Interrupt */ +#define REG_MIEN_ENRXGD (1 << 4) +/* Enable Receive Interrupt */ +#define REG_MIEN_ENRXINTR (1 << 0) + +/* REG_MISTA fields */ +/* TODO: Add error fields and support simulated errors? */ +/* Transmit Bus Error Interrupt */ +#define REG_MISTA_TXBERR (1 << 24) +/* Transmit Descriptor Unavailable Interrupt */ +#define REG_MISTA_TDU (1 << 23) +/* Transmit Completion Interrupt */ +#define REG_MISTA_TXCP (1 << 18) +/* Transmit Interrupt */ +#define REG_MISTA_TXINTR (1 << 16) +/* Receive Bus Error Interrupt */ +#define REG_MISTA_RXBERR (1 << 11) +/* Receive Descriptor Unavailable Interrupt */ +#define REG_MISTA_RDU (1 << 10) +/* DMA Early Notification Interrupt */ +#define REG_MISTA_DENI (1 << 9) +/* Maximum Frame Length Interrupt */ +#define REG_MISTA_DFOI (1 << 8) +/* Receive Good Interrupt */ +#define REG_MISTA_RXGD (1 << 4) +/* Packet Too Long Interrupt */ +#define REG_MISTA_PTLE (1 << 3) +/* Receive Interrupt */ +#define REG_MISTA_RXINTR (1 << 0) + +/* REG_MGSTA fields */ +/* Transmission Halted */ +#define REG_MGSTA_TXHA (1 << 11) +/* Receive Halted */ +#define REG_MGSTA_RXHA (1 << 11) + +/* REG_DMARFC fields */ +/* Maximum Receive Frame Length */ +#define REG_DMARFC_RXMS(word) extract32((word), 0, 16) + +/* REG MIIDA fields */ +/* Busy Bit */ +#define REG_MIIDA_BUSY (1 << 17) + +/* Transmit and receive descriptors */ +typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc; +typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc; + +struct NPCM7xxEMCTxDesc { + uint32_t flags; + uint32_t txbsa; + uint32_t status_and_length; + uint32_t ntxdsa; +}; + +struct NPCM7xxEMCRxDesc { + uint32_t status_and_length; + uint32_t rxbsa; + uint32_t reserved; + uint32_t nrxdsa; +}; + +/* NPCM7xxEMCTxDesc.flags values */ +/* Owner: 0 =3D cpu, 1 =3D emc */ +#define TX_DESC_FLAG_OWNER_MASK (1 << 31) +/* Transmit interrupt enable */ +#define TX_DESC_FLAG_INTEN (1 << 2) +/* CRC append */ +#define TX_DESC_FLAG_CRCAPP (1 << 1) +/* Padding enable */ +#define TX_DESC_FLAG_PADEN (1 << 0) + +/* NPCM7xxEMCTxDesc.status_and_length values */ +/* Collision count */ +#define TX_DESC_STATUS_CCNT_SHIFT 28 +#define TX_DESC_STATUS_CCNT_BITSIZE 4 +/* SQE error */ +#define TX_DESC_STATUS_SQE (1 << 26) +/* Transmission paused */ +#define TX_DESC_STATUS_PAU (1 << 25) +/* P transmission halted */ +#define TX_DESC_STATUS_TXHA (1 << 24) +/* Late collision */ +#define TX_DESC_STATUS_LC (1 << 23) +/* Transmission abort */ +#define TX_DESC_STATUS_TXABT (1 << 22) +/* No carrier sense */ +#define TX_DESC_STATUS_NCS (1 << 21) +/* Defer exceed */ +#define TX_DESC_STATUS_EXDEF (1 << 20) +/* Transmission complete */ +#define TX_DESC_STATUS_TXCP (1 << 19) +/* Transmission deferred */ +#define TX_DESC_STATUS_DEF (1 << 17) +/* Transmit interrupt */ +#define TX_DESC_STATUS_TXINTR (1 << 16) + +#define TX_DESC_PKT_LEN(word) extract32((word), 0, 16) + +/* Transmit buffer start address */ +#define TX_DESC_TXBSA(word) ((uint32_t) (word) & ~3u) + +/* Next transmit descriptor start address */ +#define TX_DESC_NTXDSA(word) ((uint32_t) (word) & ~3u) + +/* NPCM7xxEMCRxDesc.status_and_length values */ +/* Owner: 0b00 =3D cpu, 0b01 =3D undefined, 0b10 =3D emc, 0b11 =3D undefin= ed */ +#define RX_DESC_STATUS_OWNER_SHIFT 30 +#define RX_DESC_STATUS_OWNER_BITSIZE 2 +#define RX_DESC_STATUS_OWNER_MASK (3 << RX_DESC_STATUS_OWNER_SHIFT) +/* Runt packet */ +#define RX_DESC_STATUS_RP (1 << 22) +/* Alignment error */ +#define RX_DESC_STATUS_ALIE (1 << 21) +/* Frame reception complete */ +#define RX_DESC_STATUS_RXGD (1 << 20) +/* Packet too long */ +#define RX_DESC_STATUS_PTLE (1 << 19) +/* CRC error */ +#define RX_DESC_STATUS_CRCE (1 << 17) +/* Receive interrupt */ +#define RX_DESC_STATUS_RXINTR (1 << 16) + +#define RX_DESC_PKT_LEN(word) extract32((word), 0, 16) + +/* Receive buffer start address */ +#define RX_DESC_RXBSA(word) ((uint32_t) (word) & ~3u) + +/* Next receive descriptor start address */ +#define RX_DESC_NRXDSA(word) ((uint32_t) (word) & ~3u) + +/* Minimum packet length, when TX_DESC_FLAG_PADEN is set. */ +#define MIN_PACKET_LENGTH 64 + +struct NPCM7xxEMCState { + /*< private >*/ + SysBusDevice parent; + /*< public >*/ + + MemoryRegion iomem; + + qemu_irq tx_irq; + qemu_irq rx_irq; + + NICState *nic; + NICConf conf; + + /* 0 or 1, for log messages */ + uint8_t emc_num; + + uint32_t regs[NPCM7XX_NUM_EMC_REGS]; + + /* + * tx is active. Set to true by TSDR and then switches off when out of + * descriptors. If the TXON bit in REG_MCMDR is off then this is off. + */ + bool tx_active; + + /* + * rx is active. Set to true by RSDR and then switches off when out of + * descriptors. If the RXON bit in REG_MCMDR is off then this is off. + */ + bool rx_active; +}; + +typedef struct NPCM7xxEMCState NPCM7xxEMCState; + +#define TYPE_NPCM7XX_EMC "npcm7xx-emc" +#define NPCM7XX_EMC(obj) \ + OBJECT_CHECK(NPCM7xxEMCState, (obj), TYPE_NPCM7XX_EMC) + +#endif /* NPCM7XX_EMC_H */ diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c new file mode 100644 index 00000000000..714a742ba7a --- /dev/null +++ b/hw/net/npcm7xx_emc.c @@ -0,0 +1,857 @@ +/* + * Nuvoton NPCM7xx EMC Module + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * Unsupported/unimplemented features: + * - MCMDR.FDUP (full duplex) is ignored, half duplex is not supported + * - Only CAM0 is supported, CAM[1-15] are not + * - writes to CAMEN.[1-15] are ignored, these bits always read as zeroes + * - MII is not implemented, MIIDA.BUSY and MIID always return zero + * - MCMDR.LBK is not implemented + * - MCMDR.{OPMOD,ENSQE,AEP,ARP} are not supported + * - H/W FIFOs are not supported, MCMDR.FFTCR is ignored + * - MGSTA.SQE is not supported + * - pause and control frames are not implemented + * - MGSTA.CCNT is not supported + * - MPCNT, DMARFS are not implemented + */ + +#include "qemu/osdep.h" + +/* For crc32 */ +#include + +#include "qemu-common.h" +#include "hw/irq.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-properties.h" +#include "hw/net/npcm7xx_emc.h" +#include "net/eth.h" +#include "migration/vmstate.h" +#include "qemu/bitops.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/units.h" +#include "sysemu/dma.h" +#include "trace.h" + +#define CRC_LENGTH 4 + +/* + * The maximum size of a (layer 2) ethernet frame as defined by 802.3. + * 1518 =3D 6(dest macaddr) + 6(src macaddr) + 2(proto) + 4(crc) + 1500(pa= yload) + * This does not include an additional 4 for the vlan field (802.1q). + */ +#define MAX_ETH_FRAME_SIZE 1518 + +static const char *emc_reg_name(int regno) +{ +#define REG(name) case REG_ ## name: return #name; + switch (regno) { + REG(CAMCMR) + REG(CAMEN) + REG(TXDLSA) + REG(RXDLSA) + REG(MCMDR) + REG(MIID) + REG(MIIDA) + REG(FFTCR) + REG(TSDR) + REG(RSDR) + REG(DMARFC) + REG(MIEN) + REG(MISTA) + REG(MGSTA) + REG(MPCNT) + REG(MRPC) + REG(MRPCC) + REG(MREPC) + REG(DMARFS) + REG(CTXDSA) + REG(CTXBSA) + REG(CRXDSA) + REG(CRXBSA) + case REG_CAMM_BASE + 0: return "CAM0M"; + case REG_CAML_BASE + 0: return "CAM0L"; + case REG_CAMM_BASE + 2 ... REG_CAMML_LAST: + /* Only CAM0 is supported, fold the others into something simple. = */ + if (regno & 1) { + return "CAML"; + } else { + return "CAMM"; + } + default: return "UNKNOWN"; + } +#undef REG +} + +static void emc_reset(NPCM7xxEMCState *emc) +{ + trace_npcm7xx_emc_reset(emc->emc_num); + + memset(&emc->regs[0], 0, sizeof(emc->regs)); + + /* These regs have non-zero reset values. */ + emc->regs[REG_TXDLSA] =3D 0xfffffffc; + emc->regs[REG_RXDLSA] =3D 0xfffffffc; + emc->regs[REG_MIIDA] =3D 0x00900000; + emc->regs[REG_FFTCR] =3D 0x0101; + emc->regs[REG_DMARFC] =3D 0x0800; + emc->regs[REG_MPCNT] =3D 0x7fff; + + emc->tx_active =3D false; + emc->rx_active =3D false; +} + +static void npcm7xx_emc_reset(DeviceState *dev) +{ + NPCM7xxEMCState *emc =3D NPCM7XX_EMC(dev); + emc_reset(emc); +} + +static void emc_soft_reset(NPCM7xxEMCState *emc) +{ + /* + * The docs say at least MCMDR.{LBK,OPMOD} bits are not changed during= a + * soft reset, but does not go into further detail. For now, KISS. + */ + uint32_t mcmdr =3D emc->regs[REG_MCMDR]; + emc_reset(emc); + emc->regs[REG_MCMDR] =3D mcmdr & (REG_MCMDR_LBK | REG_MCMDR_OPMOD); + + qemu_set_irq(emc->tx_irq, 0); + qemu_set_irq(emc->rx_irq, 0); +} + +static void emc_set_link(NetClientState *nc) +{ + /* Nothing to do yet. */ +} + +/* MISTA.TXINTR is the union of the individual bits with their enables. */ +static void emc_update_mista_txintr(NPCM7xxEMCState *emc) +{ + /* Only look at the bits we support. */ + uint32_t mask =3D (REG_MISTA_TXBERR | + REG_MISTA_TDU | + REG_MISTA_TXCP); + if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & mask) { + emc->regs[REG_MISTA] |=3D REG_MISTA_TXINTR; + } else { + emc->regs[REG_MISTA] &=3D ~REG_MISTA_TXINTR; + } +} + +/* MISTA.RXINTR is the union of the individual bits with their enables. */ +static void emc_update_mista_rxintr(NPCM7xxEMCState *emc) +{ + /* Only look at the bits we support. */ + uint32_t mask =3D (REG_MISTA_RXBERR | + REG_MISTA_RDU | + REG_MISTA_RXGD); + if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & mask) { + emc->regs[REG_MISTA] |=3D REG_MISTA_RXINTR; + } else { + emc->regs[REG_MISTA] &=3D ~REG_MISTA_RXINTR; + } +} + +/* N.B. emc_update_mista_txintr must have already been called. */ +static void emc_update_tx_irq(NPCM7xxEMCState *emc) +{ + int level =3D !!(emc->regs[REG_MISTA] & + emc->regs[REG_MIEN] & + REG_MISTA_TXINTR); + trace_npcm7xx_emc_update_tx_irq(level); + qemu_set_irq(emc->tx_irq, level); +} + +/* N.B. emc_update_mista_rxintr must have already been called. */ +static void emc_update_rx_irq(NPCM7xxEMCState *emc) +{ + int level =3D !!(emc->regs[REG_MISTA] & + emc->regs[REG_MIEN] & + REG_MISTA_RXINTR); + trace_npcm7xx_emc_update_rx_irq(level); + qemu_set_irq(emc->rx_irq, level); +} + +/* Update IRQ states due to changes in MIEN,MISTA. */ +static void emc_update_irq_from_reg_change(NPCM7xxEMCState *emc) +{ + emc_update_mista_txintr(emc); + emc_update_tx_irq(emc); + + emc_update_mista_rxintr(emc); + emc_update_rx_irq(emc); +} + +static int emc_read_tx_desc(dma_addr_t addr, NPCM7xxEMCTxDesc *desc) +{ + if (dma_memory_read(&address_space_memory, addr, desc, sizeof(*desc)))= { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x= %" + HWADDR_PRIx "\n", __func__, addr); + return -1; + } + desc->flags =3D le32_to_cpu(desc->flags); + desc->txbsa =3D le32_to_cpu(desc->txbsa); + desc->status_and_length =3D le32_to_cpu(desc->status_and_length); + desc->ntxdsa =3D le32_to_cpu(desc->ntxdsa); + return 0; +} + +static int emc_write_tx_desc(const NPCM7xxEMCTxDesc *desc, dma_addr_t addr) +{ + NPCM7xxEMCTxDesc le_desc; + + le_desc.flags =3D cpu_to_le32(desc->flags); + le_desc.txbsa =3D cpu_to_le32(desc->txbsa); + le_desc.status_and_length =3D cpu_to_le32(desc->status_and_length); + le_desc.ntxdsa =3D cpu_to_le32(desc->ntxdsa); + if (dma_memory_write(&address_space_memory, addr, &le_desc, + sizeof(le_desc))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0= x%" + HWADDR_PRIx "\n", __func__, addr); + return -1; + } + return 0; +} + +static int emc_read_rx_desc(dma_addr_t addr, NPCM7xxEMCRxDesc *desc) +{ + if (dma_memory_read(&address_space_memory, addr, desc, sizeof(*desc)))= { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x= %" + HWADDR_PRIx "\n", __func__, addr); + return -1; + } + desc->status_and_length =3D le32_to_cpu(desc->status_and_length); + desc->rxbsa =3D le32_to_cpu(desc->rxbsa); + desc->reserved =3D le32_to_cpu(desc->reserved); + desc->nrxdsa =3D le32_to_cpu(desc->nrxdsa); + return 0; +} + +static int emc_write_rx_desc(const NPCM7xxEMCRxDesc *desc, dma_addr_t addr) +{ + NPCM7xxEMCRxDesc le_desc; + + le_desc.status_and_length =3D cpu_to_le32(desc->status_and_length); + le_desc.rxbsa =3D cpu_to_le32(desc->rxbsa); + le_desc.reserved =3D cpu_to_le32(desc->reserved); + le_desc.nrxdsa =3D cpu_to_le32(desc->nrxdsa); + if (dma_memory_write(&address_space_memory, addr, &le_desc, + sizeof(le_desc))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0= x%" + HWADDR_PRIx "\n", __func__, addr); + return -1; + } + return 0; +} + +static void emc_set_mista(NPCM7xxEMCState *emc, uint32_t flags) +{ + trace_npcm7xx_emc_set_mista(flags); + emc->regs[REG_MISTA] |=3D flags; + if (extract32(flags, 16, 16)) { + emc_update_mista_txintr(emc); + } + if (extract32(flags, 0, 16)) { + emc_update_mista_rxintr(emc); + } +} + +static void emc_halt_tx(NPCM7xxEMCState *emc, uint32_t mista_flag) +{ + emc->tx_active =3D false; + emc_set_mista(emc, mista_flag); +} + +static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t mista_flag) +{ + emc->rx_active =3D false; + emc_set_mista(emc, mista_flag); +} + +static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc, + const NPCM7xxEMCTxDesc *tx_desc, + uint32_t desc_addr) +{ + /* Update the current descriptor, if only to reset the owner flag. */ + if (emc_write_tx_desc(tx_desc, desc_addr)) { + /* + * We just read it so this shouldn't generally happen. + * Error already reported. + */ + emc_set_mista(emc, REG_MISTA_TXBERR); + } + emc->regs[REG_CTXDSA] =3D TX_DESC_NTXDSA(tx_desc->ntxdsa); +} + +static void emc_set_next_rx_descriptor(NPCM7xxEMCState *emc, + const NPCM7xxEMCRxDesc *rx_desc, + uint32_t desc_addr) +{ + /* Update the current descriptor, if only to reset the owner flag. */ + if (emc_write_rx_desc(rx_desc, desc_addr)) { + /* + * We just read it so this shouldn't generally happen. + * Error already reported. + */ + emc_set_mista(emc, REG_MISTA_RXBERR); + } + emc->regs[REG_CRXDSA] =3D RX_DESC_NRXDSA(rx_desc->nrxdsa); +} + +static void emc_try_send_next_packet(NPCM7xxEMCState *emc) +{ + /* Working buffer for sending out packets. Most packets fit in this. */ +#define TX_BUFFER_SIZE 2048 + uint8_t tx_send_buffer[TX_BUFFER_SIZE]; + uint32_t desc_addr =3D TX_DESC_NTXDSA(emc->regs[REG_CTXDSA]); + NPCM7xxEMCTxDesc tx_desc; + uint32_t next_buf_addr, length; + uint8_t *buf; + g_autofree uint8_t *malloced_buf =3D NULL; + + if (emc_read_tx_desc(desc_addr, &tx_desc)) { + /* Error reading descriptor, already reported. */ + emc_halt_tx(emc, REG_MISTA_TXBERR); + emc_update_tx_irq(emc); + return; + } + + /* Nothing we can do if we don't own the descriptor. */ + if (!(tx_desc.flags & TX_DESC_FLAG_OWNER_MASK)) { + trace_npcm7xx_emc_cpu_owned_desc(desc_addr); + emc_halt_tx(emc, REG_MISTA_TDU); + emc_update_tx_irq(emc); + return; + } + + /* Give the descriptor back regardless of what happens. */ + tx_desc.flags &=3D ~TX_DESC_FLAG_OWNER_MASK; + tx_desc.status_and_length &=3D 0xffff; + + /* + * Despite the h/w documentation saying the tx buffer is word aligned, + * the linux driver does not word align the buffer. There is value in = not + * aligning the buffer: See the description of NET_IP_ALIGN in linux + * kernel sources. + */ + next_buf_addr =3D tx_desc.txbsa; + emc->regs[REG_CTXBSA] =3D next_buf_addr; + length =3D TX_DESC_PKT_LEN(tx_desc.status_and_length); + buf =3D &tx_send_buffer[0]; + + if (length > sizeof(tx_send_buffer)) { + malloced_buf =3D g_malloc(length); + buf =3D malloced_buf; + } + + if (dma_memory_read(&address_space_memory, next_buf_addr, buf, length)= ) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read packet @ 0x%x\n= ", + __func__, next_buf_addr); + emc_set_mista(emc, REG_MISTA_TXBERR); + emc_set_next_tx_descriptor(emc, &tx_desc, desc_addr); + emc_update_tx_irq(emc); + trace_npcm7xx_emc_tx_done(emc->regs[REG_CTXDSA]); + return; + } + + if ((tx_desc.flags & TX_DESC_FLAG_PADEN) && (length < MIN_PACKET_LENGT= H)) { + memset(buf + length, 0, MIN_PACKET_LENGTH - length); + length =3D MIN_PACKET_LENGTH; + } + + /* N.B. emc_receive can get called here. */ + qemu_send_packet(qemu_get_queue(emc->nic), buf, length); + trace_npcm7xx_emc_sent_packet(length); + + tx_desc.status_and_length |=3D TX_DESC_STATUS_TXCP; + if (tx_desc.flags & TX_DESC_FLAG_INTEN) { + emc_set_mista(emc, REG_MISTA_TXCP); + } + if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & REG_MISTA_TXINTR) { + tx_desc.status_and_length |=3D TX_DESC_STATUS_TXINTR; + } + + emc_set_next_tx_descriptor(emc, &tx_desc, desc_addr); + emc_update_tx_irq(emc); + trace_npcm7xx_emc_tx_done(emc->regs[REG_CTXDSA]); +} + +static bool emc_can_receive(NetClientState *nc) +{ + NPCM7xxEMCState *emc =3D NPCM7XX_EMC(qemu_get_nic_opaque(nc)); + + bool can_receive =3D emc->rx_active; + trace_npcm7xx_emc_can_receive(can_receive); + return can_receive; +} + +/* If result is false then *fail_reason contains the reason. */ +static bool emc_receive_filter1(NPCM7xxEMCState *emc, const uint8_t *buf, + size_t len, const char **fail_reason) +{ + eth_pkt_types_e pkt_type =3D get_eth_packet_type(PKT_GET_ETH_HDR(buf)); + + switch (pkt_type) { + case ETH_PKT_BCAST: + if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) { + return true; + } else { + *fail_reason =3D "Broadcast packet disabled"; + return !!(emc->regs[REG_CAMCMR] & REG_CAMCMR_ABP); + } + case ETH_PKT_MCAST: + if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) { + return true; + } else { + *fail_reason =3D "Multicast packet disabled"; + return !!(emc->regs[REG_CAMCMR] & REG_CAMCMR_AMP); + } + case ETH_PKT_UCAST: { + bool matches; + if (emc->regs[REG_CAMCMR] & REG_CAMCMR_AUP) { + return true; + } + matches =3D ((emc->regs[REG_CAMCMR] & REG_CAMCMR_ECMP) && + /* We only support one CAM register, CAM0. */ + (emc->regs[REG_CAMEN] & (1 << 0)) && + memcmp(buf, emc->conf.macaddr.a, ETH_ALEN) =3D=3D 0); + if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) { + *fail_reason =3D "MACADDR matched, comparison complemented"; + return !matches; + } else { + *fail_reason =3D "MACADDR didn't match"; + return matches; + } + } + default: + g_assert_not_reached(); + } +} + +static bool emc_receive_filter(NPCM7xxEMCState *emc, const uint8_t *buf, + size_t len) +{ + const char *fail_reason =3D NULL; + bool ok =3D emc_receive_filter1(emc, buf, len, &fail_reason); + if (!ok) { + trace_npcm7xx_emc_packet_filtered_out(fail_reason); + } + return ok; +} + +static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t = len1) +{ + NPCM7xxEMCState *emc =3D NPCM7XX_EMC(qemu_get_nic_opaque(nc)); + const uint32_t len =3D len1; + size_t max_frame_len; + bool long_frame; + uint32_t desc_addr; + NPCM7xxEMCRxDesc rx_desc; + uint32_t crc; + uint8_t *crc_ptr; + uint32_t buf_addr; + + trace_npcm7xx_emc_receiving_packet(len); + + if (!emc_can_receive(nc)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Unexpected packet\n", __func__= ); + return -1; + } + + if (len < ETH_HLEN || + /* Defensive programming: drop unsupportable large packets. */ + len > 0xffff - CRC_LENGTH) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Dropped frame of %u bytes\n", + __func__, len); + return len; + } + + /* + * DENI is set if EMC received the Length/Type field of the incoming + * packet, so it will be set regardless of what happens next. + */ + emc_set_mista(emc, REG_MISTA_DENI); + + if (!emc_receive_filter(emc, buf, len)) { + emc_update_rx_irq(emc); + return len; + } + + /* Huge frames (> DMARFC) are dropped. */ + max_frame_len =3D REG_DMARFC_RXMS(emc->regs[REG_DMARFC]); + if (len + CRC_LENGTH > max_frame_len) { + trace_npcm7xx_emc_packet_dropped(len); + emc_set_mista(emc, REG_MISTA_DFOI); + emc_update_rx_irq(emc); + return len; + } + + /* + * Long Frames (> MAX_ETH_FRAME_SIZE) are also dropped, unless MCMDR.A= LP + * is set. + */ + long_frame =3D false; + if (len + CRC_LENGTH > MAX_ETH_FRAME_SIZE) { + if (emc->regs[REG_MCMDR] & REG_MCMDR_ALP) { + long_frame =3D true; + } else { + trace_npcm7xx_emc_packet_dropped(len); + emc_set_mista(emc, REG_MISTA_PTLE); + emc_update_rx_irq(emc); + return len; + } + } + + desc_addr =3D RX_DESC_NRXDSA(emc->regs[REG_CRXDSA]); + if (emc_read_rx_desc(desc_addr, &rx_desc)) { + /* Error reading descriptor, already reported. */ + emc_halt_rx(emc, REG_MISTA_RXBERR); + emc_update_rx_irq(emc); + return len; + } + + /* Nothing we can do if we don't own the descriptor. */ + if (!(rx_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK)) { + trace_npcm7xx_emc_cpu_owned_desc(desc_addr); + emc_halt_rx(emc, REG_MISTA_RDU); + emc_update_rx_irq(emc); + return len; + } + + crc =3D 0; + crc_ptr =3D (uint8_t *) &crc; + if (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC)) { + crc =3D cpu_to_be32(crc32(~0, buf, len)); + } + + /* Give the descriptor back regardless of what happens. */ + rx_desc.status_and_length &=3D ~RX_DESC_STATUS_OWNER_MASK; + + buf_addr =3D rx_desc.rxbsa; + emc->regs[REG_CRXBSA] =3D buf_addr; + if (dma_memory_write(&address_space_memory, buf_addr, buf, len) || + (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC) && + dma_memory_write(&address_space_memory, buf_addr + len, crc_ptr, + 4))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bus error writing packet\n", + __func__); + emc_set_mista(emc, REG_MISTA_RXBERR); + emc_set_next_rx_descriptor(emc, &rx_desc, desc_addr); + emc_update_rx_irq(emc); + trace_npcm7xx_emc_rx_done(emc->regs[REG_CRXDSA]); + return len; + } + + trace_npcm7xx_emc_received_packet(len); + + /* Note: We've already verified len+4 <=3D 0xffff. */ + rx_desc.status_and_length =3D len; + if (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC)) { + rx_desc.status_and_length +=3D 4; + } + rx_desc.status_and_length |=3D RX_DESC_STATUS_RXGD; + emc_set_mista(emc, REG_MISTA_RXGD); + + if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & REG_MISTA_RXINTR) { + rx_desc.status_and_length |=3D RX_DESC_STATUS_RXINTR; + } + if (long_frame) { + rx_desc.status_and_length |=3D RX_DESC_STATUS_PTLE; + } + + emc_set_next_rx_descriptor(emc, &rx_desc, desc_addr); + emc_update_rx_irq(emc); + trace_npcm7xx_emc_rx_done(emc->regs[REG_CRXDSA]); + return len; +} + +static void emc_try_receive_next_packet(NPCM7xxEMCState *emc) +{ + if (emc_can_receive(qemu_get_queue(emc->nic))) { + qemu_flush_queued_packets(qemu_get_queue(emc->nic)); + } +} + +static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned siz= e) +{ + NPCM7xxEMCState *emc =3D opaque; + uint32_t reg =3D offset / sizeof(uint32_t); + uint32_t result; + + if (reg >=3D NPCM7XX_NUM_EMC_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid offset 0x%04" HWADDR_PRIx "\n", + __func__, offset); + return 0; + } + + switch (reg) { + case REG_MIID: + /* + * We don't implement MII. For determinism, always return zero as + * writes record the last value written for debugging purposes. + */ + qemu_log_mask(LOG_UNIMP, "%s: Read of MIID, returning 0\n", __func= __); + result =3D 0; + break; + case REG_TSDR: + case REG_RSDR: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Read of write-only reg, %s/%d\n", + __func__, emc_reg_name(reg), reg); + return 0; + default: + result =3D emc->regs[reg]; + break; + } + + trace_npcm7xx_emc_reg_read(emc->emc_num, result, emc_reg_name(reg), re= g); + return result; +} + +static void npcm7xx_emc_write(void *opaque, hwaddr offset, + uint64_t v, unsigned size) +{ + NPCM7xxEMCState *emc =3D opaque; + uint32_t reg =3D offset / sizeof(uint32_t); + uint32_t value =3D v; + + g_assert(size =3D=3D sizeof(uint32_t)); + + if (reg >=3D NPCM7XX_NUM_EMC_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid offset 0x%04" HWADDR_PRIx "\n", + __func__, offset); + return; + } + + trace_npcm7xx_emc_reg_write(emc->emc_num, emc_reg_name(reg), reg, valu= e); + + switch (reg) { + case REG_CAMCMR: + emc->regs[reg] =3D value; + break; + case REG_CAMEN: + /* Only CAM0 is supported, don't pretend otherwise. */ + if (value & ~1) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Only CAM0 is supported, cannot enable other= s" + ": 0x%x\n", + __func__, value); + } + emc->regs[reg] =3D value & 1; + break; + case REG_CAMM_BASE + 0: + emc->regs[reg] =3D value; + emc->conf.macaddr.a[0] =3D value >> 24; + emc->conf.macaddr.a[1] =3D value >> 16; + emc->conf.macaddr.a[2] =3D value >> 8; + emc->conf.macaddr.a[3] =3D value >> 0; + break; + case REG_CAML_BASE + 0: + emc->regs[reg] =3D value; + emc->conf.macaddr.a[4] =3D value >> 24; + emc->conf.macaddr.a[5] =3D value >> 16; + break; + case REG_MCMDR: { + uint32_t prev; + if (value & REG_MCMDR_SWR) { + emc_soft_reset(emc); + /* On h/w the reset happens over multiple cycles. For now KISS= . */ + break; + } + prev =3D emc->regs[reg]; + emc->regs[reg] =3D value; + /* Update tx state. */ + if (!(prev & REG_MCMDR_TXON) && + (value & REG_MCMDR_TXON)) { + emc->regs[REG_CTXDSA] =3D emc->regs[REG_TXDLSA]; + /* + * Linux kernel turns TX on with CPU still holding descriptor, + * which suggests we should wait for a write to TSDR before tr= ying + * to send a packet: so we don't send one here. + */ + } else if ((prev & REG_MCMDR_TXON) && + !(value & REG_MCMDR_TXON)) { + emc->regs[REG_MGSTA] |=3D REG_MGSTA_TXHA; + } + if (!(value & REG_MCMDR_TXON)) { + emc_halt_tx(emc, 0); + } + /* Update rx state. */ + if (!(prev & REG_MCMDR_RXON) && + (value & REG_MCMDR_RXON)) { + emc->regs[REG_CRXDSA] =3D emc->regs[REG_RXDLSA]; + } else if ((prev & REG_MCMDR_RXON) && + !(value & REG_MCMDR_RXON)) { + emc->regs[REG_MGSTA] |=3D REG_MGSTA_RXHA; + } + if (!(value & REG_MCMDR_RXON)) { + emc_halt_rx(emc, 0); + } + break; + } + case REG_TXDLSA: + case REG_RXDLSA: + case REG_DMARFC: + case REG_MIID: + emc->regs[reg] =3D value; + break; + case REG_MIEN: + emc->regs[reg] =3D value; + emc_update_irq_from_reg_change(emc); + break; + case REG_MISTA: + /* Clear the bits that have 1 in "value". */ + emc->regs[reg] &=3D ~value; + emc_update_irq_from_reg_change(emc); + break; + case REG_MGSTA: + /* Clear the bits that have 1 in "value". */ + emc->regs[reg] &=3D ~value; + break; + case REG_TSDR: + if (emc->regs[REG_MCMDR] & REG_MCMDR_TXON) { + emc->tx_active =3D true; + /* Keep trying to send packets until we run out. */ + while (emc->tx_active) { + emc_try_send_next_packet(emc); + } + } + break; + case REG_RSDR: + if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) { + emc->rx_active =3D true; + emc_try_receive_next_packet(emc); + } + break; + case REG_MIIDA: + emc->regs[reg] =3D value & ~REG_MIIDA_BUSY; + break; + case REG_MRPC: + case REG_MRPCC: + case REG_MREPC: + case REG_CTXDSA: + case REG_CTXBSA: + case REG_CRXDSA: + case REG_CRXBSA: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Write to read-only reg %s/%d\n", + __func__, emc_reg_name(reg), reg); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: Write to unimplemented reg %s/%d\n", + __func__, emc_reg_name(reg), reg); + break; + } +} + +static const struct MemoryRegionOps npcm7xx_emc_ops =3D { + .read =3D npcm7xx_emc_read, + .write =3D npcm7xx_emc_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void emc_cleanup(NetClientState *nc) +{ + /* Nothing to do yet. */ +} + +static NetClientInfo net_npcm7xx_emc_info =3D { + .type =3D NET_CLIENT_DRIVER_NIC, + .size =3D sizeof(NICState), + .can_receive =3D emc_can_receive, + .receive =3D emc_receive, + .cleanup =3D emc_cleanup, + .link_status_changed =3D emc_set_link, +}; + +static void npcm7xx_emc_realize(DeviceState *dev, Error **errp) +{ + NPCM7xxEMCState *emc =3D NPCM7XX_EMC(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(emc); + + memory_region_init_io(&emc->iomem, OBJECT(emc), &npcm7xx_emc_ops, emc, + TYPE_NPCM7XX_EMC, 4 * KiB); + sysbus_init_mmio(sbd, &emc->iomem); + sysbus_init_irq(sbd, &emc->tx_irq); + sysbus_init_irq(sbd, &emc->rx_irq); + + qemu_macaddr_default_if_unset(&emc->conf.macaddr); + emc->nic =3D qemu_new_nic(&net_npcm7xx_emc_info, &emc->conf, + object_get_typename(OBJECT(dev)), dev->id, emc= ); + qemu_format_nic_info_str(qemu_get_queue(emc->nic), emc->conf.macaddr.a= ); +} + +static void npcm7xx_emc_unrealize(DeviceState *dev) +{ + NPCM7xxEMCState *emc =3D NPCM7XX_EMC(dev); + + qemu_del_nic(emc->nic); +} + +static const VMStateDescription vmstate_npcm7xx_emc =3D { + .name =3D TYPE_NPCM7XX_EMC, + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8(emc_num, NPCM7xxEMCState), + VMSTATE_UINT32_ARRAY(regs, NPCM7xxEMCState, NPCM7XX_NUM_EMC_REGS), + VMSTATE_BOOL(tx_active, NPCM7xxEMCState), + VMSTATE_BOOL(rx_active, NPCM7xxEMCState), + VMSTATE_END_OF_LIST(), + }, +}; + +static Property npcm7xx_emc_properties[] =3D { + DEFINE_NIC_PROPERTIES(NPCM7xxEMCState, conf), + DEFINE_PROP_END_OF_LIST(), +}; + +static void npcm7xx_emc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); + dc->desc =3D "NPCM7xx EMC Controller"; + dc->realize =3D npcm7xx_emc_realize; + dc->unrealize =3D npcm7xx_emc_unrealize; + dc->reset =3D npcm7xx_emc_reset; + dc->vmsd =3D &vmstate_npcm7xx_emc; + device_class_set_props(dc, npcm7xx_emc_properties); +} + +static const TypeInfo npcm7xx_emc_info =3D { + .name =3D TYPE_NPCM7XX_EMC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NPCM7xxEMCState), + .class_init =3D npcm7xx_emc_class_init, +}; + +static void npcm7xx_emc_register_type(void) +{ + type_register_static(&npcm7xx_emc_info); +} + +type_init(npcm7xx_emc_register_type) diff --git a/hw/net/meson.build b/hw/net/meson.build index 4a7051b54a0..af0749c42bb 100644 --- a/hw/net/meson.build +++ b/hw/net/meson.build @@ -35,6 +35,7 @@ softmmu_ss.add(when: 'CONFIG_I82596_COMMON', if_true: fil= es('i82596.c')) softmmu_ss.add(when: 'CONFIG_SUNHME', if_true: files('sunhme.c')) softmmu_ss.add(when: 'CONFIG_FTGMAC100', if_true: files('ftgmac100.c')) softmmu_ss.add(when: 'CONFIG_SUNGEM', if_true: files('sungem.c')) +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_emc.c')) =20 softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_eth.c')) softmmu_ss.add(when: 'CONFIG_COLDFIRE', if_true: files('mcf_fec.c')) diff --git a/hw/net/trace-events b/hw/net/trace-events index 5db45456d92..baf25ffa7e7 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -429,3 +429,20 @@ imx_fec_receive_last(int last) "rx frame flags 0x%04x" imx_enet_receive(size_t size) "len %zu" imx_enet_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d" imx_enet_receive_last(int last) "rx frame flags 0x%04x" + +# npcm7xx_emc.c +npcm7xx_emc_reset(int emc_num) "Resetting emc%d" +npcm7xx_emc_update_tx_irq(int level) "Setting tx irq to %d" +npcm7xx_emc_update_rx_irq(int level) "Setting rx irq to %d" +npcm7xx_emc_set_mista(uint32_t flags) "ORing 0x%x into MISTA" +npcm7xx_emc_cpu_owned_desc(uint32_t addr) "Can't process cpu-owned descrip= tor @0x%x" +npcm7xx_emc_sent_packet(uint32_t len) "Sent %u byte packet" +npcm7xx_emc_tx_done(uint32_t ctxdsa) "TX done, CTXDSA=3D0x%x" +npcm7xx_emc_can_receive(int can_receive) "Can receive: %d" +npcm7xx_emc_packet_filtered_out(const char* fail_reason) "Packet filtered = out: %s" +npcm7xx_emc_packet_dropped(uint32_t len) "%u byte packet dropped" +npcm7xx_emc_receiving_packet(uint32_t len) "Receiving %u byte packet" +npcm7xx_emc_received_packet(uint32_t len) "Received %u byte packet" +npcm7xx_emc_rx_done(uint32_t crxdsa) "RX done, CRXDSA=3D0x%x" +npcm7xx_emc_reg_read(int emc_num, uint32_t result, const char *name, int r= egno) "emc%d: 0x%x =3D reg[%s/%d]" +npcm7xx_emc_reg_write(int emc_num, const char *name, int regno, uint32_t v= alue) "emc%d: reg[%s/%d] =3D 0x%x" --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613494203387911.4154058315163; Tue, 16 Feb 2021 08:50:03 -0800 (PST) Received: from localhost ([::1]:51686 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3Y1-00017Q-RG for importer@patchew.org; Tue, 16 Feb 2021 11:50:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40976) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC33Q-0000Vs-MY for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:24 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:38554) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32Z-0002ZB-5A for qemu-devel@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7++HAIPf+kBQsOI8XyUWZnHk1HqjunJMxoWabmHNDsM=; b=be0rTGXjg7/DcttXy8vPzaTGzJ/cBQDN3KeIoOcCyK4ercsMkZcjLha98PSLFVB0gM qM8B2Iwtg5M4G9YAswhH3yiivvQsJ225eZkvJHfV68n56ZzGTygiMsP145kjdBbTKRx3 +nqDLsjhZe5lEmF3OiPxlE00h6QrHd1neE2nQ0Z1i9bw7KES+aMUkZ/P0/NTnRpJ5Uos apAZdZgFLVAXSt1Xh+q472EbCQgDSaGxe9U5VCNovsS/9SExqb9wkus1WzBVrYges72P tTWjqnrBOQx/gPBNE6fVqf0AKvBIEs5FlTUJonCx21jLOCAPdmU+x0lJSd7m48xLAP8q wz4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7++HAIPf+kBQsOI8XyUWZnHk1HqjunJMxoWabmHNDsM=; b=kM7i5RLi5REktIkdnR7cd/TmL7TufD/sMQ/odE770ocBvZCfjeFAtaYO/Oit0lXtC3 JrTRKy6sRaH15aNDkjx+C4cGno2mD1XFVZcYLYxGu+f2jm2X5ESWhJPalUb+ofFkupT9 +t0x6Nq6tBME3EY7DZy7CORBa7hyp+YI4AowvnoZXllGSb40Q/g+LJA3CE8FoOXmFiOV Sg+tA2yloxygJyPZULhHFNdTQqa04R5MraKhH49n5n4pX5U8Emv/c2tN7WkLAujtMIBZ mNBcl41WrZLCTr5t1iRSuLJfJ5B+hZQqbDsAX5pbI0tg2lwJ1ZZIyeE4CoygI0ulPTJ2 q4Ww== X-Gm-Message-State: AOAM533TrltG0s5bYOAWGbZzgIwCI3UyRmCpb+2aNnJ1Jpqs3gC4KnsT AZ9hnpqo4Zbnm72gWB16WDcGutJrQIZAJA== X-Google-Smtp-Source: ABdhPJztEADRee3qGLH2v0sc/KxF+BQVXS9lzjVNtPVlrQOvmOVph/f2fnhUHt3l5aowT7hK7e2JCA== X-Received: by 2002:a1c:28c1:: with SMTP id o184mr3713315wmo.183.1613492249522; Tue, 16 Feb 2021 08:17:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/40] hw/arm: Add npcm7xx emc model Date: Tue, 16 Feb 2021 16:16:57 +0000 Message-Id: <20210216161658.29881-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Doug Evans This is a 10/100 ethernet device that has several features. Only the ones needed by the Linux driver have been implemented. See npcm7xx_emc.c for a list of unimplemented features. Reviewed-by: Hao Wu Reviewed-by: Avi Fishman Reviewed-by: Peter Maydell Signed-off-by: Doug Evans Message-id: 20210213002520.1374134-3-dje@google.com Signed-off-by: Peter Maydell --- docs/system/arm/nuvoton.rst | 3 ++- include/hw/arm/npcm7xx.h | 2 ++ hw/arm/npcm7xx.c | 50 +++++++++++++++++++++++++++++++++++-- 3 files changed, 52 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index 34fc799b2df..f9fb9224da9 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -44,6 +44,7 @@ Supported devices * Analog to Digital Converter (ADC) * Pulse Width Modulation (PWM) * SMBus controller (SMBF) + * Ethernet controller (EMC) =20 Missing devices --------------- @@ -57,7 +58,7 @@ Missing devices * Shared memory (SHM) * eSPI slave interface =20 - * Ethernet controllers (GMAC and EMC) + * Ethernet controller (GMAC) * USB device (USBD) * Peripheral SPI controller (PSPI) * SD/MMC host diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index cea1bd1f620..d32849a456b 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -26,6 +26,7 @@ #include "hw/misc/npcm7xx_gcr.h" #include "hw/misc/npcm7xx_pwm.h" #include "hw/misc/npcm7xx_rng.h" +#include "hw/net/npcm7xx_emc.h" #include "hw/nvram/npcm7xx_otp.h" #include "hw/timer/npcm7xx_timer.h" #include "hw/ssi/npcm7xx_fiu.h" @@ -90,6 +91,7 @@ typedef struct NPCM7xxState { EHCISysBusState ehci; OHCISysBusState ohci; NPCM7xxFIUState fiu[2]; + NPCM7xxEMCState emc[2]; } NPCM7xxState; =20 #define TYPE_NPCM7XX "npcm7xx" diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index f8950f94708..9bd1e83f021 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -82,6 +82,8 @@ enum NPCM7xxInterrupt { NPCM7XX_UART1_IRQ, NPCM7XX_UART2_IRQ, NPCM7XX_UART3_IRQ, + NPCM7XX_EMC1RX_IRQ =3D 15, + NPCM7XX_EMC1TX_IRQ, NPCM7XX_TIMER0_IRQ =3D 32, /* Timer Module 0 */ NPCM7XX_TIMER1_IRQ, NPCM7XX_TIMER2_IRQ, @@ -120,6 +122,8 @@ enum NPCM7xxInterrupt { NPCM7XX_SMBUS15_IRQ, NPCM7XX_PWM0_IRQ =3D 93, /* PWM module 0 */ NPCM7XX_PWM1_IRQ, /* PWM module 1 */ + NPCM7XX_EMC2RX_IRQ =3D 114, + NPCM7XX_EMC2TX_IRQ, NPCM7XX_GPIO0_IRQ =3D 116, NPCM7XX_GPIO1_IRQ, NPCM7XX_GPIO2_IRQ, @@ -188,6 +192,12 @@ static const hwaddr npcm7xx_smbus_addr[] =3D { 0xf008f000, }; =20 +/* Register base address for each EMC Module */ +static const hwaddr npcm7xx_emc_addr[] =3D { + 0xf0825000, + 0xf0826000, +}; + static const struct { hwaddr regs_addr; uint32_t unconnected_pins; @@ -406,6 +416,10 @@ static void npcm7xx_init(Object *obj) for (i =3D 0; i < ARRAY_SIZE(s->pwm); i++) { object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PW= M); } + + for (i =3D 0; i < ARRAY_SIZE(s->emc); i++) { + object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EM= C); + } } =20 static void npcm7xx_realize(DeviceState *dev, Error **errp) @@ -589,6 +603,40 @@ static void npcm7xx_realize(DeviceState *dev, Error **= errp) sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i)); } =20 + /* + * EMC Modules. Cannot fail. + * The mapping of the device to its netdev backend works as follows: + * emc[i] =3D nd_table[i] + * This works around the inability to specify the netdev property for = the + * emc device: it's not pluggable and thus the -device option can't be + * used. + */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_emc_addr) !=3D ARRAY_SIZE(s->emc)= ); + QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->emc) !=3D 2); + for (i =3D 0; i < ARRAY_SIZE(s->emc); i++) { + s->emc[i].emc_num =3D i; + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->emc[i]); + if (nd_table[i].used) { + qemu_check_nic_model(&nd_table[i], TYPE_NPCM7XX_EMC); + qdev_set_nic_properties(DEVICE(sbd), &nd_table[i]); + } + /* + * The device exists regardless of whether it's connected to a QEMU + * netdev backend. So always instantiate it even if there is no + * backend. + */ + sysbus_realize(sbd, &error_abort); + sysbus_mmio_map(sbd, 0, npcm7xx_emc_addr[i]); + int tx_irq =3D i =3D=3D 0 ? NPCM7XX_EMC1TX_IRQ : NPCM7XX_EMC2TX_IR= Q; + int rx_irq =3D i =3D=3D 0 ? NPCM7XX_EMC1RX_IRQ : NPCM7XX_EMC2RX_IR= Q; + /* + * N.B. The values for the second argument sysbus_connect_irq are + * chosen to match the registration order in npcm7xx_emc_realize. + */ + sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, tx_irq)); + sysbus_connect_irq(sbd, 1, npcm7xx_irq(s, rx_irq)); + } + /* * Flash Interface Unit (FIU). Can fail if incorrect number of chip se= lects * specified, but this is a programming error. @@ -649,8 +697,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **e= rrp) create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * = KiB); create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * = KiB); create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * = KiB); - create_unimplemented_device("npcm7xx.emc1", 0xf0825000, 4 * = KiB); - create_unimplemented_device("npcm7xx.emc2", 0xf0826000, 4 * = KiB); create_unimplemented_device("npcm7xx.usbd[0]", 0xf0830000, 4 * = KiB); create_unimplemented_device("npcm7xx.usbd[1]", 0xf0831000, 4 * = KiB); create_unimplemented_device("npcm7xx.usbd[2]", 0xf0832000, 4 * = KiB); --=20 2.20.1 From nobody Wed Apr 24 16:25:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613494108930279.5997144202329; Tue, 16 Feb 2021 08:48:28 -0800 (PST) Received: from localhost ([::1]:47968 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lC3WU-0007t1-5A for importer@patchew.org; Tue, 16 Feb 2021 11:48:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41020) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lC33U-0000aU-Sf for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:28 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:37924) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lC32a-0002ZM-LA for qemu-devel@nongnu.org; Tue, 16 Feb 2021 11:18:27 -0500 Received: by mail-wr1-x42d.google.com with SMTP id b3so13781022wrj.5 for ; Tue, 16 Feb 2021 08:17:32 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d5sm30630482wrb.14.2021.02.16.08.17.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Feb 2021 08:17:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Qiq8axp4iQT5bjc5ra+O5yf3fOap+X0+eOreHTSM218=; b=Cqtwl56v4HcIL8VlXd/WBgwnif0AFQ4Bbw88/8+202z5DHPPZEaA+VW9qGbATqdeVd BWxhwSx2KFiYruJ8HWvF2X5axCAtfeL/QI7K+B4D7WTRq/ZypDXTaQUJ8QQxjvRLxGqF 16KKiHDZAdRepqP2y6WVlm3G/Ao9w7FnXY/zTlaRBprQUfassyd98t7d/80v5PDGYKHc 0wdwC827h+zoLc3SqrtU8u45kykfed0T4bIfyG9EuOe7q5vYeMctVbevUNWVRbpmbWsz KHvA9iy9gLuNurR0YGHvrGg5B4EybSYSbFRcPeMC6jrVP7jxUC9AXJn4W2RAuoO7wJUm iq6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Qiq8axp4iQT5bjc5ra+O5yf3fOap+X0+eOreHTSM218=; b=mTk1VZTjpYXbquROgv+jA7svawp9QHyd4XjkntPgyafMdzFtztJr5MOAawaorqe7jU bq5ZIf4tZzGyApcmaOuOrixeHotXEbT2HjCgg6KgLYDIcBA4Ra+3Qxa/26JYrS+RaLxu b+dpgnaXsC3SUusiS+RDcyJ5XMRjyuFTSNzTgEAWUvFA22pdggIJMz07cZ9L6SD10f5J ZLiyO5L6ySIaIbN9esRfW2hyoyzXYkidCMQpuHTAyJUYnIp9DtiyBFBndSM39GfDh8q2 KT6aAZGiB04pYPQp6M5QsbZDRrg5+mNLGsEFOKIfRvdu+tcGD/uOMObQS43WhTF0ZkQg HoEQ== X-Gm-Message-State: AOAM533t5U7M4hN+2SS5APsEZqTzR/UmBDifvxVHG5zruW/8/odAul3S KQjGx+NU1jpbWMB9U9LBTO4xiwhTGx8XyA== X-Google-Smtp-Source: ABdhPJw0x7fUnKcdT/G+iJrBR2t0V3hPIsHvWNZd+/CDn+KiIAt1IyzSLL86AyOVFZfdE8yGA5JWJg== X-Received: by 2002:adf:e94c:: with SMTP id m12mr25316898wrn.146.1613492250692; Tue, 16 Feb 2021 08:17:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/40] tests/qtests: Add npcm7xx emc model test Date: Tue, 16 Feb 2021 16:16:58 +0000 Message-Id: <20210216161658.29881-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210216161658.29881-1-peter.maydell@linaro.org> References: <20210216161658.29881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Doug Evans Reviewed-by: Hao Wu Reviewed-by: Avi Fishman Reviewed-by: Peter Maydell Signed-off-by: Doug Evans Message-id: 20210213002520.1374134-4-dje@google.com Signed-off-by: Peter Maydell --- tests/qtest/npcm7xx_emc-test.c | 862 +++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 2 files changed, 863 insertions(+) create mode 100644 tests/qtest/npcm7xx_emc-test.c diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c new file mode 100644 index 00000000000..7a281731950 --- /dev/null +++ b/tests/qtest/npcm7xx_emc-test.c @@ -0,0 +1,862 @@ +/* + * QTests for Nuvoton NPCM7xx EMC Modules. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "libqos/libqos.h" +#include "qapi/qmp/qdict.h" +#include "qapi/qmp/qnum.h" +#include "qemu/bitops.h" +#include "qemu/iov.h" + +/* Name of the emc device. */ +#define TYPE_NPCM7XX_EMC "npcm7xx-emc" + +/* Timeout for various operations, in seconds. */ +#define TIMEOUT_SECONDS 10 + +/* Address in memory of the descriptor. */ +#define DESC_ADDR (1 << 20) /* 1 MiB */ + +/* Address in memory of the data packet. */ +#define DATA_ADDR (DESC_ADDR + 4096) + +#define CRC_LENGTH 4 + +#define NUM_TX_DESCRIPTORS 3 +#define NUM_RX_DESCRIPTORS 2 + +/* Size of tx,rx test buffers. */ +#define TX_DATA_LEN 64 +#define RX_DATA_LEN 64 + +#define TX_STEP_COUNT 10000 +#define RX_STEP_COUNT 10000 + +/* 32-bit register indices. */ +typedef enum NPCM7xxPWMRegister { + /* Control registers. */ + REG_CAMCMR, + REG_CAMEN, + + /* There are 16 CAMn[ML] registers. */ + REG_CAMM_BASE, + REG_CAML_BASE, + + REG_TXDLSA =3D 0x22, + REG_RXDLSA, + REG_MCMDR, + REG_MIID, + REG_MIIDA, + REG_FFTCR, + REG_TSDR, + REG_RSDR, + REG_DMARFC, + REG_MIEN, + + /* Status registers. */ + REG_MISTA, + REG_MGSTA, + REG_MPCNT, + REG_MRPC, + REG_MRPCC, + REG_MREPC, + REG_DMARFS, + REG_CTXDSA, + REG_CTXBSA, + REG_CRXDSA, + REG_CRXBSA, + + NPCM7XX_NUM_EMC_REGS, +} NPCM7xxPWMRegister; + +enum { NUM_CAMML_REGS =3D 16 }; + +/* REG_CAMCMR fields */ +/* Enable CAM Compare */ +#define REG_CAMCMR_ECMP (1 << 4) +/* Accept Unicast Packet */ +#define REG_CAMCMR_AUP (1 << 0) + +/* REG_MCMDR fields */ +/* Software Reset */ +#define REG_MCMDR_SWR (1 << 24) +/* Frame Transmission On */ +#define REG_MCMDR_TXON (1 << 8) +/* Accept Long Packet */ +#define REG_MCMDR_ALP (1 << 1) +/* Frame Reception On */ +#define REG_MCMDR_RXON (1 << 0) + +/* REG_MIEN fields */ +/* Enable Transmit Completion Interrupt */ +#define REG_MIEN_ENTXCP (1 << 18) +/* Enable Transmit Interrupt */ +#define REG_MIEN_ENTXINTR (1 << 16) +/* Enable Receive Good Interrupt */ +#define REG_MIEN_ENRXGD (1 << 4) +/* ENable Receive Interrupt */ +#define REG_MIEN_ENRXINTR (1 << 0) + +/* REG_MISTA fields */ +/* Transmit Bus Error Interrupt */ +#define REG_MISTA_TXBERR (1 << 24) +/* Transmit Descriptor Unavailable Interrupt */ +#define REG_MISTA_TDU (1 << 23) +/* Transmit Completion Interrupt */ +#define REG_MISTA_TXCP (1 << 18) +/* Transmit Interrupt */ +#define REG_MISTA_TXINTR (1 << 16) +/* Receive Bus Error Interrupt */ +#define REG_MISTA_RXBERR (1 << 11) +/* Receive Descriptor Unavailable Interrupt */ +#define REG_MISTA_RDU (1 << 10) +/* DMA Early Notification Interrupt */ +#define REG_MISTA_DENI (1 << 9) +/* Maximum Frame Length Interrupt */ +#define REG_MISTA_DFOI (1 << 8) +/* Receive Good Interrupt */ +#define REG_MISTA_RXGD (1 << 4) +/* Packet Too Long Interrupt */ +#define REG_MISTA_PTLE (1 << 3) +/* Receive Interrupt */ +#define REG_MISTA_RXINTR (1 << 0) + +typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc; +typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc; + +struct NPCM7xxEMCTxDesc { + uint32_t flags; + uint32_t txbsa; + uint32_t status_and_length; + uint32_t ntxdsa; +}; + +struct NPCM7xxEMCRxDesc { + uint32_t status_and_length; + uint32_t rxbsa; + uint32_t reserved; + uint32_t nrxdsa; +}; + +/* NPCM7xxEMCTxDesc.flags values */ +/* Owner: 0 =3D cpu, 1 =3D emc */ +#define TX_DESC_FLAG_OWNER_MASK (1 << 31) +/* Transmit interrupt enable */ +#define TX_DESC_FLAG_INTEN (1 << 2) + +/* NPCM7xxEMCTxDesc.status_and_length values */ +/* Transmission complete */ +#define TX_DESC_STATUS_TXCP (1 << 19) +/* Transmit interrupt */ +#define TX_DESC_STATUS_TXINTR (1 << 16) + +/* NPCM7xxEMCRxDesc.status_and_length values */ +/* Owner: 0b00 =3D cpu, 0b10 =3D emc */ +#define RX_DESC_STATUS_OWNER_SHIFT 30 +#define RX_DESC_STATUS_OWNER_MASK 0xc0000000 +/* Frame Reception Complete */ +#define RX_DESC_STATUS_RXGD (1 << 20) +/* Packet too long */ +#define RX_DESC_STATUS_PTLE (1 << 19) +/* Receive Interrupt */ +#define RX_DESC_STATUS_RXINTR (1 << 16) + +#define RX_DESC_PKT_LEN(word) ((uint32_t) (word) & 0xffff) + +typedef struct EMCModule { + int rx_irq; + int tx_irq; + uint64_t base_addr; +} EMCModule; + +typedef struct TestData { + const EMCModule *module; +} TestData; + +static const EMCModule emc_module_list[] =3D { + { + .rx_irq =3D 15, + .tx_irq =3D 16, + .base_addr =3D 0xf0825000 + }, + { + .rx_irq =3D 114, + .tx_irq =3D 115, + .base_addr =3D 0xf0826000 + } +}; + +/* Returns the index of the EMC module. */ +static int emc_module_index(const EMCModule *mod) +{ + ptrdiff_t diff =3D mod - emc_module_list; + + g_assert_true(diff >=3D 0 && diff < ARRAY_SIZE(emc_module_list)); + + return diff; +} + +static void packet_test_clear(void *sockets) +{ + int *test_sockets =3D sockets; + + close(test_sockets[0]); + g_free(test_sockets); +} + +static int *packet_test_init(int module_num, GString *cmd_line) +{ + int *test_sockets =3D g_new(int, 2); + int ret =3D socketpair(PF_UNIX, SOCK_STREAM, 0, test_sockets); + g_assert_cmpint(ret, !=3D , -1); + + /* + * KISS and use -nic. We specify two nics (both emc{0,1}) because ther= e's + * currently no way to specify only emc1: The driver implicitly relies= on + * emc[i] =3D=3D nd_table[i]. + */ + if (module_num =3D=3D 0) { + g_string_append_printf(cmd_line, + " -nic socket,fd=3D%d,model=3D" TYPE_NPCM7X= X_EMC " " + " -nic user,model=3D" TYPE_NPCM7XX_EMC " ", + test_sockets[1]); + } else { + g_string_append_printf(cmd_line, + " -nic user,model=3D" TYPE_NPCM7XX_EMC " " + " -nic socket,fd=3D%d,model=3D" TYPE_NPCM7X= X_EMC " ", + test_sockets[1]); + } + + g_test_queue_destroy(packet_test_clear, test_sockets); + return test_sockets; +} + +static uint32_t emc_read(QTestState *qts, const EMCModule *mod, + NPCM7xxPWMRegister regno) +{ + return qtest_readl(qts, mod->base_addr + regno * sizeof(uint32_t)); +} + +static void emc_write(QTestState *qts, const EMCModule *mod, + NPCM7xxPWMRegister regno, uint32_t value) +{ + qtest_writel(qts, mod->base_addr + regno * sizeof(uint32_t), value); +} + +static void emc_read_tx_desc(QTestState *qts, uint32_t addr, + NPCM7xxEMCTxDesc *desc) +{ + qtest_memread(qts, addr, desc, sizeof(*desc)); + desc->flags =3D le32_to_cpu(desc->flags); + desc->txbsa =3D le32_to_cpu(desc->txbsa); + desc->status_and_length =3D le32_to_cpu(desc->status_and_length); + desc->ntxdsa =3D le32_to_cpu(desc->ntxdsa); +} + +static void emc_write_tx_desc(QTestState *qts, const NPCM7xxEMCTxDesc *des= c, + uint32_t addr) +{ + NPCM7xxEMCTxDesc le_desc; + + le_desc.flags =3D cpu_to_le32(desc->flags); + le_desc.txbsa =3D cpu_to_le32(desc->txbsa); + le_desc.status_and_length =3D cpu_to_le32(desc->status_and_length); + le_desc.ntxdsa =3D cpu_to_le32(desc->ntxdsa); + qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc)); +} + +static void emc_read_rx_desc(QTestState *qts, uint32_t addr, + NPCM7xxEMCRxDesc *desc) +{ + qtest_memread(qts, addr, desc, sizeof(*desc)); + desc->status_and_length =3D le32_to_cpu(desc->status_and_length); + desc->rxbsa =3D le32_to_cpu(desc->rxbsa); + desc->reserved =3D le32_to_cpu(desc->reserved); + desc->nrxdsa =3D le32_to_cpu(desc->nrxdsa); +} + +static void emc_write_rx_desc(QTestState *qts, const NPCM7xxEMCRxDesc *des= c, + uint32_t addr) +{ + NPCM7xxEMCRxDesc le_desc; + + le_desc.status_and_length =3D cpu_to_le32(desc->status_and_length); + le_desc.rxbsa =3D cpu_to_le32(desc->rxbsa); + le_desc.reserved =3D cpu_to_le32(desc->reserved); + le_desc.nrxdsa =3D cpu_to_le32(desc->nrxdsa); + qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc)); +} + +/* + * Reset the EMC module. + * The module must be reset before, e.g., TXDLSA,RXDLSA are changed. + */ +static bool emc_soft_reset(QTestState *qts, const EMCModule *mod) +{ + uint32_t val; + uint64_t end_time; + + emc_write(qts, mod, REG_MCMDR, REG_MCMDR_SWR); + + /* + * Wait for device to reset as the linux driver does. + * During reset the AHB reads 0 for all registers. So first wait for + * something that resets to non-zero, and then wait for SWR becoming 0. + */ + end_time =3D g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SE= COND; + + do { + qtest_clock_step(qts, 100); + val =3D emc_read(qts, mod, REG_FFTCR); + } while (val =3D=3D 0 && g_get_monotonic_time() < end_time); + if (val !=3D 0) { + do { + qtest_clock_step(qts, 100); + val =3D emc_read(qts, mod, REG_MCMDR); + if ((val & REG_MCMDR_SWR) =3D=3D 0) { + /* + * N.B. The CAMs have been reset here, so macaddr matching= of + * incoming packets will not work. + */ + return true; + } + } while (g_get_monotonic_time() < end_time); + } + + g_message("%s: Timeout expired", __func__); + return false; +} + +/* Check emc registers are reset to default value. */ +static void test_init(gconstpointer test_data) +{ + const TestData *td =3D test_data; + const EMCModule *mod =3D td->module; + QTestState *qts =3D qtest_init("-machine quanta-gsj"); + int i; + +#define CHECK_REG(regno, value) \ + do { \ + g_assert_cmphex(emc_read(qts, mod, (regno)), =3D=3D, (value)); \ + } while (0) + + CHECK_REG(REG_CAMCMR, 0); + CHECK_REG(REG_CAMEN, 0); + CHECK_REG(REG_TXDLSA, 0xfffffffc); + CHECK_REG(REG_RXDLSA, 0xfffffffc); + CHECK_REG(REG_MCMDR, 0); + CHECK_REG(REG_MIID, 0); + CHECK_REG(REG_MIIDA, 0x00900000); + CHECK_REG(REG_FFTCR, 0x0101); + CHECK_REG(REG_DMARFC, 0x0800); + CHECK_REG(REG_MIEN, 0); + CHECK_REG(REG_MISTA, 0); + CHECK_REG(REG_MGSTA, 0); + CHECK_REG(REG_MPCNT, 0x7fff); + CHECK_REG(REG_MRPC, 0); + CHECK_REG(REG_MRPCC, 0); + CHECK_REG(REG_MREPC, 0); + CHECK_REG(REG_DMARFS, 0); + CHECK_REG(REG_CTXDSA, 0); + CHECK_REG(REG_CTXBSA, 0); + CHECK_REG(REG_CRXDSA, 0); + CHECK_REG(REG_CRXBSA, 0); + +#undef CHECK_REG + + for (i =3D 0; i < NUM_CAMML_REGS; ++i) { + g_assert_cmpuint(emc_read(qts, mod, REG_CAMM_BASE + i * 2), =3D=3D, + 0); + g_assert_cmpuint(emc_read(qts, mod, REG_CAML_BASE + i * 2), =3D=3D, + 0); + } + + qtest_quit(qts); +} + +static bool emc_wait_irq(QTestState *qts, const EMCModule *mod, int step, + bool is_tx) +{ + uint64_t end_time =3D + g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND; + + do { + if (qtest_get_irq(qts, is_tx ? mod->tx_irq : mod->rx_irq)) { + return true; + } + qtest_clock_step(qts, step); + } while (g_get_monotonic_time() < end_time); + + g_message("%s: Timeout expired", __func__); + return false; +} + +static bool emc_wait_mista(QTestState *qts, const EMCModule *mod, int step, + uint32_t flag) +{ + uint64_t end_time =3D + g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND; + + do { + uint32_t mista =3D emc_read(qts, mod, REG_MISTA); + if (mista & flag) { + return true; + } + qtest_clock_step(qts, step); + } while (g_get_monotonic_time() < end_time); + + g_message("%s: Timeout expired", __func__); + return false; +} + +static bool wait_socket_readable(int fd) +{ + fd_set read_fds; + struct timeval tv; + int rv; + + FD_ZERO(&read_fds); + FD_SET(fd, &read_fds); + tv.tv_sec =3D TIMEOUT_SECONDS; + tv.tv_usec =3D 0; + rv =3D select(fd + 1, &read_fds, NULL, NULL, &tv); + if (rv =3D=3D -1) { + perror("select"); + } else if (rv =3D=3D 0) { + g_message("%s: Timeout expired", __func__); + } + return rv =3D=3D 1; +} + +/* Initialize *desc (in host endian format). */ +static void init_tx_desc(NPCM7xxEMCTxDesc *desc, size_t count, + uint32_t desc_addr) +{ + g_assert(count >=3D 2); + memset(&desc[0], 0, sizeof(*desc) * count); + /* Leave the last one alone, owned by the cpu -> stops transmission. */ + for (size_t i =3D 0; i < count - 1; ++i) { + desc[i].flags =3D + (TX_DESC_FLAG_OWNER_MASK | /* owner =3D 1: emc */ + TX_DESC_FLAG_INTEN | + 0 | /* crc append =3D 0 */ + 0 /* padding enable =3D 0 */); + desc[i].status_and_length =3D + (0 | /* collision count =3D 0 */ + 0 | /* SQE =3D 0 */ + 0 | /* PAU =3D 0 */ + 0 | /* TXHA =3D 0 */ + 0 | /* LC =3D 0 */ + 0 | /* TXABT =3D 0 */ + 0 | /* NCS =3D 0 */ + 0 | /* EXDEF =3D 0 */ + 0 | /* TXCP =3D 0 */ + 0 | /* DEF =3D 0 */ + 0 | /* TXINTR =3D 0 */ + 0 /* length filled in later */); + desc[i].ntxdsa =3D desc_addr + (i + 1) * sizeof(*desc); + } +} + +static void enable_tx(QTestState *qts, const EMCModule *mod, + const NPCM7xxEMCTxDesc *desc, size_t count, + uint32_t desc_addr, uint32_t mien_flags) +{ + /* Write the descriptors to guest memory. */ + for (size_t i =3D 0; i < count; ++i) { + emc_write_tx_desc(qts, desc + i, desc_addr + i * sizeof(*desc)); + } + + /* Trigger sending the packet. */ + /* The module must be reset before changing TXDLSA. */ + g_assert(emc_soft_reset(qts, mod)); + emc_write(qts, mod, REG_TXDLSA, desc_addr); + emc_write(qts, mod, REG_CTXDSA, ~0); + emc_write(qts, mod, REG_MIEN, REG_MIEN_ENTXCP | mien_flags); + { + uint32_t mcmdr =3D emc_read(qts, mod, REG_MCMDR); + mcmdr |=3D REG_MCMDR_TXON; + emc_write(qts, mod, REG_MCMDR, mcmdr); + } + + /* Prod the device to send the packet. */ + emc_write(qts, mod, REG_TSDR, 1); +} + +static void emc_send_verify1(QTestState *qts, const EMCModule *mod, int fd, + bool with_irq, uint32_t desc_addr, + uint32_t next_desc_addr, + const char *test_data, int test_size) +{ + NPCM7xxEMCTxDesc result_desc; + uint32_t expected_mask, expected_value, recv_len; + int ret; + char buffer[TX_DATA_LEN]; + + g_assert(wait_socket_readable(fd)); + + /* Read the descriptor back. */ + emc_read_tx_desc(qts, desc_addr, &result_desc); + /* Descriptor should be owned by cpu now. */ + g_assert((result_desc.flags & TX_DESC_FLAG_OWNER_MASK) =3D=3D 0); + /* Test the status bits, ignoring the length field. */ + expected_mask =3D 0xffff << 16; + expected_value =3D TX_DESC_STATUS_TXCP; + if (with_irq) { + expected_value |=3D TX_DESC_STATUS_TXINTR; + } + g_assert_cmphex((result_desc.status_and_length & expected_mask), =3D= =3D, + expected_value); + + /* Check data sent to the backend. */ + recv_len =3D ~0; + ret =3D qemu_recv(fd, &recv_len, sizeof(recv_len), MSG_DONTWAIT); + g_assert_cmpint(ret, =3D=3D , sizeof(recv_len)); + + g_assert(wait_socket_readable(fd)); + memset(buffer, 0xff, sizeof(buffer)); + ret =3D qemu_recv(fd, buffer, test_size, MSG_DONTWAIT); + g_assert_cmpmem(buffer, ret, test_data, test_size); +} + +static void emc_send_verify(QTestState *qts, const EMCModule *mod, int fd, + bool with_irq) +{ + NPCM7xxEMCTxDesc desc[NUM_TX_DESCRIPTORS]; + uint32_t desc_addr =3D DESC_ADDR; + static const char test1_data[] =3D "TEST1"; + static const char test2_data[] =3D "Testing 1 2 3 ..."; + uint32_t data1_addr =3D DATA_ADDR; + uint32_t data2_addr =3D data1_addr + sizeof(test1_data); + bool got_tdu; + uint32_t end_desc_addr; + + /* Prepare test data buffer. */ + qtest_memwrite(qts, data1_addr, test1_data, sizeof(test1_data)); + qtest_memwrite(qts, data2_addr, test2_data, sizeof(test2_data)); + + init_tx_desc(&desc[0], NUM_TX_DESCRIPTORS, desc_addr); + desc[0].txbsa =3D data1_addr; + desc[0].status_and_length |=3D sizeof(test1_data); + desc[1].txbsa =3D data2_addr; + desc[1].status_and_length |=3D sizeof(test2_data); + + enable_tx(qts, mod, &desc[0], NUM_TX_DESCRIPTORS, desc_addr, + with_irq ? REG_MIEN_ENTXINTR : 0); + + /* + * It's problematic to observe the interrupt for each packet. + * Instead just wait until all the packets go out. + */ + got_tdu =3D false; + while (!got_tdu) { + if (with_irq) { + g_assert_true(emc_wait_irq(qts, mod, TX_STEP_COUNT, + /*is_tx=3D*/true)); + } else { + g_assert_true(emc_wait_mista(qts, mod, TX_STEP_COUNT, + REG_MISTA_TXINTR)); + } + got_tdu =3D !!(emc_read(qts, mod, REG_MISTA) & REG_MISTA_TDU); + /* If we don't have TDU yet, reset the interrupt. */ + if (!got_tdu) { + emc_write(qts, mod, REG_MISTA, + emc_read(qts, mod, REG_MISTA) & 0xffff0000); + } + } + + end_desc_addr =3D desc_addr + 2 * sizeof(desc[0]); + g_assert_cmphex(emc_read(qts, mod, REG_CTXDSA), =3D=3D, end_desc_addr); + g_assert_cmphex(emc_read(qts, mod, REG_MISTA), =3D=3D, + REG_MISTA_TXCP | REG_MISTA_TXINTR | REG_MISTA_TDU); + + emc_send_verify1(qts, mod, fd, with_irq, + desc_addr, end_desc_addr, + test1_data, sizeof(test1_data)); + emc_send_verify1(qts, mod, fd, with_irq, + desc_addr + sizeof(desc[0]), end_desc_addr, + test2_data, sizeof(test2_data)); +} + +/* Initialize *desc (in host endian format). */ +static void init_rx_desc(NPCM7xxEMCRxDesc *desc, size_t count, + uint32_t desc_addr, uint32_t data_addr) +{ + g_assert_true(count >=3D 2); + memset(desc, 0, sizeof(*desc) * count); + desc[0].rxbsa =3D data_addr; + desc[0].status_and_length =3D + (0b10 << RX_DESC_STATUS_OWNER_SHIFT | /* owner =3D 10: emc */ + 0 | /* RP =3D 0 */ + 0 | /* ALIE =3D 0 */ + 0 | /* RXGD =3D 0 */ + 0 | /* PTLE =3D 0 */ + 0 | /* CRCE =3D 0 */ + 0 | /* RXINTR =3D 0 */ + 0 /* length (filled in later) */); + /* Leave the last one alone, owned by the cpu -> stops transmission. */ + desc[0].nrxdsa =3D desc_addr + sizeof(*desc); +} + +static void enable_rx(QTestState *qts, const EMCModule *mod, + const NPCM7xxEMCRxDesc *desc, size_t count, + uint32_t desc_addr, uint32_t mien_flags, + uint32_t mcmdr_flags) +{ + /* + * Write the descriptor to guest memory. + * FWIW, IWBN if the docs said the buffer needs to be at least DMARFC + * bytes. + */ + for (size_t i =3D 0; i < count; ++i) { + emc_write_rx_desc(qts, desc + i, desc_addr + i * sizeof(*desc)); + } + + /* Trigger receiving the packet. */ + /* The module must be reset before changing RXDLSA. */ + g_assert(emc_soft_reset(qts, mod)); + emc_write(qts, mod, REG_RXDLSA, desc_addr); + emc_write(qts, mod, REG_MIEN, REG_MIEN_ENRXGD | mien_flags); + + /* + * We don't know what the device's macaddr is, so just accept all + * unicast packets (AUP). + */ + emc_write(qts, mod, REG_CAMCMR, REG_CAMCMR_AUP); + emc_write(qts, mod, REG_CAMEN, 1 << 0); + { + uint32_t mcmdr =3D emc_read(qts, mod, REG_MCMDR); + mcmdr |=3D REG_MCMDR_RXON | mcmdr_flags; + emc_write(qts, mod, REG_MCMDR, mcmdr); + } + + /* Prod the device to accept a packet. */ + emc_write(qts, mod, REG_RSDR, 1); +} + +static void emc_recv_verify(QTestState *qts, const EMCModule *mod, int fd, + bool with_irq) +{ + NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS]; + uint32_t desc_addr =3D DESC_ADDR; + uint32_t data_addr =3D DATA_ADDR; + int ret; + uint32_t expected_mask, expected_value; + NPCM7xxEMCRxDesc result_desc; + + /* Prepare test data buffer. */ + const char test[RX_DATA_LEN] =3D "TEST"; + int len =3D htonl(sizeof(test)); + const struct iovec iov[] =3D { + { + .iov_base =3D &len, + .iov_len =3D sizeof(len), + },{ + .iov_base =3D (char *) test, + .iov_len =3D sizeof(test), + }, + }; + + /* + * Reset the device BEFORE sending a test packet, otherwise the packet + * may get swallowed by an active device of an earlier test. + */ + init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr); + enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr, + with_irq ? REG_MIEN_ENRXINTR : 0, 0); + + /* Send test packet to device's socket. */ + ret =3D iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test)); + g_assert_cmpint(ret, =3D=3D , sizeof(test) + sizeof(len)); + + /* Wait for RX interrupt. */ + if (with_irq) { + g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=3D*/fa= lse)); + } else { + g_assert_true(emc_wait_mista(qts, mod, RX_STEP_COUNT, REG_MISTA_RX= GD)); + } + + g_assert_cmphex(emc_read(qts, mod, REG_CRXDSA), =3D=3D, + desc_addr + sizeof(desc[0])); + + expected_mask =3D 0xffff; + expected_value =3D (REG_MISTA_DENI | + REG_MISTA_RXGD | + REG_MISTA_RXINTR); + g_assert_cmphex((emc_read(qts, mod, REG_MISTA) & expected_mask), + =3D=3D, expected_value); + + /* Read the descriptor back. */ + emc_read_rx_desc(qts, desc_addr, &result_desc); + /* Descriptor should be owned by cpu now. */ + g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) = =3D=3D 0); + /* Test the status bits, ignoring the length field. */ + expected_mask =3D 0xffff << 16; + expected_value =3D RX_DESC_STATUS_RXGD; + if (with_irq) { + expected_value |=3D RX_DESC_STATUS_RXINTR; + } + g_assert_cmphex((result_desc.status_and_length & expected_mask), =3D= =3D, + expected_value); + g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), =3D=3D, + RX_DATA_LEN + CRC_LENGTH); + + { + char buffer[RX_DATA_LEN]; + qtest_memread(qts, data_addr, buffer, sizeof(buffer)); + g_assert_cmpstr(buffer, =3D=3D , "TEST"); + } +} + +static void emc_test_ptle(QTestState *qts, const EMCModule *mod, int fd) +{ + NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS]; + uint32_t desc_addr =3D DESC_ADDR; + uint32_t data_addr =3D DATA_ADDR; + int ret; + NPCM7xxEMCRxDesc result_desc; + uint32_t expected_mask, expected_value; + + /* Prepare test data buffer. */ +#define PTLE_DATA_LEN 1600 + char test_data[PTLE_DATA_LEN]; + int len =3D htonl(sizeof(test_data)); + const struct iovec iov[] =3D { + { + .iov_base =3D &len, + .iov_len =3D sizeof(len), + },{ + .iov_base =3D (char *) test_data, + .iov_len =3D sizeof(test_data), + }, + }; + memset(test_data, 42, sizeof(test_data)); + + /* + * Reset the device BEFORE sending a test packet, otherwise the packet + * may get swallowed by an active device of an earlier test. + */ + init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr); + enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr, + REG_MIEN_ENRXINTR, REG_MCMDR_ALP); + + /* Send test packet to device's socket. */ + ret =3D iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test_data)); + g_assert_cmpint(ret, =3D=3D , sizeof(test_data) + sizeof(len)); + + /* Wait for RX interrupt. */ + g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=3D*/false)= ); + + /* Read the descriptor back. */ + emc_read_rx_desc(qts, desc_addr, &result_desc); + /* Descriptor should be owned by cpu now. */ + g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) = =3D=3D 0); + /* Test the status bits, ignoring the length field. */ + expected_mask =3D 0xffff << 16; + expected_value =3D (RX_DESC_STATUS_RXGD | + RX_DESC_STATUS_PTLE | + RX_DESC_STATUS_RXINTR); + g_assert_cmphex((result_desc.status_and_length & expected_mask), =3D= =3D, + expected_value); + g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), =3D=3D, + PTLE_DATA_LEN + CRC_LENGTH); + + { + char buffer[PTLE_DATA_LEN]; + qtest_memread(qts, data_addr, buffer, sizeof(buffer)); + g_assert(memcmp(buffer, test_data, PTLE_DATA_LEN) =3D=3D 0); + } +} + +static void test_tx(gconstpointer test_data) +{ + const TestData *td =3D test_data; + GString *cmd_line =3D g_string_new("-machine quanta-gsj"); + int *test_sockets =3D packet_test_init(emc_module_index(td->module), + cmd_line); + QTestState *qts =3D qtest_init(cmd_line->str); + + /* + * TODO: For pedantic correctness test_sockets[0] should be closed aft= er + * the fork and before the exec, but that will require some harness + * improvements. + */ + close(test_sockets[1]); + /* Defensive programming */ + test_sockets[1] =3D -1; + + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + + emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=3D*/false= ); + emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=3D*/true); + + qtest_quit(qts); +} + +static void test_rx(gconstpointer test_data) +{ + const TestData *td =3D test_data; + GString *cmd_line =3D g_string_new("-machine quanta-gsj"); + int *test_sockets =3D packet_test_init(emc_module_index(td->module), + cmd_line); + QTestState *qts =3D qtest_init(cmd_line->str); + + /* + * TODO: For pedantic correctness test_sockets[0] should be closed aft= er + * the fork and before the exec, but that will require some harness + * improvements. + */ + close(test_sockets[1]); + /* Defensive programming */ + test_sockets[1] =3D -1; + + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + + emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=3D*/false= ); + emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=3D*/true); + emc_test_ptle(qts, td->module, test_sockets[0]); + + qtest_quit(qts); +} + +static void emc_add_test(const char *name, const TestData* td, + GTestDataFunc fn) +{ + g_autofree char *full_name =3D g_strdup_printf( + "npcm7xx_emc/emc[%d]/%s", emc_module_index(td->module), name); + qtest_add_data_func(full_name, td, fn); +} +#define add_test(name, td) emc_add_test(#name, td, test_##name) + +int main(int argc, char **argv) +{ + TestData test_data_list[ARRAY_SIZE(emc_module_list)]; + + g_test_init(&argc, &argv, NULL); + + for (int i =3D 0; i < ARRAY_SIZE(emc_module_list); ++i) { + TestData *td =3D &test_data_list[i]; + + td->module =3D &emc_module_list[i]; + + add_test(init, td); + add_test(tx, td); + add_test(rx, td); + } + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index ba6ecaed325..8dea0b6fb62 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -136,6 +136,7 @@ qtests_sparc64 =3D \ =20 qtests_npcm7xx =3D \ ['npcm7xx_adc-test', + 'npcm7xx_emc-test', 'npcm7xx_gpio-test', 'npcm7xx_pwm-test', 'npcm7xx_rng-test', --=20 2.20.1