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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oXZJdmuHAUaTxViiBBTMLXgaD9//CuJ3J4es1nlQ2XM=; b=rev3AuoTDjhbNSys8k4mFujpcmZqOtgy7mxYuemVCzeox9hVgOoJQSDVdDB0ATvHH4 leuVEzeqxiIdyVPyX06ip/sTyATmYjBx9SD6xI9HNy1EwNCpfX2OxXUce6nlvcgxlX0I 6s2DIn9ogiomVwrdXFvRFtfi4QPhEyHJsvmw9YjQVCzWcnfpQ/3Tu8Pf+fIYbYC9dDH/ SpNOX95jvZETUxgcsu/UCos1j6SpGBtMfgjLOBgmmGwXT3GLO7PrIouT01GDKuFn2dR+ nVCy3s7f7MY0Nw26d3dILXPyZJPmgNCvPH487w9fDqGypIl2BzXLCprV9WhVVCLl0k37 pPiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oXZJdmuHAUaTxViiBBTMLXgaD9//CuJ3J4es1nlQ2XM=; b=jVxGcXv4RX0JJNjXhRE/qh62ufw4cY64S7+er6n6yGy1k0v1Aw6OCGDMMF+FcGH8bl Yzy68R2eHL5a0W4w3VyVT9vh45CH9OBHF/rlAh4N9yJx7z2oLMyNhA+7dmc4wJRo/j6B a6FhdISOYLd8RTsQxK89+PvS3eR/wRB30o4lomswUH4ZkwGaVIIZy51WaqW+fFnmaZ7E Ealn/SQUSUYUqGhsTUiPyt1osYFtXzWz8+Slro/wmo4EfMnpDpi+4jNB0U/XA9YQ2RKk QS/h6aS9+kEP9ZGmngabpmwoRaiYVDDWH1WsTwFU2bFWbTsc3CGOqFenHNTF7n50EXcP OQYQ== X-Gm-Message-State: AOAM532Cp6IbQlCV4fvYOH0kTg5aV13XhjaOQFeWEY2m0UNjCJVMnkV6 mB3PvFdRKp/B2lVYuSrImwG3wA== X-Google-Smtp-Source: ABdhPJwyPsLj2a7Ts3Lu2dfxTirtHsBABw0xGcGinpNiHPuhiL3ju2++LNzcOKN2izWjTG6fY85iIg== X-Received: by 2002:a05:600c:2dd0:: with SMTP id e16mr14528115wmh.129.1613389934819; Mon, 15 Feb 2021 03:52:14 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 07/24] hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board Date: Mon, 15 Feb 2021 11:51:21 +0000 Message-Id: <20210215115138.20465-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Set the FPGAIO num-leds and have-switches properties explicitly per-board, rather than relying on the defaults. The AN505 and AN521 both have the same settings as the default values, but the AN524 will be different. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/arm/mps2-tz.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 9add1453cc2..6e345cf1f09 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -79,6 +79,8 @@ struct MPS2TZMachineClass { uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ uint32_t len_oscclk; const uint32_t *oscclk; + uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ + bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ const char *armsse_type; }; =20 @@ -241,8 +243,11 @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *m= ms, void *opaque, const char *name, hwaddr size) { MPS2FPGAIO *fpgaio =3D opaque; + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); =20 object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAI= O); + qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); + qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_swit= ches); sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); } @@ -687,6 +692,8 @@ static void mps2tz_an505_class_init(ObjectClass *oc, vo= id *data) mmc->sysclk_frq =3D 20 * 1000 * 1000; /* 20MHz */ mmc->oscclk =3D an505_oscclk; mmc->len_oscclk =3D ARRAY_SIZE(an505_oscclk); + mmc->fpgaio_num_leds =3D 2; + mmc->fpgaio_has_switches =3D false; mmc->armsse_type =3D TYPE_IOTKIT; } =20 @@ -705,6 +712,8 @@ static void mps2tz_an521_class_init(ObjectClass *oc, vo= id *data) mmc->sysclk_frq =3D 20 * 1000 * 1000; /* 20MHz */ mmc->oscclk =3D an505_oscclk; /* AN521 is the same as AN505 here */ mmc->len_oscclk =3D ARRAY_SIZE(an505_oscclk); + mmc->fpgaio_num_leds =3D 2; + mmc->fpgaio_has_switches =3D false; mmc->armsse_type =3D TYPE_SSE200; } =20 --=20 2.20.1