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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+NbEIvKPXeseDuihlw5UuA+TE/Yh6pzRecBSPQLOGzA=; b=JcB953aXQ+kOZN6UN3HgPCvje9PxaJ4R82K4joukXBdiWrh7rvgf8d/fxkjLtTpsAU tzR2cBoV8fNtl+OM7px6ziJtYMNaKmVgCtNLa1phNiyeCsdZ3H8m9/oFTg4x+INhpQm5 UYfwDYiu6l8+pDXX/k2q/nZakEBKGNZGAEyq/4lQR8A5CcHly1teNc1gVElDTyfcvcrH cKO3K2+ge6QIrK72pxNVcqk5/A2bq+qGw1gIGYRxMrDtv9j0C8BHpqWgmzaIhZ5ieGpz sz5gLTLS9GuEZNGQ1HigVhoU442a38VIBQuDD63jMnp/A7IlQ7DYmbsB/vrZboyieO1Q I1cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+NbEIvKPXeseDuihlw5UuA+TE/Yh6pzRecBSPQLOGzA=; b=IufS4sf231Az7XWVRonLpsTdrpMoprBaQmSiHjMdlNngjuBZsoM4v302HNCFl/v9eY 4m+UDxAoEIIYKfJWK8Yzv3bvd6dbsNTM6x1InvXeG80BU4+Pu4+nj+wpZxaZyrrZgbrh SP8rxqAG1bedmq1sMad66ncHKxNXnyY7qsgpvAfyjEWgwkTNC32IKfbSwg0p5r01bZ6T juEBknOeO6BAQIp9tPTT0vwWDRcbCNBhec/EjLBC560IHq1UfGSHeFP6l7R5DiBBSiJN nUTPmYNvPlLDwGN3ugNumFZprfvCbs9Hwzg313Sa4GQj9ebvtKoKfEkHyUr+C8jP3NQ5 ZVog== X-Gm-Message-State: AOAM533RGh9kS0+3aVi0U1ZJAwB3s98ESDLyXKe6UVpniq1N35StRMl+ ZdSgXGLD63FXKLAYUmTekqNoGjJ1inXWJA== X-Google-Smtp-Source: ABdhPJxLS6lxoNJeqinL75T6aEWtu99h4Q9rgz/VWJAzitSKEkMEcDEgMNgx8imfjotfMKBRIOPYCQ== X-Received: by 2002:adf:b749:: with SMTP id n9mr18299390wre.267.1613389954486; Mon, 15 Feb 2021 03:52:34 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 13/24] hw/arm/mps2-tz: Move device IRQ info to data structures Date: Mon, 15 Feb 2021 11:51:27 +0000 Message-Id: <20210215115138.20465-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Move the specification of the IRQ information for the uart, ethernet, dma and spi devices to the data structures. (The other devices handled by the PPCPortInfo structures don't have any interrupt lines we need to wire up.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/mps2-tz.c | 52 +++++++++++++++++++++++------------------------- 1 file changed, 25 insertions(+), 27 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 085746ac3e6..014ba775783 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -208,12 +208,10 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mm= s, void *opaque, const char *name, hwaddr size, const int *irqs) { + /* The irq[] array is tx, rx, combined, in that order */ MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart =3D opaque; int i =3D uart - &mms->uart[0]; - int rxirqno =3D i * 2 + 32; - int txirqno =3D i * 2 + 33; - int combirqno =3D i + 42; SysBusDevice *s; DeviceState *orgate_dev =3D DEVICE(&mms->uart_irq_orgate); =20 @@ -222,11 +220,11 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mm= s, void *opaque, qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->sysclk_frq); sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); s =3D SYS_BUS_DEVICE(uart); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); - sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); - sysbus_connect_irq(s, 4, get_sse_irq_in(mms, combirqno)); + sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2])); return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); } =20 @@ -283,7 +281,7 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *m= ms, void *opaque, =20 s =3D SYS_BUS_DEVICE(mms->lan9118); sysbus_realize_and_unref(s, &error_fatal); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 48)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); return sysbus_mmio_get_region(s, 0); } =20 @@ -329,6 +327,7 @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, = void *opaque, const char *name, hwaddr size, const int *irqs) { + /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */ PL080State *dma =3D opaque; int i =3D dma - &mms->dma[0]; SysBusDevice *s; @@ -373,9 +372,9 @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, = void *opaque, =20 s =3D SYS_BUS_DEVICE(dma); /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 58 + i * 3)); - sysbus_connect_irq(s, 1, get_sse_irq_in(mms, 56 + i * 3)); - sysbus_connect_irq(s, 2, get_sse_irq_in(mms, 57 + i * 3)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); + sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqs[2])); =20 g_free(mscname); return sysbus_mmio_get_region(s, 0); @@ -394,13 +393,12 @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms= , void *opaque, * lines are set via the "MISC" register in the MPS2 FPGAIO device. */ PL022State *spi =3D opaque; - int i =3D spi - &mms->spi[0]; SysBusDevice *s; =20 object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022); sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal); s =3D SYS_BUS_DEVICE(spi); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); return sysbus_mmio_get_region(s, 0); } =20 @@ -551,16 +549,16 @@ static void mps2tz_common_init(MachineState *machine) }, { .name =3D "apb_ppcexp1", .ports =3D { - { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000 }, - { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000 }, - { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000 }, - { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000 }, - { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000 }, - { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, - { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, - { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, - { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, - { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, + { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000, { 51= } }, + { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000, { 52= } }, + { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000, { 53= } }, + { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000, { 54= } }, + { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000, { 55= } }, + { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000, {= 32, 33, 42 } }, + { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000, {= 34, 35, 43 } }, + { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, {= 36, 37, 44 } }, + { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, {= 38, 39, 45 } }, + { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, {= 40, 41, 46 } }, { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 }, { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 }, { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 }, @@ -582,15 +580,15 @@ static void mps2tz_common_init(MachineState *machine) { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x10= 00 }, { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x10= 00 }, { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x10= 00 }, - { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 }, + { "eth", make_eth_dev, NULL, 0x42000000, 0x100000, { 48 } = }, }, }, { .name =3D "ahb_ppcexp1", .ports =3D { - { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000 }, - { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000 }, - { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000 }, - { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000 }, + { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000, { 58= , 56, 57 } }, + { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000, { 61= , 59, 60 } }, + { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000, { 64= , 62, 63 } }, + { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000, { 67= , 65, 66 } }, }, }, }; --=20 2.20.1