From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613390145; cv=none; d=zohomail.com; s=zohoarc; b=ZBaALf8Os0bDFFZueoegoRHq/1zUYH2eXFb9Wglt7/LxvPH2xkzDDzBc//JFYbdbYmlM10VWjibz4Sko5demc79V7TYJXLHo8S2b5d9EzcUGB8bCM3sRMLY4G3stW5cPTcynD9/6ddXd6JMoBDe9afXh8wYXguJzhOPPQ5R7RSk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613390145; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4jVa3xe/kMi+C9vLk6K1uU55ZtyS+eyTIRH5FY6nhOc=; b=COu5nxmza/rznKyLIUqX22BNfWcsHr+x/HSJeu01AyzmAMUxqgV7XPgJ3fqNkBt9Qtja2uany2KxjMhXRlii/3b1PjjRZFCvg0s16pDOCIl48fiF5ObjGBgLtrhD1QgBv53f/pAJCxqLzCccVvEL04/HktaFxKJEnoKdk9vhWjw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613390145499444.8238073405762; Mon, 15 Feb 2021 03:55:45 -0800 (PST) Received: from localhost ([::1]:43362 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBcTc-0003bH-NC for importer@patchew.org; Mon, 15 Feb 2021 06:55:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38988) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBcQ4-0006hh-A8 for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:01 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:39113) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBcQ1-0003mJ-3T for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:00 -0500 Received: by mail-wr1-x42c.google.com with SMTP id v1so8500039wrd.6 for ; Mon, 15 Feb 2021 03:51:55 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.51.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:51:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4jVa3xe/kMi+C9vLk6K1uU55ZtyS+eyTIRH5FY6nhOc=; b=EJyJbHanGn5ZHrQvGMNFGCH/jR86jTMdJZRO08nuBk2ZqRG1BvS2ZH18f9zdxNyWg8 jD2jw3l0PgxuOQgi+SiO0KpXwYK5gt1C5lAQ+KFzP+GlpiXEiJ9X42vZf/Cq5UIInOvp GM6idh78MFt0yvNXwiV+iIwEMrI0uMPXKSy1wh37Ep7vkqPw/zx1Vu82Niq9YKp0jmK5 ULM9FoAQtzCIXi46+BQVyuPMaLEdo2qFtDgFwl9q+Qx9l7oDx/7GeJONTVRDCB8S/BH8 ZPh+Revu877iZLLcW38ijp+bUpLNg5MWwjemiYtPTH2FOn3rIfHKleQMaPhTuDB0aJRo B90Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4jVa3xe/kMi+C9vLk6K1uU55ZtyS+eyTIRH5FY6nhOc=; b=BTYaSpA7tgu8LJwvHBMAGYh4ijNie0UUX1QH9v/X9dLWk0L5L4kNkPiKj6WBwMQhvy 3Xtvq9NvtZm+1KV1c9NX9kZWDtScFvgxTZBLx+wjt9AL/EvLWzSFra634zfrdIEri4Lx jwKM5bkbcz/t2ndh/fD0F7HgVHDaObbi892skESPQc2NP7fxTeQsNFvBoK5NZo90UiQn NKJ5RW6ruAhyXeLsLUjMihNc0qrYPh8mTUrA33IgwqxIJnkbmLCdsZFwsymcGwdICz6I RHQXF4WycaSqxQcJye5U4/86MHSG2tkRQsA20l3UhGoAU/+9MluZzd5Ife+qU+9D2mUM L0mQ== X-Gm-Message-State: AOAM530cnesm7ZghfuRX69rGFKQSRCFZQybgT/Gerg/2f7xwamzauCxV QVB8l7NZ3toZxux53pQmmJehCEBfDwsiVQ== X-Google-Smtp-Source: ABdhPJx7hiTV86qckulmNoY6OcJpUgAvWXDqKWZJWGdkrZoWIP+gwJfNu1JvCUovZwnS8hP0M+m2tQ== X-Received: by 2002:a5d:62ce:: with SMTP id o14mr12036703wrv.174.1613389914687; Mon, 15 Feb 2021 03:51:54 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 01/24] hw/arm/mps2-tz: Make SYSCLK frequency board-specific Date: Mon, 15 Feb 2021 11:51:15 +0000 Message-Id: <20210215115138.20465-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The AN524 has a different SYSCLK frequency from the AN505 and AN521; make the SYSCLK frequency a field in the MPS2TZMachineClass rather than a compile-time constant so we can support the AN524. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 90caa914934..82ce6262817 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -76,6 +76,7 @@ struct MPS2TZMachineClass { MachineClass parent; MPS2TZFPGAType fpga_type; uint32_t scc_id; + uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ const char *armsse_type; }; =20 @@ -111,8 +112,6 @@ struct MPS2TZMachineState { =20 OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) =20 -/* Main SYSCLK frequency in Hz */ -#define SYSCLK_FRQ 20000000 /* Slow 32Khz S32KCLK frequency in Hz */ #define S32KCLK_FRQ (32 * 1000) =20 @@ -186,6 +185,7 @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState = *mms, static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size) { + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart =3D opaque; int i =3D uart - &mms->uart[0]; int rxirqno =3D i * 2; @@ -196,7 +196,7 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms,= void *opaque, =20 object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART); qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); - qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); + qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->sysclk_frq); sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); s =3D SYS_BUS_DEVICE(uart); sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); @@ -403,7 +403,7 @@ static void mps2tz_common_init(MachineState *machine) =20 /* These clocks don't need migration because they are fixed-frequency = */ mms->sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); - clock_set_hz(mms->sysclk, SYSCLK_FRQ); + clock_set_hz(mms->sysclk, mmc->sysclk_frq); mms->s32kclk =3D clock_new(OBJECT(machine), "S32KCLK"); clock_set_hz(mms->s32kclk, S32KCLK_FRQ); =20 @@ -670,6 +670,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, vo= id *data) mmc->fpga_type =3D FPGA_AN505; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id =3D 0x41045050; + mmc->sysclk_frq =3D 20 * 1000 * 1000; /* 20MHz */ mmc->armsse_type =3D TYPE_IOTKIT; } =20 @@ -685,6 +686,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, vo= id *data) mmc->fpga_type =3D FPGA_AN521; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id =3D 0x41045210; + mmc->sysclk_frq =3D 20 * 1000 * 1000; /* 20MHz */ mmc->armsse_type =3D TYPE_SSE200; } =20 --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613390054302406.38249440254936; Mon, 15 Feb 2021 03:54:14 -0800 (PST) Received: from localhost ([::1]:38996 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBcSD-0001nZ-69 for importer@patchew.org; Mon, 15 Feb 2021 06:54:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39012) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBcQ6-0006jz-DM for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:03 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:50688) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBcQ4-0003oG-0o for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:02 -0500 Received: by mail-wm1-x333.google.com with SMTP id h7so798065wmq.0 for ; Mon, 15 Feb 2021 03:51:59 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.51.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:51:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1ZjwT33c/5bdyZWF4rErskN14FmTiv7xRdzLHgQeabk=; b=jh5/RxFLhAgjA/1nvz04aJxq7ntG1MPu4TSq5ZcdsGIK8hLOc8GMtg58G1Omb/6ibJ INCjSJevfM3bLsUoMzIvu1ZaRtDEZawppFIsTHljp0hpelRmS9UzNtZ4+OdymPT02vkN vlFrjuA6L16JPrh+MReLNmeUrR5rAbyBVsx7nGSCKq1+Hx6L8ZDWoWmVYcydkq5l3kYM YsisCliKMe1L/x2eFkha7pIpubDgml2YRiFGJ4s7gjAxe4+LZz7TrMBmmV1ZAehif3WL iceQuUD6g0VQ4GCfYH34lXbqPLLsnr1maEUhu7duAr2iaqEoKiiPzu9VHqaA42EXjFpn h7dA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1ZjwT33c/5bdyZWF4rErskN14FmTiv7xRdzLHgQeabk=; b=CspbLERaP6jsejDF5A6oi/yLnNHkOSGTMgmgOvSzIObyTnHyOxZtv28TgOpqahTUkJ pqx3rgEoq41oIpJUC5nnaLTPB/ss4yz9MRsAzOXCaexqkiUpwGahcJ4PUf+ZRXxPeJ8N BU0Upixso58KUICNvfgE9Uv9O5PMqqYHt9wdXGQmA6gu8TpEyHbGgVH1EVsWfTR7oRMW rx9X1dNGtkyvnF71HvTgPgE2ahHUku5QeWm6DYEUVP5F9gdW5c8rQRj+32wFEt7r/WM1 4aAkCFK2C7rmkCJe1f8JO+pJQ5xfdgCERTN5LCFoKm5jhGIGmUQSZwyH3QlssCBIJbQo H6LQ== X-Gm-Message-State: AOAM532XgPxDiJUG5+dSS/HO0TxmsojGWeL3xmCJksa+pfksRoFN5fqf /7HbVErAzpBBWoHQEjJDvQP0aA== X-Google-Smtp-Source: ABdhPJzGHv3yOVK/OFuDYUvPRr+wO2dZ2zI0Hv/4fcc+7tB4Et4ttiAjrge5dNkRMcClzEboTkOSqw== X-Received: by 2002:a7b:cbc2:: with SMTP id n2mr13796209wmi.34.1613389918272; Mon, 15 Feb 2021 03:51:58 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 02/24] hw/misc/mps2-scc: Support configurable number of OSCCLK values Date: Mon, 15 Feb 2021 11:51:16 +0000 Message-Id: <20210215115138.20465-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Currently the MPS2 SCC device implements a fixed number of OSCCLK values (3). The variant of this device in the MPS3 AN524 board has 6 OSCCLK values. Switch to using a PROP_ARRAY, which allows board code to specify how large the OSCCLK array should be as well as its values. With a variable-length property array, the SCC no longer specifies default values for the OSCCLKs, so we must set them explicitly in the board code. This defaults are actually incorrect for the an521 and an505; we will correct this bug in a following patch. This is a migration compatibility break for all the mps boards. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- It would be possible to avoid the compat break, but we've already broken compat for the mps boards this release cycle (eg in commit eeae0b2bf4e69de2) when we added Clock support to the armsse code, so there's no point in trying to keep compat for this change. Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/mps2-scc.h | 7 +++---- hw/arm/mps2-tz.c | 5 +++++ hw/arm/mps2.c | 5 +++++ hw/misc/mps2-scc.c | 24 +++++++++++++----------- 4 files changed, 26 insertions(+), 15 deletions(-) diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h index f65d8732031..514da49f69e 100644 --- a/include/hw/misc/mps2-scc.h +++ b/include/hw/misc/mps2-scc.h @@ -19,8 +19,6 @@ #define TYPE_MPS2_SCC "mps2-scc" OBJECT_DECLARE_SIMPLE_TYPE(MPS2SCC, MPS2_SCC) =20 -#define NUM_OSCCLK 3 - struct MPS2SCC { /*< private >*/ SysBusDevice parent_obj; @@ -39,8 +37,9 @@ struct MPS2SCC { uint32_t dll; uint32_t aid; uint32_t id; - uint32_t oscclk[NUM_OSCCLK]; - uint32_t oscclk_reset[NUM_OSCCLK]; + uint32_t num_oscclk; + uint32_t *oscclk; + uint32_t *oscclk_reset; }; =20 #endif diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 82ce6262817..7c066c11ed4 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -219,6 +219,11 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms,= void *opaque, qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); + /* This will need to be per-FPGA image eventually */ + qdev_prop_set_uint32(sccdev, "len-oscclk", 3); + qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000); + qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000); + qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); } diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 39add416db5..81413b7133e 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -373,6 +373,11 @@ static void mps2_common_init(MachineState *machine) qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); + /* All these FPGA images have the same OSCCLK configuration */ + qdev_prop_set_uint32(sccdev, "len-oscclk", 3); + qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000); + qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000); + qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000); object_initialize_child(OBJECT(mms), "fpgaio", diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index ce1dfe93562..52a4e183b71 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -57,7 +57,7 @@ static bool scc_cfg_write(MPS2SCC *s, unsigned function, { trace_mps2_scc_cfg_write(function, device, value); =20 - if (function !=3D 1 || device >=3D NUM_OSCCLK) { + if (function !=3D 1 || device >=3D s->num_oscclk) { qemu_log_mask(LOG_GUEST_ERROR, "MPS2 SCC config write: bad function %d device %d\n", function, device); @@ -75,7 +75,7 @@ static bool scc_cfg_write(MPS2SCC *s, unsigned function, static bool scc_cfg_read(MPS2SCC *s, unsigned function, unsigned device, uint32_t *value) { - if (function !=3D 1 || device >=3D NUM_OSCCLK) { + if (function !=3D 1 || device >=3D s->num_oscclk) { qemu_log_mask(LOG_GUEST_ERROR, "MPS2 SCC config read: bad function %d device %d\n", function, device); @@ -227,7 +227,7 @@ static void mps2_scc_reset(DeviceState *dev) s->cfgctrl =3D 0x100000; s->cfgstat =3D 0; s->dll =3D 0xffff0001; - for (i =3D 0; i < NUM_OSCCLK; i++) { + for (i =3D 0; i < s->num_oscclk; i++) { s->oscclk[i] =3D s->oscclk_reset[i]; } for (i =3D 0; i < ARRAY_SIZE(s->led); i++) { @@ -254,12 +254,14 @@ static void mps2_scc_realize(DeviceState *dev, Error = **errp) LED_COLOR_GREEN, name); g_free(name); } + + s->oscclk =3D g_new0(uint32_t, s->num_oscclk); } =20 static const VMStateDescription mps2_scc_vmstate =3D { .name =3D "mps2-scc", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_UINT32(cfg0, MPS2SCC), VMSTATE_UINT32(cfg1, MPS2SCC), @@ -268,7 +270,8 @@ static const VMStateDescription mps2_scc_vmstate =3D { VMSTATE_UINT32(cfgctrl, MPS2SCC), VMSTATE_UINT32(cfgstat, MPS2SCC), VMSTATE_UINT32(dll, MPS2SCC), - VMSTATE_UINT32_ARRAY(oscclk, MPS2SCC, NUM_OSCCLK), + VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk, + 0, vmstate_info_uint32, uint32_t), VMSTATE_END_OF_LIST() } }; @@ -280,14 +283,13 @@ static Property mps2_scc_properties[] =3D { DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0), DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0), DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0), - /* These are the initial settings for the source clocks on the board. + /* + * These are the initial settings for the source clocks on the board. * In hardware they can be configured via a config file read by the * motherboard configuration controller to suit the FPGA image. - * These default values are used by most of the standard FPGA images. */ - DEFINE_PROP_UINT32("oscclk0", MPS2SCC, oscclk_reset[0], 50000000), - DEFINE_PROP_UINT32("oscclk1", MPS2SCC, oscclk_reset[1], 24576000), - DEFINE_PROP_UINT32("oscclk2", MPS2SCC, oscclk_reset[2], 25000000), + DEFINE_PROP_ARRAY("oscclk", MPS2SCC, num_oscclk, oscclk_reset, + qdev_prop_uint32, uint32_t), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.51.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TPCQ7hQbzvDDHnYGwctNAE4kUhgse5UxYRkoh3yegnE=; b=oHXWZxiVJIeV6r7ZllLuGWgHqlOcgt9i9v4+AcKvoXqHxs8Kq34g3qQAFi3ckE9KTP MnCbMYOUv2YHCBXYn40ABJQyxGcKCx5llTTp+iHN+wichcfQw4frUMsc+5ac3kZB3yni ZtDWTLRbdI6udDDZuXoUFNKM67bHOWqBKeB+p6Jjzv8hvpFvMAw/K2DQCgsPn4gq6jrF DZv6Cq/AAvwwih8YHllBNVpR2WueJD8heXk9b+RCkLjmM/2eLCQVP6AlU5CVS+FseWle PFhwH9Oj7/sIxwRke8c+27asaSzOZp6U9J7FsMqg4H64OCAj+uxM+o0Lz+t1pizJdFMT 37fA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TPCQ7hQbzvDDHnYGwctNAE4kUhgse5UxYRkoh3yegnE=; b=iR0+C+ysXEauhXU9/8ajvSwSQcgp/fFA9HDRjs0LftvWTt8W49N56FaXIgNyAPvjNv wkDqAktJik4SvG+BUZ6enfoCdHO0HXgtFlUxWQ2hggwKbVtRQSNJlYiGgumpOLoTpMBQ 6fxuTahvp0jo88ZBBWsveqMOsKfWP+x20voswJGPGF+i33LHsB6l6ZoaVVcKNMY+5g4J 9epz24DPBtO6+j+Sd/mP2BAC8LCtXGF1goXaJ41xBUXVShYXan3/7wqjM0zJZlh/BJoO xhu9rpK0MOvS1s2+XTA4IIi109eWyD9azN/x0YpKkWAkyo48A/qHWKZUsjNu2gtrD/p4 doLA== X-Gm-Message-State: AOAM533v82w1qc4Nwm3ua8B0p6atHH0eIEs0rLyV1Mb2rUT9ROIaNNBK xeQS+l0uiiv8idudVvyUNcXWTA== X-Google-Smtp-Source: ABdhPJwgP14LVqtJ5TrHAwQ7ibamRRjLBXmQTkMXI64NWkrlTA2lZgYA8s5lpGFxzhZN7k17pTJb2g== X-Received: by 2002:a05:6000:c1:: with SMTP id q1mr18562285wrx.114.1613389921530; Mon, 15 Feb 2021 03:52:01 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 03/24] hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511 Date: Mon, 15 Feb 2021 11:51:17 +0000 Message-Id: <20210215115138.20465-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) We were previously using the default OSCCLK settings, which are correct for the older MPS2 boards (mps2-an385, mps2-an386, mps2-an500, mps2-an511), but wrong for the mps2-an505 and mps2-511 implemented in mps2-tz.c. Now we're setting the values explicitly we can fix them to be correct. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 7c066c11ed4..976f5f5c682 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -221,8 +221,8 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, = void *opaque, qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); /* This will need to be per-FPGA image eventually */ qdev_prop_set_uint32(sccdev, "len-oscclk", 3); - qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000); - qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000); + qdev_prop_set_uint32(sccdev, "oscclk[0]", 40000000); + qdev_prop_set_uint32(sccdev, "oscclk[1]", 24580000); qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613390239; cv=none; d=zohomail.com; s=zohoarc; b=JJ6uRjAJpzF0DThWJfTYCSC+mAa/yxZgs5rQonOCpea8Nr0Ux8pU6MUqAzTdj32Whh3dBpAMl/XWnOS9LKkEhpTkiATpiCLVKimyneEEKB6Re+YjCqSoXGyZ1IORZoOdg3MRhDIhnLygPGQBiDNXPj2oX+nq3dtE93UvPgbMBGs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613390239; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PJ5Ra3RoZTdSQMlk8tvN9OiLpHO5i6WdVZO2RyHhEAs=; b=ejlTJtOHhqgkntRu0U7AuSaqJsWwngWqYRwhOSm793I6qCfLrx5/VVWPndd0YDIrIvNQ2lSc8cMkWS/69kK9L79J6j0tmTHOHS0pCY/79e09vOIvLbJ77lSbDhFwfN28zZp/W4aZCJo36bCKi6EBxcz9XB+VP3N9n6V7cIHm15Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613390238747852.68352513992; Mon, 15 Feb 2021 03:57:18 -0800 (PST) Received: from localhost ([::1]:50406 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBcVB-0006XV-KO for importer@patchew.org; Mon, 15 Feb 2021 06:57:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39092) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBcQD-0006nI-2c for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:09 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:37483) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBcQA-0003qy-1K for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:08 -0500 Received: by mail-wr1-x430.google.com with SMTP id v15so8506810wrx.4 for ; Mon, 15 Feb 2021 03:52:05 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PJ5Ra3RoZTdSQMlk8tvN9OiLpHO5i6WdVZO2RyHhEAs=; b=GYvhHamxOYpdFGBeN6ym5PzbLQ4e1nXVeGAiIvPxdpvIB4XExT5eCOoIRQMkBlp/tW 1FGxIs3Z2qnxL4Q3dzxI2iWYLhhjMNW44cFLlljEILeMfn+OP+rjxeEfiICFo8po36Tw oHsDQhCJz1jTXqiqnHqgvg1Hg96ao6078pDdg+AV//iLpD1I5XpAXTqtrILPnUQkF+uf ZYidsf9CBzZrIWJMngcNq/X0BaJfSwxYAH5gOPlCMS6FPxLpvuV2cgVlFgzqtmU8InoP brc7FDmhrna+d0bwog+ez6W1SXcKTZ+L90APG1MmhG6cM5FsV567qR/8YSeNYUvl79BL xbWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PJ5Ra3RoZTdSQMlk8tvN9OiLpHO5i6WdVZO2RyHhEAs=; b=kvPe14y5E3BVvckAFyTxLHWer128Wo7iFTLzJ+6lxyssIsckHf75neFZHd5k6l1VDG mfxJG3f46IjnHkH39w5hN91pSXY9F+FRkKu/wN1e1PNvzzwSqVd6GN9owLxkOX7+XZ2G VbhJ1XuOxsQfEHljhtGmGvrBNodVS5BlEgNCkS0AHSsMg9nFX0cR7E3XfkplyVnFvbvd yk4SDeP9i/jY17rozktZV7wClucEhuSKPZ2FbL8X6Tj0ba+CuiW9Xwmv17catM0OZiIL bP/cXA1Jb9oJScqIHuR59DZBQA+f6aHad2mSu00LiN4zcUWgu9ghXoTj1sB0F+gK+fR5 1/EQ== X-Gm-Message-State: AOAM532inadQON70YdMLHnmwngiy0Qe+eJ9ZcN2zIChmJzWxxAlarqBy zL4eIadGj3woMCckOsE7fGpksw== X-Google-Smtp-Source: ABdhPJzS4Y3IzQNIQy3CZ2nVoQe2BrRbmGm1WofmRhgrqRbiZervKwhJtPUdOM3WVyy4o2COvMINdg== X-Received: by 2002:adf:b611:: with SMTP id f17mr18119562wre.8.1613389924860; Mon, 15 Feb 2021 03:52:04 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 04/24] hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board Date: Mon, 15 Feb 2021 11:51:18 +0000 Message-Id: <20210215115138.20465-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The AN505 and AN511 happen to share the same OSCCLK values, but the AN524 will have a different set (and more of them), so split the settings out to be per-board. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 976f5f5c682..9add1453cc2 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -77,6 +77,8 @@ struct MPS2TZMachineClass { MPS2TZFPGAType fpga_type; uint32_t scc_id; uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ + uint32_t len_oscclk; + const uint32_t *oscclk; const char *armsse_type; }; =20 @@ -115,6 +117,12 @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineC= lass, MPS2TZ_MACHINE) /* Slow 32Khz S32KCLK frequency in Hz */ #define S32KCLK_FRQ (32 * 1000) =20 +static const uint32_t an505_oscclk[] =3D { + 40000000, + 24580000, + 25000000, +}; + /* Create an alias of an entire original MemoryRegion @orig * located at @base in the memory map. */ @@ -213,17 +221,18 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms= , void *opaque, MPS2SCC *scc =3D opaque; DeviceState *sccdev; MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); + int i; =20 object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); sccdev =3D DEVICE(scc); qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); - /* This will need to be per-FPGA image eventually */ - qdev_prop_set_uint32(sccdev, "len-oscclk", 3); - qdev_prop_set_uint32(sccdev, "oscclk[0]", 40000000); - qdev_prop_set_uint32(sccdev, "oscclk[1]", 24580000); - qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); + qdev_prop_set_uint32(sccdev, "len-oscclk", mmc->len_oscclk); + for (i =3D 0; i < mmc->len_oscclk; i++) { + g_autofree char *propname =3D g_strdup_printf("oscclk[%d]", i); + qdev_prop_set_uint32(sccdev, propname, mmc->oscclk[i]); + } sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); } @@ -676,6 +685,8 @@ static void mps2tz_an505_class_init(ObjectClass *oc, vo= id *data) mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id =3D 0x41045050; mmc->sysclk_frq =3D 20 * 1000 * 1000; /* 20MHz */ + mmc->oscclk =3D an505_oscclk; + mmc->len_oscclk =3D ARRAY_SIZE(an505_oscclk); mmc->armsse_type =3D TYPE_IOTKIT; } =20 @@ -692,6 +703,8 @@ static void mps2tz_an521_class_init(ObjectClass *oc, vo= id *data) mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id =3D 0x41045210; mmc->sysclk_frq =3D 20 * 1000 * 1000; /* 20MHz */ + mmc->oscclk =3D an505_oscclk; /* AN521 is the same as AN505 here */ + mmc->len_oscclk =3D ARRAY_SIZE(an505_oscclk); mmc->armsse_type =3D TYPE_SSE200; } =20 --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613390200; cv=none; d=zohomail.com; s=zohoarc; b=dg0Bs1OgsGxW0unRV2aa1TkBjEp1Eqn5JiTH4MA7lBGUCEVnIMSAtkavOQ79BV1OUvmyuZVEypjO10VV1Tqb6mlQ2nQYorojs8A89lMuwomr4Ra8PUFUlDX2wgzRHvuyzlxicQ2G+cQQkBd18fXm/EiqYdAMuG136G0gC08jD84= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=shTSJl6L/H8wb4siiGCFXvHoXe+zewsk4Ogg6uSOUOc=; b=eMzzFH4FkG4AD266JpfsaeErVXuABv5yB6R/i9kl9N7IbbIqe1N8DJFsRiV/6vz9t8 /csPJEP6Hk0uP8BjfUHZQ3xob7NStxMum6j7G+V0mqBJt7LLEyeh5/a9J67o5d2ioi41 Vh304pPZqir5NyW2MEBaBUzUu7M6JCfW08YLeHzBN8jCsj/LTWJ4+IIGGxLMJlTGCxEv hjuDlJLMSnZZ/pH4Or5WqxN7TZSOaode99kTC51R50uGi+eK50nqJh1YDQj4NYt0joze Vdq3fFf2x8OvT2UxcVEfXxefhFacf7cJIRaWSeP1edPkP7iB9kUgK8PpeGt8crGLsqU8 PIqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=shTSJl6L/H8wb4siiGCFXvHoXe+zewsk4Ogg6uSOUOc=; b=Dha1kp5tO1OUEzMOePg07zt6LtsrXtKz7XYBQHUUkeu9iMDQm5l3BU/K0Gqi5bjswr mbixwegajCXOp+51N6MksV3clcE5y+vrTACfhWuvdxNVQO1YoXe3EMo/+3ow3AwbZpSB WOklF4NXTAtZeTH0XmhVpajQPReEOfzMSo7yJHvSg/jpU5v/qFzL8Dw+1BFw1drjF1xe jqC3Ml6rZcDnIbW2avvcWfCwx2d/TDZvxn6oFgKbk84TBV3m9XmiDNDGcNHgmjCYUvti TDVIlkaMNxmJaOaGTWV2cPLNu+VKztiwXRN8X8w0sWXfn9ZBIGkibuouvDGadFwCspw4 4eZQ== X-Gm-Message-State: AOAM530aNACZ2GNK4UbdEtxf2W7TxX5POb43XFUB454CfSW7PVG90zO/ zX6W8Vomcm5SgnDhfrMGoa6cfA== X-Google-Smtp-Source: ABdhPJwVXjEuDU+18UbsXTHezjzXQHsuL9AHaS3SwmBMOhqm1u0LKPV3Dk4mHXcVH6KdyaOIsZLyQQ== X-Received: by 2002:a1c:2ed4:: with SMTP id u203mr14278234wmu.45.1613389928504; Mon, 15 Feb 2021 03:52:08 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 05/24] hw/misc/mps2-fpgaio: Make number of LEDs configurable by board Date: Mon, 15 Feb 2021 11:51:19 +0000 Message-Id: <20210215115138.20465-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The MPS2 board has 2 LEDs, but the MPS3 board has 10 LEDs. The FPGAIO device is similar on both sets of boards, but the LED0 register has correspondingly more bits that have an effect. Add a device property for number of LEDs. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/mps2-fpgaio.h | 5 ++++- hw/misc/mps2-fpgaio.c | 31 +++++++++++++++++++++++-------- 2 files changed, 27 insertions(+), 9 deletions(-) diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h index a010fdb2b6d..bfe73134e78 100644 --- a/include/hw/misc/mps2-fpgaio.h +++ b/include/hw/misc/mps2-fpgaio.h @@ -28,13 +28,16 @@ #define TYPE_MPS2_FPGAIO "mps2-fpgaio" OBJECT_DECLARE_SIMPLE_TYPE(MPS2FPGAIO, MPS2_FPGAIO) =20 +#define MPS2FPGAIO_MAX_LEDS 32 + struct MPS2FPGAIO { /*< private >*/ SysBusDevice parent_obj; =20 /*< public >*/ MemoryRegion iomem; - LEDState *led[2]; + LEDState *led[MPS2FPGAIO_MAX_LEDS]; + uint32_t num_leds; =20 uint32_t led0; uint32_t prescale; diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c index 6af0e8f837a..b28a1be22cc 100644 --- a/hw/misc/mps2-fpgaio.c +++ b/hw/misc/mps2-fpgaio.c @@ -177,9 +177,14 @@ static void mps2_fpgaio_write(void *opaque, hwaddr off= set, uint64_t value, =20 switch (offset) { case A_LED0: - s->led0 =3D value & 0x3; - led_set_state(s->led[0], value & 0x01); - led_set_state(s->led[1], value & 0x02); + if (s->num_leds !=3D 0) { + int i; + + s->led0 =3D value & MAKE_64BIT_MASK(0, s->num_leds); + for (i =3D 0; i < s->num_leds; i++) { + led_set_state(s->led[i], value & (1 << i)); + } + } break; case A_PRESCALE: resync_counter(s); @@ -238,7 +243,7 @@ static void mps2_fpgaio_reset(DeviceState *dev) s->pscntr =3D 0; s->pscntr_sync_ticks =3D now; =20 - for (size_t i =3D 0; i < ARRAY_SIZE(s->led); i++) { + for (size_t i =3D 0; i < s->num_leds; i++) { device_cold_reset(DEVICE(s->led[i])); } } @@ -256,11 +261,19 @@ static void mps2_fpgaio_init(Object *obj) static void mps2_fpgaio_realize(DeviceState *dev, Error **errp) { MPS2FPGAIO *s =3D MPS2_FPGAIO(dev); + int i; =20 - s->led[0] =3D led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH, - LED_COLOR_GREEN, "USERLED0"); - s->led[1] =3D led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH, - LED_COLOR_GREEN, "USERLED1"); + if (s->num_leds > MPS2FPGAIO_MAX_LEDS) { + error_setg(errp, "num-leds cannot be greater than %d", + MPS2FPGAIO_MAX_LEDS); + return; + } + + for (i =3D 0; i < s->num_leds; i++) { + g_autofree char *ledname =3D g_strdup_printf("USERLED%d", i); + s->led[i] =3D led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_= HIGH, + LED_COLOR_GREEN, ledname); + } } =20 static bool mps2_fpgaio_counters_needed(void *opaque) @@ -303,6 +316,8 @@ static const VMStateDescription mps2_fpgaio_vmstate =3D= { static Property mps2_fpgaio_properties[] =3D { /* Frequency of the prescale counter */ DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000), + /* Number of LEDs controlled by LED0 register */ + DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO, num_leds, 2), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gQ23dryhYlpvJQf3jI2/hncVTbnfMBWe8fcCzHmxYJw=; b=mylxvaoUVxgcyeE5u9vPxsFK32UYRzO7GKA9+a60vV3G2kaxC2ZvM4d5W/3np3s6KY CYPRLceB5+gtEItUj8M8f6/ema3TARi1A0VHZ7WLOsaC/Buxhd8gl+e9IXZUoAD54rCE rVu0CCPAZJBti+sFeaQMcpKOXB8s5lKOkfpP2VpbNwj9c1PbkW7GrF+e5k6b7dFveQPV RhBbI1RzYvB7tew5LnCE88cmTVJPseDzms/Oj7dSwVxn1qCToS8w3aMCyFx0gUh6sjAG tvkb+ZOf4+9rdrJkZ1ddUtC3KgIVjTo9vpT3ggv20OWKuWj0w4jYFsWmzV3RE4eUWIVH a/uA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gQ23dryhYlpvJQf3jI2/hncVTbnfMBWe8fcCzHmxYJw=; b=qe/wHjBsvJ7mrDobw9QgAGFWjj4VzG+005YHBIAurv0EAaPzSp1XIr0L9UzdpLaUCj AHUxfVi5gI7s/j9NxP/ZTPo4O1s1uc/xNigFc2b8JIbxezZJKV/ve673ycaAB7pyRkCP hK7S47AoX2popYFhmWZ6U9eSv7bfdpf1TKEcGQOIZXQoO5NHqhh/hij3RfrAIppNywmw nYZGo2I2JYZzCZvCUGujgpXpfhVfWIA1G/Ae3mHK17QdYh15Bwk5Lk/p3ZLN6DMqzRbW 78yzX9bllkwJa9zvv2X67MCiEl19/IoauyokCglb/SmwpkaLIgkcee93lbG1wVhpM8Ej Og8g== X-Gm-Message-State: AOAM531WweDTM++k1PaW1e61WYIUtqEIQNUzR8hfwcnWK7JfO3DP7/5G orrbZWyxZCC3jJX0b5lSTD+d0g== X-Google-Smtp-Source: ABdhPJw07kg4M+0/1iR7hFsHJh0ab2zmPcIXP8433UtT3Mf+z0smBqZ6C4rl4lGkwbRp8Gn0K85Aiw== X-Received: by 2002:a1c:4ca:: with SMTP id 193mr13925166wme.178.1613389932082; Mon, 15 Feb 2021 03:52:12 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 06/24] hw/misc/mps2-fpgaio: Support SWITCH register Date: Mon, 15 Feb 2021 11:51:20 +0000 Message-Id: <20210215115138.20465-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) MPS3 boards have an extra SWITCH register in the FPGAIO block which reports the value of some switches. Implement this, governed by a property the board code can use to specify whether whether it exists. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/mps2-fpgaio.h | 1 + hw/misc/mps2-fpgaio.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h index bfe73134e78..0d3c8eef56c 100644 --- a/include/hw/misc/mps2-fpgaio.h +++ b/include/hw/misc/mps2-fpgaio.h @@ -38,6 +38,7 @@ struct MPS2FPGAIO { MemoryRegion iomem; LEDState *led[MPS2FPGAIO_MAX_LEDS]; uint32_t num_leds; + bool has_switches; =20 uint32_t led0; uint32_t prescale; diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c index b28a1be22cc..acbd0be9f4b 100644 --- a/hw/misc/mps2-fpgaio.c +++ b/hw/misc/mps2-fpgaio.c @@ -35,6 +35,7 @@ REG32(CLK100HZ, 0x14) REG32(COUNTER, 0x18) REG32(PRESCALE, 0x1c) REG32(PSCNTR, 0x20) +REG32(SWITCH, 0x28) REG32(MISC, 0x4c) =20 static uint32_t counter_from_tickoff(int64_t now, int64_t tick_offset, int= frq) @@ -156,7 +157,15 @@ static uint64_t mps2_fpgaio_read(void *opaque, hwaddr = offset, unsigned size) resync_counter(s); r =3D s->pscntr; break; + case A_SWITCH: + if (!s->has_switches) { + goto bad_offset; + } + /* User-togglable board switches. We don't model that, so report 0= . */ + r =3D 0; + break; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "MPS2 FPGAIO read: bad offset %x\n", (int) offset); r =3D 0; @@ -318,6 +327,7 @@ static Property mps2_fpgaio_properties[] =3D { DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000), /* Number of LEDs controlled by LED0 register */ DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO, num_leds, 2), + DEFINE_PROP_BOOL("has-switches", MPS2FPGAIO, has_switches, false), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613390358; cv=none; d=zohomail.com; s=zohoarc; b=Chd1CUo9iLTPk4oLy2RGkdFamjs7QBLsBg1l/PbvR9LUlsFxIZfyRfVOkIF0kfbvZwuc+id0IcequKMeGlnsx7+O82u+Yi1xEvEYqbXYYUt1TKwVAoHv3+6n8J/lU7RmvBbjxU/bZmRPyC33q7/Tb7njJF7RtgjlGmYiznu4FtA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613390358; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oXZJdmuHAUaTxViiBBTMLXgaD9//CuJ3J4es1nlQ2XM=; b=A/u8BBDvmUXzedCpFjGHMVs+oy7qyg8oI+1IhMa4Z/URYrlT+CNBcr9NZwHaYs2DYdt0Z+p1wTe7eQwTX1n1xWcwvBBK5tSu3czCJZoS25zEE4LznIixCv28TEOtpZPInmPVvF9qGxzJ4JWPY+kfLCLXNElUxB5fr0GP98z3okY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613390358549188.5174997151446; Mon, 15 Feb 2021 03:59:18 -0800 (PST) Received: from localhost ([::1]:56952 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBcX7-0000oI-B0 for importer@patchew.org; Mon, 15 Feb 2021 06:59:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39232) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBcQN-0007DO-6E for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:19 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:38152) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBcQK-0003vJ-91 for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:18 -0500 Received: by mail-wm1-x336.google.com with SMTP id x4so9060386wmi.3 for ; Mon, 15 Feb 2021 03:52:15 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oXZJdmuHAUaTxViiBBTMLXgaD9//CuJ3J4es1nlQ2XM=; b=rev3AuoTDjhbNSys8k4mFujpcmZqOtgy7mxYuemVCzeox9hVgOoJQSDVdDB0ATvHH4 leuVEzeqxiIdyVPyX06ip/sTyATmYjBx9SD6xI9HNy1EwNCpfX2OxXUce6nlvcgxlX0I 6s2DIn9ogiomVwrdXFvRFtfi4QPhEyHJsvmw9YjQVCzWcnfpQ/3Tu8Pf+fIYbYC9dDH/ SpNOX95jvZETUxgcsu/UCos1j6SpGBtMfgjLOBgmmGwXT3GLO7PrIouT01GDKuFn2dR+ nVCy3s7f7MY0Nw26d3dILXPyZJPmgNCvPH487w9fDqGypIl2BzXLCprV9WhVVCLl0k37 pPiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oXZJdmuHAUaTxViiBBTMLXgaD9//CuJ3J4es1nlQ2XM=; b=jVxGcXv4RX0JJNjXhRE/qh62ufw4cY64S7+er6n6yGy1k0v1Aw6OCGDMMF+FcGH8bl Yzy68R2eHL5a0W4w3VyVT9vh45CH9OBHF/rlAh4N9yJx7z2oLMyNhA+7dmc4wJRo/j6B a6FhdISOYLd8RTsQxK89+PvS3eR/wRB30o4lomswUH4ZkwGaVIIZy51WaqW+fFnmaZ7E Ealn/SQUSUYUqGhsTUiPyt1osYFtXzWz8+Slro/wmo4EfMnpDpi+4jNB0U/XA9YQ2RKk QS/h6aS9+kEP9ZGmngabpmwoRaiYVDDWH1WsTwFU2bFWbTsc3CGOqFenHNTF7n50EXcP OQYQ== X-Gm-Message-State: AOAM532Cp6IbQlCV4fvYOH0kTg5aV13XhjaOQFeWEY2m0UNjCJVMnkV6 mB3PvFdRKp/B2lVYuSrImwG3wA== X-Google-Smtp-Source: ABdhPJwyPsLj2a7Ts3Lu2dfxTirtHsBABw0xGcGinpNiHPuhiL3ju2++LNzcOKN2izWjTG6fY85iIg== X-Received: by 2002:a05:600c:2dd0:: with SMTP id e16mr14528115wmh.129.1613389934819; Mon, 15 Feb 2021 03:52:14 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 07/24] hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board Date: Mon, 15 Feb 2021 11:51:21 +0000 Message-Id: <20210215115138.20465-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Set the FPGAIO num-leds and have-switches properties explicitly per-board, rather than relying on the defaults. The AN505 and AN521 both have the same settings as the default values, but the AN524 will be different. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 9add1453cc2..6e345cf1f09 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -79,6 +79,8 @@ struct MPS2TZMachineClass { uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ uint32_t len_oscclk; const uint32_t *oscclk; + uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ + bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ const char *armsse_type; }; =20 @@ -241,8 +243,11 @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *m= ms, void *opaque, const char *name, hwaddr size) { MPS2FPGAIO *fpgaio =3D opaque; + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); =20 object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAI= O); + qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); + qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_swit= ches); sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); } @@ -687,6 +692,8 @@ static void mps2tz_an505_class_init(ObjectClass *oc, vo= id *data) mmc->sysclk_frq =3D 20 * 1000 * 1000; /* 20MHz */ mmc->oscclk =3D an505_oscclk; mmc->len_oscclk =3D ARRAY_SIZE(an505_oscclk); + mmc->fpgaio_num_leds =3D 2; + mmc->fpgaio_has_switches =3D false; mmc->armsse_type =3D TYPE_IOTKIT; } =20 @@ -705,6 +712,8 @@ static void mps2tz_an521_class_init(ObjectClass *oc, vo= id *data) mmc->sysclk_frq =3D 20 * 1000 * 1000; /* 20MHz */ mmc->oscclk =3D an505_oscclk; /* AN521 is the same as AN505 here */ mmc->len_oscclk =3D ARRAY_SIZE(an505_oscclk); + mmc->fpgaio_num_leds =3D 2; + mmc->fpgaio_has_switches =3D false; mmc->armsse_type =3D TYPE_SSE200; } =20 --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613390573; cv=none; d=zohomail.com; s=zohoarc; b=PKCFCEHaGl4kxlv0kDJrzcVYLesqwL+LAqpnIAHm/7kiERUK4HPZMRiXvzPPFcDF5hp5Qoe00Gz2Erdme0FjB2I6cGUH1QyuWDxGgto+e1fA6T+PlrNQwZGBVZCD1Lt1a0PKw8cPQhgVvsSSH5t8beYEtu7Q3ZL6otlYdkWlzCo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613390573; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SKNE8HC09qZegLpjoVlF4jaNo0rqYYfYydVh0a/tGNg=; b=YBjI7ozAAHnqrEDBiJWGMnjjzlr1ZkcugBTQZ924fGBuqShDq+p8HahQ3k4PQmTI23X5ZgENKfwMdVUjHc2xVJNnnrGN6uPpXWg+kKj4cEpUVHxQdEDwh0G2RyiKihx9f8ZljtETCc65KvLITi8tGs819r4RHV3FxlxBkLJ39zE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16133905732971005.6582053139435; Mon, 15 Feb 2021 04:02:53 -0800 (PST) Received: from localhost ([::1]:38346 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBcaa-0004lA-5L for importer@patchew.org; Mon, 15 Feb 2021 07:02:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39286) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBcQQ-0007LB-09 for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:22 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:45500) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBcQM-0003wA-AZ for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:21 -0500 Received: by mail-wr1-x42d.google.com with SMTP id v7so8454659wrr.12 for ; Mon, 15 Feb 2021 03:52:17 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SKNE8HC09qZegLpjoVlF4jaNo0rqYYfYydVh0a/tGNg=; b=ItvzkFszLoSbG0DF64GJ/LUAgzbrGCYSy/c30EJVyn90bIwZeajLSYtPJyVZkuwtCi S7qBcu/si6MbtAijXdaXJamj/iEP/I5uCeJ7JVq3goxbsLIh1d64Va+6sfCajivGs/02 i9Vq0Naaz4J0eSEzWA2aOBvwaAr30g/De/9XxHRqGYwJKaPI8y3AYhAfInNKhYfT3mTA CkPEzlrOTuCtEPCeRIYOTZ0Ykr1cYjMmW2D5m/+Y9it0sgxtLUApYi9CDYpWkaXqG2vt E7JfYWREfTj26Prx5J+M5Luv1DdJ+k7BQGBD0b+zMuoxt/Bws4vd3tnQ1z85k7HCThIb /rmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SKNE8HC09qZegLpjoVlF4jaNo0rqYYfYydVh0a/tGNg=; b=Sle3KcZcv3aaQpZVB6Jg6vNm3E6hoUkWPwld9iqYi4YDr+QPa5KriuMwykYYsxRPyo vTfT9yVILWpyyidg7m2Msf6d2Qbz3Z8BwbPMxmWtohRqLlnGb4noWAlDYru4zpq2HzlF cu+8/jQg0Hw0ICV45/m5ogjvD+B4hk2T4OopOQcTDM7gQ9jToxSHb7iA05KGO6ko8Fan 4zQqV2nf2FYUnTJ/7mBEUJKNOuxT+cTigaoizHgwETRSPLtaRKEO66O0sX9C05FCUKP7 m2+kg/fvkzVhIwb490Kj2spQEcnjJnFK2+3eqp3Mh5Ns/AudE4Jj6xk8yuMxRmSnqJTA Pc6w== X-Gm-Message-State: AOAM5329EOipwa1jX87/ub0TRrI2dUXgKj7+Mfn+8ajADYShZtLlR6UY 1X5J6d/0lB1sIwPv1RATSikQKg== X-Google-Smtp-Source: ABdhPJxoJCbBXYMDKUyLqA5J+sWR72g/ANqiOeit4P4KjLC+LUUCcMCd/rwHv66fCl0T7T07RMchEg== X-Received: by 2002:adf:f54c:: with SMTP id j12mr18144770wrp.175.1613389936989; Mon, 15 Feb 2021 03:52:16 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 08/24] hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type Date: Mon, 15 Feb 2021 11:51:22 +0000 Message-Id: <20210215115138.20465-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) In the mps2-tz board code, we handle devices whose interrupt lines must be wired to all CPUs by creating IRQ splitter devices for the AN521, because it has 2 CPUs, but wiring the device IRQ directly to the SSE/IoTKit input for the AN505, which has only 1 CPU. We can avoid making an explicit check on the board type constant by instead creating and using the IRQ splitters for any board with more than 1 CPU. This avoids having to add extra cases to the conditionals every time we add new boards. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- This removes the only current user of mmc->fpga_type, but we're going to want it again later in the series. Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 6e345cf1f09..5561c30b126 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -139,17 +139,14 @@ static void make_ram_alias(MemoryRegion *mr, const ch= ar *name, static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) { /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ - MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); + MachineClass *mc =3D MACHINE_GET_CLASS(mms); =20 assert(irqno < MPS2TZ_NUMIRQ); =20 - switch (mmc->fpga_type) { - case FPGA_AN505: - return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irq= no); - case FPGA_AN521: + if (mc->max_cpus > 1) { return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); - default: - g_assert_not_reached(); + } else { + return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irq= no); } } =20 @@ -437,10 +434,12 @@ static void mps2tz_common_init(MachineState *machine) sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); =20 /* - * The AN521 needs us to create splitters to feed the IRQ inputs - * for each CPU in the SSE-200 from each device in the board. + * If this board has more than one CPU, then we need to create splitte= rs + * to feed the IRQ inputs for each CPU in the SSE from each device in = the + * board. If there is only one CPU, we can just wire the device IRQ + * directly to the SSE's IRQ input. */ - if (mmc->fpga_type =3D=3D FPGA_AN521) { + if (mc->max_cpus > 1) { for (i =3D 0; i < MPS2TZ_NUMIRQ; i++) { char *name =3D g_strdup_printf("mps2-irq-splitter%d", i); SplitIRQ *splitter =3D &mms->cpu_irq_splitter[i]; --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613390846; cv=none; d=zohomail.com; s=zohoarc; b=KQ+Z8df47znJdx1UNg5KC+5OC+13sThxFs6mc21eLVrBcF8nkj6kywH6mlyrMid1RfhMZw4sy3QxEfjky1+svgwtTWqDFQbD/ra80JfQOnMw9f2RNdJ5uOt2pLVKQedBqTmybh29OjUPyZD+w2KE8zx0/pTy1bf6iLwtfWOEdVY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613390846; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YocI5mwW2d9jWoFEVN2qubyzzCutaE6tbqO05qvCxyI=; b=VpOT0gcTZxMT7v2LW/dFFvzELYiWvBu95aZ6ih0qhCrRw3ybYweQMILfpz8RHjMTqAkAIT0/rTcamGx6YErYYdiCobgyO1RJg+258dN6OYHcr3vw4Jka9YGAi1zlJ5T58J0eBDUKOFFborQVUtcOThgotMqzclERfkPKw0wj8J8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613390846088201.31508387152405; Mon, 15 Feb 2021 04:07:26 -0800 (PST) Received: from localhost ([::1]:46962 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBcey-0008Tr-R4 for importer@patchew.org; Mon, 15 Feb 2021 07:07:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39316) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBcQR-0007P3-Ku for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:23 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:38143) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBcQP-0003yR-Ul for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:23 -0500 Received: by mail-wm1-x32b.google.com with SMTP id x4so9060671wmi.3 for ; Mon, 15 Feb 2021 03:52:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YocI5mwW2d9jWoFEVN2qubyzzCutaE6tbqO05qvCxyI=; b=Li5nd5+qO8jmsWicbG40YqUZ5Uq2zeOVi9HL2zjMN0p578CgzUVaYSq9pUZR3nptox 9VRICfQeEivD99KrvOvXfe4PEsQVExgXWmRteQIdhX6Tz76Bvz8VOU6g5K8QtrLtgM9z 4VYZQQQZik5Em8Yxk8zYE2/HPtaaUzxU+x/Fx5Vx6HIQNfA1aBVE+SQ8fOhnXQ7yPrTv SkjjSxpKU3jNcGAMVN/JWKUpGBjAWjj0mmSec7SX2ahw9+uA4GcJpd/GH5b1vl1bpl85 LzA78oZONNIzhnnKP4b00m0HXbzPZiDJnnuvEWv0PJD53bZEwPj6IwV8NHzbXQPzmzHm UxAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YocI5mwW2d9jWoFEVN2qubyzzCutaE6tbqO05qvCxyI=; b=HmpxT9uMsLKIiI6Ol52aENQwsYy/dBqHyAVtAP3ITxg/y5OYNwyIDIv8j3mq4CuAMG ZxicroRgNGTARhSKsiH8lZ0PTd+QBqXAKYqx6gk275c8N/BUhVm/YuCotMyz5RzvZlP3 /QCrLAGZsJEWu6pQ5g4vjdEug61An+B9R+/Mg4n51hLVI0lCRiC05fUh54aTmRrXeghr fcvMJcexMe+PaQyaPR/6TuQCDSRUJnCSAtgtVwDxQkyqw7IJVuiE+R5wkYDK4GY47sT8 gQCCGWeqRr6ontlnQtMrIkNz7CPReV9s8QzaYeZFkAakFK3exT5UxB0gUQpCjKbPCGZI B/WQ== X-Gm-Message-State: AOAM533TgdJcU1GTOIpneWRIBoWx16DimWFxHYWHRvOXeErItoEzX26H gUaFqV5fxM2aCxhUJGAr3H5LJlUYhmHh6A== X-Google-Smtp-Source: ABdhPJzwD5/xhdlvl2zivj5vct+gdi9XnZynLb9l6y8OfEIchHCq51Ad6nNJmKk8OYayrnr0B4BI2g== X-Received: by 2002:a1c:4ca:: with SMTP id 193mr13925685wme.178.1613389940668; Mon, 15 Feb 2021 03:52:20 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 09/24] hw/arm/mps2-tz: Make number of IRQs board-specific Date: Mon, 15 Feb 2021 11:51:23 +0000 Message-Id: <20210215115138.20465-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The AN524 has more interrupt lines than the AN505 and AN521; make numirq board-specific rather than a compile-time constant. Since the difference is small (92 on the current boards and 95 on the new one) we don't dynamically allocate the cpu_irq_splitter[] array but leave it as a fixed length array whose size is the maximum needed for any of the boards. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 5561c30b126..6362652e617 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -65,7 +65,7 @@ #include "hw/qdev-clock.h" #include "qom/object.h" =20 -#define MPS2TZ_NUMIRQ 92 +#define MPS2TZ_NUMIRQ_MAX 92 =20 typedef enum MPS2TZFPGAType { FPGA_AN505, @@ -81,6 +81,7 @@ struct MPS2TZMachineClass { const uint32_t *oscclk; uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ + int numirq; /* Number of external interrupts */ const char *armsse_type; }; =20 @@ -105,7 +106,7 @@ struct MPS2TZMachineState { SplitIRQ sec_resp_splitter; qemu_or_irq uart_irq_orgate; DeviceState *lan9118; - SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ]; + SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; Clock *sysclk; Clock *s32kclk; }; @@ -140,8 +141,9 @@ static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms,= int irqno) { /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ MachineClass *mc =3D MACHINE_GET_CLASS(mms); + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); =20 - assert(irqno < MPS2TZ_NUMIRQ); + assert(irqno < mmc->numirq); =20 if (mc->max_cpus > 1) { return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); @@ -428,7 +430,7 @@ static void mps2tz_common_init(MachineState *machine) iotkitdev =3D DEVICE(&mms->iotkit); object_property_set_link(OBJECT(&mms->iotkit), "memory", OBJECT(system_memory), &error_abort); - qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); + qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); @@ -439,8 +441,9 @@ static void mps2tz_common_init(MachineState *machine) * board. If there is only one CPU, we can just wire the device IRQ * directly to the SSE's IRQ input. */ + assert(mmc->numirq <=3D MPS2TZ_NUMIRQ_MAX); if (mc->max_cpus > 1) { - for (i =3D 0; i < MPS2TZ_NUMIRQ; i++) { + for (i =3D 0; i < mmc->numirq; i++) { char *name =3D g_strdup_printf("mps2-irq-splitter%d", i); SplitIRQ *splitter =3D &mms->cpu_irq_splitter[i]; =20 @@ -693,6 +696,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, vo= id *data) mmc->len_oscclk =3D ARRAY_SIZE(an505_oscclk); mmc->fpgaio_num_leds =3D 2; mmc->fpgaio_has_switches =3D false; + mmc->numirq =3D 92; mmc->armsse_type =3D TYPE_IOTKIT; } =20 @@ -713,6 +717,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, vo= id *data) mmc->len_oscclk =3D ARRAY_SIZE(an505_oscclk); mmc->fpgaio_num_leds =3D 2; mmc->fpgaio_has_switches =3D false; + mmc->numirq =3D 92; mmc->armsse_type =3D TYPE_SSE200; } =20 --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613390125; cv=none; d=zohomail.com; s=zohoarc; b=PzCIgJTH33UqgcQVLdAT8u1eUFGpN6slJoQC5z2dCQnReW8RRwTL5zVTXHp7vH+GAbkZWdatB1eBwmfZkZYT3HrOaYpTxvsQScOAQch69lGC3zDbPLjam64qM/hPk8PKYqozvnLcYmNMLdqvbZIVkMFzeFhvSkC49sSFFdW76cA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613390125; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DWcDLedvIdrpO/Dyf18yelSJMFxD3oqKzuBHwfEwOy0=; b=WJTRKpY+8rTbb8GRjVaAw1NEluawRFAe/XyebMiAK3N9rUo4L/4I0SC5FjG5cA4dVRooW16hnaQWggMrarYrkrzCvu2xYpULBJTUlvI6NECEWkHyNIEdJ2jLZtwuQxrmG+UpaO5WJGWZjJquA+Vp1YqUUlqYFN2qW0cU2qLKY0c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613390125369487.6176895509086; Mon, 15 Feb 2021 03:55:25 -0800 (PST) Received: from localhost ([::1]:42468 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBcTM-0003Er-2X for importer@patchew.org; Mon, 15 Feb 2021 06:55:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39354) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBcQV-0007aQ-Sj for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:27 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:38154) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBcQU-0003zs-2y for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:27 -0500 Received: by mail-wm1-x336.google.com with SMTP id x4so9060860wmi.3 for ; Mon, 15 Feb 2021 03:52:25 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DWcDLedvIdrpO/Dyf18yelSJMFxD3oqKzuBHwfEwOy0=; b=lxKioMnIiYfAs3AIWfKk9BlDEfzhv6Hqmg8rBE0k06s8Ijyj7/qjl/TSmWMR0+zD9e 2VI8w1YoxpnjwGu0dANvqK0zPDB6k4Jt0QdxUhVGEA0eA3UBJhKmboH7rVUFj1sn+uRb 3cza+JFR0/wKYi6EE2P6JXyvBlQxio1yDFht0TNjx/erdcAWEcBIDR6I63TLgCGW3Px+ jMyFtxB2asENtZHagCgmIo6r1qGlrW8kBIG/z4i9uYERw5hdPggM1wOruEwD+cNPIVj+ lFHnWMY33hTTsu3Vsd1664HdYQwet6gNsNtDoDh4ZTmc6ucIl02BLLItRtzzWCU9qA7C njtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DWcDLedvIdrpO/Dyf18yelSJMFxD3oqKzuBHwfEwOy0=; b=K5JifrQybJwfP03MWOUZNeYiYRRPS77Qo/Pr9RwJSb50vg0mIL9kYrOqkEqDqLq1jA w/NqONqMw3+mzMIg605wcvQF99vah6P/Dftt5DkGo7UwW9frOKDh+IsxljDm89QQ+ta9 UuIgFSRovRHhYqIXPtZ8fN7VOIjrTWOBdLxtUhfpk7RAibPP44YIlO8aw4EkGBT+hB9X JNaYQToI0b6m1mFknCk0Z+CD4zRJLqkL8KnnKO5hartbTxMpqNwIc3dxoyf3uP320T9Z W3E6FoiLTRhpTnHuKNqalff/ehxSdMFS96fp9N4fCZuUchyktRGnAyoTihqVFycK9mwH P1EQ== X-Gm-Message-State: AOAM531HpP7/4iROGbsZe5QIPDTEKOuzaSkjp1hi96JrDAzBDzyATq1G xJ0T8FMs26xQSBP/yzJXanLb4Q== X-Google-Smtp-Source: ABdhPJyiDdbCymhAeV2zgR2FRi/Hz8l2h20tGM386wb8J0jSX9XZqbyN5HDTMlNqJevoH3pp6OO2bg== X-Received: by 2002:a1c:2403:: with SMTP id k3mr14258325wmk.130.1613389944836; Mon, 15 Feb 2021 03:52:24 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 10/24] hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524 Date: Mon, 15 Feb 2021 11:51:24 +0000 Message-Id: <20210215115138.20465-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The AN524 version of the SCC interface has different behaviour for some of the CFG registers; implement it. Each board in this family can have minor differences in the meaning of the CFG registers, so rather than trying to specify all the possible semantics via individual device properties, we make the behaviour conditional on the part-number field of the SCC_ID register which the board code already passes us. For the AN524, the differences are: * CFG3 is reserved rather than being board switches * CFG5 is a new register ("ACLK Frequency in Hz") * CFG6 is a new register ("Clock divider for BRAM") We implement both of the new registers as reads-as-written. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/mps2-scc.h | 3 ++ hw/misc/mps2-scc.c | 71 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 72 insertions(+), 2 deletions(-) diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h index 514da49f69e..49d070616aa 100644 --- a/include/hw/misc/mps2-scc.h +++ b/include/hw/misc/mps2-scc.h @@ -29,7 +29,10 @@ struct MPS2SCC { =20 uint32_t cfg0; uint32_t cfg1; + uint32_t cfg2; uint32_t cfg4; + uint32_t cfg5; + uint32_t cfg6; uint32_t cfgdata_rtn; uint32_t cfgdata_out; uint32_t cfgctrl; diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index 52a4e183b71..562ace06a58 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -31,8 +31,11 @@ =20 REG32(CFG0, 0) REG32(CFG1, 4) +REG32(CFG2, 8) REG32(CFG3, 0xc) REG32(CFG4, 0x10) +REG32(CFG5, 0x14) +REG32(CFG6, 0x18) REG32(CFGDATA_RTN, 0xa0) REG32(CFGDATA_OUT, 0xa4) REG32(CFGCTRL, 0xa8) @@ -49,6 +52,12 @@ REG32(DLL, 0x100) REG32(AID, 0xFF8) REG32(ID, 0xFFC) =20 +static int scc_partno(MPS2SCC *s) +{ + /* Return the partno field of the SCC_ID (0x524, 0x511, etc) */ + return extract32(s->id, 4, 8); +} + /* Handle a write via the SYS_CFG channel to the specified function/device. * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit). */ @@ -100,7 +109,18 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr off= set, unsigned size) case A_CFG1: r =3D s->cfg1; break; + case A_CFG2: + if (scc_partno(s) !=3D 0x524) { + /* CFG2 reserved on other boards */ + goto bad_offset; + } + r =3D s->cfg2; + break; case A_CFG3: + if (scc_partno(s) =3D=3D 0x524) { + /* CFG3 reserved on AN524 */ + goto bad_offset; + } /* These are user-settable DIP switches on the board. We don't * model that, so just return zeroes. */ @@ -109,6 +129,20 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr off= set, unsigned size) case A_CFG4: r =3D s->cfg4; break; + case A_CFG5: + if (scc_partno(s) !=3D 0x524) { + /* CFG5 reserved on other boards */ + goto bad_offset; + } + r =3D s->cfg5; + break; + case A_CFG6: + if (scc_partno(s) !=3D 0x524) { + /* CFG6 reserved on other boards */ + goto bad_offset; + } + r =3D s->cfg6; + break; case A_CFGDATA_RTN: r =3D s->cfgdata_rtn; break; @@ -131,6 +165,7 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offs= et, unsigned size) r =3D s->id; break; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "MPS2 SCC read: bad offset %x\n", (int) offset); r =3D 0; @@ -159,6 +194,30 @@ static void mps2_scc_write(void *opaque, hwaddr offset= , uint64_t value, led_set_state(s->led[i], extract32(value, i, 1)); } break; + case A_CFG2: + if (scc_partno(s) !=3D 0x524) { + /* CFG2 reserved on other boards */ + goto bad_offset; + } + /* AN524: QSPI Select signal */ + s->cfg2 =3D value; + break; + case A_CFG5: + if (scc_partno(s) !=3D 0x524) { + /* CFG5 reserved on other boards */ + goto bad_offset; + } + /* AN524: ACLK frequency in Hz */ + s->cfg5 =3D value; + break; + case A_CFG6: + if (scc_partno(s) !=3D 0x524) { + /* CFG6 reserved on other boards */ + goto bad_offset; + } + /* AN524: Clock divider for BRAM */ + s->cfg6 =3D value; + break; case A_CFGDATA_OUT: s->cfgdata_out =3D value; break; @@ -202,6 +261,7 @@ static void mps2_scc_write(void *opaque, hwaddr offset,= uint64_t value, s->dll =3D deposit32(s->dll, 24, 8, extract32(value, 24, 8)); break; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "MPS2 SCC write: bad offset 0x%x\n", (int) offset); break; @@ -222,6 +282,9 @@ static void mps2_scc_reset(DeviceState *dev) trace_mps2_scc_reset(); s->cfg0 =3D 0; s->cfg1 =3D 0; + s->cfg2 =3D 0; + s->cfg5 =3D 0; + s->cfg6 =3D 0; s->cfgdata_rtn =3D 0; s->cfgdata_out =3D 0; s->cfgctrl =3D 0x100000; @@ -260,11 +323,15 @@ static void mps2_scc_realize(DeviceState *dev, Error = **errp) =20 static const VMStateDescription mps2_scc_vmstate =3D { .name =3D "mps2-scc", - .version_id =3D 2, - .minimum_version_id =3D 2, + .version_id =3D 3, + .minimum_version_id =3D 3, .fields =3D (VMStateField[]) { VMSTATE_UINT32(cfg0, MPS2SCC), VMSTATE_UINT32(cfg1, MPS2SCC), + VMSTATE_UINT32(cfg2, MPS2SCC), + /* cfg3, cfg4 are read-only so need not be migrated */ + VMSTATE_UINT32(cfg5, MPS2SCC), + VMSTATE_UINT32(cfg6, MPS2SCC), VMSTATE_UINT32(cfgdata_rtn, MPS2SCC), VMSTATE_UINT32(cfgdata_out, MPS2SCC), VMSTATE_UINT32(cfgctrl, MPS2SCC), --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ok51mWFe/EHn9mJ70RUpKX9SuyFsEZZOYsJcbxrhCtM=; b=MWrc0AdmkdABWEbP2TLy1p4KVEBQRu5S9EoM5KOj7yuStRi8WBRv1lHgVE6nZYdGDW 0KoycWMpLjOBd2lF0aVPyOau+OlVaeKi+U7RlcRbDGFrFRQgvUCD8zHYhx9xxFsLpLwc TIRXQsLc0R5CNfOAEbJbjJsIJwlU/litP9jK26CNJyumaVviN6SkxFmV/9bDmaRSq5Tp aoI6Y1p5Smum6V3tw30EU2O7Z2+ZiIRHJ3u+WuUB/n99JVMWrckYJsl3cVSxQbGbLdm2 6ZgyyULFAFst2U+kG/QQ6MkPG9N1gPWyOH9eUA/LjduSpzjjKzVN6Cdcv/K20wKqnbDn +Urg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ok51mWFe/EHn9mJ70RUpKX9SuyFsEZZOYsJcbxrhCtM=; b=FpAomon8pwjASRrWAY+1goKajSop7EK/v1ID5aKEHKct9kiL2SSsj48caTAx8ghZy8 b4b9nJp8jrQLtRJ+ox5vxjfBKDMK+V04/QywDL3tY+WVN/9WaEAYxE6YK8dLeuOHQ+GD ujt0pU9ehaXdIoc8w81OqpbGMKixbW9Ox798U/J+us50tlj5QjgzEJYBrOKyvzhCzD5I RHAWuDASRicdIDoSdawm8Ku+9VeQ5nOSEVO9LtfGE/RUswvWEHVuX2W3oMK+0bt3bK2L ME+DWpnRuds6lXbOibc05/bny50Kmo7/CVqoHRsXOpgBN7uMWPC5iAz8SlppdQg4hJUt HUqA== X-Gm-Message-State: AOAM530OWllDFbmL0+drHaFkcGasThHertJcojE4+SdojfD93yj84omD i0dSPAVx0DO+PTnpvTdnyPO3mQ== X-Google-Smtp-Source: ABdhPJyy0u6L1qTrOY2Uu/VHz/avD5zg6jKgMFuI26LQs9SYJxwrfidrXKhxz/ZFz2RwkCm8yvqlYw== X-Received: by 2002:a05:6000:1cc:: with SMTP id t12mr17719201wrx.142.1613389947866; Mon, 15 Feb 2021 03:52:27 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 11/24] hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI Date: Mon, 15 Feb 2021 11:51:25 +0000 Message-Id: <20210215115138.20465-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" On the MPS2 boards, the first 32 interrupt lines are entirely internal to the SSE; interrupt lines for devices outside the SSE start at 32. In the application notes that document each FPGA image, the interrupt wiring is documented from the point of view of the CPU, so '0' is the first of the SSE's interrupts and the devices in the FPGA image itself are '32' and up: so the UART 0 Receive interrupt is 32, the SPI #0 interrupt is 51, and so on. Within our implementation, because the external interrupts must be connected to the EXP_IRQ[0...n] lines of the SSE object, we made the get_sse_irq_in() function take an irqno whose values start at 0 for the first FPGA device interrupt. In this numbering scheme the UART 0 Receive interrupt is 0, the SPI #0 interrupt is 19, and so on. The result of these two different numbering schemes has been that half of the devices were wired up to the wrong IRQs: the UART IRQs are wired up correctly, but the DMA and SPI devices were passing start-at-32 values to get_sse_irq_in() and so being mis-connected. Fix the bug by making get_sse_irq_in() take values specified with the same scheme that the hardware manuals use, to avoid confusion. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 6362652e617..ff8b7e5f1ae 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -139,11 +139,21 @@ static void make_ram_alias(MemoryRegion *mr, const ch= ar *name, =20 static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) { - /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ + /* + * Return a qemu_irq which will signal IRQ n to all CPUs in the + * SSE. The irqno should be as the CPU sees it, so the first + * external-to-the-SSE interrupt is 32. + */ MachineClass *mc =3D MACHINE_GET_CLASS(mms); MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); =20 - assert(irqno < mmc->numirq); + assert(irqno >=3D 32 && irqno < (mmc->numirq + 32)); + + /* + * Convert from "CPU irq number" (as listed in the FPGA image + * documentation) to the SSE external-interrupt number. + */ + irqno -=3D 32; =20 if (mc->max_cpus > 1) { return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); @@ -197,9 +207,9 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms,= void *opaque, MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart =3D opaque; int i =3D uart - &mms->uart[0]; - int rxirqno =3D i * 2; - int txirqno =3D i * 2 + 1; - int combirqno =3D i + 10; + int rxirqno =3D i * 2 + 32; + int txirqno =3D i * 2 + 33; + int combirqno =3D i + 42; SysBusDevice *s; DeviceState *orgate_dev =3D DEVICE(&mms->uart_irq_orgate); =20 @@ -266,7 +276,7 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *m= ms, void *opaque, =20 s =3D SYS_BUS_DEVICE(mms->lan9118); sysbus_realize_and_unref(s, &error_fatal); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 48)); return sysbus_mmio_get_region(s, 0); } =20 @@ -507,7 +517,7 @@ static void mps2tz_common_init(MachineState *machine) &error_fatal); qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, - get_sse_irq_in(mms, 15)); + get_sse_irq_in(mms, 47)); =20 /* Most of the devices in the FPGA are behind Peripheral Protection * Controllers. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2BF8LO9cNQ4akwkDY93h/rSr1/g9V8BvTXqt3kC/A3Q=; b=A+JVudyhTK6Zk7cIJI7szYY653TWUCzrSa0Sr/LTbr9pC13but9HWrkliEAK27FQ0P 4fozVogQp4inrXmtswQ/1mk7IV2YLLwFBvxXuuMj4XQ9yv7JCSlEuQ0/AHE8Yu6xfEuP 4AYaJeXydD/WM/JF+INQjnfxIc1tiZoCjXdNG7PnW6u6SKgOZJsGUwRsoVruYxFRUKeX P1NP3PJ98sKxI1mNU/8bOBVkdmj6D7wXwmky9P3EMzsW0pFzW1lgn83rfcy5XI3EVPIe W1S0A/01iVj06U61bWY8bobtzTTAcOV2lXxRRymX17MKpL0YNOAKcm4Go1aPsnLijrRP +YgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2BF8LO9cNQ4akwkDY93h/rSr1/g9V8BvTXqt3kC/A3Q=; b=FNU/7C2vbkMK7ZGluHp2a75CCHtY4rrbHQ8LnZsNUHqiSPtHTbAOsC/JrmUBWcDDC8 MlY2ieXrx8xrhlrSIiBjaywaHXDJ5fze/9rleQaGp+TYN68aAyz/OKR3E8Tv1niOE9mm Ov02MpfyPwpRt5CaspJfJUafw27B2sxUx8HWIK3tP48rH/vfz7EoVddDw3HmLkd4nuNT H8xQtYX3bX+wRKJwLIjTaCyFu1BoeL/OoNf31PsSfSjj/8HmZHL384rQWlvf/AJo2rPJ VnCPq64GP8wut7yipc5aoMiwmcQ+sZG8ZB0XMuGIjbSZPrAKObaovRBdBcslSUZuHHQT 4R8g== X-Gm-Message-State: AOAM5331VS1kspNbaThkQ0YyPDV22buDmlASvgx+2EKB+T0LY55Z2wKv ADePY9JejWW1zjhzrwFT2tlebw== X-Google-Smtp-Source: ABdhPJwLzwql+GLzHQjin2n92ekN3sYL9gjL6SDKUKq5EuM4CU1uD6GRtL9uH6Ze34ldp7mKh34WSg== X-Received: by 2002:a05:6000:18ac:: with SMTP id b12mr18641743wri.77.1613389950852; Mon, 15 Feb 2021 03:52:30 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 12/24] hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts Date: Mon, 15 Feb 2021 11:51:26 +0000 Message-Id: <20210215115138.20465-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The mps2-tz code uses PPCPortInfo data structures to define what devices are present and how they are wired up. Currently we use these to specify device types and addresses, but hard-code the interrupt line wiring in each make_* helper function. This works for the two boards we have at the moment, but the AN524 has some devices with different interrupt assignments. This commit adds the framework to allow PPCPortInfo structures to specify interrupt numbers. We add an array of interrupt numbers to the PPCPortInfo struct, and pass it through to the make_* helpers. The following commit will change the make_* helpers over to using the framework. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 36 ++++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index ff8b7e5f1ae..085746ac3e6 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -170,7 +170,8 @@ static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms,= int irqno) * needs to be plugged into the downstream end of the PPC port. */ typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size); + const char *name, hwaddr size, + const int *irqs); =20 typedef struct PPCPortInfo { const char *name; @@ -178,6 +179,7 @@ typedef struct PPCPortInfo { void *opaque; hwaddr addr; hwaddr size; + int irqs[3]; /* currently no device needs more IRQ lines than this */ } PPCPortInfo; =20 typedef struct PPCInfo { @@ -186,8 +188,9 @@ typedef struct PPCInfo { } PPCInfo; =20 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, - void *opaque, - const char *name, hwaddr size) + void *opaque, + const char *name, hwaddr size, + const int *irqs) { /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, * and return a pointer to its MemoryRegion. @@ -202,7 +205,8 @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState = *mms, } =20 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart =3D opaque; @@ -227,7 +231,8 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms,= void *opaque, } =20 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { MPS2SCC *scc =3D opaque; DeviceState *sccdev; @@ -249,7 +254,8 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, = void *opaque, } =20 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { MPS2FPGAIO *fpgaio =3D opaque; MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); @@ -262,7 +268,8 @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mm= s, void *opaque, } =20 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { SysBusDevice *s; NICInfo *nd =3D &nd_table[0]; @@ -281,7 +288,8 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *m= ms, void *opaque, } =20 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { TZMPC *mpc =3D opaque; int i =3D mpc - &mms->ssram_mpc[0]; @@ -318,7 +326,8 @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, = void *opaque, } =20 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { PL080State *dma =3D opaque; int i =3D dma - &mms->dma[0]; @@ -373,7 +382,8 @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, = void *opaque, } =20 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { /* * The AN505 has five PL022 SPI controllers. @@ -395,7 +405,8 @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms, = void *opaque, } =20 static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { ArmSbconI2CState *i2c =3D opaque; SysBusDevice *s; @@ -604,7 +615,8 @@ static void mps2tz_common_init(MachineState *machine) continue; } =20 - mr =3D pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->si= ze); + mr =3D pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->si= ze, + pinfo->irqs); portname =3D g_strdup_printf("port[%d]", port); object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), &error_fatal); --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613390813; cv=none; d=zohomail.com; s=zohoarc; b=jwJW0vdAbUd/NXd85oQLSg0ejPFkxc3Hle+/i6KCCwtxzQJH13Lr51WTQmRPFEC7Onf9UjzG9RJNIZBBGAGnY6AlpaWoPQaBqPvcXv5zL6XRC84OvbgAKNdv8TVxotdk+xzkcWkxPG7zTXfxrrUBRR0IY/pkk5tB81p1pExVDSM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613390813; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+NbEIvKPXeseDuihlw5UuA+TE/Yh6pzRecBSPQLOGzA=; b=JcB953aXQ+kOZN6UN3HgPCvje9PxaJ4R82K4joukXBdiWrh7rvgf8d/fxkjLtTpsAU tzR2cBoV8fNtl+OM7px6ziJtYMNaKmVgCtNLa1phNiyeCsdZ3H8m9/oFTg4x+INhpQm5 UYfwDYiu6l8+pDXX/k2q/nZakEBKGNZGAEyq/4lQR8A5CcHly1teNc1gVElDTyfcvcrH cKO3K2+ge6QIrK72pxNVcqk5/A2bq+qGw1gIGYRxMrDtv9j0C8BHpqWgmzaIhZ5ieGpz sz5gLTLS9GuEZNGQ1HigVhoU442a38VIBQuDD63jMnp/A7IlQ7DYmbsB/vrZboyieO1Q I1cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+NbEIvKPXeseDuihlw5UuA+TE/Yh6pzRecBSPQLOGzA=; b=IufS4sf231Az7XWVRonLpsTdrpMoprBaQmSiHjMdlNngjuBZsoM4v302HNCFl/v9eY 4m+UDxAoEIIYKfJWK8Yzv3bvd6dbsNTM6x1InvXeG80BU4+Pu4+nj+wpZxaZyrrZgbrh SP8rxqAG1bedmq1sMad66ncHKxNXnyY7qsgpvAfyjEWgwkTNC32IKfbSwg0p5r01bZ6T juEBknOeO6BAQIp9tPTT0vwWDRcbCNBhec/EjLBC560IHq1UfGSHeFP6l7R5DiBBSiJN nUTPmYNvPlLDwGN3ugNumFZprfvCbs9Hwzg313Sa4GQj9ebvtKoKfEkHyUr+C8jP3NQ5 ZVog== X-Gm-Message-State: AOAM533RGh9kS0+3aVi0U1ZJAwB3s98ESDLyXKe6UVpniq1N35StRMl+ ZdSgXGLD63FXKLAYUmTekqNoGjJ1inXWJA== X-Google-Smtp-Source: ABdhPJxLS6lxoNJeqinL75T6aEWtu99h4Q9rgz/VWJAzitSKEkMEcDEgMNgx8imfjotfMKBRIOPYCQ== X-Received: by 2002:adf:b749:: with SMTP id n9mr18299390wre.267.1613389954486; Mon, 15 Feb 2021 03:52:34 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 13/24] hw/arm/mps2-tz: Move device IRQ info to data structures Date: Mon, 15 Feb 2021 11:51:27 +0000 Message-Id: <20210215115138.20465-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Move the specification of the IRQ information for the uart, ethernet, dma and spi devices to the data structures. (The other devices handled by the PPCPortInfo structures don't have any interrupt lines we need to wire up.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 52 +++++++++++++++++++++++------------------------- 1 file changed, 25 insertions(+), 27 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 085746ac3e6..014ba775783 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -208,12 +208,10 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mm= s, void *opaque, const char *name, hwaddr size, const int *irqs) { + /* The irq[] array is tx, rx, combined, in that order */ MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart =3D opaque; int i =3D uart - &mms->uart[0]; - int rxirqno =3D i * 2 + 32; - int txirqno =3D i * 2 + 33; - int combirqno =3D i + 42; SysBusDevice *s; DeviceState *orgate_dev =3D DEVICE(&mms->uart_irq_orgate); =20 @@ -222,11 +220,11 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mm= s, void *opaque, qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->sysclk_frq); sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); s =3D SYS_BUS_DEVICE(uart); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); - sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); - sysbus_connect_irq(s, 4, get_sse_irq_in(mms, combirqno)); + sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2])); return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); } =20 @@ -283,7 +281,7 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *m= ms, void *opaque, =20 s =3D SYS_BUS_DEVICE(mms->lan9118); sysbus_realize_and_unref(s, &error_fatal); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 48)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); return sysbus_mmio_get_region(s, 0); } =20 @@ -329,6 +327,7 @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, = void *opaque, const char *name, hwaddr size, const int *irqs) { + /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */ PL080State *dma =3D opaque; int i =3D dma - &mms->dma[0]; SysBusDevice *s; @@ -373,9 +372,9 @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, = void *opaque, =20 s =3D SYS_BUS_DEVICE(dma); /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 58 + i * 3)); - sysbus_connect_irq(s, 1, get_sse_irq_in(mms, 56 + i * 3)); - sysbus_connect_irq(s, 2, get_sse_irq_in(mms, 57 + i * 3)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); + sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqs[2])); =20 g_free(mscname); return sysbus_mmio_get_region(s, 0); @@ -394,13 +393,12 @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms= , void *opaque, * lines are set via the "MISC" register in the MPS2 FPGAIO device. */ PL022State *spi =3D opaque; - int i =3D spi - &mms->spi[0]; SysBusDevice *s; =20 object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022); sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal); s =3D SYS_BUS_DEVICE(spi); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); return sysbus_mmio_get_region(s, 0); } =20 @@ -551,16 +549,16 @@ static void mps2tz_common_init(MachineState *machine) }, { .name =3D "apb_ppcexp1", .ports =3D { - { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000 }, - { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000 }, - { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000 }, - { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000 }, - { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000 }, - { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, - { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, - { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, - { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, - { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, + { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000, { 51= } }, + { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000, { 52= } }, + { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000, { 53= } }, + { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000, { 54= } }, + { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000, { 55= } }, + { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000, {= 32, 33, 42 } }, + { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000, {= 34, 35, 43 } }, + { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, {= 36, 37, 44 } }, + { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, {= 38, 39, 45 } }, + { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, {= 40, 41, 46 } }, { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 }, { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 }, { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 }, @@ -582,15 +580,15 @@ static void mps2tz_common_init(MachineState *machine) { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x10= 00 }, { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x10= 00 }, { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x10= 00 }, - { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 }, + { "eth", make_eth_dev, NULL, 0x42000000, 0x100000, { 48 } = }, }, }, { .name =3D "ahb_ppcexp1", .ports =3D { - { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000 }, - { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000 }, - { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000 }, - { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000 }, + { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000, { 58= , 56, 57 } }, + { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000, { 61= , 59, 60 } }, + { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000, { 64= , 62, 63 } }, + { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000, { 67= , 65, 66 } }, }, }, }; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tA+5uc5Diq05XqZ8Xpisz6igJKvX27QKXQ3Zpt1aydo=; b=zkVbAipdtWQpfRIaeIRnDAQirG99XLbu53KEPIqb8+Yv+iZELfMPizTiopv1mtFR/c semmmsEhWi8YNs8m7/6luUNl0vrKRNsXqKjlaPE2Tkiw1GCGFEeGk18/vLKEPkhsRiDv 3ulgYKAYfeuqs/a/DPl6HVvunykNcPD2PLVn5GCZRrdy/+wFmnkkTykBy+IYSvf++3Hb vk4Mqf4joii03R2lmg8cFm/QVWoquAAHvYNM84iACib77Obb3RzuB3IjwGiVgSrWQJWS Xey7KYUvHsksyu6WiWy1gdLM4lG3iEnhthvh3mT9cKG5UyuqLWBXxK9sbWoukOIgmlqc fYKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tA+5uc5Diq05XqZ8Xpisz6igJKvX27QKXQ3Zpt1aydo=; b=MaeXGBEvKDnOW1ESmZgloo8eI1mZUbK5KDdWvN8og/mA9v/lDtnGuMIbo01OiMlTOj MqenOxGWvEyzjf/Cg2Qs+lkRj6g323XKed+zxNiIOiQF9cQSu+Y2U9XN26Yvo8bQuTsW QNmjGAFrdPk0YHH+hZheTlFKaahvlENrnw4OC0Nz+uwQJht5xYYRIhNjCb53hMNSteh/ 5KohlLDng9s29c7Jg0WI9M3c8m+h7TjN9XzVpZDPUCRwWNOglvxQ9TBdDHKbkHEcEGim QJJD3y/MsiAW6P6DmYhiia+YiV3LYIUgH2Qfk9siDl2+ajB57hASb7aF8Wx38kJUM6my fU0g== X-Gm-Message-State: AOAM530Yccyd+tud3GbjhNy2y0NoQdE8n7G6mShhnnK79Hm4JMnnOZM9 4tMH5RmzHGda7zMSpbv3bfRHSg== X-Google-Smtp-Source: ABdhPJwe7rC7R9KL+Cda+d72yinzHMSXVm+6MkCXpRh1EVByFXdzYVqkD5N/X7ePkssOr4kWOKX7uQ== X-Received: by 2002:a1c:9d81:: with SMTP id g123mr14288028wme.139.1613389958114; Mon, 15 Feb 2021 03:52:38 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 14/24] hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs Date: Mon, 15 Feb 2021 11:51:28 +0000 Message-Id: <20210215115138.20465-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We create an OR gate to wire together the overflow IRQs for all the UARTs on the board; this has to have twice the number of inputs as there are UARTs, since each UART feeds it a TX overflow and an RX overflow interrupt line. Replace the hardcoded '10' with a calculation based on the size of the uart[] array in the MPS2TZMachineState. (We rely on OR gate inputs that are never wired up or asserted being treated as always-zero.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 014ba775783..f1a9c5f65a5 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -516,13 +516,18 @@ static void mps2tz_common_init(MachineState *machine) */ memory_region_add_subregion(system_memory, 0x80000000, machine->ram); =20 - /* The overflow IRQs for all UARTs are ORed together. + /* + * The overflow IRQs for all UARTs are ORed together. * Tx, Rx and "combined" IRQs are sent to the NVIC separately. - * Create the OR gate for this. + * Create the OR gate for this: it has one input for the TX overflow + * and one for the RX overflow for each UART we might have. + * (If the board has fewer than the maximum possible number of UARTs + * those inputs are never wired up and are treated as always-zero.) */ object_initialize_child(OBJECT(mms), "uart-irq-orgate", &mms->uart_irq_orgate, TYPE_OR_IRQ); - object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", 10, + object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", + 2 * ARRAY_SIZE(mms->uart), &error_fatal); qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613390865; cv=none; d=zohomail.com; s=zohoarc; b=O7b4BU+0vXjuVt4wqdTlkcqoCxQqEJTIqnqEvqS4Tafr+R5BIRRtZYLs5wwA0SVLQ3Pi4DWckizjST46MJZq7DEiS5crd1m4dL7wCtTfbdwFGJsVWThbAnnEyQbmMUbFf5oxgAn/AtaglbMRqaV8M6+QsyelOR7ZOMKKmLFQEAQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613390865; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Mn7Me6K3TMP27APgbQca833jRzvfQ06ASXws5mXDtM8=; b=eTDDLx08freCFj8yAV0QmZr1Zivxf4mw/4LlcFnlIsw+ZjfZq11wsnA8dWtep5HaoXxRQItRgsOnih3oamRzfOtCwO7iSXqm23cGNfm9UHTL3snQWy8/fMp0N3CmrAxNEHeHPDxc2/ni8pkNQR6waG31e6NHzT1uqJ6Y3iBL5KQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613390865871907.6043598610888; Mon, 15 Feb 2021 04:07:45 -0800 (PST) Received: from localhost ([::1]:48752 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBcfI-0000sx-01 for importer@patchew.org; Mon, 15 Feb 2021 07:07:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39520) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBcQm-0008HJ-DQ for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:44 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:38151) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBcQk-00047s-TU for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:44 -0500 Received: by mail-wm1-x330.google.com with SMTP id x4so9061647wmi.3 for ; Mon, 15 Feb 2021 03:52:42 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Mn7Me6K3TMP27APgbQca833jRzvfQ06ASXws5mXDtM8=; b=WyVCAR8ecScqsmMGiwfNYiOumxkC4CgzOB8y+dwap4B/2EYXyvkO2Q0crANWuMuWHl S7AyxohBdLMq6uKROhWeFqRSjn0+U2nR5jLNfLEW8PFdDgQQksdUWQj428TZixroiThM jFZRQYMtn0IYVLFw99pVLB+TJnupkWk1tdeSlbwc9zLEMlRfTb3T7F2hjB9PT7syBSbE 0s25InGYqyXSVVftaIa27P53HcZ9w49hb0tnVigazAwpjPdUT4nv9QCz1W4IYDgWyLWf kOK2RqkncMf/ccMS7Jv84HZP2Pc8A0y8y4Z8bmGp9aanNdcpyPkH3f+Bc0tIbeURu6Hb rdXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Mn7Me6K3TMP27APgbQca833jRzvfQ06ASXws5mXDtM8=; b=gM8bS6asQmi9UOO3vebnTKWqSwhidXo314YR3ovHJ9A+z9Zd1h6H/ADcucXouBofFW Fo9s8H0x77QQGfSUzZ5FZC1NrkM6X0sfFnsjUdfafaixdH/c51nL1Q85Z3+jneKOMelu BfJahU4yr3FUP7v7Zfm/vz9xxijDH5IIo+djtMyRgP07NHrG/iy4YSNPp87FsqBtI9qj GJxIk6EDhK6XqVyoOMRlThfaM2JNQRnvur7rag8np1Pj710ywSTvEcxe0EhGfLyor8kx y7YGGH6/rLU574TGoBRbk5Lo+yhwYwjS0qZ9TcKxxwO9jErC2TDSu6F0UmVjOriA7byv FKmw== X-Gm-Message-State: AOAM531d4CC/X/tRpQzQXoQgMKa5Ck9eBiyZ+DzijmIpIx21O3QQ2Xmi z3wEUfxuMNenHV0lPlyqJ26TUQ== X-Google-Smtp-Source: ABdhPJz9+BXOne7oQGV/Dfdu5woogGLeqWuWV8q431IINfGVJ8gCdVAankiqS+BmeYALfbPh1mcebw== X-Received: by 2002:a1c:107:: with SMTP id 7mr13885028wmb.28.1613389961694; Mon, 15 Feb 2021 03:52:41 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 15/24] hw/arm/mps2-tz: Allow boards to have different PPCInfo data Date: Mon, 15 Feb 2021 11:51:29 +0000 Message-Id: <20210215115138.20465-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The AN505 and AN521 have the same device layout, but the AN524 is somewhat different. Allow for more than one PPCInfo array, which can be selected based on the board type. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- We can't just put the arrays at file-scope and set up pointers to them in the MPS2TZMachineClass struct, because the array members include entries like "&mms->uart[0]" which is only valid inside the mps2tz_common_init() function. --- hw/arm/mps2-tz.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index f1a9c5f65a5..a79966a7187 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -423,6 +423,8 @@ static void mps2tz_common_init(MachineState *machine) MemoryRegion *system_memory =3D get_system_memory(); DeviceState *iotkitdev; DeviceState *dev_splitter; + const PPCInfo *ppcs; + int num_ppcs; int i; =20 if (strcmp(machine->cpu_type, mc->default_cpu_type) !=3D 0) { @@ -544,7 +546,7 @@ static void mps2tz_common_init(MachineState *machine) * + wire up the PPC's control lines to the IoTKit object */ =20 - const PPCInfo ppcs[] =3D { { + const PPCInfo an505_ppcs[] =3D { { .name =3D "apb_ppcexp0", .ports =3D { { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1= 000 }, @@ -598,7 +600,17 @@ static void mps2tz_common_init(MachineState *machine) }, }; =20 - for (i =3D 0; i < ARRAY_SIZE(ppcs); i++) { + switch (mmc->fpga_type) { + case FPGA_AN505: + case FPGA_AN521: + ppcs =3D an505_ppcs; + num_ppcs =3D ARRAY_SIZE(an505_ppcs); + break; + default: + g_assert_not_reached(); + } + + for (i =3D 0; i < num_ppcs; i++) { const PPCInfo *ppcinfo =3D &ppcs[i]; TZPPC *ppc =3D &mms->ppc[i]; DeviceState *ppcdev; --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613391021; cv=none; d=zohomail.com; s=zohoarc; b=hFulVkUu2QeBxXp2u7zUSLvfnKbkjnR8tcAmJhbWAfjVTtJG/Unp4EpKh0W9PtnkBNGibYLeM4mOFcXo5bFMrgUo5ohpJKFWwEZsN5hSdaaPFbbgg2qQhAnjlrTtTAdEaJXBw1c0c77kF/eayTgNrtvdLBjgV8q6OpePoGeCU2g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613391021; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=g39A1Te0/340pWg5jN+HevWlGijlA8x8/t1AqKmXmB0=; b=gStL4NKSbDY70MHgKeVrM47MyoXAgdZZMCoOJETlz1+v6cVLDJqEZeYNsw/LKzv/KADdtef5mJdC4ysU/aBZ+btdHY+4LBgXRzw7fEL74BeWjOQiqiCmG7bddJi7JFDROZ7CB6TCrT0qBXysFvxpZ8sijqTk+BsVBzlmlAoIWGo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613391021533587.3590738557243; Mon, 15 Feb 2021 04:10:21 -0800 (PST) Received: from localhost ([::1]:57330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBcho-0004WT-M0 for importer@patchew.org; Mon, 15 Feb 2021 07:10:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39594) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBcQs-0008WI-7u for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:50 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:39682) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBcQp-00049g-KN for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:49 -0500 Received: by mail-wm1-x32b.google.com with SMTP id z63so3758635wmg.4 for ; Mon, 15 Feb 2021 03:52:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g39A1Te0/340pWg5jN+HevWlGijlA8x8/t1AqKmXmB0=; b=ktgnsehSPTTtEhfFHYSWJyoCJc1eJ0BDpY224afk5SsBZRgREwHoR0gufWcil4e7BL BSeio5zx/HbLEoPFTqRi4P/XwV59Ylrt4V6/L0+pPKO/CT491prLJJx4kxK/Iy32AfAh XmZbndtoyrJlNN9bnLBD1xiS4mnZOeCaSypAKSGy/7f9DSTk9sJJewgUs3cFolNCwfpW T385FTqTif8OYO19u2OjlziaNHG5WiOy+CGNX3Zq9NmPCPJye9m/IV4bYLoZsnsx/aNl iwjtHvl0TEUvi8Fe4q0cUpPWSbJ/nRludP0cA5dVqjHKUEm6sVtPn3B3hgp0xKb7i4/0 NAWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g39A1Te0/340pWg5jN+HevWlGijlA8x8/t1AqKmXmB0=; b=ATK/+8XhoAoIwK06plVZksaoBcWBdONs0vkJJUnxvOmWY782jKFU0KDuIRKN8kbJNp /e4ekFFQidY18fRfb+bE070D6m3GWWyfaYriE+sARgNX1PYa2RICL8DTOIevt0jrl5LR N1y/Wj1ejZZJdRLrBLII1XL6SrR7E4gT7xTHTlE1/SXaM+HvKH8SI9/sMTdHB6dP0X4o Mz8wXm+aTB2j1ZbGu2FB7AWD1sRrMrUnM1rPdJYdc0J4bWGRcYD26K5wBMGbUEQD2VUX NvruOszEbC+9kZ8lfqJF0hMCrofRA48V92/BC0DEJEzoe+R4bHbz/kiuMHbuGKXpXzrh RkIA== X-Gm-Message-State: AOAM5334/zvueguvJIKmwXWnkalGB6Hbm0q970tWVRJBMux1C/GVbdx4 LN/EYjRQrGqdX0Fh1TBY8BXxsA== X-Google-Smtp-Source: ABdhPJxuvJtToATN6PwOXB75ShaRBM2u7aOU3cEf5QUqbT00Ff8GDyicrhbMrSd9FY8ziYamV7Q5Rw== X-Received: by 2002:a1c:4006:: with SMTP id n6mr14058946wma.177.1613389966278; Mon, 15 Feb 2021 03:52:46 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 16/24] hw/arm/mps2-tz: Make RAM arrangement board-specific Date: Mon, 15 Feb 2021 11:51:30 +0000 Message-Id: <20210215115138.20465-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The AN505 and AN521 have the same layout of RAM; the AN524 does not. Replace the current hard-coding of where the RAM is and which parts of it are behind which MPCs with a data-driven approach. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 175 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 138 insertions(+), 37 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index a79966a7187..18f75eacfcd 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -66,12 +66,35 @@ #include "qom/object.h" =20 #define MPS2TZ_NUMIRQ_MAX 92 +#define MPS2TZ_RAM_MAX 4 =20 typedef enum MPS2TZFPGAType { FPGA_AN505, FPGA_AN521, } MPS2TZFPGAType; =20 +/* + * Define the layout of RAM in a board, including which parts are + * behind which MPCs. + * mrindex specifies the index into mms->ram[] to use for the backing RAM; + * -1 means "use the system RAM". + */ +typedef struct RAMInfo { + const char *name; + uint32_t base; + uint32_t size; + int mpc; /* MPC number, -1 for "not behind an MPC" */ + int mrindex; + int flags; +} RAMInfo; + +/* + * Flag values: + * IS_ALIAS: this RAM area is an alias to the upstream end of the + * MPC specified by its .mpc value + */ +#define IS_ALIAS 1 + struct MPS2TZMachineClass { MachineClass parent; MPS2TZFPGAType fpga_type; @@ -82,6 +105,7 @@ struct MPS2TZMachineClass { uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ int numirq; /* Number of external interrupts */ + const RAMInfo *raminfo; const char *armsse_type; }; =20 @@ -89,12 +113,11 @@ struct MPS2TZMachineState { MachineState parent; =20 ARMSSE iotkit; - MemoryRegion ssram[3]; - MemoryRegion ssram1_m; + MemoryRegion ram[MPS2TZ_RAM_MAX]; MPS2SCC scc; MPS2FPGAIO fpgaio; TZPPC ppc[5]; - TZMPC ssram_mpc[3]; + TZMPC mpc[3]; PL022State spi[5]; ArmSbconI2CState i2c[4]; UnimplementedDeviceState i2s_audio; @@ -126,6 +149,77 @@ static const uint32_t an505_oscclk[] =3D { 25000000, }; =20 +static const RAMInfo an505_raminfo[] =3D { { + .name =3D "ssram-0", + .base =3D 0x00000000, + .size =3D 0x00400000, + .mpc =3D 0, + .mrindex =3D 0, + }, { + .name =3D "ssram-1", + .base =3D 0x28000000, + .size =3D 0x00200000, + .mpc =3D 1, + .mrindex =3D 1, + }, { + .name =3D "ssram-2", + .base =3D 0x28200000, + .size =3D 0x00200000, + .mpc =3D 2, + .mrindex =3D 2, + }, { + .name =3D "ssram-0-alias", + .base =3D 0x00400000, + .size =3D 0x00400000, + .mpc =3D 0, + .mrindex =3D 3, + .flags =3D IS_ALIAS, + }, { + /* Use the largest bit of contiguous RAM as our "system memory" */ + .name =3D "mps.ram", + .base =3D 0x80000000, + .size =3D 16 * MiB, + .mpc =3D -1, + .mrindex =3D -1, + }, { + .name =3D NULL, + }, +}; + +static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mp= c) +{ + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); + const RAMInfo *p; + + for (p =3D mmc->raminfo; p->name; p++) { + if (p->mpc =3D=3D mpc && !(p->flags & IS_ALIAS)) { + return p; + } + } + /* if raminfo array doesn't have an entry for each MPC this is a bug */ + g_assert_not_reached(); +} + +static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, + const RAMInfo *raminfo) +{ + /* Return an initialized MemoryRegion for the RAMInfo. */ + MemoryRegion *ram; + + if (raminfo->mrindex < 0) { + /* Means this RAMInfo is for QEMU's "system memory" */ + MachineState *machine =3D MACHINE(mms); + return machine->ram; + } + + assert(raminfo->mrindex < MPS2TZ_RAM_MAX); + ram =3D &mms->ram[raminfo->mrindex]; + + memory_region_init_ram(ram, NULL, raminfo->name, + raminfo->size, &error_fatal); + return ram; +} + /* Create an alias of an entire original MemoryRegion @orig * located at @base in the memory map. */ @@ -290,35 +384,23 @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms= , void *opaque, const int *irqs) { TZMPC *mpc =3D opaque; - int i =3D mpc - &mms->ssram_mpc[0]; - MemoryRegion *ssram =3D &mms->ssram[i]; + int i =3D mpc - &mms->mpc[0]; MemoryRegion *upstream; - char *mpcname =3D g_strdup_printf("%s-mpc", name); - static uint32_t ramsize[] =3D { 0x00400000, 0x00200000, 0x00200000 }; - static uint32_t rambase[] =3D { 0x00000000, 0x28000000, 0x28200000 }; + const RAMInfo *raminfo =3D find_raminfo_for_mpc(mms, i); + MemoryRegion *ram =3D mr_for_raminfo(mms, raminfo); =20 - memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal); - - object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC); - object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ssram), + object_initialize_child(OBJECT(mms), name, mpc, TYPE_TZ_MPC); + object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ram), &error_fatal); sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); /* Map the upstream end of the MPC into system memory */ upstream =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); - memory_region_add_subregion(get_system_memory(), rambase[i], upstream); + memory_region_add_subregion(get_system_memory(), raminfo->base, upstre= am); /* and connect its interrupt to the IoTKit */ qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, qdev_get_gpio_in_named(DEVICE(&mms->iotkit= ), "mpcexp_status", i)= ); =20 - /* The first SSRAM is a special case as it has an alias; accesses to - * the alias region at 0x00400000 must also go to the MPC upstream. - */ - if (i =3D=3D 0) { - make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x0040000= 0); - } - - g_free(mpcname); /* Return the register interface MR for our caller to map behind the P= PC */ return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); } @@ -415,6 +497,28 @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms,= void *opaque, return sysbus_mmio_get_region(s, 0); } =20 +static void create_non_mpc_ram(MPS2TZMachineState *mms) +{ + /* + * Handle the RAMs which are either not behind MPCs or which are + * aliases to another MPC. + */ + const RAMInfo *p; + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); + + for (p =3D mmc->raminfo; p->name; p++) { + if (p->flags & IS_ALIAS) { + SysBusDevice *mpc_sbd =3D SYS_BUS_DEVICE(&mms->mpc[p->mpc]); + MemoryRegion *upstream =3D sysbus_mmio_get_region(mpc_sbd, 1); + make_ram_alias(&mms->ram[p->mrindex], p->name, upstream, p->ba= se); + } else if (p->mpc =3D=3D -1) { + /* RAM not behind an MPC */ + MemoryRegion *mr =3D mr_for_raminfo(mms, p); + memory_region_add_subregion(get_system_memory(), p->base, mr); + } + } +} + static void mps2tz_common_init(MachineState *machine) { MPS2TZMachineState *mms =3D MPS2TZ_MACHINE(machine); @@ -499,24 +603,17 @@ static void mps2tz_common_init(MachineState *machine) qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, qdev_get_gpio_in(dev_splitter, 0)); =20 - /* The IoTKit sets up much of the memory layout, including + /* + * The IoTKit sets up much of the memory layout, including * the aliases between secure and non-secure regions in the - * address space. The FPGA itself contains: - * - * 0x00000000..0x003fffff SSRAM1 - * 0x00400000..0x007fffff alias of SSRAM1 - * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 - * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices - * 0x80000000..0x80ffffff 16MB PSRAM - */ - - /* The FPGA images have an odd combination of different RAMs, + * address space, and also most of the devices in the system. + * The FPGA itself contains various RAMs and some additional devices. + * The FPGA images have an odd combination of different RAMs, * because in hardware they are different implementations and * connected to different buses, giving varying performance/size * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily - * call the 16MB our "system memory", as it's the largest lump. + * call the largest lump our "system memory". */ - memory_region_add_subregion(system_memory, 0x80000000, machine->ram); =20 /* * The overflow IRQs for all UARTs are ORed together. @@ -549,9 +646,9 @@ static void mps2tz_common_init(MachineState *machine) const PPCInfo an505_ppcs[] =3D { { .name =3D "apb_ppcexp0", .ports =3D { - { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1= 000 }, - { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1= 000 }, - { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1= 000 }, + { "ssram-0-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x100= 0 }, + { "ssram-1-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x100= 0 }, + { "ssram-2-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x100= 0 }, }, }, { .name =3D "apb_ppcexp1", @@ -684,6 +781,8 @@ static void mps2tz_common_init(MachineState *machine) =20 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); =20 + create_non_mpc_ram(mms); + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400= 000); } =20 @@ -734,6 +833,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, vo= id *data) mmc->fpgaio_num_leds =3D 2; mmc->fpgaio_has_switches =3D false; mmc->numirq =3D 92; + mmc->raminfo =3D an505_raminfo; mmc->armsse_type =3D TYPE_IOTKIT; } =20 @@ -755,6 +855,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, vo= id *data) mmc->fpgaio_num_leds =3D 2; mmc->fpgaio_has_switches =3D false; mmc->numirq =3D 92; + mmc->raminfo =3D an505_raminfo; /* AN521 is the same as AN505 here */ mmc->armsse_type =3D TYPE_SSE200; } =20 --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613391265; cv=none; d=zohomail.com; s=zohoarc; b=JOlqnEzIg1oGlez0dSwBvFv3FQM8XuLIAVyIzYep9ZpQVKdUcVjK+ff6nby1WXRuwif39E2tVDJFX+dqbP3ohBQKV7nHIF6cJA7el+hM/mU16CwZjP6Qtj5cqg0rX3pQtrvCd7hcV+8BYoYs+/dmlY1dXtgyowjcxnmXNk8JBW4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613391265; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EqrwKzWHzWMN7lxcV1Y9F0BBb0MV1m8CQjXEiMLLrtw=; b=B9WIjGwWnYiWqxQnnB0BvF9f0MswtdlpmD/flqHbjRyw8SdjxuK0Rorq8SW12uHuGJ6cHJEeFDUYb8P1E6jORHcwYh3OIflhRE+zfAmTw6a6d2ohemm9L70n4XXfqH/1snjoG8l3grMUOQ65Demwc/BK+SGw/r21B7h6C8IljHg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613391265778176.34246679090268; Mon, 15 Feb 2021 04:14:25 -0800 (PST) Received: from localhost ([::1]:39074 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBclj-0000VI-SB for importer@patchew.org; Mon, 15 Feb 2021 07:14:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39642) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBcQt-00008c-NG for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:51 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:40880) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBcQr-0004BI-Vq for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:51 -0500 Received: by mail-wm1-x32a.google.com with SMTP id o24so9023836wmh.5 for ; Mon, 15 Feb 2021 03:52:49 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EqrwKzWHzWMN7lxcV1Y9F0BBb0MV1m8CQjXEiMLLrtw=; b=JaRD7M/r+GAtMCQO5rNqqmKWe+rERAZB3+aTPn6mhCfppub3MW3j9u+5Hpfg9l5d8g EdcTOmGZyZfCvD0W9DLWN/jXya+4SXFcUQ/qyeqcusE6QjdPHpeVxChlBpcVUwB9hupd UOVJgXzYVjrs/X9Y27pU0zaHo6gRlM0ifnJSV80XUVRGVdOb9fV6sskWX9n68nI+YZYG 2zFHTngKKcHnnH5O3y1MXslYp3uZ14eEFLZwdyGfDr6FkobGFI4xlcJFLOVu1vibYOfk 0aD8UOzlLLITSDAkIozk+1UDvFUowgXAmst/Vp8Nbwy9Kj3oHGzt2Er2YCXygkX5D/61 7WHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EqrwKzWHzWMN7lxcV1Y9F0BBb0MV1m8CQjXEiMLLrtw=; b=DJjRS8FkYA7hnoyDhQ4bcOS2zNDbbQk1GyKsTPxXOUYyRmctw25h6+pu6Pubee8EwI UTyMQm9wxRGJo/dEkGk1Kpm3SdLjxEh2SSi3sU4H8GIhhukrdWS1b0vhXDUJ/VHb5LYQ 4dvDlRhY/eqHAMLBXWC2keaA1E7VXcajL8JmZanfJUKZ/NAMes8w/hNnlGs+MWfzZK94 Tf1gEIrP1TWXDH8XxEuCeXxB4pBaKIxemTMTisLVma00HaXG20AbG+BN2JIkIviSGc7F WEOBRAT9hZAcyKsb0gmQeRKy36lSLE0Q9xYXJvZhBtDCVbN/WRf73V9qraR45C8qsIzM W2wg== X-Gm-Message-State: AOAM530DU7z8lueO7yVqBwp1C7cL7IjMEdaV2RIf48pa/Lbqr/iVFRi4 Xr0PqPPU89f4UbNODNsFgHvPID6uXDoANg== X-Google-Smtp-Source: ABdhPJxvkyKF7c9ptsFXkkYMjc0e/dQ/fwx+UMroPUS2a24hwlOv5akOJLFJ3a1P5aIqwHJtwJOTdw== X-Received: by 2002:a7b:cd04:: with SMTP id f4mr14086741wmj.76.1613389968665; Mon, 15 Feb 2021 03:52:48 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 17/24] hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data Date: Mon, 15 Feb 2021 11:51:31 +0000 Message-Id: <20210215115138.20465-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Instead of hardcoding the MachineClass default_ram_size and default_ram_id fields, set them on class creation by finding the entry in the RAMInfo array which is marked as being the QEMU system RAM. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 18f75eacfcd..08dd2cbaa40 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -811,8 +811,26 @@ static void mps2tz_class_init(ObjectClass *oc, void *d= ata) =20 mc->init =3D mps2tz_common_init; iic->check =3D mps2_tz_idau_check; - mc->default_ram_size =3D 16 * MiB; - mc->default_ram_id =3D "mps.ram"; +} + +static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc) +{ + /* + * Set mc->default_ram_size and default_ram_id from the + * information in mmc->raminfo. + */ + MachineClass *mc =3D MACHINE_CLASS(mmc); + const RAMInfo *p; + + for (p =3D mmc->raminfo; p->name; p++) { + if (p->mrindex < 0) { + /* Found the entry for "system memory" */ + mc->default_ram_size =3D p->size; + mc->default_ram_id =3D p->name; + return; + } + } + g_assert_not_reached(); } =20 static void mps2tz_an505_class_init(ObjectClass *oc, void *data) @@ -835,6 +853,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, vo= id *data) mmc->numirq =3D 92; mmc->raminfo =3D an505_raminfo; mmc->armsse_type =3D TYPE_IOTKIT; + mps2tz_set_default_ram_info(mmc); } =20 static void mps2tz_an521_class_init(ObjectClass *oc, void *data) @@ -857,6 +876,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, vo= id *data) mmc->numirq =3D 92; mmc->raminfo =3D an505_raminfo; /* AN521 is the same as AN505 here */ mmc->armsse_type =3D TYPE_SSE200; + mps2tz_set_default_ram_info(mmc); } =20 static const TypeInfo mps2tz_info =3D { --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613390325; cv=none; d=zohomail.com; s=zohoarc; b=Z067vUGV9lYBcngZdZDZ8HuGBs7D8gebu5JlhI5qbRTiTVFp9cal9peTJ1F8/IVOqN0he9MIYlCcUns9juUa1M6Mm8BC4Ch3REcwDt61eOT57O+Ku4LTbuSk+bGuLIV+aqWzOGTtYORGgYFE5WSkeWFb9Y0SJVcRw+6xwH9X9Uo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613390325; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Q4947nZDfKCY91YN+GzWW3j1l05CAmRJnmXZQOGt5go=; b=Zym7BNAtOGj7qv6PmJQBRQVsGrCMHTpvholnbLhzR3QJLvl82elSD4kdh9q1GAvO0EhLaTGnpi5srTaThj0wAD3tspKBBRS3fZln7jbCU6sx1ZfgjitoAaUSTiaIEV0cw66aYHB5Z6FFoO2SDKR6jscC7PJx8sKdJyINSNrKWjg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613390324677154.97088757383688; Mon, 15 Feb 2021 03:58:44 -0800 (PST) Received: from localhost ([::1]:53432 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBcWZ-0007mm-Ew for importer@patchew.org; Mon, 15 Feb 2021 06:58:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39694) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBcQx-0000Fp-Mt for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:56 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:38213) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBcQu-0004DP-Qf for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:55 -0500 Received: by mail-wr1-x435.google.com with SMTP id b3so8510669wrj.5 for ; Mon, 15 Feb 2021 03:52:52 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q4947nZDfKCY91YN+GzWW3j1l05CAmRJnmXZQOGt5go=; b=lWGzjOTMyq/LBWnPpM9Je6oed0XfNy3ZsyZwO+WB9FL5FHkz0zjJqv8oNNve8X238m gEe1nMDaAR+fVT2+TzJV2j9AVjU2JSLRMYSkttxcWjOpHhaRNsavA4dJh/Qt/ryDe33+ Hyj2M8lgDmOVe1BnAFY2mjzQ25dJSp9PD2Jq+xq2s/4D0FIKdbQxq0maNTZtA6/La30y oBAf+J48zUqprPcXIZxETQ9ALzd2LQnEuIpXPqZNR/vT1lky1mMXoglWDFjpWKPd1nlH 3/LiH6I6msK//bl8QvrP3ZL4fHdlmNTYNQWoUW5aGR4u0+3ccc1tSAhpIjUxJwpfuFZ5 q0Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q4947nZDfKCY91YN+GzWW3j1l05CAmRJnmXZQOGt5go=; b=bkqPYfl6sZQ3EUSo3APLFgtyuQnn1GOGVjytaQ3dk4uqovsyUATGPMk0j/I0g3Au66 aOP6l1KgZRUvAua8gmldmF5dyANSqicVcuwI/1/saOpU0L9KOyAxxV5UJAyEGo/T2kqr DqbdPy7LepjaG1KaxrAnQonO3GOzCg5G6inj9Wqj4y8ve6cTqigp6DC3F5EuauKNxjfI J7tjSCQv+Gb3xQ98V5u4KCzSu6G+bA+xXFQ6b0vQ7u3eD0QIxAkIyW9JAHPqQxwscNQ9 60rSXY9kQ7GfFl3lXjAwsNRD1ItejWHEDtBa0kgqZwuiYOdtPArZyP5LnTujV29XhpfD /2yg== X-Gm-Message-State: AOAM531CP9cO/RI8d83dqy9edQD0NKVV/aLC/4zFKTudiVLVlobqzWWp 761ly4tbM83m37sdNuFyAWJzsQ== X-Google-Smtp-Source: ABdhPJyKbkpm1DU19Sl+ablDj/RM53U1K3abSO1xJkSkZxgTOtUZTZquI+W6yMXXP9XvQ27jv9/cPA== X-Received: by 2002:adf:fb49:: with SMTP id c9mr18704484wrs.72.1613389971566; Mon, 15 Feb 2021 03:52:51 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 18/24] hw/arm/mps2-tz: Support ROMs as well as RAMs Date: Mon, 15 Feb 2021 11:51:32 +0000 Message-Id: <20210215115138.20465-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The AN505 and AN521 don't have any read-only memory, but the AN524 does; add a flag to ROMInfo to mark a region as ROM. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 08dd2cbaa40..cc9d70ece54 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -92,8 +92,10 @@ typedef struct RAMInfo { * Flag values: * IS_ALIAS: this RAM area is an alias to the upstream end of the * MPC specified by its .mpc value + * IS_ROM: this RAM area is read-only */ #define IS_ALIAS 1 +#define IS_ROM 2 =20 struct MPS2TZMachineClass { MachineClass parent; @@ -209,6 +211,7 @@ static MemoryRegion *mr_for_raminfo(MPS2TZMachineState = *mms, if (raminfo->mrindex < 0) { /* Means this RAMInfo is for QEMU's "system memory" */ MachineState *machine =3D MACHINE(mms); + assert(!(raminfo->flags & IS_ROM)); return machine->ram; } =20 @@ -217,6 +220,9 @@ static MemoryRegion *mr_for_raminfo(MPS2TZMachineState = *mms, =20 memory_region_init_ram(ram, NULL, raminfo->name, raminfo->size, &error_fatal); + if (raminfo->flags & IS_ROM) { + memory_region_set_readonly(ram, true); + } return ram; } =20 --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613390999; cv=none; d=zohomail.com; s=zohoarc; b=KU+SjLxtRZ42+czpF1q1esHxh+FIDimpDwQrRUh30HYA09KwnLNU83bYN+xBxyHMhMi/q3VaVRBamkIfJu8yQFsK5Ejq7j0RNLEqi4+WS/La7zJA8uKh532RPeUzmm3LsmHZMhSZoxdDvctzusJbscDSE1ARawCvyjtgbxErVKU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613390999; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FA09qyTC4OitINqYBcwCDg9CArRGCBIo+PjjkY7Qht0=; b=NP+jk5qLlG7JBCkKN6wJdnPg8R3ldYBZi7emEfOGHTCgoLugL6mL+vgxTighl+62FMVTwybAVZTM5AGR/9XtbvzHTWnqVUm4wJWvbcNCLvWmgoGOBpgpTLR+ScxBzkQLuBWgr/7/ocft3b+aYZtDFtVLR8BKVmmWXGjIXc8DvfE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613390999026978.6004506067811; Mon, 15 Feb 2021 04:09:59 -0800 (PST) Received: from localhost ([::1]:55410 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBchR-0003ef-TR for importer@patchew.org; Mon, 15 Feb 2021 07:09:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39720) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBcR0-0000I5-8K for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:58 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:35414) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBcQx-0004F6-VJ for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:52:58 -0500 Received: by mail-wr1-x42c.google.com with SMTP id l12so8547658wry.2 for ; Mon, 15 Feb 2021 03:52:55 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FA09qyTC4OitINqYBcwCDg9CArRGCBIo+PjjkY7Qht0=; b=qj1tw5HJWVGzAKi494VKcYD85vP4YaoQq7wXCfNJ0MrdmWiM7NGNxTCkboDoEH2QSn 3c/CRKvHWcbAEtCISyIVU4W2OX1D2xNA81fd7RJo8Xp6fHcWw0X1uRwIXzsKtPFXC63e l0DPNBaRkpvePtNpXPaDILF9mR6EBVKsIDLWUJxwkL0urHJf7ZLWUOnsiIFdSX88Nm1M G8P+qfSq6LSIA7QcPxQQQft5hqbw5devLUUhPLXSirEcM6pm/8moj+sM5ALpNJIoTnQY 1USWs1j9d9STxyiuPwV8k+Ngodjy70uUYD++/tGpYPz6ylEtzuerDh5nLw2jvytadB60 vv+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FA09qyTC4OitINqYBcwCDg9CArRGCBIo+PjjkY7Qht0=; b=VQEZKVshhyMVW8wNL0bIn8OhPy2t2tI3dEzJNfBYUt8dA9XGBve8832WYPuDLG+f6o CuxB0oxPydWubLq+WweKOdsH75vS5Uq0XXp1GYtZu6FGfAggkpqWXdBms+/uNbLXUIu7 3+7ovBhpJHp8bAvY93odDyG0Ct3dl/5KgmSiVoGjo7FgvhAt4ubLNVmeZ/XX0kgvsPYZ s1TuShIStxPQY0vMxaWmNjVFpbB6qLjapQdzdlC4zCtJdfkomLsrJKBvkkymCiYCFbMW 2C/t1+//5pF99Na74Gv0rasa2gztwJ2aqvS8Ttg5m2mjll4EL3BDz51Us6hf5MhZZBT4 B5TA== X-Gm-Message-State: AOAM533KW5gvupl/h8REjLCHOGoOw36INaYK9uqpYZfJh7UL2ybnhInR j/f8QlCUd3q/AOmgRnD1sBVJBg== X-Google-Smtp-Source: ABdhPJxvNKq3Mrnr7M4W+maWg87c8b0rBsL+93F8+AKNf7fpC1pZiax1j35k9UOsvQkHga6IiEQ8wQ== X-Received: by 2002:a5d:570b:: with SMTP id a11mr18906627wrv.242.1613389974750; Mon, 15 Feb 2021 03:52:54 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 19/24] hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo Date: Mon, 15 Feb 2021 11:51:33 +0000 Message-Id: <20210215115138.20465-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The armv7m_load_kernel() function takes a mem_size argument which it expects to be the size of the memory region at guest address 0. (It uses this argument only as a limit on how large a raw image file it can load at address zero). Instead of hardcoding this value, find the RAMInfo corresponding to the 0 address and extract its size. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index cc9d70ece54..da27caa332d 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -525,6 +525,20 @@ static void create_non_mpc_ram(MPS2TZMachineState *mms) } } =20 +static uint32_t boot_ram_size(MPS2TZMachineState *mms) +{ + /* Return the size of the RAM block at guest address zero */ + const RAMInfo *p; + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); + + for (p =3D mmc->raminfo; p->name; p++) { + if (p->base =3D=3D 0) { + return p->size; + } + } + g_assert_not_reached(); +} + static void mps2tz_common_init(MachineState *machine) { MPS2TZMachineState *mms =3D MPS2TZ_MACHINE(machine); @@ -789,7 +803,8 @@ static void mps2tz_common_init(MachineState *machine) =20 create_non_mpc_ram(mms); =20 - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400= 000); + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + boot_ram_size(mms)); } =20 static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161339046725262.493677640295914; Mon, 15 Feb 2021 04:01:07 -0800 (PST) Received: from localhost ([::1]:33524 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBcYr-0002jh-IK for importer@patchew.org; Mon, 15 Feb 2021 07:01:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39780) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBcR8-0000JK-EX for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:53:07 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:36096) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBcR2-0004Hc-OS for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:53:06 -0500 Received: by mail-wm1-x331.google.com with SMTP id h67so4235011wmh.1 for ; Mon, 15 Feb 2021 03:53:00 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.52.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:52:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nRr1C7q5zeK3oCgmytzLs7IaWHaLenFMaUKqIuvkC1o=; b=OpPpikEKxNSlcFp1C0IO2iriDx06ZOgeHlpNaQvP0dzv7don/oHhjjDMZPpR7Bhd9q bx3R5fylA6oWINdbj8n0khnkp5NU2P8YW0GyO7RzzvSQlU12YJzmDGXpP3bsZmtdMn2G neCdjK53OJnCuiuSV2pg+wZpPnooy1K0HhhZbr2cnLoq5fEknSLkZjEy14OLuVjlULys Y37q3o0Z+jUVjYC0riUjlJoYEM8VmPbUYUsPAYF0e9d6UlkeZEbeLfspqHXYCjxi4YeZ NQRbd//rtlvJnKSj65keJKdnYERf2Rpy/Y50WHw5K9GLpOwRMThfYk8bCj2KVbsKAGYD ZVZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nRr1C7q5zeK3oCgmytzLs7IaWHaLenFMaUKqIuvkC1o=; b=h8eEaCNBOTz1/9t9vuGi7ed8eYbjpT+sSnCi9v2cy8qBDXrZCWbyeCsKjXIOwsjSt+ i92bDDzyYllD22LBmZvxl8naNo1J6A0wW0ExE0AOfZBy+eXfia+chho4QbWniWWw8IgO 75/4y603P1HOyCVhmoebzH1nFTRhUReZSCd89HJ6f9k0Nk0ixl2Tp0/OI5mcZXXlXSOw jsjYCNTVVeFqyJqqmCB8qHuQdvXXK8CII+alzlduMB3NrwMFYZfpLEAVYadMxcVygBWB hRXRTLEx5O2SkEPBYjyxen+tzRIkjMOwIrudRLfr/erQQguH4YJxKETJrdA7DybY/yzT nQDQ== X-Gm-Message-State: AOAM530dd36q6YnfoHtPrn0L37HJdWToaPWS6w3+cY1PG8TBLNW7xOzh vxIA3rWkg0vP6icXmeEMoeqRZQ== X-Google-Smtp-Source: ABdhPJxrED3Os/D7Be280SG43fFKMdwS4lGCUogLIYlSiBIi71pVv0jNyusp3j+bBB0GHELORpzL2Q== X-Received: by 2002:a05:600c:350c:: with SMTP id h12mr10829233wmq.39.1613389979505; Mon, 15 Feb 2021 03:52:59 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 20/24] hw/arm/mps2-tz: Add new mps3-an524 board Date: Mon, 15 Feb 2021 11:51:34 +0000 Message-Id: <20210215115138.20465-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Add support for the mps3-an524 board; this is an SSE-200 based FPGA image, like the existing mps2-an521. It has a usefully larger amount of RAM, and a PL031 RTC, as well as some more minor differences. In real hardware this image runs on a newer generation of the FPGA board, the MPS3 rather than the older MPS2. Architecturally the two boards are similar, so we implement the MPS3 boards in the mps2-tz.c file as variations of the existing MPS2 boards. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 139 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 135 insertions(+), 4 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index da27caa332d..5e12ee2c3d3 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -16,6 +16,7 @@ * This source file covers the following FPGA images, for TrustZone cores: * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 + * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524 * * Links to the TRM for the board itself and to the various Application * Notes which document the FPGA images can be found here: @@ -27,11 +28,13 @@ * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html * Application Note AN521: * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html + * Application Note AN524: + * https://developer.arm.com/documentation/dai0524/latest/ * * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Gu= ide * (ARM ECM0601256) for the details of some of the device layout: * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm0601= 256/index.html - * Similarly, the AN521 uses the SSE-200, and the SSE-200 TRM defines + * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM def= ines * most of the device layout: * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/cor= elink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_= 00_en.pdf * @@ -65,12 +68,13 @@ #include "hw/qdev-clock.h" #include "qom/object.h" =20 -#define MPS2TZ_NUMIRQ_MAX 92 +#define MPS2TZ_NUMIRQ_MAX 95 #define MPS2TZ_RAM_MAX 4 =20 typedef enum MPS2TZFPGAType { FPGA_AN505, FPGA_AN521, + FPGA_AN524, } MPS2TZFPGAType; =20 /* @@ -121,13 +125,15 @@ struct MPS2TZMachineState { TZPPC ppc[5]; TZMPC mpc[3]; PL022State spi[5]; - ArmSbconI2CState i2c[4]; + ArmSbconI2CState i2c[5]; UnimplementedDeviceState i2s_audio; UnimplementedDeviceState gpio[4]; UnimplementedDeviceState gfx; + UnimplementedDeviceState cldc; + UnimplementedDeviceState rtc; PL080State dma[4]; TZMSC msc[4]; - CMSDKAPBUART uart[5]; + CMSDKAPBUART uart[6]; SplitIRQ sec_resp_splitter; qemu_or_irq uart_irq_orgate; DeviceState *lan9118; @@ -139,6 +145,7 @@ struct MPS2TZMachineState { #define TYPE_MPS2TZ_MACHINE "mps2tz" #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") +#define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524") =20 OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) =20 @@ -151,6 +158,15 @@ static const uint32_t an505_oscclk[] =3D { 25000000, }; =20 +static const uint32_t an524_oscclk[] =3D { + 24000000, + 32000000, + 50000000, + 50000000, + 24576000, + 23750000, +}; + static const RAMInfo an505_raminfo[] =3D { { .name =3D "ssram-0", .base =3D 0x00000000, @@ -188,6 +204,37 @@ static const RAMInfo an505_raminfo[] =3D { { }, }; =20 +static const RAMInfo an524_raminfo[] =3D { { + .name =3D "bram", + .base =3D 0x00000000, + .size =3D 512 * KiB, + .mpc =3D 0, + .mrindex =3D 0, + }, { + .name =3D "sram", + .base =3D 0x20000000, + .size =3D 32 * 4 * KiB, + .mpc =3D 1, + .mrindex =3D 1, + }, { + /* We don't model QSPI flash yet; for now expose it as simple ROM = */ + .name =3D "QSPI", + .base =3D 0x28000000, + .size =3D 8 * MiB, + .mpc =3D 1, + .mrindex =3D 2, + .flags =3D IS_ROM, + }, { + .name =3D "DDR", + .base =3D 0x60000000, + .size =3D 2 * GiB, + .mpc =3D 2, + .mrindex =3D -1, + }, { + .name =3D NULL, + }, +}; + static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mp= c) { MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); @@ -717,12 +764,66 @@ static void mps2tz_common_init(MachineState *machine) }, }; =20 + const PPCInfo an524_ppcs[] =3D { { + .name =3D "apb_ppcexp0", + .ports =3D { + { "bram-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, + { "qspi-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, + { "ddr-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, + }, + }, { + .name =3D "apb_ppcexp1", + .ports =3D { + { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000 }, + { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000 }, + { "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52= } }, + { "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53= } }, + { "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54= } }, + { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000 }, + { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000 }, + { /* port 7 reserved */ }, + { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000 }, + }, + }, { + .name =3D "apb_ppcexp2", + .ports =3D { + { "scc", make_scc, &mms->scc, 0x41300000, 0x1000 }, + { "i2s-audio", make_unimp_dev, &mms->i2s_audio, + 0x41301000, 0x1000 }, + { "fpgaio", make_fpgaio, &mms->fpgaio, 0x41302000, 0x1000 = }, + { "uart0", make_uart, &mms->uart[0], 0x41303000, 0x1000, {= 32, 33, 42 } }, + { "uart1", make_uart, &mms->uart[1], 0x41304000, 0x1000, {= 34, 35, 43 } }, + { "uart2", make_uart, &mms->uart[2], 0x41305000, 0x1000, {= 36, 37, 44 } }, + { "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, {= 38, 39, 45 } }, + { "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, {= 40, 41, 46 } }, + { "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, {= 124, 125, 126 } }, + + { /* port 9 reserved */ }, + { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, + { "rtc", make_unimp_dev, &mms->rtc, 0x4130b000, 0x1000 }, + }, + }, { + .name =3D "ahb_ppcexp0", + .ports =3D { + { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x10= 00 }, + { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x10= 00 }, + { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x10= 00 }, + { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x10= 00 }, + { "eth", make_eth_dev, NULL, 0x41400000, 0x100000, { 48 } = }, + }, + }, + }; + switch (mmc->fpga_type) { case FPGA_AN505: case FPGA_AN521: ppcs =3D an505_ppcs; num_ppcs =3D ARRAY_SIZE(an505_ppcs); break; + case FPGA_AN524: + ppcs =3D an524_ppcs; + num_ppcs =3D ARRAY_SIZE(an524_ppcs); + break; default: g_assert_not_reached(); } @@ -900,6 +1001,29 @@ static void mps2tz_an521_class_init(ObjectClass *oc, = void *data) mps2tz_set_default_ram_info(mmc); } =20 +static void mps3tz_an524_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_CLASS(oc); + + mc->desc =3D "ARM MPS3 with AN524 FPGA image for dual Cortex-M33"; + mc->default_cpus =3D 2; + mc->min_cpus =3D mc->default_cpus; + mc->max_cpus =3D mc->default_cpus; + mmc->fpga_type =3D FPGA_AN524; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); + mmc->scc_id =3D 0x41045240; + mmc->sysclk_frq =3D 32 * 1000 * 1000; /* 32MHz */ + mmc->oscclk =3D an524_oscclk; + mmc->len_oscclk =3D ARRAY_SIZE(an524_oscclk); + mmc->fpgaio_num_leds =3D 10; + mmc->fpgaio_has_switches =3D true; + mmc->numirq =3D 95; + mmc->raminfo =3D an524_raminfo; + mmc->armsse_type =3D TYPE_SSE200; + mps2tz_set_default_ram_info(mmc); +} + static const TypeInfo mps2tz_info =3D { .name =3D TYPE_MPS2TZ_MACHINE, .parent =3D TYPE_MACHINE, @@ -925,11 +1049,18 @@ static const TypeInfo mps2tz_an521_info =3D { .class_init =3D mps2tz_an521_class_init, }; =20 +static const TypeInfo mps3tz_an524_info =3D { + .name =3D TYPE_MPS3TZ_AN524_MACHINE, + .parent =3D TYPE_MPS2TZ_MACHINE, + .class_init =3D mps3tz_an524_class_init, +}; + static void mps2tz_machine_init(void) { type_register_static(&mps2tz_info); type_register_static(&mps2tz_an505_info); type_register_static(&mps2tz_an521_info); + type_register_static(&mps3tz_an524_info); } =20 type_init(mps2tz_machine_init); --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.53.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:53:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=myzWPQ7aahYwu4rcii5/SdEFuQpyy/NesVoypbH4mDU=; b=nsmzH6uGWoA95x3lefjHwaVmPI+8jgU8QWsTKUNUwlz1AiopPaw47WlXfN7/eO9J1o iraAOhpiHTGWHxP98tvXklA6HW/d+6gwaIHKo/DqV+ZNXTIN0QpixAv5h4m8VHUwlonS 1LM92WFbQgmwqJls+6GvEpXbND475c46uOi+94nNLg9hcSR5PXI1bBkKaP/wa2ahgaB1 Nj3AQvUrWRr9a6BTiRBZ14TE7LGY/LL5b+qFRV5z7xFeFjQesC7KrhlTjs7kMPcv39LL qnBcQr2UxPx4ZzJL6893vKBchb6oP2a3GKJMIqSQKkk8srj1kGALCZtvW8z20rY/7xHI r6Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=myzWPQ7aahYwu4rcii5/SdEFuQpyy/NesVoypbH4mDU=; b=L5ApN1Hi4NRAgsipFllVGAPD+sUbo8U60/G9T+z+gyoy8oNW0cy5TK8r8V1cd93Piv ojne0mxwEAv3Ihniso6phk5oNKp+MKEoX/s0RO5g3Aem+kddZCRLdqVZFXW0pcKTN1Pf BeGi7sF61zVRAYZeJl7Z1++k+1kjBRoPS1ch4C4WdYU/IFobjflKOtVbr7q2XGRWVnmM 98dwBHubxILzyp1sdq1sEghylTRIv1jQld3NKq1bSens869df1nLgmUbOXO76RZipdNR Y/zE3CirKDVLC6NVqgKIdhTTwJs/pY64MeYUk/8YYgNlj9rRtjXCckFzdN5eGF93Ckjo CZwQ== X-Gm-Message-State: AOAM530MCJhs97QV2GXiPmFDjR3vrS8N+AxxnC0yGVmmwK6meNfBVytO 3bgukJXEPwvps4Z2Nw6GtNJMqg== X-Google-Smtp-Source: ABdhPJwIB9BiYia7T6DEBGYqfgH/0DadGG1AZlpp9/+AyAjzdyDheuzUwG3nuMEp4p0j+RoGVv5x4A== X-Received: by 2002:adf:e708:: with SMTP id c8mr13632529wrm.152.1613389982587; Mon, 15 Feb 2021 03:53:02 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 21/24] hw/arm/mps2-tz: Stub out USB controller for mps3-an524 Date: Mon, 15 Feb 2021 11:51:35 +0000 Message-Id: <20210215115138.20465-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The AN524 has a USB controller (an ISP1763); we don't have a model of it but we should provide a stub "unimplemented-device" for it. This is slightly complicated because the USB controller shares a PPC port with the ethernet controller. Implement a make_* function which provides creates a container MemoryRegion with both the ethernet controller and an unimplemented-device stub for the USB controller. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 5e12ee2c3d3..183c3920903 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -120,6 +120,8 @@ struct MPS2TZMachineState { =20 ARMSSE iotkit; MemoryRegion ram[MPS2TZ_RAM_MAX]; + MemoryRegion eth_usb_container; + MPS2SCC scc; MPS2FPGAIO fpgaio; TZPPC ppc[5]; @@ -131,6 +133,7 @@ struct MPS2TZMachineState { UnimplementedDeviceState gfx; UnimplementedDeviceState cldc; UnimplementedDeviceState rtc; + UnimplementedDeviceState usb; PL080State dma[4]; TZMSC msc[4]; CMSDKAPBUART uart[6]; @@ -432,6 +435,49 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *= mms, void *opaque, return sysbus_mmio_get_region(s, 0); } =20 +static MemoryRegion *make_eth_usb(MPS2TZMachineState *mms, void *opaque, + const char *name, hwaddr size, + const int *irqs) +{ + /* + * The AN524 makes the ethernet and USB share a PPC port. + * irqs[] is the ethernet IRQ. + */ + SysBusDevice *s; + NICInfo *nd =3D &nd_table[0]; + + memory_region_init(&mms->eth_usb_container, OBJECT(mms), + "mps2-tz-eth-usb-container", 0x200000); + + /* + * In hardware this is a LAN9220; the LAN9118 is software compatible + * except that it doesn't support the checksum-offload feature. + */ + qemu_check_nic_model(nd, "lan9118"); + mms->lan9118 =3D qdev_new(TYPE_LAN9118); + qdev_set_nic_properties(mms->lan9118, nd); + + s =3D SYS_BUS_DEVICE(mms->lan9118); + sysbus_realize_and_unref(s, &error_fatal); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); + + memory_region_add_subregion(&mms->eth_usb_container, + 0, sysbus_mmio_get_region(s, 0)); + + /* The USB OTG controller is an ISP1763; we don't have a model of it. = */ + object_initialize_child(OBJECT(mms), "usb-otg", + &mms->usb, TYPE_UNIMPLEMENTED_DEVICE); + qdev_prop_set_string(DEVICE(&mms->usb), "name", "usb-otg"); + qdev_prop_set_uint64(DEVICE(&mms->usb), "size", 0x100000); + s =3D SYS_BUS_DEVICE(&mms->usb); + sysbus_realize(s, &error_fatal); + + memory_region_add_subregion(&mms->eth_usb_container, + 0x100000, sysbus_mmio_get_region(s, 0)); + + return &mms->eth_usb_container; +} + static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, const int *irqs) @@ -809,7 +855,7 @@ static void mps2tz_common_init(MachineState *machine) { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x10= 00 }, { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x10= 00 }, { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x10= 00 }, - { "eth", make_eth_dev, NULL, 0x41400000, 0x100000, { 48 } = }, + { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 4= 8 } }, }, }, }; --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.53.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:53:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wGYGw0ciQ1NZJCLjbpj4MSbJnkP3xpGrgMVONXVokMg=; b=LmNoUA+bfSN/lWSQ515HzJRXmPTjyQP0d+5I7rp8koQAqo5abKaRDzsNN09H3E6Jng RaS62sHgPv8XOYIP61QNpQtZFtTEBc/Kmd3hM8Ln1up0GnaKU5x284nC5j4+2ZlRYfSv mIMsQr3XE1JjFjr4kcmJOQHqI/3JvU4/0MMFcF0HPr/BjX71qjU/CN0Fel0IS2OogZgb ilkLsLTbU7ZLl5RSSNuZzisX6kHcTfGxz3cUSf7dBIn/2uWy2wIgt1L9qMRnnZdJvRoZ vHg3VW8THxUSrTpQbne5kUA6hDhi0ePqQS1xBM3MZVK9Jl5i7tZ6M4r+gNDJAJN3ORly +aBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wGYGw0ciQ1NZJCLjbpj4MSbJnkP3xpGrgMVONXVokMg=; b=gEYLsbnTQ1EZJrTaXDwwcB5m2ETPrD9W70LFIxamcVigpo0sNnuHD1G/lqzDxUKuPU LnXhyytkYDQoSkfnYk38h3J0XRqRqs47uNJHrkXFiOZuFLHQM31LsvTLFvz/u/3AKXJU 9OZYeZiiz7etoF21/nleH8tGd5oikc1XCjF/OgbE6PSCkToQWBCXMIWotuBoJPoWHP5C e5ae9rLKxQjEQ7mmJ0kxiB2Y6EkujXABWOCn+PLXTkhFS2+75KuAuSrU+NSxXaZVaJu4 rsb7fo4dtWEB9gqX2JXB+n/5AwcnPzbPIGl63h5E/Cq4XvW4RV3Vl93FhU72W8JBztFB 5SkQ== X-Gm-Message-State: AOAM531siNIrWZHzrRBcAO+5DFr/ORPtokqh6Ihnq2j1YR9nd4BNisaC oVWRZFOI1ejofUjdVBrEDVZ2eA== X-Google-Smtp-Source: ABdhPJxmsosmTYZCu/uiHuz61aZmil72gTdlP73ugL0XOHRlCO/tFGY9H2OaY1OMOI5SR3HxCRyJ/w== X-Received: by 2002:a05:6000:108b:: with SMTP id y11mr4306458wrw.124.1613389986144; Mon, 15 Feb 2021 03:53:06 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 22/24] hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524 Date: Mon, 15 Feb 2021 11:51:36 +0000 Message-Id: <20210215115138.20465-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The AN524 has a PL031 RTC, which we have a model of; provide it rather than an unimplemented-device stub. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 183c3920903..2c385422373 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -60,6 +60,7 @@ #include "hw/misc/tz-msc.h" #include "hw/arm/armsse.h" #include "hw/dma/pl080.h" +#include "hw/rtc/pl031.h" #include "hw/ssi/pl022.h" #include "hw/i2c/arm_sbcon_i2c.h" #include "hw/net/lan9118.h" @@ -132,8 +133,8 @@ struct MPS2TZMachineState { UnimplementedDeviceState gpio[4]; UnimplementedDeviceState gfx; UnimplementedDeviceState cldc; - UnimplementedDeviceState rtc; UnimplementedDeviceState usb; + PL031State rtc; PL080State dma[4]; TZMSC msc[4]; CMSDKAPBUART uart[6]; @@ -596,6 +597,23 @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms,= void *opaque, return sysbus_mmio_get_region(s, 0); } =20 +static MemoryRegion *make_rtc(MPS2TZMachineState *mms, void *opaque, + const char *name, hwaddr size, + const int *irqs) +{ + PL031State *pl031 =3D opaque; + SysBusDevice *s; + + object_initialize_child(OBJECT(mms), name, pl031, TYPE_PL031); + s =3D SYS_BUS_DEVICE(pl031); + sysbus_realize(s, &error_fatal); + /* + * The board docs don't give an IRQ number for the PL031, so + * presumably it is not connected. + */ + return sysbus_mmio_get_region(s, 0); +} + static void create_non_mpc_ram(MPS2TZMachineState *mms) { /* @@ -846,7 +864,7 @@ static void mps2tz_common_init(MachineState *machine) =20 { /* port 9 reserved */ }, { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, - { "rtc", make_unimp_dev, &mms->rtc, 0x4130b000, 0x1000 }, + { "rtc", make_rtc, &mms->rtc, 0x4130b000, 0x1000 }, }, }, { .name =3D "ahb_ppcexp0", --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613391751; cv=none; d=zohomail.com; s=zohoarc; b=Ke7dLrGkvs4lm7DeP5hDJv1497s4ViX4ggMvFzySomWRRNzGCC0wcGx4RcfPOjaTWCACfulXqWNrG83IDFpk4+QyIwpyfyv2FJeqES72Aflg50B4m5j8Jsaa8XdeX3VTSwgCAhz+5o+ebBCXnuZItPaE9qyVldli/IZujD8U8s8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613391751; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1tcAjs6Tc8qQsl3E9FrIN+atfmeW4XdFPz3i2ahNQZg=; b=ZocZbMLP36VUf/1YGonGgDd+02wdpbGUb5/NjtXsKdL7fud5i2cgbFiHdrYaNBAYENh62CTV9XklmvW1ntCdhzeZcwgTSOWGCVBeklCrGjOym1p1JyBIw9QJ1cKX33nf4GGVK3AH3LqMVFKrHLNdM4Ym6r6/BkJZ2EMAwzCdVDw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613391751524266.77560921355905; Mon, 15 Feb 2021 04:22:31 -0800 (PST) Received: from localhost ([::1]:57482 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBcta-0000Mk-5Z for importer@patchew.org; Mon, 15 Feb 2021 07:22:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39872) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBcRI-0000P8-9O for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:53:17 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:38149) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBcRB-0004KK-ND for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:53:16 -0500 Received: by mail-wm1-x32b.google.com with SMTP id x4so9063020wmi.3 for ; Mon, 15 Feb 2021 03:53:09 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.53.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:53:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1tcAjs6Tc8qQsl3E9FrIN+atfmeW4XdFPz3i2ahNQZg=; b=EijJPzjFJs3G562lgGFUbRqLtDIgX/B2FFRNo9gsEc2aX9sgq/wltrNr1gnm1H5/DJ rhGWSMnWLp9YQEJ7QC8F9rc2ReBwkN+hDcRbldmhn4v+t+01IJmpsmgrKaoB+1d0yh51 sUkcexnwDdWDclH0vM/LdBUAOARUBi83hbok4Uuj8B3QNr2NQXZ0b/I69QLdaTNd2Mfa T9dWDA4bA+UNzbkKpVSaBqyVMOOyaA3qOS85606Hqd+ODI0OX3Cb2+BPTAhDEyaUy7s7 bFO8Q+j6aHbtc41UAMS9ndTac2TtwmxKcn4eN6r3FRrpXT6rKQNAihZj9tLfNVJSW+iz 9IIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1tcAjs6Tc8qQsl3E9FrIN+atfmeW4XdFPz3i2ahNQZg=; b=REvnZNEm+CZ22qWhjsJG2v9wOe/lGmyQVpDe8uskvMfhHlSU8nxRbdlqzvV2jcgHJ9 xJIOP3rA74AMqECjFKD65GvzHY+Yfm5Ql+yV6U7IGE7saZttaW+Edf3xNeUZfhY/MNIh MMT77jcRcj/t3V5pJ2gHyGhi5ZxTugC3qfiIf5Gw8GLF810VIMvsgH9DNZjn19qteLPt Ugy+vhzSQ17wnMmCJ963T8l9837QtynVeuxaup6G3OLMn+1bGuZhIsKzWFkJk+0pWTOB EtgEfYmjyBO/I/wswLo9vsSPX5V21bJnBYTI0zgfZ84KKehsAXaN2/bfctZNo9tkimae 5raA== X-Gm-Message-State: AOAM533Nz9fRKXMcD9FPyBNSj9uC0eimKSsGcguSLi5Pge1RbjIZJtIO cXSCZkAK072E3wgUOLvKtZOisnjMWvQRoQ== X-Google-Smtp-Source: ABdhPJwOoXvDi8iBcRkYhtmkoM2783GqUJkScwIe6dHgmBasXHC4hoFot4x6i6ZiqtIcX9XXBV0low== X-Received: by 2002:a7b:cbc2:: with SMTP id n2mr13800559wmi.34.1613389988575; Mon, 15 Feb 2021 03:53:08 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 23/24] docs/system/arm/mps2.rst: Document the new mps3-an524 board Date: Mon, 15 Feb 2021 11:51:37 +0000 Message-Id: <20210215115138.20465-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Add brief documentation of the new mps3-an524 board. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- docs/system/arm/mps2.rst | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index 8c5b5f1fe07..601ccea15cb 100644 --- a/docs/system/arm/mps2.rst +++ b/docs/system/arm/mps2.rst @@ -1,12 +1,15 @@ -Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an= 505``, ``mps2-an511``, ``mps2-an521``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, = ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 These board models all use Arm M-profile CPUs. =20 -The Arm MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger -FPGA but is otherwise the same as the 2). Since the CPU itself -and most of the devices are in the FPGA, the details of the board -as seen by the guest depend significantly on the FPGA image. +The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a +bigger FPGA but is otherwise the same as the 2; the 3 has a bigger +FPGA again, can handle 4GB of RAM and has a USB controller and QSPI flash). + +Since the CPU itself and most of the devices are in the FPGA, the +details of the board as seen by the guest depend significantly on the +FPGA image. =20 QEMU models the following FPGA images: =20 @@ -22,12 +25,21 @@ QEMU models the following FPGA images: Cortex-M3 'DesignStart' as documented in Arm Application Note AN511 ``mps2-an521`` Dual Cortex-M33 as documented in Arm Application Note AN521 +``mps3-an524`` + Dual Cortex-M33 on an MPS3, as documented in Arm Application Note AN524 =20 Differences between QEMU and real hardware: =20 - AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as if zbt_boot_ctrl is always zero) +- AN524 remapping of low memory to either BRAM or to QSPI flash is + unimplemented (QEMU always maps this to BRAM, ignoring the + SCC CFG_REG0 memory-remap bit) - QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest visible difference is that the LAN9118 doesn't support checksum offloading +- QEMU does not model the QSPI flash in MPS3 boards as real QSPI + flash, but only as simple ROM, so attempting to rewrite the flash + from the guest will fail +- QEMU does not model the USB controller in MPS3 boards --=20 2.20.1 From nobody Thu May 9 06:21:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613390852; cv=none; d=zohomail.com; s=zohoarc; b=fe0OU0bO56fAUClTLNNN6As3Lo+58BuPUBKDudpQEmPYpN9pFmigLsdbz/Kgxa1RDHzeIxjmuTIn/8yOe1F9vbBKqwLRGjhZD9p6FWOfKKhDaW6/grEKkRMRSR8K7eArySg9qVh3ukWkcwiqrKcGqobCBplLyzAQyZxs2d4qiwI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613390852; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=olyCqXlwgdAYPiStvMqcHJzP/susydF9jK1tL5ZtuZw=; b=cfwdGF/Iuap718eaOJ3tMcSvicmW5rg69j1f8oIR6RaDw06+57+L1V16x7gDmC/XC8AJk7D1cQ8nF9c5qulqdjbfOSSfmeKvHNnmChpwpAUbrUR7Y0E8WBnCttAOAYVLHo+QoGyPWs8xEGxavzd74sB4GkqlnUf7PCSyl770Uq0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613390852649457.1585577192627; Mon, 15 Feb 2021 04:07:32 -0800 (PST) Received: from localhost ([::1]:47550 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBcf5-0000Ky-DF for importer@patchew.org; Mon, 15 Feb 2021 07:07:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39926) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBcRO-0000U8-JR for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:53:22 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:46906) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBcRG-0004Kz-NQ for qemu-devel@nongnu.org; Mon, 15 Feb 2021 06:53:22 -0500 Received: by mail-wr1-x42a.google.com with SMTP id t15so8445218wrx.13 for ; Mon, 15 Feb 2021 03:53:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l83sm25574812wmf.4.2021.02.15.03.53.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 03:53:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=olyCqXlwgdAYPiStvMqcHJzP/susydF9jK1tL5ZtuZw=; b=RUrpppAz27ItZoUxpMweqNUA+M1ZBEep1ZQM02I4mf3YjvvIxXxYOXApsPDZMfhn9l dbnokCOUB3o1LPUetbAOZKa8aH0yBWbHvQRTJ6QP1cEf8H0ZOdj2/mkJ+t9Zb+u4iQZ0 ZozJHMAJZVvDN8xxE5k92u4NZvoPQiNi48WVYL5nv/6z8hchniGYVqOL0hPLcrSJg2JR UB+65i7IBA7uVyNlHnvMtizHgMMmbwrpOdlcmPdlz+QGNJCXiHoF7qiEmhBOlVEfAfSD XGyvrmJc3HxYdDUBFmp9PAF41FbtkctV9uB5kj9WNFJzdpjAc9SMu2lzhF+ZCFB6jCLf gQKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=olyCqXlwgdAYPiStvMqcHJzP/susydF9jK1tL5ZtuZw=; b=uBTnEuLK/yA0rxVxYEJEfVgbTBdQjfY23yxaMbwW4y1ktxlHy9J7musg9j2zZlV0ld pVBNxyOC+OZP7WejnGvXzLaLuZ8dhey8dwPD14+yHvMMfv03XQxNcExr0H1Q8Jd7Hd0t LJr5z0nDeamPjMx0WQ4Dtl4QXzCPKXnxgh8vfeItDhgFYU+GjC7XhCd45XZO8mkXsh5L TyYGT2gnPPnbFtkXVHsLLSvIRlbFbJEZY2K+OvuIxkNDKj+xIbhVwGXfYtJrrlo6cD9E zOkYELhbBTTGYbUxmBepENruihkmahLm3bLpPxzTdGAGRep8QQTwNcpmKKB2aLDOKJqm cLew== X-Gm-Message-State: AOAM532u9c3hqbg/2M48hirOWhqXeby2D2xNkJj+uszdzehyMO2UpsC/ QeiyPVD7Qtz9k2BHCvcka47Kiw== X-Google-Smtp-Source: ABdhPJyIL1ujDcUFtIvS8p51iYvDRj1C8dubSP0L2an/Xue7bwJXD34wrUpvptlRizh4+i2yNtAM9A== X-Received: by 2002:adf:b749:: with SMTP id n9mr18301985wre.267.1613389993300; Mon, 15 Feb 2021 03:53:13 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 24/24] hw/arm/mps2: Update old infocenter.arm.com URLs Date: Mon, 15 Feb 2021 11:51:38 +0000 Message-Id: <20210215115138.20465-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210215115138.20465-1-peter.maydell@linaro.org> References: <20210215115138.20465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Update old infocenter.arm.com URLs to the equivalent developer.arm.com ones (the old URLs should redirect, but we might as well avoid the redirection notice, and the new URLs are pleasantly shorter). This commit covers the links to the MPS2 board TRM, the various Application Notes, the IoTKit and SSE-200 documents. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- There are some other infocenter URLs in the codebase; we should probably update those too, but they don't really fit in with this patchset, so I'll do them separately later. Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/armsse.h | 4 ++-- include/hw/misc/armsse-cpuid.h | 2 +- include/hw/misc/armsse-mhu.h | 2 +- include/hw/misc/iotkit-secctl.h | 2 +- include/hw/misc/iotkit-sysctl.h | 2 +- include/hw/misc/iotkit-sysinfo.h | 2 +- include/hw/misc/mps2-fpgaio.h | 2 +- hw/arm/mps2-tz.c | 11 +++++------ hw/misc/armsse-cpuid.c | 2 +- hw/misc/armsse-mhu.c | 2 +- hw/misc/iotkit-sysctl.c | 2 +- hw/misc/iotkit-sysinfo.c | 2 +- hw/misc/mps2-fpgaio.c | 2 +- hw/misc/mps2-scc.c | 2 +- 14 files changed, 19 insertions(+), 20 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 676cd4f36b0..09284ca75cf 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -14,9 +14,9 @@ * hardware, which include the IoT Kit and the SSE-050, SSE-100 and * SSE-200. Currently we model: * - the Arm IoT Kit which is documented in - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm060125= 6/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * - the SSE-200 which is documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/core= link_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_0= 0_en.pdf + * https://developer.arm.com/documentation/101104/latest/ * * The IoTKit contains: * a Cortex-M33 diff --git a/include/hw/misc/armsse-cpuid.h b/include/hw/misc/armsse-cpuid.h index a61355e5161..9c0926322cb 100644 --- a/include/hw/misc/armsse-cpuid.h +++ b/include/hw/misc/armsse-cpuid.h @@ -12,7 +12,7 @@ /* * This is a model of the "CPU_IDENTITY" register block which is part of t= he * Arm SSE-200 and documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/core= link_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_0= 0_en.pdf + * https://developer.arm.com/documentation/101104/latest/ * * QEMU interface: * + QOM property "CPUID": the value to use for the CPUID register diff --git a/include/hw/misc/armsse-mhu.h b/include/hw/misc/armsse-mhu.h index 2671b5b978b..41925ded89b 100644 --- a/include/hw/misc/armsse-mhu.h +++ b/include/hw/misc/armsse-mhu.h @@ -12,7 +12,7 @@ /* * This is a model of the Message Handling Unit (MHU) which is part of the * Arm SSE-200 and documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/core= link_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_0= 0_en.pdf + * https://developer.arm.com/documentation/101104/latest/ * * QEMU interface: * + sysbus MMIO region 0: the system information register bank diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secct= l.h index 54c212b515c..227d44abe49 100644 --- a/include/hw/misc/iotkit-secctl.h +++ b/include/hw/misc/iotkit-secctl.h @@ -11,7 +11,7 @@ =20 /* This is a model of the security controller which is part of the * Arm IoT Kit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm060125= 6/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * * QEMU interface: * + sysbus MMIO region 0 is the "secure privilege control block" registe= rs diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysct= l.h index 2b5636b218c..2bc391138db 100644 --- a/include/hw/misc/iotkit-sysctl.h +++ b/include/hw/misc/iotkit-sysctl.h @@ -12,7 +12,7 @@ /* * This is a model of the "system control element" which is part of the * Arm IoTKit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm060125= 6/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * Specifically, it implements the "system information block" and * "system control register" blocks. * diff --git a/include/hw/misc/iotkit-sysinfo.h b/include/hw/misc/iotkit-sysi= nfo.h index 7e620e2eafe..055771d2098 100644 --- a/include/hw/misc/iotkit-sysinfo.h +++ b/include/hw/misc/iotkit-sysinfo.h @@ -12,7 +12,7 @@ /* * This is a model of the "system information block" which is part of the * Arm IoTKit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm060125= 6/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * QEMU interface: * + QOM property "SYS_VERSION": value to use for SYS_VERSION register * + QOM property "SYS_CONFIG": value to use for SYS_CONFIG register diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h index 0d3c8eef56c..e04fd590b63 100644 --- a/include/hw/misc/mps2-fpgaio.h +++ b/include/hw/misc/mps2-fpgaio.h @@ -12,7 +12,7 @@ /* This is a model of the FPGAIO register block in the AN505 * FPGA image for the MPS2 dev board; it is documented in the * application note: - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html + * https://developer.arm.com/documentation/dai0505/latest/ * * QEMU interface: * + sysbus MMIO region 0: the register bank diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 2c385422373..aca8efba6cf 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -23,21 +23,20 @@ * https://developer.arm.com/products/system-design/development-boards/fpg= a-prototyping-boards/mps2 * * Board TRM: - * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/vers= atile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_techni= cal_reference_100112_0200_06_en.pdf + * https://developer.arm.com/documentation/100112/latest/ * Application Note AN505: - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html + * https://developer.arm.com/documentation/dai0505/latest/ * Application Note AN521: - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html + * https://developer.arm.com/documentation/dai0521/latest/ * Application Note AN524: * https://developer.arm.com/documentation/dai0524/latest/ * * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Gu= ide * (ARM ECM0601256) for the details of some of the device layout: - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm0601= 256/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM def= ines * most of the device layout: - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/cor= elink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_= 00_en.pdf - * + * https://developer.arm.com/documentation/101104/latest/ */ =20 #include "qemu/osdep.h" diff --git a/hw/misc/armsse-cpuid.c b/hw/misc/armsse-cpuid.c index d58138dc28c..e785a090519 100644 --- a/hw/misc/armsse-cpuid.c +++ b/hw/misc/armsse-cpuid.c @@ -12,7 +12,7 @@ /* * This is a model of the "CPU_IDENTITY" register block which is part of t= he * Arm SSE-200 and documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/core= link_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_0= 0_en.pdf + * https://developer.arm.com/documentation/101104/latest/ * * It consists of one read-only CPUID register (set by QOM property), plus= the * usual ID registers. diff --git a/hw/misc/armsse-mhu.c b/hw/misc/armsse-mhu.c index a45d97fada8..0be7f0fc874 100644 --- a/hw/misc/armsse-mhu.c +++ b/hw/misc/armsse-mhu.c @@ -12,7 +12,7 @@ /* * This is a model of the Message Handling Unit (MHU) which is part of the * Arm SSE-200 and documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/core= link_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_0= 0_en.pdf + * https://developer.arm.com/documentation/101104/latest/ */ =20 #include "qemu/osdep.h" diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index 964b48c74d9..222511c4b04 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -12,7 +12,7 @@ /* * This is a model of the "system control element" which is part of the * Arm IoTKit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm060125= 6/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * Specifically, it implements the "system control register" blocks. */ =20 diff --git a/hw/misc/iotkit-sysinfo.c b/hw/misc/iotkit-sysinfo.c index b2dcfc4376c..52e70053df7 100644 --- a/hw/misc/iotkit-sysinfo.c +++ b/hw/misc/iotkit-sysinfo.c @@ -12,7 +12,7 @@ /* * This is a model of the "system information block" which is part of the * Arm IoTKit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm060125= 6/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * It consists of 2 read-only version/config registers, plus the * usual ID registers. */ diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c index acbd0be9f4b..76308543fcb 100644 --- a/hw/misc/mps2-fpgaio.c +++ b/hw/misc/mps2-fpgaio.c @@ -12,7 +12,7 @@ /* This is a model of the "FPGA system control and I/O" block found * in the AN505 FPGA image for the MPS2 devboard. * It is documented in AN505: - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html + * https://developer.arm.com/documentation/dai0505/latest/ */ =20 #include "qemu/osdep.h" diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index 562ace06a58..140a4b9ceba 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -13,7 +13,7 @@ * found in the FPGA images of MPS2 development boards. * * Documentation of it can be found in the MPS2 TRM: - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.100112_01= 00_03_en/index.html + * https://developer.arm.com/documentation/100112/latest/ * and also in the Application Notes documenting individual FPGA images. */ =20 --=20 2.20.1