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Rozycki" , Thomas Huth , Aurelien Jarno , Richard Henderson , Aleksandar Rikalo Subject: [RFC PATCH 21/42] target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word) Date: Sun, 14 Feb 2021 18:58:51 +0100 Message-Id: <20210214175912.732946-22-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce the PPACW opcode (Parallel Pack to Word). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tx79.decode | 1 + target/mips/tx79_translate.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 63fbe9694bb..653910371d2 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -38,6 +38,7 @@ PCGTH 011100 ..... ..... ..... 00110 001000 @= rs_rt_rd PSUBB 011100 ..... ..... ..... 01001 001000 @rs_rt_rd PCGTB 011100 ..... ..... ..... 01010 001000 @rs_rt_rd PEXTLW 011100 ..... ..... ..... 10010 001000 @rs_rt_rd +PPACW 011100 ..... ..... ..... 10011 001000 @rs_rt_rd PEXTLH 011100 ..... ..... ..... 10110 001000 @rs_rt_rd PEXTLB 011100 ..... ..... ..... 11010 001000 @rs_rt_rd =20 diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 04249b0c20a..ac75d95b82b 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -416,6 +416,36 @@ static bool trans_PCEQW(DisasContext *ctx, arg_rtype *= a) * PEXTLW rd, rs, rt Parallel Extend Lower from Word */ =20 +/* Parallel Pack to Word */ +static bool trans_PPACW(DisasContext *ctx, arg_rtype *a) +{ + TCGv_i64 a0, b0, t0; + + if (a->rd =3D=3D 0) { + /* nop */ + return true; + } + + a0 =3D tcg_temp_new_i64(); + b0 =3D tcg_temp_new_i64(); + t0 =3D tcg_temp_new_i64(); + + gen_load_gpr(a0, a->rs); + gen_load_gpr(b0, a->rt); + + gen_load_gpr_hi(t0, a->rt); /* b1 */ + tcg_gen_deposit_i64(cpu_gpr[a->rd], b0, t0, 32, 32); + + gen_load_gpr_hi(t0, a->rs); /* a1 */ + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], a0, t0, 32, 32); + + tcg_temp_free(t0); + tcg_temp_free(b0); + tcg_temp_free(a0); + + return true; +} + static bool trans_PEXTLx(DisasContext *ctx, arg_rtype *a, unsigned wlen) { TCGv_i64 ax, bx; --=20 2.26.2