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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id j40sm20223076wmp.47.2021.02.14.10.00.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:00:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MZnb2f0oqLbgB+c7ANHKvpi9xEka37HUd4LIx2gMYzU=; b=XbXD16rlF+fJtkdoQNBAXecczOqW93y7hSfOKJqIjZ9Euz4v8k0hvFsb/LLwDeICTC J6gzQjbhbPc4omLfRa0hWaEcTir7gM3s8SPwRu69B/2Bd2ETdLypfdwXWcWlRjw7i0kC 3Gd3y4CZPT6NdqVrx6MwSsf9GoXz2lxCI7gonUCyzO4dCI0vD/5Nc3zT+bjcP7gehCtM 6S8KI+KiDlDsWkX1a8JVYfH9/YfiLdJ/Pkn4vDhHa988SyEgYPjN81qaISVfGkI8Y9H7 YRXOGqdZ6BJWDNz37Vh72ed102koNUYXDKYJxnw5M6YQOGduL7cEYqF+XCJHC/Uues0S g1Zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=MZnb2f0oqLbgB+c7ANHKvpi9xEka37HUd4LIx2gMYzU=; b=jZFSN7qJ7daoFkkr4QWbLNHaDewKNUvRoaZ/vhwKiPvA8CsPEf4rbdUbZubJRStT2g aZLBtZeq9qe4oMTaHNppu741VHBXMm9Va6CdrCkzDVblJqJjGk7u6HR2r3UQASVULPux vnBR+0hgs5rf5Q6i6TE7KME2LM9U5nJfTAfg0uwEoFP7U1uNkftky+7sSlwhOFokRm7H IPNlcu+0xHcNyXWhxLUnUqYL5dFjCGA9yaJpo7igJuorbhqKY2Tr4TIYRk3evetcaD1c iV1FRsA1BlITSrTD9Yoq97hJP30Cu28E+NYn62XfBTS38DJ7D6lvWQFk/eqfsG4wZd5a A00g== X-Gm-Message-State: AOAM531b05Rbe6dL/pejwl565VVeiwoDuVqWM7e78U6prhjQVsTHc8i9 TlD5UV2wPL71xYyiXsABScI= X-Google-Smtp-Source: ABdhPJyXzF5oSjM736azj8MX/79+VOs0g5QWmjaQo/j5SeOh2JZE5X1U2UNofJ1rVeaED6dWk0oASQ== X-Received: by 2002:adf:8544:: with SMTP id 62mr15261450wrh.336.1613325649781; Sun, 14 Feb 2021 10:00:49 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Fredrik Noring , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Maciej W. Rozycki" , Thomas Huth , Aurelien Jarno , Richard Henderson , Aleksandar Rikalo Subject: [RFC PATCH 19/42] target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal) Date: Sun, 14 Feb 2021 18:58:49 +0100 Message-Id: <20210214175912.732946-20-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce the 'Parallel Compare for Equal' opcodes: - PCEQB (Parallel Compare for Equal Byte) - PCEQH (Parallel Compare for Equal Halfword) - PCEQW (Parallel Compare for Equal Word) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tx79.decode | 3 ++ target/mips/tx79_translate.c | 66 ++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 98f21d33e3f..cfe721755ca 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -40,6 +40,9 @@ PEXTLB 011100 ..... ..... ..... 11010 001000 @= rs_rt_rd =20 # MMI1 =20 +PCEQW 011100 ..... ..... ..... 00010 101000 @rs_rt_rd +PCEQH 011100 ..... ..... ..... 00110 101000 @rs_rt_rd +PCEQB 011100 ..... ..... ..... 01010 101000 @rs_rt_rd PEXTUW 011100 ..... ..... ..... 10010 101000 @rs_rt_rd =20 # MMI2 diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 11968d6edab..f084faa48a7 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -279,6 +279,72 @@ static bool trans_PNOR(DisasContext *ctx, arg_rtype *a) * PCEQW rd, rs, rt Parallel Compare for Equal Word */ =20 +static bool trans_parallel_compare(DisasContext *ctx, arg_rtype *a, + TCGCond cond, unsigned wlen) +{ + TCGv_i64 c0, c1, ax, bx, t0, t1, t2; + + if (a->rd =3D=3D 0) { + /* nop */ + return true; + } + + c0 =3D tcg_const_tl(0); + c1 =3D tcg_const_tl(0xffffffff); + ax =3D tcg_temp_new_i64(); + bx =3D tcg_temp_new_i64(); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + t2 =3D tcg_temp_new_i64(); + + /* Lower halve */ + gen_load_gpr(ax, a->rs); + gen_load_gpr(bx, a->rt); + for (int i =3D 0; i < (64 / wlen); i++) { + tcg_gen_sextract_i64(t0, ax, wlen * i, wlen); + tcg_gen_sextract_i64(t1, bx, wlen * i, wlen); + tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0); + tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], t2, wlen * i, = wlen); + } + /* Upper halve */ + gen_load_gpr_hi(ax, a->rs); + gen_load_gpr_hi(bx, a->rt); + for (int i =3D 0; i < (64 / wlen); i++) { + tcg_gen_sextract_i64(t0, ax, wlen * i, wlen); + tcg_gen_sextract_i64(t1, bx, wlen * i, wlen); + tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0); + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], t2, wlen= * i, wlen); + } + + tcg_temp_free(t2); + tcg_temp_free(t1); + tcg_temp_free(t0); + tcg_temp_free(bx); + tcg_temp_free(ax); + tcg_temp_free(c1); + tcg_temp_free(c0); + + return true; +} + +/* Parallel Compare for Equal Byte */ +static bool trans_PCEQB(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_compare(ctx, a, TCG_COND_EQ, 8); +} + +/* Parallel Compare for Equal Halfword */ +static bool trans_PCEQH(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_compare(ctx, a, TCG_COND_EQ, 16); +} + +/* Parallel Compare for Equal Word */ +static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_compare(ctx, a, TCG_COND_EQ, 32); +} + /* * LZC (1 instruction) * ------------------- --=20 2.26.2