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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id c62sm22338051wmd.43.2021.02.14.10.00.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:00:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FfRtrIVYgrZx8p+x3vP4XGNic7F4mMc3E9YYXBY0pFU=; b=o8WREhb4dKioU1pyB4M8/MK+ycuqhktIENWqKMDL3TIddaoRFYEnmIpL/hZTjiY7Lr nv5uR7FbLHouZe0wj+aUM6HsawirJQN52WM25AIaa7Q4KwgM3rL49hgxrqzfX2pYKAtu zmAkf0Ef/G0P4bR69BC5DZGhGh/vV/NaKSMRpoIDgZNtro4Ie2PpH0IPShQLwyKn4td6 Rj11lH9PAvQOfImte8KG96T8xKwNp/1gI48xluIYX1EE8rIGAPUeIjGbbMsm4tO9DTpu JTsi/URA5r1FncDuQAfFzVp+5oSMs9aDZeXAxG2KOxbqIq7HSd6OKvLkXZPogxNyxfti 1agw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=FfRtrIVYgrZx8p+x3vP4XGNic7F4mMc3E9YYXBY0pFU=; b=Ald+k2tq8DrWjB26unWzsjJGCq7zV8TGcL/Sgl7Y+BHYpcrN/nBP3/Fuz2ObMICNzI /WTbmbGuT9ZQHMoBn/NRQ+jZLlt/nTl7oAriu0EnFLVTm5yW83d3abh+NeGKbHO2Sqac 3x6t/4TjZt/nM/Fn/4BAobRjFO5PJihLu1+y8l666lAISN/xMQG+m48kyHQ2sC08xEG4 oVy1DRekIxPkUwOUjSbWq1hks+8TAgwpQq/ko+yM3v80LFr3pdmzcq9psdPuRB0MZyye e7IuwcPvllBCB9+l83BkOPosJkU9wFM/LacpEIX8ScpXr7jpxgEliMuMigR5LDgdq6l2 j4sQ== X-Gm-Message-State: AOAM530zz3Eqb8No0ftqDNHWXAKkjqqYfJgotZkv4Cv+rot/b9w+iB9t WVUx0PApjDIPkVVpU3pmCgg= X-Google-Smtp-Source: ABdhPJyIXTMd9O46RIT7MQPGfepw9iJJQEIELxVKW4OhecoTcCvUBoT8m/BJhEml5nvu+9z5PWr8/Q== X-Received: by 2002:adf:f941:: with SMTP id q1mr15161235wrr.189.1613325629787; Sun, 14 Feb 2021 10:00:29 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Fredrik Noring , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Maciej W. Rozycki" , Thomas Huth , Aurelien Jarno , Richard Henderson , Aleksandar Rikalo Subject: [RFC PATCH 15/42] target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic) Date: Sun, 14 Feb 2021 18:58:45 +0100 Message-Id: <20210214175912.732946-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce the parallel logic opcodes: - PAND (Parallel AND) - POR (Parallel OR) - PXOR (Parallel XOR) - PNOR (Parallel NOR) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tx79.decode | 4 +++ target/mips/tx79_translate.c | 54 ++++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 0f748b53a64..26c80b9bce5 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -32,8 +32,12 @@ MTLO1 011100 ..... 0000000000 00000 010011 = @rs # MMI2 =20 PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd +PAND 011100 ..... ..... ..... 10010 001001 @rs_rt_rd +PXOR 011100 ..... ..... ..... 10011 001001 @rs_rt_rd =20 # MMI3 =20 PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd +POR 011100 ..... ..... ..... 10010 101001 @rs_rt_rd +PNOR 011100 ..... ..... ..... 10011 101001 @rs_rt_rd PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 243a81c3c5e..28d07baaa73 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -2,6 +2,7 @@ * Toshiba TX79-specific instructions translation routines * * Copyright (c) 2018 Fredrik Noring + * Copyright (c) 2021 Philippe Mathieu-Daud=C3=A9 * * SPDX-License-Identifier: GPL-2.0-or-later */ @@ -139,6 +140,59 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *= a) * PNOR rd, rs, rt Parallel NOR */ =20 +static bool trans_parallel_logic(DisasContext *ctx, arg_rtype *a, + void (*gen_logic_i64)(TCGv_i64, TCGv_i64,= TCGv_i64)) +{ + TCGv_i64 ax, bx; + + if (a->rd =3D=3D 0) { + /* nop */ + return true; + } + + ax =3D tcg_temp_new_i64(); + bx =3D tcg_temp_new_i64(); + + /* Lower halve */ + gen_load_gpr(ax, a->rs); + gen_load_gpr(bx, a->rt); + gen_logic_i64(cpu_gpr[a->rd], ax, bx); + + /* Upper halve */ + gen_load_gpr_hi(ax, a->rs); + gen_load_gpr_hi(bx, a->rt); + gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx); + + tcg_temp_free(bx); + tcg_temp_free(ax); + + return true; +} + +/* Parallel And */ +static bool trans_PAND(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_logic(ctx, a, tcg_gen_and_i64); +} + +/* Parallel Or */ +static bool trans_POR(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_logic(ctx, a, tcg_gen_or_i64); +} + +/* Parallel Exclusive Or */ +static bool trans_PXOR(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_logic(ctx, a, tcg_gen_xor_i64); +} + +/* Parallel Not Or */ +static bool trans_PNOR(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_logic(ctx, a, tcg_gen_nor_i64); +} + /* * Shift (9 instructions) * ---------------------- --=20 2.26.2