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Rozycki" , Thomas Huth , Aurelien Jarno , Richard Henderson , Aleksandar Rikalo Subject: [RFC PATCH 12/42] target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree Date: Sun, 14 Feb 2021 18:58:42 +0100 Message-Id: <20210214175912.732946-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move PCPYLD (Parallel Copy Lower Doubleword) and PCPYUD (Parallel Copy Upper Doubleword) to decodetree. Remove unnecessary code / comments. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tx79.decode | 6 +++ target/mips/translate.c | 84 ------------------------------------ target/mips/tx79_translate.c | 46 ++++++++++++++++++++ 3 files changed, 52 insertions(+), 84 deletions(-) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 7af35458b0a..0f748b53a64 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -17,6 +17,7 @@ # Named instruction formats. These are generally used to # reduce the amount of duplication between instruction patterns. =20 +@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &rtype sa=3D0 @rt_rd ...... ..... rt:5 rd:5 ..... ...... &rtype rs=3D0 sa= =3D0 @rs ...... rs:5 ..... .......... ...... &rtype rt=3D0 rd= =3D0 sa=3D0 @rd ...... .......... rd:5 ..... ...... &rtype rs=3D0 rt= =3D0 sa=3D0 @@ -28,6 +29,11 @@ MTHI1 011100 ..... 0000000000 00000 010001 = @rs MFLO1 011100 0000000000 ..... 00000 010010 @rd MTLO1 011100 ..... 0000000000 00000 010011 @rs =20 +# MMI2 + +PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd + # MMI3 =20 +PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd diff --git a/target/mips/translate.c b/target/mips/translate.c index b81a66ed373..cf5a6a83ae5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24733,84 +24733,6 @@ static void decode_opc_special(CPUMIPSState *env, = DisasContext *ctx) * PEXTUW */ =20 -/* - * PCPYLD rd, rs, rt - * - * Parallel Copy Lower Doubleword - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---------+---------+-----------+ - * | MMI | rs | rt | rd | PCPYLD | MMI2 | - * +-----------+---------+---------+---------+---------+-----------+ - */ -static void gen_mmi_pcpyld(DisasContext *ctx) -{ - uint32_t rs, rt, rd; - uint32_t opcode; - - opcode =3D ctx->opcode; - - rs =3D extract32(opcode, 21, 5); - rt =3D extract32(opcode, 16, 5); - rd =3D extract32(opcode, 11, 5); - - if (rd =3D=3D 0) { - /* nop */ - } else { - if (rs =3D=3D 0) { - tcg_gen_movi_i64(cpu_gpr_hi[rd], 0); - } else { - tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr[rs]); - } - if (rt =3D=3D 0) { - tcg_gen_movi_i64(cpu_gpr[rd], 0); - } else { - if (rd !=3D rt) { - tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr[rt]); - } - } - } -} - -/* - * PCPYUD rd, rs, rt - * - * Parallel Copy Upper Doubleword - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---------+---------+-----------+ - * | MMI | rs | rt | rd | PCPYUD | MMI3 | - * +-----------+---------+---------+---------+---------+-----------+ - */ -static void gen_mmi_pcpyud(DisasContext *ctx) -{ - uint32_t rs, rt, rd; - uint32_t opcode; - - opcode =3D ctx->opcode; - - rs =3D extract32(opcode, 21, 5); - rt =3D extract32(opcode, 16, 5); - rd =3D extract32(opcode, 11, 5); - - if (rd =3D=3D 0) { - /* nop */ - } else { - if (rs =3D=3D 0) { - tcg_gen_movi_i64(cpu_gpr[rd], 0); - } else { - tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr_hi[rs]); - } - if (rt =3D=3D 0) { - tcg_gen_movi_i64(cpu_gpr_hi[rd], 0); - } else { - if (rd !=3D rt) { - tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt]); - } - } - } -} - #endif =20 =20 @@ -27859,9 +27781,6 @@ static void decode_mmi2(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI2 */ break; - case MMI_OPC_2_PCPYLD: - gen_mmi_pcpyld(ctx); - break; default: MIPS_INVAL("TX79 MMI class MMI2"); gen_reserved_instruction(ctx); @@ -27887,9 +27806,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */ break; - case MMI_OPC_3_PCPYUD: - gen_mmi_pcpyud(ctx); - break; default: MIPS_INVAL("TX79 MMI class MMI3"); gen_reserved_instruction(ctx); diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index d58b4fcd7b3..de09bb0d314 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -71,3 +71,49 @@ static bool trans_PCPYH(DisasContext *s, arg_rtype *a) =20 return true; } + +/* Parallel Copy Lower Doubleword */ +static bool trans_PCPYLD(DisasContext *s, arg_rtype *a) +{ + if (a->rd =3D=3D 0) { + /* nop */ + return true; + } + + if (a->rs =3D=3D 0) { + tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); + } else { + tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr[a->rs]); + } + + if (a->rt =3D=3D 0) { + tcg_gen_movi_i64(cpu_gpr[a->rd], 0); + } else if (a->rd !=3D a->rt) { + tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]); + } + + return true; +} + +/* Parallel Copy Upper Doubleword */ +static bool trans_PCPYUD(DisasContext *s, arg_rtype *a) +{ + if (a->rd =3D=3D 0) { + /* nop */ + return true; + } + + if (a->rs =3D=3D 0) { + tcg_gen_movi_i64(cpu_gpr[a->rd], 0); + } else { + tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr_hi[a->rs]); + } + + if (a->rt =3D=3D 0) { + tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); + } else if (a->rd !=3D a->rt) { + tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt]); + } + + return true; +} --=20 2.26.2