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Rozycki" , Thomas Huth , Aurelien Jarno , Richard Henderson , Aleksandar Rikalo Subject: [RFC PATCH 11/42] target/mips/tx79: Move PCPYH opcode to decodetree Date: Sun, 14 Feb 2021 18:58:41 +0100 Message-Id: <20210214175912.732946-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move the existing PCPYH opcode (Parallel Copy Halfword) to decodetree. Remove unnecessary code / comments. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tx79.decode | 5 +++++ target/mips/translate.c | 39 ------------------------------------ target/mips/tx79_translate.c | 22 ++++++++++++++++++++ 3 files changed, 27 insertions(+), 39 deletions(-) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 30737da54e4..7af35458b0a 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -17,6 +17,7 @@ # Named instruction formats. These are generally used to # reduce the amount of duplication between instruction patterns. =20 +@rt_rd ...... ..... rt:5 rd:5 ..... ...... &rtype rs=3D0 sa= =3D0 @rs ...... rs:5 ..... .......... ...... &rtype rt=3D0 rd= =3D0 sa=3D0 @rd ...... .......... rd:5 ..... ...... &rtype rs=3D0 rt= =3D0 sa=3D0 =20 @@ -26,3 +27,7 @@ MFHI1 011100 0000000000 ..... 00000 010000 @= rd MTHI1 011100 ..... 0000000000 00000 010001 @rs MFLO1 011100 0000000000 ..... 00000 010010 @rd MTLO1 011100 ..... 0000000000 00000 010011 @rs + +# MMI3 + +PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd diff --git a/target/mips/translate.c b/target/mips/translate.c index a13ad4959b4..b81a66ed373 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24733,42 +24733,6 @@ static void decode_opc_special(CPUMIPSState *env, = DisasContext *ctx) * PEXTUW */ =20 -/* - * PCPYH rd, rt - * - * Parallel Copy Halfword - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---------+---------+-----------+ - * | MMI |0 0 0 0 0| rt | rd | PCPYH | MMI3 | - * +-----------+---------+---------+---------+---------+-----------+ - */ -static void gen_mmi_pcpyh(DisasContext *ctx) -{ - uint32_t pd, rt, rd; - uint32_t opcode; - - opcode =3D ctx->opcode; - - pd =3D extract32(opcode, 21, 5); - rt =3D extract32(opcode, 16, 5); - rd =3D extract32(opcode, 11, 5); - - if (unlikely(pd !=3D 0)) { - gen_reserved_instruction(ctx); - } else if (rd =3D=3D 0) { - /* nop */ - } else if (rt =3D=3D 0) { - tcg_gen_movi_i64(cpu_gpr[rd], 0); - tcg_gen_movi_i64(cpu_gpr_hi[rd], 0); - } else { - tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rt], cpu_gpr[rt], 16, 16); - tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rd], cpu_gpr[rd], 32, 32); - tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt], cpu_gpr_hi[rt]= , 16, 16); - tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rd], cpu_gpr_hi[rd]= , 32, 32); - } -} - /* * PCPYLD rd, rs, rt * @@ -27923,9 +27887,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */ break; - case MMI_OPC_3_PCPYH: - gen_mmi_pcpyh(ctx); - break; case MMI_OPC_3_PCPYUD: gen_mmi_pcpyud(ctx); break; diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 905245cece7..d58b4fcd7b3 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -49,3 +49,25 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) =20 return true; } + +/* Parallel Copy Halfword */ +static bool trans_PCPYH(DisasContext *s, arg_rtype *a) +{ + if (a->rd =3D=3D 0) { + /* nop */ + return true; + } + + if (a->rt =3D=3D 0) { + tcg_gen_movi_i64(cpu_gpr[a->rd], 0); + tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); + return true; + } + + tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], cpu_gpr[a->rt], 16= , 16); + tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], cpu_gpr[a->rd], 32= , 32); + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt], cpu_gpr_hi[a= ->rt], 16, 16); + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], cpu_gpr_hi[a= ->rd], 32, 32); + + return true; +} --=20 2.26.2