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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico From: Alessandro Di Federico via X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Alessandro Di Federico Signed-off-by: Alessandro Di Federico --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 41300089b2..029f96d3bc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -192,11 +192,19 @@ Hexagon TCG CPUs M: Taylor Simpson S: Supported F: target/hexagon/ +X: target/hexagon/idef-parser/ +X: target/hexagon/gen_idef_parser_funcs.py F: linux-user/hexagon/ F: tests/tcg/hexagon/ F: disas/hexagon.c F: default-configs/targets/hexagon-linux-user.mak =20 +Hexagon idef-parser +M: Alessandro Di Federico +S: Supported +F: target/hexagon/idef-parser/ +F: target/hexagon/gen_idef_parser_funcs.py + HPPA (PA-RISC) TCG CPUs M: Richard Henderson S: Maintained --=20 2.30.0 From nobody Tue Nov 18 22:49:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 11 Feb 2021 16:51:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=PrQvs7feTJwA8x9Ow1az/xCuoCSwjnvwgIdwqqeMa0E=; b=SMnAL98pimfcUVSwhAq//CeX1B Od240SGbRxEQflBvdhDUwz/5xFBlDtK4R1MelYYY0QeXEcDaGvm2nONTVPAusM6OGSJTjulfCjJ8B NUl4gxa0rk2/jBE3OiUBpDZtiIBcx+Ov1+5eEeB1eGDI2dophf/dART1qdpSkueZWguw=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, Alessandro Di Federico Subject: [RFC PATCH 02/10] target/hexagon: import README for idef-parser Date: Thu, 11 Feb 2021 22:50:43 +0100 Message-Id: <20210211215051.2102435-3-ale.qemu@rev.ng> In-Reply-To: <20210211215051.2102435-1-ale.qemu@rev.ng> References: <20210211215051.2102435-1-ale.qemu@rev.ng> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico From: Alessandro Di Federico via X-ZohoMail-DKIM: fail (Header signature does not verify) From: Alessandro Di Federico Signed-off-by: Alessandro Di Federico --- target/hexagon/README | 5 + target/hexagon/idef-parser/README.rst | 446 ++++++++++++++++++++++++++ 2 files changed, 451 insertions(+) create mode 100644 target/hexagon/idef-parser/README.rst diff --git a/target/hexagon/README b/target/hexagon/README index b0b2435070..2f2814380c 100644 --- a/target/hexagon/README +++ b/target/hexagon/README @@ -23,6 +23,10 @@ Hexagon-specific code are encode*.def Encoding patterns for each instruction iclass.def Instruction class definitions used to dete= rmine legal VLIW slots for each instruction + qemu/target/hexagon/idef-parser + Parser that, given the high-level definitions of an instruction, + produces a C function generating equivalent tiny code instructions. + See README.rst. qemu/linux-user/hexagon Helpers for loading the ELF file and making Linux system calls, signals, etc @@ -43,6 +47,7 @@ header files in /target/hexagon gen_tcg_funcs.py -> tcg_funcs_generated.c.inc gen_tcg_func_table.py -> tcg_func_table_generated.c.inc gen_helper_funcs.py -> helper_funcs_generated.c.inc + gen_idef_parser_funcs.py -> idef_parser_input.h =20 Qemu helper functions have 3 parts DEF_HELPER declaration indicates the signature of the helper diff --git a/target/hexagon/idef-parser/README.rst b/target/hexagon/idef-pa= rser/README.rst new file mode 100644 index 0000000000..b02f52800a --- /dev/null +++ b/target/hexagon/idef-parser/README.rst @@ -0,0 +1,446 @@ +Hexagon ISA instruction definitions to tinycode generator compiler +------------------------------------------------------------------ + +idef-parser is a small compiler able to translate the Hexagon ISA descript= ion +language into tinycode generator code, that can be easily integrated into = QEMU. + +Compilation Example +------------------- + +To better understand the scope of the idef-parser, we'll explore an applic= ative +example. Let's start by one of the simplest Hexagon instruction: the ``add= ``. + +The ISA description language represents the ``add`` instruction as +follows: + +.. code:: c + + A2_add(RdV, in RsV, in RtV) { + { RdV=3DRsV+RtV;} + } + +idef-parser will compile the above code into the following code: + +.. code:: c + + /* A2_add */ + void emit_A2_add(DisasContext *ctx, Insn *insn, Packet *pkt, TCGv_i32 R= dV, + TCGv_i32 RsV, TCGv_i32 RtV) + /* { RdV=3DRsV+RtV;} */ + { + tcg_gen_movi_i32(RdV, 0); + TCGv_i32 tmp_0 =3D tcg_temp_new_i32(); + tcg_gen_add_i32(tmp_0, RsV, RtV); + tcg_gen_mov_i32(RdV, tmp_0); + tcg_temp_free_i32(tmp_0); + } + +The output of the compilation process will be a function, containing the +tinycode generator code, implementing the correct semantics. That function= will +not access any global variable, because all the accessed data structures w= ill be +passed explicitly as function parameters. Among the passed parameters we w= ill +have TCGv (tinycode variables) representing the input and output registers= of +the architecture, integers representing the immediates that come from the = code, +and other data structures which hold information about the disassemblation +context (``DisasContext`` struct). + +Let's begin by describing the input code. The ``add`` instruction is assoc= iated +with a unique identifier, in this case ``A2_add``, which allows to disting= uish +variants of the same instruction, and expresses the class to which the +instruction belongs, in this case ``A2`` corresponds to the Hexagon +``ALU32/ALU`` instruction subclass. + +After the instruction identifier, we have a series of parameters that repr= esents +TCG variables that will be passed to the generated function. Parameters ma= rked +with ``in`` are already initialized, while the others are output parameter= s. + +We will leverage this information to infer several information: + +- Fill in the output function signature with the correct TCGv registers +- Fill in the output function signature with the immediate integers +- Keep track of which registers, among the declared one, have been + initialized + +Let's now observe the actual instruction description code, in this case: + +.. code:: c + + { RdV=3DRsV+RtV;} + +This code is composed by a subset of the C syntax, and is the result of the +application of some macro definitions contained in the ``macros.h`` file. + +This file is used to reduce the complexity of the input language where com= plex +variants of similar constructs can be mapped to a unique primitive, so tha= t the +idef-parser has to handle a lower number of computation primitives. + +As you may notice, the description code modifies the registers which have = been +declared by the declaration statements. In this case all the three registe= rs +will be declared, ``RsV`` and ``RtV`` will also be read and ``RdV`` will be +written. + +Now let's have a quick look at the generated code, line by line. + +:: + + tcg_gen_movi_i32(RdV, 0); + +This code starts by initializing ``RdV``, since reading from that register +without initialization will cause a segmentation fault by QEMU. This is e= mitted +because a declaration of the ``RdV`` register was parsed, but no reading o= f the +``RdV`` register was found. + +:: + + TCGv_i32 tmp_0 =3D tcg_temp_new_i32(); + +Then we are declaring a temporary TCGv to hold the result from the sum +operation. + +:: + + tcg_gen_add_i32(tmp_0, RsV, RtV); + +Now we are actually generating the sum tinycode operator between the selec= ted +registers, storing the result in the just declared temporary. + +:: + + tcg_gen_mov_i32(RdV, tmp_0); + +The result of the addition is now stored in the temporary, we move it into= the +correct destination register. This might not seem an efficient code, but Q= EMU +will perform some tinycode optimization, reducing the unnecessary copy. + +:: + + tcg_temp_free_i32(tmp_0); + +Finally, we free the temporary we used to hold the addition result. + +Parser Structure +---------------- + +The idef-parser is built using the ``flex`` and ``bison``. + +``flex`` is used to split the input string into tokens, each described usi= ng a +regular expression. The token description is contained in the ``idef-lexer= .lex`` +source file. The flex-generated scanner takes care also to extract from the +input text other meaningful information, e.g.,=C2=A0the numerical value in= case of an +immediate constant, and decorates the token with the extracted information. + +``bison`` is used to generate the actual parser, starting from the parsing +description contained in the ``idef-parser.y`` file. The generated parser +executes the ``main`` function at the end of the ``idef-parser.y`` file, w= hich +opens input and output files, creates the parsing context, and eventually = calls +the ``yyparse()`` function, which starts the execution of the LALR(1) pars= er +(see `Wikipedia `__ for more +information about LALR parsing techniques). The LALR(1) parser, whenever i= t has +to shift a token, calls the ``yylex()`` function, which is defined by the +flex-generated code, and reads the input file returning the next scanned t= oken. + +The tokens are mapped on the source language grammar, defined in the +``idef-parser.y`` file to build a unique syntactic tree, according to the +specified operator precedences and associativity rules. + +The grammar describes the whole file which contains the Hexagon instruction +descriptions, therefore it starts from the ``input`` nonterminal, which is= a +list of instructions, each instruction is represented by the following gra= mmar +rule, representing the structure of the input file shown above: + +:: + + instruction : INAME code + + code : LBR decls statements decls RBR + + statements : statements statement + | statement + + statement : control_statement + | rvalue SEMI + | code_block + | SEMI + + code_block : LBR statements RBR + | LBR RBR + +With this initial portion of the grammar we are defining the instruction +statements, which are enclosed by the declarations. Each statement can be a +``control_statement``, a code block, which is just a bracket-enclosed list= of +statements, a ``SEMI``, which is a ``nop`` instruction, and an ``rvalue SE= MI``. + +Expressions +~~~~~~~~~~~ + +``rvalue`` is the nonterminal representing expressions, which are everythi= ng +that could be assigned to a variable. ``rvalue SEMI`` can be a statement o= n its +own because the assign statement, just as in the C language, is itself an +expression. + +``rvalue``\ s can be registers, immediates, predicates, control registers, +variables, or any combination of other ``rvalue``\ s through operators. An +``rvalue`` can be either an immediate or a TCGv, the actual type is determ= ined +by the ``t_hex_value.type`` field. In case it is an immediate, its combina= tion +with other immediates can be performed at compile-time (constant folding),= only +the result will be written into the code. If the ``rvalue`` instead is a T= CGv, +the operations performed on it will have to be emitted as tinycode instruc= tions, +therefore their result will be known only at runtime. An immediate can be = copied +into a TCGv through the ``rvalue_materialize`` function, which allocates a +temporary TCGv and copies the value of the immediate in it. Each temporary +should be freed after that it is no more used, we usually free both operan= ds of +each operator, in an SSA fashion. + +``lvalue``\ s instead represents all the variables which can be assigned t= o a +value, and are specialized into registers and variables: + +:: + + lvalue : REG + | VAR + +The effective assignment of ``lvalue``\ s is handled by the ``gen_assign()= `` +function. + +Automatic Variables +~~~~~~~~~~~~~~~~~~~ + +The input code can contain implicitly declared automatic variables, which = are +initialized with a value and then used. We performed a dedicated handling = of +such variables, because they will be matched by a generic ``VARID`` token,= which +will feature the variable name as a decoration. Each time that the variabl= e is +found, we have to check if that's the first variable use, in that case we +declare a new automatic variable in the tinycode, which can be considered = at all +effects as an immediate. Special care is taken to make sure that each vari= able +is declared only the first time it is seen. Furthermore the variable might +inherit some characteristics like the signedness and the bit width, which = must +be propagated from the initialization of the variable to all the further u= ses of +the variable. + +The combination of ``rvalue``\ s are handled through the use of the +``gen_bin_op`` and ``gen_bin_cmp`` helper functions. These two functions h= andle +the appropriate compile-time or run-time emission of operations to perform= the +required computation. + +Type System +~~~~~~~~~~~ + +idef-parser features a simple type system which is used to correctly imple= ment +the signedness and bit width of the operations. + +The type of each ``rvalue`` is determined by two attributes: its bit width +(``unsigned bit_width``) and its signedness (``bool is_unsigned``). + +For each operation, the type of ``rvalue``\ s influence the way in which t= he +operands are handled and emitted. For example a right shift between signed +operators will be an algebraic shift, while one between unsigned operators= will +be a logical shift. If one of the two operands is signed, and the other is +unsigned, the operation will be signed. + +The bit width also influences the outcome of the operations, in particular= while +the input languages features a fine granularity type system, with types of= 8, +16, 32, 64 (and more for vectorial instructions) bits, the tinycode only +features 32 and 64 bit widths. We propagate as much as possible the fine +granularity type, until the value has to be used inside an operation betwe= en +``rvalue``\ s; in that case if one of the two operands is greater than 32 = bits +we promote the whole operation to 64 bit, taking care of properly extendin= g the +two operands. Fortunately, the most critical instructions already feature +explicit casts and zero/sign extensions which are properly propagated down= to +our parser. + +Control Statements +~~~~~~~~~~~~~~~~~~ + +``control_statement``\ s are all the statements which modify the order of +execution of the generated code according to input parameters. They are ex= panded +by the following grammar rule: + +:: + + control_statement : frame_check + | cancel_statement + | if_statement + | for_statement + | fpart1_statement + +``if_statement``\ s require the emission of labels and branch instructions= which +effectively perform conditional jumps (``tcg_gen_brcondi``) according to t= he +value of an expression. All the predicated instructions, and in general al= l the +instructions where there could be alternative values assigned to an ``lval= ue``, +like C-style ternary expressions: + +:: + + rvalue : rvalue QMARK rvalue COLON rvalue + +Are handled using the conditional move tinycode instruction +(``tcg_gen_movcond``), which avoids the additional complexity of managing = labels +and jumps. + +Instead, regarding the ``for`` loops, exploiting the fact that they always +iterate on immediate values, therefore their iteration ranges are always k= nown +at compile time, we implemented those emitting plain C ``for`` loops. This= is +possible because the loops will be executed in the QEMU code, leading to t= he +consequential unrolling of the for loop, since the tinycode generator +instructions will be executed multiple times, and the respective generated +tinycode will represent the unrolled execution of the loop. + +Parsing Context +~~~~~~~~~~~~~~~ + +All the helper functions in ``idef-parser.y`` carry two fixed parameters, = which +are the parsing context ``c`` and the ``YYLLOC`` location information. The +context is explicitly passed to all the functions because the parser we ge= nerate +is a reentrant one, meaning that it does not have any global variable, and +therefore the instruction compilation could easily be parallelized in the +future. Finally for each rule we propagate information about the location = of the +involved tokens to generate a pretty error reporting, able to highlight the +portion of the input code which generated each error. + +Debugging +--------- + +Developing the idef-parser can lead to two types of errors: compile-time e= rrors +and parsing errors. + +Compile-time errors in Bison-generated parsers are usually due to conflict= s in +the described grammar. Conflicts forbid the grammar to produce a unique +derivation tree, thus must be solved (except for the dangling else problem, +which is marked as expected through the ``%expect 1`` Bison option). + +For solving conflicts you need a basic understanding of `shift-reduce conf= licts +`__ +and `reduce-reduce conflicts +`__, +then, if you are using a Bison version > 3.7.1 you can ask Bison to genera= te +some counterexamples which highlight ambiguous derivations, passing the +``-Wcex`` option to Bison. In general shift/reduce conflicts are solved by +redesigning the grammar in an unambiguous way or by setting the token prio= rity +correctly, while reduce/reduce conflicts are solved by redesigning the +interested part of the grammar. + +Run-time errors can be divided between lexing and parsing errors, lexing e= rrors +are hard to detect, since the ``VAR`` token will catch everything which is= not +catched by other tokens, but easy to fix, because most of the time a simple +regex editing will be enough. + +idef-parser features a fancy parsing error reporting scheme, which for each +parsing error reports the fragment of the input text which was involved in= the +parsing rule that generated an error. + +Implementing an instruction goes through several sequential steps, here ar= e some +suggestions to make each instruction proceed to the next step. + +- not-emitted + + Means that the parsing of the input code relative to that instruction f= ailed, + this could be due to a lexical error or to some mismatch between the or= der of + valid tokens and a parser rule. You should check that tokens are correc= tly + identified and mapped, and that there is a rule matching the token sequ= ence + that you need to parse. + +- emitted + + This instruction class contains all the instruction which are emitted b= ut + fail to compile when included in QEMU. The compilation errors are shown= by + the QEMU building process and will lead to fixing the bug. Most common + errors regard the mismatch of parameters for tinycode generator functio= ns, + which boil down to errors in the idef-parser type system. + +- compiled + + These instruction generate valid tinycode generator code, which however= fail + the QEMU or the harness tests, these cases must be handled manually by + looking into the failing tests and looking at the generated tinycode + generator instruction and at the generated tinycode itself. Tip: handle= the + failing harness tests first, because they usually feature only a single + instruction, thus will require less execution trace navigation. If a + multi-threaded test fail, fixing all the other tests will be the easier + option, hoping that the multi-threaded one will be indirectly fixed. + +- tests-passed + + This is the final goal for each instruction, meaning that the instructi= on + passes the test suite. + +Another approach to fix QEMU system test, where many instructions might fa= il, is +to compare the execution trace of your implementation with the reference +implementations already present in QEMU. To do so you should obtain a QEMU= build +where the instruction pass the test, and run it with the following command: + +:: + + sudo unshare -p sudo -u bash -c \ + 'env -i -d cpu ' + +And do the same for your implementation, the generated execution traces wi= ll be +inherently aligned and can be inspected for behavioral differences using t= he +``diff`` tool. + +Limitations and Future Development +---------------------------------- + +The main limitation of the current parser is given by the syntax-driven na= ture +of the Bison-generated parsers. This has the severe implication of only be= ing +able to generate code in the order of evaluation of the various rules, wit= hout, +in any case, being able to backtrack and alter the generated code. + +An example limitation is highlighted by this statement of the input langua= ge: + +:: + + { (PsV=3D=3D0xff) ? (PdV=3D0xff) : (PdV=3D0x00); } + +This ternary assignment, when written in this form requires us to emit some +proper control flow statements, which emit a jump to the first or to the s= econd +code block, whose implementation is extremely convoluted, because when mat= ching +the ternary assignment, the code evaluating the two assignments will be al= ready +generated. + +Instead we pre-process that statement, making it become: + +:: + + { PdV =3D ((PsV=3D=3D0xff)) ? 0xff : 0x00; } + +Which can be easily matched by the following parser rules: + +:: + + statement | rvalue SEMI + + rvalue : rvalue QMARK rvalue COLON rvalue + | rvalue EQ rvalue + | LPAR rvalue RPAR + | assign_statement + | IMM + + assign_statement : pre ASSIGN rvalue + +Another example that highlight the limitation of the flex/bison parser can= be +found even in the add operation we already saw: + +:: + + TCGv_i32 tmp_0 =3D tcg_temp_new_i32(); + tcg_gen_add_i32(tmp_0, RsV, RtV); + tcg_gen_mov_i32(RdV, tmp_0); + +The fact that we cannot directly use ``RdV`` as the destination of the sum= is a +consequence of the syntax-driven nature of the parser. In fact when we par= se the +assignment, the ``rvalue`` token, representing the sum has already been re= duced, +and thus its code emitted and unchangeable. We rely on the fact that QEMU = will +optimize our code reducing the useless move operations and the relative +temporaries. + +A possible improvement of the parser regards the support for vectorial +instructions and floating point instructions, which will require the exten= sion +of the scanner, the parser, and a partial re-design of the type system, al= lowing +to build the vectorial semantics over the available vectorial tinycode gen= erator +primitives. + +A more radical improvement will use the parser, not to generate directly t= he +tinycode generator code, but to generate an intermediate representation li= ke the +LLVM IR, which in turn could be compiled using the clang TCG backend. That= code +could be furtherly optimized, overcoming the limitations of the syntax-dri= ven +parsing and could lead to a more optimized generated code. --=20 2.30.0 From nobody Tue Nov 18 22:49:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1613080768; cv=none; d=zohomail.com; s=zohoarc; b=DfLt9BXjClbpHp6bmCIYmzXVCQ+9IOnmVtrKw2Kgil0RRhKwC/dzcESXkGy1GAb0n1iasQuKmzfhks6KO07He8Xi2bUvVToylVw+mkGatNqSkTIjCyPGbK61oEiDfmlAL7N0zfja4LWtVwy267iq0+CVD3TaHXwvyHL03Bn1TSY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613080768; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=bBcCGiswERXa5Tk9w/hGfDdFM7clZn/Igf7apyC7TK0=; b=Qb5QPkvzPXhFVzB0TuZbnTsjGUHmCg9KMNJtssXbcnElgo/MZo6rMPwu/W9Q0wr7TnYfevrBIV4Nah3LMu2SUmBcjUq80LedELNvduRH/LVpNVSyxUisMDdYaDWRE8/Y7XsrATmk1NrToga4TEEcWH1M/3tZ7QFv8i2OvWX0+Ns= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613080768498800.8178019442205; Thu, 11 Feb 2021 13:59:28 -0800 (PST) Received: from localhost ([::1]:39756 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lAJzi-00069x-Cs for importer@patchew.org; Thu, 11 Feb 2021 16:59:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57100) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lAJrt-0006Xp-Lf for qemu-devel@nongnu.org; Thu, 11 Feb 2021 16:51:21 -0500 Received: from rev.ng ([5.9.113.41]:46593) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lAJrg-00010X-ES for qemu-devel@nongnu.org; Thu, 11 Feb 2021 16:51:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=bBcCGiswERXa5Tk9w/hGfDdFM7clZn/Igf7apyC7TK0=; b=BzkSXJf5an7j/5jDwUfQ/uDrkc hThNfIw9sOFhvVMPdmeJi6o+83QCGlShc8idgiIFprACm96J8sp9yVTFJQNUUxkGqh1SuPKiaM+9M t1K46vcRle4dI4X5X5DXvEwY7eq3Vvps6Dd0Ku9fPpkG1szzel9FgkI0kDeNXI9K4dC4=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, Alessandro Di Federico Subject: [RFC PATCH 03/10] target/hexagon: make helper functions non-static Date: Thu, 11 Feb 2021 22:50:44 +0100 Message-Id: <20210211215051.2102435-4-ale.qemu@rev.ng> In-Reply-To: <20210211215051.2102435-1-ale.qemu@rev.ng> References: <20210211215051.2102435-1-ale.qemu@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico From: Alessandro Di Federico via X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Paolo Montesel Move certain helper functions required by code generated by the idef-parser available outside genptr.c, moving them into macros.h. This patch also introduces the gen_cancel and gen_fbrev helper which will be used by idef-parser. Signed-off-by: Alessandro Di Federico Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/hexagon/genptr.c | 13 ++++++++++--- target/hexagon/genptr.h | 7 +++++++ 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 7481f4c1dd..97de669f38 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -26,8 +26,15 @@ #include "translate.h" #include "macros.h" #include "gen_tcg.h" +#include "genptr.h" =20 -static inline TCGv gen_read_preg(TCGv pred, uint8_t num) +TCGv gen_read_reg(TCGv result, int num) +{ + tcg_gen_mov_tl(result, hex_gpr[num]); + return result; +} + +TCGv gen_read_preg(TCGv pred, uint8_t num) { tcg_gen_mov_tl(pred, hex_pred[num]); return pred; @@ -53,7 +60,7 @@ static inline void gen_log_predicated_reg_write(int rnum,= TCGv val, int slot) tcg_temp_free(slot_mask); } =20 -static inline void gen_log_reg_write(int rnum, TCGv val) +void gen_log_reg_write(int rnum, TCGv val) { tcg_gen_mov_tl(hex_new_value[rnum], val); #if HEX_DEBUG @@ -116,7 +123,7 @@ static void gen_log_reg_write_pair(int rnum, TCGv_i64 v= al) #endif } =20 -static inline void gen_log_pred_write(int pnum, TCGv val) +void gen_log_pred_write(int pnum, TCGv val) { TCGv zero =3D tcg_const_tl(0); TCGv base_val =3D tcg_temp_new(); diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index c158005d2a..0bfa99b463 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -19,7 +19,14 @@ #define HEXAGON_GENPTR_H =20 #include "insn.h" +#include "tcg/tcg.h" +#include "translate.h" =20 extern const SemanticInsn opcode_genptr[]; =20 +TCGv gen_read_reg(TCGv result, int num); +TCGv gen_read_preg(TCGv pred, uint8_t num); +void gen_log_reg_write(int rnum, TCGv val); +void gen_log_pred_write(int pnum, TCGv val); + #endif --=20 2.30.0 From nobody Tue Nov 18 22:49:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613080713432475.46883147957215; Thu, 11 Feb 2021 13:58:33 -0800 (PST) Received: from localhost ([::1]:37930 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lAJyq-0005NY-04 for importer@patchew.org; Thu, 11 Feb 2021 16:58:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57096) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lAJrt-0006WH-1X for qemu-devel@nongnu.org; Thu, 11 Feb 2021 16:51:21 -0500 Received: from rev.ng ([5.9.113.41]:41643) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lAJrh-00011C-Lw for qemu-devel@nongnu.org; Thu, 11 Feb 2021 16:51:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=iVBL2FQXwoDZ9qHafGZ7cLNEGrYQZCe5ZD70MffczE4=; b=SIhXZrydAkyj788lRGd5LpdUFp rv3zqNxZwURmlNAUvYXd3Zy5iIKM8l/M11h8u14fQ7+yNPeedIylnUPer9FjuX7iNALDyI6xjW7aI IGu91U5mGB3NNgPztEzEhj82IdXHf0wpkxbRED1W6rDUspmPjH4245ZTrP/N7AI89rz0=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, Alessandro Di Federico Subject: [RFC PATCH 04/10] target/hexagon: introduce new helper functions Date: Thu, 11 Feb 2021 22:50:45 +0100 Message-Id: <20210211215051.2102435-5-ale.qemu@rev.ng> In-Reply-To: <20210211215051.2102435-1-ale.qemu@rev.ng> References: <20210211215051.2102435-1-ale.qemu@rev.ng> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico From: Alessandro Di Federico via X-ZohoMail-DKIM: fail (Header signature does not verify) From: Niccol=C3=B2 Izzo These helpers will be employed by the idef-parser generated code. Signed-off-by: Alessandro Di Federico --- target/hexagon/genptr.c | 224 ++++++++++++++++++++++++++++++++++++++++ target/hexagon/genptr.h | 19 ++++ 2 files changed, 243 insertions(+) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 97de669f38..33446bd713 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -334,5 +334,229 @@ static inline void gen_store_conditional8(CPUHexagonS= tate *env, tcg_gen_movi_tl(hex_llsc_addr, ~0); } =20 +void gen_fbrev(TCGv result, TCGv src) +{ + TCGv lo =3D tcg_temp_new(); + TCGv tmp1 =3D tcg_temp_new(); + TCGv tmp2 =3D tcg_temp_new(); + + /* Bit reversal of low 16 bits */ + tcg_gen_andi_tl(lo, src, 0xffff); + tcg_gen_andi_tl(tmp1, lo, 0xaaaa); + tcg_gen_shri_tl(tmp1, tmp1, 1); + tcg_gen_andi_tl(tmp2, lo, 0x5555); + tcg_gen_shli_tl(tmp2, tmp2, 1); + tcg_gen_or_tl(lo, tmp1, tmp2); + tcg_gen_andi_tl(tmp1, lo, 0xcccc); + tcg_gen_shri_tl(tmp1, tmp1, 2); + tcg_gen_andi_tl(tmp2, lo, 0x3333); + tcg_gen_shli_tl(tmp2, tmp2, 2); + tcg_gen_or_tl(lo, tmp1, tmp2); + tcg_gen_andi_tl(tmp1, lo, 0xf0f0); + tcg_gen_shri_tl(tmp1, tmp1, 4); + tcg_gen_andi_tl(tmp2, lo, 0x0f0f); + tcg_gen_shli_tl(tmp2, tmp2, 4); + tcg_gen_or_tl(lo, tmp1, tmp2); + tcg_gen_bswap16_tl(lo, lo); + + /* Final tweaks */ + tcg_gen_andi_tl(result, src, 0xffff0000); + tcg_gen_ori_tl(result, lo, 8); + + tcg_temp_free(lo); + tcg_temp_free(tmp1); + tcg_temp_free(tmp2); +} + +TCGv gen_set_bit(int i, TCGv result, TCGv src) +{ + TCGv mask =3D tcg_const_tl(~(1 << i)); + TCGv bit =3D tcg_temp_new(); + tcg_gen_shli_tl(bit, src, i); + tcg_gen_and_tl(result, result, mask); + tcg_gen_or_tl(result, result, bit); + tcg_temp_free(mask); + tcg_temp_free(bit); + + return result; +} + +void gen_cancel(TCGv slot) +{ + TCGv one =3D tcg_const_tl(1); + TCGv mask =3D tcg_temp_new(); + tcg_gen_shl_tl(mask, one, slot); + tcg_gen_or_tl(hex_slot_cancelled, hex_slot_cancelled, mask); + tcg_temp_free(one); + tcg_temp_free(mask); +} + +void gen_store32(TCGv vaddr, TCGv src, int width, int slot) +{ + tcg_gen_mov_tl(hex_store_addr[slot], vaddr); + tcg_gen_movi_tl(hex_store_width[slot], width); + tcg_gen_mov_tl(hex_store_val32[slot], src); +} + +void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + int slot) +{ + gen_store32(vaddr, src, 1, slot); + ctx->store_width[slot] =3D 1; +} + +void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + int slot) +{ + gen_store32(vaddr, src, 2, slot); + ctx->store_width[slot] =3D 2; +} + +void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + int slot) +{ + gen_store32(vaddr, src, 4, slot); + ctx->store_width[slot] =3D 4; +} + + +void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, DisasContext *= ctx, + int slot) +{ + tcg_gen_mov_tl(hex_store_addr[slot], vaddr); + tcg_gen_movi_tl(hex_store_width[slot], 8); + tcg_gen_mov_i64(hex_store_val64[slot], src); + ctx->store_width[slot] =3D 8; +} + +void gen_set_usr_field(int field, TCGv val) +{ + tcg_gen_deposit_tl(hex_gpr[HEX_REG_USR], hex_gpr[HEX_REG_USR], val, + reg_field_info[field].offset, + reg_field_info[field].width); +} + +void gen_set_usr_fieldi(int field, int x) +{ + TCGv val =3D tcg_const_tl(x); + gen_set_usr_field(field, val); + tcg_temp_free(val); +} + +void gen_write_new_pc(TCGv addr) +{ + /* If there are multiple branches in a packet, ignore the second one */ + TCGv zero =3D tcg_const_tl(0); + tcg_gen_movcond_tl(TCG_COND_NE, hex_next_PC, hex_branch_taken, zero, + hex_next_PC, addr); + tcg_gen_movi_tl(hex_branch_taken, 1); + tcg_temp_free(zero); +} + +void gen_sat_i32(TCGv dest, TCGv source, int width, bool set_overflow) +{ + TCGv max_val =3D tcg_const_i32((1 << (width - 1)) - 1); + TCGv min_val =3D tcg_const_i32(-(1 << (width - 1))); + tcg_gen_movcond_i32(TCG_COND_GT, dest, source, max_val, max_val, sourc= e); + tcg_gen_movcond_i32(TCG_COND_LT, dest, source, min_val, min_val, dest); + /* Set Overflow Bit */ + if (set_overflow) { + TCGv ovf =3D tcg_temp_new(); + TCGv one =3D tcg_const_i32(1); + GET_USR_FIELD(USR_OVF, ovf); + tcg_gen_movcond_i32(TCG_COND_GT, ovf, source, max_val, one, ovf); + tcg_gen_movcond_i32(TCG_COND_LT, ovf, source, min_val, one, ovf); + SET_USR_FIELD(USR_OVF, ovf); + tcg_temp_free_i32(ovf); + tcg_temp_free_i32(one); + } + tcg_temp_free_i32(max_val); + tcg_temp_free_i32(min_val); +} + +void gen_satu_i32(TCGv dest, TCGv source, int width, bool set_overflow) +{ + TCGv max_val =3D tcg_const_i32((1 << width) - 1); + tcg_gen_movcond_i32(TCG_COND_GTU, dest, source, max_val, max_val, sour= ce); + TCGv_i32 zero =3D tcg_const_i32(0); + tcg_gen_movcond_i32(TCG_COND_LT, dest, source, zero, zero, dest); + /* Set Overflow Bit */ + if (set_overflow) { + TCGv ovf =3D tcg_temp_new(); + TCGv one =3D tcg_const_i32(1); + GET_USR_FIELD(USR_OVF, ovf); + tcg_gen_movcond_i32(TCG_COND_GTU, ovf, source, max_val, one, ovf); + SET_USR_FIELD(USR_OVF, ovf); + tcg_temp_free_i32(ovf); + tcg_temp_free_i32(one); + } + tcg_temp_free_i32(max_val); + tcg_temp_free_i32(zero); +} + +void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width, bool set_overf= low) +{ + TCGv_i64 max_val =3D tcg_const_i64((1 << (width - 1)) - 1); + TCGv_i64 min_val =3D tcg_const_i64(-(1 << (width - 1))); + tcg_gen_movcond_i64(TCG_COND_GT, dest, source, max_val, max_val, sourc= e); + tcg_gen_movcond_i64(TCG_COND_LT, dest, source, min_val, min_val, dest); + /* Set Overflow Bit */ + if (set_overflow) { + TCGv ovf =3D tcg_temp_new(); + TCGv_i64 ovf_ext =3D tcg_temp_new_i64(); + TCGv_i64 one =3D tcg_const_i64(1); + GET_USR_FIELD(USR_OVF, ovf); + tcg_gen_ext_i32_i64(ovf_ext, ovf); + tcg_gen_movcond_i64(TCG_COND_GT, + ovf_ext, + source, + max_val, + one, + ovf_ext); + tcg_gen_movcond_i64(TCG_COND_LT, + ovf_ext, + source, + min_val, + one, + ovf_ext); + tcg_gen_trunc_i64_tl(ovf, ovf_ext); + SET_USR_FIELD(USR_OVF, ovf); + tcg_temp_free_i32(ovf); + tcg_temp_free_i64(ovf_ext); + tcg_temp_free_i64(one); + } + tcg_temp_free_i64(max_val); + tcg_temp_free_i64(min_val); +} + +void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width, bool set_over= flow) +{ + TCGv_i64 max_val =3D tcg_const_i64((1 << width) - 1); + tcg_gen_movcond_i64(TCG_COND_GTU, dest, source, max_val, max_val, sour= ce); + TCGv_i64 zero =3D tcg_const_i64(0); + tcg_gen_movcond_i64(TCG_COND_LT, dest, source, zero, zero, dest); + /* Set Overflow Bit */ + if (set_overflow) { + TCGv ovf =3D tcg_temp_new(); + TCGv_i64 ovf_ext =3D tcg_temp_new_i64(); + TCGv_i64 one =3D tcg_const_i64(1); + GET_USR_FIELD(USR_OVF, ovf); + tcg_gen_ext_i32_i64(ovf_ext, ovf); + tcg_gen_movcond_i64(TCG_COND_GTU, + ovf_ext, + source, + max_val, + one, + ovf_ext); + tcg_gen_trunc_i64_tl(ovf, ovf_ext); + SET_USR_FIELD(USR_OVF, ovf); + tcg_temp_free_i32(ovf); + tcg_temp_free_i64(ovf_ext); + tcg_temp_free_i64(one); + } + tcg_temp_free_i64(max_val); + tcg_temp_free_i64(zero); +} + #include "tcg_funcs_generated.c.inc" #include "tcg_func_table_generated.c.inc" diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index 0bfa99b463..e7f8f2c469 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -28,5 +28,24 @@ TCGv gen_read_reg(TCGv result, int num); TCGv gen_read_preg(TCGv pred, uint8_t num); void gen_log_reg_write(int rnum, TCGv val); void gen_log_pred_write(int pnum, TCGv val); +void gen_fbrev(TCGv result, TCGv src); +void gen_cancel(TCGv slot); +TCGv gen_set_bit(int i, TCGv result, TCGv src); +void gen_store32(TCGv vaddr, TCGv src, int width, int slot); +void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + int slot); +void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + int slot); +void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + int slot); +void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, DisasContext *= ctx, + int slot); +void gen_set_usr_field(int field, TCGv val); +void gen_set_usr_fieldi(int field, int x); +void gen_write_new_pc(TCGv addr); +void gen_sat_i32(TCGv dest, TCGv source, int width, bool set_overflow); +void gen_satu_i32(TCGv dest, TCGv source, int width, bool set_overflow); +void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width, bool set_overf= low); +void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width, bool set_over= flow); =20 #endif --=20 2.30.0 From nobody Tue Nov 18 22:49:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico From: Alessandro Di Federico via X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Paolo Montesel Signed-off-by: Alessandro Di Federico --- target/hexagon/translate.c | 4 +++- target/hexagon/translate.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index eeaad5f8ba..a59db485a3 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -503,11 +503,13 @@ static void decode_and_translate_packet(CPUHexagonSta= te *env, DisasContext *ctx) if (decode_packet(nwords, words, &pkt, false) > 0) { HEX_DEBUG_PRINT_PKT(&pkt); gen_start_packet(ctx, &pkt); + ctx->npc =3D ctx->base.pc_next + pkt.encod_pkt_size_in_bytes; for (i =3D 0; i < pkt.num_insns; i++) { gen_insn(env, ctx, &pkt.insn[i], &pkt); } gen_commit_packet(ctx, &pkt); - ctx->base.pc_next +=3D pkt.encod_pkt_size_in_bytes; + ctx->base.pc_next =3D ctx->npc; + ctx->npc =3D 0; } else { gen_exception(HEX_EXCP_INVALID_PACKET); ctx->base.is_jmp =3D DISAS_NORETURN; diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 938f7fbb9f..2195e20f4b 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -36,6 +36,7 @@ typedef struct DisasContext { int preg_log_idx; uint8_t store_width[STORES_MAX]; uint8_t s1_store_processed; + uint32_t npc; } DisasContext; =20 static inline void ctx_log_reg_write(DisasContext *ctx, int rnum) --=20 2.30.0 From nobody Tue Nov 18 22:49:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" From: Alessandro Di Federico Introduce infrastructure necessary to produce a file suitable for being parsed by the idef-parser. Signed-off-by: Alessandro Di Federico --- target/hexagon/gen_idef_parser_funcs.py | 114 ++++++++++++++++ target/hexagon/idef-parser/macros.inc | 166 ++++++++++++++++++++++++ target/hexagon/idef-parser/prepare | 33 +++++ target/hexagon/meson.build | 18 +++ 4 files changed, 331 insertions(+) create mode 100644 target/hexagon/gen_idef_parser_funcs.py create mode 100644 target/hexagon/idef-parser/macros.inc create mode 100755 target/hexagon/idef-parser/prepare diff --git a/target/hexagon/gen_idef_parser_funcs.py b/target/hexagon/gen_i= def_parser_funcs.py new file mode 100644 index 0000000000..6fb3659201 --- /dev/null +++ b/target/hexagon/gen_idef_parser_funcs.py @@ -0,0 +1,114 @@ +#!/usr/bin/env python3 + +## +## Copyright(c) 2019-2020 rev.ng Srls. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +import sys +import re +import string +from io import StringIO + +import hex_common + +## +## Generate code to be fed to the idef_parser +## +## Consider A2_add: +## +## Rd32=3Dadd(Rs32,Rt32), { RdV=3DRsV+RtV;} +## +## We produce: +## +## A2_add(RdV, in RsV, in RtV) { +## { RdV=3DRsV+RtV;} +## } +## +## A2_add represents the instruction tag. Then we have a list of TCGv +## that the code generated by the parser can expect in input. Some of +## them are inputs ("in" prefix), while some others are outputs. +## +def main(): + hex_common.read_semantics_file(sys.argv[1]) + hex_common.read_attribs_file(sys.argv[2]) + hex_common.read_overrides_file(sys.argv[3]) + hex_common.calculate_attribs() + tagregs =3D hex_common.get_tagregs() + tagimms =3D hex_common.get_tagimms() + + with open(sys.argv[4], 'w') as f: + f.write('#include "macros.inc"\n\n') + + for tag in hex_common.tags: + ## Skip the priv instructions + if ( "A_PRIV" in hex_common.attribdict[tag] ) : + continue + ## Skip the guest instructions + if ( "A_GUEST" in hex_common.attribdict[tag] ) : + continue + ## Skip instructions using switch + if ( tag in {'S4_vrcrotate_acc', 'S4_vrcrotate'} ) : + continue + ## Skip trap instructions + if ( tag in {'J2_trap0', 'J2_trap1'} ) : + continue + ## Skip 128-bit instructions + if ( tag in {'A7_croundd_ri', 'A7_croundd_rr'} ) : + continue + ## Skip other unsupported instructions + if ( tag.startswith('S2_cabacdecbin') ) : + continue + if ( tag.startswith('Y') ) : + continue + if ( tag.startswith('V6_') ) : + continue + if ( tag.startswith('F') ) : + continue + if ( tag.endswith('_locked') ) : + continue + + regs =3D tagregs[tag] + imms =3D tagimms[tag] + + arguments =3D [] + if hex_common.need_ea(tag): + arguments.append("EA") + + for regtype,regid,toss,numregs in regs: + prefix =3D "in " if hex_common.is_read(regid) else "" + + is_pair =3D hex_common.is_pair(regid) + is_single_old =3D (hex_common.is_single(regid) + and hex_common.is_old_val(regtype, regid,= tag)) + is_single_new =3D (hex_common.is_single(regid) + and hex_common.is_new_val(regtype, regid,= tag)) + + if is_pair or is_single_old: + arguments.append("%s%s%sV" % (prefix, regtype, regid)) + elif is_single_new: + arguments.append("%s%s%sN" % (prefix, regtype, regid)) + else: + print("Bad register parse: ",regtype,regid,toss,numreg= s) + + for immlett,bits,immshift in imms: + arguments.append(hex_common.imm_name(immlett)) + + f.write("%s(%s) {\n" % (tag, ", ".join(arguments))) + f.write(" %s\n" % hex_common.semdict[tag]) + f.write("}\n\n") + +if __name__ =3D=3D "__main__": + main() diff --git a/target/hexagon/idef-parser/macros.inc b/target/hexagon/idef-pa= rser/macros.inc new file mode 100644 index 0000000000..719bebaee3 --- /dev/null +++ b/target/hexagon/idef-parser/macros.inc @@ -0,0 +1,166 @@ +/* + * Copyright(c) 2019-2020 rev.ng Srls. All Rights Reserved. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +/* Copy rules */ +#define fLSBOLD(VAL) (fGETBIT(0, VAL)) +#define fSATH(VAL) fSATN(16, VAL) +#define fSATUH(VAL) fSATUN(16, VAL) +#define fVSATH(VAL) fVSATN(16, VAL) +#define fVSATUH(VAL) fVSATUN(16, VAL) +#define fSATUB(VAL) fSATUN(8, VAL) +#define fSATB(VAL) fSATN(8, VAL) +#define fVSATUB(VAL) fVSATUN(8, VAL) +#define fVSATB(VAL) fVSATN(8, VAL) +#define fCALL(A) fWRITE_LR(fREAD_NPC()); fWRITE_NPC(A); +#define fCALLR(A) fWRITE_LR(fREAD_NPC()); fWRITE_NPC(A); +#define fCAST2_8s(A) fSXTN(16, 64, A) +#define fCAST2_8u(A) fZXTN(16, 64, A) +#define fCAST8S_16S(A) (fSXTN(64, 128, A)) +#define fCAST16S_8S(A) (fSXTN(128, 64, A)) +#define fVSATW(A) fVSATN(32, fCAST8_8s(A)) +#define fSATW(A) fSATN(32, fCAST8_8s(A)) +#define fVSAT(A) fVSATN(32, A) +#define fSAT(A) fSATN(32, A) + +/* Ease parsing */ +#define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00) +#define fREAD_GP() (Constant_extended ? (0) : GP) +#define fCLIP(DST, SRC, U) (DST =3D fMIN((1 << U) - 1, fMAX(SRC, -(1 << U)= ))) +#define fBIDIR_ASHIFTL(SRC, SHAMT, REGSTYPE) \ + ((SHAMT > 0) ? \ + (fCAST##REGSTYPE##s(SRC) << SHAMT) : \ + (fCAST##REGSTYPE##s(SRC) >> -SHAMT)) + +#define fBIDIR_LSHIFTL(SRC, SHAMT, REGSTYPE) \ + ((SHAMT > 0) ? \ + (fCAST##REGSTYPE##u(SRC) << SHAMT) : \ + (fCAST##REGSTYPE##u(SRC) >>> -SHAMT)) + +#define fBIDIR_ASHIFTR(SRC, SHAMT, REGSTYPE) \ + ((SHAMT > 0) ? \ + (fCAST##REGSTYPE##s(SRC) >> SHAMT) : \ + (fCAST##REGSTYPE##s(SRC) << -SHAMT)) + +#define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \ + (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \ + : (fCAST##REGSTYPE(SRC) >> (SHAMT))) + +#define fBIDIR_LSHIFTR(SRC, SHAMT, REGSTYPE) \ + fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u) + +#define fSATVALN(N, VAL) \ + fSET_OVERFLOW( \ + ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1) \ + ) + +#define fSAT_ORIG_SHL(A, ORIG_REG) \ + (((fCAST4s((fSAT(A)) ^ (fCAST4s(ORIG_REG)))) < 0) \ + ? fSATVALN(32, (fCAST4s(ORIG_REG))) \ + : ((((ORIG_REG) > 0) && ((A) =3D=3D 0)) ? fSATVALN(32, (ORIG_REG))= \ + : fSAT(A))) + +#define fBIDIR_ASHIFTR_SAT(SRC, SHAMT, REGSTYPE) \ + (((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) \ + << ((-(SHAMT)) - 1)) << 1, (SRC)) \ + : (fCAST##REGSTYPE##s(SRC) >> (SHAMT))) + +#define fBIDIR_ASHIFTL_SAT(SRC, SHAMT, REGSTYPE) \ + (((SHAMT) < 0) \ + ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \ + : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT), (SRC))) + +#define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \ + (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8))) + +#define fCARRY_FROM_ADD(A, B, C) \ + fGETUWORD(1, \ + fGETUWORD(1, A) + \ + fGETUWORD(1, B) + \ + fGETUWORD(1, \ + fGETUWORD(0, A) + \ + fGETUWORD(0, B) + C)) + +#define fADDSAT64(DST, A, B) \ + __a =3D fCAST8u(A); \ + __b =3D fCAST8u(B); \ + __sum =3D __a + __b; \ + __xor =3D __a ^ __b; \ + __mask =3D 0x8000000000000000ULL; \ + if (__xor & __mask) { \ + DST =3D __sum; \ + } \ + else if ((__a ^ __sum) & __mask) { \ + if (__sum & __mask) { \ + DST =3D 0x7FFFFFFFFFFFFFFFLL; \ + fSET_OVERFLOW(); \ + } else { \ + DST =3D 0x8000000000000000ULL; \ + fSET_OVERFLOW(); \ + } \ + } else { \ + DST =3D __sum; \ + } + +/* Negation operator */ +#define fLSBOLDNOT(VAL) (!fGETBIT(0, VAL)) +#define fLSBNEWNOT(PNUM) (!fLSBNEW(PNUM)) +#define fLSBNEW0NOT (!fLSBNEW0) + +/* Assignments */ +#define fPCALIGN(IMM) (IMM =3D IMM & ~3) +#define fWRITE_LR(A) (LR =3D A) +#define fWRITE_FP(A) (FP =3D A) +#define fWRITE_SP(A) (SP =3D A) +#define fBRANCH(LOC, TYPE) (PC =3D LOC) +#define fJUMPR(REGNO, TARGET, TYPE) (PC =3D TARGET) +#define fWRITE_LOOP_REGS0(START, COUNT) SA0 =3D START; (LC0 =3D COUNT) +#define fWRITE_LOOP_REGS1(START, COUNT) SA1 =3D START; (LC1 =3D COUNT) +#define fWRITE_LC0(VAL) (LC0 =3D VAL) +#define fWRITE_LC1(VAL) (LC1 =3D VAL) +#define fSET_LPCFG(VAL) (USR.LPCFG =3D VAL) +#define fWRITE_P0(VAL) P0 =3D VAL; +#define fWRITE_P1(VAL) P1 =3D VAL; +#define fWRITE_P3(VAL) P3 =3D VAL; +#define fEA_RI(REG, IMM) (EA =3D REG + IMM) +#define fEA_RRs(REG, REG2, SCALE) (EA =3D REG + (REG2 << SCALE)) +#define fEA_IRs(IMM, REG, SCALE) (EA =3D IMM + (REG << SCALE)) +#define fEA_IMM(IMM) (EA =3D IMM) +#define fEA_REG(REG) (EA =3D REG) +#define fEA_BREVR(REG) (EA =3D fbrev(REG)) +#define fEA_GPI(IMM) (EA =3D fREAD_GP() + IMM) +#define fPM_I(REG, IMM) (REG =3D REG + IMM) +#define fPM_M(REG, MVAL) (REG =3D REG + MVAL) +#define fWRITE_NPC(VAL) (PC =3D VAL) + +/* Unary operators */ +#define fROUND(A) (A + 0x8000) + +/* Binary operators */ +#define fADD128(A, B) (A + B) +#define fSUB128(A, B) (A - B) +#define fSHIFTR128(A, B) (size8s_t) (A >> B) +#define fSHIFTL128(A, B) (A << B) +#define fAND128(A, B) (A & B) +#define fSCALE(N, A) (A << N) +#define fASHIFTR(SRC, SHAMT, REGSTYPE) (SRC >> SHAMT) +#define fLSHIFTR(SRC, SHAMT, REGSTYPE) (SRC >>> SHAMT) +#define fROTL(SRC, SHAMT, REGSTYPE) fROTL(SRC, SHAMT) +#define fASHIFTL(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) << SHAMT) + +/* Purge non-relavant parts */ +#define fHIDE(A) +#define fBRANCH_SPECULATE_STALL(A, B, C, D, E) diff --git a/target/hexagon/idef-parser/prepare b/target/hexagon/idef-parse= r/prepare new file mode 100755 index 0000000000..a11a86dc01 --- /dev/null +++ b/target/hexagon/idef-parser/prepare @@ -0,0 +1,33 @@ +#!/bin/bash + +# +# Copyright(c) 2019-2020 rev.ng Srls. All Rights Reserved. +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . +# + +set -e +set -o pipefail + +# 1. Run the preprocessor +# 2. Transform +# +# condition ? A =3D B : A =3D C +# +# in +# +# A =3D (condition ? B : C) +# +# 3. Remove comments (starting with "#") +cpp "$@" | sed 's/\(\s*[{;]\)\s*\([^;?]*\) ? (\([^;=3D]*\)=3D\([^;)]*\))\s= *:\s*([^;=3D]*=3D\([^;)]*\));/\1 \3 =3D (\2) ? \4 : \5;/' | grep -v '^#' diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index 06f449da66..e2e6b64766 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -22,6 +22,7 @@ prog_python =3D import('python').find_installation('pytho= n3') hex_common_py =3D 'hex_common.py' attribs_def =3D meson.current_source_dir() / 'attribs_def.h.inc' gen_tcg_h =3D meson.current_source_dir() / 'gen_tcg.h' +idef_parser_dir =3D meson.current_source_dir() / 'idef-parser' =20 # # Step 1 @@ -190,4 +191,21 @@ hexagon_ss.add(files( 'conv_emu.c', )) =20 +idef_parser_input_generated =3D custom_target( + 'idef_parser_input.h.inc', + output: 'idef_parser_input.h.inc', + input: 'gen_idef_parser_funcs.py', + depend_files: [hex_common_py], + command: [prog_python, '@INPUT@', semantics_generated, attribs_def, ge= n_tcg_h, '@OUTPUT@'], +) + +idef_parser_input_generated_prep =3D custom_target( + 'idef_parser_input.preprocessed.h.inc', + output: 'idef_parser_input.preprocessed.h.inc', + input: idef_parser_input_generated, + capture: true, + depend_files: [hex_common_py], + command: [idef_parser_dir / 'prepare', '@INPUT@', '-I' + idef_parser_d= ir], +) + target_arch +=3D {'hexagon': hexagon_ss} --=20 2.30.0 From nobody Tue Nov 18 22:49:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 11 Feb 2021 16:51:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=8spDaotpUtdVV+Pej9PcYQZUKTvB95PZ+CiOjPT/JT8=; b=Z29/jTHd0GwOPPWpvAaj2S+c6K BYbqclkVlkm+Jogx9z+0ISooJ6lx3bXOZBEodYqZ4+8cjaDVPsHm7hK7l3Zj7R3SI13Mej49kGXNd wVI4HGjW3syDC38smuv9TuX5Xv4FROX9YqOlew1q0xHl2qcmHUWxYP7fsUyrmpONVMW8=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, Alessandro Di Federico Subject: [RFC PATCH 07/10] target/hexagon: import lexer for idef-parser Date: Thu, 11 Feb 2021 22:50:48 +0100 Message-Id: <20210211215051.2102435-8-ale.qemu@rev.ng> In-Reply-To: <20210211215051.2102435-1-ale.qemu@rev.ng> References: <20210211215051.2102435-1-ale.qemu@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico From: Alessandro Di Federico via X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Paolo Montesel Signed-off-by: Alessandro Di Federico --- target/hexagon/idef-parser/idef-lexer.lex | 648 ++++++++++++++++++++++ target/hexagon/idef-parser/idef-parser.h | 245 ++++++++ target/hexagon/meson.build | 4 + 3 files changed, 897 insertions(+) create mode 100644 target/hexagon/idef-parser/idef-lexer.lex create mode 100644 target/hexagon/idef-parser/idef-parser.h diff --git a/target/hexagon/idef-parser/idef-lexer.lex b/target/hexagon/ide= f-parser/idef-lexer.lex new file mode 100644 index 0000000000..b0e460b4d4 --- /dev/null +++ b/target/hexagon/idef-parser/idef-lexer.lex @@ -0,0 +1,648 @@ +%option noyywrap noinput nounput +%option 8bit reentrant bison-bridge +%option warn nodefault +%option header-file=3D"idef-parser.yy.h" +%option bison-locations + +%{ +/* + * Copyright(c) 2019-2020 rev.ng Srls. All Rights Reserved. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include +#include + +#include "idef-parser.h" +#include "idef-parser.tab.h" + +/* Keep track of scanner position for error message printout */ +#define YY_USER_ACTION yylloc->first_column =3D yylloc->last_column; \ + for (int i =3D 0; yytext[i] !=3D '\0'; i++) { \ + yylloc->last_column++; \ + } + +/* Global Error Counter */ +int error_count; + +%} + +/* Definitions */ +DIGIT [0-9] +LOWER_ID [a-z] +UPPER_ID [A-Z] +ID LOWER_ID|UPPER_ID +INST_NAME [A-Z]+[0-9]_([A-Za-z]|[0-9]|_)+ +HEX_DIGIT [0-9a-fA-F] +REG_ID_32 e|s|d|t|u|v|x|y +REG_ID_64 ee|ss|dd|tt|uu|vv|xx|yy +SYS_ID_32 s|d +SYS_ID_64 ss|dd +LOWER_PRE d|s|t|u|v|e|x|x +ZERO_ONE 0|1 +IMM_ID r|s|S|u|U +VAR_ID [a-zA-Z_][a-zA-Z0-9_]* +SIGN_ID s|u + +/* Tokens */ +%% + +[ \t\f\v]+ { /* Ignore whitespaces. */ } +[\n\r]+ { /* Ignore newlines. */ } + +{INST_NAME} { yylval->string =3D strdup(yytext); + return INAME; } +"fFLOAT" | +"fUNFLOAT" | +"fDOUBLE" | +"fUNDOUBLE" | +"0.0" | +"0x1.0p52" | +"0x1.0p-52" { return FAIL; } +"R"{REG_ID_32}"V" { + yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D GENERAL_PURPOSE; + yylval->rvalue.reg.id =3D yytext[1]; + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.is_dotnew =3D false; + return REG; } +"R"{REG_ID_32}"N" { + yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D DOTNEW; + yylval->rvalue.reg.id =3D yytext[1]; + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.is_dotnew =3D true; + return REG; } +"R"{REG_ID_64}"V" { + yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D GENERAL_PURPOSE; + yylval->rvalue.reg.id =3D yytext[1]; + yylval->rvalue.reg.bit_width =3D 64; + yylval->rvalue.bit_width =3D 64; + yylval->rvalue.is_dotnew =3D false; + return REG; } +"R"{REG_ID_64}"N" { + yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D DOTNEW; + yylval->rvalue.reg.id =3D yytext[1]; + yylval->rvalue.reg.bit_width =3D 64; + yylval->rvalue.bit_width =3D 64; + yylval->rvalue.is_dotnew =3D true; + return REG; } +"MuV" { + yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D MODIFIER; + yylval->rvalue.reg.id =3D 'u'; + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + return REG; } +"C"{REG_ID_32}"V" { + yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D CONTROL; + yylval->rvalue.reg.id =3D yytext[1]; + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.is_dotnew =3D false; + return REG; } +"C"{REG_ID_64}"V" { + yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D CONTROL; + yylval->rvalue.reg.id =3D yytext[1]; + yylval->rvalue.reg.bit_width =3D 64; + yylval->rvalue.bit_width =3D 64; + yylval->rvalue.is_dotnew =3D false; + return REG; } +{IMM_ID}"iV" { + yylval->rvalue.type =3D IMMEDIATE; + yylval->rvalue.is_unsigned =3D false; + yylval->rvalue.imm.type =3D VARIABLE; + yylval->rvalue.imm.id =3D yytext[0]; + yylval->rvalue.is_dotnew =3D false; + return IMM; } +"P"{LOWER_PRE}"V" { + yylval->rvalue.type =3D PREDICATE; + yylval->rvalue.pre.id =3D yytext[1]; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.is_dotnew =3D false; + return PRE; } +"P"{LOWER_PRE}"N" { + yylval->rvalue.type =3D PREDICATE; + yylval->rvalue.pre.id =3D yytext[1]; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.is_dotnew =3D true; + return PRE; } +"in R"{REG_ID_32}"V" { + yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D GENERAL_PURPOSE; + yylval->rvalue.reg.id =3D yytext[4]; + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.is_dotnew =3D false; + return RREG; } +"in R"{REG_ID_64}"V" { + yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D GENERAL_PURPOSE; + yylval->rvalue.reg.id =3D yytext[4]; + yylval->rvalue.reg.bit_width =3D 64; + yylval->rvalue.bit_width =3D 64; + yylval->rvalue.is_dotnew =3D false; + return RREG; } +"in N"{REG_ID_32}"N" { + yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D DOTNEW; + yylval->rvalue.reg.id =3D yytext[4]; + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.is_dotnew =3D true; + return RREG; } +"in N"{REG_ID_64}"N" { + yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D DOTNEW; + yylval->rvalue.reg.id =3D yytext[4]; + yylval->rvalue.reg.bit_width =3D 64; + yylval->rvalue.bit_width =3D 64; + yylval->rvalue.is_dotnew =3D true; + return RREG; } +"in P"{LOWER_PRE}"V" { + yylval->rvalue.type =3D PREDICATE; + yylval->rvalue.pre.id =3D yytext[4]; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.is_dotnew =3D false; + return RPRE; } +"in P"{LOWER_PRE}"N" { + yylval->rvalue.type =3D PREDICATE; + yylval->rvalue.pre.id =3D yytext[4]; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.is_dotnew =3D true; + return RPRE; } +"in MuV" { + yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D MODIFIER; + yylval->rvalue.reg.id =3D 'u'; + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + return RREG; } +"in C"{REG_ID_32}"V" { + yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D CONTROL; + yylval->rvalue.reg.id =3D yytext[4]; + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.is_dotnew =3D false; + return RREG; } +"in C"{REG_ID_64}"V" { + yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D CONTROL; + yylval->rvalue.reg.id =3D yytext[4]; + yylval->rvalue.reg.bit_width =3D 64; + yylval->rvalue.bit_width =3D 64; + yylval->rvalue.is_dotnew =3D false; + return RREG; } +"fGEN_TCG_"{INST_NAME}"(" { return FWRAP; } +"(unsigned int)" { /* Skip c-style casts */ } +"{" { return LBR; } +"}" { return RBR; } +"[" { return LSQ; } +"]" { return RSQ; } +"(" { return LPAR; } +")" { return RPAR; } +"IV1DEAD()" | +"fPAUSE(uiV);" | +";" { return SEMI; } +":" { return COLON; } +"+" { return PLUS; } +"-" { return MINUS; } +"*" { return MUL; } +"**" { return POW; } +"/" { return DIV; } +"%" { return MOD; } +"&" { return AND; } +"|" { return OR; } +"^" { return XOR; } +"~" { return NOT; } +"=3D" { return ASSIGN; } +"+=3D" { return INC; } +"-=3D" { return DEC; } +"++" { return PLUSPLUS; } +"&=3D" { return ANDA; } +"|=3D" { return ORA; } +"^=3D" { return XORA; } +"<" { return LT; } +">" { return GT; } +"<<" { return ASL; } +">>" { return ASR; } +">>>" { return LSR; } +"=3D=3D" { return EQ; } +"!=3D" { return NEQ; } +"<=3D" { return LTE; } +">=3D" { return GTE; } +"&&" { return ANDL; } +"||" { return ORL; } +"!" { return NOTL; } +"," { return COMMA; } +"else" { return ELSE; } +"for" { return FOR; } +"fREAD_IREG" { return ICIRC; } +"fPART1" { return PART1; } +"if" { return IF; } +"fFRAME_SCRAMBLE" { return FSCR; } +"fFRAME_UNSCRAMBLE" { return FSCR; } +"fFRAMECHECK" { return FCHK; } +"Constant_extended" { return CONSTEXT; } +"fCL1_"{DIGIT} { return LOCNT; } +"fBREV_8" { return BREV_8; } +"fBREV_4" { return BREV_4; } +"fbrev" { return BREV; } +"fSXTN" { return SXT; } +"fZXTN" { return ZXT; } +"fDF_MAX" | +"fSF_MAX" | +"fMAX" { return MAX; } +"fDF_MIN" | +"fSF_MIN" | +"fMIN" { return MIN; } +"fABS" { return ABS; } +"fRNDN" { return ROUND; } +"fCRND" { return CROUND; } +"fCRNDN" { return CROUND; } +"fPM_CIRI" { return CIRCADD; } +"fPM_CIRR" { return CIRCADD; } +"fCOUNTONES_"{DIGIT} { return COUNTONES; } +"fSATN" { yylval->sat.set_overflow =3D false; + yylval->sat.is_unsigned =3D false; + return SAT; } +"fVSATN" { yylval->sat.set_overflow =3D true; + yylval->sat.is_unsigned =3D false; + return SAT; } +"fSATUN" { yylval->sat.set_overflow =3D false; + yylval->sat.is_unsigned =3D true; + return SAT; } +"fVSATUN" { yylval->sat.set_overflow =3D true; + yylval->sat.is_unsigned =3D true; + return SAT; } +"fSE32_64" { yylval->cast.bit_width =3D 64; + yylval->cast.is_unsigned =3D false; + return CAST; } +"fCAST4_4u" { yylval->cast.bit_width =3D 32; + yylval->cast.is_unsigned =3D true; + return CAST; } +"fCAST4_8s" { yylval->cast.bit_width =3D 64; + yylval->cast.is_unsigned =3D false; + return CAST; } +"fCAST4_8u" { return CAST4_8U; } +"fCAST4u" { yylval->cast.bit_width =3D 32; + yylval->cast.is_unsigned =3D true; + return CAST; } +"fCAST4s" { yylval->cast.bit_width =3D 32; + yylval->cast.is_unsigned =3D false; + return CAST; } +"fCAST8_8u" { yylval->cast.bit_width =3D 64; + yylval->cast.is_unsigned =3D true; + return CAST; } +"fCAST8u" { yylval->cast.bit_width =3D 64; + yylval->cast.is_unsigned =3D true; + return CAST; } +"fCAST8s" { yylval->cast.bit_width =3D 64; + yylval->cast.is_unsigned =3D false; + return CAST; } +"fGETBIT" { yylval->extract.bit_width =3D 1; + yylval->extract.storage_bit_width =3D 1; + yylval->extract.is_unsigned =3D true; + return EXTRACT; } +"fGETBYTE" { yylval->extract.bit_width =3D 8; + yylval->extract.storage_bit_width =3D 8; + yylval->extract.is_unsigned =3D false; + return EXTRACT; } +"fGETUBYTE" { yylval->extract.bit_width =3D 8; + yylval->extract.storage_bit_width =3D 8; + yylval->extract.is_unsigned =3D true; + return EXTRACT; } +"fGETHALF" { yylval->extract.bit_width =3D 16; + yylval->extract.storage_bit_width =3D 16; + yylval->extract.is_unsigned =3D false; + return EXTRACT; } +"fGETUHALF" { yylval->extract.bit_width =3D 16; + yylval->extract.storage_bit_width =3D 16; + yylval->extract.is_unsigned =3D true; + return EXTRACT; } +"fGETWORD" { yylval->extract.bit_width =3D 32; + yylval->extract.storage_bit_width =3D 64; + yylval->extract.is_unsigned =3D false; + return EXTRACT; } +"fGETUWORD" { yylval->extract.bit_width =3D 32; + yylval->extract.storage_bit_width =3D 64; + yylval->extract.is_unsigned =3D true; + return EXTRACT; } +"fEXTRACTU_BITS" { return EXTBITS; } +"fEXTRACTU_RANGE" { return EXTRANGE; } +"fSETBIT" { yylval->cast.bit_width =3D 1; + yylval->cast.is_unsigned =3D false; + return DEPOSIT; } +"fSETBYTE" { yylval->cast.bit_width =3D 8; + yylval->cast.is_unsigned =3D false; + return DEPOSIT; } +"fSETHALF" { yylval->cast.bit_width =3D 16; + yylval->cast.is_unsigned =3D false; + return SETHALF; } +"fSETWORD" { yylval->cast.bit_width =3D 32; + yylval->cast.is_unsigned =3D false; + return DEPOSIT; } +"fINSERT_BITS" { return INSBITS; } +"fSETBITS" { return SETBITS; } +"fMPY8UU" { yylval->mpy.first_bit_width =3D 8; + yylval->mpy.second_bit_width =3D 8; + yylval->mpy.first_unsigned =3D true; + yylval->mpy.second_unsigned =3D true; + return MPY; } +"fMPY8US" { yylval->mpy.first_bit_width =3D 8; + yylval->mpy.second_bit_width =3D 8; + yylval->mpy.first_unsigned =3D true; + yylval->mpy.second_unsigned =3D false; + return MPY; } +"fMPY8SU" { yylval->mpy.first_bit_width =3D 8; + yylval->mpy.second_bit_width =3D 8; + yylval->mpy.first_unsigned =3D false; + yylval->mpy.second_unsigned =3D true; + return MPY; } +"fMPY8SS" { yylval->mpy.first_bit_width =3D 8; + yylval->mpy.second_bit_width =3D 8; + yylval->mpy.first_unsigned =3D false; + yylval->mpy.second_unsigned =3D false; + return MPY; } +"fMPY16UU" { yylval->mpy.first_bit_width =3D 16; + yylval->mpy.second_bit_width =3D 16; + yylval->mpy.first_unsigned =3D true; + yylval->mpy.second_unsigned =3D true; + return MPY; } +"fMPY16US" { yylval->mpy.first_bit_width =3D 16; + yylval->mpy.second_bit_width =3D 16; + yylval->mpy.first_unsigned =3D true; + yylval->mpy.second_unsigned =3D false; + return MPY; } +"fMPY16SU" { yylval->mpy.first_bit_width =3D 16; + yylval->mpy.second_bit_width =3D 16; + yylval->mpy.first_unsigned =3D false; + yylval->mpy.second_unsigned =3D true; + return MPY; } +"fMPY16SS" { yylval->mpy.first_bit_width =3D 16; + yylval->mpy.second_bit_width =3D 16; + yylval->mpy.first_unsigned =3D false; + yylval->mpy.second_unsigned =3D false; + return MPY; } +"fMPY32UU" { yylval->mpy.first_bit_width =3D 32; + yylval->mpy.second_bit_width =3D 32; + yylval->mpy.first_unsigned =3D true; + yylval->mpy.second_unsigned =3D true; + return MPY; } +"fMPY32US" { yylval->mpy.first_bit_width =3D 32; + yylval->mpy.second_bit_width =3D 32; + yylval->mpy.first_unsigned =3D true; + yylval->mpy.second_unsigned =3D false; + return MPY; } +"fMPY32SU" { yylval->mpy.first_bit_width =3D 32; + yylval->mpy.second_bit_width =3D 32; + yylval->mpy.first_unsigned =3D false; + yylval->mpy.second_unsigned =3D true; + return MPY; } +"fSFMPY" | +"fMPY32SS" { yylval->mpy.first_bit_width =3D 32; + yylval->mpy.second_bit_width =3D 32; + yylval->mpy.first_unsigned =3D false; + yylval->mpy.second_unsigned =3D false; + return MPY; } +"fMPY3216SS" { yylval->mpy.first_bit_width =3D 32; + yylval->mpy.second_bit_width =3D 16; + yylval->mpy.first_unsigned =3D false; + yylval->mpy.second_unsigned =3D false; + return MPY; } +"fMPY3216SU" { yylval->mpy.first_bit_width =3D 32; + yylval->mpy.second_bit_width =3D 16; + yylval->mpy.first_unsigned =3D false; + yylval->mpy.second_unsigned =3D true; + return MPY; } +"fNEWREG" | +"fNEWREG_ST" | +"fIMMEXT" | +"fMUST_IMMEXT" | +"fCAST2_2s" | +"fCAST2_2u" | +"fCAST4_4s" | +"fCAST8_8s" | +"fZE8_16" | +"fSE8_16" | +"fZE16_32" | +"fSE16_32" | +"fZE32_64" | +"fPASS" | +"fECHO" { return IDENTITY; } +"(size8"[us]"_t)" { yylval->cast.bit_width =3D 8; + yylval->cast.is_unsigned =3D ((yytext[6]) =3D= =3D 'u'); + return CAST; } +"(size16"[us]"_t)" { yylval->cast.bit_width =3D 16; + yylval->cast.is_unsigned =3D ((yytext[7]) =3D= =3D 'u'); + return CAST; } +"(int)" { yylval->cast.bit_width =3D 32; + yylval->cast.is_unsigned =3D false; + return CAST; } +"?" { return QMARK; } +"fREAD_PC()" | +"PC" { return PC; } +"fREAD_NPC()" | +"NPC" { return NPC; } +"fGET_LPCFG" | +"USR.LPCFG" { return LPCFG; } +"LOAD_CANCEL(EA)" | +"STORE_CANCEL(EA)" | +"CANCEL" { return CANC; } +"N"{LOWER_ID} { yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D GENERAL_PURPOSE; + yylval->rvalue.reg.id =3D yytext[1]; + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + return REG; } +"N"{LOWER_ID}"N" { yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D DOTNEW; + yylval->rvalue.reg.id =3D yytext[1]; + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + return REG; } +[rR]{DIGIT}+ { yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D GENERAL_PURPOSE; + yylval->rvalue.reg.id =3D atoi(yytext + 1); + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + return REG; } +"fREAD_SP()" | +"SP" { yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D CONTROL; + yylval->rvalue.reg.id =3D SP; + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + return REG; } +"fREAD_FP()" | +"FP" { yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D CONTROL; + yylval->rvalue.reg.id =3D FP; + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + return REG; } +"fREAD_LR()" | +"LR" { yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D CONTROL; + yylval->rvalue.reg.id =3D LR; + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + return REG; } +"GP" { yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D CONTROL; + yylval->rvalue.reg.id =3D GP; + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + return REG; } +"fREAD_LC"{ZERO_ONE} { yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D CONTROL; + yylval->rvalue.reg.id =3D LC0 + atoi(yytext + 8= ); + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + return REG; } +"LC"{ZERO_ONE} { yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D CONTROL; + yylval->rvalue.reg.id =3D LC0 + atoi(yytext + 2= ); + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + return REG; } +"fREAD_SA"{ZERO_ONE} { yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D CONTROL; + yylval->rvalue.reg.id =3D SA0 + atoi(yytext + 8= ); + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + return REG; } +"SA"{ZERO_ONE} { yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D CONTROL; + yylval->rvalue.reg.id =3D SA0 + atoi(yytext + 2= ); + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + return REG; } +"MuN" { return MUN; } +"fREAD_P0()" { yylval->rvalue.type =3D PREDICATE; + yylval->rvalue.pre.id =3D '0'; + yylval->rvalue.bit_width =3D 32; + return PRE; } +[pP]{DIGIT} { yylval->rvalue.type =3D PREDICATE; + yylval->rvalue.pre.id =3D yytext[1]; + yylval->rvalue.bit_width =3D 32; + return PRE; } +"fLSBNEW(P"{LOWER_PRE}"N)" { yylval->rvalue.type =3D PREDICATE; + yylval->rvalue.pre.id =3D yytext[9]; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.is_dotnew =3D true; + return PRE; } +"fLSBNEW0" { yylval->rvalue.type =3D PREDICATE; + yylval->rvalue.pre.id =3D '0'; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.is_dotnew =3D true; + return PRE; } +"fLSBNEW1" { yylval->rvalue.type =3D PREDICATE; + yylval->rvalue.pre.id =3D '1'; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.is_dotnew =3D true; + return PRE; } +"fLSBNEW1NOT" { yylval->rvalue.type =3D PREDICATE; + yylval->rvalue.pre.id =3D '1'; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.is_dotnew =3D true; + return PRE; } +"N" { yylval->rvalue.type =3D IMMEDIATE; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.imm.type =3D VARIABLE; + yylval->rvalue.imm.id =3D 'N'; + return IMM; } +"i" { yylval->rvalue.type =3D IMMEDIATE; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.imm.type =3D I; + return IMM; } +{SIGN_ID} { yylval->is_unsigned =3D (yytext[0] =3D=3D 'u'); + return SIGN; + } +"fSF_BIAS()" { yylval->rvalue.type =3D IMMEDIATE; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.is_unsigned =3D false; + yylval->rvalue.imm.type =3D VALUE; + yylval->rvalue.imm.value =3D 127; + return IMM; } +{DIGIT}+ { yylval->rvalue.type =3D IMMEDIATE; + yylval->rvalue.bit_width =3D 64; + yylval->rvalue.is_unsigned =3D false; + yylval->rvalue.imm.type =3D VALUE; + yylval->rvalue.imm.value =3D atoi(yytext); + return IMM; } +{DIGIT}+"LL" { yylval->rvalue.type =3D IMMEDIATE; + yylval->rvalue.bit_width =3D 64; + yylval->rvalue.is_unsigned =3D false; + yylval->rvalue.imm.type =3D VALUE; + yylval->rvalue.imm.value =3D atoi(yytext); + return IMM; } +"0x"{HEX_DIGIT}+ { yylval->rvalue.type =3D IMMEDIATE; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.is_unsigned =3D false; + yylval->rvalue.imm.type =3D VALUE; + yylval->rvalue.imm.value =3D strtol(yytext, NUL= L, 16); + return IMM; } +"0x"{HEX_DIGIT}+"LL" { yylval->rvalue.type =3D IMMEDIATE; + yylval->rvalue.bit_width =3D 64; + yylval->rvalue.is_unsigned =3D false; + yylval->rvalue.imm.type =3D VALUE; + yylval->rvalue.imm.value =3D strtol(yytext, NUL= L, 16); + return IMM; } +"0x"{HEX_DIGIT}+"ULL" { yylval->rvalue.type =3D IMMEDIATE; + yylval->rvalue.bit_width =3D 64; + yylval->rvalue.is_unsigned =3D true; + yylval->rvalue.imm.type =3D VALUE; + yylval->rvalue.imm.value =3D strtoul(yytext, NU= LL, 16); + return IMM; } +"fCONSTLL" { return CONSTLL; } +"fCONSTULL" { return CONSTULL; } +"fLOAD" { return LOAD; } +"fSTORE" { return STORE; } +"fROTL" { return ROTL; } +"fSET_OVERFLOW" { return SETOVF; } +"fDEINTERLEAVE" { return DEINTERLEAVE; } +"fINTERLEAVE" { return INTERLEAVE; } +{VAR_ID} { /* Variable name, we adopt the C names conventi= on */ + yylval->rvalue.type =3D VARID; + yylval->rvalue.var.name =3D strndup(yytext, + ALLOC_NAME_SI= ZE); + /* Default types are int */ + yylval->rvalue.bit_width =3D 32; + if (yylval->rvalue.var.name =3D=3D NULL) { + fprintf(stderr, + "Error: failed to duplicate var nam= e: " + "\"%s\"\n", + yytext); + error_count++; + return -1; /* invalid token */ + } + return VAR; } +"fHINTJR(RsV)" { /* Emit no token */ } +. { fprintf(stderr, + "Error: unexpected token \"%s\"\n", + yytext); + error_count++; + return -1; /* invalid token */ + } + +%% diff --git a/target/hexagon/idef-parser/idef-parser.h b/target/hexagon/idef= -parser/idef-parser.h new file mode 100644 index 0000000000..d08b9c80ea --- /dev/null +++ b/target/hexagon/idef-parser/idef-parser.h @@ -0,0 +1,245 @@ +/* + * Copyright(c) 2019-2020 rev.ng Srls. All Rights Reserved. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef IDEF_PARSER_H +#define IDEF_PARSER_H + +#include +#include +#include + +#define TCGV_NAME_SIZE 7 +#define MAX_WRITTEN_REGS 32 +#define OFFSET_STR_LEN 32 +#define ALLOC_LIST_LEN 32 +#define ALLOC_NAME_SIZE 32 +#define INIT_LIST_LEN 32 +#define OUT_BUF_LEN (1024 * 1024) +#define SIGNATURE_BUF_LEN (128 * 1024) +#define HEADER_BUF_LEN (128 * 1024) + +/* Variadic macros to wrap the buffer printing functions */ +#define EMIT(c, ...) \ + do { \ + (c)->out_c +=3D snprintf((c)->out_buffer + (c)->out_c, \ + OUT_BUF_LEN - (c)->out_c, \ + __VA_ARGS__); \ + } while (0) + +#define EMIT_SIG(c, ...) = \ + do { = \ + (c)->signature_c +=3D snprintf((c)->signature_buffer + (c)->signat= ure_c, \ + SIGNATURE_BUF_LEN - (c)->signature_c,= \ + __VA_ARGS__); = \ + } while (0) + +#define EMIT_HEAD(c, ...) = \ + do { = \ + (c)->header_c +=3D snprintf((c)->header_buffer + (c)->header_c, = \ + SIGNATURE_BUF_LEN - (c)->header_c, = \ + __VA_ARGS__); = \ + } while (0) + +/** + * Type of register, assigned to the HexReg.type field + */ +typedef enum {GENERAL_PURPOSE, CONTROL, MODIFIER, DOTNEW} RegType; + +/** + * Types of control registers, assigned to the HexReg.id field + */ +typedef enum {SP, FP, LR, GP, LC0, LC1, SA0, SA1} CregType; + +/** + * Identifier string of the control registers, indexed by the CregType enum + */ +extern const char *creg_str[]; + +/** + * Semantic record of the REG tokens, identifying registers + */ +typedef struct HexReg { + CregType id; /**< Identifier of the register = */ + RegType type; /**< Type of the register = */ + unsigned bit_width; /**< Bit width of the reg, 32 or 64 bits = */ +} HexReg; + +/** + * Data structure, identifying a TCGv temporary value + */ +typedef struct HexTmp { + int index; /**< Index of the TCGv temporary value */ +} HexTmp; + +/** + * Enum of the possible immediated, an immediate is a value which is known + * at tinycode generation time, e.g. an integer value, not a TCGv + */ +enum ImmUnionTag {I, VARIABLE, VALUE, QEMU_TMP, IMM_PC, IMM_CONSTEXT}; + +/** + * Semantic record of the IMM token, identifying an immediate constant + */ +typedef struct HexImm { + union { + char id; /**< Identifier of the immediate = */ + uint64_t value; /**< Immediate value (for VALUE type immediate= s) */ + uint64_t index; /**< Index of the immediate (for int temp vars= ) */ + }; + enum ImmUnionTag type; /**< Type of the immediate = */ +} HexImm; + +/** + * Semantic record of the PRE token, identifying a predicate + */ +typedef struct HexPre { + char id; /**< Identifier of the predicate = */ +} HexPre; + +/** + * Semantic record of the SAT token, identifying the saturate operator + */ +typedef struct HexSat { + bool set_overflow; /**< Set-overflow feature for the sat operator= */ + bool is_unsigned; /**< Unsigned flag for the saturate operator = */ +} HexSat; + +/** + * Semantic record of the CAST token, identifying the cast operator + */ +typedef struct HexCast { + int bit_width; /**< Bit width of the cast operator = */ + bool is_unsigned; /**< Unsigned flag for the cast operator = */ +} HexCast; + +/** + * Semantic record of the EXTRACT token, identifying the cast operator + */ +typedef struct HexExtract { + int bit_width; /**< Bit width of the extract operator = */ + int storage_bit_width; /**< Actual bit width of the extract operator = */ + bool is_unsigned; /**< Unsigned flag for the extract operator = */ +} HexExtract; + +/** + * Semantic record of the MPY token, identifying the fMPY multiplication + * operator + */ +typedef struct HexMpy { + int first_bit_width; /**< Bit width of the first operand of fMPY op= */ + int second_bit_width; /**< Bit width of the second operand of fMPY = */ + bool first_unsigned; /**< Unsigned flag for the first operand of fM= PY */ + bool second_unsigned; /**< Unsigned flag for second operand of fMPY = */ +} HexMpy; + +/** + * Semantic record of the VARID token, identifying automatic variables + * of the input language + */ +typedef struct HexVar { + char *name; /**< Name of the VARID automatic variable = */ +} HexVar; + +/** + * Data structure uniquely identifying an automatic VARID variable, used f= or + * keeping track of declared variable, so that any variable is declared on= ly + * once, and its properties are propagated through all the subsequent inst= ances + * of that variable + */ +typedef struct Var { + char *name; /**< Name of the VARID automatic variable = */ + uint8_t bit_width; /**< Bit width of the VARID automatic variable= */ + bool is_unsigned; /**< Unsigned flag for the VARID automatic var= */ +} Var; + +/** + * Enum of the possible rvalue types, used in the HexValue.type field + */ +enum RvalueUnionTag {REGISTER, TEMP, IMMEDIATE, PREDICATE, VARID}; + +/** + * Semantic record of the rvalue token, identifying any numeric value, + * immediate or register based. The rvalue tokens are combined together + * through the use of several operators, to encode expressions + */ +typedef struct HexValue { + union { + HexReg reg; /**< rvalue of register type = */ + HexTmp tmp; /**< rvalue of temporary type = */ + HexImm imm; /**< rvalue of immediate type = */ + HexPre pre; /**< rvalue of predicate type = */ + HexVar var; /**< rvalue of automatic variable type = */ + }; + enum RvalueUnionTag type; /**< Type of the rvalue = */ + unsigned bit_width; /**< Bit width of the rvalue = */ + bool is_unsigned; /**< Unsigned flag for the rvalue = */ + bool is_dotnew; /**< rvalue of predicate type is dotnew? = */ + bool is_manual; /**< Opt out of automatic freeing of params = */ +} HexValue; + +/** + * Operator type, used for referencing the correct operator when calling t= he + * gen_bin_op() function, which in turn will generate the correct code to + * execute the operation between the two rvalues + */ +enum OpType {ADD_OP, SUB_OP, MUL_OP, DIV_OP, ASL_OP, ASR_OP, LSR_OP, ANDB_= OP, + ORB_OP, XORB_OP, ANDL_OP, MINI_OP, MAXI_OP, MOD_OP}; + +/** + * Data structure including instruction specific information, to be cleared + * out after the compilation of each instruction + */ +typedef struct Inst { + char *name; /**< Name of the compiled instruction = */ + char *code_begin; /**< Beginning of instruction input code= */ + char *code_end; /**< End of instruction input code = */ + int tmp_count; /**< Index of the last declared TCGv tem= p */ + int qemu_tmp_count; /**< Index of the last declared int temp= */ + int if_count; /**< Index of the last declared if label= */ + int error_count; /**< Number of generated errors = */ + Var allocated[ALLOC_LIST_LEN]; /**< Allocated VARID automatic vars = */ + int allocated_count; /**< Elements contained in allocated[] = */ + HexValue init_list[INIT_LIST_LEN]; /**< List of initialized registers = */ + int init_count; /**< Number of members of init_list = */ +} Inst; + +/** + * Data structure representing the whole translation context, which in a + * reentrant flex/bison parser just like ours is passed between the scanner + * and the parser, holding all the necessary information to perform the + * parsing, this data structure survives between the compilation of differ= ent + * instructions + * + */ +typedef struct Context { + void *scanner; /**< Reentrant parser state pointer = */ + char *input_buffer; /**< Buffer containing the input code = */ + char *out_buffer; /**< Buffer containing the output code = */ + int out_c; /**< Characters emitted into out_buffer = */ + char *signature_buffer; /**< Buffer containing the signatures co= de */ + int signature_c; /**< Characters emitted into sig..._buff= er */ + char *header_buffer; /**< Buffer containing the output code = */ + int header_c; /**< Characters emitted into header buff= er */ + FILE *defines_file; /**< FILE * of the generated header = */ + FILE *output_file; /**< FILE * of the C output file = */ + FILE *enabled_file; /**< FILE * of the list of enabled inst = */ + int total_insn; /**< Number of instructions in input fil= e */ + int implemented_insn; /**< Instruction compiled without errors= */ + Inst inst; /**< Parsing data of the current inst = */ +} Context; + +#endif /* IDEF_PARSER_H */ diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index e2e6b64766..1a008e7e86 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -208,4 +208,8 @@ idef_parser_input_generated_prep =3D custom_target( command: [idef_parser_dir / 'prepare', '@INPUT@', '-I' + idef_parser_d= ir], ) =20 +flex =3D generator(find_program('flex'), + output: '@PLAINNAME@.yy.c', + arguments: ['-o', '@OUTPUT@', '@INPUT@']) + target_arch +=3D {'hexagon': hexagon_ss} --=20 2.30.0 From nobody Tue Nov 18 22:49:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1613080746; cv=none; d=zohomail.com; s=zohoarc; b=ZVZvTfx2nQ8t1KYHEWayw0SWG+OgyGuyc0XI2F4HcPxfnvArCQr7VdCJF8gWOP1bWuJT4+hdxkDPR8nkedNnbBat8v0urelIdGeOo1ccyktQEnb1JdrVfRXzwBMvJjusctwnfKGXDdL4vTwEWY2PQ75rrq6PrbCz5wSIV3eTKHE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613080746; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=wwMLXQPAdccnoLYeQAz55NoKrHgheLsL+MaYvgyAWIM=; b=CkwTNJvLLGneZBPi+4qs2WNBD8nnKue4RgsdqOzDmTvsA3IlyPhGaBrs8zwMJM6bDVi3E+NcIi+hAKNQVb7CVbYhp7pxhTbp785Ok8qaWyabL2O/IKGWE4B3zJDWE/a7vywmlytQS7c5xC3B3zJitgeLM0bXPsQDX41nZyuglZg= ARC-Authentication-Results: i=1; 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Thu, 11 Feb 2021 16:51:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=wwMLXQPAdccnoLYeQAz55NoKrHgheLsL+MaYvgyAWIM=; b=khmKLf49XPjP0qabS5MiIEYovC TMzJAgn5jiduOM7Cpn5o5+Z58wl/QhssvBXJ5T+UQAjTHCSo9d5m0IIjclVJS0e1Z9W0bbNQNDd6U Gh+hEQN9XsbU2gqdZK5s+My5YOjVlc3Tlja7qVuQrCuXw9CmeBfrpF/P1cnkmmZKXBpE=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, Alessandro Di Federico Subject: [RFC PATCH 08/10] target/hexagon: import parser for idef-parser Date: Thu, 11 Feb 2021 22:50:49 +0100 Message-Id: <20210211215051.2102435-9-ale.qemu@rev.ng> In-Reply-To: <20210211215051.2102435-1-ale.qemu@rev.ng> References: <20210211215051.2102435-1-ale.qemu@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico From: Alessandro Di Federico via X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Paolo Montesel Signed-off-by: Alessandro Di Federico --- target/hexagon/idef-parser/idef-parser.y | 1248 ++++++++++++ target/hexagon/idef-parser/parser-helpers.c | 1925 +++++++++++++++++++ target/hexagon/idef-parser/parser-helpers.h | 293 +++ target/hexagon/meson.build | 22 +- 4 files changed, 3487 insertions(+), 1 deletion(-) create mode 100644 target/hexagon/idef-parser/idef-parser.y create mode 100644 target/hexagon/idef-parser/parser-helpers.c create mode 100644 target/hexagon/idef-parser/parser-helpers.h diff --git a/target/hexagon/idef-parser/idef-parser.y b/target/hexagon/idef= -parser/idef-parser.y new file mode 100644 index 0000000000..80490101ca --- /dev/null +++ b/target/hexagon/idef-parser/idef-parser.y @@ -0,0 +1,1248 @@ +%{ +/* + * Copyright(c) 2019-2020 rev.ng Srls. All Rights Reserved. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; withOUT even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "idef-parser.h" +#include "parser-helpers.h" +#include "idef-parser.tab.h" +#include "idef-parser.yy.h" + +/* Uncomment this to disable yyasserts */ +/* #define NDEBUG */ + +#define ERR_LINE_CONTEXT 40 + +%} + +%lex-param {void *scanner} +%parse-param {void *scanner} +%parse-param {Context *c} + +%define parse.error detailed +%define parse.lac full +%define api.pure full + +%locations + +%union { + char *string; + HexValue rvalue; + HexSat sat; + HexCast cast; + HexExtract extract; + HexMpy mpy; + bool is_unsigned; + int index; +} + +/* Tokens */ +%start input + +%expect 1 + +%token INAME DREG DIMM DPRE DEA RREG WREG FREG FIMM RPRE WPRE FPRE FWRAP F= EA +%token VAR LBR RBR LPAR RPAR LSQ RSQ SEMI COLON PLUS MINUS MUL POW DIV MOD= ABS +%token CROUND ROUND CIRCADD COUNTONES AND OR XOR NOT ASSIGN INC DEC ANDA O= RA +%token XORA PLUSPLUS LT GT ASL ASR LSR EQ NEQ LTE GTE MIN MAX ANDL ORL NOTL +%token COMMA FOR ICIRC IF MUN FSCR FCHK SXT ZXT NEW CONSTEXT LOCNT BREV SI= GN +%token LOAD STORE CONSTLL CONSTULL PC NPC LPCFG CANC QMARK IDENTITY PART1 +%token BREV_4 BREV_8 ROTL INSBITS SETBITS EXTBITS EXTRANGE CAST4_8U SETOVF= FAIL +%token DEINTERLEAVE INTERLEAVE + +%token REG IMM PRE +%token ELSE +%token MPY +%token SAT +%token CAST DEPOSIT SETHALF +%token EXTRACT +%type INAME +%type rvalue lvalue VAR assign_statement pre +%type DREG DIMM DPRE RREG RPRE FAIL +%type if_stmt IF +%type SIGN + +/* Operator Precedences */ +%left MIN MAX +%left LPAR +%left COMMA +%left ASSIGN +%right CIRCADD +%right INC DEC ANDA ORA XORA +%left QMARK COLON +%left ORL +%left ANDL +%left OR +%left XOR ANDOR +%left AND +%left EQ NEQ +%left LT GT LTE GTE +%left ASL ASR LSR +%right ABS +%left MINUS PLUS +%left POW +%left MUL DIV MOD MPY +%right NOT NOTL +%left LSQ +%left NEW +%right CAST +%right LOCNT BREV + +/* Bison Grammar */ +%% + +/* Input file containing the description of each hexagon instruction */ +input : instructions +{ + YYACCEPT; +} +; + +instructions : instruction instructions +| %empty +; + +instruction : INAME +{ + /* Early-free if the parser failed on the previous instruction */ + free_instruction(c); + + c->total_insn++; + c->inst.name =3D $1; + emit_header(c); +} +arguments +{ + EMIT_SIG(c, ")"); + EMIT_HEAD(c, "{\n"); + + /* Initialize declared but uninitialized registers, but only for */ + /* non-conditional instructions */ + for (int i =3D 0; i < c->inst.init_count; i++) { + bool is64 =3D c->inst.init_list[i].bit_width =3D=3D 64; + const char *type =3D is64 ? "i64" : "i32"; + if (c->inst.init_list[i].type =3D=3D REGISTER) { + OUT(c, &@1, "tcg_gen_movi_", type, + "(", &(c->inst.init_list[i]), ", 0);\n"); + } else if (c->inst.init_list[i].type =3D=3D PREDICATE) { + OUT(c, &@1, "tcg_gen_movi_", type, + "(", &(c->inst.init_list[i]), ", 0);\n"); + } + } +} +code +{ + if (c->inst.error_count !=3D 0) { + fprintf(stderr, + "Parsing of instruction %s generated %d errors!\n", + c->inst.name, + c->inst.error_count); + EMIT(c, "assert(false && \"This instruction is not implemented!\")= ;"); + } else { + free_variables(c, &@1); + c->implemented_insn++; + fprintf(c->enabled_file, "%s\n", c->inst.name); + emit_footer(c); + commit(c); + } + free_instruction(c); +} +| error /* Recover gracefully after instruction compilation error */ +; + +arguments : LPAR RPAR +| +LPAR argument_list RPAR +; + +argument_list : decl COMMA argument_list +| decl +; + +/* Return the modified registers list */ +code : LBR statements RBR +{ + c->inst.code_begin =3D c->input_buffer + @2.first_column; + c->inst.code_end =3D c->input_buffer + @2.last_column - 1; +} +| +LBR +{ + /* Nop */ +} +RBR +; + +decl : REG +{ + emit_arg(c, &@1, &$1); + /* Enqueue register into initialization list */ + yyassert(c, &@1, c->inst.init_count < INIT_LIST_LEN, + "init_count overflow"); + c->inst.init_list[c->inst.init_count] =3D $1; + c->inst.init_count++; +} +| IMM +{ + EMIT_SIG(c, ", int %ciV", $1.imm.id); +} +| PRE +{ + emit_arg(c, &@1, &$1); + /* Enqueue predicate into initialization list */ + c->inst.init_list[c->inst.init_count] =3D $1; + c->inst.init_count++; +} +| VAR +{ + yyassert(c, &@1, !strcmp($1.var.name, "EA"), "Unknown argument variabl= e!"); +} +| RREG +{ + emit_arg(c, &@1, &$1); +} +| WREG +| FREG +| FIMM +| RPRE +{ + emit_arg(c, &@1, &$1); +} +| WPRE +| FPRE +| FEA +; + +code_block : LBR statements RBR { /* does nothing */ } +| LBR RBR { /* does nothing */ } +; + +/* A list of one or more statements */ +statements : statements statement { /* does nothing */ } +| statement { /* does nothing */ } +; + +/* Statements can be assignment (rvalue SEMI), control or memory statement= s */ +statement : control_statement { /* does nothing */ } +| rvalue SEMI { rvalue_free(c, &@1, &$1); } +| code_block { /* does nothing */ } +| SEMI { /* does nothing */ } +; + +assign_statement : lvalue ASSIGN rvalue +{ + @1.last_column =3D @3.last_column; + gen_assign(c, &@1, &$1, &$3); + $$ =3D $1; +} +| lvalue INC rvalue +{ + @1.last_column =3D @3.last_column; + HexValue tmp =3D gen_bin_op(c, &@1, ADD_OP, &$1, &$3); + gen_assign(c, &@1, &$1, &tmp); + $$ =3D $1; +} +| lvalue DEC rvalue +{ + @1.last_column =3D @3.last_column; + HexValue tmp =3D gen_bin_op(c, &@1, SUB_OP, &$1, &$3); + gen_assign(c, &@1, &$1, &tmp); + $$ =3D $1; +} +| lvalue ANDA rvalue +{ + @1.last_column =3D @3.last_column; + HexValue tmp =3D gen_bin_op(c, &@1, ANDB_OP, &$1, &$3); + gen_assign(c, &@1, &$1, &tmp); + $$ =3D $1; +} +| lvalue ORA rvalue +{ + @1.last_column =3D @3.last_column; + HexValue tmp =3D gen_bin_op(c, &@1, ORB_OP, &$1, &$3); + gen_assign(c, &@1, &$1, &tmp); + $$ =3D $1; +} +| lvalue XORA rvalue +{ + @1.last_column =3D @3.last_column; + HexValue tmp =3D gen_bin_op(c, &@1, XORB_OP, &$1, &$3); + gen_assign(c, &@1, &$1, &tmp); + $$ =3D $1; +} +| pre ASSIGN rvalue +{ + @1.last_column =3D @3.last_column; + bool is_direct =3D is_direct_predicate(&$1); + char pre_id[2] =3D " "; + pre_id[0] =3D $1.pre.id; + /* Extract predicate TCGv */ + if (is_direct) { + $1 =3D gen_tmp_value(c, &@1, "0", 32); + } + $3 =3D rvalue_materialize(c, &@1, &$3); + $3 =3D rvalue_truncate(c, &@1, &$3); + /* Extract first 8 bits, and store new predicate value */ + if ($3.type =3D=3D IMMEDIATE) { + OUT(c, &@1, &$3, " =3D (", &$3, " & 0xff) << i;\n"); + OUT(c, &@1, "tcg_gen_ori_i32(", &$1, ", ", &$1, ", ", &$3, ");\n"); + } else { + OUT(c, &@1, "tcg_gen_mov_i32(", &$1, ", ", &$3, ");\n"); + OUT(c, &@1, "tcg_gen_andi_i32(", &$1, ", ", &$1, ", 0xff);\n"); + } + if (is_direct) { + OUT(c, &@1, "gen_log_pred_write(", pre_id, ", ", &$1, ");\n"); + OUT(c, &@1, "ctx_log_pred_write(ctx, ", pre_id, ");\n"); + rvalue_free(c, &@1, &$1); + } + rvalue_free(c, &@1, &$3); /* Free temporary value */ +} +| IMM ASSIGN rvalue +{ + @1.last_column =3D @3.last_column; + yyassert(c, &@1, $3.type =3D=3D IMMEDIATE, + "Cannot assign non-immediate to immediate!"); + yyassert(c, &@1, $1.imm.type =3D=3D VARIABLE, + "Cannot assign to non-variable!"); + /* Assign to the function argument */ + OUT(c, &@1, &$1, " =3D ", &$3, ";\n"); + $$ =3D $1; +} +| PC ASSIGN rvalue +{ + @1.last_column =3D @3.last_column; + $3 =3D rvalue_truncate(c, &@1, &$3); + $3 =3D rvalue_materialize(c, &@1, &$3); + OUT(c, &@1, "gen_write_new_pc(", &$3, ");\n"); + rvalue_free(c, &@1, &$3); /* Free temporary value */ +} +| LOAD LPAR IMM COMMA IMM COMMA SIGN COMMA VAR COMMA lvalue RPAR +{ + @1.last_column =3D @12.last_column; + /* Memop width is specified in the load macro */ + int bit_width =3D ($5.imm.value > 4) ? 64 : 32; + const char *sign_suffix =3D ($5.imm.value > 4) ? "" : (($7) ? "u" : "s= "); + char size_suffix[4] =3D { 0 }; + /* Create temporary variable (if not present) */ + if ($11.type =3D=3D VARID) { + /* TODO: this is a common pattern, the parser should be varid-awar= e. */ + varid_allocate(c, &@1, &$11, bit_width, $7); + } + snprintf(size_suffix, 4, "%" PRIu64, $5.imm.value * 8); + if (bit_width =3D=3D 32) { + $11 =3D rvalue_truncate(c, &@1, &$11); + } else { + $11 =3D rvalue_extend(c, &@1, &$11); + } + if ($9.type =3D=3D VARID) { + int var_id =3D find_variable(c, &@1, &$9); + yyassert(c, &@1, var_id !=3D -1, "Load variable must exist!\n"); + /* We need to enforce the variable size */ + $9.bit_width =3D c->inst.allocated[var_id].bit_width; + } + if ($9.bit_width !=3D 32) { + $9 =3D rvalue_truncate(c, &@1, &$9); + } + OUT(c, &@1, "if (insn->slot =3D=3D 0 && pkt->pkt_has_store_s1) {\n"); + OUT(c, &@1, "process_store(ctx, 1);\n"); + OUT(c, &@1, "}\n"); + OUT(c, &@1, "tcg_gen_qemu_ld", size_suffix, sign_suffix); + OUT(c, &@1, "(", &$11, ", ", &$9, ", 0);\n"); + /* If the var in $9 was truncated it is now a tmp HexValue, so free it= . */ + rvalue_free(c, &@1, &$9); +} +| STORE LPAR IMM COMMA IMM COMMA VAR COMMA rvalue RPAR /* Store primitive = */ +{ + @1.last_column =3D @10.last_column; + /* Memop width is specified in the store macro */ + int mem_width =3D $5.imm.value; + /* Adjust operand bit width to memop bit width */ + if (mem_width < 8) { + $9 =3D rvalue_truncate(c, &@1, &$9); + } else { + $9 =3D rvalue_extend(c, &@1, &$9); + } + if ($7.type =3D=3D VARID) { + int var_id =3D find_variable(c, &@1, &$7); + yyassert(c, &@1, var_id !=3D -1, "Load variable must exist!\n"); + /* We need to enforce the variable size */ + $7.bit_width =3D c->inst.allocated[var_id].bit_width; + } + if ($7.bit_width !=3D 32) { + $7 =3D rvalue_truncate(c, &@1, &$7); + } + $9 =3D rvalue_materialize(c, &@1, &$9); + OUT(c, &@1, "gen_store", &mem_width, "(cpu_env, ", &$7, ", ", &$9); + OUT(c, &@1, ", ctx, insn->slot);\n"); + rvalue_free(c, &@1, &$9); + /* If the var in $7 was truncated it is now a tmp HexValue, so free it= . */ + rvalue_free(c, &@1, &$7); +} +| LPCFG ASSIGN rvalue +{ + @1.last_column =3D @3.last_column; + $3 =3D rvalue_truncate(c, &@1, &$3); + $3 =3D rvalue_materialize(c, &@1, &$3); + OUT(c, &@1, "SET_USR_FIELD(USR_LPCFG, ", &$3, ");\n"); + rvalue_free(c, &@1, &$3); +} +| DEPOSIT LPAR rvalue COMMA rvalue COMMA rvalue RPAR +{ + @1.last_column =3D @8.last_column; + gen_deposit_op(c, &@1, &$5, &$7, &$3, &$1); +} +| SETHALF LPAR rvalue COMMA lvalue COMMA rvalue RPAR +{ + @1.last_column =3D @8.last_column; + yyassert(c, &@1, $3.type =3D=3D IMMEDIATE, + "Deposit index must be immediate!\n"); + if ($5.type =3D=3D VARID) { + int var_id =3D find_variable(c, &@1, &$5); + if (var_id =3D=3D -1) { + HexValue zero =3D gen_imm_value(c, &@1, 0, 64); + zero.is_unsigned =3D true; + $5.bit_width =3D 64; + gen_assign(c, &@1, &$5, &zero); + } else { + /* We need to enforce the variable size (default is 32) */ + $5.bit_width =3D c->inst.allocated[var_id].bit_width; + } + } + gen_deposit_op(c, &@1, &$5, &$7, &$3, &$1); +} +| SETBITS LPAR rvalue COMMA rvalue COMMA rvalue COMMA rvalue RPAR +{ + @1.last_column =3D @10.last_column; + yyassert(c, &@1, $3.type =3D=3D IMMEDIATE && + $3.imm.type =3D=3D VALUE && + $5.type =3D=3D IMMEDIATE && + $5.imm.type =3D=3D VALUE, + "Range deposit needs immediate values!\n"); + int i; + $9 =3D rvalue_truncate(c, &@1, &$9); + for (i =3D $5.imm.value; i <=3D $3.imm.value; ++i) { + OUT(c, &@1, "gen_set_bit(", &i, ", ", &$7, ", ", &$9, ");\n"); + } + rvalue_free(c, &@1, &$3); + rvalue_free(c, &@1, &$5); + rvalue_free(c, &@1, &$7); + rvalue_free(c, &@1, &$9); +} +| INSBITS LPAR lvalue COMMA rvalue COMMA rvalue COMMA rvalue RPAR +{ + @1.last_column =3D @10.last_column; + gen_rdeposit_op(c, &@1, &$3, &$9, &$7, &$5); +} +| IDENTITY LPAR rvalue RPAR +{ + @1.last_column =3D @4.last_column; + $$ =3D $3; +} +; + +control_statement : frame_check { /* does nothing */ } +| cancel_statement { /* does nothing */ } +| if_statement { /* does nothing */ } +| for_statement { /* does nothing */ } +| fpart1_statement { /* does nothing */ } +; + +frame_check : FCHK LPAR rvalue COMMA rvalue RPAR SEMI { + /* does nothing */ + rvalue_free(c, &@1, &$3); + rvalue_free(c, &@1, &$5); +} +; + +cancel_statement : CANC +{ + HexValue slot =3D gen_tmp_value(c, &@1, "insn->slot", 32); + OUT(c, &@1, "gen_cancel(", &slot, ");\n"); + rvalue_free(c, &@1, &slot); +} +; + +if_statement : if_stmt +{ + /* Fix else label */ + OUT(c, &@1, "gen_set_label(if_label_", &$1, ");\n"); +} +| if_stmt ELSE +{ + @1.last_column =3D @2.last_column; + /* Generate label to jump if else is not verified */ + OUT(c, &@1, "TCGLabel *if_label_", &c->inst.if_count, + " =3D gen_new_label();\n"); + $2 =3D c->inst.if_count; + c->inst.if_count++; + /* Jump out of the else statement */ + OUT(c, &@1, "tcg_gen_br(if_label_", &$2, ");\n"); + /* Fix the else label */ + OUT(c, &@1, "gen_set_label(if_label_", &$1, ");\n"); +} +statement +{ + OUT(c, &@1, "gen_set_label(if_label_", &$2, ");\n"); +} +; + +for_statement : FOR LPAR IMM ASSIGN IMM SEMI IMM LT IMM SEMI IMM PLUSPLUS = RPAR +{ + @1.last_column =3D @13.last_column; + OUT(c, &@1, "for (int ", &$3, " =3D ", &$5, "; ", &$7, " < ", &$9); + OUT(c, &@1, "; ", &$11, "++) {\n"); +} +code_block +{ + OUT(c, &@1, "}\n"); +} +; + +for_statement : FOR LPAR IMM ASSIGN IMM SEMI IMM LT IMM SEMI IMM INC IMM R= PAR +{ + @1.last_column =3D @14.last_column; + OUT(c, &@1, "for (int ", &$3, " =3D ", &$5, "; ", &$7, " < ", &$9); + OUT(c, &@1, "; ", &$11, " +=3D ", &$13, ") {\n"); +} +code_block +{ + OUT(c, &@1, "}\n"); +} +; + +fpart1_statement : PART1 +{ + OUT(c, &@1, "if (insn->part1) {\n"); +} +LPAR statements RPAR +{ + @1.last_column =3D @3.last_column; + OUT(c, &@1, "return; }\n"); +} +; + +if_stmt : IF +{ + /* Generate an end label, if false branch to that label */ + OUT(c, &@1, "TCGLabel *if_label_", &c->inst.if_count, + " =3D gen_new_label();\n"); +} +LPAR rvalue RPAR +{ + @1.last_column =3D @3.last_column; + $4 =3D rvalue_materialize(c, &@1, &$4); + const char *bit_suffix =3D ($4.bit_width =3D=3D 64) ? "i64" : "i32"; + OUT(c, &@1, "tcg_gen_brcondi_", bit_suffix, "(TCG_COND_EQ, ", &$4, + ", 0, if_label_", &c->inst.if_count, ");\n"); + rvalue_free(c, &@1, &$4); + $1 =3D c->inst.if_count; + c->inst.if_count++; +} +statement +{ + $$ =3D $1; +} +; + +rvalue : FAIL +{ + @1.last_column =3D @1.last_column; + yyassert(c, &@1, false, "Encountered a FAIL token as rvalue.\n"); +} +| +assign_statement { /* does nothing */ } +| REG +{ + if ($1.reg.type =3D=3D CONTROL) { + $$ =3D gen_read_creg(c, &@1, &$1); + } else { + $$ =3D $1; + } +} +| IMM +{ + $$ =3D $1; +} +| CONSTLL LPAR IMM RPAR +{ + $3.is_unsigned =3D false; + $3.bit_width =3D 64; + $$ =3D $3; +} +| CONSTULL LPAR IMM RPAR +{ + $3.is_unsigned =3D true; + $3.bit_width =3D 64; + $$ =3D $3; +} +| pre +{ + if (is_direct_predicate(&$1)) { + bool is_dotnew =3D $1.is_dotnew; + char predicate_id[2] =3D {$1.pre.id, '\0'}; + char *pre_str =3D (char *) &predicate_id; + $1 =3D gen_tmp_value(c, &@1, "0", 32); + if (is_dotnew) { + OUT(c, &@1, "tcg_gen_mov_i32(", &$1, ", hex_new_pred_value["); + OUT(c, &@1, pre_str, "]);\n"); + } else { + OUT(c, &@1, "gen_read_preg(", &$1, ", ", pre_str, ");\n"); + } + } + $$ =3D $1; +} +| PC +{ + /* Read PC from the CR */ + $$ =3D gen_tmp(c, &@1, 32); + OUT(c, &@1, "tcg_gen_mov_i32(", &$$, ", hex_gpr[HEX_REG_PC]);\n"); +} +| NPC +{ + /* NPC is only read from CALLs, so we can hardcode it at translation t= ime */ + $$ =3D gen_tmp(c, &@1, 32); + OUT(c, &@1, "tcg_gen_movi_i32(", &$$, ", ctx->npc);\n"); +} +| CONSTEXT +{ + HexValue rvalue; + rvalue.type =3D IMMEDIATE; + rvalue.imm.type =3D IMM_CONSTEXT; + rvalue.is_unsigned =3D true; + rvalue.is_dotnew =3D false; + rvalue.is_manual =3D false; + $$ =3D rvalue; +} +| VAR +{ + /* Assign correct bit width and signedness */ + bool found =3D false; + for (int i =3D 0; i < c->inst.allocated_count; i++) { + if (!strcmp($1.var.name, c->inst.allocated[i].name)) { + found =3D true; + free(c->inst.allocated[i].name); + c->inst.allocated[i].name =3D $1.var.name; + $1.bit_width =3D c->inst.allocated[i].bit_width; + $1.is_unsigned =3D c->inst.allocated[i].is_unsigned; + break; + } + } + yyassert(c, &@1, found, "Undefined symbol!\n"); + $$ =3D $1; +} +| MPY LPAR rvalue COMMA rvalue RPAR +{ + @1.last_column =3D @6.last_column; + $3.is_unsigned =3D $1.first_unsigned; + $5.is_unsigned =3D $1.second_unsigned; + $3 =3D gen_cast_op(c, &@1, &$3, $1.first_bit_width * 2); + /* Handle fMPTY3216.. */ + if ($1.first_bit_width =3D=3D 32) { + $5 =3D gen_cast_op(c, &@1, &$5, 64); + } else { + $5 =3D gen_cast_op(c, &@1, &$5, $1.second_bit_width * 2); + } + $$ =3D gen_bin_op(c, &@1, MUL_OP, &$3, &$5); + /* Handle special cases required by the language */ + if ($1.first_bit_width =3D=3D 16 && $1.second_bit_width =3D=3D 16) { + HexValue src_width =3D gen_imm_value(c, &@1, 32, 32); + HexValue dst_width =3D gen_imm_value(c, &@1, 64, 32); + $$ =3D gen_extend_op(c, &@1, &src_width, &dst_width, &$$, + $1.first_unsigned && $1.second_unsigned); + } +} +| rvalue PLUS rvalue +{ + @1.last_column =3D @3.last_column; + $$ =3D gen_bin_op(c, &@1, ADD_OP, &$1, &$3); +} +| rvalue MINUS rvalue +{ + @1.last_column =3D @3.last_column; + $$ =3D gen_bin_op(c, &@1, SUB_OP, &$1, &$3); +} +| rvalue MUL rvalue +{ + @1.last_column =3D @3.last_column; + $$ =3D gen_bin_op(c, &@1, MUL_OP, &$1, &$3); +} +| rvalue POW rvalue +{ + @1.last_column =3D @3.last_column; + /* We assume that this is a shorthand for a shift */ + yyassert(c, &@1, $1.type =3D=3D IMMEDIATE && $1.imm.value =3D=3D 2, + "Exponentiation is not a left shift!\n"); + HexValue one =3D gen_imm_value(c, &@1, 1, 32); + HexValue shift =3D gen_bin_op(c, &@1, SUB_OP, &$3, &one); + $$ =3D gen_bin_op(c, &@1, ASL_OP, &$1, &shift); + rvalue_free(c, &@1, &one); + rvalue_free(c, &@1, &shift); +} +| rvalue DIV rvalue +{ + @1.last_column =3D @3.last_column; + $$ =3D gen_bin_op(c, &@1, DIV_OP, &$1, &$3); +} +| rvalue MOD rvalue +{ + @1.last_column =3D @3.last_column; + $$ =3D gen_bin_op(c, &@1, MOD_OP, &$1, &$3); +} +| rvalue ASL rvalue +{ + @1.last_column =3D @3.last_column; + $$ =3D gen_bin_op(c, &@1, ASL_OP, &$1, &$3); +} +| rvalue ASR rvalue +{ + @1.last_column =3D @3.last_column; + if ($1.is_unsigned) { + $$ =3D gen_bin_op(c, &@1, LSR_OP, &$1, &$3); + } else { + $$ =3D gen_bin_op(c, &@1, ASR_OP, &$1, &$3); + } +} +| rvalue LSR rvalue +{ + @1.last_column =3D @3.last_column; + $$ =3D gen_bin_op(c, &@1, LSR_OP, &$1, &$3); +} +| rvalue AND rvalue +{ + @1.last_column =3D @3.last_column; + $$ =3D gen_bin_op(c, &@1, ANDB_OP, &$1, &$3); +} +| rvalue OR rvalue +{ + @1.last_column =3D @3.last_column; + $$ =3D gen_bin_op(c, &@1, ORB_OP, &$1, &$3); +} +| rvalue XOR rvalue +{ + @1.last_column =3D @3.last_column; + $$ =3D gen_bin_op(c, &@1, XORB_OP, &$1, &$3); +} +| rvalue ANDL rvalue +{ + @1.last_column =3D @3.last_column; + $$ =3D gen_bin_op(c, &@1, ANDL_OP, &$1, &$3); +} +| MIN LPAR rvalue COMMA rvalue RPAR +{ + @1.last_column =3D @3.last_column; + $$ =3D gen_bin_op(c, &@1, MINI_OP, &$3, &$5); +} +| MAX LPAR rvalue COMMA rvalue RPAR +{ + @1.last_column =3D @3.last_column; + $$ =3D gen_bin_op(c, &@1, MAXI_OP, &$3, &$5); +} +| NOT rvalue +{ + @1.last_column =3D @2.last_column; + const char *bit_suffix =3D ($2.bit_width =3D=3D 64) ? "i64" : "i32"; + int bit_width =3D ($2.bit_width =3D=3D 64) ? 64 : 32; + HexValue res; + res.is_unsigned =3D $2.is_unsigned; + res.is_dotnew =3D false; + res.is_manual =3D false; + if ($2.type =3D=3D IMMEDIATE) { + res.type =3D IMMEDIATE; + res.imm.type =3D QEMU_TMP; + res.imm.index =3D c->inst.qemu_tmp_count; + OUT(c, &@1, "int", &bit_width, "_t ", &res, " =3D ~", &$2, ";\n"); + c->inst.qemu_tmp_count++; + } else { + res =3D gen_tmp(c, &@1, bit_width); + OUT(c, &@1, "tcg_gen_not_", bit_suffix, "(", &res, + ", ", &$2, ");\n"); + rvalue_free(c, &@1, &$2); + } + $$ =3D res; +} +| NOTL rvalue +{ + @1.last_column =3D @2.last_column; + const char *bit_suffix =3D ($2.bit_width =3D=3D 64) ? "i64" : "i32"; + int bit_width =3D ($2.bit_width =3D=3D 64) ? 64 : 32; + HexValue res; + res.is_unsigned =3D $2.is_unsigned; + res.is_dotnew =3D false; + res.is_manual =3D false; + if ($2.type =3D=3D IMMEDIATE) { + res.type =3D IMMEDIATE; + res.imm.type =3D QEMU_TMP; + res.imm.index =3D c->inst.qemu_tmp_count; + OUT(c, &@1, "int", &bit_width, "_t ", &res, " =3D !", &$2, ";\n"); + c->inst.qemu_tmp_count++; + $$ =3D res; + } else { + res =3D gen_tmp(c, &@1, bit_width); + HexValue zero =3D gen_tmp_value(c, &@1, "0", bit_width); + HexValue one =3D gen_tmp_value(c, &@1, "0xff", bit_width); + OUT(c, &@1, "tcg_gen_movcond_", bit_suffix); + OUT(c, &@1, "(TCG_COND_EQ, ", &res, ", ", &$2, ", ", &zero); + OUT(c, &@1, ", ", &one, ", ", &zero, ");\n"); + rvalue_free(c, &@1, &$2); + rvalue_free(c, &@1, &zero); + rvalue_free(c, &@1, &one); + $$ =3D res; + } +} +| SAT LPAR IMM COMMA rvalue RPAR +{ + @1.last_column =3D @6.last_column; + if ($1.set_overflow) { + yyassert(c, &@1, $3.imm.value < $5.bit_width, "To compute overflow= , " + "source width must be greater than saturation width!"); + } + HexValue res =3D gen_tmp(c, &@1, $5.bit_width); + const char *bit_suffix =3D ($5.bit_width =3D=3D 64) ? "i64" : "i32"; + const char *overflow_str =3D ($1.set_overflow) ? "true" : "false"; + const char *unsigned_str =3D ($1.is_unsigned) ? "u" : ""; + OUT(c, &@1, "gen_sat", unsigned_str, "_", bit_suffix, "(", &res, ", "); + OUT(c, &@1, &$5, ", ", &$3.imm.value, ", ", overflow_str, ");\n"); + res.is_unsigned =3D $1.is_unsigned; + rvalue_free(c, &@1, &$5); + $$ =3D res; +} +| CAST rvalue +{ + @1.last_column =3D @2.last_column; + /* Assign target signedness */ + $2.is_unsigned =3D $1.is_unsigned; + $$ =3D gen_cast_op(c, &@1, &$2, $1.bit_width); + $$.is_unsigned =3D $1.is_unsigned; +} +| rvalue LSQ rvalue RSQ +{ + @1.last_column =3D @4.last_column; + HexValue one =3D gen_imm_value(c, &@1, 1, $3.bit_width); + HexValue tmp =3D gen_bin_op(c, &@1, ASR_OP, &$1, &$3); + $$ =3D gen_bin_op(c, &@1, ANDB_OP, &tmp, &one); +} +| rvalue EQ rvalue +{ + @1.last_column =3D @3.last_column; + $$ =3D gen_bin_cmp(c, &@1, "TCG_COND_EQ", &$1, &$3); +} +| rvalue NEQ rvalue +{ + @1.last_column =3D @3.last_column; + $$ =3D gen_bin_cmp(c, &@1, "TCG_COND_NE", &$1, &$3); +} +| rvalue LT rvalue +{ + @1.last_column =3D @3.last_column; + if ($1.is_unsigned || $3.is_unsigned) { + $$ =3D gen_bin_cmp(c, &@1, "TCG_COND_LTU", &$1, &$3); + } else { + $$ =3D gen_bin_cmp(c, &@1, "TCG_COND_LT", &$1, &$3); + } +} +| rvalue GT rvalue +{ + @1.last_column =3D @3.last_column; + if ($1.is_unsigned || $3.is_unsigned) { + $$ =3D gen_bin_cmp(c, &@1, "TCG_COND_GTU", &$1, &$3); + } else { + $$ =3D gen_bin_cmp(c, &@1, "TCG_COND_GT", &$1, &$3); + } +} +| rvalue LTE rvalue +{ + @1.last_column =3D @3.last_column; + if ($1.is_unsigned || $3.is_unsigned) { + $$ =3D gen_bin_cmp(c, &@1, "TCG_COND_LEU", &$1, &$3); + } else { + $$ =3D gen_bin_cmp(c, &@1, "TCG_COND_LE", &$1, &$3); + } +} +| rvalue GTE rvalue +{ + @1.last_column =3D @3.last_column; + if ($1.is_unsigned || $3.is_unsigned) { + $$ =3D gen_bin_cmp(c, &@1, "TCG_COND_GEU", &$1, &$3); + } else { + $$ =3D gen_bin_cmp(c, &@1, "TCG_COND_GE", &$1, &$3); + } +} +| rvalue QMARK rvalue COLON rvalue +{ + @1.last_column =3D @5.last_column; + bool is_64bit =3D ($3.bit_width =3D=3D 64) || ($5.bit_width =3D=3D 64); + int bit_width =3D (is_64bit) ? 64 : 32; + if (is_64bit) { + $1 =3D rvalue_extend(c, &@1, &$1); + $3 =3D rvalue_extend(c, &@1, &$3); + $5 =3D rvalue_extend(c, &@1, &$5); + } else { + $1 =3D rvalue_truncate(c, &@1, &$1); + } + $1 =3D rvalue_materialize(c, &@1, &$1); + $3 =3D rvalue_materialize(c, &@1, &$3); + $5 =3D rvalue_materialize(c, &@1, &$5); + HexValue res =3D gen_local_tmp(c, &@1, bit_width); + HexValue zero =3D gen_tmp_value(c, &@1, "0", bit_width); + OUT(c, &@1, "tcg_gen_movcond_i", &bit_width); + OUT(c, &@1, "(TCG_COND_NE, ", &res, ", ", &$1, ", ", &zero); + OUT(c, &@1, ", ", &$3, ", ", &$5, ");\n"); + rvalue_free(c, &@1, &zero); + rvalue_free(c, &@1, &$1); + rvalue_free(c, &@1, &$3); + rvalue_free(c, &@1, &$5); + $$ =3D res; +} +| FSCR LPAR rvalue RPAR +{ + @1.last_column =3D @4.last_column; + HexValue key =3D gen_tmp(c, &@1, 64); + HexValue res =3D gen_tmp(c, &@1, 64); + $3 =3D rvalue_extend(c, &@1, &$3); + HexValue frame_key =3D gen_tmp(c, &@1, 32); + OUT(c, &@1, "READ_REG(", &frame_key, ", HEX_REG_FRAMEKEY);\n"); + OUT(c, &@1, "tcg_gen_concat_i32_i64(", + &key, ", ", &frame_key, ", ", &frame_key, ");\n"); + OUT(c, &@1, "tcg_gen_xor_i64(", &res, ", ", &$3, ", ", &key, ");\n"); + rvalue_free(c, &@1, &key); + rvalue_free(c, &@1, &frame_key); + rvalue_free(c, &@1, &$3); + $$ =3D res; +} +| SXT LPAR rvalue COMMA IMM COMMA rvalue RPAR +{ + @1.last_column =3D @8.last_column; + yyassert(c, &@1, $5.type =3D=3D IMMEDIATE && + $5.imm.type =3D=3D VALUE, + "SXT expects immediate values\n"); + $5.imm.value =3D 64; + $$ =3D gen_extend_op(c, &@1, &$3, &$5, &$7, false); +} +| ZXT LPAR rvalue COMMA IMM COMMA rvalue RPAR +{ + @1.last_column =3D @8.last_column; + yyassert(c, &@1, $5.type =3D=3D IMMEDIATE && + $5.imm.type =3D=3D VALUE, + "ZXT expects immediate values\n"); + $$ =3D gen_extend_op(c, &@1, &$3, &$5, &$7, true); +} +| LPAR rvalue RPAR +{ + $$ =3D $2; +} +| ABS rvalue +{ + @1.last_column =3D @2.last_column; + const char *bit_suffix =3D ($2.bit_width =3D=3D 64) ? "i64" : "i32"; + int bit_width =3D ($2.bit_width =3D=3D 64) ? 64 : 32; + HexValue res; + res.is_unsigned =3D $2.is_unsigned; + res.is_dotnew =3D false; + res.is_manual =3D false; + if ($2.type =3D=3D IMMEDIATE) { + res.type =3D IMMEDIATE; + res.imm.type =3D QEMU_TMP; + res.imm.index =3D c->inst.qemu_tmp_count; + OUT(c, &@1, "int", &bit_width, "_t ", &res, " =3D abs(", &$2, ");\= n"); + c->inst.qemu_tmp_count++; + $$ =3D res; + } else { + res =3D gen_tmp(c, &@1, bit_width); + HexValue zero =3D gen_tmp_value(c, &@1, "0", bit_width); + OUT(c, &@1, "tcg_gen_neg_", bit_suffix, "(", &res, ", ", + &$2, ");\n"); + OUT(c, &@1, "tcg_gen_movcond_i", &bit_width); + OUT(c, &@1, "(TCG_COND_GT, ", &res, ", ", &$2, ", ", &zero); + OUT(c, &@1, ", ", &$2, ", ", &res, ");\n"); + rvalue_free(c, &@1, &zero); + rvalue_free(c, &@1, &$2); + $$ =3D res; + } +} +| CROUND LPAR rvalue COMMA rvalue RPAR +{ + @1.last_column =3D @6.last_column; + $$ =3D gen_convround_n(c, &@1, &$3, &$5); +} +| CROUND LPAR rvalue RPAR +{ + @1.last_column =3D @4.last_column; + $$ =3D gen_convround(c, &@1, &$3); +} +| ROUND LPAR rvalue COMMA rvalue RPAR +{ + @1.last_column =3D @6.last_column; + $$ =3D gen_round(c, &@1, &$3, &$5); +} +| MINUS rvalue +{ + @1.last_column =3D @2.last_column; + const char *bit_suffix =3D ($2.bit_width =3D=3D 64) ? "i64" : "i32"; + int bit_width =3D ($2.bit_width =3D=3D 64) ? 64 : 32; + HexValue res; + res.is_unsigned =3D $2.is_unsigned; + res.is_dotnew =3D false; + res.is_manual =3D false; + if ($2.type =3D=3D IMMEDIATE) { + res.type =3D IMMEDIATE; + res.imm.type =3D QEMU_TMP; + res.imm.index =3D c->inst.qemu_tmp_count; + OUT(c, &@1, "int", &bit_width, "_t ", &res, " =3D -", &$2, ";\n"); + c->inst.qemu_tmp_count++; + $$ =3D res; + } else { + res =3D gen_tmp(c, &@1, bit_width); + OUT(c, &@1, "tcg_gen_neg_", bit_suffix, "(", &res, ", ", + &$2, ");\n"); + rvalue_free(c, &@1, &$2); + $$ =3D res; + } +} +| ICIRC LPAR rvalue RPAR ASL IMM +{ + @1.last_column =3D @6.last_column; + $$ =3D gen_tmp(c, &@1, 32); + OUT(c, &@1, "gen_read_ireg(", &$$, ", ", &$3, ", ", &$6, ");\n"); + rvalue_free(c, &@1, &$3); +} +| CIRCADD LPAR rvalue COMMA rvalue COMMA rvalue RPAR +{ + @1.last_column =3D @8.last_column; + $$ =3D gen_circ_op(c, &@1, &$3, &$5, &$7); +} +| LOCNT LPAR rvalue RPAR +{ + @1.last_column =3D @4.last_column; + /* Leading ones count */ + $$ =3D gen_locnt_op(c, &@1, &$3); +} +| COUNTONES LPAR rvalue RPAR +{ + @1.last_column =3D @4.last_column; + /* Ones count */ + $$ =3D gen_ctpop_op(c, &@1, &$3); +} +| LPCFG +{ + $$ =3D gen_tmp_value(c, &@1, "0", 32); + OUT(c, &@1, "tcg_gen_extract_tl(", &$$, ", hex_gpr[HEX_REG_USR], "); + OUT(c, &@1, "reg_field_info[USR_LPCFG].offset, "); + OUT(c, &@1, "reg_field_info[USR_LPCFG].width);\n"); +} +| EXTRACT LPAR rvalue COMMA rvalue RPAR +{ + @1.last_column =3D @6.last_column; + $$ =3D gen_extract_op(c, &@1, &$5, &$3, &$1); +} +| EXTBITS LPAR rvalue COMMA rvalue COMMA rvalue RPAR +{ + @1.last_column =3D @8.last_column; + yyassert(c, &@1, $5.type =3D=3D IMMEDIATE && + $5.imm.type =3D=3D VALUE && + $7.type =3D=3D IMMEDIATE && + $7.imm.type =3D=3D VALUE, + "Range extract needs immediate values!\n"); + $$ =3D gen_rextract_op(c, &@1, &$3, $7.imm.value, $5.imm.value); +} +| EXTRANGE LPAR rvalue COMMA rvalue COMMA rvalue RPAR +{ + @1.last_column =3D @8.last_column; + yyassert(c, &@1, $5.type =3D=3D IMMEDIATE && + $5.imm.type =3D=3D VALUE && + $7.type =3D=3D IMMEDIATE && + $7.imm.type =3D=3D VALUE, + "Range extract needs immediate values!\n"); + $$ =3D gen_rextract_op(c, + &@1, + &$3, + $7.imm.value, + $5.imm.value - $7.imm.value + 1); +} +| CAST4_8U LPAR rvalue RPAR +{ + @1.last_column =3D @4.last_column; + $$ =3D rvalue_truncate(c, &@1, &$3); + $$.is_unsigned =3D true; + $$ =3D rvalue_materialize(c, &@1, &$$); + $$ =3D rvalue_extend(c, &@1, &$$); +} +| BREV LPAR rvalue RPAR +{ + @1.last_column =3D @4.last_column; + yyassert(c, &@1, $3.bit_width <=3D 32, + "fbrev not implemented for 64-bit integers!"); + HexValue res =3D gen_tmp(c, &@1, $3.bit_width); + $3 =3D rvalue_materialize(c, &@1, &$3); + OUT(c, &@1, "gen_fbrev(", &res, ", ", &$3, ");\n"); + rvalue_free(c, &@1, &$3); + $$ =3D res; +} +| BREV_4 LPAR rvalue RPAR +{ + @1.last_column =3D @4.last_column; + $$ =3D gen_fbrev_4(c, &@1, &$3); +} +| BREV_8 LPAR rvalue RPAR +{ + @1.last_column =3D @4.last_column; + $$ =3D gen_fbrev_8(c, &@1, &$3); +} +| ROTL LPAR rvalue COMMA rvalue RPAR +{ + @1.last_column =3D @6.last_column; + $$ =3D gen_rotl(c, &@1, &$3, &$5); +} +| SETOVF LPAR RPAR +{ + @1.last_column =3D @3.last_column; + OUT(c, &@1, "gen_set_usr_fieldi(USR_OVF, 1);\n"); +} +| SETOVF LPAR rvalue RPAR +{ + /* Convenience fSET_OVERFLOW with pass-through */ + @1.last_column =3D @3.last_column; + OUT(c, &@1, "gen_set_usr_fieldi(USR_OVF, 1);\n"); + $$ =3D $3; +} +| DEINTERLEAVE LPAR rvalue RPAR +{ + @1.last_column =3D @4.last_column; + $$ =3D gen_deinterleave(c, &@1, &$3); +} +| INTERLEAVE LPAR rvalue COMMA rvalue RPAR +{ + @1.last_column =3D @6.last_column; + $$ =3D gen_interleave(c, &@1, &$3, &$5); +} +; + +pre : PRE +{ + $$ =3D $1; +} +| pre NEW +{ + $$ =3D $1; + $$.is_dotnew =3D true; +} +; + +lvalue : FAIL +{ + @1.last_column =3D @1.last_column; + yyassert(c, &@1, false, "Encountered a FAIL token as lvalue.\n"); +} +| REG +{ + $$ =3D $1; +} +| VAR +{ + $$ =3D $1; +} +; + +%% + +int main(int argc, char **argv) +{ + if (argc !=3D 5) { + fprintf(stderr, + "Semantics: Hexagon ISA to tinycode generator compiler\n\n= "); + fprintf(stderr, + "Usage: ./semantics IDEFS EMITTER_C EMITTER_H " + "ENABLED_INSTRUCTIONS_LIST\n"); + return 1; + } + + enum { + ARG_INDEX_ARGV0 =3D 0, + ARG_INDEX_IDEFS, + ARG_INDEX_EMITTER_C, + ARG_INDEX_EMITTER_H, + ARG_INDEX_ENABLED_INSTRUCTIONS_LIST + }; + + FILE *enabled_file =3D fopen(argv[ARG_INDEX_ENABLED_INSTRUCTIONS_LIST]= , "w"); + + FILE *output_file =3D fopen(argv[ARG_INDEX_EMITTER_C], "w"); + fputs("#include \"qemu/osdep.h\"\n", output_file); + fputs("#include \"qemu/log.h\"\n", output_file); + fputs("#include \"cpu.h\"\n", output_file); + fputs("#include \"internal.h\"\n", output_file); + fputs("#include \"tcg/tcg-op.h\"\n", output_file); + fputs("#include \"insn.h\"\n", output_file); + fputs("#include \"opcodes.h\"\n", output_file); + fputs("#include \"translate.h\"\n", output_file); + fputs("#define QEMU_GENERATE\n", output_file); + fputs("#include \"genptr.h\"\n", output_file); + fputs("#include \"tcg/tcg.h\"\n", output_file); + fputs("#include \"macros.h\"\n", output_file); + fprintf(output_file, "#include \"%s\"\n", argv[ARG_INDEX_EMITTER_H]); + + FILE *defines_file =3D fopen(argv[ARG_INDEX_EMITTER_H], "w"); + assert(defines_file !=3D NULL); + fputs("#ifndef HEX_EMITTER_H\n", defines_file); + fputs("#define HEX_EMITTER_H\n", defines_file); + fputs("\n", defines_file); + fputs("#include \"insn.h\"\n\n", defines_file); + + /* Parser input file */ + Context context =3D { 0 }; + context.defines_file =3D defines_file; + context.output_file =3D output_file; + context.enabled_file =3D enabled_file; + /* Initialize buffers */ + context.out_buffer =3D (char *) calloc(OUT_BUF_LEN, sizeof(char)); + context.signature_buffer =3D (char *) calloc(SIGNATURE_BUF_LEN, sizeof= (char)); + context.header_buffer =3D (char *) calloc(HEADER_BUF_LEN, sizeof(char)= ); + /* Read input file */ + FILE *input_file =3D fopen(argv[ARG_INDEX_IDEFS], "r"); + fseek(input_file, 0L, SEEK_END); + long input_size =3D ftell(input_file); + context.input_buffer =3D (char *) calloc(input_size + 1, sizeof(char)); + fseek(input_file, 0L, SEEK_SET); + size_t read_chars =3D fread(context.input_buffer, + sizeof(char), + input_size, + input_file); + if (read_chars !=3D input_size) { + fprintf(stderr, "Error: an error occurred while reading input file= !\n"); + return -1; + } + yylex_init(&context.scanner); + YY_BUFFER_STATE buffer; + buffer =3D yy_scan_string(context.input_buffer, context.scanner); + /* Start the parsing procedure */ + yyparse(context.scanner, &context); + fprintf(stderr, "%d/%d meta instructions have been implemented!\n", + context.implemented_insn, + context.total_insn); + fputs("#endif " START_COMMENT " HEX_EMITTER_h " END_COMMENT "\n", + defines_file); + /* Cleanup */ + yy_delete_buffer(buffer, context.scanner); + yylex_destroy(context.scanner); + fclose(output_file); + fclose(input_file); + fclose(defines_file); + fclose(enabled_file); + free(context.input_buffer); + free(context.out_buffer); + free(context.signature_buffer); + + return 0; +} diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/i= def-parser/parser-helpers.c new file mode 100644 index 0000000000..368c8b4928 --- /dev/null +++ b/target/hexagon/idef-parser/parser-helpers.c @@ -0,0 +1,1925 @@ +/* + * Copyright(c) 2019-2020 rev.ng Srls. All Rights Reserved. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; withOUT even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "idef-parser.h" +#include "parser-helpers.h" +#include "idef-parser.tab.h" +#include "idef-parser.yy.h" + +const char *COND_EQ =3D "TCG_COND_EQ"; +const char *COND_NE =3D "TCG_COND_NE"; +const char *COND_GT =3D "TCG_COND_GT"; +const char *COND_LT =3D "TCG_COND_LT"; +const char *COND_GE =3D "TCG_COND_GE"; +const char *COND_LE =3D "TCG_COND_LE"; +const char *COND_GTU =3D "TCG_COND_GTU"; +const char *COND_LTU =3D "TCG_COND_LTU"; +const char *COND_GEU =3D "TCG_COND_GEU"; +const char *COND_LEU =3D "TCG_COND_LEU"; + +const char *creg_str[] =3D {"HEX_REG_SP", "HEX_REG_FP", "HEX_REG_LR", + "HEX_REG_GP", "HEX_REG_LC0", "HEX_REG_LC1", + "HEX_REG_SA0", "HEX_REG_SA1"}; + +void yyerror(YYLTYPE *locp, + yyscan_t scanner __attribute__((unused)), + Context *c, + const char *s) +{ + const char *code_ptr =3D c->input_buffer; + + fprintf(stderr, "WARNING (%s): '%s'\n", c->inst.name, s); + + fprintf(stderr, "Problematic range: "); + for (int i =3D locp->first_column; i < locp->last_column; i++) { + if (code_ptr[i] !=3D '\n') { + fprintf(stderr, "%c", code_ptr[i]); + } + } + fprintf(stderr, "\n"); + + for (int i =3D 0; + i < 80 && + code_ptr[locp->first_column - 10 + i] !=3D '\0' && + code_ptr[locp->first_column - 10 + i] !=3D '\n'; + i++) { + fprintf(stderr, "%c", code_ptr[locp->first_column - 10 + i]); + } + fprintf(stderr, "\n"); + for (int i =3D 0; i < 9; i++) { + fprintf(stderr, " "); + } + fprintf(stderr, "^"); + for (int i =3D 0; i < (locp->last_column - locp->first_column) - 1; i+= +) { + fprintf(stderr, "~"); + } + fprintf(stderr, "\n"); + c->inst.error_count++; +} + +bool is_direct_predicate(HexValue *value) +{ + return value->pre.id >=3D '0' && value->pre.id <=3D '3'; +} + +/* Print functions */ +void str_print(Context *c, YYLTYPE *locp, char *string) +{ + EMIT(c, "%s", string); +} + + +void uint64_print(Context *c, YYLTYPE *locp, uint64_t *num) +{ + EMIT(c, "%" PRIu64, *num); +} + +void int_print(Context *c, YYLTYPE *locp, int *num) +{ + EMIT(c, "%d", *num); +} + +void uint_print(Context *c, YYLTYPE *locp, unsigned *num) +{ + EMIT(c, "%u", *num); +} + +void tmp_print(Context *c, YYLTYPE *locp, HexTmp *tmp) +{ + EMIT(c, "tmp_"); + EMIT(c, "%d", tmp->index); +} + +void pre_print(Context *c, YYLTYPE *locp, HexPre *pre, bool is_dotnew) +{ + char suffix =3D is_dotnew ? 'N' : 'V'; + EMIT(c, "P%c%c", pre->id, suffix); +} + +void reg_compose(Context *c, YYLTYPE *locp, HexReg *reg, char reg_id[5]) +{ + switch (reg->type) { + case GENERAL_PURPOSE: + reg_id[0] =3D 'R'; + break; + case CONTROL: + reg_id[0] =3D 'C'; + break; + case MODIFIER: + reg_id[0] =3D 'M'; + break; + case DOTNEW: + /* The DOTNEW case is managed by the upper level function */ + break; + } + switch (reg->bit_width) { + case 32: + reg_id[1] =3D reg->id; + reg_id[2] =3D 'V'; + break; + case 64: + reg_id[1] =3D reg->id; + reg_id[2] =3D reg->id; + reg_id[3] =3D 'V'; + break; + default: + yyassert(c, locp, false, "Unhandled register bit width!\n"); + } +} + +void reg_print(Context *c, YYLTYPE *locp, HexReg *reg) +{ + if (reg->type =3D=3D DOTNEW) { + EMIT(c, "N%cN", reg->id); + } else { + char reg_id[5] =3D { 0 }; + reg_compose(c, locp, reg, reg_id); + EMIT(c, "%s", reg_id); + } +} + +void imm_print(Context *c, YYLTYPE *locp, HexImm *imm) +{ + switch (imm->type) { + case I: + EMIT(c, "i"); + break; + case VARIABLE: + EMIT(c, "%ciV", imm->id); + break; + case VALUE: + EMIT(c, "((int64_t)%" PRIu64 "ULL)", (int64_t)imm->value); + break; + case QEMU_TMP: + EMIT(c, "qemu_tmp_%" PRIu64, imm->index); + break; + case IMM_PC: + EMIT(c, "dc->pc"); + break; + case IMM_CONSTEXT: + EMIT(c, "insn->extension_valid"); + break; + default: + yyassert(c, locp, false, "Cannot print this expression!"); + } +} + +void var_print(Context *c, YYLTYPE *locp, HexVar *var) +{ + EMIT(c, "%s", var->name); +} + +void rvalue_out(Context *c, YYLTYPE *locp, void *pointer) +{ + HexValue *rvalue =3D (HexValue *) pointer; + switch (rvalue->type) { + case REGISTER: + reg_print(c, locp, &rvalue->reg); + break; + case TEMP: + tmp_print(c, locp, &rvalue->tmp); + break; + case IMMEDIATE: + imm_print(c, locp, &rvalue->imm); + break; + case VARID: + var_print(c, locp, &rvalue->var); + break; + case PREDICATE: + pre_print(c, locp, &rvalue->pre, rvalue->is_dotnew); + break; + default: + yyassert(c, locp, false, "Cannot print this expression!"); + } +} + +/* Copy output code buffer */ +void commit(Context *c) +{ + /* Emit instruction pseudocode */ + EMIT_SIG(c, "\n" START_COMMENT " "); + for (char *x =3D c->inst.code_begin; x < c->inst.code_end; x++) { + EMIT_SIG(c, "%c", *x); + } + EMIT_SIG(c, " " END_COMMENT "\n"); + + /* Commit instruction code to output file */ + fwrite(c->signature_buffer, sizeof(char), c->signature_c, c->output_fi= le); + fwrite(c->header_buffer, sizeof(char), c->header_c, c->output_file); + fwrite(c->out_buffer, sizeof(char), c->out_c, c->output_file); + + fwrite(c->signature_buffer, sizeof(char), c->signature_c, c->defines_f= ile); + fprintf(c->defines_file, ";\n"); +} + +const char *cmp_swap(Context *c, YYLTYPE *locp, const char *type) +{ + if (type =3D=3D COND_EQ) { + return COND_EQ; + } else if (type =3D=3D COND_NE) { + return COND_NE; + } else if (type =3D=3D COND_GT) { + return COND_LT; + } else if (type =3D=3D COND_LT) { + return COND_GT; + } else if (type =3D=3D COND_GE) { + return COND_LE; + } else if (type =3D=3D COND_LE) { + return COND_GE; + } else if (type =3D=3D COND_GTU) { + return COND_LTU; + } else if (type =3D=3D COND_LTU) { + return COND_GTU; + } else if (type =3D=3D COND_GEU) { + return COND_LEU; + } else if (type =3D=3D COND_LEU) { + return COND_GEU; + } else { + yyassert(c, locp, false, "Unhandled comparison swap!"); + return NULL; + } +} + +/* Temporary values creation */ +static inline HexValue gen_tmp_impl(Context *c, + YYLTYPE *locp, + int bit_width, + bool is_local) +{ + HexValue rvalue; + rvalue.type =3D TEMP; + bit_width =3D (bit_width =3D=3D 64) ? 64 : 32; + rvalue.bit_width =3D bit_width; + rvalue.is_unsigned =3D false; + rvalue.is_dotnew =3D false; + rvalue.is_manual =3D false; + rvalue.tmp.index =3D c->inst.tmp_count; + const char *suffix =3D is_local ? "local_" : ""; + OUT(c, locp, "TCGv_i", &bit_width, " tmp_", &c->inst.tmp_count, + " =3D tcg_temp_", suffix, "new_i", &bit_width, "();\n"); + c->inst.tmp_count++; + return rvalue; +} + +HexValue gen_tmp(Context *c, YYLTYPE *locp, int bit_width) +{ + return gen_tmp_impl(c, locp, bit_width, false); +} + +HexValue gen_local_tmp(Context *c, YYLTYPE *locp, int bit_width) +{ + return gen_tmp_impl(c, locp, bit_width, true); +} + +HexValue gen_tmp_value(Context *c, + YYLTYPE *locp, + const char *value, + int bit_width) +{ + HexValue rvalue; + rvalue.type =3D TEMP; + rvalue.bit_width =3D bit_width; + rvalue.is_unsigned =3D false; + rvalue.is_dotnew =3D false; + rvalue.is_manual =3D false; + rvalue.tmp.index =3D c->inst.tmp_count; + OUT(c, locp, "TCGv_i", &bit_width, " tmp_", &c->inst.tmp_count, + " =3D tcg_const_i", &bit_width, "(", value, ");\n"); + c->inst.tmp_count++; + return rvalue; +} + +HexValue gen_imm_value(Context *c __attribute__((unused)), + YYLTYPE *locp, + int value, + int bit_width) +{ + HexValue rvalue; + rvalue.type =3D IMMEDIATE; + rvalue.bit_width =3D bit_width; + rvalue.is_unsigned =3D false; + rvalue.is_dotnew =3D false; + rvalue.is_manual =3D false; + rvalue.imm.type =3D VALUE; + rvalue.imm.value =3D value; + return rvalue; +} + +void rvalue_free(Context *c, YYLTYPE *locp, HexValue *rvalue) +{ + if (rvalue->type =3D=3D TEMP && !rvalue->is_manual) { + const char *bit_suffix =3D (rvalue->bit_width =3D=3D 64) ? "i64" := "i32"; + OUT(c, locp, "tcg_temp_free_", bit_suffix, "(", rvalue, ");\n"); + } +} + +static void rvalue_free_manual(Context *c, YYLTYPE *locp, HexValue *rvalue) +{ + rvalue->is_manual =3D false; + rvalue_free(c, locp, rvalue); +} + +static void rvalue_free_ext(Context *c, YYLTYPE *locp, HexValue *rvalue, + bool free_manual) { + if (free_manual) { + rvalue_free_manual(c, locp, rvalue); + } else { + rvalue_free(c, locp, rvalue); + } +} + +HexValue rvalue_materialize(Context *c, YYLTYPE *locp, HexValue *rvalue) +{ + if (rvalue->type =3D=3D IMMEDIATE) { + HexValue tmp =3D gen_tmp(c, locp, rvalue->bit_width); + tmp.is_unsigned =3D rvalue->is_unsigned; + const char *bit_suffix =3D (rvalue->bit_width =3D=3D 64) ? "i64" := "i32"; + OUT(c, locp, "tcg_gen_movi_", bit_suffix, + "(", &tmp, ", ", rvalue, ");\n"); + rvalue_free(c, locp, rvalue); + return tmp; + } + return *rvalue; +} + +HexValue rvalue_extend(Context *c, YYLTYPE *locp, HexValue *rvalue) +{ + if (rvalue->type =3D=3D IMMEDIATE) { + HexValue res =3D *rvalue; + res.bit_width =3D 64; + return res; + } else { + if (rvalue->bit_width =3D=3D 32) { + HexValue res =3D gen_tmp(c, locp, 64); + const char *sign_suffix =3D (rvalue->is_unsigned) ? "u" : ""; + OUT(c, locp, "tcg_gen_ext", sign_suffix, + "_i32_i64(", &res, ", ", rvalue, ");\n"); + rvalue_free(c, locp, rvalue); + return res; + } + } + return *rvalue; +} + +HexValue rvalue_truncate(Context *c, YYLTYPE *locp, HexValue *rvalue) +{ + if (rvalue->type =3D=3D IMMEDIATE) { + HexValue res =3D *rvalue; + res.bit_width =3D 32; + return res; + } else { + if (rvalue->bit_width =3D=3D 64) { + HexValue res =3D gen_tmp(c, locp, 32); + OUT(c, locp, "tcg_gen_trunc_i64_tl(", &res, ", ", rvalue, ");\= n"); + rvalue_free(c, locp, rvalue); + return res; + } + } + return *rvalue; +} + +int find_variable(Context *c, YYLTYPE *locp, HexValue *varid) +{ + for (int i =3D 0; i < c->inst.allocated_count; i++) { + if (!strcmp(varid->var.name, c->inst.allocated[i].name)) { + return i; + } + } + return -1; +} + +void varid_allocate(Context *c, + YYLTYPE *locp, + HexValue *varid, + int width, + bool is_unsigned) +{ + varid->bit_width =3D width; + const char *bit_suffix =3D width =3D=3D 64 ? "64" : "32"; + yyassert(c, locp, c->inst.allocated_count < ALLOC_LIST_LEN, + "Too many automatic variables required!"); + int index =3D find_variable(c, locp, varid); + bool found =3D index !=3D -1; + if (found) { + free((char *) varid->var.name); + varid->var.name =3D c->inst.allocated[index].name; + varid->bit_width =3D c->inst.allocated[index].bit_width; + varid->is_unsigned =3D c->inst.allocated[index].is_unsigned; + } else { + EMIT_HEAD(c, "TCGv_i%s %s", bit_suffix, varid->var.name); + EMIT_HEAD(c, " =3D tcg_temp_local_new_i%s();\n", bit_suffix); + c->inst.allocated[c->inst.allocated_count].name =3D varid->var.nam= e; + c->inst.allocated[c->inst.allocated_count].bit_width =3D width; + c->inst.allocated[c->inst.allocated_count].is_unsigned =3D is_unsi= gned; + c->inst.allocated_count++; + } +} + +void ea_free(Context *c, YYLTYPE *locp) +{ + OUT(c, locp, "tcg_temp_free(EA);\n"); +} + +enum OpTypes { + IMM_IMM =3D 0, + IMM_REG =3D 1, + REG_IMM =3D 2, + REG_REG =3D 3, +}; + +HexValue gen_bin_cmp(Context *c, + YYLTYPE *locp, + const char *type, + HexValue *op1_ptr, + HexValue *op2_ptr) +{ + HexValue op1 =3D *op1_ptr; + HexValue op2 =3D *op2_ptr; + enum OpTypes op_types =3D (op1.type !=3D IMMEDIATE) << 1 + | (op2.type !=3D IMMEDIATE); + + /* Find bit width of the two operands, if at least one is 64 bit use a= */ + /* 64bit operation, eventually extend 32bit operands. */ + bool op_is64bit =3D op1.bit_width =3D=3D 64 || op2.bit_width =3D=3D 64; + const char *bit_suffix =3D op_is64bit ? "i64" : "i32"; + int bit_width =3D (op_is64bit) ? 64 : 32; + if (op_is64bit) { + switch (op_types) { + case IMM_IMM: + break; + case IMM_REG: + op2 =3D rvalue_extend(c, locp, &op2); + break; + case REG_IMM: + op1 =3D rvalue_extend(c, locp, &op1); + break; + case REG_REG: + op1 =3D rvalue_extend(c, locp, &op1); + op2 =3D rvalue_extend(c, locp, &op2); + break; + } + } + + HexValue res =3D gen_tmp(c, locp, bit_width); + + switch (op_types) { + case IMM_IMM: + { + OUT(c, locp, "tcg_gen_movi_", bit_suffix, + "(", &res, ", ", &op1, " =3D=3D ", &op2, ");\n"); + break; + } + case IMM_REG: + { + HexValue swp =3D op2; + op2 =3D op1; + op1 =3D swp; + /* Swap comparison direction */ + type =3D cmp_swap(c, locp, type); + } + /* fallthrough */ + case REG_IMM: + { + OUT(c, locp, "tcg_gen_setcondi_", bit_suffix, "("); + OUT(c, locp, type, ", ", &res, ", ", &op1, ", ", &op2, ");\n"); + break; + } + case REG_REG: + { + OUT(c, locp, "tcg_gen_setcond_", bit_suffix, "("); + OUT(c, locp, type, ", ", &res, ", ", &op1, ", ", &op2, ");\n"); + break; + } + default: + { + fprintf(stderr, "Error in evalutating immediateness!"); + abort(); + } + } + + /* Free operands */ + rvalue_free(c, locp, &op1); + rvalue_free(c, locp, &op2); + + return res; +} + +static void gen_add_op(Context *c, YYLTYPE *locp, unsigned bit_width, + const char *bit_suffix, HexValue *res, + enum OpTypes op_types, HexValue *op1, HexValue *op2) +{ + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", res, + " =3D ", op1, " + ", op2, ";\n"); + break; + case IMM_REG: + OUT(c, locp, "tcg_gen_addi_", bit_suffix, + "(", res, ", ", op2, ", ", op1, ");\n"); + break; + case REG_IMM: + OUT(c, locp, "tcg_gen_addi_", bit_suffix, + "(", res, ", ", op1, ", ", op2, ");\n"); + break; + case REG_REG: + OUT(c, locp, "tcg_gen_add_", bit_suffix, + "(", res, ", ", op1, ", ", op2, ");\n"); + break; + } + rvalue_free(c, locp, op1); + rvalue_free(c, locp, op2); +} + +static void gen_sub_op(Context *c, YYLTYPE *locp, unsigned bit_width, + const char *bit_suffix, HexValue *res, + enum OpTypes op_types, HexValue *op1, HexValue *op2) +{ + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", res, + " =3D ", op1, " - ", op2, ";\n"); + break; + case IMM_REG: + OUT(c, locp, "tcg_gen_subfi_", bit_suffix, + "(", res, ", ", op1, ", ", op2, ");\n"); + break; + case REG_IMM: + OUT(c, locp, "tcg_gen_subi_", bit_suffix, + "(", res, ", ", op1, ", ", op2, ");\n"); + break; + case REG_REG: + OUT(c, locp, "tcg_gen_sub_", bit_suffix, + "(", res, ", ", op1, ", ", op2, ");\n"); + break; + } + rvalue_free(c, locp, op1); + rvalue_free(c, locp, op2); +} + +static void gen_mul_op(Context *c, YYLTYPE *locp, + const char *bit_suffix, HexValue *res, + enum OpTypes op_types, HexValue *op1, HexValue *op2) +{ + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int64_t ", res, " =3D ", op1, " * ", op2, ";\n"); + break; + case IMM_REG: + OUT(c, locp, "tcg_gen_muli_", bit_suffix, + "(", res, ", ", op2, ", (int64_t)", op1, ");\n"); + break; + case REG_IMM: + OUT(c, locp, "tcg_gen_muli_", bit_suffix, + "(", res, ", ", op1, ", (int64_t)", op2, ");\n"); + break; + case REG_REG: + OUT(c, locp, "tcg_gen_mul_", bit_suffix, + "(", res, ", ", op1, ", ", op2, ");\n"); + break; + } + rvalue_free(c, locp, op1); + rvalue_free(c, locp, op2); +} + +static void gen_div_op(Context *c, YYLTYPE *locp, HexValue *res, + enum OpTypes op_types, HexValue *op1, HexValue *op2) +{ + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int64_t ", res, " =3D ", op1, " / ", op2, ";\n"); + break; + case IMM_REG: + case REG_IMM: + case REG_REG: + OUT(c, locp, res, " =3D gen_helper_divu(" + "cpu_env, ", op1, ", ", op2, ");\n"); + break; + } + rvalue_free(c, locp, op1); + rvalue_free(c, locp, op2); +} + +static void gen_asl_op(Context *c, YYLTYPE *locp, unsigned bit_width, + bool op_is64bit, const char *bit_suffix, HexValue *= res, + enum OpTypes op_types, HexValue *op1_ptr, + HexValue *op2_ptr) +{ + HexValue op1 =3D *op1_ptr; + HexValue op2 =3D *op2_ptr; + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", res, + " =3D ", &op1, " << ", &op2, ";\n"); + break; + case REG_IMM: + { + /* Need to work around assert(op2 < 64) in tcg_gen_shli */ + if (op_is64bit) { + op2 =3D rvalue_extend(c, locp, &op2); + } + op2 =3D rvalue_materialize(c, locp, &op2); + const char *mask =3D op_is64bit ? "0xffffffffffffffc0" + : "0xffffffc0"; + HexValue zero =3D gen_tmp_value(c, locp, "0", bit_width); + HexValue tmp =3D gen_tmp(c, locp, bit_width); + OUT(c, locp, "tcg_gen_andi_", bit_suffix, + "(", &tmp, ", ", &op2, ", ", mask, ");\n"); + OUT(c, locp, "tcg_gen_movcond_i", &bit_width); + OUT(c, locp, "(TCG_COND_EQ, ", &tmp, ", ", &tmp, ", ", &zero); + OUT(c, locp, ", ", &op2, ", ", &zero, ");\n"); + OUT(c, locp, "tcg_gen_shl_", bit_suffix, + "(", res, ", ", &op1, ", ", &tmp, ");\n"); + rvalue_free(c, locp, &zero); + rvalue_free(c, locp, &tmp); + } + break; + case IMM_REG: + op1.bit_width =3D bit_width; + op1 =3D rvalue_materialize(c, locp, &op1); + /* Fallthrough */ + case REG_REG: + OUT(c, locp, "tcg_gen_shl_", bit_suffix, + "(", res, ", ", &op1, ", ", &op2, ");\n"); + break; + } + if (op_types !=3D IMM_IMM) { + /* Handle left shift by 64 which hexagon-sim expects to clear out = */ + /* register */ + HexValue edge =3D gen_tmp_value(c, locp, "64", bit_width); + HexValue zero =3D gen_tmp_value(c, locp, "0", bit_width); + if (op_is64bit) { + op2 =3D rvalue_extend(c, locp, &op2); + } + op1 =3D rvalue_materialize(c, locp, &op1); + op2 =3D rvalue_materialize(c, locp, &op2); + OUT(c, locp, "tcg_gen_movcond_i", &bit_width); + if (op_types =3D=3D REG_REG || op_types =3D=3D IMM_REG) { + OUT(c, locp, "(TCG_COND_EQ, ", res, ", ", &op2, ", ", &edge); + } else { + OUT(c, locp, "(TCG_COND_EQ, ", res, ", ", &op2, ", ", &edge); + } + OUT(c, locp, ", ", &zero, ", ", res, ");\n"); + rvalue_free(c, locp, &edge); + rvalue_free(c, locp, &zero); + } + rvalue_free(c, locp, &op1); + rvalue_free(c, locp, &op2); +} + +static void gen_asr_op(Context *c, YYLTYPE *locp, unsigned bit_width, + const char *bit_suffix, HexValue *res, + enum OpTypes op_types, HexValue *op1, HexValue *op2) +{ + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", res, + " =3D ", op1, " >> ", op2, ";\n"); + break; + case REG_IMM: + OUT(c, locp, "tcg_gen_sari_", bit_suffix, + "(", res, ", ", op1, ", ", op2, ");\n"); + break; + case IMM_REG: + rvalue_materialize(c, locp, op1); + /* Fallthrough */ + case REG_REG: + OUT(c, locp, "tcg_gen_sar_", bit_suffix, + "(", res, ", ", op1, ", ", op2, ");\n"); + break; + } + rvalue_free(c, locp, op1); + rvalue_free(c, locp, op2); +} + +static void gen_lsr_op(Context *c, YYLTYPE *locp, unsigned bit_width, + const char *bit_suffix, HexValue *res, + enum OpTypes op_types, HexValue *op1_ptr, HexValue = *op2) +{ + HexValue op1 =3D *op1_ptr; + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", + res, " =3D ", &op1, " >> ", op2, ";\n"); + break; + case REG_IMM: + OUT(c, locp, "tcg_gen_shri_", bit_suffix, + "(", res, ", ", &op1, ", ", op2, ");\n"); + break; + case IMM_REG: + op1 =3D rvalue_materialize(c, locp, &op1); + /* Fallthrough */ + case REG_REG: + OUT(c, locp, "tcg_gen_shr_", bit_suffix, + "(", res, ", ", &op1, ", ", op2, ");\n"); + break; + } + rvalue_free(c, locp, &op1); + rvalue_free(c, locp, op2); +} + +static void gen_andb_op(Context *c, YYLTYPE *locp, unsigned bit_width, + const char *bit_suffix, HexValue *res, + enum OpTypes op_types, HexValue *op1, HexValue *op= 2) +{ + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", + res, " =3D ", op1, " & ", op2, ";\n"); + break; + case IMM_REG: + OUT(c, locp, "tcg_gen_andi_", bit_suffix, + "(", res, ", ", op2, ", ", op1, ");\n"); + break; + case REG_IMM: + OUT(c, locp, "tcg_gen_andi_", bit_suffix, + "(", res, ", ", op1, ", ", op2, ");\n"); + break; + case REG_REG: + OUT(c, locp, "tcg_gen_and_", bit_suffix, + "(", res, ", ", op1, ", ", op2, ");\n"); + break; + } + rvalue_free(c, locp, op1); + rvalue_free(c, locp, op2); +} + +static void gen_orb_op(Context *c, YYLTYPE *locp, unsigned bit_width, + const char *bit_suffix, HexValue *res, + enum OpTypes op_types, HexValue *op1, HexValue *op2) +{ + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", + res, " =3D ", op1, " & ", op2, ";\n"); + break; + case IMM_REG: + OUT(c, locp, "tcg_gen_ori_", bit_suffix, + "(", res, ", ", op2, ", ", op1, ");\n"); + break; + case REG_IMM: + OUT(c, locp, "tcg_gen_ori_", bit_suffix, + "(", res, ", ", op1, ", ", op2, ");\n"); + break; + case REG_REG: + OUT(c, locp, "tcg_gen_or_", bit_suffix, + "(", res, ", ", op1, ", ", op2, ");\n"); + break; + } + rvalue_free(c, locp, op1); + rvalue_free(c, locp, op2); +} + +static void gen_xorb_op(Context *c, YYLTYPE *locp, unsigned bit_width, + const char *bit_suffix, HexValue *res, + enum OpTypes op_types, HexValue *op1, HexValue *op= 2) +{ + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", + res, " =3D ", op1, " & ", op2, ";\n"); + break; + case IMM_REG: + OUT(c, locp, "tcg_gen_xori_", bit_suffix, + "(", res, ", ", op2, ", ", op1, ");\n"); + break; + case REG_IMM: + OUT(c, locp, "tcg_gen_xori_", bit_suffix, + "(", res, ", ", op1, ", ", op2, ");\n"); + break; + case REG_REG: + OUT(c, locp, "tcg_gen_xor_", bit_suffix, + "(", res, ", ", op1, ", ", op2, ");\n"); + break; + } + rvalue_free(c, locp, op1); + rvalue_free(c, locp, op2); +} + +static void gen_andl_op(Context *c, YYLTYPE *locp, unsigned bit_width, + const char *bit_suffix, HexValue *res, + enum OpTypes op_types, HexValue *op1, HexValue *op= 2) +{ + HexValue zero, tmp1, tmp2; + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", + res, " =3D ", op1, " && ", op2, ";\n"); + break; + case IMM_REG: + zero =3D gen_tmp_value(c, locp, "0", 32); + tmp2 =3D gen_bin_cmp(c, locp, "TCG_COND_NE", op2, &zero); + OUT(c, locp, "tcg_gen_andi_", bit_suffix, + "(", res, ", ", op1, " !=3D 0 , ", &tmp2, ");\n"); + rvalue_free(c, locp, &tmp2); + break; + case REG_IMM: + zero =3D gen_tmp_value(c, locp, "0", 32); + tmp1 =3D gen_bin_cmp(c, locp, "TCG_COND_NE", op1, &zero); + OUT(c, locp, "tcg_gen_andi_", bit_suffix, + "(", res, ", ", &tmp1, ", ", op2, " !=3D 0);\n"); + rvalue_free(c, locp, &tmp1); + break; + case REG_REG: + zero =3D gen_tmp_value(c, locp, "0", 32); + zero.is_manual =3D true; + tmp1 =3D gen_bin_cmp(c, locp, "TCG_COND_NE", op1, &zero); + tmp2 =3D gen_bin_cmp(c, locp, "TCG_COND_NE", op2, &zero); + OUT(c, locp, "tcg_gen_and_", bit_suffix, + "(", res, ", ", &tmp1, ", ", &tmp2, ");\n"); + rvalue_free_manual(c, locp, &zero); + rvalue_free(c, locp, &tmp1); + rvalue_free(c, locp, &tmp2); + break; + } +} + +static void gen_mini_op(Context *c, YYLTYPE *locp, unsigned bit_width, + HexValue *res, enum OpTypes op_types, + HexValue *op1_ptr, HexValue *op2_ptr) +{ + HexValue op1 =3D *op1_ptr; + HexValue op2 =3D *op2_ptr; + const char *comparison =3D res->is_unsigned + ? "TCG_COND_LEU" + : "TCG_COND_LE"; + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", res, " =3D (", &op1, " <=3D= "); + OUT(c, locp, &op2, ") ? ", &op1, " : ", &op2, ";\n"); + break; + case IMM_REG: + op1.bit_width =3D bit_width; + op1 =3D rvalue_materialize(c, locp, &op1); + OUT(c, locp, "tcg_gen_movcond_i", &bit_width); + OUT(c, locp, "(", comparison, ", ", res, ", ", &op1, ", ", &op2); + OUT(c, locp, ", ", &op1, ", ", &op2, ");\n"); + break; + case REG_IMM: + op2.bit_width =3D bit_width; + op2 =3D rvalue_materialize(c, locp, &op2); + /* Fallthrough */ + case REG_REG: + OUT(c, locp, "tcg_gen_movcond_i", &bit_width); + OUT(c, locp, "(", comparison, ", ", res, ", ", &op1, ", ", &op2); + OUT(c, locp, ", ", &op1, ", ", &op2, ");\n"); + break; + } + rvalue_free(c, locp, &op1); + rvalue_free(c, locp, &op2); +} + +static void gen_maxi_op(Context *c, YYLTYPE *locp, unsigned bit_width, + HexValue *res, enum OpTypes op_types, + HexValue *op1_ptr, HexValue *op2_ptr) +{ + HexValue op1 =3D *op1_ptr; + HexValue op2 =3D *op2_ptr; + const char *comparison =3D res->is_unsigned + ? "TCG_COND_LEU" + : "TCG_COND_LE"; + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", res, " =3D (", &op1, " <=3D= "); + OUT(c, locp, &op2, ") ? ", &op2, " : ", &op1, ";\n"); + break; + case IMM_REG: + op1.bit_width =3D bit_width; + op1 =3D rvalue_materialize(c, locp, &op1); + OUT(c, locp, "tcg_gen_movcond_i", &bit_width); + OUT(c, locp, "(", comparison, ", ", res, ", ", &op1, ", ", &op2); + OUT(c, locp, ", ", &op2, ", ", &op1, ");\n"); + break; + case REG_IMM: + op2.bit_width =3D bit_width; + op2 =3D rvalue_materialize(c, locp, &op2); + /* Fallthrough */ + case REG_REG: + OUT(c, locp, "tcg_gen_movcond_i", &bit_width); + OUT(c, locp, "(", comparison, ", ", res, ", ", &op1, ", ", &op2); + OUT(c, locp, ", ", &op2, ", ", &op1, ");\n"); + break; + } + rvalue_free(c, locp, &op1); + rvalue_free(c, locp, &op2); +} + +static void gen_mod_op(Context *c, YYLTYPE *locp, HexValue *res, + enum OpTypes op_types, HexValue *op1, HexValue *op2) +{ + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int64_t ", res, " =3D ", op1, " % ", op2, ";\n"); + break; + case IMM_REG: + case REG_IMM: + case REG_REG: + OUT(c, locp, "gen_helper_mod(", + res, ", ", op1, ", ", op2, ");\n"); + break; + } + rvalue_free(c, locp, op1); + rvalue_free(c, locp, op2); +} + +/* Code generation functions */ +HexValue gen_bin_op(Context *c, + YYLTYPE *locp, + enum OpType type, + HexValue *operand1, + HexValue *operand2) +{ + /* Replicate operands to avoid side effects */ + HexValue op1 =3D *operand1; + HexValue op2 =3D *operand2; + + /* Enforce variables' size */ + if (op1.type =3D=3D VARID) { + int index =3D find_variable(c, locp, &op1); + yyassert(c, locp, index >=3D 0, "Variable in bin_op must exist!\n"= ); + op1.bit_width =3D c->inst.allocated[index].bit_width; + } + if (op2.type =3D=3D VARID) { + int index =3D find_variable(c, locp, &op2); + yyassert(c, locp, index >=3D 0, "Variable in bin_op must exist!\n"= ); + op2.bit_width =3D c->inst.allocated[index].bit_width; + } + + enum OpTypes op_types =3D (op1.type !=3D IMMEDIATE) << 1 + | (op2.type !=3D IMMEDIATE); + + /* Find bit width of the two operands, if at least one is 64 bit use a= */ + /* 64bit operation, eventually extend 32bit operands. */ + bool op_is64bit =3D op1.bit_width =3D=3D 64 || op2.bit_width =3D=3D 64; + /* Shift greater than 32 are 64 bits wide */ + if (type =3D=3D ASL_OP && op2.type =3D=3D IMMEDIATE && + op2.imm.type =3D=3D VALUE && op2.imm.value >=3D 32) + op_is64bit =3D true; + const char *bit_suffix =3D op_is64bit ? "i64" : "i32"; + int bit_width =3D (op_is64bit) ? 64 : 32; + /* Handle bit width */ + if (op_is64bit) { + switch (op_types) { + case IMM_IMM: + break; + case IMM_REG: + op2 =3D rvalue_extend(c, locp, &op2); + break; + case REG_IMM: + op1 =3D rvalue_extend(c, locp, &op1); + break; + case REG_REG: + op1 =3D rvalue_extend(c, locp, &op1); + op2 =3D rvalue_extend(c, locp, &op2); + break; + } + } + HexValue res; + if (op_types !=3D IMM_IMM) { + res =3D gen_tmp(c, locp, bit_width); + } else { + res.type =3D IMMEDIATE; + res.is_dotnew =3D false; + res.is_manual =3D false; + res.imm.type =3D QEMU_TMP; + res.imm.index =3D c->inst.qemu_tmp_count; + res.bit_width =3D bit_width; + } + /* Handle signedness, if both unsigned -> result is unsigned, else sig= ned */ + res.is_unsigned =3D op1.is_unsigned && op2.is_unsigned; + + switch (type) { + case ADD_OP: + gen_add_op(c, locp, bit_width, bit_suffix, &res, op_types, &op1, &= op2); + break; + case SUB_OP: + gen_sub_op(c, locp, bit_width, bit_suffix, &res, op_types, &op1, &= op2); + break; + case MUL_OP: + gen_mul_op(c, locp, bit_suffix, &res, op_types, &op1, &op2); + break; + case DIV_OP: + gen_div_op(c, locp, &res, op_types, &op1, &op2); + break; + case ASL_OP: + gen_asl_op(c, locp, bit_width, op_is64bit, bit_suffix, &res, op_ty= pes, + &op1, &op2); + break; + case ASR_OP: + gen_asr_op(c, locp, bit_width, bit_suffix, &res, op_types, &op1, &= op2); + break; + case LSR_OP: + gen_lsr_op(c, locp, bit_width, bit_suffix, &res, op_types, &op1, &= op2); + break; + case ANDB_OP: + gen_andb_op(c, locp, bit_width, bit_suffix, &res, op_types, &op1, = &op2); + break; + case ORB_OP: + gen_orb_op(c, locp, bit_width, bit_suffix, &res, op_types, &op1, &= op2); + break; + case XORB_OP: + gen_xorb_op(c, locp, bit_width, bit_suffix, &res, op_types, &op1, = &op2); + break; + case ANDL_OP: + gen_andl_op(c, locp, bit_width, bit_suffix, &res, op_types, &op1, = &op2); + break; + case MINI_OP: + gen_mini_op(c, locp, bit_width, &res, op_types, &op1, &op2); + break; + case MAXI_OP: + gen_maxi_op(c, locp, bit_width, &res, op_types, &op1, &op2); + break; + case MOD_OP: + gen_mod_op(c, locp, &res, op_types, &op1, &op2); + break; + } + if (op_types =3D=3D IMM_IMM) { + c->inst.qemu_tmp_count++; + } + return res; +} + +HexValue gen_cast_op(Context *c, + YYLTYPE *locp, + HexValue *source, + unsigned target_width) { + if (source->bit_width =3D=3D target_width) { + return *source; + } else if (source->type =3D=3D IMMEDIATE) { + HexValue res =3D *source; + res.bit_width =3D target_width; + return res; + } else { + HexValue res =3D gen_tmp(c, locp, target_width); + /* Truncate */ + if (source->bit_width > target_width) { + OUT(c, locp, "tcg_gen_trunc_i64_tl(", &res, ", ", source, ");\= n"); + } else { + if (source->is_unsigned) { + /* Extend unsigned */ + OUT(c, locp, "tcg_gen_extu_i32_i64(", + &res, ", ", source, ");\n"); + } else { + /* Extend signed */ + OUT(c, locp, "tcg_gen_ext_i32_i64(", + &res, ", ", source, ");\n"); + } + } + rvalue_free(c, locp, source); + return res; + } +} + +HexValue gen_extend_op(Context *c, + YYLTYPE *locp, + HexValue *src_width_ptr, + HexValue *dst_width_ptr, + HexValue *value_ptr, + bool is_unsigned) { + HexValue src_width =3D *src_width_ptr; + HexValue dst_width =3D *dst_width_ptr; + HexValue value =3D *value_ptr; + src_width =3D rvalue_extend(c, locp, &src_width); + value =3D rvalue_extend(c, locp, &value); + src_width =3D rvalue_materialize(c, locp, &src_width); + value =3D rvalue_materialize(c, locp, &value); + + HexValue res =3D gen_tmp(c, locp, 64); + HexValue shift =3D gen_tmp_value(c, locp, "64", 64); + HexValue zero =3D gen_tmp_value(c, locp, "0", 64); + OUT(c, locp, "tcg_gen_sub_i64(", + &shift, ", ", &shift, ", ", &src_width, ");\n"); + if (is_unsigned) { + HexValue mask =3D gen_tmp_value(c, locp, "0xffffffffffffffff", 64); + OUT(c, locp, "tcg_gen_shr_i64(", + &mask, ", ", &mask, ", ", &shift, ");\n"); + OUT(c, locp, "tcg_gen_and_i64(", + &res, ", ", &value, ", ", &mask, ");\n"); + rvalue_free(c, locp, &mask); + } else { + OUT(c, locp, "tcg_gen_shl_i64(", + &res, ", ", &value, ", ", &shift, ");\n"); + OUT(c, locp, "tcg_gen_sar_i64(", + &res, ", ", &res, ", ", &shift, ");\n"); + } + OUT(c, locp, "tcg_gen_movcond_i64(", COND_EQ, ", ", &res, ", "); + OUT(c, locp, &src_width, ", ", &zero, ", ", &zero, ", ", &res, ");\n"); + + rvalue_free(c, locp, &src_width); + rvalue_free(c, locp, &dst_width); + rvalue_free(c, locp, &value); + rvalue_free(c, locp, &shift); + rvalue_free(c, locp, &zero); + + res.is_unsigned =3D is_unsigned; + return res; +} + +void gen_rdeposit_op(Context *c, + YYLTYPE *locp, + HexValue *dest, + HexValue *value, + HexValue *begin, + HexValue *width) +{ + HexValue dest_m =3D *dest; + dest_m.is_manual =3D true; + + HexValue value_m =3D rvalue_extend(c, locp, value); + HexValue begin_m =3D rvalue_extend(c, locp, begin); + HexValue width_orig =3D *width; + width_orig.is_manual =3D true; + HexValue width_m =3D rvalue_extend(c, locp, &width_orig); + width_m =3D rvalue_materialize(c, locp, &width_m); + + HexValue mask =3D gen_tmp_value(c, locp, "0xffffffffffffffffUL", 64); + mask.is_unsigned =3D true; + HexValue k64 =3D gen_tmp_value(c, locp, "64", 64); + k64 =3D gen_bin_op(c, locp, SUB_OP, &k64, &width_m); + mask =3D gen_bin_op(c, locp, LSR_OP, &mask, &k64); + begin_m.is_manual =3D true; + mask =3D gen_bin_op(c, locp, ASL_OP, &mask, &begin_m); + mask.is_manual =3D true; + value_m =3D gen_bin_op(c, locp, ASL_OP, &value_m, &begin_m); + value_m =3D gen_bin_op(c, locp, ANDB_OP, &value_m, &mask); + + OUT(c, locp, "tcg_gen_not_i64(", &mask, ", ", &mask, ");\n"); + mask.is_manual =3D false; + HexValue res =3D gen_bin_op(c, locp, ANDB_OP, &dest_m, &mask); + res =3D gen_bin_op(c, locp, ORB_OP, &res, &value_m); + + if (dest->bit_width !=3D res.bit_width) { + res =3D rvalue_truncate(c, locp, &res); + } + + HexValue zero =3D gen_tmp_value(c, locp, "0", res.bit_width); + OUT(c, locp, "tcg_gen_movcond_i", &res.bit_width, "(TCG_COND_NE, ", de= st); + OUT(c, locp, ", ", &width_orig, ", ", &zero, ", ", &res, ", ", dest, + ");\n"); + + rvalue_free(c, locp, &zero); + rvalue_free(c, locp, width); + rvalue_free(c, locp, &res); +} + +void gen_deposit_op(Context *c, + YYLTYPE *locp, + HexValue *dest, + HexValue *value, + HexValue *index, + HexCast *cast) +{ + yyassert(c, locp, index->type =3D=3D IMMEDIATE, + "Deposit index must be immediate!\n"); + HexValue value_m =3D *value; + int bit_width =3D (dest->bit_width =3D=3D 64) ? 64 : 32; + int width =3D cast->bit_width; + /* If the destination value is 32, truncate the value, otherwise exten= d */ + if (dest->bit_width !=3D value->bit_width) { + if (bit_width =3D=3D 32) { + value_m =3D rvalue_truncate(c, locp, &value_m); + } else { + value_m =3D rvalue_extend(c, locp, &value_m); + } + } + value_m =3D rvalue_materialize(c, locp, &value_m); + OUT(c, locp, "tcg_gen_deposit_i", &bit_width, "(", dest, ", ", dest, "= , "); + OUT(c, locp, &value_m, ", ", index, " * ", &width, ", ", &width, ");\n= "); + rvalue_free(c, locp, index); + rvalue_free(c, locp, &value_m); +} + +HexValue gen_rextract_op(Context *c, + YYLTYPE *locp, + HexValue *source, + int begin, + int width) { + int bit_width =3D (source->bit_width =3D=3D 64) ? 64 : 32; + HexValue res =3D gen_tmp(c, locp, bit_width); + OUT(c, locp, "tcg_gen_extract_i", &bit_width, "(", &res); + OUT(c, locp, ", ", source, ", ", &begin, ", ", &width, ");\n"); + rvalue_free(c, locp, source); + return res; +} + +HexValue gen_extract_op(Context *c, + YYLTYPE *locp, + HexValue *source, + HexValue *index, + HexExtract *extract) { + yyassert(c, locp, index->type =3D=3D IMMEDIATE, + "Extract index must be immediate!\n"); + int bit_width =3D (source->bit_width =3D=3D 64) ? 64 : 32; + const char *sign_prefix =3D (extract->is_unsigned) ? "" : "s"; + int width =3D extract->bit_width; + HexValue res =3D gen_tmp(c, locp, bit_width); + res.is_unsigned =3D extract->is_unsigned; + OUT(c, locp, "tcg_gen_", sign_prefix, "extract_i", &bit_width, + "(", &res, ", ", source); + OUT(c, locp, ", ", index, " * ", &width, ", ", &width, ");\n"); + + /* Some extract operations have bit_width !=3D storage_bit_width */ + if (extract->storage_bit_width > bit_width) { + HexValue tmp =3D gen_tmp(c, locp, extract->storage_bit_width); + tmp.is_unsigned =3D extract->is_unsigned; + if (extract->is_unsigned) { + /* Extend unsigned */ + OUT(c, locp, "tcg_gen_extu_i32_i64(", + &tmp, ", ", &res, ");\n"); + } else { + /* Extend signed */ + OUT(c, locp, "tcg_gen_ext_i32_i64(", + &tmp, ", ", &res, ");\n"); + } + rvalue_free(c, locp, &res); + res =3D tmp; + } + + rvalue_free(c, locp, source); + rvalue_free(c, locp, index); + return res; +} + +HexValue gen_read_creg(Context *c, YYLTYPE *locp, HexValue *reg) +{ + yyassert(c, locp, reg->type =3D=3D REGISTER, "reg must be a register!"= ); + if (reg->reg.id < 'a') { + HexValue tmp =3D gen_tmp_value(c, locp, "0", 32); + const char *id =3D creg_str[(uint8_t)reg->reg.id]; + OUT(c, locp, "READ_REG(", &tmp, ", ", id, ");\n"); + rvalue_free(c, locp, reg); + return tmp; + } + return *reg; +} + +void gen_write_creg(Context *c, + YYLTYPE *locp, + HexValue *reg, + HexValue *value) +{ + yyassert(c, locp, reg->type =3D=3D REGISTER, "reg must be a register!"= ); + HexValue value_m =3D *value; + value_m =3D rvalue_truncate(c, locp, &value_m); + value_m =3D rvalue_materialize(c, locp, &value_m); + OUT(c, + locp, + "gen_log_reg_write(", creg_str[(uint8_t)reg->reg.id], ", ", + &value_m, ");\n"); + OUT(c, + locp, + "ctx_log_reg_write(ctx, ", creg_str[(uint8_t)reg->reg.id], ");\n"); + rvalue_free(c, locp, reg); + rvalue_free(c, locp, &value_m); +} + +void gen_assign(Context *c, + YYLTYPE *locp, + HexValue *dest, + HexValue *value) +{ + HexValue value_m =3D *value; + if (dest->type =3D=3D REGISTER && + dest->reg.type =3D=3D CONTROL && dest->reg.id < 'a') { + gen_write_creg(c, locp, dest, &value_m); + return; + } + /* Create (if not present) and assign to temporary variable */ + if (dest->type =3D=3D VARID) { + varid_allocate(c, locp, dest, value_m.bit_width, value_m.is_unsign= ed); + } + int bit_width =3D dest->bit_width =3D=3D 64 ? 64 : 32; + if (bit_width !=3D value_m.bit_width) { + if (bit_width =3D=3D 64) { + value_m =3D rvalue_extend(c, locp, &value_m); + } else { + value_m =3D rvalue_truncate(c, locp, &value_m); + } + } + value_m =3D rvalue_materialize(c, locp, &value_m); + if (value_m.type =3D=3D IMMEDIATE) { + OUT(c, locp, "tcg_gen_movi_i", &bit_width, + "(", dest, ", ", &value_m, ");\n"); + } else { + OUT(c, locp, "tcg_gen_mov_i", &bit_width, + "(", dest, ", ", &value_m, ");\n"); + } + rvalue_free(c, locp, &value_m); +} + +HexValue gen_convround(Context *c, + YYLTYPE *locp, + HexValue *source) +{ + HexValue src =3D *source; + src.is_manual =3D true; + + unsigned bit_width =3D src.bit_width; + const char *size =3D (bit_width =3D=3D 32) ? "32" : "64"; + HexValue res =3D gen_tmp(c, locp, bit_width); + HexValue mask =3D gen_tmp_value(c, locp, "0x3", bit_width); + mask.is_manual =3D true; + HexValue and =3D gen_bin_op(c, locp, ANDB_OP, &src, &mask); + HexValue one =3D gen_tmp_value(c, locp, "1", bit_width); + HexValue src_p1 =3D gen_bin_op(c, locp, ADD_OP, &src, &one); + + OUT(c, locp, "tcg_gen_movcond_i", size, "(TCG_COND_EQ, ", &res); + OUT(c, locp, ", ", &and, ", ", &mask, ", "); + OUT(c, locp, &src_p1, ", ", &src, ");\n"); + + /* Free src but use the original `is_manual` value */ + rvalue_free(c, locp, source); + + /* Free the rest of the values */ + rvalue_free_manual(c, locp, &mask); + rvalue_free(c, locp, &and); + rvalue_free(c, locp, &src_p1); + + return res; +} + +static HexValue gen_convround_n_a(Context *c, + YYLTYPE *locp, + HexValue *a, + HexValue *n) +{ + HexValue res =3D gen_tmp(c, locp, 64); + OUT(c, locp, "tcg_gen_ext_i32_i64(", &res, ", ", a, ");\n"); + rvalue_free(c, locp, a); + rvalue_free(c, locp, n); + return res; +} + +static HexValue gen_convround_n_b(Context *c, + YYLTYPE *locp, + HexValue *a, + HexValue *n) +{ + HexValue res =3D gen_tmp(c, locp, 64); + OUT(c, locp, "tcg_gen_ext_i32_i64(", &res, ", ", a, ");\n"); + + HexValue one =3D gen_tmp_value(c, locp, "1", 32); + HexValue tmp =3D gen_tmp(c, locp, 32); + HexValue tmp_64 =3D gen_tmp(c, locp, 64); + + OUT(c, locp, "tcg_gen_shl_i32(", &tmp); + OUT(c, locp, ", ", &one, ", ", n, ");\n"); + OUT(c, locp, "tcg_gen_and_i32(", &tmp); + OUT(c, locp, ", ", &tmp, ", ", a, ");\n"); + OUT(c, locp, "tcg_gen_shri_i32(", &tmp); + OUT(c, locp, ", ", &tmp, ", 1);\n"); + OUT(c, locp, "tcg_gen_ext_i32_i64(", &tmp_64, ", ", &tmp, ");\n"); + OUT(c, locp, "tcg_gen_add_i64(", &res); + OUT(c, locp, ", ", &res, ", ", &tmp_64, ");\n"); + + rvalue_free(c, locp, a); + rvalue_free(c, locp, n); + rvalue_free(c, locp, &one); + rvalue_free(c, locp, &tmp); + rvalue_free(c, locp, &tmp_64); + + return res; +} + +static HexValue gen_convround_n_c(Context *c, + YYLTYPE *locp, + HexValue *a, + HexValue *n) +{ + HexValue res =3D gen_tmp(c, locp, 64); + OUT(c, locp, "tcg_gen_ext_i32_i64(", &res, ", ", a, ");\n"); + + HexValue one =3D gen_tmp_value(c, locp, "1", 32); + HexValue tmp =3D gen_tmp(c, locp, 32); + HexValue tmp_64 =3D gen_tmp(c, locp, 64); + + OUT(c, locp, "tcg_gen_subi_i32(", &tmp); + OUT(c, locp, ", ", n, ", 1);\n"); + OUT(c, locp, "tcg_gen_shl_i32(", &tmp); + OUT(c, locp, ", ", &one, ", ", &tmp, ");\n"); + OUT(c, locp, "tcg_gen_ext_i32_i64(", &tmp_64, ", ", &tmp, ");\n"); + OUT(c, locp, "tcg_gen_add_i64(", &res); + OUT(c, locp, ", ", &res, ", ", &tmp_64, ");\n"); + + rvalue_free(c, locp, a); + rvalue_free(c, locp, n); + rvalue_free(c, locp, &one); + rvalue_free(c, locp, &tmp); + rvalue_free(c, locp, &tmp_64); + + return res; +} + +HexValue gen_convround_n(Context *c, + YYLTYPE *locp, + HexValue *source_ptr, + HexValue *bit_pos_ptr) +{ + /* If input is 64 bit cast it to 32 */ + HexValue source =3D gen_cast_op(c, locp, source_ptr, 32); + HexValue bit_pos =3D gen_cast_op(c, locp, bit_pos_ptr, 32); + + source =3D rvalue_materialize(c, locp, &source); + bit_pos =3D rvalue_materialize(c, locp, &bit_pos); + + bool free_source_sym =3D !rvalue_equal(&source, source_ptr); + bool free_bit_pos_sym =3D !rvalue_equal(&bit_pos, bit_pos_ptr); + source.is_manual =3D true; + bit_pos.is_manual =3D true; + + HexValue r1 =3D gen_convround_n_a(c, locp, &source, &bit_pos); + HexValue r2 =3D gen_convround_n_b(c, locp, &source, &bit_pos); + HexValue r3 =3D gen_convround_n_c(c, locp, &source, &bit_pos); + + HexValue l_32 =3D gen_tmp_value(c, locp, "1", 32); + + HexValue cond =3D gen_tmp(c, locp, 32); + HexValue cond_64 =3D gen_tmp(c, locp, 64); + HexValue mask =3D gen_tmp(c, locp, 32); + HexValue n_64 =3D gen_tmp(c, locp, 64); + HexValue res =3D gen_tmp(c, locp, 64); + HexValue zero =3D gen_tmp_value(c, locp, "0", 64); + + OUT(c, locp, "tcg_gen_sub_i32(", &mask); + OUT(c, locp, ", ", &bit_pos, ", ", &l_32, ");\n"); + OUT(c, locp, "tcg_gen_shl_i32(", &mask); + OUT(c, locp, ", ", &l_32, ", ", &mask, ");\n"); + OUT(c, locp, "tcg_gen_sub_i32(", &mask); + OUT(c, locp, ", ", &mask, ", ", &l_32, ");\n"); + OUT(c, locp, "tcg_gen_and_i32(", &cond); + OUT(c, locp, ", ", &source, ", ", &mask, ");\n"); + OUT(c, locp, "tcg_gen_extu_i32_i64(", &cond_64, ", ", &cond, ");\n"); + OUT(c, locp, "tcg_gen_ext_i32_i64(", &n_64, ", ", &bit_pos, ");\n"); + + OUT(c, locp, "tcg_gen_movcond_i64"); + OUT(c, locp, "(TCG_COND_EQ, ", &res, ", ", &cond_64, ", ", &zero); + OUT(c, locp, ", ", &r2, ", ", &r3, ");\n"); + + OUT(c, locp, "tcg_gen_movcond_i64"); + OUT(c, locp, "(TCG_COND_EQ, ", &res, ", ", &n_64, ", ", &zero); + OUT(c, locp, ", ", &r1, ", ", &res, ");\n"); + + OUT(c, locp, "tcg_gen_shr_i64(", &res); + OUT(c, locp, ", ", &res, ", ", &n_64, ");\n"); + + rvalue_free_ext(c, locp, &source, free_source_sym); + rvalue_free_ext(c, locp, &bit_pos, free_bit_pos_sym); + + rvalue_free(c, locp, &r1); + rvalue_free(c, locp, &r2); + rvalue_free(c, locp, &r3); + + rvalue_free(c, locp, &cond); + rvalue_free(c, locp, &cond_64); + rvalue_free(c, locp, &l_32); + rvalue_free(c, locp, &mask); + rvalue_free(c, locp, &n_64); + rvalue_free(c, locp, &zero); + + res =3D rvalue_truncate(c, locp, &res); + return res; +} + +HexValue gen_round(Context *c, + YYLTYPE *locp, + HexValue *source, + HexValue *position) { + yyassert(c, locp, source->bit_width <=3D 32, + "fRNDN not implemented for bit widths > 32!"); + + HexValue src =3D *source; + HexValue pos =3D *position; + + HexValue src_width =3D gen_imm_value(c, locp, src.bit_width, 32); + HexValue dst_width =3D gen_imm_value(c, locp, 64, 32); + HexValue a =3D gen_extend_op(c, locp, &src_width, &dst_width, &src, fa= lse); + + src_width =3D gen_imm_value(c, locp, 5, 32); + dst_width =3D gen_imm_value(c, locp, 64, 32); + HexValue b =3D gen_extend_op(c, locp, &src_width, &dst_width, &pos, tr= ue); + + /* Disable auto-free of values used more than once */ + a.is_manual =3D true; + b.is_manual =3D true; + + HexValue res =3D gen_tmp(c, locp, 64); + + HexValue one =3D gen_tmp_value(c, locp, "1", 64); + HexValue n_m1 =3D gen_bin_op(c, locp, SUB_OP, &b, &one); + one =3D gen_tmp_value(c, locp, "1", 64); + HexValue shifted =3D gen_bin_op(c, locp, ASL_OP, &one, &n_m1); + HexValue sum =3D gen_bin_op(c, locp, ADD_OP, &shifted, &a); + + HexValue zero =3D gen_tmp_value(c, locp, "0", 64); + OUT(c, locp, "tcg_gen_movcond_i64"); + OUT(c, locp, "(TCG_COND_EQ, ", &res, ", ", &b, ", ", &zero); + OUT(c, locp, ", ", &a, ", ", &sum, ");\n"); + + rvalue_free_manual(c, locp, &a); + rvalue_free_manual(c, locp, &b); + rvalue_free(c, locp, &zero); + rvalue_free(c, locp, &sum); + + return res; +} + +/* Circular addressing mode with auto-increment */ +HexValue gen_circ_op(Context *c, + YYLTYPE *locp, + HexValue *addr, + HexValue *increment, + HexValue *modifier) { + HexValue increment_m =3D *increment; + HexValue res =3D gen_tmp(c, locp, addr->bit_width); + res.is_unsigned =3D addr->is_unsigned; + HexValue cs =3D gen_tmp(c, locp, 32); + increment_m =3D rvalue_materialize(c, locp, &increment_m); + OUT(c, locp, "READ_REG(", &cs, ", HEX_REG_CS0 + MuN);\n"); + OUT(c, + locp, + "gen_helper_fcircadd(", + &res, + ", ", + addr, + ", ", + &increment_m, + ", ", + modifier); + OUT(c, locp, ", ", &cs, ");\n"); + rvalue_free(c, locp, addr); + rvalue_free(c, locp, &increment_m); + rvalue_free(c, locp, modifier); + rvalue_free(c, locp, &cs); + return res; +} + +HexValue gen_locnt_op(Context *c, YYLTYPE *locp, HexValue *source) +{ + HexValue source_m =3D *source; + const char *bit_suffix =3D source->bit_width =3D=3D 64 ? "64" : "32"; + HexValue res =3D gen_tmp(c, locp, source->bit_width =3D=3D 64 ? 64 : 3= 2); + res.type =3D TEMP; + source_m =3D rvalue_materialize(c, locp, &source_m); + OUT(c, locp, "tcg_gen_not_i", bit_suffix, "(", + &res, ", ", &source_m, ");\n"); + OUT(c, locp, "tcg_gen_clzi_i", bit_suffix, "(", &res, ", ", &res, ", "= ); + OUT(c, locp, bit_suffix, ");\n"); + rvalue_free(c, locp, &source_m); + return res; +} + +HexValue gen_ctpop_op(Context *c, YYLTYPE *locp, HexValue *source) +{ + HexValue source_m =3D *source; + const char *bit_suffix =3D source_m.bit_width =3D=3D 64 ? "64" : "32"; + HexValue res =3D gen_tmp(c, locp, source_m.bit_width =3D=3D 64 ? 64 : = 32); + res.type =3D TEMP; + source_m =3D rvalue_materialize(c, locp, &source_m); + OUT(c, locp, "tcg_gen_ctpop_i", bit_suffix, + "(", &res, ", ", &source_m, ");\n"); + rvalue_free(c, locp, &source_m); + return res; +} + +HexValue gen_fbrev_4(Context *c, YYLTYPE *locp, HexValue *source) +{ + HexValue source_m =3D *source; + + HexValue res =3D gen_tmp(c, locp, 32); + HexValue tmp1 =3D gen_tmp(c, locp, 32); + HexValue tmp2 =3D gen_tmp(c, locp, 32); + + source_m =3D rvalue_materialize(c, locp, &source_m); + source_m =3D rvalue_truncate(c, locp, &source_m); + + OUT(c, locp, "tcg_gen_mov_tl(", &res, ", ", &source_m, ");\n"); + OUT(c, locp, "tcg_gen_andi_tl(", &tmp1, ", ", &res, ", 0xaaaaaaaa);\n"= ); + OUT(c, locp, "tcg_gen_shri_tl(", &tmp1, ", ", &tmp1, ", 1);\n"); + OUT(c, locp, "tcg_gen_andi_tl(", &tmp2, ", ", &res, ", 0x55555555);\n"= ); + OUT(c, locp, "tcg_gen_shli_tl(", &tmp2, ", ", &tmp2, ", 1);\n"); + OUT(c, locp, "tcg_gen_or_tl(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"); + OUT(c, locp, "tcg_gen_andi_tl(", &tmp1, ", ", &res, ", 0xcccccccc);\n"= ); + OUT(c, locp, "tcg_gen_shri_tl(", &tmp1, ", ", &tmp1, ", 2);\n"); + OUT(c, locp, "tcg_gen_andi_tl(", &tmp2, ", ", &res, ", 0x33333333);\n"= ); + OUT(c, locp, "tcg_gen_shli_tl(", &tmp2, ", ", &tmp2, ", 2);\n"); + OUT(c, locp, "tcg_gen_or_tl(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"); + OUT(c, locp, "tcg_gen_andi_tl(", &tmp1, ", ", &res, ", 0xf0f0f0f0);\n"= ); + OUT(c, locp, "tcg_gen_shri_tl(", &tmp1, ", ", &tmp1, ", 4);\n"); + OUT(c, locp, "tcg_gen_andi_tl(", &tmp2, ", ", &res, ", 0x0f0f0f0f);\n"= ); + OUT(c, locp, "tcg_gen_shli_tl(", &tmp2, ", ", &tmp2, ", 4);\n"); + OUT(c, locp, "tcg_gen_or_tl(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"); + OUT(c, locp, "tcg_gen_andi_tl(", &tmp1, ", ", &res, ", 0xff00ff00);\n"= ); + OUT(c, locp, "tcg_gen_shri_tl(", &tmp1, ", ", &tmp1, ", 8);\n"); + OUT(c, locp, "tcg_gen_andi_tl(", &tmp2, ", ", &res, ", 0x00ff00ff);\n"= ); + OUT(c, locp, "tcg_gen_shli_tl(", &tmp2, ", ", &tmp2, ", 8);\n"); + OUT(c, locp, "tcg_gen_or_tl(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"); + OUT(c, locp, "tcg_gen_shri_tl(", &tmp1, ", ", &res, ", 16);\n"); + OUT(c, locp, "tcg_gen_shli_tl(", &tmp2, ", ", &res, ", 16);\n"); + OUT(c, locp, "tcg_gen_or_tl(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"); + + rvalue_free(c, locp, &tmp1); + rvalue_free(c, locp, &tmp2); + rvalue_free(c, locp, &source_m); + + return res; +} + +HexValue gen_fbrev_8(Context *c, YYLTYPE *locp, HexValue *source) +{ + HexValue source_m =3D *source; + + source_m =3D rvalue_extend(c, locp, &source_m); + source_m =3D rvalue_materialize(c, locp, &source_m); + + HexValue res =3D gen_tmp(c, locp, 64); + HexValue tmp1 =3D gen_tmp(c, locp, 64); + HexValue tmp2 =3D gen_tmp(c, locp, 64); + + OUT(c, locp, "tcg_gen_mov_i64(", + &res, ", ", &source_m, ");\n"); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp1, ", ", &res, ", 0xaaaaaaaaaaaaaaaa);\n"); + OUT(c, locp, "tcg_gen_shri_i64(", + &tmp1, ", ", &tmp1, ", 1);\n"); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp2, ", ", &res, ", 0x5555555555555555);\n"); + OUT(c, locp, "tcg_gen_shli_i64(", + &tmp2, ", ", &tmp2, ", 1);\n"); + OUT(c, locp, "tcg_gen_or_i64(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"= ); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp1, ", ", &res, ", 0xcccccccccccccccc);\n"); + OUT(c, locp, "tcg_gen_shri_i64(", + &tmp1, ", ", &tmp1, ", 2);\n"); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp2, ", ", &res, ", 0x3333333333333333);\n"); + OUT(c, locp, "tcg_gen_shli_i64(", + &tmp2, ", ", &tmp2, ", 2);\n"); + OUT(c, locp, "tcg_gen_or_i64(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"= ); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp1, ", ", &res, ", 0xf0f0f0f0f0f0f0f0);\n"); + OUT(c, locp, "tcg_gen_shri_i64(", + &tmp1, ", ", &tmp1, ", 4);\n"); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp2, ", ", &res, ", 0x0f0f0f0f0f0f0f0f);\n"); + OUT(c, locp, "tcg_gen_shli_i64(", + &tmp2, ", ", &tmp2, ", 4);\n"); + OUT(c, locp, "tcg_gen_or_i64(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"= ); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp1, ", ", &res, ", 0xff00ff00ff00ff00);\n"); + OUT(c, locp, "tcg_gen_shri_i64(", + &tmp1, ", ", &tmp1, ", 8);\n"); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp2, ", ", &res, ", 0x00ff00ff00ff00ff);\n"); + OUT(c, locp, "tcg_gen_shli_i64(", + &tmp2, ", ", &tmp2, ", 8);\n"); + OUT(c, locp, "tcg_gen_or_i64(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"= ); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp1, ", ", &res, ", 0xffff0000ffff0000);\n"); + OUT(c, locp, "tcg_gen_shri_i64(", + &tmp1, ", ", &tmp1, ", 16);\n"); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp2, ", ", &res, ", 0x0000ffff0000ffff);\n"); + OUT(c, locp, "tcg_gen_shli_i64(", + &tmp2, ", ", &tmp2, ", 16);\n"); + OUT(c, locp, "tcg_gen_or_i64(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"= ); + OUT(c, locp, "tcg_gen_shri_i64(", &tmp1, ", ", &res, ", 32);\n"); + OUT(c, locp, "tcg_gen_shli_i64(", &tmp2, ", ", &res, ", 32);\n"); + OUT(c, locp, "tcg_gen_or_i64(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"= ); + + rvalue_free(c, locp, &tmp1); + rvalue_free(c, locp, &tmp2); + rvalue_free(c, locp, &source_m); + + return res; +} + +HexValue gen_rotl(Context *c, YYLTYPE *locp, HexValue *source, HexValue *n) +{ + const char *suffix =3D source->bit_width =3D=3D 64 ? "i64" : "i32"; + + HexValue res =3D gen_tmp(c, locp, source->bit_width); + res.is_unsigned =3D source->is_unsigned; + HexValue tmp_l =3D gen_tmp(c, locp, source->bit_width); + HexValue tmp_r =3D gen_tmp(c, locp, source->bit_width); + HexValue shr =3D gen_tmp(c, locp, source->bit_width); + + OUT(c, locp, "tcg_gen_movi_", suffix, "(", + &shr, ", ", &source->bit_width, ");\n"); + OUT(c, locp, "tcg_gen_subi_", suffix, "(", + &shr, ", ", &shr, ", ", n, ");\n"); + OUT(c, locp, "tcg_gen_shli_", suffix, "(", + &tmp_l, ", ", source, ", ", n, ");\n"); + OUT(c, locp, "tcg_gen_shr_", suffix, "(", + &tmp_r, ", ", source, ", ", &shr, ");\n"); + OUT(c, locp, "tcg_gen_or_", suffix, "(", + &res, ", ", &tmp_l, ", ", &tmp_r, ");\n"); + + rvalue_free(c, locp, source); + rvalue_free(c, locp, n); + rvalue_free(c, locp, &tmp_l); + rvalue_free(c, locp, &tmp_r); + rvalue_free(c, locp, &shr); + + return res; +} + +const char *INTERLEAVE_MASKS[6] =3D { + "0x5555555555555555ULL", + "0x3333333333333333ULL", + "0x0f0f0f0f0f0f0f0fULL", + "0x00ff00ff00ff00ffULL", + "0x0000ffff0000ffffULL", + "0x00000000ffffffffULL", +}; + +HexValue gen_deinterleave(Context *c, YYLTYPE *locp, HexValue *mixed) +{ + HexValue src =3D rvalue_extend(c, locp, mixed); + + HexValue a =3D gen_tmp(c, locp, 64); + a.is_unsigned =3D true; + HexValue b =3D gen_tmp(c, locp, 64); + b.is_unsigned =3D true; + + const char **masks =3D INTERLEAVE_MASKS; + + OUT(c, locp, "tcg_gen_shri_i64(", &a, ", ", &src, ", 1);\n"); + OUT(c, locp, "tcg_gen_andi_i64(", &a, ", ", &a, ", ", masks[0], ");\n"= ); + OUT(c, locp, "tcg_gen_andi_i64(", &b, ", ", &src, ", ", masks[0], ");\= n"); + + HexValue res =3D gen_tmp(c, locp, 64); + res.is_unsigned =3D true; + + unsigned shift =3D 1; + for (unsigned i =3D 1; i < 6; ++i) { + OUT(c, locp, "tcg_gen_shri_i64(", &res, ", ", &b, ", ", &shift, ")= ;\n"); + OUT(c, locp, "tcg_gen_or_i64(", &b, ", ", &res, ", ", &b, ");\n"); + OUT(c, locp, "tcg_gen_andi_i64(", &b, ", ", &b, ", ", masks[i], ")= ;\n"); + OUT(c, locp, "tcg_gen_shri_i64(", &res, ", ", &a, ", ", &shift, ")= ;\n"); + OUT(c, locp, "tcg_gen_or_i64(", &a, ", ", &res, ", ", &a, ");\n"); + OUT(c, locp, "tcg_gen_andi_i64(", &a, ", ", &a, ", ", masks[i], ")= ;\n"); + shift <<=3D 1; + } + + OUT(c, locp, "tcg_gen_shli_i64(", &a, ", ", &a, ", 32);\n"); + OUT(c, locp, "tcg_gen_or_i64(", &res, ", ", &a, ", ", &b, ");\n"); + + rvalue_free(c, locp, &a); + rvalue_free(c, locp, &b); + + return res; +} + +HexValue gen_interleave(Context *c, + YYLTYPE *locp, + HexValue *odd, + HexValue *even) +{ + HexValue a =3D rvalue_truncate(c, locp, odd); + a.is_unsigned =3D true; + HexValue b =3D rvalue_truncate(c, locp, even); + a.is_unsigned =3D true; + + a =3D rvalue_extend(c, locp, &a); + b =3D rvalue_extend(c, locp, &b); + + HexValue res =3D gen_tmp(c, locp, 64); + res.is_unsigned =3D true; + + const char **masks =3D INTERLEAVE_MASKS; + + unsigned shift =3D 16; + for (int i =3D 4; i >=3D 0; --i) { + OUT(c, locp, "tcg_gen_shli_i64(", &res, ", ", &a, ", ", &shift, ")= ;\n"); + OUT(c, locp, "tcg_gen_or_i64(", &a, ", ", &res, ", ", &a, ");\n"); + OUT(c, locp, "tcg_gen_andi_i64(", &a, ", ", &a, ", ", masks[i], ")= ;\n"); + OUT(c, locp, "tcg_gen_shli_i64(", &res, ", ", &b, ", ", &shift, ")= ;\n"); + OUT(c, locp, "tcg_gen_or_i64(", &b, ", ", &res, ", ", &b, ");\n"); + OUT(c, locp, "tcg_gen_andi_i64(", &b, ", ", &b, ", ", masks[i], ")= ;\n"); + shift >>=3D 1; + } + + OUT(c, locp, "tcg_gen_shli_i64(", &a, ", ", &a, ", 1);\n"); + OUT(c, locp, "tcg_gen_or_i64(", &res, ", ", &a, ", ", &b, ");\n"); + + rvalue_free(c, locp, &a); + rvalue_free(c, locp, &b); + + return res; +} + +bool reg_equal(HexReg *r1, HexReg *r2) +{ + return !memcmp(r1, r2, sizeof(HexReg)); +} + +bool pre_equal(HexPre *p1, HexPre *p2) +{ + return !memcmp(p1, p2, sizeof(HexPre)); +} + +bool rvalue_equal(HexValue *v1, HexValue *v2) +{ + if (v1->is_dotnew !=3D v2->is_dotnew) { + return false; + } else if (v1->type =3D=3D REGISTER && v2->type =3D=3D REGISTER) { + return reg_equal(&(v1->reg), &(v2->reg)); + } else if (v1->type =3D=3D PREDICATE && v2->type =3D=3D PREDICATE) { + return pre_equal(&(v1->pre), &(v2->pre)); + } else { + return false; + } +} + +void emit_header(Context *c) +{ + EMIT_SIG(c, START_COMMENT " %s " END_COMMENT "\n", c->inst.name); + EMIT_SIG(c, "void emit_%s(DisasContext *ctx, Insn *insn, Packet *pkt", + c->inst.name); +} + +void emit_arg(Context *c, YYLTYPE *locp, HexValue *arg) +{ + switch (arg->type) { + case REGISTER: + if (arg->reg.type =3D=3D DOTNEW) { + EMIT_SIG(c, ", TCGv N%cN", arg->reg.id); + } else { + bool is64 =3D (arg->bit_width =3D=3D 64); + const char *type =3D is64 ? "TCGv_i64" : "TCGv_i32"; + char reg_id[5] =3D { 0 }; + reg_compose(c, locp, &(arg->reg), reg_id); + EMIT_SIG(c, ", %s %s", type, reg_id); + /* MuV register requires also MuN to provide its index */ + if (arg->reg.type =3D=3D MODIFIER) { + EMIT_SIG(c, ", int MuN"); + } + } + break; + case PREDICATE: + { + char suffix =3D arg->is_dotnew ? 'N' : 'V'; + EMIT_SIG(c, ", TCGv P%c%c", arg->pre.id, suffix); + } + break; + default: + { + fprintf(stderr, "emit_arg got unsupported argument!"); + abort(); + } + } +} + +void emit_footer(Context *c) +{ + EMIT(c, "}\n"); + EMIT(c, "\n"); +} + +void free_variables(Context *c, YYLTYPE *locp) +{ + for (unsigned i =3D 0; i < c->inst.allocated_count; ++i) { + Var *var =3D &c->inst.allocated[i]; + const char *suffix =3D var->bit_width =3D=3D 64 ? "i64" : "i32"; + OUT(c, locp, "tcg_temp_free_", suffix, "(", var->name, ");\n"); + } +} + +void free_instruction(Context *c) +{ + /* Reset buffers */ + c->signature_c =3D 0; + c->out_c =3D 0; + c->header_c =3D 0; + /* Free allocated register tracking */ + for (int i =3D 0; i < c->inst.allocated_count; i++) { + free((char *)c->inst.allocated[i].name); + } + /* Free INAME token value */ + free(c->inst.name); + /* Initialize instruction-specific portion of the context */ + memset(&(c->inst), 0, sizeof(Inst)); +} diff --git a/target/hexagon/idef-parser/parser-helpers.h b/target/hexagon/i= def-parser/parser-helpers.h new file mode 100644 index 0000000000..36d260ecb7 --- /dev/null +++ b/target/hexagon/idef-parser/parser-helpers.h @@ -0,0 +1,293 @@ +/* + * Copyright(c) 2019-2020 rev.ng Srls. All Rights Reserved. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; withOUT even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef PARSER_HELPERS_H +#define PARSER_HELPERS_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "idef-parser.tab.h" +#include "idef-parser.yy.h" +#include "parser-helpers.h" +#include "idef-parser.h" + +/* Decomment this to disable yyasserts */ +/* #define NDEBUG */ + +#define ERR_LINE_CONTEXT 40 + +#define START_COMMENT "/" "*" +#define END_COMMENT "*" "/" + +void yyerror(YYLTYPE *locp, + yyscan_t scanner __attribute__((unused)), + Context *c, + const char *s); + +#ifndef NDEBUG +#define yyassert(context, locp, condition, msg) \ + if (!(condition)) { \ + yyerror(locp, (context)->scanner, (context), (msg)); \ + } +#endif + +bool is_direct_predicate(HexValue *value); + +/* Print functions */ +void str_print(Context *c, YYLTYPE *locp, char *string); + +void uint64_print(Context *c, YYLTYPE *locp, uint64_t *num); + +void int_print(Context *c, YYLTYPE *locp, int *num); + +void uint_print(Context *c, YYLTYPE *locp, unsigned *num); + +void tmp_print(Context *c, YYLTYPE *locp, HexTmp *tmp); + +void pre_print(Context *c, YYLTYPE *locp, HexPre *pre, bool is_dotnew); + +void reg_compose(Context *c, YYLTYPE *locp, HexReg *reg, char reg_id[5]); + +void reg_print(Context *c, YYLTYPE *locp, HexReg *reg); + +void imm_print(Context *c, YYLTYPE *locp, HexImm *imm); + +void var_print(Context *c, YYLTYPE *locp, HexVar *var); + +void rvalue_out(Context *c, YYLTYPE *locp, void *pointer); + +/* Copy output code buffer into stdout */ +void commit(Context *c); + +#define OUT_IMPL(c, locp, x) \ + do { \ + if (__builtin_types_compatible_p(typeof(*x), char)) { \ + str_print((c), (locp), (char *) x); \ + } else if (__builtin_types_compatible_p(typeof(*x), uint64_t)) { \ + uint64_print((c), (locp), (uint64_t *) x); \ + } else if (__builtin_types_compatible_p(typeof(*x), int)) { \ + int_print((c), (locp), (int *) x); \ + } else if (__builtin_types_compatible_p(typeof(*x), unsigned)) { \ + uint_print((c), (locp), (unsigned *) x); \ + } else if (__builtin_types_compatible_p(typeof(*x), HexValue)) { \ + rvalue_out((c), (locp), (HexValue *) x); \ + } else { \ + yyassert(c, locp, false, "Unhandled print type!"); \ + } \ + } while (0); + +/* Make a FOREACH macro */ +#define FE_1(c, locp, WHAT, X) WHAT(c, locp, X) +#define FE_2(c, locp, WHAT, X, ...) \ + WHAT(c, locp, X)FE_1(c, locp, WHAT, __VA_ARGS__) +#define FE_3(c, locp, WHAT, X, ...) \ + WHAT(c, locp, X)FE_2(c, locp, WHAT, __VA_ARGS__) +#define FE_4(c, locp, WHAT, X, ...) \ + WHAT(c, locp, X)FE_3(c, locp, WHAT, __VA_ARGS__) +#define FE_5(c, locp, WHAT, X, ...) \ + WHAT(c, locp, X)FE_4(c, locp, WHAT, __VA_ARGS__) +#define FE_6(c, locp, WHAT, X, ...) \ + WHAT(c, locp, X)FE_5(c, locp, WHAT, __VA_ARGS__) +#define FE_7(c, locp, WHAT, X, ...) \ + WHAT(c, locp, X)FE_6(c, locp, WHAT, __VA_ARGS__) +#define FE_8(c, locp, WHAT, X, ...) \ + WHAT(c, locp, X)FE_7(c, locp, WHAT, __VA_ARGS__) +#define FE_9(c, locp, WHAT, X, ...) \ + WHAT(c, locp, X)FE_8(c, locp, WHAT, __VA_ARGS__) +/* repeat as needed */ + +#define GET_MACRO(_1, _2, _3, _4, _5, _6, _7, _8, _9, NAME, ...) NAME + +#define FOR_EACH(c, locp, action, ...) \ + do { \ + GET_MACRO(__VA_ARGS__, \ + FE_9, \ + FE_8, \ + FE_7, \ + FE_6, \ + FE_5, \ + FE_4, \ + FE_3, \ + FE_2, \ + FE_1)(c, locp, action, \ + __VA_ARGS__) \ + } while (0) + +#define OUT(c, locp, ...) FOR_EACH((c), (locp), OUT_IMPL, __VA_ARGS__) + +const char *cmp_swap(Context *c, YYLTYPE *locp, const char *type); + +/* Temporary values creation */ +HexValue gen_tmp(Context *c, YYLTYPE *locp, int bit_width); + +HexValue gen_local_tmp(Context *c, YYLTYPE *locp, int bit_width); + +HexValue gen_tmp_value(Context *c, + YYLTYPE *locp, + const char *value, + int bit_width); + +HexValue gen_imm_value(Context *c __attribute__((unused)), + YYLTYPE *locp, + int value, + int bit_width); + +void rvalue_free(Context *c, YYLTYPE *locp, HexValue *rvalue); + +HexValue rvalue_materialize(Context *c, YYLTYPE *locp, HexValue *rvalue); + +HexValue rvalue_extend(Context *c, YYLTYPE *locp, HexValue *rvalue); + +HexValue rvalue_truncate(Context *c, YYLTYPE *locp, HexValue *rvalue); + +int find_variable(Context *c, YYLTYPE *locp, HexValue *varid); + +void varid_allocate(Context *c, + YYLTYPE *locp, + HexValue *varid, + int width, + bool is_unsigned); + +void ea_free(Context *c, YYLTYPE *locp); + +HexValue gen_bin_cmp(Context *c, + YYLTYPE *locp, + const char *type, + HexValue *op1_ptr, + HexValue *op2_ptr); + +/* Code generation functions */ +HexValue gen_bin_op(Context *c, + YYLTYPE *locp, + enum OpType type, + HexValue *operand1, + HexValue *operand2); + +HexValue gen_cast_op(Context *c, + YYLTYPE *locp, + HexValue *source, + unsigned target_width); + +HexValue gen_extend_op(Context *c, + YYLTYPE *locp, + HexValue *src_width_ptr, + HexValue *dst_width_ptr, + HexValue *value_ptr, + bool is_unsigned); + +void gen_rdeposit_op(Context *c, + YYLTYPE *locp, + HexValue *dest, + HexValue *value, + HexValue *begin, + HexValue *width); + +void gen_deposit_op(Context *c, + YYLTYPE *locp, + HexValue *dest, + HexValue *value, + HexValue *index, + HexCast *cast); + +HexValue gen_rextract_op(Context *c, + YYLTYPE *locp, + HexValue *source, + int begin, + int width); + +HexValue gen_extract_op(Context *c, + YYLTYPE *locp, + HexValue *source, + HexValue *index, + HexExtract *extract); + +HexValue gen_read_creg(Context *c, YYLTYPE *locp, HexValue *reg); + +void gen_write_creg(Context *c, + YYLTYPE *locp, + HexValue *reg, + HexValue *value); + +void gen_assign(Context *c, + YYLTYPE *locp, + HexValue *dest, + HexValue *value); + +HexValue gen_convround(Context *c, + YYLTYPE *locp, + HexValue *source); + +HexValue gen_round(Context *c, + YYLTYPE *locp, + HexValue *source, + HexValue *position); + +HexValue gen_convround_n(Context *c, + YYLTYPE *locp, + HexValue *source_ptr, + HexValue *bit_pos_ptr); + +/* Circular addressing mode with auto-increment */ +HexValue gen_circ_op(Context *c, + YYLTYPE *locp, + HexValue *addr, + HexValue *increment, + HexValue *modifier); + +HexValue gen_locnt_op(Context *c, YYLTYPE *locp, HexValue *source); + +HexValue gen_ctpop_op(Context *c, YYLTYPE *locp, HexValue *source); + +HexValue gen_fbrev_4(Context *c, YYLTYPE *locp, HexValue *source); + +HexValue gen_fbrev_8(Context *c, YYLTYPE *locp, HexValue *source); + +HexValue gen_rotl(Context *c, YYLTYPE *locp, HexValue *source, HexValue *n= ); + +HexValue gen_deinterleave(Context *c, YYLTYPE *locp, HexValue *mixed); + +HexValue gen_interleave(Context *c, + YYLTYPE *locp, + HexValue *odd, + HexValue *even); + + +bool reg_equal(HexReg *r1, HexReg *r2); + +bool pre_equal(HexPre *p1, HexPre *p2); + +bool rvalue_equal(HexValue *v1, HexValue *v2); + +void emit_header(Context *c); + +void emit_arg(Context *c, YYLTYPE *locp, HexValue *arg); + +void emit_footer(Context *c); + +void free_variables(Context *c, YYLTYPE *locp); + +void free_instruction(Context *c); + +#endif /* PARSER_HELPERS_h */ diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index 1a008e7e86..c094adff57 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -199,7 +199,7 @@ idef_parser_input_generated =3D custom_target( command: [prog_python, '@INPUT@', semantics_generated, attribs_def, ge= n_tcg_h, '@OUTPUT@'], ) =20 -idef_parser_input_generated_prep =3D custom_target( +preprocessed_idef_parser_input_generated =3D custom_target( 'idef_parser_input.preprocessed.h.inc', output: 'idef_parser_input.preprocessed.h.inc', input: idef_parser_input_generated, @@ -212,4 +212,24 @@ flex =3D generator(find_program('flex'), output: '@PLAINNAME@.yy.c', arguments: ['-o', '@OUTPUT@', '@INPUT@']) =20 +bison =3D generator(find_program('bison'), + output: ['@BASENAME@.tab.c', '@BASENAME@.tab.h'], + arguments: ['@INPUT@', '--defines=3D@OUTPUT1@', '--outpu= t=3D@OUTPUT0@']) + +idef_parser =3D executable('idef-parser', + [flex.process(idef_parser_dir / 'idef-lexer.lex'), + bison.process(idef_parser_dir / 'idef-parser.y'), + idef_parser_dir / 'parser-helpers.c'], + include_directories: 'idef-parser') + +idef_generated_tcg =3D custom_target( + 'idef-generated-tcg', + output: ['idef-generated-emitter.c.inc', + 'idef-generated-emitter.h.inc', + 'idef-generated-enabled-instructions'], + input: preprocessed_idef_parser_input_generated, + depend_files: [hex_common_py], + command: [idef_parser, '@INPUT@', '@OUTPUT0@', '@OUTPUT1@', '@OUTPUT2@= '], +) + target_arch +=3D {'hexagon': hexagon_ss} --=20 2.30.0 From nobody Tue Nov 18 22:49:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1613080395; cv=none; d=zohomail.com; s=zohoarc; b=hvaBTjmSq2LXjeSFqHnRvZe6fVZimtAOoebB8vdPyM1M5OH3CPvamUYwehh4coZrZuwOOmmXWnVm1TloIELSAcm7qRwP8V6N3B5akve4kDgEXsc1RfibqxmUfSYsqgqoLJ/38qdbnfp00ht2IUgnsXvLCJQbaM2y509XY5I4qBg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613080395; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=cr4pj3Z81b0hwKopGGqrCVTmYkE9NfPUPLjpp7e4mwU=; b=j6jidVfZQGaqBhX5atbJtrfG8fgbLWjkZYW/O7EJO1v/TZMkwmDs07xnGc3ozDHe3/Gy9DlAsMxXdjEyOasIliggmjL3dLtZ3Ehfv09qQAd9l0v4HRxfq+vqhYGDlW/XGrMRPe3gq0xZ8GwZmAf10sYHBssaZTHLGIpWRnB6U7w= ARC-Authentication-Results: i=1; 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Thu, 11 Feb 2021 16:51:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=cr4pj3Z81b0hwKopGGqrCVTmYkE9NfPUPLjpp7e4mwU=; b=XmJ0FUYlCN7fv9tpEjRDOQ6aML 6ODPmygCkElo1EubqaUCiSZbguHDCbJM0AXScvFS3RRfHEAAZ1PbKGJAvCiVc89rYT41FfMRPzpIa h83PbUQVujuJAAy7ObMPgJFemE7yTPoGixmvjMF5LXEtlbFWuSRQgiXOmudjXrjN959o=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, Alessandro Di Federico Subject: [RFC PATCH 09/10] target/hexagon: call idef-parser functions Date: Thu, 11 Feb 2021 22:50:50 +0100 Message-Id: <20210211215051.2102435-10-ale.qemu@rev.ng> In-Reply-To: <20210211215051.2102435-1-ale.qemu@rev.ng> References: <20210211215051.2102435-1-ale.qemu@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico From: Alessandro Di Federico via X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Alessandro Di Federico Extend gen_tcg_funcs.py in order to emit calls to the functions emitted by the idef-parser, if available. Signed-off-by: Alessandro Di Federico --- target/hexagon/gen_tcg_funcs.py | 28 ++++++++++++++++++++++-- target/hexagon/hex_common.py | 10 +++++++++ target/hexagon/idef-parser/idef-parser.y | 10 +++++---- target/hexagon/meson.build | 25 ++++++++++++--------- 4 files changed, 57 insertions(+), 16 deletions(-) diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index fe4d8e5730..c3f04949a0 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -394,7 +394,29 @@ def gen_tcg_func(f, tag, regs, imms): if (hex_common.is_read(regid)): genptr_src_read_opn(f,regtype,regid,tag) =20 - if ( hex_common.skip_qemu_helper(tag) ): + if hex_common.is_idef_parser_enabled(tag): + declared =3D [] + ## Handle registers + for regtype,regid,toss,numregs in regs: + if (hex_common.is_pair(regid) + or (hex_common.is_single(regid) + and hex_common.is_old_val(regtype, regid, tag))): + declared.append("%s%sV" % (regtype, regid)) + if regtype =3D=3D "M": + declared.append("%s%sN" % (regtype, regid)) + elif hex_common.is_new_val(regtype, regid, tag): + declared.append("%s%sN" % (regtype,regid)) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + + ## Handle immediates + for immlett,bits,immshift in imms: + declared.append(hex_common.imm_name(immlett)) + + arguments =3D ", ".join(["ctx", "insn", "pkt"] + declared) + f.write(" emit_%s(%s);\n" % (tag, arguments)) + + elif ( hex_common.skip_qemu_helper(tag) ): f.write(" fGEN_TCG_%s(%s);\n" % (tag, hex_common.semdict[tag])) else: ## Generate the call to the helper @@ -455,12 +477,14 @@ def main(): hex_common.read_attribs_file(sys.argv[2]) hex_common.read_overrides_file(sys.argv[3]) hex_common.calculate_attribs() + hex_common.read_idef_parser_enabled_file(sys.argv[4]) tagregs =3D hex_common.get_tagregs() tagimms =3D hex_common.get_tagimms() =20 - with open(sys.argv[4], 'w') as f: + with open(sys.argv[5], 'w') as f: f.write("#ifndef HEXAGON_TCG_FUNCS_H\n") f.write("#define HEXAGON_TCG_FUNCS_H\n\n") + f.write("#include \"idef-generated-emitter.h.inc\"\n\n") =20 for tag in hex_common.tags: ## Skip the priv instructions diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index b3b534057d..648ad29e94 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -28,6 +28,7 @@ macros =3D {} # macro -> macro information... attribinfo =3D {} # Register information and misc tags =3D [] # list of all tags overrides =3D {} # tags with helper overrides +idef_parser_enabled =3D {} # tags enabled for idef-parser =20 # We should do this as a hash for performance, # but to keep order let's keep it as a list. @@ -201,6 +202,9 @@ def need_ea(tag): def skip_qemu_helper(tag): return tag in overrides.keys() =20 +def is_idef_parser_enabled(tag): + return tag in idef_parser_enabled + def imm_name(immlett): return "%siV" % immlett =20 @@ -232,3 +236,9 @@ def read_overrides_file(name): continue tag =3D overridere.findall(line)[0] overrides[tag] =3D True + +def read_idef_parser_enabled_file(name): + global idef_parser_enabled + with open(name, "r") as idef_parser_enabled_file: + lines =3D idef_parser_enabled_file.read().strip().split("\n") + idef_parser_enabled =3D set(lines) diff --git a/target/hexagon/idef-parser/idef-parser.y b/target/hexagon/idef= -parser/idef-parser.y index 80490101ca..9adf165c76 100644 --- a/target/hexagon/idef-parser/idef-parser.y +++ b/target/hexagon/idef-parser/idef-parser.y @@ -357,7 +357,7 @@ assign_statement : lvalue ASSIGN rvalue $9 =3D rvalue_truncate(c, &@1, &$9); } OUT(c, &@1, "if (insn->slot =3D=3D 0 && pkt->pkt_has_store_s1) {\n"); - OUT(c, &@1, "process_store(ctx, 1);\n"); + OUT(c, &@1, "process_store(ctx, pkt, 1);\n"); OUT(c, &@1, "}\n"); OUT(c, &@1, "tcg_gen_qemu_ld", size_suffix, sign_suffix); OUT(c, &@1, "(", &$11, ", ", &$9, ", 0);\n"); @@ -1228,9 +1228,11 @@ int main(int argc, char **argv) buffer =3D yy_scan_string(context.input_buffer, context.scanner); /* Start the parsing procedure */ yyparse(context.scanner, &context); - fprintf(stderr, "%d/%d meta instructions have been implemented!\n", - context.implemented_insn, - context.total_insn); + if (context.implemented_insn !=3D context.total_insn) { + fprintf(stderr, "%d/%d meta instructions have been implemented!\n", + context.implemented_insn, + context.total_insn); + } fputs("#endif " START_COMMENT " HEX_EMITTER_h " END_COMMENT "\n", defines_file); /* Cleanup */ diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index c094adff57..7a0fc96844 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -74,15 +74,6 @@ helper_protos_generated =3D custom_target( ) hexagon_ss.add(helper_protos_generated) =20 -tcg_funcs_generated =3D custom_target( - 'tcg_funcs_generated.c.inc', - output: 'tcg_funcs_generated.c.inc', - input: 'gen_tcg_funcs.py', - depends: [semantics_generated], - depend_files: [hex_common_py, attribs_def, gen_tcg_h], - command: [prog_python, '@INPUT@', semantics_generated, attribs_def, ge= n_tcg_h, '@OUTPUT@'], -) -hexagon_ss.add(tcg_funcs_generated) =20 tcg_func_table_generated =3D custom_target( 'tcg_func_table_generated.c.inc', @@ -224,7 +215,7 @@ idef_parser =3D executable('idef-parser', =20 idef_generated_tcg =3D custom_target( 'idef-generated-tcg', - output: ['idef-generated-emitter.c.inc', + output: ['idef-generated-emitter.c', 'idef-generated-emitter.h.inc', 'idef-generated-enabled-instructions'], input: preprocessed_idef_parser_input_generated, @@ -232,4 +223,18 @@ idef_generated_tcg =3D custom_target( command: [idef_parser, '@INPUT@', '@OUTPUT0@', '@OUTPUT1@', '@OUTPUT2@= '], ) =20 +idef_generated_list =3D idef_generated_tcg[2].full_path() + +hexagon_ss.add(idef_generated_tcg) + +tcg_funcs_generated =3D custom_target( + 'tcg_funcs_generated.c.inc', + output: 'tcg_funcs_generated.c.inc', + input: 'gen_tcg_funcs.py', + depends: [semantics_generated, idef_generated_tcg], + depend_files: [hex_common_py, attribs_def, gen_tcg_h], + command: [prog_python, '@INPUT@', semantics_generated, attribs_def, ge= n_tcg_h, idef_generated_list, '@OUTPUT@'], +) +hexagon_ss.add(tcg_funcs_generated) + target_arch +=3D {'hexagon': hexagon_ss} --=20 2.30.0 From nobody Tue Nov 18 22:49:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1613080921; cv=none; d=zohomail.com; s=zohoarc; b=FQKd6jBV/7N7dNloREl+O0TsF4KV9dqfo6mV3uI50eIzrleUAZpHp0kEXWDfcUsEqa7p2oDgzs4cYuUAdo0Ujx1/HXM9bzNc/LCFkUwmpM28AVEWpFG18upWLwH7M0vPbOYByVK8BET4JdUVHxY3pXwzARgGQDsWFcX0UFaHRM0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613080921; 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b=jPP08QYwFFdwuoqBITts6bh800 TrxYJzXOa9keSCVzDIvCpcCgrYO481OIMnawwxGKybIeE2piqdE2Ygru/6gsSZHOdZz+PwuFgbZFN tccFLAnRBpVNYgvzFNV+CYsa9JUtt/vQiuBQtgv/L2gfp74VwA1VnOx4xa0FWp+ZMqc0=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, Alessandro Di Federico Subject: [RFC PATCH 10/10] target/hexagon: import additional tests Date: Thu, 11 Feb 2021 22:50:51 +0100 Message-Id: <20210211215051.2102435-11-ale.qemu@rev.ng> In-Reply-To: <20210211215051.2102435-1-ale.qemu@rev.ng> References: <20210211215051.2102435-1-ale.qemu@rev.ng> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico From: Alessandro Di Federico via X-ZohoMail-DKIM: fail (Header signature does not verify) From: Niccol=C3=B2 Izzo Signed-off-by: Alessandro Di Federico --- tests/tcg/hexagon/Makefile.target | 35 ++++++++++++++++- tests/tcg/hexagon/crt.S | 28 +++++++++++++ tests/tcg/hexagon/first.S | 24 ++++++------ tests/tcg/hexagon/test_abs.S | 20 ++++++++++ tests/tcg/hexagon/test_add.S | 20 ++++++++++ tests/tcg/hexagon/test_andp.S | 23 +++++++++++ tests/tcg/hexagon/test_bitcnt.S | 42 ++++++++++++++++++++ tests/tcg/hexagon/test_bitsplit.S | 25 ++++++++++++ tests/tcg/hexagon/test_call.S | 63 ++++++++++++++++++++++++++++++ tests/tcg/hexagon/test_clobber.S | 35 +++++++++++++++++ tests/tcg/hexagon/test_cmp.S | 34 ++++++++++++++++ tests/tcg/hexagon/test_cmpy.S | 31 +++++++++++++++ tests/tcg/hexagon/test_djump.S | 24 ++++++++++++ tests/tcg/hexagon/test_dotnew.S | 39 ++++++++++++++++++ tests/tcg/hexagon/test_dstore.S | 29 ++++++++++++++ tests/tcg/hexagon/test_ext.S | 18 +++++++++ tests/tcg/hexagon/test_fibonacci.S | 33 ++++++++++++++++ tests/tcg/hexagon/test_hello.S | 21 ++++++++++ tests/tcg/hexagon/test_hl.S | 19 +++++++++ tests/tcg/hexagon/test_hwloops.S | 25 ++++++++++++ tests/tcg/hexagon/test_jmp.S | 25 ++++++++++++ tests/tcg/hexagon/test_lsr.S | 39 ++++++++++++++++++ tests/tcg/hexagon/test_mpyi.S | 20 ++++++++++ tests/tcg/hexagon/test_packet.S | 26 ++++++++++++ tests/tcg/hexagon/test_reorder.S | 31 +++++++++++++++ tests/tcg/hexagon/test_round.S | 31 +++++++++++++++ tests/tcg/hexagon/test_vavgw.S | 33 ++++++++++++++++ tests/tcg/hexagon/test_vcmpb.S | 32 +++++++++++++++ tests/tcg/hexagon/test_vcmpw.S | 29 ++++++++++++++ tests/tcg/hexagon/test_vcmpy.S | 50 ++++++++++++++++++++++++ tests/tcg/hexagon/test_vlsrw.S | 23 +++++++++++ tests/tcg/hexagon/test_vmaxh.S | 37 ++++++++++++++++++ tests/tcg/hexagon/test_vminh.S | 37 ++++++++++++++++++ tests/tcg/hexagon/test_vpmpyh.S | 30 ++++++++++++++ tests/tcg/hexagon/test_vspliceb.S | 33 ++++++++++++++++ 35 files changed, 1051 insertions(+), 13 deletions(-) create mode 100644 tests/tcg/hexagon/crt.S create mode 100644 tests/tcg/hexagon/test_abs.S create mode 100644 tests/tcg/hexagon/test_add.S create mode 100644 tests/tcg/hexagon/test_andp.S create mode 100644 tests/tcg/hexagon/test_bitcnt.S create mode 100644 tests/tcg/hexagon/test_bitsplit.S create mode 100644 tests/tcg/hexagon/test_call.S create mode 100644 tests/tcg/hexagon/test_clobber.S create mode 100644 tests/tcg/hexagon/test_cmp.S create mode 100644 tests/tcg/hexagon/test_cmpy.S create mode 100644 tests/tcg/hexagon/test_djump.S create mode 100644 tests/tcg/hexagon/test_dotnew.S create mode 100644 tests/tcg/hexagon/test_dstore.S create mode 100644 tests/tcg/hexagon/test_ext.S create mode 100644 tests/tcg/hexagon/test_fibonacci.S create mode 100644 tests/tcg/hexagon/test_hello.S create mode 100644 tests/tcg/hexagon/test_hl.S create mode 100644 tests/tcg/hexagon/test_hwloops.S create mode 100644 tests/tcg/hexagon/test_jmp.S create mode 100644 tests/tcg/hexagon/test_lsr.S create mode 100644 tests/tcg/hexagon/test_mpyi.S create mode 100644 tests/tcg/hexagon/test_packet.S create mode 100644 tests/tcg/hexagon/test_reorder.S create mode 100644 tests/tcg/hexagon/test_round.S create mode 100644 tests/tcg/hexagon/test_vavgw.S create mode 100644 tests/tcg/hexagon/test_vcmpb.S create mode 100644 tests/tcg/hexagon/test_vcmpw.S create mode 100644 tests/tcg/hexagon/test_vcmpy.S create mode 100644 tests/tcg/hexagon/test_vlsrw.S create mode 100644 tests/tcg/hexagon/test_vmaxh.S create mode 100644 tests/tcg/hexagon/test_vminh.S create mode 100644 tests/tcg/hexagon/test_vpmpyh.S create mode 100644 tests/tcg/hexagon/test_vspliceb.S diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile= .target index 616af697fe..f4a774cda1 100644 --- a/tests/tcg/hexagon/Makefile.target +++ b/tests/tcg/hexagon/Makefile.target @@ -32,7 +32,7 @@ CFLAGS +=3D -Wno-incompatible-pointer-types -Wno-undefine= d-internal HEX_SRC=3D$(SRC_PATH)/tests/tcg/hexagon VPATH +=3D $(HEX_SRC) =20 -first: $(HEX_SRC)/first.S +%: $(HEX_SRC)/%.S $(HEX_SRC)/crt.S $(CC) -static -mv67 -nostdlib $^ -o $@ =20 HEX_TESTS =3D first @@ -43,4 +43,37 @@ HEX_TESTS +=3D mem_noshuf HEX_TESTS +=3D atomics HEX_TESTS +=3D fpstuff =20 +HEX_TESTS +=3D test_abs +HEX_TESTS +=3D test_add +HEX_TESTS +=3D test_andp +HEX_TESTS +=3D test_bitcnt +HEX_TESTS +=3D test_bitsplit +HEX_TESTS +=3D test_call +HEX_TESTS +=3D test_clobber +HEX_TESTS +=3D test_cmp +HEX_TESTS +=3D test_cmpy +HEX_TESTS +=3D test_djump +HEX_TESTS +=3D test_dotnew +HEX_TESTS +=3D test_dstore +HEX_TESTS +=3D test_ext +HEX_TESTS +=3D test_fibonacci +HEX_TESTS +=3D test_hello +HEX_TESTS +=3D test_hl +HEX_TESTS +=3D test_hwloops +HEX_TESTS +=3D test_jmp +HEX_TESTS +=3D test_lsr +HEX_TESTS +=3D test_mpyi +HEX_TESTS +=3D test_packet +HEX_TESTS +=3D test_reorder +HEX_TESTS +=3D test_round +HEX_TESTS +=3D test_vavgw +HEX_TESTS +=3D test_vcmpb +HEX_TESTS +=3D test_vcmpw +HEX_TESTS +=3D test_vcmpy +HEX_TESTS +=3D test_vlsrw +HEX_TESTS +=3D test_vmaxh +HEX_TESTS +=3D test_vminh +HEX_TESTS +=3D test_vpmpyh +HEX_TESTS +=3D test_vspliceb + TESTS +=3D $(HEX_TESTS) diff --git a/tests/tcg/hexagon/crt.S b/tests/tcg/hexagon/crt.S new file mode 100644 index 0000000000..2c10577470 --- /dev/null +++ b/tests/tcg/hexagon/crt.S @@ -0,0 +1,28 @@ +#define SYS_exit_group 94 + + .text + .globl init +init: + { + allocframe(r29,#0):raw + } + { + r0=3D#256 + } + { + dealloc_return + } + + .space 240 + + .globl pass +pass: + r0 =3D #0 + r6 =3D #SYS_exit_group + trap0(#1) + + .globl fail +fail: + r0 =3D #1 + r6 =3D #SYS_exit_group + trap0(#1) diff --git a/tests/tcg/hexagon/first.S b/tests/tcg/hexagon/first.S index e9f2d963ec..7f96b4332e 100644 --- a/tests/tcg/hexagon/first.S +++ b/tests/tcg/hexagon/first.S @@ -21,24 +21,24 @@ =20 #define FD_STDOUT 1 =20 - .type str,@object - .section .rodata + .type str,@object + .section .rodata str: - .string "Hello!\n" - .size str, 8 + .string "Hello!\n" + .size str, 8 =20 .text .global _start _start: - r6 =3D #SYS_write - r0 =3D #FD_STDOUT - r1 =3D ##str - r2 =3D #7 - trap0(#1) + r6 =3D #SYS_write + r0 =3D #FD_STDOUT + r1 =3D ##str + r2 =3D #7 + trap0(#1) =20 - r0 =3D #0 - r6 =3D #SYS_exit_group - trap0(#1) + r0 =3D #0 + r6 =3D #SYS_exit_group + trap0(#1) =20 .section ".note.ABI-tag", "a" .align 4 diff --git a/tests/tcg/hexagon/test_abs.S b/tests/tcg/hexagon/test_abs.S new file mode 100644 index 0000000000..880b2886b5 --- /dev/null +++ b/tests/tcg/hexagon/test_abs.S @@ -0,0 +1,20 @@ +/* Purpose: test example, verify the soundness of the abs operation */ + + .text + .globl _start + +_start: + { + call init + } + { + r1=3D#-2 + r2=3D#2 + } + { + r3=3Dabs(r1) + } + { + p0 =3D cmp.eq(r3, r2); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_add.S b/tests/tcg/hexagon/test_add.S new file mode 100644 index 0000000000..ce2ed295a0 --- /dev/null +++ b/tests/tcg/hexagon/test_add.S @@ -0,0 +1,20 @@ +/* Purpose: test example, verify the soundness of the add operation */ + + .text + .globl _start + +_start: + { + call init + } + { + r1=3D#0 + r2=3D#0 + } + { + r3=3Dadd(r2,r3) + } + { + p0 =3D cmp.eq(r3, #0); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_andp.S b/tests/tcg/hexagon/test_andp.S new file mode 100644 index 0000000000..3c4aa8b2ae --- /dev/null +++ b/tests/tcg/hexagon/test_andp.S @@ -0,0 +1,23 @@ +/* Purpose: test a multiple predicate AND combination */ + + .text + .globl _start + +_start: + { + r1+=3Dsub(r2,r3) + call init + } + { + r0=3D#0 + r1=3D#1 + } + { + p0=3Dcmp.gt(r0,r1) + p0=3Dcmp.gt(r0,r1) + p0=3Dcmp.gt(r1,r0) + } + { + if (!p0) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_bitcnt.S b/tests/tcg/hexagon/test_bitcn= t.S new file mode 100644 index 0000000000..df77fe61e2 --- /dev/null +++ b/tests/tcg/hexagon/test_bitcnt.S @@ -0,0 +1,42 @@ +/* Purpose: test example, verify the soundness of the cl[01] operations + * + * the number 0x000001aa has 23 leading zeroes + * they become 55 when considered as 64 bit register + * and it has 1 trailing zero + */ + .text + .globl _start + +_start: + { + call init + } + { + r0=3D#426 + r1=3D#0 + } + { + r2=3Dcl0(r0) + } + { + p0 =3D cmp.eq(r2, #23); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + r2=3Dcl0(r1:0) + } + { + p0 =3D cmp.eq(r2, #55); if (p0.new) jump:t test3 + jump fail + } + +test3: + { + r2=3Dct0(r0) + } + { + p0 =3D cmp.eq(r2, #1); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_bitsplit.S b/tests/tcg/hexagon/test_bit= split.S new file mode 100644 index 0000000000..787cce72e4 --- /dev/null +++ b/tests/tcg/hexagon/test_bitsplit.S @@ -0,0 +1,25 @@ +/* Purpose: test example, verify the soundness of the bitsplit operation */ + + .text + .globl _start + +_start: + { + call init + } + { + r1=3D#187 + } + { + r3:2=3Dbitsplit(r1, #3) + } + { + p0 =3D cmp.eq(r2, #3); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + p0 =3D cmp.eq(r3, #23); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_call.S b/tests/tcg/hexagon/test_call.S new file mode 100644 index 0000000000..53a2450522 --- /dev/null +++ b/tests/tcg/hexagon/test_call.S @@ -0,0 +1,63 @@ +/* Purpose: test function calls and duplex instructions. + * The string "Hello there, I'm a test string!" with the first letter repl= aced + * with a capital L should be printed out. + */ + + .text + .globl test +test: + { + jumpr r31 + memb(r0+#0)=3D#76 + } +.Lfunc_end0: +.Ltmp0: + .size test, .Ltmp0-test + + .globl _start +_start: + { + call init + } + { + call test + r0=3D##dummy_buffer + allocframe(#0) + } + { + call write + } + { + jump pass + } + { + r31:30=3Ddeallocframe(r30):raw + } +.Lfunc_end1: +.Ltmp1: + .size _start, .Ltmp1-_start +write: + { + r2=3D##dummy_buffer + } + { r0=3Dr2; } + { + r2=3D#256 + } + { r1=3Dr2; } + { trap0(#7); } + { + jumpr r31 + } +.Lfunc_end2: +.Ltmp2: + .size write, .Ltmp2-write + + .type dummy_buffer,@object + .data + .globl dummy_buffer + .p2align 3 +dummy_buffer: + .string "Hello there, I'm a test string!\n" + .space 223 + .size dummy_buffer, 256 diff --git a/tests/tcg/hexagon/test_clobber.S b/tests/tcg/hexagon/test_clob= ber.S new file mode 100644 index 0000000000..198817ebd5 --- /dev/null +++ b/tests/tcg/hexagon/test_clobber.S @@ -0,0 +1,35 @@ +/* Purpose: demonstrate the succesful operation of the register save mecha= nism, + * in which the caller saves the registers that will be clobbered, and res= tores + * them after the call. + */ + + .text + .globl _start + +_start: + { + call init + } + { + r16=3D#47 + r17=3D#155 + } + { + memd(r29+#-16)=3Dr17:16; allocframe(#8) + } + { + r16=3D#255 + r17=3D#42 + } + { + r17:16=3Dmemd(r29+#0); deallocframe + } + { + r3=3Dadd(r16,r17) + } + { + p0 =3D cmp.eq(r3, #202); if (p0.new) jump:t pass + } + { + jump fail + } diff --git a/tests/tcg/hexagon/test_cmp.S b/tests/tcg/hexagon/test_cmp.S new file mode 100644 index 0000000000..31ee9565fe --- /dev/null +++ b/tests/tcg/hexagon/test_cmp.S @@ -0,0 +1,34 @@ +/* Purpose: test a signed and unsigned comparison */ + + .text + .globl _start + +_start: + { + call init + } + { + jump signed + } + + .globl signed +signed: + { + r0=3D#-2 + r1=3D#0 + } + { + p0 =3D cmp.lt(r0, r1); if (p0.new) jump:t unsigned + jump fail + } + + .globl unsigned +unsigned: + { + r0=3D#-2 + r1=3D#0 + } + { + p0 =3D cmp.gtu(r0, r1); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_cmpy.S b/tests/tcg/hexagon/test_cmpy.S new file mode 100644 index 0000000000..0b3dfb95de --- /dev/null +++ b/tests/tcg/hexagon/test_cmpy.S @@ -0,0 +1,31 @@ +/* Purpose: test example, verify the soundness of the cmpy operation + * + * 3j+5 * 2j+4 =3D 22j+14 + * + * the complex multiply between 0x00030005 and 0x00020004 is 0x00000016000= 0000e + */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=3D#196613 + r1=3D#131076 + } + { + r3:2=3Dcmpy(r0, r1):sat + } + { + p0 =3D cmp.eq(r2, #14); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + p0 =3D cmp.eq(r3, #22); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_djump.S b/tests/tcg/hexagon/test_djump.S new file mode 100644 index 0000000000..dbad7eb0a1 --- /dev/null +++ b/tests/tcg/hexagon/test_djump.S @@ -0,0 +1,24 @@ +/* Purpose: show dual jumps actually work. This program features a packet = where + * two jumps should (in theory) be performed if !P0. However, we correctly + * handle the situation by performing only the first one and ignoring the = second + * one. This can be verified by checking that the CPU dump contains 0xDEAD= BEEF + * in R2. + */ + + .text + .globl _start + +_start: + { + call init + } + { + r1 =3D #255; + } + { + p0 =3D r1; + } + { + if (p0) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_dotnew.S b/tests/tcg/hexagon/test_dotne= w.S new file mode 100644 index 0000000000..3897c6bc96 --- /dev/null +++ b/tests/tcg/hexagon/test_dotnew.S @@ -0,0 +1,39 @@ +/* Purpose: test the .new operator while performing memory stores. + * In the final CPU dump R0 should contain 3, R1 should contain 2 and R2 s= hould + * contain 1. + */ + .text + .globl _start + +_start: + { + call init + } + { + r0=3D#1 + memw(sp+#0)=3Dr0.new + } + { + r1=3D#2 + memw(sp+#4)=3Dr1.new + } + { + r2=3D#3 + memw(sp+#8)=3Dr2.new + } + { + r0=3Dmemw(sp+#8) + } + { + r1=3Dmemw(sp+#4) + } + { + r2=3Dmemw(sp+#0) + } + { + r3=3Dmpyi(r1,r2) + } + { + p0 =3D cmp.eq(r3, #2); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_dstore.S b/tests/tcg/hexagon/test_dstor= e.S new file mode 100644 index 0000000000..62c4301eb1 --- /dev/null +++ b/tests/tcg/hexagon/test_dstore.S @@ -0,0 +1,29 @@ +/* Purpose: test dual stores correctness. + * In this example the values 1 and 2 are both written on the top of the s= tack + * in a single packet. + * The value is then read back in R3, which should contain only the latest= value + * written (2). + */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=3D#1 + r1=3D#2 + } + { + memw(sp+#0)=3Dr0 + memw(sp+#0)=3Dr1 + } + { + r3=3Dmemw(sp+#0) + } + { + p0 =3D cmp.eq(r3, #2); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_ext.S b/tests/tcg/hexagon/test_ext.S new file mode 100644 index 0000000000..0f6e21593a --- /dev/null +++ b/tests/tcg/hexagon/test_ext.S @@ -0,0 +1,18 @@ +/* Purpose: test immediate extender instructions. + * In the CPU dump R0 should contain 0xDEADBEEF. + */ + + .text + .globl _start + +_start: + { + call init + } + { + r2=3D##-559038737 + } + { + p0 =3D cmp.eq(r2, ##-559038737); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_fibonacci.S b/tests/tcg/hexagon/test_fi= bonacci.S new file mode 100644 index 0000000000..41cb1517cb --- /dev/null +++ b/tests/tcg/hexagon/test_fibonacci.S @@ -0,0 +1,33 @@ +/* Purpose: computes the Fibonacci series up to a constant number. */ + + .text + .globl _start + +_start: + { + call init + } + { + r2=3D#100 + } + { + p0=3Dcmp.gt(r2,#0); if (!p0.new) jump:nt .LBB0_3 + } + { + r3=3D#0 + r4=3D#1 + } +.LBB0_2: + { + r5=3Dr4 + } + { + p0=3Dcmp.gt(r2,r5); if (p0.new) jump:nt .LBB0_2 + r4=3Dadd(r3,r4) + r3=3Dr5 + } +.LBB0_3: + { + p0 =3D cmp.eq(r3, #144); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_hello.S b/tests/tcg/hexagon/test_hello.S new file mode 100644 index 0000000000..89c7da677f --- /dev/null +++ b/tests/tcg/hexagon/test_hello.S @@ -0,0 +1,21 @@ +/* Purpose: simple hello world program. */ + + .text + .globl _start + +_start: + { + call init + } + { r0=3D#4; } + { + r1=3D##.L.str + } + { trap0(#0); } + { + jump pass + } + +.L.str: + .string "Hello world!\n" + .size .L.str, 14 diff --git a/tests/tcg/hexagon/test_hl.S b/tests/tcg/hexagon/test_hl.S new file mode 100644 index 0000000000..217b3143e2 --- /dev/null +++ b/tests/tcg/hexagon/test_hl.S @@ -0,0 +1,19 @@ +/* Purpose: test example, verify the soundness of the high/low assignment = */ + + .text + .globl _start + +_start: + { + call init + } + { + r0.H=3D#42 + } + { + r0.L=3D#69 + } + { + p0 =3D cmp.eq(r0, #2752581); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_hwloops.S b/tests/tcg/hexagon/test_hwlo= ops.S new file mode 100644 index 0000000000..8337083d8e --- /dev/null +++ b/tests/tcg/hexagon/test_hwloops.S @@ -0,0 +1,25 @@ +/* Purpose: simple C Program to test hardware loops. + * It should print numbersfrom 0 to 9. + */ + + .text + .globl _start + +_start: + { + call init + } + { + loop0(.LBB0_1,#10) + r2=3D#0 + } +.Ltmp0: +.LBB0_1: + { + r2=3Dadd(r2,#1) + nop + }:endloop0 + { + p0 =3D cmp.eq(r2, #10); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_jmp.S b/tests/tcg/hexagon/test_jmp.S new file mode 100644 index 0000000000..cd87bac89b --- /dev/null +++ b/tests/tcg/hexagon/test_jmp.S @@ -0,0 +1,25 @@ +/* Purpose: test example, verify the soundness of the add operation */ + + .text + .globl _start + +_start: + { + call init + } + { + r1=3D#0 + r2=3D#0 + } + { + r3=3Dadd(r2,r3) + } + { + p0 =3D cmp.eq(r3, #0) + } + { + if (p0) jump:t pass + } + { + jump fail + } diff --git a/tests/tcg/hexagon/test_lsr.S b/tests/tcg/hexagon/test_lsr.S new file mode 100644 index 0000000000..202eb4aec7 --- /dev/null +++ b/tests/tcg/hexagon/test_lsr.S @@ -0,0 +1,39 @@ +/* Purpose: test the soundness of the lsr operation */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=3D#-56984 + r1=3D#2147483647 + } + { + r2=3D#0x19 + } + { + r0&=3Dlsr(r1, r2) + } + { + p0 =3D cmp.eq(r0, #0x28); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + r0=3D#0x0000000a + r1=3D#0x00000000 + } + { + r2=3D#-1 + } + { + r1:0=3Dlsl(r1:0, r2) + } + { + p0 =3D cmp.eq(r0, #0x5); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_mpyi.S b/tests/tcg/hexagon/test_mpyi.S new file mode 100644 index 0000000000..b8e0d50b68 --- /dev/null +++ b/tests/tcg/hexagon/test_mpyi.S @@ -0,0 +1,20 @@ +/* Purpose: test a simple multiplication operation */ + + .text + .globl _start + +_start: + { + call init + } + { + r1=3D#4 + r2=3D#6 + } + { + r3=3Dmpyi(r1,r2) + } + { + p0 =3D cmp.eq(r3, #24); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_packet.S b/tests/tcg/hexagon/test_packe= t.S new file mode 100644 index 0000000000..d26e284be9 --- /dev/null +++ b/tests/tcg/hexagon/test_packet.S @@ -0,0 +1,26 @@ +/* Purpose: test that writes of a register in a packet are performed only = after + * that packet has finished its execution. + */ + + .text + .globl _start + +_start: + { + call init + } + { + r2=3D#4 + r3=3D#6 + } + { + memw(sp+#0)=3Dr2 + } + { + r3=3Dmemw(sp+#0) + r0=3Dadd(r2,r3) + } + { + p0 =3D cmp.eq(r0, #10); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_reorder.S b/tests/tcg/hexagon/test_reor= der.S new file mode 100644 index 0000000000..508d5302f9 --- /dev/null +++ b/tests/tcg/hexagon/test_reorder.S @@ -0,0 +1,31 @@ +/* Purpose: demonstrate handling of .new uses appearing before the associa= ted + * definition. + * Here we perform a jump that skips the code resetting R2 from 0xDEADBEEF= to 0, + * only if P0.new is true, but P0 is assigned to 1 (R4) in the next instru= ction + * in the packet. + * A successful run of the program will show R2 retaining the 0xDEADBEEF v= alue + * in the CPU dump. + */ + + .text + .globl _start + +_start: + { + call init + } + { r2=3D#-559038737 } + { r4=3D#1 } + { + if (p0.new) jump:nt skip + p0=3Dr4; + } + +fallthrough: + { r2=3D#0 } + +skip: + { + p0 =3D cmp.eq(r2, #-559038737); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_round.S b/tests/tcg/hexagon/test_round.S new file mode 100644 index 0000000000..2becd62c4c --- /dev/null +++ b/tests/tcg/hexagon/test_round.S @@ -0,0 +1,31 @@ +/* Purpose: test example, verify the soundness of the cround operation + * 106 =3D 0b1101010 with the comma at third digit is 12.5 which is cround= ed to 12 + * but rounded to 13 + */ + + .text + .globl _start + +_start: + { + call init + } + { + r1=3D#200 + } + { + r2=3Dround(r1, #4) + } + { + p0 =3D cmp.eq(r2, #13); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + r2=3Dcround(r1, #4) + } + { + p0 =3D cmp.eq(r2, #12); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_vavgw.S b/tests/tcg/hexagon/test_vavgw.S new file mode 100644 index 0000000000..8f67238900 --- /dev/null +++ b/tests/tcg/hexagon/test_vavgw.S @@ -0,0 +1,33 @@ +/* Purpose: test example, verify the soundness of the vavgw operation + * + * 0x00030001 averaged with 0x00010003 results 0x00020002 + */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=3D#3 + r1=3D#1 + } + { + r2=3D#1 + r3=3D#3 + } + { + r1:0=3Dvavgw(r1:0, r3:2):crnd + } + { + p0 =3D cmp.eq(r0, #2); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + p0 =3D cmp.eq(r1, #2); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_vcmpb.S b/tests/tcg/hexagon/test_vcmpb.S new file mode 100644 index 0000000000..3c6700a63a --- /dev/null +++ b/tests/tcg/hexagon/test_vcmpb.S @@ -0,0 +1,32 @@ +/* Purpose: test example, verify the soundness of the vector compare bytes + * operation + * + * Vector word comparison between 0x1234567887654321 and 0x1234567800000000 + * should result in 0x11110000 + */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=3D#305419896 + r1=3D#-2023406815 + } + { + r2=3D#305419896 + r3=3D#0 + } + { + p2=3Dvcmpb.eq(r1:0, r3:2) + } + { + r4=3Dp2 + } + { + p0 =3D cmp.eq(r4, #15); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_vcmpw.S b/tests/tcg/hexagon/test_vcmpw.S new file mode 100644 index 0000000000..112f08c92f --- /dev/null +++ b/tests/tcg/hexagon/test_vcmpw.S @@ -0,0 +1,29 @@ +/* Purpose: test example, verify the soundness of the vector compare words + * operation + * + * Vector word comparison between 0x1234567887654321 and 0x1234567800000000 + * should result in 0x11110000 + */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=3D#305419896 + r1=3D#-2023406815 + } + { + r2=3D#305419896 + r3=3D#0 + } + { + p2=3Dvcmpw.eq(r1:0, r3:2) + } + { + if (p2) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_vcmpy.S b/tests/tcg/hexagon/test_vcmpy.S new file mode 100644 index 0000000000..df379f9186 --- /dev/null +++ b/tests/tcg/hexagon/test_vcmpy.S @@ -0,0 +1,50 @@ +/* Purpose: test example, verify the soundness of the vcmpy operation + * this operation is a complex multiply and accumulate on vectors of two v= alues + * + * (3j+5 * 2j+4) + (4j+6 * 5j+2) =3D 22j+14 + * + * the complex multiply between 0x00030005 and 0x00020004 is 0x0000001600= 00000e + * the complex multiply between 0x00040006 and 0x00050002 is 0x0000001600= 00000e + */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=3D#196613 + r1=3D#131076 + } + { + r2=3D#262150 + r3=3D#327682 + } + { + r5:4=3Dvcmpyr(r1:0, r3:2):sat + r7:6=3Dvcmpyi(r1:0, r3:2):sat + } + { + p0 =3D cmp.eq(r4, #18); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + p0 =3D cmp.eq(r5, #-2); if (p0.new) jump:t test3 + jump fail + } + +test3: + { + p0 =3D cmp.eq(r6, #38); if (p0.new) jump:t test4 + jump fail + } + +test4: + { + p0 =3D cmp.eq(r7, #24); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_vlsrw.S b/tests/tcg/hexagon/test_vlsrw.S new file mode 100644 index 0000000000..962ec99543 --- /dev/null +++ b/tests/tcg/hexagon/test_vlsrw.S @@ -0,0 +1,23 @@ +/* Purpose: test the soundness of the vlsrw operation */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=3D#0x00000001 + r1=3D#0x00000001 + } + { + r1:0=3Dvlsrw(r1:0, #1) + } + { + r0 =3D add(r0, r1) + } + { + p0 =3D cmp.eq(r0, #0); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_vmaxh.S b/tests/tcg/hexagon/test_vmaxh.S new file mode 100644 index 0000000000..1fce935e35 --- /dev/null +++ b/tests/tcg/hexagon/test_vmaxh.S @@ -0,0 +1,37 @@ +/* Purpose: test example, verify the soundness of the vrmaxh operation + * + * the maximum between 0x0002000300010005 and 0x0003000200020007 is + * 0x0003000300020007. + * + * r1=3D0x00010003 r0=3D0x00010005 r3=3D0x00030002 r2= =3D0x00020007 + * result: r1=3D0x00030003 r0=3D0x00020007 + */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=3D#65541 + r1=3D#65539 + } + { + r2=3D#131079 + r3=3D#196610 + } + { + r1:0=3Dvmaxh(r1:0, r3:2) + } + { + p0 =3D cmp.eq(r0, #131079); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + p0 =3D cmp.eq(r1, #196611); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_vminh.S b/tests/tcg/hexagon/test_vminh.S new file mode 100644 index 0000000000..6c6d18c673 --- /dev/null +++ b/tests/tcg/hexagon/test_vminh.S @@ -0,0 +1,37 @@ +/* Purpose: test example, verify the soundness of the vrmaxh operation + * + * the minimum between 0x0002000300010005 and 0x0003000200020007 is + * 0x0003000300020007 + * + * r1=3D0x00010003 r0=3D0x00010005 r3=3D0x00030002 r2= =3D0x00020007 + * result: r1=3D0x00010002 r0=3D0x00010005 + */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=3D#65541 + r1=3D#65539 + } + { + r2=3D#131079 + r3=3D#196610 + } + { + r1:0=3Dvminh(r1:0, r3:2) + } + { + p0 =3D cmp.eq(r0, #65541); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + p0 =3D cmp.eq(r1, #65538); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_vpmpyh.S b/tests/tcg/hexagon/test_vpmpy= h.S new file mode 100644 index 0000000000..942d691da4 --- /dev/null +++ b/tests/tcg/hexagon/test_vpmpyh.S @@ -0,0 +1,30 @@ +/* Purpose: test example, verify the soundness of the vpmpyh operator + * + * 0x01020304 vector polynomial multiplied with 0x04030201 results + * 0x000400060b060b04 + */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=3D#16909060 + r1=3D#67305985 + } + { + r1:0=3Dvpmpyh(r0, r1) + } + { + p0 =3D cmp.eq(r0, #184945412); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + p0 =3D cmp.eq(r1, #262150); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_vspliceb.S b/tests/tcg/hexagon/test_vsp= liceb.S new file mode 100644 index 0000000000..bae2a9c163 --- /dev/null +++ b/tests/tcg/hexagon/test_vspliceb.S @@ -0,0 +1,33 @@ +/* Purpose: test example, verify the soundness of the vspliceb operation + * the operation is a binary splice of two 64bit operators + * + * vspliceb(0xffffffffffffffff,0x0000000000000000,5) =3D 0x00000000000000= 1f + */ + .text + .globl _start + +_start: + { + call init + } + { + r0=3D#-1 + r1=3D#-1 + } + { + r2=3D#0 + r3=3D#0 + } + { + r5:4=3Dvspliceb(r1:0, r3:2, #5) + } + { + p0 =3D cmp.eq(r4, #-1); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + p0 =3D cmp.eq(r5, #255); if (p0.new) jump:t pass + jump fail + } --=20 2.30.0