From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613049940; cv=none; d=zohomail.com; s=zohoarc; b=ZTtzEpYxMWVsUnc5IFL8d/9YisJmz71TYUANlzX0m4BaaI0DdwQS0uOyyzGhJrH6z+uNkXV4DmjSdtgfId1wYRUnumuDLDoPlU5LHGzx54XzzrgEFBniRs5NhQxB3UkI1c80NausIO8zKDGHNLs24cwDF+dHmmiwdt9hAFOrlGg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613049940; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=55fSBVW6bM/EwxuFa4hfg9eqTtioyVGk4PvCa+Q/Udk=; b=KmHYYNw2bsLgLj01/XjbHTxa3UlPlNaGdr6ao/VrQGw6DWrfqk3DJL+P5R+5OtZOpRLwpklEXKY9tXw/nZvros2bEjv0nATjt02SHtv7vix1YJsaHRDIqlCZtwL7LCnxI6ontIftCgejSPRmsByBuy3FbyUpJM0RVrZPuLJNRz0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613049939896952.378495566573; Thu, 11 Feb 2021 05:25:39 -0800 (PST) Received: from localhost ([::1]:57160 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lABn5-0003IL-Ot for importer@patchew.org; Thu, 11 Feb 2021 08:13:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33142) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABYo-0007lh-8P for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:06 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:45613) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABYm-0008Jk-LK for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:05 -0500 Received: by mail-wr1-x429.google.com with SMTP id m13so4038379wro.12 for ; Thu, 11 Feb 2021 04:59:04 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=55fSBVW6bM/EwxuFa4hfg9eqTtioyVGk4PvCa+Q/Udk=; b=s2njYhYJA/yu5tJ+ZRCikl9HbZLFtQoBYRacBvfGQ430f++X4mtGVbHQUEVywJ0V6c 4INainZfIQ2LsRQp81DbJRYWPMJXlSImAwDAov6bZ50zQ9b1E4W6XxKnT823pfQ4ML8u aKF6dF1auyGQYTAEwzqnHCEqolVT6VxLzPR17LqqijJczYYvEs0LE18JO60oEdpiOUei 2iBgUqNsFFW1TYDIHaSctOjY2xHT1ZUrELqLVfjqOXDo9udEaQZZqpK3Ps7caTTTvf+t 4EblbAJqFO3mWQQ1PPV2S26bFNsVbZoKlAtCfTeSJw28edB9v+qLDhiiJPW9muSYWSKF eXJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=55fSBVW6bM/EwxuFa4hfg9eqTtioyVGk4PvCa+Q/Udk=; b=aAfNMb46idH5gLmeYznH/OCuy1yurMxjOCf7qkOjaTFIyGrBe6pICAnrmxTKP3mEWt EU5rGaFJi0hRtrPplKJ7nwqkemYe3wOeLQzPLlZiYrIbBeVorPAfpZDk4tfCYbWjXhz/ mUhN+WnQ745s3/HKnQK0Rf2iIb/kG6AwiI0gCzdMK/S8QWAnxMhFyfyOVltgbsxVTXY8 yq9d82Kodx1hc69R+NE1lshqnjgfUk7RbXKFjH/y8VJAP4wPLskYJlfQzm3iWhjgH96o NOirqratctq62PQ/riWfThaEXtV2gpW5QVCPVsAMxKMIRDPucp8336VgIn3NnJyTSRNz ytLw== X-Gm-Message-State: AOAM531PBxM0RHTqwhn3OZMg1Ja8MZD74cpuf+OIfB31rws+aQ0M86VU Fo1ms4u0eZRJc3XLm9K0VVO2/156A3YSDg== X-Google-Smtp-Source: ABdhPJzIkr34Dq5izHwcQwHH4Utl8gzLT5KO2yCDIGLEa2utq7wzMnHj2VF+e124/U/sugoWO0CVaQ== X-Received: by 2002:a5d:56c2:: with SMTP id m2mr689068wrw.325.1613048343414; Thu, 11 Feb 2021 04:59:03 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/45] target/arm: Don't migrate CPUARMState.features Date: Thu, 11 Feb 2021 12:58:16 +0000 Message-Id: <20210211125900.22777-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay As feature flags are added or removed, the meanings of bits in the `features` field can change between QEMU versions, causing migration failures. Additionally, migrating the field is not useful because it is a constant function of the CPU being used. Fixes: LP:1914696 Signed-off-by: Aaron Lindsay Suggested-by: Peter Maydell Reviewed-by: Andrew Jones Tested-by: Andrew Jones Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/machine.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/machine.c b/target/arm/machine.c index 581852bc53b..6ad1d306b12 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -810,7 +810,7 @@ const VMStateDescription vmstate_arm_cpu =3D { VMSTATE_UINT64(env.exclusive_addr, ARMCPU), VMSTATE_UINT64(env.exclusive_val, ARMCPU), VMSTATE_UINT64(env.exclusive_high, ARMCPU), - VMSTATE_UINT64(env.features, ARMCPU), + VMSTATE_UNUSED(sizeof(uint64_t)), VMSTATE_UINT32(env.exception.syndrome, ARMCPU), VMSTATE_UINT32(env.exception.fsr, ARMCPU), VMSTATE_UINT64(env.exception.vaddress, ARMCPU), --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613049765; cv=none; d=zohomail.com; s=zohoarc; b=WsBZuhWDGNr339RHtWiX85fskzFnRGhNozlP7lQOuUSKs7Tl21Wt4ZN5uIO9rUGtmBHGUK4d4uFukJqWDtr/sDGqjMw2D9HcRe5cZOlIM7SrgRX9zG1wNAR105pG4djKhJ47P4tjDKTpsE8HRthVC2dEutQiDi6jlSaN2EBzmM8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613049765; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JYi1J+pSxxdr5OmGrLhfG7W3WTtQ7/vYCTvWo3PWr+o=; b=JMWJgulIUXfdbzQcXKsI9oE+u40XpGJPRTRMbLnpH0MXx/3g+LBnl3iulv496Co2Ah6OvmZYGuEnc+rUmJDUva1msOLZSS0oybylxHbeEJzO9BS9mPNgP5roZzMYDJjKBgdaSupXWq3OXb44ZevQuIyBMPwyiQcKVebOnq9DBVA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161304976524263.40184870719486; Thu, 11 Feb 2021 05:22:45 -0800 (PST) Received: from localhost ([::1]:43766 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lABvg-0001LP-6K for importer@patchew.org; Thu, 11 Feb 2021 08:22:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33216) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABYr-0007r9-4x for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:09 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:41865) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABYn-0008K0-S9 for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:08 -0500 Received: by mail-wr1-x436.google.com with SMTP id n6so4072225wrv.8 for ; Thu, 11 Feb 2021 04:59:05 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=JYi1J+pSxxdr5OmGrLhfG7W3WTtQ7/vYCTvWo3PWr+o=; b=Vk9KFBVkX4AmLdPrKaVl5vCW9nBSuFu/NNe9Qk0t4Ctd7IN/uWRDVVE3vzXd0k9eYJ JcCWioUFJwrgfOLEmOGD1/3paxVZoJIs6u937lsujMRg5WIEhIGp8arQt3H34+8pT74K FXb8nXze/+bJSdnehrgus3nh6UDvXcxXio3fau/Tz55dbXThzgXzqiDPcmzBNcyauSVB 92UcNfEdTVbI85svwCPS2/3gMfDg0jwd6uKhFmzE9vfN8ooR6WZc+0DvM/zncqvCKace F8nuuKWEijkuJyHY+MzT4d1bokazhlHJ3wipuI3/r8f6en3wgWXZtLEfve65gub2FUQ+ bqAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JYi1J+pSxxdr5OmGrLhfG7W3WTtQ7/vYCTvWo3PWr+o=; b=m9ZiO7ojfeQXgU0Q+DKNnsteamRUOOHR4EPw+HNcrPjUFzYr4YutiRULxrvjrwpqZo MpfCkD58e3EaQDsqeDWwMPsQQbo3IYg1uJtdneDPwN771NzGlqI44V3okPd81LnsMNLp s8VaVQTpVoctBhFDAFRkjYz5k22UvWhmn/VRhvpDJga6OziU9bUaeJpp2MlqhQK8RrHO ZfbLLKcWGeuJjuqrHMUCtAnUPznA7M7xgO2bVxGTQhtCU47M1WeWE+qfmBx3YMROeLju aw4J3ck1Zen7LFZZ/N2Ry2HWcw1ulCTVrsK6KtHYNGSYqWLgjrsjgG1ew3MbDUilZeWg QfoA== X-Gm-Message-State: AOAM530y2qtE3XlMGEf5hqe4Fjxwz84tK33HBnCDg3O/zCLE2oIguZ5J NieMUwAQ3QjhCRMgD+5M5tWiPKYd5Q9VQg== X-Google-Smtp-Source: ABdhPJyst8yslT4QkvrkCEs9C513cguwxgsC8jMslUtpR+SncKsoW9IqEpaYSt/34gLG+c0jach6Bw== X-Received: by 2002:adf:8104:: with SMTP id 4mr5559344wrm.265.1613048344041; Thu, 11 Feb 2021 04:59:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/45] target/arm: Fix SCR RES1 handling Date: Thu, 11 Feb 2021 12:58:17 +0000 Message-Id: <20210211125900.22777-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Mike Nawrocki The FW and AW bits of SCR_EL3 are RES1 only in some contexts. Force them to 1 only when there is no support for AArch32 at EL1 or above. The reset value will be 0x30 only if the CPU is AArch64-only; if there is support for AArch32 at EL1 or above, it will be reset to 0. Also adds helper function isar_feature_aa64_aa32_el1 to check if AArch32 is supported at EL1 or above. Signed-off-by: Mike Nawrocki Reviewed-by: Richard Henderson Message-id: 20210203165552.16306-2-michael.nawrocki@gtri.gatech.edu Signed-off-by: Peter Maydell --- target/arm/cpu.h | 5 +++++ target/arm/helper.c | 16 ++++++++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d080239863c..39633f73f36 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4033,6 +4033,11 @@ static inline bool isar_feature_aa64_aa32(const ARMI= SARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >=3D 2; } =20 +static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2; +} + static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 1a64bd748ce..51330a0c489 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2024,7 +2024,10 @@ static void scr_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) ARMCPU *cpu =3D env_archcpu(env); =20 if (ri->state =3D=3D ARM_CP_STATE_AA64) { - value |=3D SCR_FW | SCR_AW; /* these two bits are RES1. */ + if (arm_feature(env, ARM_FEATURE_AARCH64) && + !cpu_isar_feature(aa64_aa32_el1, cpu)) { + value |=3D SCR_FW | SCR_AW; /* these two bits are RES1. = */ + } valid_mask &=3D ~SCR_NET; =20 if (cpu_isar_feature(aa64_lor, cpu)) { @@ -2063,6 +2066,15 @@ static void scr_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) raw_write(env, ri, value); } =20 +static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* + * scr_write will set the RES1 bits on an AArch64-only CPU. + * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise. + */ + scr_write(env, ri, 0); +} + static CPAccessResult access_aa64_tid2(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -5785,7 +5797,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { { .name =3D "SCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.scr_= el3), - .resetvalue =3D 0, .writefn =3D scr_write }, + .resetfn =3D scr_reset, .writefn =3D scr_write }, { .name =3D "SCR", .type =3D ARM_CP_ALIAS | ARM_CP_NEWEL, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613049913; cv=none; d=zohomail.com; s=zohoarc; b=cLrO4mrX0QTYi/tGHSUFFrCs7rzECt3mYiGAITDEZ4cXercwSc1HkbrLPKYCuU08LzelQKJYiRPv5CspWC0QV2xNOmcRu8dCQY7SLB0qQOBpa1ijMIC+nA+E3jUIQGgGFkKLyvxfEElx4oTiPoSub0fccUbxoiHpqhsPB5yxxAc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613049913; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gQrBoxbz171rw0tzOvaF5Z4ybjSP1s8QC0fPYVKKgNg=; b=A+C4YMgH1/FFjxuLC2bI2ivZ4viOHGk8wPtKd97T2JbigxDSEpBUCduIEZruJTIIVka7nu/eUHgSmqX77ELHB3yLE4U9BAxrvCQf4haozCN0utvLz1rkEGAyWw+aEtIOFbExmDlcYYgPPVzja0q6eo5WX+3ieZAsrVQuleHFspc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613049912942815.7698964380289; Thu, 11 Feb 2021 05:25:12 -0800 (PST) Received: from localhost ([::1]:52100 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lABy2-0004pA-9Q for importer@patchew.org; Thu, 11 Feb 2021 08:25:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33228) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABYr-0007rW-CE for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:09 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:34466) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABYn-0008Ky-Sd for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:09 -0500 Received: by mail-wr1-x436.google.com with SMTP id g10so4123384wrx.1 for ; Thu, 11 Feb 2021 04:59:05 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=gQrBoxbz171rw0tzOvaF5Z4ybjSP1s8QC0fPYVKKgNg=; b=rU/EndC9FYN5f/eKExsLm3FCagHo/hELLBoIrCV9RSRMpJBMMyqh9SmAbOztCwPrww 2A2UXZizCvpzAStDT77ZMm1yyfowrjws7ZlgDESlzoqFuIh8lW3knC+5HVpKwJPj/Lk8 ISPA5Rotjg3xHSoHm8IvMajMPAFT2eZaFunhMitpe4nLTWrGHSEIKyUgUJIZ3WQN8uJQ p72w9wiNJ9knfZG1+SW0NqGMPKbLKPh7mahSxS2YfdJF+kCaTUmfnxuf9v4zqc47YuUd B6nbfD4begwMmqo1hpWyC09glpmYoNTrwMFu3A4wasjtBPZ2y75/kFcYhNrEuBWdgXRn 7G0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gQrBoxbz171rw0tzOvaF5Z4ybjSP1s8QC0fPYVKKgNg=; b=rNcxsWpVcs0NISdgOuoqYwmRFBUy7KgnlV3J+tcD9fnDUvBm7iVFfGpurdTpYCyH5o 48mxv6s650g/wDE2A8ckn5/54xEJgprbbnN0nyeLg8und86mTs5W0dBoAuQP99E0DeM7 b22g24Ux1hvAcpSLWCikGYn9y1j0YU8f9GLj/FU+zn4KIemx2QAkJeCwabYsrTiR2Zam W4MoZzUo1Mu+Fx1pc2XrAcQKCbNeKoEur3lLH04HITK2eqr2qbGOMb3dyKoiTuvygRPg HcDAMoyBt6a/WmZ1bNeBq+sFdOPZt6K5SFtGO6zjZRtYiPadUq5oLEvb55BGDFGKtLzQ 7cxA== X-Gm-Message-State: AOAM530S9IyFpNktYw3nkW8y5h9tvRUSBFLaAEwOcMUFlenonmjZ4ieq 26wAZdbwvUTe4TSgje6oVNkfxdBOkdzp0w== X-Google-Smtp-Source: ABdhPJxCNMn63t4C5oYKmLtRlpt2AU4PdyMVscyiTzDItQlae+fh1CQs4YG0gwQthZQLiHDr3xyQUg== X-Received: by 2002:adf:fe46:: with SMTP id m6mr5692717wrs.92.1613048344675; Thu, 11 Feb 2021 04:59:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/45] hw/arm: Remove GPIO from unimplemented NPCM7XX Date: Thu, 11 Feb 2021 12:58:18 +0000 Message-Id: <20210211125900.22777-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Hao Wu NPCM7XX GPIO devices have been implemented in hw/gpio/npcm7xx-gpio.c. So we removed them from the unimplemented devices list. Reviewed-by: Doug Evans Reviewed-by: Tyrong Ting Signed-off-by: Hao Wu Message-id: 20210129005845.416272-2-wuhaotsh@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/npcm7xx.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 72040d40799..d1fe9bd1df6 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -576,14 +576,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **= errp) create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * = KiB); create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * = KiB); create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * = KiB); - create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * = KiB); - create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * = KiB); - create_unimplemented_device("npcm7xx.gpio[2]", 0xf0012000, 4 * = KiB); - create_unimplemented_device("npcm7xx.gpio[3]", 0xf0013000, 4 * = KiB); - create_unimplemented_device("npcm7xx.gpio[4]", 0xf0014000, 4 * = KiB); - create_unimplemented_device("npcm7xx.gpio[5]", 0xf0015000, 4 * = KiB); - create_unimplemented_device("npcm7xx.gpio[6]", 0xf0016000, 4 * = KiB); - create_unimplemented_device("npcm7xx.gpio[7]", 0xf0017000, 4 * = KiB); create_unimplemented_device("npcm7xx.smbus[0]", 0xf0080000, 4 * = KiB); create_unimplemented_device("npcm7xx.smbus[1]", 0xf0081000, 4 * = KiB); create_unimplemented_device("npcm7xx.smbus[2]", 0xf0082000, 4 * = KiB); --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613049905; cv=none; d=zohomail.com; s=zohoarc; b=N6cNzVrGL1UiOUqtcTLybXXKWPZRIX1+mJVKmpZLr1rELjTiSC2XGh99zHYzZeg9nDrLPq6C5Qiv4GibJSIwK711uUuM49ph6AQdEaKkpRJ2gCBLtY8JktF7/r+uGtNyo6F1CgkEb0luYNSKVQO6WBeaL9sRfGlF+6YpOU1/Ccw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613049905; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rMwGAAPGdMhnkTOfB0jTA8QMpl2mDEy1rD2Rrr1X41c=; b=FiAptDbLpjpT8yyX6qJFPX0zjJxIFp21PqeEH6UTGr4pUv9iTkbURvwPRyLd++LKYP9VTQcxlRN2a5XrfTAk8hclUXfgaezN7rHZlVnl+BOXI7e3zLiGpRSBiueU5DBaFirYMXrccCo7+YCW/gq2oCegROQtJoxcDbl3EDpZqII= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613049904340699.3094240670301; Thu, 11 Feb 2021 05:25:04 -0800 (PST) Received: from localhost ([::1]:50428 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lABjr-0000PH-0q for importer@patchew.org; Thu, 11 Feb 2021 08:10:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33194) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABYq-0007pm-Ie for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:08 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:38396) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABYo-0008LT-Ln for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:08 -0500 Received: by mail-wr1-x434.google.com with SMTP id b3so4092995wrj.5 for ; Thu, 11 Feb 2021 04:59:06 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rMwGAAPGdMhnkTOfB0jTA8QMpl2mDEy1rD2Rrr1X41c=; b=jnZtt2X+jK5oITVm5DvbIqfD4/HJyaObl0gmjDuWfsq4HD+uo449DrCKjDFNDSXudW TkEi8psvp6V9s+n9jYiSJ27hNSJeN2yk0dS5YKiPvQ9QfkVMcGxrBZ7uOnYxxhZXNBoz 6xiKCwS234CMYXtOmLwEjLHeSVNtQ43h78zaQIhacgLNLBaz09Iz89mab6OuDP8lHcz8 8K83RJ3qtVuNcvzZmx+DZqbeuampDFXF/U4ojkNHJu5VNLCSfKw4FvsFMjZZWuijmVtn wc3xrA9QZ34kq3YysiX3dN806pvZ0b2L0aJYf6Jh9ym6p33+qRHXVafDFTVZzDA88HVK la1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rMwGAAPGdMhnkTOfB0jTA8QMpl2mDEy1rD2Rrr1X41c=; b=EY10VVDpQUDQrRsOFjbnj3O6lnLoZyJqy7F7QM/PaFOZ8UIhmZDtwSk3pKK/PmiieH pXDtE5xHQDGeoLIFhDK+dNkQTP6hiXvCUywX/i1rvgUjTLsgNgU83eolGE6za7YyMesc chSoSkit/rAapcXiPBTjBdBWMQxriP2hgJxt3YCKl5XfUKz4Jp38Bli72cO09XWASNxE UcIJ80a4ePoqU43YieS8sg7NhoZPiQ4Q/dIgaEIQsyu7QLIh/GMh7zmNbPlmlJQny6e1 K4zu/92iTqhIitEZX+a1NNXojSOuY5m3Nhn9T4Q+iBRLgHmkbglsaZk0rtIJB+gDkd+O 1jVg== X-Gm-Message-State: AOAM533ftJooWwN/FY11XhWV3+qoLMDwRVQ51G4RW19yHix/ja1iEfsR e5FXjZHOUirKoJiC25AS5UqGV+PPUXcOAw== X-Google-Smtp-Source: ABdhPJzThVZUNmUnVenc2kNQwzCpfUFNHnJ97ejA9dymcyYxxVTaEF4/l9lnCbEKXdMuhYo/queuXg== X-Received: by 2002:a05:6000:2aa:: with SMTP id l10mr5617608wry.368.1613048345426; Thu, 11 Feb 2021 04:59:05 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/45] target/arm: Add support for FEAT_DIT, Data Independent Timing Date: Thu, 11 Feb 2021 12:58:19 +0000 Message-Id: <20210211125900.22777-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Rebecca Cran Add support for FEAT_DIT. DIT (Data Independent Timing) is a required feature for ARMv8.4. Since virtual machine execution is largely nondeterministic and TCG is outside of the security domain, it's implemented as a NOP. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson Message-id: 20210208065700.19454-2-rebecca@nuviainc.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 12 ++++++++++++ target/arm/internals.h | 6 ++++++ target/arm/helper.c | 22 ++++++++++++++++++++++ target/arm/translate-a64.c | 12 ++++++++++++ 4 files changed, 52 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 39633f73f36..f240275407b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1243,6 +1243,7 @@ void pmu_init(ARMCPU *cpu); #define CPSR_IT_2_7 (0xfc00U) #define CPSR_GE (0xfU << 16) #define CPSR_IL (1U << 20) +#define CPSR_DIT (1U << 21) #define CPSR_PAN (1U << 22) #define CPSR_J (1U << 24) #define CPSR_IT_0_1 (3U << 25) @@ -1310,6 +1311,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_SS (1U << 21) #define PSTATE_PAN (1U << 22) #define PSTATE_UAO (1U << 23) +#define PSTATE_DIT (1U << 24) #define PSTATE_TCO (1U << 25) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) @@ -3876,6 +3878,11 @@ static inline bool isar_feature_aa32_tts2uxn(const A= RMISARegisters *id) return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) !=3D 0; } =20 +static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) !=3D 0; +} + /* * 64-bit feature tests via id registers. */ @@ -4125,6 +4132,11 @@ static inline bool isar_feature_aa64_tts2uxn(const A= RMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) !=3D 0; } =20 +static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) !=3D 0; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 448982dd2f9..b251fe44506 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1228,6 +1228,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64= _t features, if (isar_feature_aa32_pan(id)) { valid |=3D CPSR_PAN; } + if (isar_feature_aa32_dit(id)) { + valid |=3D CPSR_DIT; + } =20 return valid; } @@ -1246,6 +1249,9 @@ static inline uint32_t aarch64_pstate_valid_mask(cons= t ARMISARegisters *id) if (isar_feature_aa64_uao(id)) { valid |=3D PSTATE_UAO; } + if (isar_feature_aa64_dit(id)) { + valid |=3D PSTATE_DIT; + } if (isar_feature_aa64_mte(id)) { valid |=3D PSTATE_TCO; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 51330a0c489..cf8e80419da 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4431,6 +4431,24 @@ static const ARMCPRegInfo uao_reginfo =3D { .readfn =3D aa64_uao_read, .writefn =3D aa64_uao_write }; =20 +static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_DIT; +} + +static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate =3D (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT); +} + +static const ARMCPRegInfo dit_reginfo =3D { + .name =3D "DIT", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 5, + .type =3D ARM_CP_NO_RAW, .access =3D PL0_RW, + .readfn =3D aa64_dit_read, .writefn =3D aa64_dit_write +}; + static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -8224,6 +8242,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &uao_reginfo); } =20 + if (cpu_isar_feature(aa64_dit, cpu)) { + define_one_arm_cp_reg(cpu, &dit_reginfo); + } + if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { define_arm_cp_regs(cpu, vhe_reginfo); } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ffc060e5d70..1c4b8d02f3b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1700,6 +1700,18 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, tcg_temp_free_i32(t1); break; =20 + case 0x1a: /* DIT */ + if (!dc_isar_feature(aa64_dit, s)) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_DIT); + } else { + clear_pstate_bits(PSTATE_DIT); + } + /* There's no need to rebuild hflags because DIT is a nop */ + break; + case 0x1e: /* DAIFSet */ t1 =3D tcg_const_i32(crm); gen_helper_msr_i_daifset(cpu_env, t1); --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=eUbSMazfyfMsBMjES0tnhx8PHPELPJGOsUzJPWKDUhc=; b=G7Yu9PDtCtU0HiaHnuSTqPv6Y7i1UYGpfAvy1klT0qeMBkvzhI0UVRcSRP2CikvB3O zhfhUv/SHVWC3Ug1v2Q+MTqrjl5VC2mFX4tFT6v2+AoiZBj80qUfyXewxf2T4rRLOPAu MP7GslXKncUEQ2PJLze1t2romx/3Fq/A7PzeACfLveyiq10lGUechey/9ddJ2T7A+tjh 0uxvhGOvroK/cYwRrXt+F+JHaWh6+UnC/Mh4FNOoocS3j4+pKjuVshrjQythgJPmdfkF pVNdbuY7eunW73eJV208+O8MgnPO/tGHzHvDPaK4Y6zrj+hnCNGFQLZHT7ezQU+PI8ji momw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eUbSMazfyfMsBMjES0tnhx8PHPELPJGOsUzJPWKDUhc=; b=faGHPgapi8A0cd06PAKKag1ZOihlPLbDJJ7g/x1TOJDnR0LUhd2Hc15xmWwAwj86YQ y/zR3qiJo/1Ix5WP6CjfBDfXXMxNy6Vw9DnZA8+1tjsGcHj8j/PrtJKGYrRnaKAAO4y3 rGNUYCFHJwLl+U0wttDV76U3EkYKSo7Dv00sJu8VjI5GPl+xI6jfjBlGGPcrWy7COwiH yBVnnywezYOPHIglB3+Z6X0C5tQa4UJ99L/WNEnMLP24cd9q+dt9vhdcZHliSDT82gB9 E6gPwamVY8TYj0+dZJBGPmPAYvmJ5sulbmoNksvVCtchAi0W1nkhHGPebWhLX9qmCdg7 0nQQ== X-Gm-Message-State: AOAM530yGmdZKeNS7kYzYUeUdd2LHtYNFXPTp+G2GUcAUaoaS/77XnuC F1Ig6byHnDpwnfCPX2dS7qt8AKUzyHYZEA== X-Google-Smtp-Source: ABdhPJz26srC/HdltingZmthvnJdaAvfKeDP/b4fddLjG3kCLI8vmxMUSFg/T54tlwt5N2B6zN81Lg== X-Received: by 2002:a5d:4a0b:: with SMTP id m11mr5770300wrq.51.1613048346340; Thu, 11 Feb 2021 04:59:06 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/45] target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate Date: Thu, 11 Feb 2021 12:58:20 +0000 Message-Id: <20210211125900.22777-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Rebecca Cran cpsr has been treated as being the same as spsr, but it isn't. Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate. This allows us to add support for CPSR_DIT, adding helper functions to merge SPSR_ELx to and from CPSR. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson Message-id: 20210208065700.19454-3-rebecca@nuviainc.com Signed-off-by: Peter Maydell --- target/arm/helper-a64.c | 27 +++++++++++++++++++++++---- target/arm/helper.c | 24 ++++++++++++++++++------ target/arm/op_helper.c | 9 +-------- 3 files changed, 42 insertions(+), 18 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index c426c23d2c4..ae611d73c2c 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -945,11 +945,31 @@ static int el_from_spsr(uint32_t spsr) } } =20 +static void cpsr_write_from_spsr_elx(CPUARMState *env, + uint32_t val) +{ + uint32_t mask; + + /* Save SPSR_ELx.SS into PSTATE. */ + env->pstate =3D (env->pstate & ~PSTATE_SS) | (val & PSTATE_SS); + val &=3D ~PSTATE_SS; + + /* Move DIT to the correct location for CPSR */ + if (val & PSTATE_DIT) { + val &=3D ~PSTATE_DIT; + val |=3D CPSR_DIT; + } + + mask =3D aarch32_cpsr_valid_mask(env->features, \ + &env_archcpu(env)->isar); + cpsr_write(env, val, mask, CPSRWriteRaw); +} + void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) { int cur_el =3D arm_current_el(env); unsigned int spsr_idx =3D aarch64_banked_spsr_index(cur_el); - uint32_t mask, spsr =3D env->banked_spsr[spsr_idx]; + uint32_t spsr =3D env->banked_spsr[spsr_idx]; int new_el; bool return_to_aa64 =3D (spsr & PSTATE_nRW) =3D=3D 0; =20 @@ -998,10 +1018,9 @@ void HELPER(exception_return)(CPUARMState *env, uint6= 4_t new_pc) * will sort the register banks out for us, and we've already * caught all the bad-mode cases in el_from_spsr(). */ - mask =3D aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)-= >isar); - cpsr_write(env, spsr, mask, CPSRWriteRaw); + cpsr_write_from_spsr_elx(env, spsr); if (!arm_singlestep_active(env)) { - env->uncached_cpsr &=3D ~PSTATE_SS; + env->pstate &=3D ~PSTATE_SS; } aarch64_sync_64_to_32(env); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index cf8e80419da..2c27077fb2d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9445,7 +9445,7 @@ static void take_aarch32_exception(CPUARMState *env, = int new_mode, * For exceptions taken to AArch32 we must clear the SS bit in both * PSTATE and in the old-state value we save to SPSR_, so zero i= t now. */ - env->uncached_cpsr &=3D ~PSTATE_SS; + env->pstate &=3D ~PSTATE_SS; env->spsr =3D cpsr_read(env); /* Clear IT bits. */ env->condexec_bits =3D 0; @@ -9801,6 +9801,21 @@ static int aarch64_regnum(CPUARMState *env, int aarc= h32_reg) } } =20 +static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env) +{ + uint32_t ret =3D cpsr_read(env); + + /* Move DIT to the correct location for SPSR_ELx */ + if (ret & CPSR_DIT) { + ret &=3D ~CPSR_DIT; + ret |=3D PSTATE_DIT; + } + /* Merge PSTATE.SS into SPSR_ELx */ + ret |=3D env->pstate & PSTATE_SS; + + return ret; +} + /* Handle exception entry to a target EL which is using AArch64 */ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) { @@ -9923,7 +9938,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) aarch64_save_sp(env, arm_current_el(env)); env->elr_el[new_el] =3D env->pc; } else { - old_mode =3D cpsr_read(env); + old_mode =3D cpsr_read_for_spsr_elx(env); env->elr_el[new_el] =3D env->regs[15]; =20 aarch64_sync_32_to_64(env); @@ -13217,7 +13232,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, target_ulong *cs_base, uint32_t *pflags) { uint32_t flags =3D env->hflags; - uint32_t pstate_for_ss; =20 *cs_base =3D 0; assert_hflags_rebuild_correctly(env); @@ -13227,7 +13241,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags =3D FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } - pstate_for_ss =3D env->pstate; } else { *pc =3D env->regs[15]; =20 @@ -13275,7 +13288,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, =20 flags =3D FIELD_DP32(flags, TBFLAG_AM32, THUMB, env->thumb); flags =3D FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_b= its); - pstate_for_ss =3D env->uncached_cpsr; } =20 /* @@ -13288,7 +13300,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. */ if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) && - (pstate_for_ss & PSTATE_SS)) { + (env->pstate & PSTATE_SS)) { flags =3D FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); } =20 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 5e0f123043b..65cb37d088f 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -389,14 +389,7 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uin= t32_t syndrome) =20 uint32_t HELPER(cpsr_read)(CPUARMState *env) { - /* - * We store the ARMv8 PSTATE.SS bit in env->uncached_cpsr. - * This is convenient for populating SPSR_ELx, but must be - * hidden from aarch32 mode, where it is not visible. - * - * TODO: ARMv8.4-DIT -- need to move SS somewhere else. - */ - return cpsr_read(env) & ~(CPSR_EXEC | PSTATE_SS); + return cpsr_read(env) & ~CPSR_EXEC; } =20 void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613049477; cv=none; d=zohomail.com; s=zohoarc; b=AmAiXPIt/25EEIj16T1r5vwlKRBCjR19sSXBgCRoqyQHOXP+H53bOrN2KJ/wydwLx+5vu/IVJD5yChCsJQM76IaQIv8eTd8LZ3Svb3KJgYuGEHDuS8d9t2/MM+mrI3s8zJmo448414VtIOv3NPsEDvk80E45udFdeDbzjXgpmoo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613049477; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3wSv6Cbip4MMdQNJC+tS9CGgkSpKZaUik6k+8A1am0s=; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=3wSv6Cbip4MMdQNJC+tS9CGgkSpKZaUik6k+8A1am0s=; b=Y9qsTguq/OTzLz9e84kMScXSq7m2elCEGz3NjNnX1pyMH86+mrMKJdtj0VtlZ+YAt0 9cXpUx76eEqKTOXzQBb0xNpzAxza5bRAIuaDXISmYFy3sac2X2z8gTuudJp+WpJx/PiF eIMLIRv1VYzAq+PJs8f1GqRZYdCx6VkTJW1U4lxAL9f1g6+Q8TCCtVzRjkAQip8cc08H RqPEOyO/5nzo7mQ3sJSzG2Qwqgq7NyIPCpQ2StpfFRqmRL0agezV0uje7lVzQK3hQhTW XBQ0Ps7fPUWi07H4x0fDuDtmviVKvCWMqmhhYdlCDwZPdUE7Eh7QBmqITw4YGBN0Y6hG 8hvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3wSv6Cbip4MMdQNJC+tS9CGgkSpKZaUik6k+8A1am0s=; b=tsRdrHtmtEkIpzkYSYJRhWFQu0ptBMiKqr41trJQeyhNj0G1kekHZx6Echn5jNCvCs 9DnqqA9CAbdJPRs6f7MTJdwX0h44rSY722An9eDJYtAq1JGw2/Un8aA6MXGk3NKqb1gx MV/rgNBO/2Xu1BguBaVNpGJv57EkNYtMpWaVxjtFNwqR/U3TOcgqX+LOyPbnHhdZ4Nd+ NX+z+OvQHWRVUGdj6zntUHcTzqAtTxqeAvl2w9MVIxRpvC6mH/jc86pS3DzgLkx9Y5Jo jPXTj/sjFnqjTxsT4N89DgrbdhWI0CPMyFWvy4Q6oSrdrwDgkH0IXTEotdmzrtqiR0Sw CYLw== X-Gm-Message-State: AOAM531VORnD9CVXxN/sFVtYTivsUESrxQoJlmZjBGIz+sdMeP6UOycv H1NG71CzCR1GimnGSCEL0oAsEikCluVByA== X-Google-Smtp-Source: ABdhPJwRQaWUS0mcUXHQVgwrBDi0qv0ACmhrtgUBVqTTYu0JI1iL08g5z21l45PUop0WGavFygiP7A== X-Received: by 2002:a05:6000:18a3:: with SMTP id b3mr5621838wri.373.1613048347170; Thu, 11 Feb 2021 04:59:07 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/45] target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU Date: Thu, 11 Feb 2021 12:58:21 +0000 Message-Id: <20210211125900.22777-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Rebecca Cran Enable FEAT_DIT for the "max" AARCH64 CPU. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson Message-id: 20210208065700.19454-4-rebecca@nuviainc.com Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 10c51181767..c255f1bcc39 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -669,6 +669,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; @@ -718,6 +719,10 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 =3D u; =20 + u =3D cpu->isar.id_pfr0; + u =3D FIELD_DP32(u, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D u; + u =3D cpu->isar.id_mmfr3; u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ cpu->isar.id_mmfr3 =3D u; --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613049757; cv=none; d=zohomail.com; s=zohoarc; b=AmdSwPEDjdhH+2nJJOH2T6dbmblSFneK74wehI3GOg6vxyCHoQ2+GR5HCEshxxyQspqOmDBYjWkMYWOwMru0ndR4I1d0bmQbd+e6CGudi+yU7WtFQeICjohnod5xGO10iFoBCBvh5Yx908hGUTzbKuJYeIBGraw0cK6rHlVGqjQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613049757; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WshNHyd6X+FZoKhq1yVntiLeg2lGOxs8cfnC0ZZ7SBI=; b=BWWE7CZeELGRkaeNKmwstD9/jATrtu+LZHeesRl4khUqgmK9zsk40IZ9YORiizfe4/Rol/wZoffcC/J8oH+Ff9lG/Z1zrpfSoDgsaFb3PYnoGVX5SN9dcx91XFf1KoIAbVWEQ9t6Ms4sCHok1dtlHRXX6UlICWwMjHKYcJLAqvU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613049757143858.2010567906218; Thu, 11 Feb 2021 05:22:37 -0800 (PST) Received: from localhost ([::1]:43436 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lABvY-0001CF-1w for importer@patchew.org; Thu, 11 Feb 2021 08:22:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33248) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABYs-0007u4-P6 for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:10 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:39658) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABYr-0008NO-CD for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:10 -0500 Received: by mail-wr1-x433.google.com with SMTP id v1so495821wrd.6 for ; Thu, 11 Feb 2021 04:59:08 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=WshNHyd6X+FZoKhq1yVntiLeg2lGOxs8cfnC0ZZ7SBI=; b=Rq3w4uHMalxPcDxkh6zdl8wIdAbYyCKaa+wfD0qc15EWcHd2xdmXMe3E7MF70Ze/7D SS6u+6/1ZGPqd1/Qn+bDFbwPgMtkGdwI8qIqo61WFM7G02TBfYEAjVGUrFhh2L9Gj8Yn 4D/Nq0DBok99gpOfbr4lAHJkwI2N7vrmk5xlLrBmQ8et1jU4Q0Y/cnDcNNmZpmZ0Dt0y SI5131Q48ymp+3KGwxavuq59S6NKBxXWki3Fupb4TzVwvlJLmlshEiluVfkbYLHDpx6w SY9gGFyrUwu+OVtiNe/2W3awzZmvuaDH1ALRl0bXDTobwq1ZuHXdq8fcwDbJNui7g1wL bU3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WshNHyd6X+FZoKhq1yVntiLeg2lGOxs8cfnC0ZZ7SBI=; b=B+udZsZFxka/J669wJROXs7GA9tzVJmlfZ+LP1C/4rQjQvEm58j1UUllf2gEsVnE05 x1tai6sYVIGFZg4Mnm0N8k8JP8oSBwWfSuAua5MbyrGR8AxZbk3RZoq6GWCY0+yQaPfw lFtYxqmDjvv7wJ90hUkmMais1vfg9Gxh9bE++zICCOfz+3q5fhBld3iXM1BMM0AORbID C9SbwxNpczIJdvvwStqWAaxOd8AbKDHdPvGFRhV/dpVMG4l3HiNVTMqG+ES+i8zWoAer qtRhy/3ZdtFNrS1PJm4EAeToo5EEhh0olRlKdf/XFv/pB29R7VSwGw1zumlQMGeFdDx1 s5DQ== X-Gm-Message-State: AOAM530fMxF5MUkMBA1R+ACrXbGZAwBNGCyv6HOTZgMksK/Jlr7M8i5Y hyKO/ujQyojivnffV7vX+7SND+C4f82hYg== X-Google-Smtp-Source: ABdhPJx/x2Kl0ifr0W2nwlhA728APngnSm73KKktfz4nOBWXIcUdWwIwx3vyKF9V+tQRilx9se7eZw== X-Received: by 2002:a05:6000:1362:: with SMTP id q2mr5581707wrz.31.1613048348130; Thu, 11 Feb 2021 04:59:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/45] target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU Date: Thu, 11 Feb 2021 12:58:22 +0000 Message-Id: <20210211125900.22777-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Rebecca Cran Enable FEAT_DIT for the "max" 32-bit CPU. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson Message-id: 20210208065700.19454-5-rebecca@nuviainc.com Signed-off-by: Peter Maydell --- target/arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8ddb2556f8c..5cf6c056c50 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2202,6 +2202,10 @@ static void arm_max_initfn(Object *obj) t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ cpu->isar.id_mmfr4 =3D t; + + t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D t; } #endif } --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613048540; cv=none; d=zohomail.com; s=zohoarc; b=Fd9w8htEFTGP4BJXa0f97OD1ec97+jNYA3BVwkUeZ9ddnlXChGUDshRzNQIkM0kjt+UAjqhMBLL7FiY/tDwpyh46JmBgaj4D9rlWdnaNrgiFfv/mrADhQpTAKgu6Efasjw/vqgugl/U17WOFdxxKU47r7vsPAaEskT6ghL7mlFY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613048540; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=z8oR6cjhvDNb7fmg2sC9i29QfpU4+AsUPB9KwGEI9Q0=; b=j3EQIUc9+jeWZ61HGu+XDzP/ydqg0okWCs3lWkWbDLao1ceo/jhwuaY7wku/obiAHwLIlcHMrMzPAPkingNZrpny/nRgQtFvmcr4QGJHU2KQqr4mUf/0yjwVPL7oyWyuyd1lWLQD2kaUcQRFNdXvQYIuOoQveFnlzc4LYRaFIHQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613048540473159.78767470986782; Thu, 11 Feb 2021 05:02:20 -0800 (PST) Received: from localhost ([::1]:36630 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lABbu-0001kj-K6 for importer@patchew.org; Thu, 11 Feb 2021 08:02:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33288) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABYu-0007xU-HZ for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:12 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:36244) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABYs-0008Nl-HJ for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:12 -0500 Received: by mail-wm1-x32b.google.com with SMTP id i9so5656739wmq.1 for ; Thu, 11 Feb 2021 04:59:10 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=z8oR6cjhvDNb7fmg2sC9i29QfpU4+AsUPB9KwGEI9Q0=; b=b7zkPbj5BU+kJeBFrE6YLlanpx3LqQ2FqwK6CwQZVXrul3hpEw9GXtGjpsnWSXPgIR 6kEbPQ9yINGL+BosAYurmEvzy98Hv09Lb9p4jXOnZrINnHTNsKHUGbtr9N3sZllpWxyl Piy5w3QcZPSCCUvbF6KOW+u8L9TAMScyIcNszGpGmm8tpC5i+qKJ5anlWaFCWoDMcv31 aYl4WiqHX1Cw0/dF/A3iHSu0NsjKlYm17Qni7qbmT5XIDjGdvv32qggYlikAcqNUDdEs f0hlp0fgzURxVT8oskmsItySrZDI/uA32mQhlnPEJ2o2atKm1VX03pyH4KTYHfYBLT4t WOlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z8oR6cjhvDNb7fmg2sC9i29QfpU4+AsUPB9KwGEI9Q0=; b=etzz5NKsmSV8t4nnrZmTuEQoZHlrcHHsnO4+IznrqKyaRQ9/9pIMm2uxIksNHkVS/a FE//WhEVsyB2GlY6bSzii8E49Jaz+etayKdLdTlN4IxycFv8670IqdrWqKka+jvUaJkW v93GnKHujhwpv+mA5mr1XGs+4yTIhmKZVwzb26kK4l5c6nppHOQLne0Q3Dysdqt5Touw ZAfxgSqHU39yEtYCsVqP40GDpVvp+QsD+UxORb7Zd7WjLtzqh9Pp9okr8bmmQRU/5Ske H/5oUTTBJhniKg6ZFiKfE++zZWuRnBo09ImGhEuz3Ah6mB77cYJWeGg+fo/58O8vDXa9 TN6A== X-Gm-Message-State: AOAM5333VLic0PRLl+YcIfWcmFC932gAQBlc6oUD2AcHVzZrUjzbjvAP tFBXojlEzcGvl3fXkc7h+I2J9gBidBeVRA== X-Google-Smtp-Source: ABdhPJwbhc/jN0NbzeRhJnJXPs/782/XC+/B0OQOLpgj7fRSnR3NGoO8OgBtrzzAkjLVHDMPMHN31g== X-Received: by 2002:a7b:c04c:: with SMTP id u12mr5132083wmc.185.1613048349152; Thu, 11 Feb 2021 04:59:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/45] arm: Update infocenter.arm.com URLs Date: Thu, 11 Feb 2021 12:58:23 +0000 Message-Id: <20210211125900.22777-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Update infocenter.arm.com URLs for various pieces of Arm documentation to the new developer.arm.com equivalents. (There is a redirection in place from the old URLs, but we might as well update our comments in case the redirect ever disappears in future.) This patch covers all the URLs which are not MPS2/SSE-200/IoTKit related (those are dealt with in a different patch). Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210205171456.19939-1-peter.maydell@linaro.org --- include/hw/dma/pl080.h | 7 ++++--- include/hw/misc/arm_integrator_debug.h | 2 +- include/hw/ssi/pl022.h | 5 +++-- hw/arm/aspeed_ast2600.c | 2 +- hw/arm/musca.c | 4 ++-- hw/misc/arm_integrator_debug.c | 2 +- hw/timer/arm_timer.c | 7 ++++--- 7 files changed, 16 insertions(+), 13 deletions(-) diff --git a/include/hw/dma/pl080.h b/include/hw/dma/pl080.h index 1883f042701..3c9659e4381 100644 --- a/include/hw/dma/pl080.h +++ b/include/hw/dma/pl080.h @@ -10,11 +10,12 @@ * (at your option) any later version. */ =20 -/* This is a model of the Arm PrimeCell PL080/PL081 DMA controller: +/* + * This is a model of the Arm PrimeCell PL080/PL081 DMA controller: * The PL080 TRM is: - * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0196g/DDI0196.pdf + * https://developer.arm.com/documentation/ddi0196/latest * and the PL081 TRM is: - * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0218e/DDI0218.pdf + * https://developer.arm.com/documentation/ddi0218/latest * * QEMU interface: * + sysbus IRQ 0: DMACINTR combined interrupt line diff --git a/include/hw/misc/arm_integrator_debug.h b/include/hw/misc/arm_i= ntegrator_debug.h index 0077dacb44d..798b0821646 100644 --- a/include/hw/misc/arm_integrator_debug.h +++ b/include/hw/misc/arm_integrator_debug.h @@ -3,7 +3,7 @@ * * Browse the data sheet: * - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.dui015= 9b/Babbfijf.html + * https://developer.arm.com/documentation/dui0159/b/peripherals-and-inte= rfaces/debug-leds-and-dip-switch-interface * * Copyright (c) 2013 Alex Benn=C3=A9e * diff --git a/include/hw/ssi/pl022.h b/include/hw/ssi/pl022.h index 545b52689c1..25d58db5f32 100644 --- a/include/hw/ssi/pl022.h +++ b/include/hw/ssi/pl022.h @@ -9,9 +9,10 @@ * (at your option) any later version. */ =20 -/* This is a model of the Arm PrimeCell PL022 synchronous serial port. +/* + * This is a model of the Arm PrimeCell PL022 synchronous serial port. * The PL022 TRM is: - * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0194h/DDI0194H_ssp_= pl022_trm.pdf + * https://developer.arm.com/documentation/ddi0194/latest * * QEMU interface: * + sysbus IRQ: SSPINTR combined interrupt line diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 12e4a16d376..bf31ca351fe 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -216,7 +216,7 @@ static void aspeed_soc_ast2600_init(Object *obj) /* * ASPEED ast2600 has 0xf as cluster ID * - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ddi0388e/= CIHEBGFG.html + * https://developer.arm.com/documentation/ddi0388/e/the-system-control-co= processors/summary-of-system-control-coprocessor-registers/multiprocessor-a= ffinity-register */ static uint64_t aspeed_calc_affinity(int cpu) { diff --git a/hw/arm/musca.c b/hw/arm/musca.c index 945643c3cd7..7a83f7dda7d 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -15,8 +15,8 @@ * https://developer.arm.com/products/system-design/development-boards/iot= -test-chips-and-boards/musca-a-test-chip-board * https://developer.arm.com/products/system-design/development-boards/iot= -test-chips-and-boards/musca-b-test-chip-board * We model the A and B1 variants of this board, as described in the TRMs: - * http://infocenter.arm.com/help/topic/com.arm.doc.101107_0000_00_en/inde= x.html - * http://infocenter.arm.com/help/topic/com.arm.doc.101312_0000_00_en/inde= x.html + * https://developer.arm.com/documentation/101107/latest/ + * https://developer.arm.com/documentation/101312/latest/ */ =20 #include "qemu/osdep.h" diff --git a/hw/misc/arm_integrator_debug.c b/hw/misc/arm_integrator_debug.c index ec0d4b90d3d..9a197278290 100644 --- a/hw/misc/arm_integrator_debug.c +++ b/hw/misc/arm_integrator_debug.c @@ -6,7 +6,7 @@ * to this area. * * The real h/w is described at: - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.dui0159b= /Babbfijf.html + * https://developer.arm.com/documentation/dui0159/b/peripherals-and-inte= rfaces/debug-leds-and-dip-switch-interface * * Copyright (c) 2013 Alex Benn=C3=A9e * diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 98e70b2d262..15caff0e41c 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -185,10 +185,11 @@ static arm_timer_state *arm_timer_init(uint32_t freq) return s; } =20 -/* ARM PrimeCell SP804 dual timer module. +/* + * ARM PrimeCell SP804 dual timer module. * Docs at - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ddi0271d/= index.html -*/ + * https://developer.arm.com/documentation/ddi0271/latest/ + */ =20 #define TYPE_SP804 "sp804" OBJECT_DECLARE_SIMPLE_TYPE(SP804State, SP804) --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050154; cv=none; d=zohomail.com; s=zohoarc; b=RVqDjTaVDr/hnIT5VUtVxHN+UUs1bcJqJYgSXaVc1zqf3111eMKQraDXiAcFRts6Edzj+76lmMfyLE3vCioCQxz+1Xw4PdCn6W/Br9d/GR9K/qFhJOUHZ11RVzcCfvlVJabpFZmfZaw394MmhVMir5QU1n3rZTd1tu0ZrziOSW8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PtDeqeyUBjOCMcS5vyrE3R/MbPIwJDRp4dT9irDCFLM=; b=EeGDLSAzF//2ZQ4oPh6L0wA5onvEzim4h76ICULhGQ2cM8L+5/D7Itc6e/sDWgU/2e SLQdMVHJKU9MGUZ8PiUx1onDgssebtenAtcJXTBYA5GtyhbVAGQ84vZ5oGcTPYhcIS2W tImm+fTMWekzaDqXQ6OQaZQzTViNFBzd6kHmLA/Uo8rVYsBBUDS/2mEQzqA3VdlUp+6U hr/J1K9urVYPGotc4DT2lci68YAYx+pnw0TRUXWak6811rImvAqF98f9HTj4ibDQT0DZ pUBatMXRxGR8UJtY5AmtHkUxPa7aD44KnwPNBsmgRWlrHTdGdSudR1GREfXYiCIjZb5k tt2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PtDeqeyUBjOCMcS5vyrE3R/MbPIwJDRp4dT9irDCFLM=; b=gIAJ3WlOfmTX8+htL8Gm2/DEo8an+1L+MkrEmAnhBpsGP5cbplAbCQdzUow607f2uN LhXzSKIdaR9JLrsS11Wcf9hOcFFvrfOMXOPtshe98iYAlwcEWc4Y2ZOQeqsU0lEPkrCv 1xycvzbiAp2SvvnL2mZ1ScUGo4TFGVaoq4SjaTdmOc9C8G90yEs48rZ1TPR6fP0wx0SV yu5HzKvNpbHRwQUr4xW51yIeuky8qNOJx4QNLzDM9w1vLi30OJYtk0b2FVpaKH7Y50St HYUh2mWxKSdiYup1ijV77uBv+9zwsSr2EreITeGOxqwHgVG4vTrSBKf08mFM9gMiYkRt zpYA== X-Gm-Message-State: AOAM53198f9hMLvPKzPr5BztGUrKzqUTmjgxNFFwk2o1FxKhFbxRarhn r0rfDXSWQ7m6yxzhdIUHo9Cb8hBWLIYn6A== X-Google-Smtp-Source: ABdhPJzRbWuZ6dqyY5QYydHfZrmGx3uHMitsLysXliVEfuQwSyH5V5vwA1SzIQakgd5QnNoAeKXF/g== X-Received: by 2002:a5d:56c2:: with SMTP id m2mr689461wrw.325.1613048349812; Thu, 11 Feb 2021 04:59:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/45] accel/tcg: Add URL of clang bug to comment about our workaround Date: Thu, 11 Feb 2021 12:58:24 +0000 Message-Id: <20210211125900.22777-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) In cpu_exec() we have a longstanding workaround for compilers which do not correctly implement the part of the sigsetjmp()/siglongjmp() spec which requires that local variables which are not changed between the setjmp and the longjmp retain their value. I recently ran across the upstream clang bug report for this; add a link to it to the comment describing the workaround, and generally expand the comment, so that we have a reasonable chance in future of understanding why it's there and determining when we can remove it, assuming clang eventually fixes the bug. Remove the /* buggy compiler */ comments on the #else and #endif: they don't add anything to understanding and are somewhat misleading since they're sandwiching the code path for *non*-buggy compilers. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Message-id: 20210129130330.30820-1-peter.maydell@linaro.org --- accel/tcg/cpu-exec.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index d9ef69121cb..f2819eec7da 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -773,17 +773,30 @@ int cpu_exec(CPUState *cpu) /* prepare setjmp context for exception handling */ if (sigsetjmp(cpu->jmp_env, 0) !=3D 0) { #if defined(__clang__) - /* Some compilers wrongly smash all local variables after - * siglongjmp. There were bug reports for gcc 4.5.0 and clang. + /* + * Some compilers wrongly smash all local variables after + * siglongjmp (the spec requires that only non-volatile locals + * which are changed between the sigsetjmp and siglongjmp are + * permitted to be trashed). There were bug reports for gcc + * 4.5.0 and clang. The bug is fixed in all versions of gcc + * that we support, but is still unfixed in clang: + * https://bugs.llvm.org/show_bug.cgi?id=3D21183 + * * Reload essential local variables here for those compilers. - * Newer versions of gcc would complain about this code (-Wclobber= ed). */ + * Newer versions of gcc would complain about this code (-Wclobber= ed), + * so we only perform the workaround for clang. + */ cpu =3D current_cpu; cc =3D CPU_GET_CLASS(cpu); -#else /* buggy compiler */ - /* Assert that the compiler does not smash local variables. */ +#else + /* + * Non-buggy compilers preserve these locals; assert that + * they have the correct value. + */ g_assert(cpu =3D=3D current_cpu); g_assert(cc =3D=3D CPU_GET_CLASS(cpu)); -#endif /* buggy compiler */ +#endif + #ifndef CONFIG_SOFTMMU tcg_debug_assert(!have_mmap_lock()); #endif --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050112; cv=none; d=zohomail.com; s=zohoarc; b=Aj/m1oRi7dd/tGCRwYjijZIsCgfZSwttGPzDxFK4H/CCYX/C0CQSLiwQd819IroVDtyB3F6984TgT02HFoe+l+NzScXRLKLTmKjCs39osbNhtdMoglLqv5wiIgqPHHge1I7wMV8haL+YR4Jzv55drTvXrahH7tzkWcGl8vd1yGE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613050112; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CSXGnS1gkrXS4FditUHGUBL10HyJbKipRKA9UbQE/Fs=; b=Msc3aOJOFAnemlxqcKP+DJVhvuLcWs8Zd/BWUJ/mn3fpN1nKfyWmU7MNWRuyiN7I41zWRcA8F/WUcuO61cT/mCZ0ZHgw2Mt3u0I4ZGCxgXOEYb4hdcm0wyl99cDoHRMAp5PTr3A7BOn87pXYHU4O6hWQv+VCo/69ny9Fttil4e4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613050112274270.34797128296816; Thu, 11 Feb 2021 05:28:32 -0800 (PST) Received: from localhost ([::1]:60318 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lAC1C-0000jY-BU for importer@patchew.org; Thu, 11 Feb 2021 08:28:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33316) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABYv-0007zm-TV for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:13 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:37393) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABYt-0008O5-Ot for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:13 -0500 Received: by mail-wr1-x429.google.com with SMTP id v15so4088128wrx.4 for ; Thu, 11 Feb 2021 04:59:11 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CSXGnS1gkrXS4FditUHGUBL10HyJbKipRKA9UbQE/Fs=; b=SYwlo1On32j7eoU2HlYHsNfAKClFzcpxG0G6YJK7dntE2LNusStBpQBA7x2U2kS2Km cVD9oiq9VOeXYh+eqMKWKT08TljSRi0pUP6zk+PPQ5zA6MSBlHgF2mORboI3oAp/gZnf FOghQMnfuzj2FG0tuym9PUNB+4+EtKiWoIl6p0TXjywf3x0E3lViuT4ysv8YXFNAap3y k0W0rc9vLXE5FomhRPmVBgi1cBU2Kn+f1ArSLqBeRXqTv3nWFchgx5VjX1ma9i5L1qjX 4As/MTIud+dXZMe82vwl2yJMPFyQQBr4wzQsFtX05GGiOs3syiS4WmCk/WxoGrYVllh4 jN5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CSXGnS1gkrXS4FditUHGUBL10HyJbKipRKA9UbQE/Fs=; b=hQo3gWzMdYbG+7+hsY2nl4KCxmsxt60VuO+AkNkbDFBZmAs5I1ht5FdRv31kLk+KhQ TfeBBPXSmMUfDq21TuweQNFIf+kU5Qbk1db7YtPBfS1VI1SngqPy9GCP1JaHGzaPfxj4 +kpTYWJKA2atJ65HTxclpm1v3dNSRaamGPm8YsOe51xKX78x/JjnyqKhE9sUyhWLK3Dm MI2sNyoBi10WvQgx4i1JupiknYnEr23irRtMDu0SyMnpkdlTUXQrm+eDbNYnwDTp7gZR THZfgvUvvhui2wtPYONIPo34Sf1pFKzC9mehTwqFDiRs4f2OhZFItps2bcYW+iv4tcrP XlnA== X-Gm-Message-State: AOAM530cC3QHV7zYLHAqiOl+3oUn+bhebWGF09Z6B0jmNtqIWqFTBTrZ HBN+rxm7TtpTwnLgA4750NkYRYJIziZJaA== X-Google-Smtp-Source: ABdhPJzPlC8O4SjRnGaqj+ab5FWG9t0b2ppd4rSWALWBW0EY7ZEqsOqSG1EAKm1WhLj69LfnURB5+A== X-Received: by 2002:adf:fd87:: with SMTP id d7mr5860989wrr.361.1613048350518; Thu, 11 Feb 2021 04:59:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/45] tcg: Introduce target-specific page data for user-only Date: Thu, 11 Feb 2021 12:58:25 +0000 Message-Id: <20210211125900.22777-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This data can be allocated by page_alloc_target_data() and released by page_set_flags(start, end, prot | PAGE_RESET). This data will be used to hold tag memory for AArch64 MTE. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu-all.h | 42 +++++++++++++++++++++++++++++++++------ accel/tcg/translate-all.c | 28 ++++++++++++++++++++++++++ linux-user/mmap.c | 4 +++- linux-user/syscall.c | 4 ++-- 4 files changed, 69 insertions(+), 9 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index cfb1d793311..af555f1798d 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -264,15 +264,21 @@ extern intptr_t qemu_host_page_mask; #define PAGE_EXEC 0x0004 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) #define PAGE_VALID 0x0008 -/* original state of the write flag (used when tracking self-modifying - code */ +/* + * Original state of the write flag (used when tracking self-modifying cod= e) + */ #define PAGE_WRITE_ORG 0x0010 -/* Invalidate the TLB entry immediately, helpful for s390x - * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs= () */ -#define PAGE_WRITE_INV 0x0040 +/* + * Invalidate the TLB entry immediately, helpful for s390x + * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs= () + */ +#define PAGE_WRITE_INV 0x0020 +/* For use with page_set_flags: page is being replaced; target_data cleare= d. */ +#define PAGE_RESET 0x0040 + #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ -#define PAGE_RESERVED 0x0020 +#define PAGE_RESERVED 0x0100 #endif /* Target-specific bits that will be used via page_get_flags(). */ #define PAGE_TARGET_1 0x0080 @@ -287,6 +293,30 @@ int walk_memory_regions(void *, walk_memory_regions_fn= ); int page_get_flags(target_ulong address); void page_set_flags(target_ulong start, target_ulong end, int flags); int page_check_range(target_ulong start, target_ulong len, int flags); + +/** + * page_alloc_target_data(address, size) + * @address: guest virtual address + * @size: size of data to allocate + * + * Allocate @size bytes of out-of-band data to associate with the + * guest page at @address. If the page is not mapped, NULL will + * be returned. If there is existing data associated with @address, + * no new memory will be allocated. + * + * The memory will be freed when the guest page is deallocated, + * e.g. with the munmap system call. + */ +void *page_alloc_target_data(target_ulong address, size_t size); + +/** + * page_get_target_data(address) + * @address: guest virtual address + * + * Return any out-of-bound memory assocated with the guest page + * at @address, as per page_alloc_target_data. + */ +void *page_get_target_data(target_ulong address); #endif =20 CPUArchState *cpu_copy(CPUArchState *env); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 81d4c83f225..bba9c8e0b3e 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -114,6 +114,7 @@ typedef struct PageDesc { unsigned int code_write_count; #else unsigned long flags; + void *target_data; #endif #ifndef CONFIG_USER_ONLY QemuSpin lock; @@ -2740,6 +2741,7 @@ int page_get_flags(target_ulong address) void page_set_flags(target_ulong start, target_ulong end, int flags) { target_ulong addr, len; + bool reset_target_data; =20 /* This function should never be called with addresses outside the guest address space. If this assert fires, it probably indicates @@ -2754,6 +2756,8 @@ void page_set_flags(target_ulong start, target_ulong = end, int flags) if (flags & PAGE_WRITE) { flags |=3D PAGE_WRITE_ORG; } + reset_target_data =3D !(flags & PAGE_VALID) || (flags & PAGE_RESET); + flags &=3D ~PAGE_RESET; =20 for (addr =3D start, len =3D end - start; len !=3D 0; @@ -2767,10 +2771,34 @@ void page_set_flags(target_ulong start, target_ulon= g end, int flags) p->first_tb) { tb_invalidate_phys_page(addr, 0); } + if (reset_target_data && p->target_data) { + g_free(p->target_data); + p->target_data =3D NULL; + } p->flags =3D flags; } } =20 +void *page_get_target_data(target_ulong address) +{ + PageDesc *p =3D page_find(address >> TARGET_PAGE_BITS); + return p ? p->target_data : NULL; +} + +void *page_alloc_target_data(target_ulong address, size_t size) +{ + PageDesc *p =3D page_find(address >> TARGET_PAGE_BITS); + void *ret =3D NULL; + + if (p->flags & PAGE_VALID) { + ret =3D p->target_data; + if (!ret) { + p->target_data =3D ret =3D g_malloc0(size); + } + } + return ret; +} + int page_check_range(target_ulong start, target_ulong len, int flags) { PageDesc *p; diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 810653c5035..c693505b601 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -599,6 +599,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, in= t target_prot, } } the_end1: + page_flags |=3D PAGE_RESET; page_set_flags(start, start + len, page_flags); the_end: trace_target_mmap_complete(start); @@ -792,7 +793,8 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong ol= d_size, new_addr =3D h2g(host_addr); prot =3D page_get_flags(old_addr); page_set_flags(old_addr, old_addr + old_size, 0); - page_set_flags(new_addr, new_addr + new_size, prot | PAGE_VALID); + page_set_flags(new_addr, new_addr + new_size, + prot | PAGE_VALID | PAGE_RESET); } tb_invalidate_phys_range(new_addr, new_addr + new_size); mmap_unlock(); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 34760779c8e..6001022e968 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -4632,8 +4632,8 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_en= v, raddr=3Dh2g((unsigned long)host_raddr); =20 page_set_flags(raddr, raddr + shm_info.shm_segsz, - PAGE_VALID | PAGE_READ | - ((shmflg & SHM_RDONLY)? 0 : PAGE_WRITE)); + PAGE_VALID | PAGE_RESET | PAGE_READ | + (shmflg & SHM_RDONLY ? 0 : PAGE_WRITE)); =20 for (i =3D 0; i < N_SHM_REGIONS; i++) { if (!shm_regions[i].in_use) { --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613049868; cv=none; d=zohomail.com; s=zohoarc; b=hwAVdEnoQ6s4H/dqA4STLFW45ofrxN4oslGZn//gHVzqRxwtJT2yr0cQUqgtrYdlx52KYY28XYmWqFVWNAUiMb1B6OquZe+2fDlmarmXC7OF3YPFFPghlt3DU2HBKO4p+94WI+wb+me6VXzOI+gUMLU8St05fxBBvQFe/waPuLE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613049868; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QlIazxiXuq6OlFVvjRA2pSJoSvTPBDYgrUB/CjxIRR8=; b=V121Vpm17u5dvIGptgsaLYE7MhRjGMg1YsNVzDWylJQGX56/ZhY7k1BMBMj1QzIiT8O+yo9qaWjrunWTBaOXluTWWDeagSSj28VByOmZFTa33oIAvad3FnVPtfrYoAE8ORQiH3+GXW+BCwSWmllJCA5+K1sWL+EFetEPx6136xE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161304986829451.63432694927121; Thu, 11 Feb 2021 05:24:28 -0800 (PST) Received: from localhost ([::1]:49698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lABjC-0008WH-Ik for importer@patchew.org; Thu, 11 Feb 2021 08:09:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33344) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABYw-00081x-Tr for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:14 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:39917) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABYu-0008Ox-J7 for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:14 -0500 Received: by mail-wm1-x32f.google.com with SMTP id u14so5649834wmq.4 for ; Thu, 11 Feb 2021 04:59:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=QlIazxiXuq6OlFVvjRA2pSJoSvTPBDYgrUB/CjxIRR8=; b=JWTp3FwS9Sx5Of8paQhTdjJiA7660XMjTKuy+nmhyTZSL7w5I1OoQxe15bETl6/Z55 zHhCoaxxFaxJpUujdxVeDg07uwOoNNHJM3km6LSx14uB7A6/L4SD8r/W2L4aSUd4WUgW 9WUYhMp5BXRFB0XTxcMFKvG4tFt0RfJUobnmiN/IV8kunQW5JXiqyJafuaDGK4Gz2kAN gAZ5kzQmqEvl/MU/FTeQn6ksauiw4wW7iYAbOSs6koA4hF0/pN1BYjM5tbpIoAu++KEu hO9TuVXDajRJH2ZBNka29eX1covsAN4AOHT4mvnjFSIKNr21EFJXlh/iMgHVXuSA7u53 Wa5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QlIazxiXuq6OlFVvjRA2pSJoSvTPBDYgrUB/CjxIRR8=; b=silNtgcuJpyE0IKudMN/bM7pjU4ZcmdahUsTb6X7dHKZZDCXSgMSZqLGFhXiMO3mh7 LFzokoUyf2O5kFbNYB14L4aADOQvrivo0sUr6b5PleFJNr/686oTDmj6CqocqUAVynvh rEICuAuVqtIBW60OU8r5hSXljzdC1pN4ZcpxzlbrPYUJlnJB1HGSuUtfazH+vQFD37HD f8KiP0zAaJNbKzS9ujDth6mv+AOg1XaDHXDVNIIjQwpZloBQne5KjEpwHq1whhq+ko3b GqShfkkEfGYdp4qe9ysM6xMARP/ugMXyDlagoRqD+8B+BhjV+MTjoXlD7lp8oOPkVKBY 5xZg== X-Gm-Message-State: AOAM532k4MQjTpWoQRtp7erKoKaJKCn2dvl2kR0WAdhLlA07PUPldnfH oXGtFH3Zx3p8QEkKF9BPUFVELvwMe/y/IQ== X-Google-Smtp-Source: ABdhPJz8hVyfEBx+m7wsyVihk7tjCWIc74Gc1NIYlUM3qRSBtnMSjdj7nN7U9TpL3/97aar9F9OIzg== X-Received: by 2002:a05:600c:21d2:: with SMTP id x18mr5173243wmj.186.1613048351162; Thu, 11 Feb 2021 04:59:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/45] linux-user: Introduce PAGE_ANON Date: Thu, 11 Feb 2021 12:58:26 +0000 Message-Id: <20210211125900.22777-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Record whether the backing page is anonymous, or if it has file backing. This will allow us to get close to the Linux AArch64 ABI for MTE, which allows tag memory only on ram-backed VMAs. The real ABI allows tag memory on files, when those files are on ram-backed filesystems, such as tmpfs. We will not be able to implement that in QEMU linux-user. Thankfully, anonymous memory for malloc arenas is the primary consumer of this feature, so this restricted version should still be of use. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu-all.h | 2 ++ linux-user/mmap.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index af555f1798d..1f47e0fe44a 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -275,6 +275,8 @@ extern intptr_t qemu_host_page_mask; #define PAGE_WRITE_INV 0x0020 /* For use with page_set_flags: page is being replaced; target_data cleare= d. */ #define PAGE_RESET 0x0040 +/* For linux-user, indicates that the page is MAP_ANON. */ +#define PAGE_ANON 0x0080 =20 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ diff --git a/linux-user/mmap.c b/linux-user/mmap.c index c693505b601..7fb4c628e11 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -599,6 +599,9 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, in= t target_prot, } } the_end1: + if (flags & MAP_ANONYMOUS) { + page_flags |=3D PAGE_ANON; + } page_flags |=3D PAGE_RESET; page_set_flags(start, start + len, page_flags); the_end: --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613049883; cv=none; d=zohomail.com; s=zohoarc; b=PqDQwXwEWiBJyhwnTaT6sEfuGL4fKx1qCEBuycFaWEdappRzoW5NKcjbPNWsvzIn42nAy5hDXnODhGWb3z+lqrDTZCIuNcvV2tCVcHgkU/iAolV47GBMi0xJKxSyXIC0kcafJ8Ozls/aHE7DAQPbZkNsxm1LRRqqmmYWqkbvaug= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613049883; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Gp/a/dceSKg/i2f6bwOBGMj9RSJz04wOVY62te5/QwU=; b=ANAvnFBqHE0uFdCr3vvq6wrggEfO7DE4oesFRXrRUI6WYW2UBuMlt5LvssH3TWIQflUckP0nIS8xN6GmYcnkezM5sNTkTEs3ggqyJST0NzCAq2xT0X2y8oVO1ehf/i3UP69/W/KeT6rc+ma4WETa26h6OC2CYuDc9H1Q5hlJ78U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613049883081713.0389302501576; Thu, 11 Feb 2021 05:24:43 -0800 (PST) Received: from localhost ([::1]:51742 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lABxZ-0004fR-Th for importer@patchew.org; Thu, 11 Feb 2021 08:24:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33352) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABYx-00082s-CT for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:15 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:43457) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABYv-0008Pj-GV for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:15 -0500 Received: by mail-wr1-x42e.google.com with SMTP id z6so4051024wrq.10 for ; Thu, 11 Feb 2021 04:59:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Gp/a/dceSKg/i2f6bwOBGMj9RSJz04wOVY62te5/QwU=; b=agxCnFfUTOyQgoupOI8jUDCq79cnLZ0KDLyJh8gUIM4ziYpx8kns9sIiwUY7JrV7js U9dTY+3VYYZ1C5gB+bVZyuz4+Kh6zZObFennlyKoer2bf+xWVv8mMalA9kmyQVEOyRqw T0sstBxL1IztRhHdAVI7omIi4T0RlJTCkOJv7ag1BniEydaCfPJ0YxDeXnrVLN1spGVG PqAYvGBVBoS3Q1zZX3AVS5WVMZ+A3aLFyTC5G50ASkxt4wMJoj8hdFDc5WV21cSrltJv PytEYkzy2iz9iGq3NHZrstbhqynZU/HpVhjO6XRd+4fTZAW1yGFta8PJweU58nu+qEzv K6pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Gp/a/dceSKg/i2f6bwOBGMj9RSJz04wOVY62te5/QwU=; b=pqR/dTkoerAQwpcjM0DSaZuzUi3wtCXZuBBMyUdmyElCifLTSHfbBxu4EuvL0NNOty wF4m09aYyK7GQtXLeN18VaNETm6+Jzucm3BIAWM/iCPYcndAbvNq1+U6HLU4hiXbSrwC NrNKeO6ITVXrIb0ukaQ1dSp6+oOdh/Wr24KGtBtM+n2loQSaL+VcdZdZdCMAGYiTT9tC XMz43o+dKvEX8eB7UOD+8DFpZZ6PnrPRuYoqhM/Hvjkd3XHj+3BKx2GsY+IYLYSwqVQH HcwxTsqEI4kgekrKgexLNgUXpNR8K0avNmRq3O/0k5RhTx9Y2TLKSWgjD9YEOaCfHkL7 ph3Q== X-Gm-Message-State: AOAM532DJtanPPrpi8okRCgyILChmjm0OS4/RaSKxvYlDcFlzxSygoMb DMkUp5JkpdRazIOOO9H7KJNGzMfJTF5bsg== X-Google-Smtp-Source: ABdhPJz6FKTUHocf2RvsHKNs7TyKRhe4GBxbWYBAq6F/nXOU5BavDzFqbFowF9we3vIuipsKTigMmA== X-Received: by 2002:a5d:408a:: with SMTP id o10mr669215wrp.427.1613048351985; Thu, 11 Feb 2021 04:59:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/45] exec: Use uintptr_t for guest_base Date: Thu, 11 Feb 2021 12:58:27 +0000 Message-Id: <20210211125900.22777-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is more descriptive than 'unsigned long'. No functional change, since these match on all linux+bsd hosts. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu-all.h | 2 +- bsd-user/main.c | 4 ++-- linux-user/elfload.c | 4 ++-- linux-user/main.c | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 1f47e0fe44a..d6ad774c015 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -158,7 +158,7 @@ static inline void tswap64s(uint64_t *s) /* On some host systems the guest address space is reserved on the host. * This allows the guest address space to be offset to a convenient locati= on. */ -extern unsigned long guest_base; +extern uintptr_t guest_base; extern bool have_guest_base; extern unsigned long reserved_va; =20 diff --git a/bsd-user/main.c b/bsd-user/main.c index 7cc08024e36..385d35886a0 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -42,7 +42,7 @@ =20 int singlestep; unsigned long mmap_min_addr; -unsigned long guest_base; +uintptr_t guest_base; bool have_guest_base; unsigned long reserved_va; =20 @@ -970,7 +970,7 @@ int main(int argc, char **argv) g_free(target_environ); =20 if (qemu_loglevel_mask(CPU_LOG_PAGE)) { - qemu_log("guest_base 0x%lx\n", guest_base); + qemu_log("guest_base %p\n", (void *)guest_base); log_page_dump("binary load"); =20 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); diff --git a/linux-user/elfload.c b/linux-user/elfload.c index a64050713f2..29f07bb2346 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2135,9 +2135,9 @@ static void pgb_have_guest_base(const char *image_nam= e, abi_ulong guest_loaddr, void *addr, *test; =20 if (!QEMU_IS_ALIGNED(guest_base, align)) { - fprintf(stderr, "Requested guest base 0x%lx does not satisfy " + fprintf(stderr, "Requested guest base %p does not satisfy " "host minimum alignment (0x%lx)\n", - guest_base, align); + (void *)guest_base, align); exit(EXIT_FAILURE); } =20 diff --git a/linux-user/main.c b/linux-user/main.c index 2e3c1698787..81f48ff54ed 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -59,7 +59,7 @@ static const char *cpu_model; static const char *cpu_type; static const char *seed_optarg; unsigned long mmap_min_addr; -unsigned long guest_base; +uintptr_t guest_base; bool have_guest_base; =20 /* @@ -824,7 +824,7 @@ int main(int argc, char **argv, char **envp) g_free(target_environ); =20 if (qemu_loglevel_mask(CPU_LOG_PAGE)) { - qemu_log("guest_base 0x%lx\n", guest_base); + qemu_log("guest_base %p\n", (void *)guest_base); log_page_dump("binary load"); =20 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050752; cv=none; d=zohomail.com; s=zohoarc; b=NiL0FczcDl21A7LsvExIQ3rFf1Ms50vmL7+rnTh9+ElzxB3l+NL5poBFWsKX45XsROmbp1gJxghRy52mqSMjRXXLfOMq8vXztnt8bjT1Jdy43GlFoo4RCM0hMS2s66z96cFpj7cVKVnKX0s4KoSmKRQ/GVuN9jD9Trt0Z+cP8qc= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=4Zl9k+RBMwhw8/WWyjo+oRnYDhbgHyVsV5EaC0rKvvc=; b=S/CYV782LDcyWg5f8OK3hc8hRSN1iVm4P9f+hnyTPLj2LxqL5C0R3b3q+tKdJeDS3K KzTMxMFl2Mf+3mbv9sJ8P7Cpd1jfauvxjgVwiJ5vKcxlOa0hwJQ0ZPgg1lHXG6fZVm3r xh2+m1qdgH/c2CTE+CUnXxeC64koxnJXBrcRH2iDC9fn9Wxksrgl+WxBZAZPz/8ymdoG Q1gQgyM4BHJb4azu9HdDMvz97uQnN4KU02cHGYQTAsNlUqc/up2k5485OlVRIdDb0PaZ V9qjnkPrjL368PNIKh7xUKmzC1rvRTDMLtyORY6MwkLc5XSFZpXX2FgppjXWGmvBgmF0 oQlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4Zl9k+RBMwhw8/WWyjo+oRnYDhbgHyVsV5EaC0rKvvc=; b=UDxuY6aaFS69Ct2kwUIkoB1cB65u2RxWRnIDKStykTLEaCaer3VcHY5l2Bk2O6EdyX VwZK8ugoUblZHizIb5etZGGZtjrCniVrRg6qMCQKUTc+SUL2pW0nnREYGCbvwjaSY8Dx RaKdOzjbxJJuXGBwPvnW2kksdijZR645VaczUAqlL/FZrNUvW0Rf23PMC5YBvxU2jY7Y wf0BVJZkiuFiOltFkahD/fJOfjNLbkzQq3IkOlC4DQg1G0iZ8g6rUKutE4m0gwGJureO QOy8zexmHlrxBu5cIDbhgpaCY35bZ8+DtPlpOWbCyvcRUBDNTxLS1YxJgXdPutaf5Yl1 930Q== X-Gm-Message-State: AOAM532oOKfy2y05EBjge+a3tRqp4hw9HhrfZk/82sa3EwKRCZ4r3Bm+ axRbOW8s+7LCQI9H9TqF3R7QD6SxV944lw== X-Google-Smtp-Source: ABdhPJyVp0+rceGyyOSU2Wc/Frrrl9XMMNAIXr3Rr40J7/VUetLo5YCqKcRdDVtsogPXkBOAWDEUOQ== X-Received: by 2002:a1c:b7d7:: with SMTP id h206mr5128926wmf.64.1613048352752; Thu, 11 Feb 2021 04:59:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/45] exec: Use uintptr_t in cpu_ldst.h Date: Thu, 11 Feb 2021 12:58:28 +0000 Message-Id: <20210211125900.22777-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is more descriptive than 'unsigned long'. No functional change, since these match on all linux+bsd hosts. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu_ldst.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index ef54cb7e1f8..3f9063aaded 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -70,14 +70,14 @@ typedef uint64_t abi_ptr; #endif =20 /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ -#define g2h(x) ((void *)((unsigned long)(abi_ptr)(x) + guest_base)) +#define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) =20 #if HOST_LONG_BITS <=3D TARGET_VIRT_ADDR_SPACE_BITS #define guest_addr_valid(x) (1) #else #define guest_addr_valid(x) ((x) <=3D GUEST_ADDR_MAX) #endif -#define h2g_valid(x) guest_addr_valid((unsigned long)(x) - guest_base) +#define h2g_valid(x) guest_addr_valid((uintptr_t)(x) - guest_base) =20 static inline int guest_range_valid(unsigned long start, unsigned long len) { @@ -85,7 +85,7 @@ static inline int guest_range_valid(unsigned long start, = unsigned long len) } =20 #define h2g_nocheck(x) ({ \ - unsigned long __ret =3D (unsigned long)(x) - guest_base; \ + uintptr_t __ret =3D (uintptr_t)(x) - guest_base; \ (abi_ptr)__ret; \ }) =20 --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050291; cv=none; d=zohomail.com; s=zohoarc; b=IKv4N58Ui9CcK56w4ht8CBfr4kSPDwIhYQ6LaUcXascfh/2M/msVffzagveahx2OUuJh/BUpq+mbi19eRyYJ0P4rLcZR+yO+IKrQLF6aUbcWypWSfbZUUWLLwChj8ywjGSV0Vm3B5QnAFkytQDrP+ROwQIQ/GBqqcaErtODTGvY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613050291; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DCszVGUp3iayThJPWT9pda+ZcUuou8eH26qHc7GyT0A=; b=Ss65H1wCqx8zDm6LXKUqlDZaKjqNtUJgwHz1iaNxCIZJk8GgyF+HAunZbuX9z2zEYAiuNp37CGC/uQqUnvp3UC4AaGdaRQtpoPZh+zRpiNQ0lAtfBw3xyKXdV5yaMERJiB9WMd9v5lYOVZ3Zqo3UmiYxpMIFTeRy6n3YVtucRjM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613050291443506.8579411162174; Thu, 11 Feb 2021 05:31:31 -0800 (PST) Received: from localhost ([::1]:40422 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lAC4A-0004Vf-5d for importer@patchew.org; Thu, 11 Feb 2021 08:31:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33452) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZ1-0008A1-1e for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:19 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:51170) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABYw-0008Q4-L1 for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:18 -0500 Received: by mail-wm1-x335.google.com with SMTP id 190so5475451wmz.0 for ; Thu, 11 Feb 2021 04:59:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DCszVGUp3iayThJPWT9pda+ZcUuou8eH26qHc7GyT0A=; b=jtu8C/ANWsLvM4OemxJadzfYWfZS/rY26KL+zdqAsqBhFQRhhL8XrkPpFqCDd/cUqK KjP5jzS/h9Rwsj94Wnw1An20qfHhHfouM+H63lFxZnEKidT9KIzSv1Y6mVbnuHCa5cYL 4iMvHFoH2lwA8DOOY4Atp1pEiT4GyF6rB66uQbB89seHGeiLZakbVToA21SXkrLXqmZ6 yojqLqjBGLY4wA51INtMPAfws8rVBKlt1fNONyKwXOz+txOpNiCzcPHicNAlFgtvm7op V32D6TF7GasdgHi4Aq2qqeaaUkFAy41WDJKVoTTI/SLJvWrolOpQtqYsEjQjmuJGfUgb erxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DCszVGUp3iayThJPWT9pda+ZcUuou8eH26qHc7GyT0A=; b=hk6r09wjHax+WXwnuBYHSUKqqGmSKYWnTUqDkA6TED66Vlhgb6+X33cymkfj6YSITn mFIK2c3THA7+KOQg2/vNq7q2QdT22K4Q46sAkMCx63aUf0hbjDnT3abbEOS3xsqy/8ic fOdHFVW6gUJvvhQitv0QqXN/DXQvfRw4mbvKQjD0rXH4F90DpmgkVM++5tt/y/2IupKm ty9RkZ9Y5cCazLjhn/lnMnOhJmS0CBROjkGDDXNz6ckhMYyNijGe2N8dBgXEVwjSqYcd M0hBcYsq7dry24nPcpt3YIQ6edOZmJrKj9Mzu8mtwgfkH1SdfEeLx3UE79VPSPll1DVF igKg== X-Gm-Message-State: AOAM532Fba2x+JHjZRRY9Exwc6TT7iRvNw8OYoQYXZHUeAbfvWbnSUPP B5iMNWwRQYDNPY+AT7RMM6vXy0j//4ZMAQ== X-Google-Smtp-Source: ABdhPJz7zgP2CHNOYX8OV2+atBFhLOSlxbEnJTGtWJkZYsoi/Vwi4IxVLHnYOeH4dNRDHl/3YtPOww== X-Received: by 2002:a1c:720b:: with SMTP id n11mr5180014wmc.154.1613048353390; Thu, 11 Feb 2021 04:59:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/45] exec: Improve types for guest_addr_valid Date: Thu, 11 Feb 2021 12:58:29 +0000 Message-Id: <20210211125900.22777-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Return bool not int; pass abi_ulong not 'unsigned long'. All callers use abi_ulong already, so the change in type has no effect. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu_ldst.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 3f9063aaded..5e8878ee9b1 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -79,7 +79,7 @@ typedef uint64_t abi_ptr; #endif #define h2g_valid(x) guest_addr_valid((uintptr_t)(x) - guest_base) =20 -static inline int guest_range_valid(unsigned long start, unsigned long len) +static inline bool guest_range_valid(abi_ulong start, abi_ulong len) { return len - 1 <=3D GUEST_ADDR_MAX && start <=3D GUEST_ADDR_MAX - len = + 1; } --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613049735; cv=none; d=zohomail.com; s=zohoarc; b=PausEcyvrV6kSkoW/KDcqmbmmh1Iw6t44eNbieJhjUWW6D0/ez2rz63/q6MNlNUI6S6w8DGe+ukiqUK2j9G3+A7SNimJ4/Jm0iBPzIpXeC3KaxaltsmmLuflF4h6VNNOZzWTZrNZNkssbRiANUQo3yOyUfnjlPmlIkAP7OQroj8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613049735; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OnfOygHIMNXAAkLXI4Fs2xQ1ZBnGDlgl1MLlwjZp+qg=; b=Q5NGmr0kPrnYfUGnZBi/3xxEvjnrlli0P65hDEB8NkWuUqaxdj7umppBBu5/9HWSPyDr2hOSAb8lwLBF1TqzuzXF3KfqoxxKbS/9MYpELA+Fokkw45Odk6uU+poGCh/slZHDkYocvja18PK4JHlHH/XeZdn6ejUgZxrEGoB2rgI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613049734843541.1215893558771; Thu, 11 Feb 2021 05:22:14 -0800 (PST) Received: from localhost ([::1]:43198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lABv3-000144-L7 for importer@patchew.org; Thu, 11 Feb 2021 08:22:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33392) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABYz-00085q-0v for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:17 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:32797) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABYx-0008QW-8N for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:16 -0500 Received: by mail-wr1-x42c.google.com with SMTP id 7so4127443wrz.0 for ; Thu, 11 Feb 2021 04:59:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OnfOygHIMNXAAkLXI4Fs2xQ1ZBnGDlgl1MLlwjZp+qg=; b=L2+1HmwfbKYrq8a20zuaE796fdN0RYQjB2CnkiTrFqqMBmn1b3n8EH7bEuP3d55a/e q1DcRSl1wqsRNMxH2fiHKp5xv2+WF4yDvMylSuhfeE6JZFEWGNiPFyNbHsK9KDkG4HZZ w4eG/6PzpgHVVtX9tgCcYUvxyIFATSRTAjzmAv5oToEgN3O5E6cqudmOuEZNAuAuF6yK VbY1gPyXze84eED2YKq7BWLDr2q+jityQ8z7tPfKD8/nM9keIEQUq6aKoYXPUZUD10WO so8/7zUIY5NE+CdQd4CO9q6WlJfbBUcFS2VsY190C8rL+YzFnllX6+kfIu1mAPPC5BOK yeig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OnfOygHIMNXAAkLXI4Fs2xQ1ZBnGDlgl1MLlwjZp+qg=; b=WQjGAyXxDTBEGAbkuw7uzHGfvGpNsJjIH2q5/YyKwltXxdZxcm25XasguBiVxWaG3l xbyNDhjUJHfOrde/h00/KZr3grWOAYohyMMCgPSMaAiCwKStl+r/+oOb70mWOdeXQ+VE ZD7JGv6ioRhRfhRXHGiIaoJPe715cqsH3heFLKVVIeslz3kyCtalgSHWCJ6RRp5upqG4 mHfWCg/3Y2D2sKAGXki22m37P8HiEUyqjmEH1+V5GorIZAPVyoKlqnIRECrAubm7UorT Yn+cJG4KUKZtvIYgb74YLOBSiobPuW8jQXmbraLexjSpGzcaBAA6c0SdhKeZUyTc10+u UXpw== X-Gm-Message-State: AOAM532HmvAS7l/XJ9M70KWqd7aPAgN4moJY9gXqNuLHqc5W5lif3EqY cZQXEy2amZ/PJ7gQa1nF7tIluJKV50FaNA== X-Google-Smtp-Source: ABdhPJx4lYa+PjJbCccT9xQN/DvrarbBpv0PMpmiHQcQlLjwu0RY3q8kJMf6c1YkA05bHojI+Y4xLw== X-Received: by 2002:adf:e511:: with SMTP id j17mr5781754wrm.251.1613048354005; Thu, 11 Feb 2021 04:59:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/45] linux-user: Check for overflow in access_ok Date: Thu, 11 Feb 2021 12:58:30 +0000 Message-Id: <20210211125900.22777-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Verify that addr + size - 1 does not wrap around. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/qemu.h | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 17aa9921657..441ba6a78bb 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -491,12 +491,19 @@ extern unsigned long guest_stack_size; #define VERIFY_READ 0 #define VERIFY_WRITE 1 /* implies read access */ =20 -static inline int access_ok(int type, abi_ulong addr, abi_ulong size) +static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { - return guest_addr_valid(addr) && - (size =3D=3D 0 || guest_addr_valid(addr + size - 1)) && - page_check_range((target_ulong)addr, size, - (type =3D=3D VERIFY_READ) ? PAGE_READ : (PAGE_= READ | PAGE_WRITE)) =3D=3D 0; + if (!guest_addr_valid(addr)) { + return false; + } + if (size !=3D 0 && + (addr + size - 1 < addr || + !guest_addr_valid(addr + size - 1))) { + return false; + } + return page_check_range((target_ulong)addr, size, + (type =3D=3D VERIFY_READ) ? PAGE_READ : + (PAGE_READ | PAGE_WRITE)) =3D=3D 0; } =20 /* NOTE __get_user and __put_user use host pointers and don't check access. --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613049882; cv=none; d=zohomail.com; s=zohoarc; b=SVXiRXYJ6pyswnuTkXQcqu4YAIc1stvIhBktBfDNnpU63XY58a+GnISIS6gN9n6ZKHHi0efyXgc1a6Fdoim9YXQk59gDRRmYOiE+i44n+yUD78LbZjcv/0ljwuSClhMHuzdjYA5Xco5vkxiRNGvA7G0oYjZHxVFByDyXqKDHX3k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613049882; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=k24l6V2v0PKg+s2YVxBs6b556yq59N9tvuPY0mxSPMk=; b=d8sjn58S30NKhHRV5lDT6ezcnUH4kNKZH6Scs5/f1MRGAT+hf8rNVcHCprPgicCpisKHKBykrbZz1SJ4ZFRDKiOJjEXJ2H0SmhLAiaEnvFs/StALcDatVpC0Uyy/B6hZit/Q1pe/ZBnsWI6ubGzks3A5hRlrPhM/zNInA/mfGSg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16130498817495.21124265707806; Thu, 11 Feb 2021 05:24:41 -0800 (PST) Received: from localhost ([::1]:51642 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lABxY-0004dD-Ka for importer@patchew.org; Thu, 11 Feb 2021 08:24:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33404) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABYz-000873-EC for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:17 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:37276) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABYx-0008RQ-SW for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:17 -0500 Received: by mail-wm1-x331.google.com with SMTP id m1so5642960wml.2 for ; Thu, 11 Feb 2021 04:59:15 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=k24l6V2v0PKg+s2YVxBs6b556yq59N9tvuPY0mxSPMk=; b=ylKsB2WKERWij7lfxJhhp9Gr1hQF8/30glw9WlHf9t0t1eLd7J61JUZJBIH60Ny696 UlnVmOsfCYbOZFbEbCnyCk2HE+wqaWP0eJoGYlDg/VXdeh9w3IKfvu8OkzQry2R85EFk Gcxp3RKZkrb4GJXe3oGkrHF7cMlnPjndQb3VDKArw2f/96fbZ+u9b7apivKAhOieygqX oakRIFGCO6FTSFzuR5R4o8s4l+p3Rs9vSKAtfQk8VPvyujxOAzelNm1qZ1MBVvWPfZXv h5E5ztElCbhOtvuBZvvYdDWl1kufG4bBgBQu77/5dtWavN1afhsCA4j/QbAwqsqQ04d1 hh9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=k24l6V2v0PKg+s2YVxBs6b556yq59N9tvuPY0mxSPMk=; b=hVEvU+n8KV84oc7h1gfqlCQH9ODt9r2C2nW3HsbIOtFYj0Qu/tvRI0f/x7S1pV76Sd 9d5Ljku4QGTWIS+2jS52rjyFt+o/1O3prTohwJ2HbE9M8onw7fOkJkk0KGnJTaawPdMb 4WD4sHVCF6s7qW7il6xNMY2btSVWEeowx8ppCd/Ch8cVtYA/hcWJvIGKepzCDjYCRlaX XxJcKWikYz2Q42oRRDnOkw/jxJ4L9oitgNCSzBvJNOMtBJPZ1m4lmKA536/RiL01Eonu JY1ap0WlXEdYY2yWA6nuyN1zKRMyTr8nAGNLTxbDM6sHXft+FxzhH10zA7XFo1Lxn9i/ vsuA== X-Gm-Message-State: AOAM532npIvpyG5SmD2CNeUlDON1DkVoQ3y26lQUocjQD3NZnL8/BHjK Olg3Om1sZzbxyU4ED4qAFb73lf9nze0E5Q== X-Google-Smtp-Source: ABdhPJxMczFN1d8qrvR+zOSNFIiy1FyRmv3OtKiy5VVWd8HwE7xiexQ5pt/41+aqOOylBqIHiXhmPQ== X-Received: by 2002:a1c:7312:: with SMTP id d18mr5023438wmb.155.1613048354606; Thu, 11 Feb 2021 04:59:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/45] linux-user: Tidy VERIFY_READ/VERIFY_WRITE Date: Thu, 11 Feb 2021 12:58:31 +0000 Message-Id: <20210211125900.22777-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson These constants are only ever used with access_ok, and friends. Rather than translating them to PAGE_* bits, let them equal the PAGE_* bits to begin. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/qemu.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 441ba6a78bb..9251337daf2 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -488,8 +488,8 @@ extern unsigned long guest_stack_size; =20 /* user access */ =20 -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 /* implies read access */ +#define VERIFY_READ PAGE_READ +#define VERIFY_WRITE (PAGE_READ | PAGE_WRITE) =20 static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { @@ -501,9 +501,7 @@ static inline bool access_ok(int type, abi_ulong addr, = abi_ulong size) !guest_addr_valid(addr + size - 1))) { return false; } - return page_check_range((target_ulong)addr, size, - (type =3D=3D VERIFY_READ) ? PAGE_READ : - (PAGE_READ | PAGE_WRITE)) =3D=3D 0; + return page_check_range((target_ulong)addr, size, type) =3D=3D 0; } =20 /* NOTE __get_user and __put_user use host pointers and don't check access. --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050089; cv=none; d=zohomail.com; s=zohoarc; b=JLr5ixsqeXeimk3qJ1JxiEWMUlfPBEjHH/zwxYRPn+avM5ewuZF9aWY49H0hFmEVJxvEDPKCnhmfeMXVMzsbKXBDDUTZrXmbQIX8t0oCjRyvB3wiJLEk0k3yWuXuADATy/ZBjCevSBbPLjZ+rMhB4vwSz+yxPKAfON55fJnh/aw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613050089; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=r4/XUYibNUpbYwhy/01KppmQNmZXhGw9VCHepnGtsvI=; b=ee1aKQSTGwPJdV0FbTy40tA2nzBvKMrZqDL29TsoBNJmEzCCgP47sbCBw2fScu3at2S3zFOqvHK76n8w+0Yb4FA6vHtHAhB/sm15ilQrVHFt4sAfOKoLtpM482mHTY3vIFbiL3yefRtImF4w2Ev2k3V5+xAC9z0BjHAd7JVWfRg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613050088758800.9669639466925; Thu, 11 Feb 2021 05:28:08 -0800 (PST) Received: from localhost ([::1]:59950 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lAC0t-0000Z0-90 for importer@patchew.org; Thu, 11 Feb 2021 08:28:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33426) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZ0-00088H-8g for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:18 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:51159) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABYy-0008Rb-IR for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:17 -0500 Received: by mail-wm1-x329.google.com with SMTP id 190so5475533wmz.0 for ; Thu, 11 Feb 2021 04:59:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=r4/XUYibNUpbYwhy/01KppmQNmZXhGw9VCHepnGtsvI=; b=wsYhXN0ewg11CKys2fvCscPEwk7i4vvxRNe4k1Lv5yDyPgU+Dj9drN0/zE5d6lBfLK EXxr+SGwIMKheWvQlpaLfeNdlY2FUZVE6Gn9RfDtyvOv3FlzU8idTiLpHJBoZMmgqLix PKPtU0lgroOe+LGxfoA8F15/7tj20QNE8PMez99GupEKsfTjTOIm5j0uRqwRLhNSQP1X eZygP5HQGL5biLDuMeRUZ/zhs+4sRaEhm2AFgrwEiwJrgdw5T3R+gjmRlQavRlsn35wZ X5pDIdaGwwdW/9l8tmzw//L2cnrVDkBdejd1CBBU6s6aQjiKlyrekJ/Tzq9eEaTQxk+O kWAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r4/XUYibNUpbYwhy/01KppmQNmZXhGw9VCHepnGtsvI=; b=VHCeCK6jSm7PVDfOD+1GIBC+uG9kvJFV13iPJau+wNsMvykZVrRluNjB/Pdc9LGOnv jr+6HcK6zsTSw7+zvF7jPkySPeyKFSGy9GHUMTmIcvRFDZUIKHd0ZAMrmwA+lRMY+Nz4 HRKyK6R2NCkRPzgBx74bdVn/+0hUBolR+wKi+i4LEwdCiK/nij7if87m3zDDlVew7EY5 g1FYdTPw2JzQTt6SZJ+6vpazv73nJekHg7yQPIlaKzyy1UWT3hZynf93g5ORqiTBjDte Uir0I2djybFjLyXbMz6+ATW8Uz6Vg8LbtSNXzA3q0bULaZ6gEaRosnp3pkebd8OicuR8 9cYg== X-Gm-Message-State: AOAM5300u2gr85fMQqVjd+mesXp1fqOWZN9KZwRVKx5UQ034b3B66M/D IhD9HGBedH+e4L0Tkm2lYydKeShqZ1rw9w== X-Google-Smtp-Source: ABdhPJxQAbtVtDFlaOrSZgcENcZnhqUQZ8I/PPCtqZO3tgLx91/61rqpxEIhwH3hRw43zjdUF1PpIg== X-Received: by 2002:a1c:5f82:: with SMTP id t124mr5141010wmb.55.1613048355270; Thu, 11 Feb 2021 04:59:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/45] bsd-user: Tidy VERIFY_READ/VERIFY_WRITE Date: Thu, 11 Feb 2021 12:58:32 +0000 Message-Id: <20210211125900.22777-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson These constants are only ever used with access_ok, and friends. Rather than translating them to PAGE_* bits, let them equal the PAGE_* bits to begin. Reviewed-by: Warner Losh Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- bsd-user/qemu.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index f8bb1e5459d..4076adabd08 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -218,13 +218,12 @@ extern unsigned long x86_stack_size; =20 /* user access */ =20 -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 /* implies read access */ +#define VERIFY_READ PAGE_READ +#define VERIFY_WRITE (PAGE_READ | PAGE_WRITE) =20 -static inline int access_ok(int type, abi_ulong addr, abi_ulong size) +static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { - return page_check_range((target_ulong)addr, size, - (type =3D=3D VERIFY_READ) ? PAGE_READ : (PAGE_= READ | PAGE_WRITE)) =3D=3D 0; + return page_check_range((target_ulong)addr, size, type) =3D=3D 0; } =20 /* NOTE __get_user and __put_user use host pointers and don't check access= . */ --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050280; cv=none; d=zohomail.com; s=zohoarc; b=O1xI/t/Xw9JkPpEb192kfx2R5inLo+Lcf+RDdxpvzh7eXFYyb3GXE6jF/7QPVuxCE9T/mOj/Co6NgubLJNuMOr7flM/1IBo4uuxxdHv0l4UwZNa6cmarN29wBm3MCs43osMnrlf54feTmR1UVLs1Y+Uq9A3Ve9IShltYtkHQ5Hs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613050280; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=efv+EhfVcvK/k/9b5RYb8iS1WEkIs2L9Rka7/t1fQqQ=; b=c1GDE5hnIfWhVYG3dG9Zwhi9gYeJTnZai1W28UVkqzNtAisC1WW7/QcNyRmGxWnCQyN5SdcbajBWgj/1h7RA7jdn/VP8ndy6XxRxlIkM55D2GEfemwx9qm58Dnu4H4jmvC/F+fs8PRbgwNjiFwEMd05dFjltNfIELrKCxSKeeVQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613050280003614.2868345662283; Thu, 11 Feb 2021 05:31:20 -0800 (PST) Received: from localhost ([::1]:39998 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lAC3y-0004LK-NS for importer@patchew.org; Thu, 11 Feb 2021 08:31:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33508) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZ3-0008Ev-Vj for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:22 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:35639) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABYz-0008S4-9v for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:21 -0500 Received: by mail-wm1-x333.google.com with SMTP id n10so3779353wmq.0 for ; Thu, 11 Feb 2021 04:59:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=efv+EhfVcvK/k/9b5RYb8iS1WEkIs2L9Rka7/t1fQqQ=; b=GRBBFLaKmfGoCcbYqCC9eCt9BmTwpnCXcsPeX8swUYoKx/3wfeLq28t0aIp7DiVTeB zPN01L8Vv+bfDBHjgZL3fqFhY8AF4jr5bhCKiF1x4nL5RxvmFAlUky1GT2NXPo9xQ9SN jwgUSGICPl0yqKgqd0eOYY+Gh4k5mgOp+ebd1fNORNOHEnWBSau+Bjd5Zjkcpy4JOVrA 1LDSfg+oWac3H1Wt/mk0t1yUvT7ySelaU5l2qKhk5oY3WpkmrSC1KjfLclCFDa2T2tiZ wtuoRVzNvdALUxd2o8LlyyjZfRf3lijTvub5BG9uJEdaKgWbOU7DIfuWlev98pUBDVLp NY8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=efv+EhfVcvK/k/9b5RYb8iS1WEkIs2L9Rka7/t1fQqQ=; b=WBezaCMTGEvtXS53PAKS84sCE+dI5GPmEIn1kEp4r33OUUKK+lt5YvFUTDsSVSV/P+ lihUKAzaxP32qBzQAKrqXaoYLWxKaKVFMVNa4Hb9OfUq613tmwnZXxoWoGKnOYIRJebK u0pmYjm//oI0Xn5+OZN2H4iLMBza3mkMWhj2LH+vt+I0jvvJIHLtY+ni95CFEcFw3XtQ qcl40NIpAni93ksNFIBTR/QhH7/kFyMK/d6vQVk8rLlX70lYw328VeP6eClCx300E5YT 4kjTGD/qT2HMLqtcTNDf/DVchJpUd8Nmb47tD89DUYL3+PZ9Dz38rcogQXfYY3bu+K7s sM6w== X-Gm-Message-State: AOAM531z339z8LmiZ9p9EKfqRVCqkp8D9pzRcLkI/j+xpGg33wHc6kLG PRTAAVZIyL3nlqOLMvV3IyygRic/vwLfNg== X-Google-Smtp-Source: ABdhPJxZbL1n38DPsQAh6xbUpnntioftMWLVR3Dfak9ua7uItGU2CiUZ+nRciQ9BIAuxu9xnQ65ZgQ== X-Received: by 2002:a1c:7f93:: with SMTP id a141mr5181492wmd.105.1613048356016; Thu, 11 Feb 2021 04:59:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/45] linux-user: Do not use guest_addr_valid for h2g_valid Date: Thu, 11 Feb 2021 12:58:33 +0000 Message-Id: <20210211125900.22777-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is the only use of guest_addr_valid that does not begin with a guest address, but a host address being transformed to a guest address. We will shortly adjust guest_addr_valid to handle guest memory tags, and the host address should not be subjected to that. Move h2g_valid adjacent to the other h2g macros. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu_ldst.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 5e8878ee9b1..4e6ef3d5429 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -77,13 +77,16 @@ typedef uint64_t abi_ptr; #else #define guest_addr_valid(x) ((x) <=3D GUEST_ADDR_MAX) #endif -#define h2g_valid(x) guest_addr_valid((uintptr_t)(x) - guest_base) =20 static inline bool guest_range_valid(abi_ulong start, abi_ulong len) { return len - 1 <=3D GUEST_ADDR_MAX && start <=3D GUEST_ADDR_MAX - len = + 1; } =20 +#define h2g_valid(x) \ + (HOST_LONG_BITS <=3D TARGET_VIRT_ADDR_SPACE_BITS || \ + (uintptr_t)(x) - guest_base <=3D GUEST_ADDR_MAX) + #define h2g_nocheck(x) ({ \ uintptr_t __ret =3D (uintptr_t)(x) - guest_base; \ (abi_ptr)__ret; \ --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613049793; cv=none; d=zohomail.com; s=zohoarc; b=LDmsFp9Epni8dAvw8/vaJPkJpL8X9Eu9aUiqOGWt6T6/YlSBp08shs34Zc06WC0FKyebBQE6zuLeEYeO/vscmwvSsv/Iv1+WmJfPL4WkrQeY9NpubSBaPDXhnglw0F68VS35XOSd0Gm4ius9Fj/UaJWMFkQjrDmhA2mSo312mpI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613049793; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cQDWIhDilC+yNy4j3Tp1pvBrVTMvqQhhNRHgD7iTmbc=; b=gofxjJR83MPCq4abM4jo+HpFFEE7eJox1Jl2iX/b5FnxKZkq7QvdBC7MmYuCWVxfisOU8y1tnSTxVnDe8D8pnEgdqf65Dpxicf3eg7IETlqqtETnqJerEanldxK67zbhtUu0sYO4UkTXZmvbW2i6ca7kKMFyE/ALaY+CG5y80L8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613049793669254.7744070678175; Thu, 11 Feb 2021 05:23:13 -0800 (PST) Received: from localhost ([::1]:44778 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lABw8-0001mc-Ic for importer@patchew.org; Thu, 11 Feb 2021 08:23:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33480) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZ2-0008Di-P7 for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:20 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:39923) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZ0-0008Sa-3I for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:19 -0500 Received: by mail-wm1-x334.google.com with SMTP id u14so5650087wmq.4 for ; Thu, 11 Feb 2021 04:59:17 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cQDWIhDilC+yNy4j3Tp1pvBrVTMvqQhhNRHgD7iTmbc=; b=Kf1zQ9i9GUhpktYVj1CTgj/HT0qjH4qSNOPQDk/xq/Jy6hWCN5rL+swqw42t0UiQ/Y mBCukuq/mJkJVr9439I4ypKGjsd0jbhlfyBmIt7XHeedE/530N0qjtzDHfRuo2pH8afF OsIl2Oc8PAcN4UsHhqjf/cp7z9vYiS3JITW/7La9CwoXMyXnnqYg15DNlHUM6WOPUMmS fBsTj5vOZPe9JuVGM2YfGa/A0kidaMnIEI6LQ04SC+3wnyWj8pCwR/uFkzT4sB4V5CjK 9q2SdN+hC7Pm20zsqdBj+Nznq+8x8ma5n/Ucr+TWezhPoF9cudNb01xxqzGpF4gRCv6G vn6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cQDWIhDilC+yNy4j3Tp1pvBrVTMvqQhhNRHgD7iTmbc=; b=AhxyCO2dAdmwsCohiuTBjPrml79xa/GxuSKu3AlfxtlEt4vgcTltNdsz+l5YP6D1hS rd8+9E8P6UBzj2simQM+w6LkzyGAFN0XQZtJ6wPrMHN05l+JxGfKyzZPQt59mPzpMB7c Rv/TR3/8dgFDiNHMd9rO3t1hcv6Z/4p79KHhNhFQzlPzu6sTwhyEOSPs+PlywV1Cf3SW ocNvxt1/f6D5mI+VxgumtEmDy46gBPTgGpw4QH9hhUIvf3cayb5nksvxDuvudjQhuCGY FkWrkvlYtSs0x5w+A1QOjVyQL+T4rkDZBBbY5diklN4gOCxFe5uYh6Y0M8J91EAObzBO AQCw== X-Gm-Message-State: AOAM532iEYx/RP2DuEjGFMvr+2c9C5/X+DFvb2UEenWdKJExsZF5XFY4 2ueMqLhtrq0NBDo6/g7SEWF1ZLW6ciE3wA== X-Google-Smtp-Source: ABdhPJxRpvA05Iv/nwxnrGuwFTxH0mzQWpBv4+ODIIn1FFSev9pRiYtXUWbnNSwrAcL1h2EVjHWz/A== X-Received: by 2002:a1c:3cd6:: with SMTP id j205mr4995120wma.166.1613048356762; Thu, 11 Feb 2021 04:59:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/45] linux-user: Fix guest_addr_valid vs reserved_va Date: Thu, 11 Feb 2021 12:58:34 +0000 Message-Id: <20210211125900.22777-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We must always use GUEST_ADDR_MAX, because even 32-bit hosts can use -R to restrict the memory address of the guest. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu_ldst.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 4e6ef3d5429..e62f4fba001 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -72,11 +72,10 @@ typedef uint64_t abi_ptr; /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ #define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) =20 -#if HOST_LONG_BITS <=3D TARGET_VIRT_ADDR_SPACE_BITS -#define guest_addr_valid(x) (1) -#else -#define guest_addr_valid(x) ((x) <=3D GUEST_ADDR_MAX) -#endif +static inline bool guest_addr_valid(abi_ulong x) +{ + return x <=3D GUEST_ADDR_MAX; +} =20 static inline bool guest_range_valid(abi_ulong start, abi_ulong len) { --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613049531; cv=none; d=zohomail.com; s=zohoarc; b=HVrqlACtVmfbzZsiXUNpPPEZmI+lGJDhnHTHBRAYisgmDeVPFr3jSgTVnQOAQZuM/OiAWeVWSp7MYzCG2CrlZ+/QN9hLDHOZd51EuCI8iy2yr6/yyy9rJUvzYYLmlGYeZsiAgFCxAPuZZor8ogXQprv+5f0ISLYmh02zGxqZnNY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613049531; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=C5mj6NRrt0u/DreoETKEeLg2CeSxNg+EEqC7ggdCjng=; b=bFZsT2oGyjbMEn8WgJM3rINwfMwPTp5bvF+oPNGirwFw/jDGAz8cA3kA2DmXSt0wgsNA00JkeFNhTyP6iq01lgGhGHObQvQkkQnlXnliZbqivVermhJ43JnlCGwI8TDh3BaqYnk3PkxeBQAPQx+/FfyC65g0oz/DvExAOGPFbUU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613049531126239.96507663654006; Thu, 11 Feb 2021 05:18:51 -0800 (PST) Received: from localhost ([::1]:36918 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lABru-0006lg-0K for importer@patchew.org; Thu, 11 Feb 2021 08:18:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33474) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZ2-0008DK-DI for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:20 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:40798) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZ0-0008T8-Oi for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:20 -0500 Received: by mail-wr1-x435.google.com with SMTP id v14so4071490wro.7 for ; Thu, 11 Feb 2021 04:59:18 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=C5mj6NRrt0u/DreoETKEeLg2CeSxNg+EEqC7ggdCjng=; b=itf6PiAiojqn65r7+GKQsdtqZBz2FHfuvdH5k5NvkQ4MJyqTVj1qDeCBnt2TfxIiHz F8zWDpMjqa1+YS74YG+ufegp8dV4k0LUNYoBQquZ8ALJ/Gbc/H+OXAEhVCSyZo7fDTXB jw9c1OHi7YmvZv0AIhcKM01SSnzCsh4JKMFgKWBr9sfEBV8yped4wLZb0PDE4PlycVIc dYClkclw8+JaM0CTQZY4f+cMWyhmf5DeIkmMLawj7z4awolhT/Kh1k5lG/wD6/akob67 orpheQfkkUr3VEcDbaHrS+NjKdpdZlQgqG8tOHjcDT4DF/TpFLFZWe8DY+y4+9ni9rjP 9p6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=C5mj6NRrt0u/DreoETKEeLg2CeSxNg+EEqC7ggdCjng=; b=AcRgy+4Zp8ixor8G0iRdm64/YUCShBpxiTLlASyhfMnyOcO65sHnM5kQYlWSP4yLng Cd4ZLotbh6aJV+dijrZKvJXfTjBjWr/Y2MdTHbOCihJKC+PDXKe6aeSd9ebcrcIm/JVG RHRAbZZL7X+Avg8nNtpMaPzWlLm7uh8/k7hb0bdnnieoldZCAVmKfafZaOrNl+HL+7/h EnDrhtYPtPTROsMttJ5XLQ0KK1pw1AyvbCy38P517UNjeWnst0loeGMBdJ3LrZ8Iflvx +p17gvBsn2kVW6TtkU6V8u+738JppvtqpypkhqY9DXTeSCrR/egV6C4fHruJl08hDzRv V4kA== X-Gm-Message-State: AOAM5330rDT7WIGACcnuuUbvLWzPS/hL36mkHzlCXCtWpimkfJrsyPjr sUbDFX/Filh2Ki5NFAaZFRjMZ/ZZnETvFw== X-Google-Smtp-Source: ABdhPJxemAGwdzCxfbeZY3UNAbSJi9NDPnHoDlJwMWELDmXSzKhc24NpoFHooBw30UowQ8PaXkjx9Q== X-Received: by 2002:a5d:4a0b:: with SMTP id m11mr5770958wrq.51.1613048357431; Thu, 11 Feb 2021 04:59:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/45] exec: Introduce cpu_untagged_addr Date: Thu, 11 Feb 2021 12:58:35 +0000 Message-Id: <20210211125900.22777-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Provide an identity fallback for target that do not use tagged addresses. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu_ldst.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index e62f4fba001..d9dc1de414a 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -69,6 +69,13 @@ typedef uint64_t abi_ptr; #define TARGET_ABI_FMT_ptr "%"PRIx64 #endif =20 +#ifndef TARGET_TAGGED_ADDRESSES +static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x) +{ + return x; +} +#endif + /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ #define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) =20 --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050116; cv=none; d=zohomail.com; s=zohoarc; b=DvMVTVi8p8LAa5PZdu4hn4YW1rueR5HjV3hDsg/Dy82jgCZXRMMXAK6dXXJANvdPTMCuSHt7wk7YjbWRRz1YCV7nN3lX3AGj7/g/MVayjIuIe7g9WVK1yPpkKnz5wM+ml6o+9aRFDkn7059h9Xi0MuMnv6EHhcv2/cyrhtiQ+w4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613050116; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bGQeqrPNRMWUIPWlWl33MFFZXZ8RP3UvtHo5HLflpTo=; b=PL1tCOImfuJHixGwbCx+vZs1pkRmFNyiwB0C+8DAhEWSRX1jVTZWiuRhIfXJCRP1C/yX9PJURmoGvOX2lst0B7Aa9zK8lgfOUnOBpt3pgRvOJ/KvLv1oJVEhfKr24vimKBDpDOnjpOpYqlmmE6QDHzaOZECmdDO9sYLFRg+0iMY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613050116196560.4811333668862; Thu, 11 Feb 2021 05:28:36 -0800 (PST) Received: from localhost ([::1]:60420 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lAC1K-0000mB-Rm for importer@patchew.org; Thu, 11 Feb 2021 08:28:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33574) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZ8-0008IY-Kr for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:27 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:37998) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZ2-0008UM-Vr for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:26 -0500 Received: by mail-wm1-x330.google.com with SMTP id y134so5659465wmd.3 for ; Thu, 11 Feb 2021 04:59:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bGQeqrPNRMWUIPWlWl33MFFZXZ8RP3UvtHo5HLflpTo=; b=TVjjXcpTnNbMRW+GMls76FKhJKuzpf8eNSarnkdUPqJzbAZiiWqUtmv5c3uTUV/rR3 Q70ro6DlE+yAZ1dpvecPgON1jaACcsrXS03lWcLbc9ZLGNr+c3VikrCfMSKFOf0pU2qa d/X6cM//Umvcgbvj0rRi9K0TeesHL3lyRDBp/otgDzDQhknVfZ3nabyRK2pMYlHTdaxb i6px46Zo4ixK5utodl2i4FOe/JZXBMY0jwUvOQIo52mUChSzP9wTnsNujcabiGi01tGg /jdNa1yGC7BoxKBC0zYbbcLq8H99ME1WTwFryBejRsTPeGZwVXkH30JL6s5VFflhx26l 6IlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bGQeqrPNRMWUIPWlWl33MFFZXZ8RP3UvtHo5HLflpTo=; b=Ubj9jMLIPKcVUDl8TEobM/bBktvkXXYRhTWSWYQY/0ilUHKVNkjC+HcnNmmqqepudK iUHWva0WY0nWUOjM1sV0ucZ4z0+c64rAEXZUoeoBk5gFwvOc10CURJqZn/A7yr0sl8yC 3n+IW3/dRFc76tYXIEqX+RdzNJ7Jknv7pS95CooVsWDa6OzpUyatBwDbucIydEFLxpjc u2VK1eJbXIbHUFqnqEAdC5cAzfigZCHfmI8uIUnhAU3UBfDexsQ6s+AhH0yueGKf4TN5 CT0WomRz5TYa+TpFazudm0mSUqsnNEHAFnfky26Pte8VNpBA3lGvxGHGT7bR3G3WcPUB ftDQ== X-Gm-Message-State: AOAM532egK39PIIbIuSi7POvcRi4RbmVVFb8DOSX3QzZOR4YaZPeNhUu cIgc+n0UJI21306pK7Anug+KF+3jPLEovQ== X-Google-Smtp-Source: ABdhPJwQ9Eu/IllLMwj8K/rZg8xT+igThJcRN86GybkoZI6IDyXp8l8ePG9YQ/5Ur8wA5JblpPvfYg== X-Received: by 2002:a1c:20c7:: with SMTP id g190mr4959640wmg.156.1613048359021; Thu, 11 Feb 2021 04:59:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/45] exec: Use cpu_untagged_addr in g2h; split out g2h_untagged Date: Thu, 11 Feb 2021 12:58:36 +0000 Message-Id: <20210211125900.22777-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use g2h_untagged in contexts that have no cpu, e.g. the binary loaders that operate before the primary cpu is created. As a colollary, target_mmap and friends must use untagged addresses, since they are used by the loaders. Use g2h_untagged on values returned from target_mmap, as the kernel never applies a tag itself. Use g2h_untagged on all pc values. The only current user of tags, aarch64, removes tags from code addresses upon branch, so "pc" is always untagged. Use g2h with the cpu context on hand wherever possible. Use g2h_untagged in lock_user, which will be updated soon. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu_ldst.h | 12 +++++- include/exec/exec-all.h | 2 +- linux-user/qemu.h | 6 +-- accel/tcg/translate-all.c | 4 +- accel/tcg/user-exec.c | 48 ++++++++++++------------ linux-user/elfload.c | 12 +++--- linux-user/flatload.c | 2 +- linux-user/hppa/cpu_loop.c | 31 ++++++++-------- linux-user/i386/cpu_loop.c | 4 +- linux-user/mmap.c | 45 +++++++++++----------- linux-user/ppc/signal.c | 4 +- linux-user/syscall.c | 72 +++++++++++++++++++----------------- target/arm/helper-a64.c | 4 +- target/hppa/op_helper.c | 2 +- target/i386/tcg/mem_helper.c | 2 +- target/s390x/mem_helper.c | 4 +- 16 files changed, 135 insertions(+), 119 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index d9dc1de414a..c54069e3cd0 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -77,7 +77,15 @@ static inline abi_ptr cpu_untagged_addr(CPUState *cs, ab= i_ptr x) #endif =20 /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ -#define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) +static inline void *g2h_untagged(abi_ptr x) +{ + return (void *)((uintptr_t)(x) + guest_base); +} + +static inline void *g2h(CPUState *cs, abi_ptr x) +{ + return g2h_untagged(cpu_untagged_addr(cs, x)); +} =20 static inline bool guest_addr_valid(abi_ulong x) { @@ -448,7 +456,7 @@ static inline int cpu_ldsw_code(CPUArchState *env, abi_= ptr addr) static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, MMUAccessType access_type, int mmu_i= dx) { - return g2h(addr); + return g2h(env_cpu(env), addr); } #else void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f933c74c446..d30c7a84f6a 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -616,7 +616,7 @@ static inline tb_page_addr_t get_page_addr_code_hostp(C= PUArchState *env, void **hostp) { if (hostp) { - *hostp =3D g2h(addr); + *hostp =3D g2h_untagged(addr); } return addr; } diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 9251337daf2..9fbc5edc4bd 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -652,7 +652,7 @@ static inline void *lock_user(int type, abi_ulong guest= _addr, long len, int copy return addr; } #else - return g2h(guest_addr); + return g2h_untagged(guest_addr); #endif } =20 @@ -666,10 +666,10 @@ static inline void unlock_user(void *host_ptr, abi_ul= ong guest_addr, #ifdef DEBUG_REMAP if (!host_ptr) return; - if (host_ptr =3D=3D g2h(guest_addr)) + if (host_ptr =3D=3D g2h_untagged(guest_addr)) return; if (len > 0) - memcpy(g2h(guest_addr), host_ptr, len); + memcpy(g2h_untagged(guest_addr), host_ptr, len); g_free(host_ptr); #endif } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bba9c8e0b3e..2c34adccce5 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1762,7 +1762,7 @@ static inline void tb_page_add(PageDesc *p, Translati= onBlock *tb, prot |=3D p2->flags; p2->flags &=3D ~PAGE_WRITE; } - mprotect(g2h(page_addr), qemu_host_page_size, + mprotect(g2h_untagged(page_addr), qemu_host_page_size, (prot & PAGE_BITS) & ~PAGE_WRITE); if (DEBUG_TB_INVALIDATE_GATE) { printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_= addr); @@ -2912,7 +2912,7 @@ int page_unprotect(target_ulong address, uintptr_t pc) } #endif } - mprotect((void *)g2h(host_start), qemu_host_page_size, + mprotect((void *)g2h_untagged(host_start), qemu_host_page_size, prot & PAGE_BITS); } mmap_unlock(); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 0b6f56ca407..fa1847b2a61 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -234,7 +234,7 @@ int probe_access_flags(CPUArchState *env, target_ulong = addr, int flags; =20 flags =3D probe_access_internal(env, addr, 0, access_type, nonfault, r= a); - *phost =3D flags ? NULL : g2h(addr); + *phost =3D flags ? NULL : g2h(env_cpu(env), addr); return flags; } =20 @@ -247,7 +247,7 @@ void *probe_access(CPUArchState *env, target_ulong addr= , int size, flags =3D probe_access_internal(env, addr, size, access_type, false, r= a); g_assert(flags =3D=3D 0); =20 - return size ? g2h(addr) : NULL; + return size ? g2h(env_cpu(env), addr) : NULL; } =20 #if defined(__i386__) @@ -842,7 +842,7 @@ uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo =3D trace_mem_get_info(MO_UB, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldub_p(g2h(ptr)); + ret =3D ldub_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -853,7 +853,7 @@ int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo =3D trace_mem_get_info(MO_SB, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldsb_p(g2h(ptr)); + ret =3D ldsb_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -864,7 +864,7 @@ uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr pt= r) uint16_t meminfo =3D trace_mem_get_info(MO_BEUW, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D lduw_be_p(g2h(ptr)); + ret =3D lduw_be_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -875,7 +875,7 @@ int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo =3D trace_mem_get_info(MO_BESW, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldsw_be_p(g2h(ptr)); + ret =3D ldsw_be_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -886,7 +886,7 @@ uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo =3D trace_mem_get_info(MO_BEUL, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldl_be_p(g2h(ptr)); + ret =3D ldl_be_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -897,7 +897,7 @@ uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo =3D trace_mem_get_info(MO_BEQ, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldq_be_p(g2h(ptr)); + ret =3D ldq_be_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -908,7 +908,7 @@ uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr pt= r) uint16_t meminfo =3D trace_mem_get_info(MO_LEUW, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D lduw_le_p(g2h(ptr)); + ret =3D lduw_le_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -919,7 +919,7 @@ int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo =3D trace_mem_get_info(MO_LESW, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldsw_le_p(g2h(ptr)); + ret =3D ldsw_le_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -930,7 +930,7 @@ uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo =3D trace_mem_get_info(MO_LEUL, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldl_le_p(g2h(ptr)); + ret =3D ldl_le_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -941,7 +941,7 @@ uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo =3D trace_mem_get_info(MO_LEQ, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldq_le_p(g2h(ptr)); + ret =3D ldq_le_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; } @@ -1051,7 +1051,7 @@ void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uin= t32_t val) uint16_t meminfo =3D trace_mem_get_info(MO_UB, MMU_USER_IDX, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - stb_p(g2h(ptr), val); + stb_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } =20 @@ -1060,7 +1060,7 @@ void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) uint16_t meminfo =3D trace_mem_get_info(MO_BEUW, MMU_USER_IDX, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - stw_be_p(g2h(ptr), val); + stw_be_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } =20 @@ -1069,7 +1069,7 @@ void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) uint16_t meminfo =3D trace_mem_get_info(MO_BEUL, MMU_USER_IDX, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - stl_be_p(g2h(ptr), val); + stl_be_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } =20 @@ -1078,7 +1078,7 @@ void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, = uint64_t val) uint16_t meminfo =3D trace_mem_get_info(MO_BEQ, MMU_USER_IDX, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - stq_be_p(g2h(ptr), val); + stq_be_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } =20 @@ -1087,7 +1087,7 @@ void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) uint16_t meminfo =3D trace_mem_get_info(MO_LEUW, MMU_USER_IDX, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - stw_le_p(g2h(ptr), val); + stw_le_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } =20 @@ -1096,7 +1096,7 @@ void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) uint16_t meminfo =3D trace_mem_get_info(MO_LEUL, MMU_USER_IDX, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - stl_le_p(g2h(ptr), val); + stl_le_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } =20 @@ -1105,7 +1105,7 @@ void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, = uint64_t val) uint16_t meminfo =3D trace_mem_get_info(MO_LEQ, MMU_USER_IDX, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - stq_le_p(g2h(ptr), val); + stq_le_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } =20 @@ -1170,7 +1170,7 @@ uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr) uint32_t ret; =20 set_helper_retaddr(1); - ret =3D ldub_p(g2h(ptr)); + ret =3D ldub_p(g2h_untagged(ptr)); clear_helper_retaddr(); return ret; } @@ -1180,7 +1180,7 @@ uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr ptr) uint32_t ret; =20 set_helper_retaddr(1); - ret =3D lduw_p(g2h(ptr)); + ret =3D lduw_p(g2h_untagged(ptr)); clear_helper_retaddr(); return ret; } @@ -1190,7 +1190,7 @@ uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr ptr) uint32_t ret; =20 set_helper_retaddr(1); - ret =3D ldl_p(g2h(ptr)); + ret =3D ldl_p(g2h_untagged(ptr)); clear_helper_retaddr(); return ret; } @@ -1200,7 +1200,7 @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr) uint64_t ret; =20 set_helper_retaddr(1); - ret =3D ldq_p(g2h(ptr)); + ret =3D ldq_p(g2h_untagged(ptr)); clear_helper_retaddr(); return ret; } @@ -1213,7 +1213,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, if (unlikely(addr & (size - 1))) { cpu_loop_exit_atomic(env_cpu(env), retaddr); } - void *ret =3D g2h(addr); + void *ret =3D g2h(env_cpu(env), addr); set_helper_retaddr(retaddr); return ret; } diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 29f07bb2346..f542841ba24 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -389,7 +389,7 @@ enum { =20 static bool init_guest_commpage(void) { - void *want =3D g2h(ARM_COMMPAGE & -qemu_host_page_size); + void *want =3D g2h_untagged(ARM_COMMPAGE & -qemu_host_page_size); void *addr =3D mmap(want, qemu_host_page_size, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE | MAP_FIXED, -1, 0); =20 @@ -402,7 +402,7 @@ static bool init_guest_commpage(void) } =20 /* Set kernel helper versions; rest of page is 0. */ - __put_user(5, (uint32_t *)g2h(0xffff0ffcu)); + __put_user(5, (uint32_t *)g2h_untagged(0xffff0ffcu)); =20 if (mprotect(addr, qemu_host_page_size, PROT_READ)) { perror("Protecting guest commpage"); @@ -1872,8 +1872,8 @@ static void zero_bss(abi_ulong elf_bss, abi_ulong las= t_bss, int prot) here is still actually needed. For now, continue with it, but merge it with the "normal" mmap that would allocate the bss. */ =20 - host_start =3D (uintptr_t) g2h(elf_bss); - host_end =3D (uintptr_t) g2h(last_bss); + host_start =3D (uintptr_t) g2h_untagged(elf_bss); + host_end =3D (uintptr_t) g2h_untagged(last_bss); host_map_start =3D REAL_HOST_PAGE_ALIGN(host_start); =20 if (host_map_start < host_end) { @@ -2171,7 +2171,7 @@ static void pgb_have_guest_base(const char *image_nam= e, abi_ulong guest_loaddr, } =20 /* Reserve the address space for the binary, or reserved_va. */ - test =3D g2h(guest_loaddr); + test =3D g2h_untagged(guest_loaddr); addr =3D mmap(test, guest_hiaddr - guest_loaddr, PROT_NONE, flags, -1,= 0); if (test !=3D addr) { pgb_fail_in_use(image_name); @@ -2393,7 +2393,7 @@ static void pgb_reserved_va(const char *image_name, a= bi_ulong guest_loaddr, =20 /* Reserve the memory on the host. */ assert(guest_base !=3D 0); - test =3D g2h(0); + test =3D g2h_untagged(0); addr =3D mmap(test, reserved_va, PROT_NONE, flags, -1, 0); if (addr =3D=3D MAP_FAILED || addr !=3D test) { error_report("Unable to reserve 0x%lx bytes of virtual address " diff --git a/linux-user/flatload.c b/linux-user/flatload.c index 14d2999d153..3e5594cf894 100644 --- a/linux-user/flatload.c +++ b/linux-user/flatload.c @@ -668,7 +668,7 @@ static int load_flat_file(struct linux_binprm * bprm, } =20 /* zero the BSS. */ - memset(g2h(datapos + data_len), 0, bss_len); + memset(g2h_untagged(datapos + data_len), 0, bss_len); =20 return 0; } diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index d7e1ec77220..944511bbe43 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -23,6 +23,7 @@ =20 static abi_ulong hppa_lws(CPUHPPAState *env) { + CPUState *cs =3D env_cpu(env); uint32_t which =3D env->gr[20]; abi_ulong addr =3D env->gr[26]; abi_ulong old =3D env->gr[25]; @@ -39,7 +40,7 @@ static abi_ulong hppa_lws(CPUHPPAState *env) } old =3D tswap32(old); new =3D tswap32(new); - ret =3D qatomic_cmpxchg((uint32_t *)g2h(addr), old, new); + ret =3D qatomic_cmpxchg((uint32_t *)g2h(cs, addr), old, new); ret =3D tswap32(ret); break; =20 @@ -58,38 +59,38 @@ static abi_ulong hppa_lws(CPUHPPAState *env) can be host-endian as well. */ switch (size) { case 0: - old =3D *(uint8_t *)g2h(old); - new =3D *(uint8_t *)g2h(new); - ret =3D qatomic_cmpxchg((uint8_t *)g2h(addr), old, new); + old =3D *(uint8_t *)g2h(cs, old); + new =3D *(uint8_t *)g2h(cs, new); + ret =3D qatomic_cmpxchg((uint8_t *)g2h(cs, addr), old, new); ret =3D ret !=3D old; break; case 1: - old =3D *(uint16_t *)g2h(old); - new =3D *(uint16_t *)g2h(new); - ret =3D qatomic_cmpxchg((uint16_t *)g2h(addr), old, new); + old =3D *(uint16_t *)g2h(cs, old); + new =3D *(uint16_t *)g2h(cs, new); + ret =3D qatomic_cmpxchg((uint16_t *)g2h(cs, addr), old, new); ret =3D ret !=3D old; break; case 2: - old =3D *(uint32_t *)g2h(old); - new =3D *(uint32_t *)g2h(new); - ret =3D qatomic_cmpxchg((uint32_t *)g2h(addr), old, new); + old =3D *(uint32_t *)g2h(cs, old); + new =3D *(uint32_t *)g2h(cs, new); + ret =3D qatomic_cmpxchg((uint32_t *)g2h(cs, addr), old, new); ret =3D ret !=3D old; break; case 3: { uint64_t o64, n64, r64; - o64 =3D *(uint64_t *)g2h(old); - n64 =3D *(uint64_t *)g2h(new); + o64 =3D *(uint64_t *)g2h(cs, old); + n64 =3D *(uint64_t *)g2h(cs, new); #ifdef CONFIG_ATOMIC64 - r64 =3D qatomic_cmpxchg__nocheck((uint64_t *)g2h(addr), + r64 =3D qatomic_cmpxchg__nocheck((uint64_t *)g2h(cs, addr), o64, n64); ret =3D r64 !=3D o64; #else start_exclusive(); - r64 =3D *(uint64_t *)g2h(addr); + r64 =3D *(uint64_t *)g2h(cs, addr); ret =3D 1; if (r64 =3D=3D o64) { - *(uint64_t *)g2h(addr) =3D n64; + *(uint64_t *)g2h(cs, addr) =3D n64; ret =3D 0; } end_exclusive(); diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index 70cde417e60..19c8a18cd30 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -379,7 +379,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) env->idt.base =3D target_mmap(0, sizeof(uint64_t) * (env->idt.limit + = 1), PROT_READ|PROT_WRITE, MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); - idt_table =3D g2h(env->idt.base); + idt_table =3D g2h_untagged(env->idt.base); set_idt(0, 0); set_idt(1, 0); set_idt(2, 0); @@ -409,7 +409,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) PROT_READ|PROT_WRITE, MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); env->gdt.limit =3D sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; - gdt_table =3D g2h(env->gdt.base); + gdt_table =3D g2h_untagged(env->gdt.base); #ifdef TARGET_ABI32 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 7fb4c628e11..088c50592cf 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -141,7 +141,7 @@ int target_mprotect(abi_ulong start, abi_ulong len, int= target_prot) } end =3D host_end; } - ret =3D mprotect(g2h(host_start), qemu_host_page_size, + ret =3D mprotect(g2h_untagged(host_start), qemu_host_page_size, prot1 & PAGE_BITS); if (ret !=3D 0) { goto error; @@ -153,7 +153,7 @@ int target_mprotect(abi_ulong start, abi_ulong len, int= target_prot) for (addr =3D end; addr < host_end; addr +=3D TARGET_PAGE_SIZE) { prot1 |=3D page_get_flags(addr); } - ret =3D mprotect(g2h(host_end - qemu_host_page_size), + ret =3D mprotect(g2h_untagged(host_end - qemu_host_page_size), qemu_host_page_size, prot1 & PAGE_BITS); if (ret !=3D 0) { goto error; @@ -163,7 +163,8 @@ int target_mprotect(abi_ulong start, abi_ulong len, int= target_prot) =20 /* handle the pages in the middle */ if (host_start < host_end) { - ret =3D mprotect(g2h(host_start), host_end - host_start, host_prot= ); + ret =3D mprotect(g2h_untagged(host_start), + host_end - host_start, host_prot); if (ret !=3D 0) { goto error; } @@ -186,7 +187,7 @@ static int mmap_frag(abi_ulong real_start, int prot1, prot_new; =20 real_end =3D real_start + qemu_host_page_size; - host_start =3D g2h(real_start); + host_start =3D g2h_untagged(real_start); =20 /* get the protection of the target pages outside the mapping */ prot1 =3D 0; @@ -218,7 +219,7 @@ static int mmap_frag(abi_ulong real_start, mprotect(host_start, qemu_host_page_size, prot1 | PROT_WRITE); =20 /* read the corresponding file data */ - if (pread(fd, g2h(start), end - start, offset) =3D=3D -1) + if (pread(fd, g2h_untagged(start), end - start, offset) =3D=3D -1) return -1; =20 /* put final protection */ @@ -229,7 +230,7 @@ static int mmap_frag(abi_ulong real_start, mprotect(host_start, qemu_host_page_size, prot_new); } if (prot_new & PROT_WRITE) { - memset(g2h(start), 0, end - start); + memset(g2h_untagged(start), 0, end - start); } } return 0; @@ -338,7 +339,7 @@ abi_ulong mmap_find_vma(abi_ulong start, abi_ulong size= , abi_ulong align) * - mremap() with MREMAP_FIXED flag * - shmat() with SHM_REMAP flag */ - ptr =3D mmap(g2h(addr), size, PROT_NONE, + ptr =3D mmap(g2h_untagged(addr), size, PROT_NONE, MAP_ANONYMOUS|MAP_PRIVATE|MAP_NORESERVE, -1, 0); =20 /* ENOMEM, if host address space has no memory */ @@ -497,7 +498,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, in= t target_prot, /* Note: we prefer to control the mapping address. It is especially important if qemu_host_page_size > qemu_real_host_page_size */ - p =3D mmap(g2h(start), host_len, host_prot, + p =3D mmap(g2h_untagged(start), host_len, host_prot, flags | MAP_FIXED | MAP_ANONYMOUS, -1, 0); if (p =3D=3D MAP_FAILED) { goto fail; @@ -505,10 +506,10 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, = int target_prot, /* update start so that it points to the file position at 'offset'= */ host_start =3D (unsigned long)p; if (!(flags & MAP_ANONYMOUS)) { - p =3D mmap(g2h(start), len, host_prot, + p =3D mmap(g2h_untagged(start), len, host_prot, flags | MAP_FIXED, fd, host_offset); if (p =3D=3D MAP_FAILED) { - munmap(g2h(start), host_len); + munmap(g2h_untagged(start), host_len); goto fail; } host_start +=3D offset - host_offset; @@ -548,7 +549,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, in= t target_prot, -1, 0); if (retaddr =3D=3D -1) goto fail; - if (pread(fd, g2h(start), len, offset) =3D=3D -1) + if (pread(fd, g2h_untagged(start), len, offset) =3D=3D -1) goto fail; if (!(host_prot & PROT_WRITE)) { ret =3D target_mprotect(start, len, target_prot); @@ -592,7 +593,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, in= t target_prot, offset1 =3D 0; else offset1 =3D offset + real_start - start; - p =3D mmap(g2h(real_start), real_end - real_start, + p =3D mmap(g2h_untagged(real_start), real_end - real_start, host_prot, flags, fd, offset1); if (p =3D=3D MAP_FAILED) goto fail; @@ -652,7 +653,7 @@ static void mmap_reserve(abi_ulong start, abi_ulong siz= e) real_end -=3D qemu_host_page_size; } if (real_start !=3D real_end) { - mmap(g2h(real_start), real_end - real_start, PROT_NONE, + mmap(g2h_untagged(real_start), real_end - real_start, PROT_NONE, MAP_FIXED | MAP_ANONYMOUS | MAP_PRIVATE | MAP_NORESERVE, -1, 0); } @@ -707,7 +708,7 @@ int target_munmap(abi_ulong start, abi_ulong len) if (reserved_va) { mmap_reserve(real_start, real_end - real_start); } else { - ret =3D munmap(g2h(real_start), real_end - real_start); + ret =3D munmap(g2h_untagged(real_start), real_end - real_start= ); } } =20 @@ -736,8 +737,8 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong ol= d_size, mmap_lock(); =20 if (flags & MREMAP_FIXED) { - host_addr =3D mremap(g2h(old_addr), old_size, new_size, - flags, g2h(new_addr)); + host_addr =3D mremap(g2h_untagged(old_addr), old_size, new_size, + flags, g2h_untagged(new_addr)); =20 if (reserved_va && host_addr !=3D MAP_FAILED) { /* If new and old addresses overlap then the above mremap will @@ -753,8 +754,9 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong ol= d_size, errno =3D ENOMEM; host_addr =3D MAP_FAILED; } else { - host_addr =3D mremap(g2h(old_addr), old_size, new_size, - flags | MREMAP_FIXED, g2h(mmap_start)); + host_addr =3D mremap(g2h_untagged(old_addr), old_size, new_siz= e, + flags | MREMAP_FIXED, + g2h_untagged(mmap_start)); if (reserved_va) { mmap_reserve(old_addr, old_size); } @@ -770,14 +772,15 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong = old_size, } } if (prot =3D=3D 0) { - host_addr =3D mremap(g2h(old_addr), old_size, new_size, flags); + host_addr =3D mremap(g2h_untagged(old_addr), + old_size, new_size, flags); =20 if (host_addr !=3D MAP_FAILED) { /* Check if address fits target address space */ if (!guest_range_valid(h2g(host_addr), new_size)) { /* Revert mremap() changes */ - host_addr =3D mremap(g2h(old_addr), new_size, old_size, - flags); + host_addr =3D mremap(g2h_untagged(old_addr), + new_size, old_size, flags); errno =3D ENOMEM; host_addr =3D MAP_FAILED; } else if (reserved_va && old_size > new_size) { diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c index 20a02c197cb..b78613f7c86 100644 --- a/linux-user/ppc/signal.c +++ b/linux-user/ppc/signal.c @@ -365,7 +365,7 @@ static void restore_user_regs(CPUPPCState *env, uint64_t v_addr; /* 64-bit needs to recover the pointer to the vectors from the fra= me */ __get_user(v_addr, &frame->v_regs); - v_regs =3D g2h(v_addr); + v_regs =3D g2h(env_cpu(env), v_addr); #else v_regs =3D (ppc_avr_t *)frame->mc_vregs.altivec; #endif @@ -552,7 +552,7 @@ void setup_rt_frame(int sig, struct target_sigaction *k= a, if (get_ppc64_abi(image) < 2) { /* ELFv1 PPC64 function pointers are pointers to OPD entries. */ struct target_func_ptr *handler =3D - (struct target_func_ptr *)g2h(ka->_sa_handler); + (struct target_func_ptr *)g2h(env_cpu(env), ka->_sa_handler); env->nip =3D tswapl(handler->entry); env->gpr[2] =3D tswapl(handler->toc); } else { diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 6001022e968..748893904e3 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -907,7 +907,7 @@ abi_long do_brk(abi_ulong new_brk) /* Heap contents are initialized to zero, as for anonymous * mapped pages. */ if (new_brk > target_brk) { - memset(g2h(target_brk), 0, new_brk - target_brk); + memset(g2h_untagged(target_brk), 0, new_brk - target_brk); } target_brk =3D new_brk; DEBUGF_BRK(TARGET_ABI_FMT_lx " (new_brk <=3D brk_page)\n", target_= brk); @@ -933,7 +933,7 @@ abi_long do_brk(abi_ulong new_brk) * come from the remaining part of the previous page: it may * contains garbage data due to a previous heap usage (grown * then shrunken). */ - memset(g2h(target_brk), 0, brk_page - target_brk); + memset(g2h_untagged(target_brk), 0, brk_page - target_brk); =20 target_brk =3D new_brk; brk_page =3D HOST_PAGE_ALIGN(target_brk); @@ -4611,7 +4611,7 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_en= v, mmap_lock(); =20 if (shmaddr) - host_raddr =3D shmat(shmid, (void *)g2h(shmaddr), shmflg); + host_raddr =3D shmat(shmid, (void *)g2h_untagged(shmaddr), shmflg); else { abi_ulong mmap_start; =20 @@ -4622,7 +4622,8 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_en= v, errno =3D ENOMEM; host_raddr =3D (void *)-1; } else - host_raddr =3D shmat(shmid, g2h(mmap_start), shmflg | SHM_REMA= P); + host_raddr =3D shmat(shmid, g2h_untagged(mmap_start), + shmflg | SHM_REMAP); } =20 if (host_raddr =3D=3D (void *)-1) { @@ -4663,7 +4664,7 @@ static inline abi_long do_shmdt(abi_ulong shmaddr) break; } } - rv =3D get_errno(shmdt(g2h(shmaddr))); + rv =3D get_errno(shmdt(g2h_untagged(shmaddr))); =20 mmap_unlock(); =20 @@ -6133,10 +6134,10 @@ static abi_long write_ldt(CPUX86State *env, MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); if (env->ldt.base =3D=3D -1) return -TARGET_ENOMEM; - memset(g2h(env->ldt.base), 0, + memset(g2h_untagged(env->ldt.base), 0, TARGET_LDT_ENTRIES * TARGET_LDT_ENTRY_SIZE); env->ldt.limit =3D 0xffff; - ldt_table =3D g2h(env->ldt.base); + ldt_table =3D g2h_untagged(env->ldt.base); } =20 /* NOTE: same code as Linux kernel */ @@ -6204,7 +6205,7 @@ static abi_long do_modify_ldt(CPUX86State *env, int f= unc, abi_ulong ptr, #if defined(TARGET_ABI32) abi_long do_set_thread_area(CPUX86State *env, abi_ulong ptr) { - uint64_t *gdt_table =3D g2h(env->gdt.base); + uint64_t *gdt_table =3D g2h_untagged(env->gdt.base); struct target_modify_ldt_ldt_s ldt_info; struct target_modify_ldt_ldt_s *target_ldt_info; int seg_32bit, contents, read_exec_only, limit_in_pages; @@ -6290,7 +6291,7 @@ install: static abi_long do_get_thread_area(CPUX86State *env, abi_ulong ptr) { struct target_modify_ldt_ldt_s *target_ldt_info; - uint64_t *gdt_table =3D g2h(env->gdt.base); + uint64_t *gdt_table =3D g2h_untagged(env->gdt.base); uint32_t base_addr, limit, flags; int seg_32bit, contents, read_exec_only, limit_in_pages, idx; int seg_not_present, useable, lm; @@ -7585,8 +7586,8 @@ static int do_safe_futex(int *uaddr, int op, int val, tricky. However they're probably useless because guest atomic operations won't work either. */ #if defined(TARGET_NR_futex) -static int do_futex(target_ulong uaddr, int op, int val, target_ulong time= out, - target_ulong uaddr2, int val3) +static int do_futex(CPUState *cpu, target_ulong uaddr, int op, int val, + target_ulong timeout, target_ulong uaddr2, int val3) { struct timespec ts, *pts; int base_op; @@ -7607,11 +7608,14 @@ static int do_futex(target_ulong uaddr, int op, int= val, target_ulong timeout, } else { pts =3D NULL; } - return do_safe_futex(g2h(uaddr), op, tswap32(val), pts, NULL, val3= ); + return do_safe_futex(g2h(cpu, uaddr), + op, tswap32(val), pts, NULL, val3); case FUTEX_WAKE: - return do_safe_futex(g2h(uaddr), op, val, NULL, NULL, 0); + return do_safe_futex(g2h(cpu, uaddr), + op, val, NULL, NULL, 0); case FUTEX_FD: - return do_safe_futex(g2h(uaddr), op, val, NULL, NULL, 0); + return do_safe_futex(g2h(cpu, uaddr), + op, val, NULL, NULL, 0); case FUTEX_REQUEUE: case FUTEX_CMP_REQUEUE: case FUTEX_WAKE_OP: @@ -7621,10 +7625,9 @@ static int do_futex(target_ulong uaddr, int op, int = val, target_ulong timeout, to satisfy the compiler. We do not need to tswap TIMEOUT since it's not compared to guest memory. */ pts =3D (struct timespec *)(uintptr_t) timeout; - return do_safe_futex(g2h(uaddr), op, val, pts, g2h(uaddr2), + return do_safe_futex(g2h(cpu, uaddr), op, val, pts, g2h(cpu, uaddr= 2), (base_op =3D=3D FUTEX_CMP_REQUEUE - ? tswap32(val3) - : val3)); + ? tswap32(val3) : val3)); default: return -TARGET_ENOSYS; } @@ -7632,7 +7635,8 @@ static int do_futex(target_ulong uaddr, int op, int v= al, target_ulong timeout, #endif =20 #if defined(TARGET_NR_futex_time64) -static int do_futex_time64(target_ulong uaddr, int op, int val, target_ulo= ng timeout, +static int do_futex_time64(CPUState *cpu, target_ulong uaddr, int op, + int val, target_ulong timeout, target_ulong uaddr2, int val3) { struct timespec ts, *pts; @@ -7656,11 +7660,12 @@ static int do_futex_time64(target_ulong uaddr, int = op, int val, target_ulong tim } else { pts =3D NULL; } - return do_safe_futex(g2h(uaddr), op, tswap32(val), pts, NULL, val3= ); + return do_safe_futex(g2h(cpu, uaddr), op, + tswap32(val), pts, NULL, val3); case FUTEX_WAKE: - return do_safe_futex(g2h(uaddr), op, val, NULL, NULL, 0); + return do_safe_futex(g2h(cpu, uaddr), op, val, NULL, NULL, 0); case FUTEX_FD: - return do_safe_futex(g2h(uaddr), op, val, NULL, NULL, 0); + return do_safe_futex(g2h(cpu, uaddr), op, val, NULL, NULL, 0); case FUTEX_REQUEUE: case FUTEX_CMP_REQUEUE: case FUTEX_WAKE_OP: @@ -7670,10 +7675,9 @@ static int do_futex_time64(target_ulong uaddr, int o= p, int val, target_ulong tim to satisfy the compiler. We do not need to tswap TIMEOUT since it's not compared to guest memory. */ pts =3D (struct timespec *)(uintptr_t) timeout; - return do_safe_futex(g2h(uaddr), op, val, pts, g2h(uaddr2), + return do_safe_futex(g2h(cpu, uaddr), op, val, pts, g2h(cpu, uaddr= 2), (base_op =3D=3D FUTEX_CMP_REQUEUE - ? tswap32(val3) - : val3)); + ? tswap32(val3) : val3)); default: return -TARGET_ENOSYS; } @@ -7848,7 +7852,7 @@ static int open_self_maps(void *cpu_env, int fd) const char *path; =20 max =3D h2g_valid(max - 1) ? - max : (uintptr_t) g2h(GUEST_ADDR_MAX) + 1; + max : (uintptr_t) g2h_untagged(GUEST_ADDR_MAX) + 1; =20 if (page_check_range(h2g(min), max - min, flags) =3D=3D -1) { continue; @@ -8265,8 +8269,8 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, =20 if (ts->child_tidptr) { put_user_u32(0, ts->child_tidptr); - do_sys_futex(g2h(ts->child_tidptr), FUTEX_WAKE, INT_MAX, - NULL, NULL, 0); + do_sys_futex(g2h(cpu, ts->child_tidptr), + FUTEX_WAKE, INT_MAX, NULL, NULL, 0); } thread_cpu =3D NULL; g_free(ts); @@ -8631,7 +8635,7 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, if (!arg5) { ret =3D mount(p, p2, p3, (unsigned long)arg4, NULL); } else { - ret =3D mount(p, p2, p3, (unsigned long)arg4, g2h(arg5)); + ret =3D mount(p, p2, p3, (unsigned long)arg4, g2h(cpu, arg= 5)); } ret =3D get_errno(ret); =20 @@ -9726,15 +9730,15 @@ static abi_long do_syscall1(void *cpu_env, int num,= abi_long arg1, /* ??? msync/mlock/munlock are broken for softmmu. */ #ifdef TARGET_NR_msync case TARGET_NR_msync: - return get_errno(msync(g2h(arg1), arg2, arg3)); + return get_errno(msync(g2h(cpu, arg1), arg2, arg3)); #endif #ifdef TARGET_NR_mlock case TARGET_NR_mlock: - return get_errno(mlock(g2h(arg1), arg2)); + return get_errno(mlock(g2h(cpu, arg1), arg2)); #endif #ifdef TARGET_NR_munlock case TARGET_NR_munlock: - return get_errno(munlock(g2h(arg1), arg2)); + return get_errno(munlock(g2h(cpu, arg1), arg2)); #endif #ifdef TARGET_NR_mlockall case TARGET_NR_mlockall: @@ -12225,7 +12229,7 @@ static abi_long do_syscall1(void *cpu_env, int num,= abi_long arg1, =20 #if defined(TARGET_NR_set_tid_address) && defined(__NR_set_tid_address) case TARGET_NR_set_tid_address: - return get_errno(set_tid_address((int *)g2h(arg1))); + return get_errno(set_tid_address((int *)g2h(cpu, arg1))); #endif =20 case TARGET_NR_tkill: @@ -12312,11 +12316,11 @@ static abi_long do_syscall1(void *cpu_env, int nu= m, abi_long arg1, #endif #ifdef TARGET_NR_futex case TARGET_NR_futex: - return do_futex(arg1, arg2, arg3, arg4, arg5, arg6); + return do_futex(cpu, arg1, arg2, arg3, arg4, arg5, arg6); #endif #ifdef TARGET_NR_futex_time64 case TARGET_NR_futex_time64: - return do_futex_time64(arg1, arg2, arg3, arg4, arg5, arg6); + return do_futex_time64(cpu, arg1, arg2, arg3, arg4, arg5, arg6); #endif #if defined(TARGET_NR_inotify_init) && defined(__NR_inotify_init) case TARGET_NR_inotify_init: diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index ae611d73c2c..7f56c78fa6c 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -542,7 +542,7 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, = uint64_t addr, =20 #ifdef CONFIG_USER_ONLY /* ??? Enforce alignment. */ - uint64_t *haddr =3D g2h(addr); + uint64_t *haddr =3D g2h(env_cpu(env), addr); =20 set_helper_retaddr(ra); o0 =3D ldq_le_p(haddr + 0); @@ -612,7 +612,7 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, = uint64_t addr, =20 #ifdef CONFIG_USER_ONLY /* ??? Enforce alignment. */ - uint64_t *haddr =3D g2h(addr); + uint64_t *haddr =3D g2h(env_cpu(env), addr); =20 set_helper_retaddr(ra); o1 =3D ldq_be_p(haddr + 0); diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 7ae31e1a154..96d9391c399 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -63,7 +63,7 @@ static void atomic_store_3(CPUHPPAState *env, target_ulon= g addr, uint32_t val, #ifdef CONFIG_USER_ONLY uint32_t old, new, cmp; =20 - uint32_t *haddr =3D g2h(addr - 1); + uint32_t *haddr =3D g2h(env_cpu(env), addr - 1); old =3D *haddr; while (1) { new =3D (old & ~mask) | (val & mask); diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index e5cd2de1bff..591f512bffe 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -66,7 +66,7 @@ void helper_cmpxchg8b(CPUX86State *env, target_ulong a0) =20 #ifdef CONFIG_USER_ONLY { - uint64_t *haddr =3D g2h(a0); + uint64_t *haddr =3D g2h(env_cpu(env), a0); cmpv =3D cpu_to_le64(cmpv); newv =3D cpu_to_le64(newv); oldv =3D qatomic_cmpxchg__nocheck(haddr, cmpv, newv); diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 1901e9dfc7c..25cfede806a 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1780,7 +1780,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, =20 if (parallel) { #ifdef CONFIG_USER_ONLY - uint32_t *haddr =3D g2h(a1); + uint32_t *haddr =3D g2h(env_cpu(env), a1); ov =3D qatomic_cmpxchg__nocheck(haddr, cv, nv); #else TCGMemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mem_= idx); @@ -1804,7 +1804,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, if (parallel) { #ifdef CONFIG_ATOMIC64 # ifdef CONFIG_USER_ONLY - uint64_t *haddr =3D g2h(a1); + uint64_t *haddr =3D g2h(env_cpu(env), a1); ov =3D qatomic_cmpxchg__nocheck(haddr, cv, nv); # else TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN, mem_i= dx); --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050698; cv=none; d=zohomail.com; s=zohoarc; b=OP3XThArubVaaMc851kjX65JReGOEr9cD7Blr60T/bIqhxIN5UXvf5n3irw5qOQJgGdJPZtNtNmDdKvznUaakVJWQZt+a5SwLruYOZaqfmoVcxwUpKRipXTmE5jIkWicVxoajzLpjI3REsGsyT39wSFiQh0JwM8vU78Fr86GpPs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613050698; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hb0J2s80EhWinzon/ZpySDkNPOarrpfCwXclcW514TM=; b=Sudd6JT036b7qFHXWBjghg29U2scZYnBEPCduIRAuG8KnJuyMIK1oHiZBVLCSuZHQK3IW6ix5nhbuT3bdwOh2diXtAXd0576hYK8qG5ynM/IyYcxHsEfxar8Hf2G9ffq/Oqvm8y6Od0itC7/gsO0X1fsK5376wUn4TuRbaTuyA0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613050697993496.10862292854426; Thu, 11 Feb 2021 05:38:17 -0800 (PST) Received: from localhost ([::1]:57228 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lACAi-0003C7-Vm for importer@patchew.org; Thu, 11 Feb 2021 08:38:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZE-0008Kf-Fk for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:33 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:37277) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZ3-0008Up-2b for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:31 -0500 Received: by mail-wm1-x331.google.com with SMTP id m1so5643225wml.2 for ; Thu, 11 Feb 2021 04:59:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hb0J2s80EhWinzon/ZpySDkNPOarrpfCwXclcW514TM=; b=P1vtQghUTDqLRDSr/E0s0AgG+dz3qEc337TGf62zNONLf9JfA6kUPRtJ07mLrzHHbm Fibq5rNv5MrclW2f6CG0XIUl1L3+3Dd+svAN7+JWmOIXdp1BlrEKOtsy+P7p8E4piGr2 poq7cTPbkUTI6mqQhnt7EDF+Ft4bI5zyQ/z/jA4TBFN7iYXXIHezFmU/Axf9pmN+ht/a zJ3EDZMSxqH6swu/d5twgYtVpn1YAvFwrvN6w8vN/ANU19tHYC+eUB5qil3U1VwkZ+E1 IxAcmMm/QKAXwA0J8yrLDb/r/kP+jVclmPatMXPaLmyP3rPMZ+/SiXPUd+y7i75G4m9y jZ4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hb0J2s80EhWinzon/ZpySDkNPOarrpfCwXclcW514TM=; b=VjU1oOEA/2acC65k1kOKReHUqyRbEu4OufycPEy5HLrQlk2j0fumiQw9X+C+6nhiB4 JGQf8zEYOdFnD7fcmmn4yyI7bSATEbLn8o8z3fRKxoeH6pvH6bE6e4RjxL5jpz8IDhXP pvKnzWab545MqfI4+hKzvMxanMnh83GYy29NgDktoi6rUTh9iWw3DC8lHwuFDblRU9Xu 6u+0lUoX2HziTARFluO7UEXEKBar/dbBC9mVjwN+YBUZftenvFFzNeDj3ChOdBhojX98 +BZE5kC7KogRrk2Xd8k5RO8S71EVW7GIcW8AqFjnEW5lk29tYgfVXCrbRdL5K7rQN7qG 8MIg== X-Gm-Message-State: AOAM5312DJNtIztcQbdDxcLgxo7mvcGmbtorwn6H9ZAomQaumkTHtxrg xrWYL9sRsaGUxkrelUxH2tgaZr0g+Wjd7g== X-Google-Smtp-Source: ABdhPJzzX6TnUvKvGNxCyIbYtw3wZIVlT9WNLfNWawIJBJLYkCGBlrRWt7DpcD8zpeIklRcP0GuUtg== X-Received: by 2002:a1c:4e13:: with SMTP id g19mr5239403wmh.55.1613048359838; Thu, 11 Feb 2021 04:59:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/45] linux-user: Explicitly untag memory management syscalls Date: Thu, 11 Feb 2021 12:58:37 +0000 Message-Id: <20210211125900.22777-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We define target_mmap et al as untagged, so that they can be used from the binary loaders. Explicitly call cpu_untagged_addr for munmap, mprotect, mremap syscall entry points. Add a few comments for the syscalls that are exempted by the kernel's tagged-address-abi.rst. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/syscall.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 748893904e3..4451f8e4f08 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -889,6 +889,8 @@ abi_long do_brk(abi_ulong new_brk) abi_long mapped_addr; abi_ulong new_alloc_size; =20 + /* brk pointers are always untagged */ + DEBUGF_BRK("do_brk(" TARGET_ABI_FMT_lx ") -> ", new_brk); =20 if (!new_brk) { @@ -4588,6 +4590,8 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_en= v, int i,ret; abi_ulong shmlba; =20 + /* shmat pointers are always untagged */ + /* find out the length of the shared memory segment */ ret =3D get_errno(shmctl(shmid, IPC_STAT, &shm_info)); if (is_error(ret)) { @@ -4655,6 +4659,8 @@ static inline abi_long do_shmdt(abi_ulong shmaddr) int i; abi_long rv; =20 + /* shmdt pointers are always untagged */ + mmap_lock(); =20 for (i =3D 0; i < N_SHM_REGIONS; ++i) { @@ -9691,6 +9697,7 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, v5, v6)); } #else + /* mmap pointers are always untagged */ ret =3D get_errno(target_mmap(arg1, arg2, arg3, target_to_host_bitmask(arg4, mmap_flag= s_tbl), arg5, @@ -9709,8 +9716,10 @@ static abi_long do_syscall1(void *cpu_env, int num, = abi_long arg1, return get_errno(ret); #endif case TARGET_NR_munmap: + arg1 =3D cpu_untagged_addr(cpu, arg1); return get_errno(target_munmap(arg1, arg2)); case TARGET_NR_mprotect: + arg1 =3D cpu_untagged_addr(cpu, arg1); { TaskState *ts =3D cpu->opaque; /* Special hack to detect libc making the stack executable. */ @@ -9725,6 +9734,8 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, return get_errno(target_mprotect(arg1, arg2, arg3)); #ifdef TARGET_NR_mremap case TARGET_NR_mremap: + arg1 =3D cpu_untagged_addr(cpu, arg1); + /* mremap new_addr (arg5) is always untagged */ return get_errno(target_mremap(arg1, arg2, arg3, arg4, arg5)); #endif /* ??? msync/mlock/munlock are broken for softmmu. */ --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050490; cv=none; d=zohomail.com; s=zohoarc; b=MAG4TuDGEdVcFBvSv7xfRJd2jRLWrYTf0myTHnre+7rFvMe//7aztGWCpp4yJWnJgv8wdrFN70rDJjmBbSIJq+2NkmRyLnFAi+tEtTLeKUSWyTlQ9XWe29bwc9EkEbNjO97BO2i9N6bipGSp2YI8hFLhD4/6OcHyn9N7yhh7+Sw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613050490; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8hJfKWlZ7fO6Xix7TA92xQ2IC7VHBbIlzPjoCjc38sI=; b=No6kQOux07Rl2Rya7WFCcYOhZXhG0DfpOjTy6zRVgJ+N0bfYbo4zDE13FtriygqCeukiFynO2iVIexc5FEFzTciUIJB4yDT/sEU7OmJW/0ZqqRRYk7sKkyNynSOBWfUCsRJCpv3Ngn1rqkc7AZit9kaFLkWzkKG1uCMDj56XAuA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613050489966405.1234960551027; Thu, 11 Feb 2021 05:34:49 -0800 (PST) Received: from localhost ([::1]:48788 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lAC7M-00084D-Rj for importer@patchew.org; Thu, 11 Feb 2021 08:34:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33548) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZ6-0008Gk-JR for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:24 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:36758) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZ3-0008V0-Mt for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:24 -0500 Received: by mail-wr1-x435.google.com with SMTP id u14so4118035wri.3 for ; Thu, 11 Feb 2021 04:59:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8hJfKWlZ7fO6Xix7TA92xQ2IC7VHBbIlzPjoCjc38sI=; b=zJ345KYZOFODnBQMFFox1pGLxWvXURd7EUOYw2+wGYCDz44qdjYzTcItuuqvAnrG8K DU8ssq4NtV/NSLRM9vMRUaGSpHgajqI87jljs8lFZlG1/LypLagsuMwhzfceKJLNhUVl LfMyh9ZWWPg4mLZR8FUCnZSA1/xJ/3EYb3vHnd0nX67bzZRFGmlvthbCeba8RJvB7dd6 cm7XMOhps1DZ0LzL/Oc6ec3UqAQsqL0joVsBxyV4++KNSEPvwRL4Yi9NH+rCQgDy8/2H ZugSmZmqNQIMcUFyD9N0RImbyANrjOj71AAEDMvq7M5mv0HGgI0b4iOePQx+3nv192Xp 3h8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8hJfKWlZ7fO6Xix7TA92xQ2IC7VHBbIlzPjoCjc38sI=; b=QnX2rSOanqLq/ETyrl2bZoW3/9afWyXwB2e9coZkpkLKfhxg57ki6hKeAhGEUiY4OQ tXixWngf7jo6a8Z+KgyJt1eodMoP8D2zfwChhnHAMfELHeUyYM6SZSdKbcUzRfCirgcv mUGYbXfhGMkxW//fVBMJrTh+yJFzG8YQKfQPDVxZ/ITiUm1+OOwq7jpmDoSZYIWNnN9b Lb12wdTqZJHsXlyW4ipzBPTv6DN3r9+v4h9lOcYfbTwZz/hr4QI7ZvjZ9p1i1tZzDu/y nXhWv8uK7sgRZ2V9P/G8uuitjudjxTkKsoZ00UYzwHYphG3kCa30BUDACYMjC1aiQz2E LM3w== X-Gm-Message-State: AOAM530F/xy9SxyupFTKmeNZnlKPL4HK/F9ioZ3KUH9VNOM9ga1CxIap vrAICvyT9AITYqNjFTHSCpNjGlwVlu+IdQ== X-Google-Smtp-Source: ABdhPJxAdriuBt3lpvTYkW3jhopbF0VnHYwLGoW/Nwfj6rK3HaqsqAjrjmXm5Q3jR/hRXkYMJEB21g== X-Received: by 2002:a5d:4708:: with SMTP id y8mr5491223wrq.402.1613048360474; Thu, 11 Feb 2021 04:59:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/45] linux-user: Use guest_range_valid in access_ok Date: Thu, 11 Feb 2021 12:58:38 +0000 Message-Id: <20210211125900.22777-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We're currently open-coding the range check in access_ok; use guest_range_valid when size !=3D 0. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/qemu.h | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 9fbc5edc4bd..ba122a79039 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -493,12 +493,9 @@ extern unsigned long guest_stack_size; =20 static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { - if (!guest_addr_valid(addr)) { - return false; - } - if (size !=3D 0 && - (addr + size - 1 < addr || - !guest_addr_valid(addr + size - 1))) { + if (size =3D=3D 0 + ? !guest_addr_valid(addr) + : !guest_range_valid(addr, size)) { return false; } return page_check_range((target_ulong)addr, size, type) =3D=3D 0; --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050698; cv=none; d=zohomail.com; s=zohoarc; b=drTm3qbQ3evdzSSPyX8N+CfuZ50AQqWHoFAiQX48qQUvA8zr9u28iUJ80bnZJ9waoLvyNY7+rQSm/ixRULHX+5+ZF1frXwpohtnFfcJtubsxiJEyBb8Zqn/4tmYcTSrGLp8tPY2u3mGLxtpf/EuMk+/pyq6EjhijsViSELJuAhw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613050698; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YgxGpzJeSkPHs78f+HAWSg84qQk3nAuymHYPvqcfEew=; b=RIbMqlevt/xj2YBqJi2G/DSF+Gy+zsG8czL30/sML2XxU9MCX+4+a583r/ANj8xB2o/envb69hHrWT2hvItwQglpLNyn+1uLSsicgvx900beEp0ARHOzmEuoNjJn+JArJvLIURxr9HSb/LTDDJmli3XtfYxw1NZSIYd4Uhht5Cw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613050698112550.6068256683666; Thu, 11 Feb 2021 05:38:18 -0800 (PST) Received: from localhost ([::1]:57234 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lACAi-0003CL-Tq for importer@patchew.org; Thu, 11 Feb 2021 08:38:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33624) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZB-0008JU-Ev for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:30 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:36252) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZ4-0008VP-EK for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:28 -0500 Received: by mail-wm1-x331.google.com with SMTP id i9so5657353wmq.1 for ; Thu, 11 Feb 2021 04:59:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YgxGpzJeSkPHs78f+HAWSg84qQk3nAuymHYPvqcfEew=; b=SKA5o95AQwH7UouHpQB7V3PltzTJlfwjHc+1XEPaztb2pBnxlMeuw+LmM6GHqt+5Qk aMswFnrkadeyRGjdnluXcNFTtiRGcWeXyK1X/veenLap82HWt8xvi602cKS6DBv+gTZy C0EqvF2IDRYa8SvVO/0Fr3/dcp42BNfgnrqLdvom/yvPiKnQXfx+B5WKMK1MRdwnUt78 rm3C2FNWzn8Zb0/QFba+nt05cvncfcORvBkn+PNsaWM3A6bAadv7Qa695wS9rNixnFJm UOwE1Lj591W26bFoUgnLMSOhf/NjVQtvTLOZfQIFz0/5Lq7ZfttmBmKnjyKpKY90Xg+w pMPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YgxGpzJeSkPHs78f+HAWSg84qQk3nAuymHYPvqcfEew=; b=ZJy3pVKSsUKIh9Q51RvSGP7j9IkKSn6Y7/jX50rniPPC7YjWb7BoAUDtxXNfIRL8Aa 7HTib1idSvEpYutEnVSiKZ26jf1S4WNkPBHvEdTo2FW1BFco2LCtf+j0DaPVlbeSX1q2 r5wauPQ354qe6DdNrt79LIMObi4k3X22cCTpsjETxCefRjDrdhKbR5mGlpfarn2dDs0I dHY5JcAOT2tSNgZe7Mpwm2sXtawpYGULyxMsAuKcUo2qx+i7Opg4UxNpS9ceZ5NV4Hal T65c54rzM5gkxSmZKkIuB5bLR3XJIqwfDidBWDFntkBYpkk7x03bxJw5zS2uRtYNBMua PlMw== X-Gm-Message-State: AOAM531lp84JuES2ptmAeoprhZXTjC9Pb8li96pfV4oKEd3iCxFgTXVJ KvrESvyzLXg5X0FrzEyvh4TCB+1K7HUhJQ== X-Google-Smtp-Source: ABdhPJxfMB4N2suHNwo+o28MNbBD/ly7w0MavfVUZNQYOjNNc5Q1FzRQcN269Iljomf95N/ErbxVoA== X-Received: by 2002:a1c:f604:: with SMTP id w4mr5131853wmc.39.1613048361170; Thu, 11 Feb 2021 04:59:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/45] exec: Rename guest_{addr,range}_valid to *_untagged Date: Thu, 11 Feb 2021 12:58:39 +0000 Message-Id: <20210211125900.22777-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson The places that use these are better off using untagged addresses, so do not provide a tagged versions. Rename to make it clear about the address type. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu_ldst.h | 4 ++-- linux-user/qemu.h | 4 ++-- accel/tcg/user-exec.c | 3 ++- linux-user/mmap.c | 12 ++++++------ linux-user/syscall.c | 2 +- 5 files changed, 13 insertions(+), 12 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index c54069e3cd0..ce6ce826182 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -87,12 +87,12 @@ static inline void *g2h(CPUState *cs, abi_ptr x) return g2h_untagged(cpu_untagged_addr(cs, x)); } =20 -static inline bool guest_addr_valid(abi_ulong x) +static inline bool guest_addr_valid_untagged(abi_ulong x) { return x <=3D GUEST_ADDR_MAX; } =20 -static inline bool guest_range_valid(abi_ulong start, abi_ulong len) +static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong l= en) { return len - 1 <=3D GUEST_ADDR_MAX && start <=3D GUEST_ADDR_MAX - len = + 1; } diff --git a/linux-user/qemu.h b/linux-user/qemu.h index ba122a79039..b3ccffbf0fa 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -494,8 +494,8 @@ extern unsigned long guest_stack_size; static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { if (size =3D=3D 0 - ? !guest_addr_valid(addr) - : !guest_range_valid(addr, size)) { + ? !guest_addr_valid_untagged(addr) + : !guest_range_valid_untagged(addr, size)) { return false; } return page_check_range((target_ulong)addr, size, type) =3D=3D 0; diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index fa1847b2a61..0d8cc27b213 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -213,7 +213,8 @@ static int probe_access_internal(CPUArchState *env, tar= get_ulong addr, g_assert_not_reached(); } =20 - if (!guest_addr_valid(addr) || page_check_range(addr, 1, flags) < 0) { + if (!guest_addr_valid_untagged(addr) || + page_check_range(addr, 1, flags) < 0) { if (nonfault) { return TLB_INVALID_MASK; } else { diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 088c50592cf..6690384752f 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -119,7 +119,7 @@ int target_mprotect(abi_ulong start, abi_ulong len, int= target_prot) } len =3D TARGET_PAGE_ALIGN(len); end =3D start + len; - if (!guest_range_valid(start, len)) { + if (!guest_range_valid_untagged(start, len)) { return -TARGET_ENOMEM; } if (len =3D=3D 0) { @@ -528,7 +528,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, in= t target_prot, * It can fail only on 64-bit host with 32-bit target. * On any other target/host host mmap() handles this error correct= ly. */ - if (end < start || !guest_range_valid(start, len)) { + if (end < start || !guest_range_valid_untagged(start, len)) { errno =3D ENOMEM; goto fail; } @@ -669,7 +669,7 @@ int target_munmap(abi_ulong start, abi_ulong len) if (start & ~TARGET_PAGE_MASK) return -TARGET_EINVAL; len =3D TARGET_PAGE_ALIGN(len); - if (len =3D=3D 0 || !guest_range_valid(start, len)) { + if (len =3D=3D 0 || !guest_range_valid_untagged(start, len)) { return -TARGET_EINVAL; } =20 @@ -727,9 +727,9 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong ol= d_size, int prot; void *host_addr; =20 - if (!guest_range_valid(old_addr, old_size) || + if (!guest_range_valid_untagged(old_addr, old_size) || ((flags & MREMAP_FIXED) && - !guest_range_valid(new_addr, new_size))) { + !guest_range_valid_untagged(new_addr, new_size))) { errno =3D ENOMEM; return -1; } @@ -777,7 +777,7 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong ol= d_size, =20 if (host_addr !=3D MAP_FAILED) { /* Check if address fits target address space */ - if (!guest_range_valid(h2g(host_addr), new_size)) { + if (!guest_range_valid_untagged(h2g(host_addr), new_size))= { /* Revert mremap() changes */ host_addr =3D mremap(g2h_untagged(old_addr), new_size, old_size, flags); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 4451f8e4f08..30a5021509e 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -4608,7 +4608,7 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_en= v, return -TARGET_EINVAL; } } - if (!guest_range_valid(shmaddr, shm_info.shm_segsz)) { + if (!guest_range_valid_untagged(shmaddr, shm_info.shm_segsz)) { return -TARGET_EINVAL; } =20 --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rCXXZb8RGeVRsjgPYQzTpFm0H5PWMKbHXfySrTVhE1o=; b=cKaMcHhD2MvJNmE/9bbNVUjHFJGw6fgDkK5wITZH9wFCAphjMUWJf2K2VG/r+YRKoi C7tcoTgkCLO0gcE0EaeU/OSG2SCwu9Sl3V95cHbwXPyg/W0CPd5MX8C0E5mFXjLu9K6R YPgn5/e6hBhRPJUnsBl/FvPxRex9NFnUaEgTZB3Q8x7quYXtvxYlXC7OQb1gorbq8NLA DaUOhP+LWfpyBQpYKAT2wywzy3O1mOR7kwsPB4VJsuNd3E3J+1zsU1RjZSzEuO3/2mhi nSJNkxrO8cmw7jb89ZP4Bvrk6aYh7FWG1JqJWbH9QtUS2+qX6buk0R3AVrMKZQZZf+0F 0DTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rCXXZb8RGeVRsjgPYQzTpFm0H5PWMKbHXfySrTVhE1o=; b=apOQRL7lR72hAnEL/tfNSc+ZGcGHKLmzyPEmgVKtmAlLw8LylkhofXw/In4xI2yt8i 9t80qr3HKGB7Y58tbACBgdm9PkvLF/m7mV2ckjNvRGgMzoPT1vYBNhs/gLzKJmlMQTZX lD75y6yGaUUDVdfhcwlHuKTCmi5++JyD033eb0ShOD3ewfzoKS9oTtB8j8gxLm+sLpMR yVn8VcIPH6teChyc32bTFdbZfHfq+zQGjdIfc33uMnWEa02zvqi/BWj1Gx5k4vRjrYC0 pXxX3avu5U5DQ1iB0hAqVqzADaFuW8b69N46kEa8e/5IMsxiaZj8mjBtxzxxxxAOgSti o2lw== X-Gm-Message-State: AOAM532jNxkxH/laS7vYKLBFcr6a0waS7MgElkB+RzEHLldpxebER/9Q XqXw+T+9CnUwACJi5LNupKECBQ/noNW5ZA== X-Google-Smtp-Source: ABdhPJwnak3MLwAda9UNneCgYjxe2iuCPAjYLvp3PZtR8msq8vWMBg0qfROAMjfNZi6WMKbz/GupPw== X-Received: by 2002:a1c:9cc5:: with SMTP id f188mr4939686wme.171.1613048361901; Thu, 11 Feb 2021 04:59:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/45] linux-user: Use cpu_untagged_addr in access_ok; split out *_untagged Date: Thu, 11 Feb 2021 12:58:40 +0000 Message-Id: <20210211125900.22777-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Provide both tagged and untagged versions of access_ok. In a few places use thread_cpu, as the user is several callees removed from do_syscall1. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/qemu.h | 11 +++++++++-- linux-user/elfload.c | 2 +- linux-user/hppa/cpu_loop.c | 8 ++++---- linux-user/i386/cpu_loop.c | 2 +- linux-user/i386/signal.c | 5 +++-- linux-user/syscall.c | 9 ++++++--- 6 files changed, 24 insertions(+), 13 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index b3ccffbf0fa..82eabb73f80 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -491,7 +491,7 @@ extern unsigned long guest_stack_size; #define VERIFY_READ PAGE_READ #define VERIFY_WRITE (PAGE_READ | PAGE_WRITE) =20 -static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) +static inline bool access_ok_untagged(int type, abi_ulong addr, abi_ulong = size) { if (size =3D=3D 0 ? !guest_addr_valid_untagged(addr) @@ -501,6 +501,12 @@ static inline bool access_ok(int type, abi_ulong addr,= abi_ulong size) return page_check_range((target_ulong)addr, size, type) =3D=3D 0; } =20 +static inline bool access_ok(CPUState *cpu, int type, + abi_ulong addr, abi_ulong size) +{ + return access_ok_untagged(type, cpu_untagged_addr(cpu, addr), size); +} + /* NOTE __get_user and __put_user use host pointers and don't check access. These are usually used to access struct data members once the struct has been locked - usually with lock_user_struct. */ @@ -636,8 +642,9 @@ abi_long copy_to_user(abi_ulong gaddr, void *hptr, size= _t len); host area will have the same contents as the guest. */ static inline void *lock_user(int type, abi_ulong guest_addr, long len, in= t copy) { - if (!access_ok(type, guest_addr, len)) + if (!access_ok_untagged(type, guest_addr, len)) { return NULL; + } #ifdef DEBUG_REMAP { void *addr; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f542841ba24..e7209e03cb5 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -3500,7 +3500,7 @@ static int vma_get_mapping_count(const struct mm_stru= ct *mm) static abi_ulong vma_dump_size(const struct vm_area_struct *vma) { /* if we cannot even read the first page, skip it */ - if (!access_ok(VERIFY_READ, vma->vma_start, TARGET_PAGE_SIZE)) + if (!access_ok_untagged(VERIFY_READ, vma->vma_start, TARGET_PAGE_SIZE)) return (0); =20 /* diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 944511bbe43..3aaaf3337cb 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -35,7 +35,7 @@ static abi_ulong hppa_lws(CPUHPPAState *env) return -TARGET_ENOSYS; =20 case 0: /* elf32 atomic 32bit cmpxchg */ - if ((addr & 3) || !access_ok(VERIFY_WRITE, addr, 4)) { + if ((addr & 3) || !access_ok(cs, VERIFY_WRITE, addr, 4)) { return -TARGET_EFAULT; } old =3D tswap32(old); @@ -50,9 +50,9 @@ static abi_ulong hppa_lws(CPUHPPAState *env) return -TARGET_ENOSYS; } if (((addr | old | new) & ((1 << size) - 1)) - || !access_ok(VERIFY_WRITE, addr, 1 << size) - || !access_ok(VERIFY_READ, old, 1 << size) - || !access_ok(VERIFY_READ, new, 1 << size)) { + || !access_ok(cs, VERIFY_WRITE, addr, 1 << size) + || !access_ok(cs, VERIFY_READ, old, 1 << size) + || !access_ok(cs, VERIFY_READ, new, 1 << size)) { return -TARGET_EFAULT; } /* Note that below we use host-endian loads so that the cmpxchg diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index 19c8a18cd30..f813e87294a 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -99,7 +99,7 @@ static bool write_ok_or_segv(CPUX86State *env, abi_ptr ad= dr, size_t len) * For all the vsyscalls, NULL means "don't write anything" not * "write it at address 0". */ - if (addr =3D=3D 0 || access_ok(VERIFY_WRITE, addr, len)) { + if (addr =3D=3D 0 || access_ok(env_cpu(env), VERIFY_WRITE, addr, len))= { return true; } =20 diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c index 97a39204cc2..9320e1d4726 100644 --- a/linux-user/i386/signal.c +++ b/linux-user/i386/signal.c @@ -513,9 +513,10 @@ restore_sigcontext(CPUX86State *env, struct target_sig= context *sc) =20 fpstate_addr =3D tswapl(sc->fpstate); if (fpstate_addr !=3D 0) { - if (!access_ok(VERIFY_READ, fpstate_addr, - sizeof(struct target_fpstate))) + if (!access_ok(env_cpu(env), VERIFY_READ, fpstate_addr, + sizeof(struct target_fpstate))) { goto badframe; + } #ifndef TARGET_X86_64 cpu_x86_frstor(env, fpstate_addr, 1); #else diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 30a5021509e..24fc1daf023 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -3515,8 +3515,9 @@ static abi_long do_accept4(int fd, abi_ulong target_a= ddr, return -TARGET_EINVAL; } =20 - if (!access_ok(VERIFY_WRITE, target_addr, addrlen)) + if (!access_ok(thread_cpu, VERIFY_WRITE, target_addr, addrlen)) { return -TARGET_EFAULT; + } =20 addr =3D alloca(addrlen); =20 @@ -3546,8 +3547,9 @@ static abi_long do_getpeername(int fd, abi_ulong targ= et_addr, return -TARGET_EINVAL; } =20 - if (!access_ok(VERIFY_WRITE, target_addr, addrlen)) + if (!access_ok(thread_cpu, VERIFY_WRITE, target_addr, addrlen)) { return -TARGET_EFAULT; + } =20 addr =3D alloca(addrlen); =20 @@ -3577,8 +3579,9 @@ static abi_long do_getsockname(int fd, abi_ulong targ= et_addr, return -TARGET_EINVAL; } =20 - if (!access_ok(VERIFY_WRITE, target_addr, addrlen)) + if (!access_ok(thread_cpu, VERIFY_WRITE, target_addr, addrlen)) { return -TARGET_EFAULT; + } =20 addr =3D alloca(addrlen); =20 --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050840; cv=none; d=zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=kS0wcoQoiBYMcu4/cbxljJngWS6Q8+y8v/3NNJnmd7E=; b=fa116oVH6sL8mM94Nxm3AWGyUnqeQvxdHgCDxCJ1qgEU2+r74mRAkw3CROJv7+ryl8 Wox/pE3C8hfWxeKjDUmlHHZJYkRcGC4cV0LqlGdHGeNxPDzxJDG7/xBzqJrjrIU5rXBa 4dTApUCw9RcEBwihSrj7IALTFqVtxl8YNh7RtiQIa9pXCZr1DbOPxmk2WUAFWehnbvdR OzbCbfvQrmkhnt62I9CjRpVwxe1eWvDJcGTcMeFJ2NNi9NelIUqITprNWe6YNAL46iig puuU7K5doP0Iufh1PVvPjvU+ivmTtvb1aekO8wD76REgMmbmV3InE1YcRWyi3BGXBh4O HBeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kS0wcoQoiBYMcu4/cbxljJngWS6Q8+y8v/3NNJnmd7E=; b=RLH4ekiUQtw9tsmo6CLijNYtvQN/e2V9+NbhiJ/J4N5m2weNDI4UrYveiS/U4XOgBo 24Sfl3AfPrqjqE+Mx3ajkFZhfePaUN78sM2VXgweaoqNe/Grxy9zlDe66c4b5SJEwt6T 9ZfhoKTxXnMdHvSLF3UUuSjshsdxF0eSYB1houH5awq5O8BOnC64o32uVciRPoa8K4cB 37CO3a+E6gbdRgFzcIqFgtqZhveOnnYdbV+w5OFFAflcRayjrOBId/zvfgjV7gB/yX/d su4q2EpqUmiRhTie67d8nxXLavNpow04zC3Wyypx+MqUom6l95cmN+McDebnXf/peJG6 N6YQ== X-Gm-Message-State: AOAM5302Y70PpDg5aNfF9eod5Fq/idyXijIi1LRrJUncMbn+vIlp8ncK aWAu05lJ5LgD0F1AfDgWe163L+lMAz8+vQ== X-Google-Smtp-Source: ABdhPJzoiezDkEyp4HeIcxGXcKeTnR8mBOnMNK/xAJnQuxlZTPOL+TPH4nUCPODw758OB2i+S8yL6A== X-Received: by 2002:a1c:720b:: with SMTP id n11mr5180555wmc.154.1613048362541; Thu, 11 Feb 2021 04:59:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/45] linux-user: Move lock_user et al out of line Date: Thu, 11 Feb 2021 12:58:41 +0000 Message-Id: <20210211125900.22777-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson These functions are not small, except for unlock_user without debugging enabled. Move them out of line, and add missing braces on the way. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/qemu.h | 45 ++++++------------------------------------- linux-user/uaccess.c | 46 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 39 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 82eabb73f80..36b58bd840f 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -640,57 +640,24 @@ abi_long copy_to_user(abi_ulong gaddr, void *hptr, si= ze_t len); =20 /* Lock an area of guest memory into the host. If copy is true then the host area will have the same contents as the guest. */ -static inline void *lock_user(int type, abi_ulong guest_addr, long len, in= t copy) -{ - if (!access_ok_untagged(type, guest_addr, len)) { - return NULL; - } -#ifdef DEBUG_REMAP - { - void *addr; - addr =3D g_malloc(len); - if (copy) - memcpy(addr, g2h(guest_addr), len); - else - memset(addr, 0, len); - return addr; - } -#else - return g2h_untagged(guest_addr); -#endif -} +void *lock_user(int type, abi_ulong guest_addr, long len, int copy); =20 /* Unlock an area of guest memory. The first LEN bytes must be flushed back to guest memory. host_ptr =3D NULL is explicitly allowed and does nothing. */ -static inline void unlock_user(void *host_ptr, abi_ulong guest_addr, - long len) -{ - #ifdef DEBUG_REMAP - if (!host_ptr) - return; - if (host_ptr =3D=3D g2h_untagged(guest_addr)) - return; - if (len > 0) - memcpy(g2h_untagged(guest_addr), host_ptr, len); - g_free(host_ptr); +static inline void unlock_user(void *host_ptr, abi_ulong guest_addr, long = len) +{ } +#else +void unlock_user(void *host_ptr, abi_ulong guest_addr, long len); #endif -} =20 /* Return the length of a string in target memory or -TARGET_EFAULT if access error. */ abi_long target_strlen(abi_ulong gaddr); =20 /* Like lock_user but for null terminated strings. */ -static inline void *lock_user_string(abi_ulong guest_addr) -{ - abi_long len; - len =3D target_strlen(guest_addr); - if (len < 0) - return NULL; - return lock_user(VERIFY_READ, guest_addr, (long)(len + 1), 1); -} +void *lock_user_string(abi_ulong guest_addr); =20 /* Helper macros for locking/unlocking a target struct. */ #define lock_user_struct(type, host_ptr, guest_addr, copy) \ diff --git a/linux-user/uaccess.c b/linux-user/uaccess.c index e215ecc2a60..bba012ed159 100644 --- a/linux-user/uaccess.c +++ b/linux-user/uaccess.c @@ -4,6 +4,52 @@ =20 #include "qemu.h" =20 +void *lock_user(int type, abi_ulong guest_addr, long len, int copy) +{ + if (!access_ok_untagged(type, guest_addr, len)) { + return NULL; + } +#ifdef DEBUG_REMAP + { + void *addr; + addr =3D g_malloc(len); + if (copy) { + memcpy(addr, g2h(guest_addr), len); + } else { + memset(addr, 0, len); + } + return addr; + } +#else + return g2h_untagged(guest_addr); +#endif +} + +#ifdef DEBUG_REMAP +void unlock_user(void *host_ptr, abi_ulong guest_addr, long len); +{ + if (!host_ptr) { + return; + } + if (host_ptr =3D=3D g2h_untagged(guest_addr)) { + return; + } + if (len > 0) { + memcpy(g2h_untagged(guest_addr), host_ptr, len); + } + g_free(host_ptr); +} +#endif + +void *lock_user_string(abi_ulong guest_addr) +{ + abi_long len =3D target_strlen(guest_addr); + if (len < 0) { + return NULL; + } + return lock_user(VERIFY_READ, guest_addr, (long)(len + 1), 1); +} + /* copy_from_user() and copy_to_user() are usually used to copy data * buffers between the target and host. These internally perform * locking/unlocking of the memory. --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050512; cv=none; d=zohomail.com; s=zohoarc; b=GtL8VRQ4+2wzGSjI4yBxrKP3wR2P7BxdoIfgvFd1rFP3O8B06/ximYoGSDnhhZvV61Gz3IH55lxXH02ze4cP/2vASvw1VshTaSQS3IknY0cg2gX7KFb+6ze6sXqgld/9Wsk28TlYPJUqYvO/Y7Cf7W+uN308IQtEXFNWmCIGIJ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613050512; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=u7gQJdYfeB2TD4ECturIjPYtiu4xSyaQm8fEdsXqpVI=; b=YMRNVCQw4rIgCe4hS9T8UJ5ZHD87n1Cblyqx8gE9oLzIT2qdO5OvS9aVJKLLNWYy/AVCGtQ3CZ9LkZFQW6um7TiyhDN6iSAupNg1T4jM9xkonFrfcpH4+plom2rEYoRSuWtKAlmf958/3uF4tKu6LALUXQcdr+7vSp3rHGtpSuU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613050511676920.9876547370994; Thu, 11 Feb 2021 05:35:11 -0800 (PST) Received: from localhost ([::1]:49788 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lAC7i-0008W2-EQ for importer@patchew.org; Thu, 11 Feb 2021 08:35:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33708) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZG-0008L8-6s for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:35 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:34189) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZ8-00004t-9g for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:33 -0500 Received: by mail-wm1-x32f.google.com with SMTP id o10so5932301wmc.1 for ; Thu, 11 Feb 2021 04:59:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=u7gQJdYfeB2TD4ECturIjPYtiu4xSyaQm8fEdsXqpVI=; b=WeV9fQflPVrwParK0E94Nf7FuHgOA3FB8Zme+PcF6ujHDVQbqcv5/yeOB+2YIur+gJ symK+GN7HtrkGB3VfKGvZqKMIXyzkamfA06D9B0wD5erHXKIqu4RiPiETAjUkJPjN9+m dlgmnqJF3Rc+tR+wa6TpVkBqD4FJ1refMH1jaDLJFeEFpiRh8Fr5IRTSVBun3t4jHL5r HC6mlhQ3Dthqno/IEr+sEKyQ9et/J7aGjAR1WerLw3jjuMNqwMAxGWz4o7k5V8fTbxBo V0Ikc0zeiHI3ALenFKn61T7NSLKs7WOGadJ4XR7Eemt7JJK+B/i/8ljEsSv6eJJNMASO 3Y3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u7gQJdYfeB2TD4ECturIjPYtiu4xSyaQm8fEdsXqpVI=; b=CnU4Wro1AbFDzmZ79+/Fzf2J1NfgMLZNgndWQW9Xe8ZnSDAGb4W9639Pu8kqlQq68U LfP16Mw84z2VZX+BnOZh8j0EDAL8iinjO0HcVb6OptZIO7/An/npj5XjyFbwPl0M9Prq r9Ehe2aQ9Xhj9MLTaBScsV7tPkOx2DlE6c45u9ahv0pxIcMxI8NjYwaCArlUghrkS4I/ Q2tr+VDvtYO4eO/TjQkF02T5dHzic81h4NzkOZXgU0F/De0GEzNtNoLVF9ZtjNVYYmH3 0HKOUcnINgshmvNq3X76DdfvFkw9JLnE6TZqNQy25PFKQZvkdzswfpgIjV5SoJBWxX1c eRpQ== X-Gm-Message-State: AOAM533EtXpCW3VyFe+7aHGV3dDAt+F6zCAAHyCKR9pbrpnKc9lvbDoI Jjzzuk7HEfS9/z3EENVUmLJ5nAwfQwo7MQ== X-Google-Smtp-Source: ABdhPJzwG39nNvn7B6xQUvMEoQCXxHHymIkZLdNbDfCXlgHAf9nJOohs4wJOEgmuO2551TlqTkQPkA== X-Received: by 2002:a7b:c95a:: with SMTP id i26mr5014145wml.164.1613048363284; Thu, 11 Feb 2021 04:59:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/45] linux-user: Fix types in uaccess.c Date: Thu, 11 Feb 2021 12:58:42 +0000 Message-Id: <20210211125900.22777-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson For copy_*_user, only 0 and -TARGET_EFAULT are returned; no need to involve abi_long. Use size_t for lengths. Use bool for the lock_user copy argument. Use ssize_t for target_strlen, because we can't overflow the host memory space. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/qemu.h | 14 ++++++-------- linux-user/uaccess.c | 45 ++++++++++++++++++++++---------------------- 2 files changed, 29 insertions(+), 30 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 36b58bd840f..d25a5dafc0f 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -7,8 +7,6 @@ #include "exec/cpu_ldst.h" =20 #undef DEBUG_REMAP -#ifdef DEBUG_REMAP -#endif /* DEBUG_REMAP */ =20 #include "exec/user/abitypes.h" =20 @@ -629,8 +627,8 @@ static inline bool access_ok(CPUState *cpu, int type, * buffers between the target and host. These internally perform * locking/unlocking of the memory. */ -abi_long copy_from_user(void *hptr, abi_ulong gaddr, size_t len); -abi_long copy_to_user(abi_ulong gaddr, void *hptr, size_t len); +int copy_from_user(void *hptr, abi_ulong gaddr, size_t len); +int copy_to_user(abi_ulong gaddr, void *hptr, size_t len); =20 /* Functions for accessing guest memory. The tget and tput functions read/write single values, byteswapping as necessary. The lock_user fun= ction @@ -640,13 +638,13 @@ abi_long copy_to_user(abi_ulong gaddr, void *hptr, si= ze_t len); =20 /* Lock an area of guest memory into the host. If copy is true then the host area will have the same contents as the guest. */ -void *lock_user(int type, abi_ulong guest_addr, long len, int copy); +void *lock_user(int type, abi_ulong guest_addr, size_t len, bool copy); =20 /* Unlock an area of guest memory. The first LEN bytes must be flushed back to guest memory. host_ptr =3D NULL is explicitly allowed and does nothing. */ -#ifdef DEBUG_REMAP -static inline void unlock_user(void *host_ptr, abi_ulong guest_addr, long = len) +#ifndef DEBUG_REMAP +static inline void unlock_user(void *host_ptr, abi_ulong guest_addr, size_= t len) { } #else void unlock_user(void *host_ptr, abi_ulong guest_addr, long len); @@ -654,7 +652,7 @@ void unlock_user(void *host_ptr, abi_ulong guest_addr, = long len); =20 /* Return the length of a string in target memory or -TARGET_EFAULT if access error. */ -abi_long target_strlen(abi_ulong gaddr); +ssize_t target_strlen(abi_ulong gaddr); =20 /* Like lock_user but for null terminated strings. */ void *lock_user_string(abi_ulong guest_addr); diff --git a/linux-user/uaccess.c b/linux-user/uaccess.c index bba012ed159..76af6a92b11 100644 --- a/linux-user/uaccess.c +++ b/linux-user/uaccess.c @@ -4,7 +4,7 @@ =20 #include "qemu.h" =20 -void *lock_user(int type, abi_ulong guest_addr, long len, int copy) +void *lock_user(int type, abi_ulong guest_addr, size_t len, bool copy) { if (!access_ok_untagged(type, guest_addr, len)) { return NULL; @@ -26,7 +26,7 @@ void *lock_user(int type, abi_ulong guest_addr, long len,= int copy) } =20 #ifdef DEBUG_REMAP -void unlock_user(void *host_ptr, abi_ulong guest_addr, long len); +void unlock_user(void *host_ptr, abi_ulong guest_addr, size_t len); { if (!host_ptr) { return; @@ -34,7 +34,7 @@ void unlock_user(void *host_ptr, abi_ulong guest_addr, lo= ng len); if (host_ptr =3D=3D g2h_untagged(guest_addr)) { return; } - if (len > 0) { + if (len !=3D 0) { memcpy(g2h_untagged(guest_addr), host_ptr, len); } g_free(host_ptr); @@ -43,53 +43,53 @@ void unlock_user(void *host_ptr, abi_ulong guest_addr, = long len); =20 void *lock_user_string(abi_ulong guest_addr) { - abi_long len =3D target_strlen(guest_addr); + ssize_t len =3D target_strlen(guest_addr); if (len < 0) { return NULL; } - return lock_user(VERIFY_READ, guest_addr, (long)(len + 1), 1); + return lock_user(VERIFY_READ, guest_addr, (size_t)len + 1, 1); } =20 /* copy_from_user() and copy_to_user() are usually used to copy data * buffers between the target and host. These internally perform * locking/unlocking of the memory. */ -abi_long copy_from_user(void *hptr, abi_ulong gaddr, size_t len) +int copy_from_user(void *hptr, abi_ulong gaddr, size_t len) { - abi_long ret =3D 0; - void *ghptr; + int ret =3D 0; + void *ghptr =3D lock_user(VERIFY_READ, gaddr, len, 1); =20 - if ((ghptr =3D lock_user(VERIFY_READ, gaddr, len, 1))) { + if (ghptr) { memcpy(hptr, ghptr, len); unlock_user(ghptr, gaddr, 0); - } else + } else { ret =3D -TARGET_EFAULT; - + } return ret; } =20 - -abi_long copy_to_user(abi_ulong gaddr, void *hptr, size_t len) +int copy_to_user(abi_ulong gaddr, void *hptr, size_t len) { - abi_long ret =3D 0; - void *ghptr; + int ret =3D 0; + void *ghptr =3D lock_user(VERIFY_WRITE, gaddr, len, 0); =20 - if ((ghptr =3D lock_user(VERIFY_WRITE, gaddr, len, 0))) { + if (ghptr) { memcpy(ghptr, hptr, len); unlock_user(ghptr, gaddr, len); - } else + } else { ret =3D -TARGET_EFAULT; + } =20 return ret; } =20 /* Return the length of a string in target memory or -TARGET_EFAULT if access error */ -abi_long target_strlen(abi_ulong guest_addr1) +ssize_t target_strlen(abi_ulong guest_addr1) { uint8_t *ptr; abi_ulong guest_addr; - int max_len, len; + size_t max_len, len; =20 guest_addr =3D guest_addr1; for(;;) { @@ -101,11 +101,12 @@ abi_long target_strlen(abi_ulong guest_addr1) unlock_user(ptr, guest_addr, 0); guest_addr +=3D len; /* we don't allow wrapping or integer overflow */ - if (guest_addr =3D=3D 0 ||=20 - (guest_addr - guest_addr1) > 0x7fffffff) + if (guest_addr =3D=3D 0 || (guest_addr - guest_addr1) > 0x7fffffff= ) { return -TARGET_EFAULT; - if (len !=3D max_len) + } + if (len !=3D max_len) { break; + } } return guest_addr - guest_addr1; } --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050306; cv=none; d=zohomail.com; s=zohoarc; b=OD0h2fc4kesoZX8COSaSLwYrCN4sEswHJ8ob0ivTtXpmeeADC44rEnNVAAGJRS5p7cmN/PtkICK+QdLUMxXdp2XXAVJGA6iDtlX2+qKShEbqgTpdjsPfeFx97D7tU9mhEyiEcjnNsgTKEwn515f2By7jdxk5zdtG4WgbcPPZxZg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613050306; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=A7ZOkJKx8zqr+LMVmnNNeeuYc84tBTozRptYcVKimjQ=; b=dR1SaHceJMAAGFGWFRZwR0wXyQy9yugghsSPL++1P7lhGSGkw9QH+IDHIgdQpr/lAuzgY15bbifVMvtCYJIeir3hp2hv368HeH/1WDq7uIO1xJlN7fdHPIWiiYqppMr+3mGyYKG/YrniI5NsfbMo2mlrr6oXEh+ei1c/7pblATg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16130503064761013.990109421734; Thu, 11 Feb 2021 05:31:46 -0800 (PST) Received: from localhost ([::1]:41154 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lAC4P-0004vJ-9E for importer@patchew.org; Thu, 11 Feb 2021 08:31:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33710) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZG-0008LQ-7r for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:35 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:36756) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZ8-00004y-9M for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:34 -0500 Received: by mail-wr1-x432.google.com with SMTP id u14so4118236wri.3 for ; Thu, 11 Feb 2021 04:59:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=A7ZOkJKx8zqr+LMVmnNNeeuYc84tBTozRptYcVKimjQ=; b=b/s1eUvylo0iHE6NN156d6kGZzdPzpaN/6glbrqfpvWNC9lUyD3UjqRaQj0Rpyfo0B WVsBnrYAOFPFQaHLE2KVuQ5KJkyc/crDudODnBW0Cu/IMWSQThj4nZFpRMok6aifC9t0 939/dmV59n+tM6XmOIOOjy0B26wjxFSUhS1vwzF4BHu35eUzBIkkXFDN7bD17lE0aHDx r8GLD9Wk/1LVJzYW8czo5iX7husGikgRNCor0RnVkquJlRZ6mUzg/xjgXnHK6EW3GOtx 0+WvcrE2qXRqQ3BdnZ/ehfcxzaAb3Oz+c+NhOKQ2U+pPiSMDGtooLKOl00NPyz3qTghd f8LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A7ZOkJKx8zqr+LMVmnNNeeuYc84tBTozRptYcVKimjQ=; b=lg8X2JIMktnrOhJyWH1W1dFnnnMU8Typ1eaZf0/YqKn7/LWfYjPusGS2Tb6LRqigEp iz9Vcrk+LSubxt3f0Wagd4FM1URxlSmTsb9nm+7ESLvsqxGCWFwXiWV2WRAe6dMSNsFA Q8Ye5kxfAGM5Iwj6aE9vrkqGjTFrwALAPWIMBOP2I3SD8qM9+haA1ARbDItAH0I5uyfO MUxHYtDMdoh2m5Nz4LRo+vumO2oSaIENYx0V1ml5GLZp0Y8vl3IUWr/wieZbnUZpd+nz SFrzz5xbHYqu9cBZlJiFrHswfXHvT/2h0a8lkolNqLAZoOjYphwFvjRpEdwR8x9HE1of FCSg== X-Gm-Message-State: AOAM530KUem3fxXGdDS5H0I52QrwhXLewKPaNxyNeCg71yzmhhmV9S7t WxyMyeFGCVzOTXPyGj2TfPDa/ZbBzVt5jg== X-Google-Smtp-Source: ABdhPJxfwKkQfhp2Sefryw44qiojNKqSdMF2Es93mAhI0A9gCbO9z/9vA2NEw1pcuahuHsivYS5l0A== X-Received: by 2002:a5d:47a2:: with SMTP id 2mr5580927wrb.393.1613048363937; Thu, 11 Feb 2021 04:59:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/45] linux-user: Handle tags in lock_user/unlock_user Date: Thu, 11 Feb 2021 12:58:43 +0000 Message-Id: <20210211125900.22777-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Resolve the untagged address once, using thread_cpu. Tidy the DEBUG_REMAP code using glib routines. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20210210000223.884088-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/uaccess.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/linux-user/uaccess.c b/linux-user/uaccess.c index 76af6a92b11..c6969130163 100644 --- a/linux-user/uaccess.c +++ b/linux-user/uaccess.c @@ -6,36 +6,37 @@ =20 void *lock_user(int type, abi_ulong guest_addr, size_t len, bool copy) { + void *host_addr; + + guest_addr =3D cpu_untagged_addr(thread_cpu, guest_addr); if (!access_ok_untagged(type, guest_addr, len)) { return NULL; } + host_addr =3D g2h_untagged(guest_addr); #ifdef DEBUG_REMAP - { - void *addr; - addr =3D g_malloc(len); - if (copy) { - memcpy(addr, g2h(guest_addr), len); - } else { - memset(addr, 0, len); - } - return addr; + if (copy) { + host_addr =3D g_memdup(host_addr, len); + } else { + host_addr =3D g_malloc0(len); } -#else - return g2h_untagged(guest_addr); #endif + return host_addr; } =20 #ifdef DEBUG_REMAP void unlock_user(void *host_ptr, abi_ulong guest_addr, size_t len); { + void *host_ptr_conv; + if (!host_ptr) { return; } - if (host_ptr =3D=3D g2h_untagged(guest_addr)) { + host_ptr_conv =3D g2h(thread_cpu, guest_addr); + if (host_ptr =3D=3D host_ptr_conv) { return; } if (len !=3D 0) { - memcpy(g2h_untagged(guest_addr), host_ptr, len); + memcpy(host_ptr_conv, host_ptr, len); } g_free(host_ptr); } --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613049952; cv=none; d=zohomail.com; s=zohoarc; b=LHyTWr8nr4eD1rq9tIzaTXgKppV9XaS0bHXTSi7FCTcrFQ/GNwChskWNL5Fj+8OfOIuL/OqR6U23EhF2v6KjlEP9Cie9Ph+SFFug9+wBaBpmt6kHsEkg1rQH9/a+g61S3QSx05LTzxYvzyJaQ736QKMRC3sTJckfCxZV+HKzmDg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613049952; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NFcO/onIf9UrRkiC/VPWZV5WM29pVldbxiccR8vCivc=; b=V1OA3QsFugQEN4wuBpH381cDasAkMS4wHxmEUdzo+WUKugaV3/FmP6X48XvnGdfwLbrp8cm1nlL9UiRK4kWiq0hhgXYBP0+HMgl0o1bAwdyBdw6Ma+XXXlLk3LkZUvCOOY1T/vSvVjF0gCPqWZSzp+52y9nP2aTGiNzD4OcJQKE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613049952424261.73571961588686; Thu, 11 Feb 2021 05:25:52 -0800 (PST) Received: from localhost ([::1]:53018 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lAByh-0005Is-9z for importer@patchew.org; Thu, 11 Feb 2021 08:25:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33688) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZE-0008Kn-IB for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:33 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:46562) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZ8-00005D-AY for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:32 -0500 Received: by mail-wr1-x433.google.com with SMTP id t15so1765647wrx.13 for ; Thu, 11 Feb 2021 04:59:25 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NFcO/onIf9UrRkiC/VPWZV5WM29pVldbxiccR8vCivc=; b=sAhnMKE0Z2LFELo3XDqTqXeln2XffRTwPqxd1fzescjHfL9WWZJ73DNqzjUx/NvE3V kNTdSSgPQoOgOePIRhHJ5b/3fqdy50luRZw72+CQZgZbXEff14VzuIsx8fJvfrIskD7L EQpLnTU5s0yTYj0xrwvUk2HWbZ42tvrPuqfJCQz8Hj8Rohrx9B2ad/kMh+r8ogSNw5k6 h0lmWNaUQsGvSo76gP+wLK79oKzm3lLgUqlad8mjp/qAzJi1Yq+YPekADPS0LmDILUL+ feffuD4CXDsBg3f2LErSXiM8hGMG1wpJcGuiAYfdrCp0YAeaW1KzCEpr3ZcYX3mXkk5J so1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NFcO/onIf9UrRkiC/VPWZV5WM29pVldbxiccR8vCivc=; b=bskLlf+NCLlBhxEjHZPBO2d0jqV1lf+r9c/MqpomtjZWpOb3IefdSaBTKrG9byXDI7 noB2G0iEKBUzJs/1OI6RS6/IfmDCEqO1qfiOhgosKEIQOmRQUSk2PEa310q6kvk7+fl6 o+qF7hVI7lty4SKBy9+I5yMalSbRV2AHiHSF2gsN+r+J75WfbnLTiWmTMQ9oAE9zaI8y Orvp0bCsawM9zssEkmJaQ+hIa9xHHUtYQo+EpTkBA+ghkxJdQ3hQkxiEBTsF856ulpbI YXbfoAIw8QWXITh1sEQdu6mMUhv9kvxfL4Qtze+y444Qon5VZ6/11OhtIhPioXCNaw9U Wh4A== X-Gm-Message-State: AOAM531K0CMqBgDAlk5SaIhGE4jqIPet6slmDgSxuxhjXnZVPVoPl635 i6dDihgIQbjrcQnGmW7wNUQ7z1xHtysspg== X-Google-Smtp-Source: ABdhPJwjkWtkVxshkFqKc/kWYtibKixnouQNH9jc1H6hQbim5/JlW2PYK+9BzncVczq6cFjIIvTkjQ== X-Received: by 2002:adf:ec82:: with SMTP id z2mr5633317wrn.16.1613048364673; Thu, 11 Feb 2021 04:59:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/45] linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE Date: Thu, 11 Feb 2021 12:58:44 +0000 Message-Id: <20210211125900.22777-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is the prctl bit that controls whether syscalls accept tagged addresses. See Documentation/arm64/tagged-address-abi.rst in the linux kernel. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/aarch64/target_syscall.h | 4 ++++ target/arm/cpu-param.h | 3 +++ target/arm/cpu.h | 31 +++++++++++++++++++++++++++++ linux-user/syscall.c | 24 ++++++++++++++++++++++ 4 files changed, 62 insertions(+) diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/targe= t_syscall.h index 3194e6b0093..820601dfcc8 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -30,4 +30,8 @@ struct target_pt_regs { # define TARGET_PR_PAC_APDBKEY (1 << 3) # define TARGET_PR_PAC_APGAKEY (1 << 4) =20 +#define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 +#define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 +# define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) + #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 00e7d9e9377..7f38d33b8ea 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -20,6 +20,9 @@ =20 #ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 12 +# ifdef TARGET_AARCH64 +# define TARGET_TAGGED_ADDRESSES +# endif #else /* * ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f240275407b..72a0819eb8c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -721,6 +721,11 @@ typedef struct CPUARMState { const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ void *gicv3state; + +#ifdef TARGET_TAGGED_ADDRESSES + /* Linux syscall tagged address support */ + bool tagged_addr_enable; +#endif } CPUARMState; =20 static inline void set_feature(CPUARMState *env, int feature) @@ -3604,6 +3609,32 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTx= Attrs *x) */ #define PAGE_BTI PAGE_TARGET_1 =20 +#ifdef TARGET_TAGGED_ADDRESSES +/** + * cpu_untagged_addr: + * @cs: CPU context + * @x: tagged address + * + * Remove any address tag from @x. This is explicitly related to the + * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. + * + * There should be a better place to put this, but we need this in + * include/exec/cpu_ldst.h, and not some place linux-user specific. + */ +static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + if (cpu->env.tagged_addr_enable) { + /* + * TBI is enabled for userspace but not kernelspace addresses. + * Only clear the tag if bit 55 is clear. + */ + x &=3D sextract64(x, 0, 56); + } + return x; +} +#endif + /* * Naming convention for isar_feature functions: * Functions which test 32-bit ID registers should have _aa32_ in diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 24fc1daf023..ba4da7f8a67 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10981,6 +10981,30 @@ static abi_long do_syscall1(void *cpu_env, int num= , abi_long arg1, } } return -TARGET_EINVAL; + case TARGET_PR_SET_TAGGED_ADDR_CTRL: + { + abi_ulong valid_mask =3D TARGET_PR_TAGGED_ADDR_ENABLE; + CPUARMState *env =3D cpu_env; + + if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + env->tagged_addr_enable =3D arg2 & TARGET_PR_TAGGED_ADDR_E= NABLE; + return 0; + } + case TARGET_PR_GET_TAGGED_ADDR_CTRL: + { + abi_long ret =3D 0; + CPUARMState *env =3D cpu_env; + + if (arg2 || arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + if (env->tagged_addr_enable) { + ret |=3D TARGET_PR_TAGGED_ADDR_ENABLE; + } + return ret; + } #endif /* AARCH64 */ case PR_GET_SECCOMP: case PR_SET_SECCOMP: --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050134; cv=none; d=zohomail.com; s=zohoarc; b=es0T1uzsEcliWsD+ItqGG9LPWdhgJt6kGcpo/wmlMwU2PR70xqGV9YkfGicWb4l8IXSTchlEeRtPecfy4rNoU0T5iDJHvKQl6L3JmhknuFFMelJr86ACgjd1iMDwZwKzCC/rnreLXM9zsvkoh+PXOPUdWqg+8o7kdsJw1mwuS6U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613050134; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=B7Md5FuB4zN4GGBUtZ2CBu4dxFI5W4WDEoeLJYQNPbI=; b=VBTJzdH8X/q8l7HwVysfm+kRU7b+XrWA+3oeGe6Ks1gWOhPBYeIrvLNePZc5vkeaCmySRkNWV+XqneKxp6GCFCYVwCw4WBm63m3bHLxqlLjmvegNveiY1ZiMn4Lu2A9KDcA2N1o+Dcu5e5Rj2JhQRLQUCGnKQHeImO7ndol8RAU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613050133779356.3984779897612; Thu, 11 Feb 2021 05:28:53 -0800 (PST) Received: from localhost ([::1]:33084 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lAC1b-00018p-PR for importer@patchew.org; Thu, 11 Feb 2021 08:28:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33732) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZH-0008Mu-Q0 for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:35 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:32802) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZA-00005J-7c for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:35 -0500 Received: by mail-wr1-x42f.google.com with SMTP id 7so4127973wrz.0 for ; Thu, 11 Feb 2021 04:59:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=B7Md5FuB4zN4GGBUtZ2CBu4dxFI5W4WDEoeLJYQNPbI=; b=Y8CxfNgJ54/1UTffvtn8YVEe/+Hdbo25zGnk6xr+mOgN5BOpftZCBNJRZPNiDAwe0W bI9zw2ewcimgnuEluSpqvrzRGFk6IXJVlQ9iYSE2eQ947Gu6Wple7+2HacWdeW13tg0W hYS52iEDCJTxU6qVVPrD8fAQGlGZa7XLKct0Q5LFoPo67lr86yi2+n0uKH0Hqh2ROoD4 imXQAMKgEpMr/7pOuOKuF9f+826ye+jcSBJCXmV9bRIZBRGk3Ed2VOLP0cqcwVQa7Vdw brrNUe2L89ziZbW/cCXy0QQTQDBmvd4OryN8fXtUYuE2nYgRcnJIvGQq6QmNzn9XCU1S LgzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B7Md5FuB4zN4GGBUtZ2CBu4dxFI5W4WDEoeLJYQNPbI=; b=JTm6bVMujAYC77BEf3Bj0sJSnesa6apzwh/ygzGfHPT0RSM1m9j0K1sn3kDafDIyud dPwJ2VdoSW5p05mdz22KMASNc3/Pzo+hgZq9Sd4I3zV72IogbyBtM28K9bbPsaGXAyj3 K/cYue/PzreA0vMheF+0OGktfztJ207uV/gEXlj/OQ33RUIX9ny9IeUbXiz2+1fLiYRA Cz+2X8l6kNoXkzTA678po+MMkNQgJkR6TP0CxWm+knSM0VdR5zjfyuiIaVdyg4wMIGw6 omxLsRzN3sqntlH5qjBZykI10WqRjBy8sSyAQawtmmK/3SNvm4OhGsjmAMVMzgFE6uP5 FD2A== X-Gm-Message-State: AOAM532wvCBSqaZKrsgBisLAqKs2umwM6wba/JAsqeNVzmEp95O5yhOv v8lEuBUiHUdufsY1Q1Oi1wR2R2+R/Ld9Xg== X-Google-Smtp-Source: ABdhPJzlbQ+TJzrM/h8jI5VxFDs4fKClRqnH6TxLGXH2uTGD+TMcT1ajTyfvlL2xwV591DsEjQUGNQ== X-Received: by 2002:a05:6000:1201:: with SMTP id e1mr5808352wrx.14.1613048365368; Thu, 11 Feb 2021 04:59:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/45] target/arm: Improve gen_top_byte_ignore Date: Thu, 11 Feb 2021 12:58:45 +0000 Message-Id: <20210211125900.22777-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use simple arithmetic instead of a conditional move when tbi0 !=3D tbi1. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1c4b8d02f3b..b23a8975d54 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -183,17 +183,20 @@ static void gen_top_byte_ignore(DisasContext *s, TCGv= _i64 dst, /* Sign-extend from bit 55. */ tcg_gen_sextract_i64(dst, src, 0, 56); =20 - if (tbi !=3D 3) { - TCGv_i64 tcg_zero =3D tcg_const_i64(0); - - /* - * The two TBI bits differ. - * If tbi0, then !tbi1: only use the extension if positive. - * if !tbi0, then tbi1: only use the extension if negative. - */ - tcg_gen_movcond_i64(tbi =3D=3D 1 ? TCG_COND_GE : TCG_COND_LT, - dst, dst, tcg_zero, dst, src); - tcg_temp_free_i64(tcg_zero); + switch (tbi) { + case 1: + /* tbi0 but !tbi1: only use the extension if positive */ + tcg_gen_and_i64(dst, dst, src); + break; + case 2: + /* !tbi0 but tbi1: only use the extension if negative */ + tcg_gen_or_i64(dst, dst, src); + break; + case 3: + /* tbi0 and tbi1: always use the extension */ + break; + default: + g_assert_not_reached(); } } } --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050726; cv=none; d=zohomail.com; s=zohoarc; b=ilYyQ2Vl3xzLXAc0aNa4avU6ACvS5q5jt+l5uZbklJRnqXDkBRz+GZ4O2ia85fFp0hXqJuKIZJ3gjIS+/9rVRLI+cWJDKtgnFgwFeOVQWs5pnik770ead4hOvGfrVOR/qd5BOFtNEVJmGIXbmnnyIfYLeHsTqObItz1mQ4PTuds= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613050726; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YgCr6mYaUGxtwKUqfZylaoD+2M0uQDgCb7ALhaIpey0=; b=MrEXaSdypObilt8mlOHNm8ercPx08pT4dZQ2eH8ru1Z3IeiaCgurCwf9eDcViwf996uVcaBbfiTSJ/Hzycg0MG9V11GvCOpEqQ7iBSboDkR3zgyvS61z/Ht0o8oXm7rlBz6Z5NGYVyrjR/cnHCT0mcEq+MtizDgBkAVbkp0ERUA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613050726475396.24265900562807; Thu, 11 Feb 2021 05:38:46 -0800 (PST) Received: from localhost ([::1]:58874 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lACBB-0003vd-De for importer@patchew.org; Thu, 11 Feb 2021 08:38:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33836) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZP-0008Tb-66 for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:43 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:39653) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZA-00005O-9u for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:42 -0500 Received: by mail-wr1-x42b.google.com with SMTP id v1so496579wrd.6 for ; Thu, 11 Feb 2021 04:59:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YgCr6mYaUGxtwKUqfZylaoD+2M0uQDgCb7ALhaIpey0=; b=oF/4Y2Wn0nTcSCtvWLabyVTNXTizCwcoTbWW17/K0gMqDkGGYjKKDRWBcyGTt7z5oz LavH0fxkKXWF+maNPJ13txxxYORfDIDeoY8z453hzQjlDp7XqTMwdTM4XbB1qovBQdk6 tO3MG4xYYA/GF71ilZ+aIZbmyrmGNErTsgvtbiyzI9hHTb7WYJZSqTehyjnNdsA2Zt/B OxoU5PLvy7LOQf9Y/YRsBTe4NURAT6zY0YFedM3EzwtBnld3GMcorD8cgQ9HPZAz5XS4 MtrJq5MYz9D8H3CnorKGxVpJkWfJf3D3yJmqdSgpb2vyof4p52GEmDrMq20Ec+lq/BiO ziiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YgCr6mYaUGxtwKUqfZylaoD+2M0uQDgCb7ALhaIpey0=; b=cI3zstw7PnG1GJBmJ0OR7LQ3wzyh6iGSJVGA40q5BdHUVYHj62MU3u2DNjbgiDPV+A g4xLIJ7nkvDpki3nGeo+nTIKKwN+wg24xzYqruS9ufy1bBMOCJa5Oi+zAMeQTPsjLqj2 FdrSVHC2pYc+C4bF2BCwb1uzvDcH4G/lkp/WZut/brM7YhRUIiUlY957YdiX4jUFDwDh YYXZO5A3l/lTgYu2VA9Qp69RtKUf+/DLlSsYHt1h15861F4qfr9jZLz8NWmTylanvWPc WeWXJRbJcrhczIcnhnxGSrVcDbW2xLaC7/83T63WbPZFEJWbfhoP8iSSJHPFo1xFlUFn KTJQ== X-Gm-Message-State: AOAM531i2L3oEuF0/Nt9CHwaTHO7RI/KORfu1Hs3la+c2ACzCYl0VYUg aGhXXkqBkEtsI0vjhXRWC4TAh8/sBD6vaw== X-Google-Smtp-Source: ABdhPJx0TrrLHU+GO2DpBskKCm/aLhmTNSNTEcUWiVuxBjqBJNEtGFLDpExzgG1YV4Cxr/oI34zsPA== X-Received: by 2002:adf:fe46:: with SMTP id m6mr5693992wrs.92.1613048366066; Thu, 11 Feb 2021 04:59:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/45] target/arm: Use the proper TBI settings for linux-user Date: Thu, 11 Feb 2021 12:58:46 +0000 Message-Id: <20210211125900.22777-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We were fudging TBI1 enabled to speed up the generated code. Now that we've improved the code generation, remove this. Also, tidy the comment to reflect the current code. The pauth test was testing a kernel address (-1) and making incorrect assumptions about TBI1; stick to userland addresses. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 4 ++-- target/arm/cpu.c | 10 +++------- tests/tcg/aarch64/pauth-2.c | 1 - 3 files changed, 5 insertions(+), 10 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index b251fe44506..112bbb14f07 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1425,9 +1425,9 @@ static inline bool tcma_check(uint32_t desc, int bit5= 5, int ptr_tag) */ static inline uint64_t useronly_clean_ptr(uint64_t ptr) { - /* TBI is known to be enabled. */ #ifdef CONFIG_USER_ONLY - ptr =3D sextract64(ptr, 0, 56); + /* TBI0 is known to be enabled, while TBI1 is disabled. */ + ptr &=3D sextract64(ptr, 0, 56); #endif return ptr; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5cf6c056c50..70cfcbc9181 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -205,14 +205,10 @@ static void arm_cpu_reset(DeviceState *dev) env->vfp.zcr_el[1] =3D MIN(cpu->sve_max_vq - 1, 3); } /* - * Enable TBI0 and TBI1. While the real kernel only enables TBI0, - * turning on both here will produce smaller code and otherwise - * make no difference to the user-level emulation. - * - * In sve_probe_page, we assume that this is set. - * Do not modify this without other changes. + * Enable TBI0 but not TBI1. + * Note that this must match useronly_clean_ptr. */ - env->cp15.tcr_el[1].raw_tcr =3D (3ULL << 37); + env->cp15.tcr_el[1].raw_tcr =3D (1ULL << 37); #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { diff --git a/tests/tcg/aarch64/pauth-2.c b/tests/tcg/aarch64/pauth-2.c index 9bba0beb639..978652ede3a 100644 --- a/tests/tcg/aarch64/pauth-2.c +++ b/tests/tcg/aarch64/pauth-2.c @@ -53,7 +53,6 @@ void do_test(uint64_t value) int main() { do_test(0); - do_test(-1); do_test(0xda004acedeadbeefull); return 0; } --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050841; cv=none; d=zohomail.com; s=zohoarc; b=BlY5xvAUZ/U3hMaBoJgxMkKIveRMqPRyadoAna5WQeH9WhtVJ5h9J/sHYIJWSqsPliVofHJSpRAcPsrZRTOoJ+oDZgqafOQRggFyXMWqLV8HWVlnZajdYWdRwFtjOX17BOd/OVx0hPgNfZ4CEcpieLvh2DzUXpFGgUoTHGp4JzU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613050841; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=T4551kNNJ3EgbP/hZlRobuhumCTtrfNVFzhtY4opKq8=; b=hzz33p3uTNleBPooyMGir/HKuP/kztk5mLSqJ3cPdEdbpQCBu6slV+q7Fkg6yOUP1EZB/sDSw0CXMDKPGY2xiGKF6h1R2b1sSUy47f6OQzzzb1GC7KekosPJFrsRN/CX0Mwp/qpGxNQ5scdMHat/VJFUZ1d9SrUmkHZ0hKNxFcQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613050840951777.6085301409312; Thu, 11 Feb 2021 05:40:40 -0800 (PST) Received: from localhost ([::1]:37526 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lACD1-0007Ft-MF for importer@patchew.org; Thu, 11 Feb 2021 08:40:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33764) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZJ-0008O8-LJ for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:37 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:41862) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZA-00005c-9l for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:37 -0500 Received: by mail-wr1-x42f.google.com with SMTP id n6so4073286wrv.8 for ; Thu, 11 Feb 2021 04:59:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=T4551kNNJ3EgbP/hZlRobuhumCTtrfNVFzhtY4opKq8=; b=ozsbo/EXSbZs3jt0vrfFdAj2DoaaoN6TMfT0vhbcWad7gIbnVjVmwjpS6DWAdxSVRv UmN/R/4OWQ4+UU3EWwtoCunp/QS9Dbjcm0Iq97efHLiRrOsAAu6oFCrp43Zzwd4Bg+yE PZLytWvxzI9KGc3BQ/+3WRKQF9E80D2NGjqSjchoFGiJOL81RKd5HSTzjHMLAH3nXkvm s6UbTd1trZG/o28k1mAocluTn3bSRrm1YnLuyMsK9KwxPKFDb4cRp9egXiMz2we0MmHh o3tw+HJMO53ERzvJVkgMl7dRTe6reXWzVPoYpFAk7fDy6Cuo25LGs19eZ1P2X5G9US/V aK/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T4551kNNJ3EgbP/hZlRobuhumCTtrfNVFzhtY4opKq8=; b=pZGFgBTMYZetEpSO6Ga1TJLi0ke+NH16L2fcT4tYPvPN5Qs99QS/HGuyV/nka4hFXe wG9D+vNOY4tHJeEskKn6ACyDdi/H49/9rE230pIHU9BGTH7nvDvC2SqMTGKs+VvDVuM/ IkIc9QFJJJ5HuU1HPA/4EbYnPg/TvDe9/fJG/axkuKDCigD8PknsVDeJINb+3EJujTbm gRLrNYsoWoXfS+7PmjfiqM8OoZChOPUAUSu9SrkytOR9xu5JBmQVNjMQN1RJOAkc7pjR CvbpCvoGmIJ+6tPZr/LFgaR9yOE/0siEyp64XR0lttwxu9U0snMa/GO2K8Tj95LBmLX4 04dA== X-Gm-Message-State: AOAM530TROPwt/vLPve/Mg/2Q1K4nHm1lAeqS4qWtZmnsEhDcsKDe9C+ uVAd1m3TK0etLY4dNv4m5ObzDRuzjqDPAQ== X-Google-Smtp-Source: ABdhPJzF/HDn9+b93CGZ5cN6Te2lCzCdv3euRCe25i4few/hm3Ck/UfqF9iqMENvt54VmVEOULhQXw== X-Received: by 2002:adf:808c:: with SMTP id 12mr5640005wrl.139.1613048366800; Thu, 11 Feb 2021 04:59:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/45] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG Date: Thu, 11 Feb 2021 12:58:47 +0000 Message-Id: <20210211125900.22777-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson These prctl fields are required for the function of MTE. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/aarch64/target_syscall.h | 9 ++++++ linux-user/syscall.c | 43 +++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/targe= t_syscall.h index 820601dfcc8..76f6c3391d3 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -33,5 +33,14 @@ struct target_pt_regs { #define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 #define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 # define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) +/* MTE tag check fault modes */ +# define TARGET_PR_MTE_TCF_SHIFT 1 +# define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT) +# define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT) +# define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT) +# define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT) +/* MTE tag inclusion mask */ +# define TARGET_PR_MTE_TAG_SHIFT 3 +# define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIF= T) =20 #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index ba4da7f8a67..61bf6148e7f 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10985,17 +10985,53 @@ static abi_long do_syscall1(void *cpu_env, int nu= m, abi_long arg1, { abi_ulong valid_mask =3D TARGET_PR_TAGGED_ADDR_ENABLE; CPUARMState *env =3D cpu_env; + ARMCPU *cpu =3D env_archcpu(env); + + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |=3D TARGET_PR_MTE_TCF_MASK; + valid_mask |=3D TARGET_PR_MTE_TAG_MASK; + } =20 if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) { return -TARGET_EINVAL; } env->tagged_addr_enable =3D arg2 & TARGET_PR_TAGGED_ADDR_E= NABLE; + + if (cpu_isar_feature(aa64_mte, cpu)) { + switch (arg2 & TARGET_PR_MTE_TCF_MASK) { + case TARGET_PR_MTE_TCF_NONE: + case TARGET_PR_MTE_TCF_SYNC: + case TARGET_PR_MTE_TCF_ASYNC: + break; + default: + return -EINVAL; + } + + /* + * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. + * Note that the syscall values are consistent with hw. + */ + env->cp15.sctlr_el[1] =3D + deposit64(env->cp15.sctlr_el[1], 38, 2, + arg2 >> TARGET_PR_MTE_TCF_SHIFT); + + /* + * Write PR_MTE_TAG to GCR_EL1[Exclude]. + * Note that the syscall uses an include mask, + * and hardware uses an exclude mask -- invert. + */ + env->cp15.gcr_el1 =3D + deposit64(env->cp15.gcr_el1, 0, 16, + ~arg2 >> TARGET_PR_MTE_TAG_SHIFT); + arm_rebuild_hflags(env); + } return 0; } case TARGET_PR_GET_TAGGED_ADDR_CTRL: { abi_long ret =3D 0; CPUARMState *env =3D cpu_env; + ARMCPU *cpu =3D env_archcpu(env); =20 if (arg2 || arg3 || arg4 || arg5) { return -TARGET_EINVAL; @@ -11003,6 +11039,13 @@ static abi_long do_syscall1(void *cpu_env, int num= , abi_long arg1, if (env->tagged_addr_enable) { ret |=3D TARGET_PR_TAGGED_ADDR_ENABLE; } + if (cpu_isar_feature(aa64_mte, cpu)) { + /* See above. */ + ret |=3D (extract64(env->cp15.sctlr_el[1], 38, 2) + << TARGET_PR_MTE_TCF_SHIFT); + ret =3D deposit64(ret, TARGET_PR_MTE_TAG_SHIFT, 16, + ~env->cp15.gcr_el1); + } return ret; } #endif /* AARCH64 */ --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Td1SZqricVmJobvnC2bV9MTlMvXZFc8dAKhtITA+Nog=; b=INIaVQdvx12S40AoN+MoZHO4IHLz+RenMAJAuVBEqNAnAw1jaz1/O2S1kkkuA3AQ50 4YLaucptuTK02ITnbSMnYYFBH89M2scQnGpxQ9X8GxF9aNkIq2ETEVLx0BA8j4Y0AdAB sXm2tLlH3/tMSNSdkNjMEleThLoZqUKjlgEKDYQQEUQtxzR0YWxhtxD3d7rEwrkMFmny hQIQR+bzwh85zSoSLLyIZmRFsiTBLNm81NgiGSLvTuOGhbgant2HD8H8XFyuBPMgfN/M BJEWU8VCF6tSWBrwQmqZNkFSTQka95uYL+TXXFQosvZdWiO4q34dMAccCViVERUl9bfG TiHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Td1SZqricVmJobvnC2bV9MTlMvXZFc8dAKhtITA+Nog=; b=C3bX9fhhpipQby5Ckc+7H3OEJH//0NcUkf6DBtAX9RMTGzOjiufwVN10nkHrD450BK YFxQe7ip3kUIkF4GYPOhtvgDLAKSgUfFKzwXaw0ITPOTmzUctI0GwxSlAdUY+Zw3sU+/ C/fH5HnysChFVRlOI1INYsq/v0uCljpFDRKYC3rZGDGuGtm4Tn20+NNtohz0a8Tn5O7v rGlKHihXbqUtXp3ZbvQfJbDF0ReZGiSv8VlLXmELLJdlLMq1aYXQIREqUXc0ydlqMQm9 HSi2GlHtvRh8Fxs9cic/jZMe5rgJBJfN5nNudwPdeIkaoWify3+3obSzVMGrtU5eeMRq HRMQ== X-Gm-Message-State: AOAM533OPGqvZQ4WYtKXrrSnQLoWEJnNp9dCypscdvLFhdrdDoFzMjf1 pbQvD8ZQaHNlG/XKTphPe+Ab9xxiGJjdUQ== X-Google-Smtp-Source: ABdhPJw3aOzxG97IatOnnQNABcwvj7I075/igALUdmvV5TyLxOCWtuMEinjffaWkwQRHttYYlag4hQ== X-Received: by 2002:a05:6000:2aa:: with SMTP id l10mr5618867wry.368.1613048367499; Thu, 11 Feb 2021 04:59:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/45] linux-user/aarch64: Implement PROT_MTE Date: Thu, 11 Feb 2021 12:58:48 +0000 Message-Id: <20210211125900.22777-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Remember the PROT_MTE bit as PAGE_MTE/PAGE_TARGET_2. Otherwise this does not yet have effect. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu-all.h | 1 + linux-user/syscall_defs.h | 1 + target/arm/cpu.h | 1 + linux-user/mmap.c | 22 ++++++++++++++-------- 4 files changed, 17 insertions(+), 8 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index d6ad774c015..09b9be845d1 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -284,6 +284,7 @@ extern intptr_t qemu_host_page_mask; #endif /* Target-specific bits that will be used via page_get_flags(). */ #define PAGE_TARGET_1 0x0080 +#define PAGE_TARGET_2 0x0200 =20 #if defined(CONFIG_USER_ONLY) void page_dump(FILE *f); diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index f98c1c1c8de..46a960fccb4 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -1311,6 +1311,7 @@ struct target_winsize { =20 #ifdef TARGET_AARCH64 #define TARGET_PROT_BTI 0x10 +#define TARGET_PROT_MTE 0x20 #endif =20 /* Common */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 72a0819eb8c..efa1618c4d5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3608,6 +3608,7 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxA= ttrs *x) * AArch64 usage of the PAGE_TARGET_* bits for linux-user. */ #define PAGE_BTI PAGE_TARGET_1 +#define PAGE_MTE PAGE_TARGET_2 =20 #ifdef TARGET_TAGGED_ADDRESSES /** diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 6690384752f..85e218ab1d0 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -84,18 +84,24 @@ static int validate_prot_to_pageflags(int *host_prot, i= nt prot) | (prot & PROT_EXEC ? PROT_READ : 0); =20 #ifdef TARGET_AARCH64 - /* - * The PROT_BTI bit is only accepted if the cpu supports the feature. - * Since this is the unusual case, don't bother checking unless - * the bit has been requested. If set and valid, record the bit - * within QEMU's page_flags. - */ - if (prot & TARGET_PROT_BTI) { + { ARMCPU *cpu =3D ARM_CPU(thread_cpu); - if (cpu_isar_feature(aa64_bti, cpu)) { + + /* + * The PROT_BTI bit is only accepted if the cpu supports the featu= re. + * Since this is the unusual case, don't bother checking unless + * the bit has been requested. If set and valid, record the bit + * within QEMU's page_flags. + */ + if ((prot & TARGET_PROT_BTI) && cpu_isar_feature(aa64_bti, cpu)) { valid |=3D TARGET_PROT_BTI; page_flags |=3D PAGE_BTI; } + /* Similarly for the PROT_MTE bit. */ + if ((prot & TARGET_PROT_MTE) && cpu_isar_feature(aa64_mte, cpu)) { + valid |=3D TARGET_PROT_MTE; + page_flags |=3D PAGE_MTE; + } } #endif =20 --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050980; cv=none; d=zohomail.com; s=zohoarc; b=V4JW3nAy2mgXrEWfB01B6ViFhdZh7NVAPeIL7yxTltMP5Ue4s2k59zJ5naWqKspn2v5lqb0M4MB5lZIMEiLUXX+yc5hV2L3fjmVtgswg8jKURTMlj8MN1GIg42n7Aj3v/t3LJTDmU3h9RH6E/JqFEW5EcdcmohZMHnJCTSm1OJQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613050980; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ijaQagooHuIH5z5NGwZXJPms0B2RYsBAzhVKOPfgUV4=; b=G6sHl6EwtuRTci1tl+izzXL2hBU8+Y7ll/TRLE7D0C5vc3LQiwvSZtotpsSW2h5N4Uz55N8oZZTgVs6lrOF9PDWEt9KM/t6A+2NDIPne3JeRCYJXrjDpRCqnFU06w70dBIA3igNdQ41yapFilrQidPlarLbQPFNar+NDe3gjm8k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613050980062351.269443926613; Thu, 11 Feb 2021 05:43:00 -0800 (PST) Received: from localhost ([::1]:45608 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lACFG-0002GP-JZ for importer@patchew.org; Thu, 11 Feb 2021 08:42:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33796) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZL-0008Ot-Vu for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:41 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:37274) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZC-00005r-7M for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:38 -0500 Received: by mail-wm1-x32c.google.com with SMTP id m1so5643594wml.2 for ; Thu, 11 Feb 2021 04:59:29 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ijaQagooHuIH5z5NGwZXJPms0B2RYsBAzhVKOPfgUV4=; b=kqDojDyWUBWCkGSMErBDRKwRgqsTEFBUVmFn2TN9d1eG/bVwILmj6zKbg+o8Gxz67T Vsx984iGlbSikidylYcsG3q9gWAUoSzVNDHxcDmQphXHVVwqtAysauORkfvv4GEwuQ4p 9mzD2q7tKBHHMG01q77luG79WNDHf9CY/Kzoy4AEBRW084NR/QU62pQXyMX/ZmVrvY0V VUpFaL5Wm7ewRv250rPGU4i07HpDWYLALxuwluMxegOJOvIMc85Cu4zIxSAYVrrAMVm4 0YhuikCzV7yGmFgXgY9/KfW51H60F39WdrWuroZ2S0J89rIJNVJHN7Zcd1HDDnv2E5C6 n2Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ijaQagooHuIH5z5NGwZXJPms0B2RYsBAzhVKOPfgUV4=; b=cV6K2NxtR9U60gzMpWn6Es/el/xX7RO9rDvno7gdAfLT4FfJXLDuMQvjNnh7URxs1C AdwXWXDYWUYgsykeL8dof1ZeGAFWSndBE8ovPJFBK2vd1a1NGAJLVQzLTDBOWV1aqu9V 8CW5xkFCo8gtbJ22rZC4e8QSfzwK6Ci8hnpHnQE3c+aySfgMstB88+Wvf79jtocj/nQp goMdLZvGyyW2BIr+Nrtr311a6QWyhW/Cmf7s5xHfjPSbmeI51N62pjnzZgE1yTFaoIFB OlYPhyMKvXWxdAu+zfqavvD7RYoKhsAEAvGa6bMiYrAelNnSfj44GNb3TbPUWyDNVC8O 7jjQ== X-Gm-Message-State: AOAM531W1ZoNC7fxukRWeydkEDSjzsPquwabaIiOBj/Pf627KnZT1Fld qGLGV4zu3JpQVgrtppKBHyGv7yORMDybBA== X-Google-Smtp-Source: ABdhPJy89TfT6Jk2UDLvfynpSn91Wn82UBcnQntYm5wIeSDAMJYizjvrDd2LlshAtyNqdZ9ucm2f9A== X-Received: by 2002:a05:600c:204e:: with SMTP id p14mr5064633wmg.157.1613048368423; Thu, 11 Feb 2021 04:59:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/45] target/arm: Split out syndrome.h from internals.h Date: Thu, 11 Feb 2021 12:58:49 +0000 Message-Id: <20210211125900.22777-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Move everything related to syndromes to a new file, which can be shared with linux-user. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 245 +----------------------------------- target/arm/syndrome.h | 273 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 274 insertions(+), 244 deletions(-) create mode 100644 target/arm/syndrome.h diff --git a/target/arm/internals.h b/target/arm/internals.h index 112bbb14f07..c38d5410175 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -26,6 +26,7 @@ #define TARGET_ARM_INTERNALS_H =20 #include "hw/registerfields.h" +#include "syndrome.h" =20 /* register banks for CPU modes */ #define BANK_USRSYS 0 @@ -262,250 +263,6 @@ static inline bool extended_addresses_enabled(CPUARMS= tate *env) (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EA= E)); } =20 -/* Valid Syndrome Register EC field values */ -enum arm_exception_class { - EC_UNCATEGORIZED =3D 0x00, - EC_WFX_TRAP =3D 0x01, - EC_CP15RTTRAP =3D 0x03, - EC_CP15RRTTRAP =3D 0x04, - EC_CP14RTTRAP =3D 0x05, - EC_CP14DTTRAP =3D 0x06, - EC_ADVSIMDFPACCESSTRAP =3D 0x07, - EC_FPIDTRAP =3D 0x08, - EC_PACTRAP =3D 0x09, - EC_CP14RRTTRAP =3D 0x0c, - EC_BTITRAP =3D 0x0d, - EC_ILLEGALSTATE =3D 0x0e, - EC_AA32_SVC =3D 0x11, - EC_AA32_HVC =3D 0x12, - EC_AA32_SMC =3D 0x13, - EC_AA64_SVC =3D 0x15, - EC_AA64_HVC =3D 0x16, - EC_AA64_SMC =3D 0x17, - EC_SYSTEMREGISTERTRAP =3D 0x18, - EC_SVEACCESSTRAP =3D 0x19, - EC_INSNABORT =3D 0x20, - EC_INSNABORT_SAME_EL =3D 0x21, - EC_PCALIGNMENT =3D 0x22, - EC_DATAABORT =3D 0x24, - EC_DATAABORT_SAME_EL =3D 0x25, - EC_SPALIGNMENT =3D 0x26, - EC_AA32_FPTRAP =3D 0x28, - EC_AA64_FPTRAP =3D 0x2c, - EC_SERROR =3D 0x2f, - EC_BREAKPOINT =3D 0x30, - EC_BREAKPOINT_SAME_EL =3D 0x31, - EC_SOFTWARESTEP =3D 0x32, - EC_SOFTWARESTEP_SAME_EL =3D 0x33, - EC_WATCHPOINT =3D 0x34, - EC_WATCHPOINT_SAME_EL =3D 0x35, - EC_AA32_BKPT =3D 0x38, - EC_VECTORCATCH =3D 0x3a, - EC_AA64_BKPT =3D 0x3c, -}; - -#define ARM_EL_EC_SHIFT 26 -#define ARM_EL_IL_SHIFT 25 -#define ARM_EL_ISV_SHIFT 24 -#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) -#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) - -static inline uint32_t syn_get_ec(uint32_t syn) -{ - return syn >> ARM_EL_EC_SHIFT; -} - -/* Utility functions for constructing various kinds of syndrome value. - * Note that in general we follow the AArch64 syndrome values; in a - * few cases the value in HSR for exceptions taken to AArch32 Hyp - * mode differs slightly, and we fix this up when populating HSR in - * arm_cpu_do_interrupt_aarch32_hyp(). - * The exception is FP/SIMD access traps -- these report extra information - * when taking an exception to AArch32. For those we include the extra cop= roc - * and TA fields, and mask them out when taking the exception to AArch64. - */ -static inline uint32_t syn_uncategorized(void) -{ - return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; -} - -static inline uint32_t syn_aa64_svc(uint32_t imm16) -{ - return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa64_hvc(uint32_t imm16) -{ - return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa64_smc(uint32_t imm16) -{ - return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) -{ - return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) - | (is_16bit ? 0 : ARM_EL_IL); -} - -static inline uint32_t syn_aa32_hvc(uint32_t imm16) -{ - return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa32_smc(void) -{ - return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; -} - -static inline uint32_t syn_aa64_bkpt(uint32_t imm16) -{ - return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff= ); -} - -static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) -{ - return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) - | (is_16bit ? 0 : ARM_EL_IL); -} - -static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, - int crn, int crm, int rt, - int isread) -{ - return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL - | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) - | (crm << 1) | isread; -} - -static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int op= c2, - int crn, int crm, int rt, int isre= ad, - bool is_16bit) -{ - return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) - | (crn << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int op= c2, - int crn, int crm, int rt, int isre= ad, - bool is_16bit) -{ - return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) - | (crn << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int c= rm, - int rt, int rt2, int isread, - bool is_16bit) -{ - return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc1 << 16) - | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int c= rm, - int rt, int rt2, int isread, - bool is_16bit) -{ - return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc1 << 16) - | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) -{ - /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA =3D=3D 0 coproc =3D= =3D 0xa */ - return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | 0xa; -} - -static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bi= t) -{ - /* AArch32 SIMD trap: TA =3D=3D 1 coproc =3D=3D 0 */ - return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (1 << 5); -} - -static inline uint32_t syn_sve_access_trap(void) -{ - return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; -} - -static inline uint32_t syn_pactrap(void) -{ - return EC_PACTRAP << ARM_EL_EC_SHIFT; -} - -static inline uint32_t syn_btitrap(int btype) -{ - return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; -} - -static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int = fsc) -{ - return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; -} - -static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, - int ea, int cm, int s1ptw, - int wnr, int fsc) -{ - return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL - | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) - | (wnr << 6) | fsc; -} - -static inline uint32_t syn_data_abort_with_iss(int same_el, - int sas, int sse, int srt, - int sf, int ar, - int ea, int cm, int s1ptw, - int wnr, int fsc, - bool is_16bit) -{ - return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) - | (sf << 15) | (ar << 14) - | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; -} - -static inline uint32_t syn_swstep(int same_el, int isv, int ex) -{ - return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SH= IFT) - | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; -} - -static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) -{ - return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIF= T) - | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; -} - -static inline uint32_t syn_breakpoint(int same_el) -{ - return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIF= T) - | ARM_EL_IL | 0x22; -} - -static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) -{ - return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | - (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | - (cv << 24) | (cond << 20) | ti; -} - /* Update a QEMU watchpoint based on the information the guest has set in = the * DBGWCR_EL1 and DBGWVR_EL1 registers. */ diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h new file mode 100644 index 00000000000..39a31260f2d --- /dev/null +++ b/target/arm/syndrome.h @@ -0,0 +1,273 @@ +/* + * QEMU ARM CPU -- syndrome functions and types + * + * Copyright (c) 2014 Linaro Ltd + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + * + * This header defines functions, types, etc which need to be shared + * between different source files within target/arm/ but which are + * private to it and not required by the rest of QEMU. + */ + +#ifndef TARGET_ARM_SYNDROME_H +#define TARGET_ARM_SYNDROME_H + +/* Valid Syndrome Register EC field values */ +enum arm_exception_class { + EC_UNCATEGORIZED =3D 0x00, + EC_WFX_TRAP =3D 0x01, + EC_CP15RTTRAP =3D 0x03, + EC_CP15RRTTRAP =3D 0x04, + EC_CP14RTTRAP =3D 0x05, + EC_CP14DTTRAP =3D 0x06, + EC_ADVSIMDFPACCESSTRAP =3D 0x07, + EC_FPIDTRAP =3D 0x08, + EC_PACTRAP =3D 0x09, + EC_CP14RRTTRAP =3D 0x0c, + EC_BTITRAP =3D 0x0d, + EC_ILLEGALSTATE =3D 0x0e, + EC_AA32_SVC =3D 0x11, + EC_AA32_HVC =3D 0x12, + EC_AA32_SMC =3D 0x13, + EC_AA64_SVC =3D 0x15, + EC_AA64_HVC =3D 0x16, + EC_AA64_SMC =3D 0x17, + EC_SYSTEMREGISTERTRAP =3D 0x18, + EC_SVEACCESSTRAP =3D 0x19, + EC_INSNABORT =3D 0x20, + EC_INSNABORT_SAME_EL =3D 0x21, + EC_PCALIGNMENT =3D 0x22, + EC_DATAABORT =3D 0x24, + EC_DATAABORT_SAME_EL =3D 0x25, + EC_SPALIGNMENT =3D 0x26, + EC_AA32_FPTRAP =3D 0x28, + EC_AA64_FPTRAP =3D 0x2c, + EC_SERROR =3D 0x2f, + EC_BREAKPOINT =3D 0x30, + EC_BREAKPOINT_SAME_EL =3D 0x31, + EC_SOFTWARESTEP =3D 0x32, + EC_SOFTWARESTEP_SAME_EL =3D 0x33, + EC_WATCHPOINT =3D 0x34, + EC_WATCHPOINT_SAME_EL =3D 0x35, + EC_AA32_BKPT =3D 0x38, + EC_VECTORCATCH =3D 0x3a, + EC_AA64_BKPT =3D 0x3c, +}; + +#define ARM_EL_EC_SHIFT 26 +#define ARM_EL_IL_SHIFT 25 +#define ARM_EL_ISV_SHIFT 24 +#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) +#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) + +static inline uint32_t syn_get_ec(uint32_t syn) +{ + return syn >> ARM_EL_EC_SHIFT; +} + +/* + * Utility functions for constructing various kinds of syndrome value. + * Note that in general we follow the AArch64 syndrome values; in a + * few cases the value in HSR for exceptions taken to AArch32 Hyp + * mode differs slightly, and we fix this up when populating HSR in + * arm_cpu_do_interrupt_aarch32_hyp(). + * The exception is FP/SIMD access traps -- these report extra information + * when taking an exception to AArch32. For those we include the extra cop= roc + * and TA fields, and mask them out when taking the exception to AArch64. + */ +static inline uint32_t syn_uncategorized(void) +{ + return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + +static inline uint32_t syn_aa64_svc(uint32_t imm16) +{ + return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa64_hvc(uint32_t imm16) +{ + return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa64_smc(uint32_t imm16) +{ + return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) +{ + return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) + | (is_16bit ? 0 : ARM_EL_IL); +} + +static inline uint32_t syn_aa32_hvc(uint32_t imm16) +{ + return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa32_smc(void) +{ + return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + +static inline uint32_t syn_aa64_bkpt(uint32_t imm16) +{ + return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff= ); +} + +static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) +{ + return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) + | (is_16bit ? 0 : ARM_EL_IL); +} + +static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, + int crn, int crm, int rt, + int isread) +{ + return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL + | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) + | (crm << 1) | isread; +} + +static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int op= c2, + int crn, int crm, int rt, int isre= ad, + bool is_16bit) +{ + return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) + | (crn << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int op= c2, + int crn, int crm, int rt, int isre= ad, + bool is_16bit) +{ + return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) + | (crn << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int c= rm, + int rt, int rt2, int isread, + bool is_16bit) +{ + return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc1 << 16) + | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int c= rm, + int rt, int rt2, int isread, + bool is_16bit) +{ + return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc1 << 16) + | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) +{ + /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA =3D=3D 0 coproc =3D= =3D 0xa */ + return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | 0xa; +} + +static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bi= t) +{ + /* AArch32 SIMD trap: TA =3D=3D 1 coproc =3D=3D 0 */ + return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (1 << 5); +} + +static inline uint32_t syn_sve_access_trap(void) +{ + return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; +} + +static inline uint32_t syn_pactrap(void) +{ + return EC_PACTRAP << ARM_EL_EC_SHIFT; +} + +static inline uint32_t syn_btitrap(int btype) +{ + return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; +} + +static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int = fsc) +{ + return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; +} + +static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, + int ea, int cm, int s1ptw, + int wnr, int fsc) +{ + return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL + | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) + | (wnr << 6) | fsc; +} + +static inline uint32_t syn_data_abort_with_iss(int same_el, + int sas, int sse, int srt, + int sf, int ar, + int ea, int cm, int s1ptw, + int wnr, int fsc, + bool is_16bit) +{ + return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) + | (sf << 15) | (ar << 14) + | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; +} + +static inline uint32_t syn_swstep(int same_el, int isv, int ex) +{ + return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SH= IFT) + | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; +} + +static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) +{ + return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIF= T) + | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; +} + +static inline uint32_t syn_breakpoint(int same_el) +{ + return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIF= T) + | ARM_EL_IL | 0x22; +} + +static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) +{ + return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | + (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | + (cv << 24) | (cond << 20) | ti; +} + +#endif /* TARGET_ARM_SYNDROME_H */ --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613051042; cv=none; d=zohomail.com; s=zohoarc; b=j5aDqKzpeXBYVUZUwcgrVGpd468pT8qqociJvbUKOtn3si6aWu1J4cUPwy7oT9lpWik4z31BHL5dNimIsMLrDrDMExh96MzcFVkNx9VlsSTffdJj6i6xNB6yUlMSeQlvNbHrEZpMA5abUj/LviVMCN48jJXXlVAbMHUMceeLiFw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613051042; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wZUolxBc97njL0lUBedVjqcYfU8uIXWcGrJqQadqG7M=; b=gxZkbQIhfZhsYzP3Jg+mePLbi/LXnYCIuG4fInZfd3SXE0du450/qGpVdQp786WBDbBW6pfvfrX0zzTnkPTESfKHy7FJhyKpA9+jjAPY6jDw2pB0wpq3Mg1BulOCDYy0iazeH7K0A8pZvhyCidzKFcV1waFNt66XDtXD30ZaYJk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613051042486653.7822281379938; Thu, 11 Feb 2021 05:44:02 -0800 (PST) Received: from localhost ([::1]:48762 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lACGH-0003Z8-D7 for importer@patchew.org; Thu, 11 Feb 2021 08:44:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33832) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZO-0008SY-O8 for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:42 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:36248) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZC-000063-CO for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:42 -0500 Received: by mail-wm1-x32c.google.com with SMTP id i9so5657731wmq.1 for ; Thu, 11 Feb 2021 04:59:29 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wZUolxBc97njL0lUBedVjqcYfU8uIXWcGrJqQadqG7M=; b=IoONwXUwGjSsPuAjYcgychdX4rQmHYitaIMggLllmI04rABdVQ/JUxpI38cQdQTe71 4ap99bYqnGxp5Fl2SvQT9zomqx0E9UGQkMYkYVqjuSbP+riOSXbK0zJwt6ZXck+plHS7 qBGm3diggWfhQPkov9l5G/SSwNMO1s+CVTIkzwio5fwwZe0uTUYp0Dx/ECCZpD4sT3kg PA8e2DEAjKFSyeJBo8NOViblePHU5NWzjlPvEzfktPZnzp2+2Mjqfi09Ab9C9g3cxZHh BM2yby0arozvQW6XuY5ni3Zuh0L4dmr/P6ihQtD7VZJ0RpmPAc0vpUt7hnYpZtdsYpsr c+pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wZUolxBc97njL0lUBedVjqcYfU8uIXWcGrJqQadqG7M=; b=WVTI5rxlw4rqQUBtLPGl6uRHypEqBBgbmYYX/UimxVSXH9BHrojEA9UaTTuJ4XZXmU HvapuNIx9/1mvP42ilSlwESvxXGTYvhH6+qPPnlQsCDyvd99WaAo1qFgN2lqcNGB9lEE tPoRD0M06OH6WWBAOkzV9qabH44tYGNcxM5nnJx11uN8BqZh8CSarfciB0C1vJgaK2IW guMKWOXduNiXga38bPTOHDOFJSC+zdpbPqwnv6VcGjWFv+JvwRA+1NJp4nghIc/sEFym NGvLaklLz14qHyD6avra8o2sFjhNYcXMvDjsxPwQeO/2Dm0DNXZqStJ20kegHqQrhT58 2E8w== X-Gm-Message-State: AOAM533K9jod3v/lJRVfQWAvARfPFmZbEG/H6g/lAOW6f37vxyXCQSR5 k0vcbT0kZ1qI6xgLLUaEGPxwuIRmyRz6Ig== X-Google-Smtp-Source: ABdhPJwzU2unVxIDLEVOjBl5e53MnqDF0FdvY1DevZLVbBdnuzn5jsZMEVPOCnFGcJ0fnys7UiiVQQ== X-Received: by 2002:a1c:6402:: with SMTP id y2mr4985436wmb.43.1613048369120; Thu, 11 Feb 2021 04:59:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/45] linux-user/aarch64: Pass syndrome to EXC_*_ABORT Date: Thu, 11 Feb 2021 12:58:50 +0000 Message-Id: <20210211125900.22777-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson A proper syndrome is required to fill in the proper si_code. Use page_get_flags to determine permission vs translation for user-only. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-27-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/aarch64/cpu_loop.c | 24 +++++++++++++++++++++--- target/arm/tlb_helper.c | 15 +++++++++------ 2 files changed, 30 insertions(+), 9 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 42b9c15f536..4e43906e66a 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -23,6 +23,7 @@ #include "cpu_loop-common.h" #include "qemu/guest-random.h" #include "hw/semihosting/common-semi.h" +#include "target/arm/syndrome.h" =20 #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r =3D get_user_u32((x), (gaddr)); \ @@ -76,7 +77,7 @@ void cpu_loop(CPUARMState *env) { CPUState *cs =3D env_cpu(env); - int trapnr; + int trapnr, ec, fsc; abi_long ret; target_siginfo_t info; =20 @@ -117,9 +118,26 @@ void cpu_loop(CPUARMState *env) case EXCP_DATA_ABORT: info.si_signo =3D TARGET_SIGSEGV; info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; info._sifields._sigfault._addr =3D env->exception.vaddress; + + /* We should only arrive here with EC in {DATAABORT, INSNABORT= }. */ + ec =3D syn_get_ec(env->exception.syndrome); + assert(ec =3D=3D EC_DATAABORT || ec =3D=3D EC_INSNABORT); + + /* Both EC have the same format for FSC, or close enough. */ + fsc =3D extract32(env->exception.syndrome, 0, 6); + switch (fsc) { + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + info.si_code =3D TARGET_SEGV_MAPERR; + break; + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + info.si_code =3D TARGET_SEGV_ACCERR; + break; + default: + g_assert_not_reached(); + } + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_DEBUG: diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index df85079d9f0..9609333cbdf 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -154,21 +154,24 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr) { ARMCPU *cpu =3D ARM_CPU(cs); + ARMMMUFaultInfo fi =3D {}; =20 #ifdef CONFIG_USER_ONLY - cpu->env.exception.vaddress =3D address; - if (access_type =3D=3D MMU_INST_FETCH) { - cs->exception_index =3D EXCP_PREFETCH_ABORT; + int flags =3D page_get_flags(useronly_clean_ptr(address)); + if (flags & PAGE_VALID) { + fi.type =3D ARMFault_Permission; } else { - cs->exception_index =3D EXCP_DATA_ABORT; + fi.type =3D ARMFault_Translation; } - cpu_loop_exit_restore(cs, retaddr); + + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); #else hwaddr phys_addr; target_ulong page_size; int prot, ret; MemTxAttrs attrs =3D {}; - ARMMMUFaultInfo fi =3D {}; ARMCacheAttrs cacheattrs =3D {}; =20 /* --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-28-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/aarch64/target_signal.h | 2 ++ linux-user/aarch64/cpu_loop.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target= _signal.h index ddd73169f0f..777fb667fea 100644 --- a/linux-user/aarch64/target_signal.h +++ b/linux-user/aarch64/target_signal.h @@ -21,5 +21,7 @@ typedef struct target_sigaltstack { =20 #include "../generic/signal.h" =20 +#define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */ + #define TARGET_ARCH_HAS_SETUP_FRAME #endif /* AARCH64_TARGET_SIGNAL_H */ diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 4e43906e66a..b6a2e65593f 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -134,6 +134,9 @@ void cpu_loop(CPUARMState *env) case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ info.si_code =3D TARGET_SEGV_ACCERR; break; + case 0x11: /* Synchronous Tag Check Fault */ + info.si_code =3D TARGET_SEGV_MTESERR; + break; default: g_assert_not_reached(); } --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613051333; cv=none; d=zohomail.com; s=zohoarc; b=XNYoXduHAQvjHhP1pjamo2bv9aHaRVMbF8rHC56xBOqMmW4SHZDj7YYoG/QCLWhVX4bWmtfDBrc1Yc+KbDFAj3rXvCQvg4StTGbnqj9ZzRbPyN5vu3shZ6BpTRWZWNil2D8PEFWaLT6B51VN2D1wEqYFaN/mxQYuosf8h0maU3A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613051333; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7J6XWT7lnNznOqQ/E74q/yJaH9LSrrM5aTsBvvX3CmU=; b=Zx12nGz8AeQ93lavA+WXPikyzHmyD/AU9+okXdnG/mcuOsFhLcVZFoyYqHlLcTTZnn KnKYx916Y8VFG2+cQfyxZ5zRl+cBJrRe0mFbnsaZwtotcnXY5suhye0B3vAPN6hArUPc 3xwBwNQBFaMKK9/04JyBv501txbO5bnUl4THMIVGAG1h9A04Aftyai9Z6VmZ8wJIryWo bUqfznN4cFbka/Q5uQzP4XY8m4Yy5un4ze3AVREXmE8W+iqlRvqaOqJNG76kk+ifQpHS CW175xOIf6AfLZ0lhSdkBLQnKk/n8uhghcvbbdpmJ2Q734Ko7fRzk3PlhOpbr2duRJKC ioew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7J6XWT7lnNznOqQ/E74q/yJaH9LSrrM5aTsBvvX3CmU=; b=KQaERaq/zvFLWodQlbMHY523uvqFlh21niCV4kKw2fBtOJxu9CXhwUX5BRsymFk5qO lEIQefm/XWYBo0SRRE3viouFWijSRleKx+hZ/sFC1DxuY6U4RqmLPbHCGkNNHHc4s2KH G15HvffqNXV0bIQBxFpotgxJzuCef9jxeQ4CTFeYjr603sShBcqcHVdFwgtEMiDZAp6m cXoYwSEBHSPFvPyj4ItUK402VcrPjQbWoZLxmOQmet/1fNnaJvMYW5hWMXwAOt8IzbZH NECEFBWa5xyeovMXVQGGG096JrtujnCbfiC7b6o4CIJyoia1Pmoo0FtN2ewknt7ZAy0u kuUQ== X-Gm-Message-State: AOAM5325RreHtCblKLk70qRx4ch9GPg4SR8AkwZhOufAstxFlhDHTo+C V27mK2jQJNyCTawCVoBp/11De77Ly0+MkQ== X-Google-Smtp-Source: ABdhPJxoMDFuuaZ4X+rAiFNOIfLv09nZliubhENDSrVv9oUoZuZBP9wgnhkIDcucCQx0UlMhHTXQDA== X-Received: by 2002:adf:de11:: with SMTP id b17mr689120wrm.225.1613048370454; Thu, 11 Feb 2021 04:59:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/45] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error Date: Thu, 11 Feb 2021 12:58:52 +0000 Message-Id: <20210211125900.22777-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson The real kernel collects _TIF_MTE_ASYNC_FAULT into the current thread's state on any kernel entry (interrupt, exception etc), and then delivers the signal in advance of resuming the thread. This means that while the signal won't be delivered immediately, it will not be delayed forever -- at minimum it will be delivered after the next clock interrupt. We don't have a clock interrupt in linux-user, so we issue a cpu_kick to signal a return to the main loop at the end of the current TB. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/aarch64/target_signal.h | 1 + linux-user/aarch64/cpu_loop.c | 11 +++++++++++ target/arm/mte_helper.c | 10 ++++++++++ 3 files changed, 22 insertions(+) diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target= _signal.h index 777fb667fea..18013e1b235 100644 --- a/linux-user/aarch64/target_signal.h +++ b/linux-user/aarch64/target_signal.h @@ -21,6 +21,7 @@ typedef struct target_sigaltstack { =20 #include "../generic/signal.h" =20 +#define TARGET_SEGV_MTEAERR 8 /* Asynchronous ARM MTE error */ #define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */ =20 #define TARGET_ARCH_HAS_SETUP_FRAME diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index b6a2e65593f..7c42f657068 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -164,6 +164,17 @@ void cpu_loop(CPUARMState *env) EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\= n", trapnr); abort(); } + + /* Check for MTE asynchronous faults */ + if (unlikely(env->cp15.tfsr_el[0])) { + env->cp15.tfsr_el[0] =3D 0; + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info._sifields._sigfault._addr =3D 0; + info.si_code =3D TARGET_SEGV_MTEAERR; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + process_pending_signals(env); /* Exception return on AArch64 always clears the exclusive monitor, * so any return to running guest code implies this. diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 153bd1e9df8..d55f8d1e1ed 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -565,6 +565,16 @@ static void mte_check_fail(CPUARMState *env, uint32_t = desc, select =3D 0; } env->cp15.tfsr_el[el] |=3D 1 << select; +#ifdef CONFIG_USER_ONLY + /* + * Stand in for a timer irq, setting _TIF_MTE_ASYNC_FAULT, + * which then sends a SIGSEGV when the thread is next scheduled. + * This cpu will return to the main loop at the end of the TB, + * which is rather sooner than "normal". But the alternative + * is waiting until the next syscall. + */ + qemu_cpu_kick(env_cpu(env)); +#endif break; =20 default: --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050724; cv=none; d=zohomail.com; s=zohoarc; b=Hk3L2F2kblvRQpKykgbRZO01otoZeHt8Z8szgiHnJdipWQrRMNo0BlQLkISqC1x2dXBcuCdIVrcdHf0d1hD6BATmHs0ZxmwR15FS6qtNR7b08s4BMfQfI8zz7hMKMxYKOEuDsiOdnAqp9keX0lk+/PitoZOHzmJDAPzQttf82aQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613050724; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=g2Yy6Gw+Zt5E0Xgr51AYWc0qRdU0SjlUfwyoeBPlQ/c=; b=ksoCfgVjtLGEhx3WW34dpvx2F5osaRewth1/HG0PBX917//GXnMIpFl1tByWql4g2vTUJ9nri3CNzsB8FekIBt6XKsMqvcnW2ylHazB7iwNLTWeEmqN2pLTXe9ObBHRLD1zHKBkbNRQ/AOqcyefqCJ3jRujL2ewXEtAQ0Ca7CtE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613050724485766.8108321769786; Thu, 11 Feb 2021 05:38:44 -0800 (PST) Received: from localhost ([::1]:58632 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lACB9-0003no-EO for importer@patchew.org; Thu, 11 Feb 2021 08:38:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33828) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZO-0008S4-I5 for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:42 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:34464) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZE-00006d-D3 for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:42 -0500 Received: by mail-wr1-x42f.google.com with SMTP id g10so4124656wrx.1 for ; Thu, 11 Feb 2021 04:59:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=g2Yy6Gw+Zt5E0Xgr51AYWc0qRdU0SjlUfwyoeBPlQ/c=; b=RlJapo9DbgT4rlHnOoCiNNsJ1g3ckDZ9ioFGbaP0bi8eIVtS746/jqEpYAFSvha2Xo v8y9qdw9nlUFSZ0i8WVhgg7jB+6u4ph4p3F9dZ/vkDl98sb41NGRkoY/fi90Wgq6K4XQ Q9pI9N9BCpeOLj+dRTlyKcAZOrPsfdLnpoQPgJgKEJpRJfcU5QAE1Je/fNI/T4o4/hg0 mpdZzy0ByQiZ5M8yxqWmahlCkgmdI3x1diJZgOH3ODui5qTMZKuRDfhGd/EXVc0Mp5+F 9hJUvsQiI5BXHU9tygMJpUSAfQ0U59Suy1RIg6j2SKlmEHe2E8Dp6btD8dwXkHUKF5Nf 2Kmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g2Yy6Gw+Zt5E0Xgr51AYWc0qRdU0SjlUfwyoeBPlQ/c=; b=LXP7+kTv/KKsih2bMMA25MWxn0hPu1dOrhPBez1U4Ry/85Ze6ppyU7d8TzrxuFPdPN 44qdq0fcTzkLl5gTqE15uCSj2T0leJ6PGTdtxwPdIzRVINlhEV+5dCg1nTh8oIo7WhFX w4R/2Cgxw34+wsI5yFfaC/6G9ZtwvHWHqtq1leGkpWWIjkk0Bja36oCjIdyB8dEWrxz1 uqkyMpt51Mja1POkomz4Mj8/CO5SumrVhIS+pajnB1Wcd+o71GNQq8kKgsIS9+M1mIpo HTAdVBFxtAwPnquz/Vw1kASl3CdIKIbztcn8OgHVGhwO890rKC/NzzrsMIBEw8TNDmR5 jhhA== X-Gm-Message-State: AOAM533R9apJa0MgJ6thuPPoiK93tjc4IC2rJZaPyECOYMg0n4fBbLY5 VU58bwL8Rmolu0g1QBBfsrEMRNVmHLqp3g== X-Google-Smtp-Source: ABdhPJxDzQaxx2WXmBpHkGKdAswdGy4S0S3y9uINErbfW52rDKt942pzgPqnBu6UPRh+QDBEfOlqkg== X-Received: by 2002:a5d:4708:: with SMTP id y8mr5491816wrq.402.1613048371190; Thu, 11 Feb 2021 04:59:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/45] target/arm: Add allocation tag storage for user mode Date: Thu, 11 Feb 2021 12:58:53 +0000 Message-Id: <20210211125900.22777-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use the now-saved PAGE_ANON and PAGE_MTE bits, and the per-page saved data. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-30-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/mte_helper.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index d55f8d1e1ed..1c569336eae 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -78,8 +78,33 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int= ptr_mmu_idx, int tag_size, uintptr_t ra) { #ifdef CONFIG_USER_ONLY - /* Tag storage not implemented. */ - return NULL; + uint64_t clean_ptr =3D useronly_clean_ptr(ptr); + int flags =3D page_get_flags(clean_ptr); + uint8_t *tags; + uintptr_t index; + + if (!(flags & (ptr_access =3D=3D MMU_DATA_STORE ? PAGE_WRITE : PAGE_RE= AD))) { + /* SIGSEGV */ + arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access, + ptr_mmu_idx, false, ra); + g_assert_not_reached(); + } + + /* Require both MAP_ANON and PROT_MTE for the page. */ + if (!(flags & PAGE_ANON) || !(flags & PAGE_MTE)) { + return NULL; + } + + tags =3D page_get_target_data(clean_ptr); + if (tags =3D=3D NULL) { + size_t alloc_size =3D TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); + tags =3D page_alloc_target_data(clean_ptr, alloc_size); + assert(tags !=3D NULL); + } + + index =3D extract32(ptr, LOG2_TAG_GRANULE + 1, + TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); + return tags + index; #else uintptr_t index; CPUIOTLBEntry *iotlbentry; --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613050852; cv=none; d=zohomail.com; s=zohoarc; b=hnIhUNbVw+p7avwB4X3tN07Jst0h58/o6bStmIIFUs4elj3BlMmJO98wi/87QsLcU+zQBE0C0QITWWxITH3XhN16hv+BVLNwEkQzsJG+JqiN3NvMX+tDSJNbZ5YsQROjM0QKmo15Hl6JFt8wUbtsO56EdoZXacF/OwcEeG8Rtu0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613050852; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KWSycCSx4+GuKx3YydDF8ApKFvT897T9h34Lsj16JAU=; b=YTWfj5yx6kIur9XAxtjHV+Wg1Kom1uAWFHwFoIX3meiKijC/o/gl0snLeL6Kq4iE1YuwpnEZxG+CENJvAufgGVJq3CAJ5L3v4t944sAnIzLRPSLvSYldanIAEgZ4ncmjXtaOLBCWgmYTKjsdsdsw9+XIgqjNc8b4LQSVsZWDc7k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613050851684572.0316033320253; Thu, 11 Feb 2021 05:40:51 -0800 (PST) Received: from localhost ([::1]:38592 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lACDC-0007gs-Ge for importer@patchew.org; Thu, 11 Feb 2021 08:40:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33852) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZQ-0008Ve-0I for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:44 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:34466) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZF-00007H-Jm for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:43 -0500 Received: by mail-wr1-x431.google.com with SMTP id g10so4124694wrx.1 for ; Thu, 11 Feb 2021 04:59:32 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-31-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 70cfcbc9181..b8bc89e71fc 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -209,6 +209,21 @@ static void arm_cpu_reset(DeviceState *dev) * Note that this must match useronly_clean_ptr. */ env->cp15.tcr_el[1].raw_tcr =3D (1ULL << 37); + + /* Enable MTE */ + if (cpu_isar_feature(aa64_mte, cpu)) { + /* Enable tag access, but leave TCF0 as No Effect (0). */ + env->cp15.sctlr_el[1] |=3D SCTLR_ATA0; + /* + * Exclude all tags, so that tag 0 is always used. + * This corresponds to Linux current->thread.gcr_incl =3D 0. + * + * Set RRND, so that helper_irg() will generate a seed later. + * Here in cpu_reset(), the crypto subsystem has not yet been + * initialized. + */ + env->cp15.gcr_el1 =3D 0x1ffff; + } #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613051157; cv=none; d=zohomail.com; s=zohoarc; b=Z4fa51tF01aN1BEJwu37YuK/Uan3JZ9DLcgUK8mAmesexztH9fpgbDAdTYHYTm/vEUAPAXVlwRtl86slArTjseFc+IIDTPg3cuNs9BROslwo1Q0eEWGuttQ+yQvLcSPpTntpFl+FFBHyYr3yBhA/By1xiQcDn7IEWrGjUz+mj+E= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210210000223.884088-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- tests/tcg/aarch64/mte.h | 60 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/mte-1.c | 28 +++++++++++++++ tests/tcg/aarch64/mte-2.c | 45 +++++++++++++++++++++++ tests/tcg/aarch64/mte-3.c | 51 ++++++++++++++++++++++++++ tests/tcg/aarch64/mte-4.c | 45 +++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 6 ++++ tests/tcg/configure.sh | 4 +++ 7 files changed, 239 insertions(+) create mode 100644 tests/tcg/aarch64/mte.h create mode 100644 tests/tcg/aarch64/mte-1.c create mode 100644 tests/tcg/aarch64/mte-2.c create mode 100644 tests/tcg/aarch64/mte-3.c create mode 100644 tests/tcg/aarch64/mte-4.c diff --git a/tests/tcg/aarch64/mte.h b/tests/tcg/aarch64/mte.h new file mode 100644 index 00000000000..141cef522ce --- /dev/null +++ b/tests/tcg/aarch64/mte.h @@ -0,0 +1,60 @@ +/* + * Linux kernel fallback API definitions for MTE and test helpers. + * + * Copyright (c) 2021 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef PR_SET_TAGGED_ADDR_CTRL +# define PR_SET_TAGGED_ADDR_CTRL 55 +#endif +#ifndef PR_TAGGED_ADDR_ENABLE +# define PR_TAGGED_ADDR_ENABLE (1UL << 0) +#endif +#ifndef PR_MTE_TCF_SHIFT +# define PR_MTE_TCF_SHIFT 1 +# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TAG_SHIFT 3 +#endif + +#ifndef PROT_MTE +# define PROT_MTE 0x20 +#endif + +#ifndef SEGV_MTEAERR +# define SEGV_MTEAERR 8 +# define SEGV_MTESERR 9 +#endif + +static void enable_mte(int tcf) +{ + int r =3D prctl(PR_SET_TAGGED_ADDR_CTRL, + PR_TAGGED_ADDR_ENABLE | tcf | (0xfffe << PR_MTE_TAG_SHIF= T), + 0, 0, 0); + if (r < 0) { + perror("PR_SET_TAGGED_ADDR_CTRL"); + exit(2); + } +} + +static void *alloc_mte_mem(size_t size) +{ + void *p =3D mmap(NULL, size, PROT_READ | PROT_WRITE | PROT_MTE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (p =3D=3D MAP_FAILED) { + perror("mmap PROT_MTE"); + exit(2); + } + return p; +} diff --git a/tests/tcg/aarch64/mte-1.c b/tests/tcg/aarch64/mte-1.c new file mode 100644 index 00000000000..88dcd617add --- /dev/null +++ b/tests/tcg/aarch64/mte-1.c @@ -0,0 +1,28 @@ +/* + * Memory tagging, basic pass cases. + * + * Copyright (c) 2021 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "mte.h" + +int main(int ac, char **av) +{ + int *p0, *p1, *p2; + long c; + + enable_mte(PR_MTE_TCF_NONE); + p0 =3D alloc_mte_mem(sizeof(*p0)); + + asm("irg %0,%1,%2" : "=3Dr"(p1) : "r"(p0), "r"(1)); + assert(p1 !=3D p0); + asm("subp %0,%1,%2" : "=3Dr"(c) : "r"(p0), "r"(p1)); + assert(c =3D=3D 0); + + asm("stg %0, [%0]" : : "r"(p1)); + asm("ldg %0, [%1]" : "=3Dr"(p2) : "r"(p0), "0"(p0)); + assert(p1 =3D=3D p2); + + return 0; +} diff --git a/tests/tcg/aarch64/mte-2.c b/tests/tcg/aarch64/mte-2.c new file mode 100644 index 00000000000..a62278276a4 --- /dev/null +++ b/tests/tcg/aarch64/mte-2.c @@ -0,0 +1,45 @@ +/* + * Memory tagging, basic fail cases, synchronous signals. + * + * Copyright (c) 2021 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "mte.h" + +void pass(int sig, siginfo_t *info, void *uc) +{ + assert(info->si_code =3D=3D SEGV_MTESERR); + exit(0); +} + +int main(int ac, char **av) +{ + struct sigaction sa; + int *p0, *p1, *p2; + long excl =3D 1; + + enable_mte(PR_MTE_TCF_SYNC); + p0 =3D alloc_mte_mem(sizeof(*p0)); + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=3Dr"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl !=3D 1); + asm("irg %0,%1,%2" : "=3Dr"(p2) : "r"(p0), "r"(excl)); + assert(p1 !=3D p2); + + /* Store the tag from the first pointer. */ + asm("stg %0, [%0]" : : "r"(p1)); + + *p1 =3D 0; + + memset(&sa, 0, sizeof(sa)); + sa.sa_sigaction =3D pass; + sa.sa_flags =3D SA_SIGINFO; + sigaction(SIGSEGV, &sa, NULL); + + *p2 =3D 0; + + abort(); +} diff --git a/tests/tcg/aarch64/mte-3.c b/tests/tcg/aarch64/mte-3.c new file mode 100644 index 00000000000..424ea685c2b --- /dev/null +++ b/tests/tcg/aarch64/mte-3.c @@ -0,0 +1,51 @@ +/* + * Memory tagging, basic fail cases, asynchronous signals. + * + * Copyright (c) 2021 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "mte.h" + +void pass(int sig, siginfo_t *info, void *uc) +{ + assert(info->si_code =3D=3D SEGV_MTEAERR); + exit(0); +} + +int main(int ac, char **av) +{ + struct sigaction sa; + long *p0, *p1, *p2; + long excl =3D 1; + + enable_mte(PR_MTE_TCF_ASYNC); + p0 =3D alloc_mte_mem(sizeof(*p0)); + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=3Dr"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl !=3D 1); + asm("irg %0,%1,%2" : "=3Dr"(p2) : "r"(p0), "r"(excl)); + assert(p1 !=3D p2); + + /* Store the tag from the first pointer. */ + asm("stg %0, [%0]" : : "r"(p1)); + + *p1 =3D 0; + + memset(&sa, 0, sizeof(sa)); + sa.sa_sigaction =3D pass; + sa.sa_flags =3D SA_SIGINFO; + sigaction(SIGSEGV, &sa, NULL); + + /* + * Signal for async error will happen eventually. + * For a real kernel this should be after the next IRQ (e.g. timer). + * For qemu linux-user, we kick the cpu and exit at the next TB. + * In either case, loop until this happens (or killed by timeout). + * For extra sauce, yield, producing EXCP_YIELD to cpu_loop(). + */ + asm("str %0, [%0]; yield" : : "r"(p2)); + while (1); +} diff --git a/tests/tcg/aarch64/mte-4.c b/tests/tcg/aarch64/mte-4.c new file mode 100644 index 00000000000..a8cc9f59841 --- /dev/null +++ b/tests/tcg/aarch64/mte-4.c @@ -0,0 +1,45 @@ +/* + * Memory tagging, re-reading tag checks. + * + * Copyright (c) 2021 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "mte.h" + +void __attribute__((noinline)) tagset(void *p, size_t size) +{ + size_t i; + for (i =3D 0; i < size; i +=3D 16) { + asm("stg %0, [%0]" : : "r"(p + i)); + } +} + +void __attribute__((noinline)) tagcheck(void *p, size_t size) +{ + size_t i; + void *c; + + for (i =3D 0; i < size; i +=3D 16) { + asm("ldg %0, [%1]" : "=3Dr"(c) : "r"(p + i), "0"(p)); + assert(c =3D=3D p); + } +} + +int main(int ac, char **av) +{ + size_t size =3D getpagesize() * 4; + long excl =3D 1; + int *p0, *p1; + + enable_mte(PR_MTE_TCF_ASYNC); + p0 =3D alloc_mte_mem(size); + + /* Tag the pointer. */ + asm("irg %0,%1,%2" : "=3Dr"(p1) : "r"(p0), "r"(excl)); + + tagset(p1, size); + tagcheck(p1, size); + + return 0; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index d7d33e293c0..bf53ad00870 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -35,6 +35,12 @@ endif # bti-2 tests PROT_BTI, so no special compiler support required. AARCH64_TESTS +=3D bti-2 =20 +# MTE Tests +ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_MTE),) +AARCH64_TESTS +=3D mte-1 mte-2 mte-3 mte-4 +mte-%: CFLAGS +=3D -march=3Darmv8.5-a+memtag +endif + # Semihosting smoke test for linux-user AARCH64_TESTS +=3D semihosting run-semihosting: semihosting diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index e1b70e25f23..ba8ac9a93e9 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -244,6 +244,10 @@ for target in $target_list; do -mbranch-protection=3Dstandard -o $TMPE $TMPC; then echo "CROSS_CC_HAS_ARMV8_BTI=3Dy" >> $config_target_mak fi + if do_compiler "$target_compiler" $target_compiler_cflags \ + -march=3Darmv8.5-a+memtag -o $TMPE $TMPC; then + echo "CROSS_CC_HAS_ARMV8_MTE=3Dy" >> $config_target_mak + fi ;; esac =20 --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613051011; cv=none; d=zohomail.com; s=zohoarc; b=oAzP0KpdcULlehLxlTe0Mc1KrKanjI8jkZzU6ESnVTTa1Fxomj/GUwU05wMKVUarnh6MYnMSUFNTlMqkYUUHx+JYbffzaLPkqIy6skGZBwYQHmY02Qh/7OwIIuNrm8P3CPaSpqaEV8duznc1YihkiCBB25yTPMnb4xJeGbkeyiI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613051011; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Q2Pql5JVNPwY12WQkdobgW15XaCLpJq0RQKKvdfLhoM=; b=fYT8igRHEoH7YxwcynmDWZe3zQsDQSXCxWFbZG2M8l/KiXgLOjutqk9GcUSG0RzmtmQNm8HYLrLNGEcG069gZ1JBcha6ZAmj4/rWrjvpdYb0ccnCOkCHIxnUAcnyLpwrrgZDyw6rw237AFtiaV+7rajUlppHHxgKAz3lfzgh3IU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613051011407443.72059232010827; Thu, 11 Feb 2021 05:43:31 -0800 (PST) Received: from localhost ([::1]:47044 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lACFm-0002rr-3z for importer@patchew.org; Thu, 11 Feb 2021 08:43:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33912) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZT-0000BW-53 for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:47 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:36249) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZH-00007s-HJ for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:46 -0500 Received: by mail-wm1-x32c.google.com with SMTP id i9so5658014wmq.1 for ; Thu, 11 Feb 2021 04:59:34 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Q2Pql5JVNPwY12WQkdobgW15XaCLpJq0RQKKvdfLhoM=; b=xOT76Kao0JWOd/2ZYbwt1zlNR/d0hlRnLYSCfNUv4lPpm0nTVlar1mlPziDQoRHdpu KA4+uHZlPSHUE2d2bNF2hKiUAQvxQw8xOfsQjuv0Rrl3yxJk1dv3wqhG9ez/n5ioSNie wByv/B0DQ33xDLodiprF/nEXPbllauIEgRuNYidlBpet5+U339Tkt3ptmn1sRhBta6xt fbFZvT1+WLA66f2+Z2mKfCw7KNnHUG9HWsiZ4DOreYVI8Nck9TuJdjwugcHCvQkvQnDS bDC2nsF8N7OSIFHhQLb9QR/sdzVgONZiitFqPYZ6m5Rjga0C8yK+qUQPW9okNahSEzWA sY4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q2Pql5JVNPwY12WQkdobgW15XaCLpJq0RQKKvdfLhoM=; b=T7QXSe7p6ASG/FgQVJIq1PNE9Y/HMwwxzY59dncvNB1WWJtnaeTnYrsGYErL5pdMgL yU7LUUZCW8Fp6jxm7wZyiBRakLr0OnfTVLLedZLPWa9AcGX5ch+3VQXSj0/B/2YCS7QQ r0yx8keYLnvPT9XsOHv5fBdh1tAMZg2nJrgl7ItufKt5ku7eKdbD6b/fZ/MWXOWmjgha uHeVneRJHXN0ArspolauB+zEDoiMTvwUzjV47hv74gXGwZSV2qFEWlgqTSESipALBUIX vLSF0Of7fdtnlPzmwUW/Vv1EFMM5LNtf7mcfrBquwUe7s5bn0X411aBcRdceq0upUpJv Kkvg== X-Gm-Message-State: AOAM533JiUiEQvqsBF5wXiRW1F9l6CpNg20OsdGsXJPt5LDkaOSiO0DV B6XpuBffg1HqDHPZ5WiwNJe6kD6vVjsFEg== X-Google-Smtp-Source: ABdhPJxablqGQVSvtSGJAEiCMLWxN3uWsvLd43R1zpLRfm/wD8KySNTX2t3tSEIK21c3r/0LBpNetw== X-Received: by 2002:a1c:720b:: with SMTP id n11mr5181210wmc.154.1613048373894; Thu, 11 Feb 2021 04:59:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 41/45] hw/net: Add npcm7xx emc model Date: Thu, 11 Feb 2021 12:58:56 +0000 Message-Id: <20210211125900.22777-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Doug Evans This is a 10/100 ethernet device that has several features. Only the ones needed by the Linux driver have been implemented. See npcm7xx_emc.c for a list of unimplemented features. Reviewed-by: Hao Wu Reviewed-by: Avi Fishman Signed-off-by: Doug Evans Message-id: 20210209015541.778833-2-dje@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/net/npcm7xx_emc.h | 286 ++++++++++++ hw/net/npcm7xx_emc.c | 857 +++++++++++++++++++++++++++++++++++ hw/net/meson.build | 1 + hw/net/trace-events | 17 + 4 files changed, 1161 insertions(+) create mode 100644 include/hw/net/npcm7xx_emc.h create mode 100644 hw/net/npcm7xx_emc.c diff --git a/include/hw/net/npcm7xx_emc.h b/include/hw/net/npcm7xx_emc.h new file mode 100644 index 00000000000..eac7f298167 --- /dev/null +++ b/include/hw/net/npcm7xx_emc.h @@ -0,0 +1,286 @@ +/* + * Nuvoton NPCM7xx EMC Module + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef NPCM7XX_EMC_H +#define NPCM7XX_EMC_H + +#include "hw/irq.h" +#include "hw/sysbus.h" +#include "net/net.h" + +/* 32-bit register indices. */ +enum NPCM7xxPWMRegister { + /* Control registers. */ + REG_CAMCMR, + REG_CAMEN, + + /* There are 16 CAMn[ML] registers. */ + REG_CAMM_BASE, + REG_CAML_BASE, + REG_CAMML_LAST =3D 0x21, + + REG_TXDLSA =3D 0x22, + REG_RXDLSA, + REG_MCMDR, + REG_MIID, + REG_MIIDA, + REG_FFTCR, + REG_TSDR, + REG_RSDR, + REG_DMARFC, + REG_MIEN, + + /* Status registers. */ + REG_MISTA, + REG_MGSTA, + REG_MPCNT, + REG_MRPC, + REG_MRPCC, + REG_MREPC, + REG_DMARFS, + REG_CTXDSA, + REG_CTXBSA, + REG_CRXDSA, + REG_CRXBSA, + + NPCM7XX_NUM_EMC_REGS, +}; + +/* REG_CAMCMR fields */ +/* Enable CAM Compare */ +#define REG_CAMCMR_ECMP (1 << 4) +/* Complement CAM Compare */ +#define REG_CAMCMR_CCAM (1 << 3) +/* Accept Broadcast Packet */ +#define REG_CAMCMR_ABP (1 << 2) +/* Accept Multicast Packet */ +#define REG_CAMCMR_AMP (1 << 1) +/* Accept Unicast Packet */ +#define REG_CAMCMR_AUP (1 << 0) + +/* REG_MCMDR fields */ +/* Software Reset */ +#define REG_MCMDR_SWR (1 << 24) +/* Internal Loopback Select */ +#define REG_MCMDR_LBK (1 << 21) +/* Operation Mode Select */ +#define REG_MCMDR_OPMOD (1 << 20) +/* Enable MDC Clock Generation */ +#define REG_MCMDR_ENMDC (1 << 19) +/* Full-Duplex Mode Select */ +#define REG_MCMDR_FDUP (1 << 18) +/* Enable SQE Checking */ +#define REG_MCMDR_ENSEQ (1 << 17) +/* Send PAUSE Frame */ +#define REG_MCMDR_SDPZ (1 << 16) +/* No Defer */ +#define REG_MCMDR_NDEF (1 << 9) +/* Frame Transmission On */ +#define REG_MCMDR_TXON (1 << 8) +/* Strip CRC Checksum */ +#define REG_MCMDR_SPCRC (1 << 5) +/* Accept CRC Error Packet */ +#define REG_MCMDR_AEP (1 << 4) +/* Accept Control Packet */ +#define REG_MCMDR_ACP (1 << 3) +/* Accept Runt Packet */ +#define REG_MCMDR_ARP (1 << 2) +/* Accept Long Packet */ +#define REG_MCMDR_ALP (1 << 1) +/* Frame Reception On */ +#define REG_MCMDR_RXON (1 << 0) + +/* REG_MIEN fields */ +/* Enable Transmit Descriptor Unavailable Interrupt */ +#define REG_MIEN_ENTDU (1 << 23) +/* Enable Transmit Completion Interrupt */ +#define REG_MIEN_ENTXCP (1 << 18) +/* Enable Transmit Interrupt */ +#define REG_MIEN_ENTXINTR (1 << 16) +/* Enable Receive Descriptor Unavailable Interrupt */ +#define REG_MIEN_ENRDU (1 << 10) +/* Enable Receive Good Interrupt */ +#define REG_MIEN_ENRXGD (1 << 4) +/* Enable Receive Interrupt */ +#define REG_MIEN_ENRXINTR (1 << 0) + +/* REG_MISTA fields */ +/* TODO: Add error fields and support simulated errors? */ +/* Transmit Bus Error Interrupt */ +#define REG_MISTA_TXBERR (1 << 24) +/* Transmit Descriptor Unavailable Interrupt */ +#define REG_MISTA_TDU (1 << 23) +/* Transmit Completion Interrupt */ +#define REG_MISTA_TXCP (1 << 18) +/* Transmit Interrupt */ +#define REG_MISTA_TXINTR (1 << 16) +/* Receive Bus Error Interrupt */ +#define REG_MISTA_RXBERR (1 << 11) +/* Receive Descriptor Unavailable Interrupt */ +#define REG_MISTA_RDU (1 << 10) +/* DMA Early Notification Interrupt */ +#define REG_MISTA_DENI (1 << 9) +/* Maximum Frame Length Interrupt */ +#define REG_MISTA_DFOI (1 << 8) +/* Receive Good Interrupt */ +#define REG_MISTA_RXGD (1 << 4) +/* Packet Too Long Interrupt */ +#define REG_MISTA_PTLE (1 << 3) +/* Receive Interrupt */ +#define REG_MISTA_RXINTR (1 << 0) + +/* REG_MGSTA fields */ +/* Transmission Halted */ +#define REG_MGSTA_TXHA (1 << 11) +/* Receive Halted */ +#define REG_MGSTA_RXHA (1 << 11) + +/* REG_DMARFC fields */ +/* Maximum Receive Frame Length */ +#define REG_DMARFC_RXMS(word) extract32((word), 0, 16) + +/* REG MIIDA fields */ +/* Busy Bit */ +#define REG_MIIDA_BUSY (1 << 17) + +/* Transmit and receive descriptors */ +typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc; +typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc; + +struct NPCM7xxEMCTxDesc { + uint32_t flags; + uint32_t txbsa; + uint32_t status_and_length; + uint32_t ntxdsa; +}; + +struct NPCM7xxEMCRxDesc { + uint32_t status_and_length; + uint32_t rxbsa; + uint32_t reserved; + uint32_t nrxdsa; +}; + +/* NPCM7xxEMCTxDesc.flags values */ +/* Owner: 0 =3D cpu, 1 =3D emc */ +#define TX_DESC_FLAG_OWNER_MASK (1 << 31) +/* Transmit interrupt enable */ +#define TX_DESC_FLAG_INTEN (1 << 2) +/* CRC append */ +#define TX_DESC_FLAG_CRCAPP (1 << 1) +/* Padding enable */ +#define TX_DESC_FLAG_PADEN (1 << 0) + +/* NPCM7xxEMCTxDesc.status_and_length values */ +/* Collision count */ +#define TX_DESC_STATUS_CCNT_SHIFT 28 +#define TX_DESC_STATUS_CCNT_BITSIZE 4 +/* SQE error */ +#define TX_DESC_STATUS_SQE (1 << 26) +/* Transmission paused */ +#define TX_DESC_STATUS_PAU (1 << 25) +/* P transmission halted */ +#define TX_DESC_STATUS_TXHA (1 << 24) +/* Late collision */ +#define TX_DESC_STATUS_LC (1 << 23) +/* Transmission abort */ +#define TX_DESC_STATUS_TXABT (1 << 22) +/* No carrier sense */ +#define TX_DESC_STATUS_NCS (1 << 21) +/* Defer exceed */ +#define TX_DESC_STATUS_EXDEF (1 << 20) +/* Transmission complete */ +#define TX_DESC_STATUS_TXCP (1 << 19) +/* Transmission deferred */ +#define TX_DESC_STATUS_DEF (1 << 17) +/* Transmit interrupt */ +#define TX_DESC_STATUS_TXINTR (1 << 16) + +#define TX_DESC_PKT_LEN(word) extract32((word), 0, 16) + +/* Transmit buffer start address */ +#define TX_DESC_TXBSA(word) ((uint32_t) (word) & ~3u) + +/* Next transmit descriptor start address */ +#define TX_DESC_NTXDSA(word) ((uint32_t) (word) & ~3u) + +/* NPCM7xxEMCRxDesc.status_and_length values */ +/* Owner: 0b00 =3D cpu, 0b01 =3D undefined, 0b10 =3D emc, 0b11 =3D undefin= ed */ +#define RX_DESC_STATUS_OWNER_SHIFT 30 +#define RX_DESC_STATUS_OWNER_BITSIZE 2 +#define RX_DESC_STATUS_OWNER_MASK (3 << RX_DESC_STATUS_OWNER_SHIFT) +/* Runt packet */ +#define RX_DESC_STATUS_RP (1 << 22) +/* Alignment error */ +#define RX_DESC_STATUS_ALIE (1 << 21) +/* Frame reception complete */ +#define RX_DESC_STATUS_RXGD (1 << 20) +/* Packet too long */ +#define RX_DESC_STATUS_PTLE (1 << 19) +/* CRC error */ +#define RX_DESC_STATUS_CRCE (1 << 17) +/* Receive interrupt */ +#define RX_DESC_STATUS_RXINTR (1 << 16) + +#define RX_DESC_PKT_LEN(word) extract32((word), 0, 16) + +/* Receive buffer start address */ +#define RX_DESC_RXBSA(word) ((uint32_t) (word) & ~3u) + +/* Next receive descriptor start address */ +#define RX_DESC_NRXDSA(word) ((uint32_t) (word) & ~3u) + +/* Minimum packet length, when TX_DESC_FLAG_PADEN is set. */ +#define MIN_PACKET_LENGTH 64 + +struct NPCM7xxEMCState { + /*< private >*/ + SysBusDevice parent; + /*< public >*/ + + MemoryRegion iomem; + + qemu_irq tx_irq; + qemu_irq rx_irq; + + NICState *nic; + NICConf conf; + + /* 0 or 1, for log messages */ + uint8_t emc_num; + + uint32_t regs[NPCM7XX_NUM_EMC_REGS]; + + /* + * tx is active. Set to true by TSDR and then switches off when out of + * descriptors. If the TXON bit in REG_MCMDR is off then this is off. + */ + bool tx_active; + + /* + * rx is active. Set to true by RSDR and then switches off when out of + * descriptors. If the RXON bit in REG_MCMDR is off then this is off. + */ + bool rx_active; +}; + +typedef struct NPCM7xxEMCState NPCM7xxEMCState; + +#define TYPE_NPCM7XX_EMC "npcm7xx-emc" +#define NPCM7XX_EMC(obj) \ + OBJECT_CHECK(NPCM7xxEMCState, (obj), TYPE_NPCM7XX_EMC) + +#endif /* NPCM7XX_EMC_H */ diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c new file mode 100644 index 00000000000..714a742ba7a --- /dev/null +++ b/hw/net/npcm7xx_emc.c @@ -0,0 +1,857 @@ +/* + * Nuvoton NPCM7xx EMC Module + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * Unsupported/unimplemented features: + * - MCMDR.FDUP (full duplex) is ignored, half duplex is not supported + * - Only CAM0 is supported, CAM[1-15] are not + * - writes to CAMEN.[1-15] are ignored, these bits always read as zeroes + * - MII is not implemented, MIIDA.BUSY and MIID always return zero + * - MCMDR.LBK is not implemented + * - MCMDR.{OPMOD,ENSQE,AEP,ARP} are not supported + * - H/W FIFOs are not supported, MCMDR.FFTCR is ignored + * - MGSTA.SQE is not supported + * - pause and control frames are not implemented + * - MGSTA.CCNT is not supported + * - MPCNT, DMARFS are not implemented + */ + +#include "qemu/osdep.h" + +/* For crc32 */ +#include + +#include "qemu-common.h" +#include "hw/irq.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-properties.h" +#include "hw/net/npcm7xx_emc.h" +#include "net/eth.h" +#include "migration/vmstate.h" +#include "qemu/bitops.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/units.h" +#include "sysemu/dma.h" +#include "trace.h" + +#define CRC_LENGTH 4 + +/* + * The maximum size of a (layer 2) ethernet frame as defined by 802.3. + * 1518 =3D 6(dest macaddr) + 6(src macaddr) + 2(proto) + 4(crc) + 1500(pa= yload) + * This does not include an additional 4 for the vlan field (802.1q). + */ +#define MAX_ETH_FRAME_SIZE 1518 + +static const char *emc_reg_name(int regno) +{ +#define REG(name) case REG_ ## name: return #name; + switch (regno) { + REG(CAMCMR) + REG(CAMEN) + REG(TXDLSA) + REG(RXDLSA) + REG(MCMDR) + REG(MIID) + REG(MIIDA) + REG(FFTCR) + REG(TSDR) + REG(RSDR) + REG(DMARFC) + REG(MIEN) + REG(MISTA) + REG(MGSTA) + REG(MPCNT) + REG(MRPC) + REG(MRPCC) + REG(MREPC) + REG(DMARFS) + REG(CTXDSA) + REG(CTXBSA) + REG(CRXDSA) + REG(CRXBSA) + case REG_CAMM_BASE + 0: return "CAM0M"; + case REG_CAML_BASE + 0: return "CAM0L"; + case REG_CAMM_BASE + 2 ... REG_CAMML_LAST: + /* Only CAM0 is supported, fold the others into something simple. = */ + if (regno & 1) { + return "CAML"; + } else { + return "CAMM"; + } + default: return "UNKNOWN"; + } +#undef REG +} + +static void emc_reset(NPCM7xxEMCState *emc) +{ + trace_npcm7xx_emc_reset(emc->emc_num); + + memset(&emc->regs[0], 0, sizeof(emc->regs)); + + /* These regs have non-zero reset values. */ + emc->regs[REG_TXDLSA] =3D 0xfffffffc; + emc->regs[REG_RXDLSA] =3D 0xfffffffc; + emc->regs[REG_MIIDA] =3D 0x00900000; + emc->regs[REG_FFTCR] =3D 0x0101; + emc->regs[REG_DMARFC] =3D 0x0800; + emc->regs[REG_MPCNT] =3D 0x7fff; + + emc->tx_active =3D false; + emc->rx_active =3D false; +} + +static void npcm7xx_emc_reset(DeviceState *dev) +{ + NPCM7xxEMCState *emc =3D NPCM7XX_EMC(dev); + emc_reset(emc); +} + +static void emc_soft_reset(NPCM7xxEMCState *emc) +{ + /* + * The docs say at least MCMDR.{LBK,OPMOD} bits are not changed during= a + * soft reset, but does not go into further detail. For now, KISS. + */ + uint32_t mcmdr =3D emc->regs[REG_MCMDR]; + emc_reset(emc); + emc->regs[REG_MCMDR] =3D mcmdr & (REG_MCMDR_LBK | REG_MCMDR_OPMOD); + + qemu_set_irq(emc->tx_irq, 0); + qemu_set_irq(emc->rx_irq, 0); +} + +static void emc_set_link(NetClientState *nc) +{ + /* Nothing to do yet. */ +} + +/* MISTA.TXINTR is the union of the individual bits with their enables. */ +static void emc_update_mista_txintr(NPCM7xxEMCState *emc) +{ + /* Only look at the bits we support. */ + uint32_t mask =3D (REG_MISTA_TXBERR | + REG_MISTA_TDU | + REG_MISTA_TXCP); + if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & mask) { + emc->regs[REG_MISTA] |=3D REG_MISTA_TXINTR; + } else { + emc->regs[REG_MISTA] &=3D ~REG_MISTA_TXINTR; + } +} + +/* MISTA.RXINTR is the union of the individual bits with their enables. */ +static void emc_update_mista_rxintr(NPCM7xxEMCState *emc) +{ + /* Only look at the bits we support. */ + uint32_t mask =3D (REG_MISTA_RXBERR | + REG_MISTA_RDU | + REG_MISTA_RXGD); + if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & mask) { + emc->regs[REG_MISTA] |=3D REG_MISTA_RXINTR; + } else { + emc->regs[REG_MISTA] &=3D ~REG_MISTA_RXINTR; + } +} + +/* N.B. emc_update_mista_txintr must have already been called. */ +static void emc_update_tx_irq(NPCM7xxEMCState *emc) +{ + int level =3D !!(emc->regs[REG_MISTA] & + emc->regs[REG_MIEN] & + REG_MISTA_TXINTR); + trace_npcm7xx_emc_update_tx_irq(level); + qemu_set_irq(emc->tx_irq, level); +} + +/* N.B. emc_update_mista_rxintr must have already been called. */ +static void emc_update_rx_irq(NPCM7xxEMCState *emc) +{ + int level =3D !!(emc->regs[REG_MISTA] & + emc->regs[REG_MIEN] & + REG_MISTA_RXINTR); + trace_npcm7xx_emc_update_rx_irq(level); + qemu_set_irq(emc->rx_irq, level); +} + +/* Update IRQ states due to changes in MIEN,MISTA. */ +static void emc_update_irq_from_reg_change(NPCM7xxEMCState *emc) +{ + emc_update_mista_txintr(emc); + emc_update_tx_irq(emc); + + emc_update_mista_rxintr(emc); + emc_update_rx_irq(emc); +} + +static int emc_read_tx_desc(dma_addr_t addr, NPCM7xxEMCTxDesc *desc) +{ + if (dma_memory_read(&address_space_memory, addr, desc, sizeof(*desc)))= { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x= %" + HWADDR_PRIx "\n", __func__, addr); + return -1; + } + desc->flags =3D le32_to_cpu(desc->flags); + desc->txbsa =3D le32_to_cpu(desc->txbsa); + desc->status_and_length =3D le32_to_cpu(desc->status_and_length); + desc->ntxdsa =3D le32_to_cpu(desc->ntxdsa); + return 0; +} + +static int emc_write_tx_desc(const NPCM7xxEMCTxDesc *desc, dma_addr_t addr) +{ + NPCM7xxEMCTxDesc le_desc; + + le_desc.flags =3D cpu_to_le32(desc->flags); + le_desc.txbsa =3D cpu_to_le32(desc->txbsa); + le_desc.status_and_length =3D cpu_to_le32(desc->status_and_length); + le_desc.ntxdsa =3D cpu_to_le32(desc->ntxdsa); + if (dma_memory_write(&address_space_memory, addr, &le_desc, + sizeof(le_desc))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0= x%" + HWADDR_PRIx "\n", __func__, addr); + return -1; + } + return 0; +} + +static int emc_read_rx_desc(dma_addr_t addr, NPCM7xxEMCRxDesc *desc) +{ + if (dma_memory_read(&address_space_memory, addr, desc, sizeof(*desc)))= { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x= %" + HWADDR_PRIx "\n", __func__, addr); + return -1; + } + desc->status_and_length =3D le32_to_cpu(desc->status_and_length); + desc->rxbsa =3D le32_to_cpu(desc->rxbsa); + desc->reserved =3D le32_to_cpu(desc->reserved); + desc->nrxdsa =3D le32_to_cpu(desc->nrxdsa); + return 0; +} + +static int emc_write_rx_desc(const NPCM7xxEMCRxDesc *desc, dma_addr_t addr) +{ + NPCM7xxEMCRxDesc le_desc; + + le_desc.status_and_length =3D cpu_to_le32(desc->status_and_length); + le_desc.rxbsa =3D cpu_to_le32(desc->rxbsa); + le_desc.reserved =3D cpu_to_le32(desc->reserved); + le_desc.nrxdsa =3D cpu_to_le32(desc->nrxdsa); + if (dma_memory_write(&address_space_memory, addr, &le_desc, + sizeof(le_desc))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0= x%" + HWADDR_PRIx "\n", __func__, addr); + return -1; + } + return 0; +} + +static void emc_set_mista(NPCM7xxEMCState *emc, uint32_t flags) +{ + trace_npcm7xx_emc_set_mista(flags); + emc->regs[REG_MISTA] |=3D flags; + if (extract32(flags, 16, 16)) { + emc_update_mista_txintr(emc); + } + if (extract32(flags, 0, 16)) { + emc_update_mista_rxintr(emc); + } +} + +static void emc_halt_tx(NPCM7xxEMCState *emc, uint32_t mista_flag) +{ + emc->tx_active =3D false; + emc_set_mista(emc, mista_flag); +} + +static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t mista_flag) +{ + emc->rx_active =3D false; + emc_set_mista(emc, mista_flag); +} + +static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc, + const NPCM7xxEMCTxDesc *tx_desc, + uint32_t desc_addr) +{ + /* Update the current descriptor, if only to reset the owner flag. */ + if (emc_write_tx_desc(tx_desc, desc_addr)) { + /* + * We just read it so this shouldn't generally happen. + * Error already reported. + */ + emc_set_mista(emc, REG_MISTA_TXBERR); + } + emc->regs[REG_CTXDSA] =3D TX_DESC_NTXDSA(tx_desc->ntxdsa); +} + +static void emc_set_next_rx_descriptor(NPCM7xxEMCState *emc, + const NPCM7xxEMCRxDesc *rx_desc, + uint32_t desc_addr) +{ + /* Update the current descriptor, if only to reset the owner flag. */ + if (emc_write_rx_desc(rx_desc, desc_addr)) { + /* + * We just read it so this shouldn't generally happen. + * Error already reported. + */ + emc_set_mista(emc, REG_MISTA_RXBERR); + } + emc->regs[REG_CRXDSA] =3D RX_DESC_NRXDSA(rx_desc->nrxdsa); +} + +static void emc_try_send_next_packet(NPCM7xxEMCState *emc) +{ + /* Working buffer for sending out packets. Most packets fit in this. */ +#define TX_BUFFER_SIZE 2048 + uint8_t tx_send_buffer[TX_BUFFER_SIZE]; + uint32_t desc_addr =3D TX_DESC_NTXDSA(emc->regs[REG_CTXDSA]); + NPCM7xxEMCTxDesc tx_desc; + uint32_t next_buf_addr, length; + uint8_t *buf; + g_autofree uint8_t *malloced_buf =3D NULL; + + if (emc_read_tx_desc(desc_addr, &tx_desc)) { + /* Error reading descriptor, already reported. */ + emc_halt_tx(emc, REG_MISTA_TXBERR); + emc_update_tx_irq(emc); + return; + } + + /* Nothing we can do if we don't own the descriptor. */ + if (!(tx_desc.flags & TX_DESC_FLAG_OWNER_MASK)) { + trace_npcm7xx_emc_cpu_owned_desc(desc_addr); + emc_halt_tx(emc, REG_MISTA_TDU); + emc_update_tx_irq(emc); + return; + } + + /* Give the descriptor back regardless of what happens. */ + tx_desc.flags &=3D ~TX_DESC_FLAG_OWNER_MASK; + tx_desc.status_and_length &=3D 0xffff; + + /* + * Despite the h/w documentation saying the tx buffer is word aligned, + * the linux driver does not word align the buffer. There is value in = not + * aligning the buffer: See the description of NET_IP_ALIGN in linux + * kernel sources. + */ + next_buf_addr =3D tx_desc.txbsa; + emc->regs[REG_CTXBSA] =3D next_buf_addr; + length =3D TX_DESC_PKT_LEN(tx_desc.status_and_length); + buf =3D &tx_send_buffer[0]; + + if (length > sizeof(tx_send_buffer)) { + malloced_buf =3D g_malloc(length); + buf =3D malloced_buf; + } + + if (dma_memory_read(&address_space_memory, next_buf_addr, buf, length)= ) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read packet @ 0x%x\n= ", + __func__, next_buf_addr); + emc_set_mista(emc, REG_MISTA_TXBERR); + emc_set_next_tx_descriptor(emc, &tx_desc, desc_addr); + emc_update_tx_irq(emc); + trace_npcm7xx_emc_tx_done(emc->regs[REG_CTXDSA]); + return; + } + + if ((tx_desc.flags & TX_DESC_FLAG_PADEN) && (length < MIN_PACKET_LENGT= H)) { + memset(buf + length, 0, MIN_PACKET_LENGTH - length); + length =3D MIN_PACKET_LENGTH; + } + + /* N.B. emc_receive can get called here. */ + qemu_send_packet(qemu_get_queue(emc->nic), buf, length); + trace_npcm7xx_emc_sent_packet(length); + + tx_desc.status_and_length |=3D TX_DESC_STATUS_TXCP; + if (tx_desc.flags & TX_DESC_FLAG_INTEN) { + emc_set_mista(emc, REG_MISTA_TXCP); + } + if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & REG_MISTA_TXINTR) { + tx_desc.status_and_length |=3D TX_DESC_STATUS_TXINTR; + } + + emc_set_next_tx_descriptor(emc, &tx_desc, desc_addr); + emc_update_tx_irq(emc); + trace_npcm7xx_emc_tx_done(emc->regs[REG_CTXDSA]); +} + +static bool emc_can_receive(NetClientState *nc) +{ + NPCM7xxEMCState *emc =3D NPCM7XX_EMC(qemu_get_nic_opaque(nc)); + + bool can_receive =3D emc->rx_active; + trace_npcm7xx_emc_can_receive(can_receive); + return can_receive; +} + +/* If result is false then *fail_reason contains the reason. */ +static bool emc_receive_filter1(NPCM7xxEMCState *emc, const uint8_t *buf, + size_t len, const char **fail_reason) +{ + eth_pkt_types_e pkt_type =3D get_eth_packet_type(PKT_GET_ETH_HDR(buf)); + + switch (pkt_type) { + case ETH_PKT_BCAST: + if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) { + return true; + } else { + *fail_reason =3D "Broadcast packet disabled"; + return !!(emc->regs[REG_CAMCMR] & REG_CAMCMR_ABP); + } + case ETH_PKT_MCAST: + if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) { + return true; + } else { + *fail_reason =3D "Multicast packet disabled"; + return !!(emc->regs[REG_CAMCMR] & REG_CAMCMR_AMP); + } + case ETH_PKT_UCAST: { + bool matches; + if (emc->regs[REG_CAMCMR] & REG_CAMCMR_AUP) { + return true; + } + matches =3D ((emc->regs[REG_CAMCMR] & REG_CAMCMR_ECMP) && + /* We only support one CAM register, CAM0. */ + (emc->regs[REG_CAMEN] & (1 << 0)) && + memcmp(buf, emc->conf.macaddr.a, ETH_ALEN) =3D=3D 0); + if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) { + *fail_reason =3D "MACADDR matched, comparison complemented"; + return !matches; + } else { + *fail_reason =3D "MACADDR didn't match"; + return matches; + } + } + default: + g_assert_not_reached(); + } +} + +static bool emc_receive_filter(NPCM7xxEMCState *emc, const uint8_t *buf, + size_t len) +{ + const char *fail_reason =3D NULL; + bool ok =3D emc_receive_filter1(emc, buf, len, &fail_reason); + if (!ok) { + trace_npcm7xx_emc_packet_filtered_out(fail_reason); + } + return ok; +} + +static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t = len1) +{ + NPCM7xxEMCState *emc =3D NPCM7XX_EMC(qemu_get_nic_opaque(nc)); + const uint32_t len =3D len1; + size_t max_frame_len; + bool long_frame; + uint32_t desc_addr; + NPCM7xxEMCRxDesc rx_desc; + uint32_t crc; + uint8_t *crc_ptr; + uint32_t buf_addr; + + trace_npcm7xx_emc_receiving_packet(len); + + if (!emc_can_receive(nc)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Unexpected packet\n", __func__= ); + return -1; + } + + if (len < ETH_HLEN || + /* Defensive programming: drop unsupportable large packets. */ + len > 0xffff - CRC_LENGTH) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Dropped frame of %u bytes\n", + __func__, len); + return len; + } + + /* + * DENI is set if EMC received the Length/Type field of the incoming + * packet, so it will be set regardless of what happens next. + */ + emc_set_mista(emc, REG_MISTA_DENI); + + if (!emc_receive_filter(emc, buf, len)) { + emc_update_rx_irq(emc); + return len; + } + + /* Huge frames (> DMARFC) are dropped. */ + max_frame_len =3D REG_DMARFC_RXMS(emc->regs[REG_DMARFC]); + if (len + CRC_LENGTH > max_frame_len) { + trace_npcm7xx_emc_packet_dropped(len); + emc_set_mista(emc, REG_MISTA_DFOI); + emc_update_rx_irq(emc); + return len; + } + + /* + * Long Frames (> MAX_ETH_FRAME_SIZE) are also dropped, unless MCMDR.A= LP + * is set. + */ + long_frame =3D false; + if (len + CRC_LENGTH > MAX_ETH_FRAME_SIZE) { + if (emc->regs[REG_MCMDR] & REG_MCMDR_ALP) { + long_frame =3D true; + } else { + trace_npcm7xx_emc_packet_dropped(len); + emc_set_mista(emc, REG_MISTA_PTLE); + emc_update_rx_irq(emc); + return len; + } + } + + desc_addr =3D RX_DESC_NRXDSA(emc->regs[REG_CRXDSA]); + if (emc_read_rx_desc(desc_addr, &rx_desc)) { + /* Error reading descriptor, already reported. */ + emc_halt_rx(emc, REG_MISTA_RXBERR); + emc_update_rx_irq(emc); + return len; + } + + /* Nothing we can do if we don't own the descriptor. */ + if (!(rx_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK)) { + trace_npcm7xx_emc_cpu_owned_desc(desc_addr); + emc_halt_rx(emc, REG_MISTA_RDU); + emc_update_rx_irq(emc); + return len; + } + + crc =3D 0; + crc_ptr =3D (uint8_t *) &crc; + if (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC)) { + crc =3D cpu_to_be32(crc32(~0, buf, len)); + } + + /* Give the descriptor back regardless of what happens. */ + rx_desc.status_and_length &=3D ~RX_DESC_STATUS_OWNER_MASK; + + buf_addr =3D rx_desc.rxbsa; + emc->regs[REG_CRXBSA] =3D buf_addr; + if (dma_memory_write(&address_space_memory, buf_addr, buf, len) || + (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC) && + dma_memory_write(&address_space_memory, buf_addr + len, crc_ptr, + 4))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bus error writing packet\n", + __func__); + emc_set_mista(emc, REG_MISTA_RXBERR); + emc_set_next_rx_descriptor(emc, &rx_desc, desc_addr); + emc_update_rx_irq(emc); + trace_npcm7xx_emc_rx_done(emc->regs[REG_CRXDSA]); + return len; + } + + trace_npcm7xx_emc_received_packet(len); + + /* Note: We've already verified len+4 <=3D 0xffff. */ + rx_desc.status_and_length =3D len; + if (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC)) { + rx_desc.status_and_length +=3D 4; + } + rx_desc.status_and_length |=3D RX_DESC_STATUS_RXGD; + emc_set_mista(emc, REG_MISTA_RXGD); + + if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & REG_MISTA_RXINTR) { + rx_desc.status_and_length |=3D RX_DESC_STATUS_RXINTR; + } + if (long_frame) { + rx_desc.status_and_length |=3D RX_DESC_STATUS_PTLE; + } + + emc_set_next_rx_descriptor(emc, &rx_desc, desc_addr); + emc_update_rx_irq(emc); + trace_npcm7xx_emc_rx_done(emc->regs[REG_CRXDSA]); + return len; +} + +static void emc_try_receive_next_packet(NPCM7xxEMCState *emc) +{ + if (emc_can_receive(qemu_get_queue(emc->nic))) { + qemu_flush_queued_packets(qemu_get_queue(emc->nic)); + } +} + +static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned siz= e) +{ + NPCM7xxEMCState *emc =3D opaque; + uint32_t reg =3D offset / sizeof(uint32_t); + uint32_t result; + + if (reg >=3D NPCM7XX_NUM_EMC_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid offset 0x%04" HWADDR_PRIx "\n", + __func__, offset); + return 0; + } + + switch (reg) { + case REG_MIID: + /* + * We don't implement MII. For determinism, always return zero as + * writes record the last value written for debugging purposes. + */ + qemu_log_mask(LOG_UNIMP, "%s: Read of MIID, returning 0\n", __func= __); + result =3D 0; + break; + case REG_TSDR: + case REG_RSDR: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Read of write-only reg, %s/%d\n", + __func__, emc_reg_name(reg), reg); + return 0; + default: + result =3D emc->regs[reg]; + break; + } + + trace_npcm7xx_emc_reg_read(emc->emc_num, result, emc_reg_name(reg), re= g); + return result; +} + +static void npcm7xx_emc_write(void *opaque, hwaddr offset, + uint64_t v, unsigned size) +{ + NPCM7xxEMCState *emc =3D opaque; + uint32_t reg =3D offset / sizeof(uint32_t); + uint32_t value =3D v; + + g_assert(size =3D=3D sizeof(uint32_t)); + + if (reg >=3D NPCM7XX_NUM_EMC_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid offset 0x%04" HWADDR_PRIx "\n", + __func__, offset); + return; + } + + trace_npcm7xx_emc_reg_write(emc->emc_num, emc_reg_name(reg), reg, valu= e); + + switch (reg) { + case REG_CAMCMR: + emc->regs[reg] =3D value; + break; + case REG_CAMEN: + /* Only CAM0 is supported, don't pretend otherwise. */ + if (value & ~1) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Only CAM0 is supported, cannot enable other= s" + ": 0x%x\n", + __func__, value); + } + emc->regs[reg] =3D value & 1; + break; + case REG_CAMM_BASE + 0: + emc->regs[reg] =3D value; + emc->conf.macaddr.a[0] =3D value >> 24; + emc->conf.macaddr.a[1] =3D value >> 16; + emc->conf.macaddr.a[2] =3D value >> 8; + emc->conf.macaddr.a[3] =3D value >> 0; + break; + case REG_CAML_BASE + 0: + emc->regs[reg] =3D value; + emc->conf.macaddr.a[4] =3D value >> 24; + emc->conf.macaddr.a[5] =3D value >> 16; + break; + case REG_MCMDR: { + uint32_t prev; + if (value & REG_MCMDR_SWR) { + emc_soft_reset(emc); + /* On h/w the reset happens over multiple cycles. For now KISS= . */ + break; + } + prev =3D emc->regs[reg]; + emc->regs[reg] =3D value; + /* Update tx state. */ + if (!(prev & REG_MCMDR_TXON) && + (value & REG_MCMDR_TXON)) { + emc->regs[REG_CTXDSA] =3D emc->regs[REG_TXDLSA]; + /* + * Linux kernel turns TX on with CPU still holding descriptor, + * which suggests we should wait for a write to TSDR before tr= ying + * to send a packet: so we don't send one here. + */ + } else if ((prev & REG_MCMDR_TXON) && + !(value & REG_MCMDR_TXON)) { + emc->regs[REG_MGSTA] |=3D REG_MGSTA_TXHA; + } + if (!(value & REG_MCMDR_TXON)) { + emc_halt_tx(emc, 0); + } + /* Update rx state. */ + if (!(prev & REG_MCMDR_RXON) && + (value & REG_MCMDR_RXON)) { + emc->regs[REG_CRXDSA] =3D emc->regs[REG_RXDLSA]; + } else if ((prev & REG_MCMDR_RXON) && + !(value & REG_MCMDR_RXON)) { + emc->regs[REG_MGSTA] |=3D REG_MGSTA_RXHA; + } + if (!(value & REG_MCMDR_RXON)) { + emc_halt_rx(emc, 0); + } + break; + } + case REG_TXDLSA: + case REG_RXDLSA: + case REG_DMARFC: + case REG_MIID: + emc->regs[reg] =3D value; + break; + case REG_MIEN: + emc->regs[reg] =3D value; + emc_update_irq_from_reg_change(emc); + break; + case REG_MISTA: + /* Clear the bits that have 1 in "value". */ + emc->regs[reg] &=3D ~value; + emc_update_irq_from_reg_change(emc); + break; + case REG_MGSTA: + /* Clear the bits that have 1 in "value". */ + emc->regs[reg] &=3D ~value; + break; + case REG_TSDR: + if (emc->regs[REG_MCMDR] & REG_MCMDR_TXON) { + emc->tx_active =3D true; + /* Keep trying to send packets until we run out. */ + while (emc->tx_active) { + emc_try_send_next_packet(emc); + } + } + break; + case REG_RSDR: + if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) { + emc->rx_active =3D true; + emc_try_receive_next_packet(emc); + } + break; + case REG_MIIDA: + emc->regs[reg] =3D value & ~REG_MIIDA_BUSY; + break; + case REG_MRPC: + case REG_MRPCC: + case REG_MREPC: + case REG_CTXDSA: + case REG_CTXBSA: + case REG_CRXDSA: + case REG_CRXBSA: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Write to read-only reg %s/%d\n", + __func__, emc_reg_name(reg), reg); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: Write to unimplemented reg %s/%d\n", + __func__, emc_reg_name(reg), reg); + break; + } +} + +static const struct MemoryRegionOps npcm7xx_emc_ops =3D { + .read =3D npcm7xx_emc_read, + .write =3D npcm7xx_emc_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void emc_cleanup(NetClientState *nc) +{ + /* Nothing to do yet. */ +} + +static NetClientInfo net_npcm7xx_emc_info =3D { + .type =3D NET_CLIENT_DRIVER_NIC, + .size =3D sizeof(NICState), + .can_receive =3D emc_can_receive, + .receive =3D emc_receive, + .cleanup =3D emc_cleanup, + .link_status_changed =3D emc_set_link, +}; + +static void npcm7xx_emc_realize(DeviceState *dev, Error **errp) +{ + NPCM7xxEMCState *emc =3D NPCM7XX_EMC(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(emc); + + memory_region_init_io(&emc->iomem, OBJECT(emc), &npcm7xx_emc_ops, emc, + TYPE_NPCM7XX_EMC, 4 * KiB); + sysbus_init_mmio(sbd, &emc->iomem); + sysbus_init_irq(sbd, &emc->tx_irq); + sysbus_init_irq(sbd, &emc->rx_irq); + + qemu_macaddr_default_if_unset(&emc->conf.macaddr); + emc->nic =3D qemu_new_nic(&net_npcm7xx_emc_info, &emc->conf, + object_get_typename(OBJECT(dev)), dev->id, emc= ); + qemu_format_nic_info_str(qemu_get_queue(emc->nic), emc->conf.macaddr.a= ); +} + +static void npcm7xx_emc_unrealize(DeviceState *dev) +{ + NPCM7xxEMCState *emc =3D NPCM7XX_EMC(dev); + + qemu_del_nic(emc->nic); +} + +static const VMStateDescription vmstate_npcm7xx_emc =3D { + .name =3D TYPE_NPCM7XX_EMC, + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8(emc_num, NPCM7xxEMCState), + VMSTATE_UINT32_ARRAY(regs, NPCM7xxEMCState, NPCM7XX_NUM_EMC_REGS), + VMSTATE_BOOL(tx_active, NPCM7xxEMCState), + VMSTATE_BOOL(rx_active, NPCM7xxEMCState), + VMSTATE_END_OF_LIST(), + }, +}; + +static Property npcm7xx_emc_properties[] =3D { + DEFINE_NIC_PROPERTIES(NPCM7xxEMCState, conf), + DEFINE_PROP_END_OF_LIST(), +}; + +static void npcm7xx_emc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); + dc->desc =3D "NPCM7xx EMC Controller"; + dc->realize =3D npcm7xx_emc_realize; + dc->unrealize =3D npcm7xx_emc_unrealize; + dc->reset =3D npcm7xx_emc_reset; + dc->vmsd =3D &vmstate_npcm7xx_emc; + device_class_set_props(dc, npcm7xx_emc_properties); +} + +static const TypeInfo npcm7xx_emc_info =3D { + .name =3D TYPE_NPCM7XX_EMC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NPCM7xxEMCState), + .class_init =3D npcm7xx_emc_class_init, +}; + +static void npcm7xx_emc_register_type(void) +{ + type_register_static(&npcm7xx_emc_info); +} + +type_init(npcm7xx_emc_register_type) diff --git a/hw/net/meson.build b/hw/net/meson.build index 4a7051b54a0..af0749c42bb 100644 --- a/hw/net/meson.build +++ b/hw/net/meson.build @@ -35,6 +35,7 @@ softmmu_ss.add(when: 'CONFIG_I82596_COMMON', if_true: fil= es('i82596.c')) softmmu_ss.add(when: 'CONFIG_SUNHME', if_true: files('sunhme.c')) softmmu_ss.add(when: 'CONFIG_FTGMAC100', if_true: files('ftgmac100.c')) softmmu_ss.add(when: 'CONFIG_SUNGEM', if_true: files('sungem.c')) +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_emc.c')) =20 softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_eth.c')) softmmu_ss.add(when: 'CONFIG_COLDFIRE', if_true: files('mcf_fec.c')) diff --git a/hw/net/trace-events b/hw/net/trace-events index 5db45456d92..baf25ffa7e7 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -429,3 +429,20 @@ imx_fec_receive_last(int last) "rx frame flags 0x%04x" imx_enet_receive(size_t size) "len %zu" imx_enet_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d" imx_enet_receive_last(int last) "rx frame flags 0x%04x" + +# npcm7xx_emc.c +npcm7xx_emc_reset(int emc_num) "Resetting emc%d" +npcm7xx_emc_update_tx_irq(int level) "Setting tx irq to %d" +npcm7xx_emc_update_rx_irq(int level) "Setting rx irq to %d" +npcm7xx_emc_set_mista(uint32_t flags) "ORing 0x%x into MISTA" +npcm7xx_emc_cpu_owned_desc(uint32_t addr) "Can't process cpu-owned descrip= tor @0x%x" +npcm7xx_emc_sent_packet(uint32_t len) "Sent %u byte packet" +npcm7xx_emc_tx_done(uint32_t ctxdsa) "TX done, CTXDSA=3D0x%x" +npcm7xx_emc_can_receive(int can_receive) "Can receive: %d" +npcm7xx_emc_packet_filtered_out(const char* fail_reason) "Packet filtered = out: %s" +npcm7xx_emc_packet_dropped(uint32_t len) "%u byte packet dropped" +npcm7xx_emc_receiving_packet(uint32_t len) "Receiving %u byte packet" +npcm7xx_emc_received_packet(uint32_t len) "Received %u byte packet" +npcm7xx_emc_rx_done(uint32_t crxdsa) "RX done, CRXDSA=3D0x%x" +npcm7xx_emc_reg_read(int emc_num, uint32_t result, const char *name, int r= egno) "emc%d: 0x%x =3D reg[%s/%d]" +npcm7xx_emc_reg_write(int emc_num, const char *name, int regno, uint32_t v= alue) "emc%d: reg[%s/%d] =3D 0x%x" --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LzBTmBL9YnEImIkUMy8UG7fGG75xh7OZfoQ3KN3oMP0=; b=Bjtt+jc9wpI9peMoh45GOf1aKFwzrVq8s4CR1WDky5lPwZNZQozAHi4aBQzk5t76OK OHAp63eT+SqzaoKRKtauisNsVt1KXkh3nehoYDEfOTKxvll6N1csKUV5GrVRb6UQRY+E 08XO5k97h1CZhXZ6EZ+H3DaUt2zfbiGziua49vLUtekpPsvhs5xuXfcuCbT7eUa5wrs4 RDhdv1ErnyBF+pp8/KrZJn1C7oM6VtkRlvK4PBeIzJ4PtK9cxqZD8usP+W34HM0NL//E xWTAnd115+5Qv9Se+5tkkw83NZerKB0Xv2pqrQKSaMx176rqxt2pkprXn1pkESE9V39e PElA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LzBTmBL9YnEImIkUMy8UG7fGG75xh7OZfoQ3KN3oMP0=; b=XdF1Ao9c0VgqKIDB2RJxvlEpAfo1btKCS3HCJAr14IbArsm0BWp9Cptnm8V4AcphS3 boJod8hAB/bFR+dFH1rdeZrY/XsZSSnbOa+SKU9KaACF6zauC+X6n1xsi5KulZsbXQu9 C0bqZ7BleMaDs1a9IgR8JAj1GaUKlaXKYtRNQJFK8LDxx3IeHdiRfXt7xeWdClHJ8BQg KBBJjeaI3qYiyqfHDvGgi17AASB/kTmwVXXaMvpm9rcKjhY3vAGaByfO+AcomnfBg8SB cpGQZ5OC2WF6ZFDw7o/rQH5tXl20TKoxB0Qu4/Jksuwq3ywYc3zD3FrJrNS1uKlJlVN2 tAwg== X-Gm-Message-State: AOAM5307SQllO16/zc3Dne/6AA8c4j6lYCXM41X4gBckqFq2bpTmsGAi nyVgOJh4dhFmeTQCwIu6phsDaZiY3G84Ng== X-Google-Smtp-Source: ABdhPJyXuVhgFoRb2FocPRZgJhh7YaSMZxI6G7K0a6e6je4gRaI2Uumkv0oAqjTcmdOUlm8gbVUn5w== X-Received: by 2002:adf:fd87:: with SMTP id d7mr5862414wrr.361.1613048374642; Thu, 11 Feb 2021 04:59:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/45] hw/arm: Add npcm7xx emc model Date: Thu, 11 Feb 2021 12:58:57 +0000 Message-Id: <20210211125900.22777-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Doug Evans This is a 10/100 ethernet device that has several features. Only the ones needed by the Linux driver have been implemented. See npcm7xx_emc.c for a list of unimplemented features. Reviewed-by: Hao Wu Reviewed-by: Avi Fishman Reviewed-by: Peter Maydell Signed-off-by: Doug Evans Message-id: 20210209015541.778833-3-dje@google.com Signed-off-by: Peter Maydell --- docs/system/arm/nuvoton.rst | 3 ++- include/hw/arm/npcm7xx.h | 2 ++ hw/arm/npcm7xx.c | 50 +++++++++++++++++++++++++++++++++++-- 3 files changed, 52 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index a1786342e21..c6e9a4c17e4 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -43,6 +43,7 @@ Supported devices * GPIO controller * Analog to Digital Converter (ADC) * Pulse Width Modulation (PWM) + * Ethernet controller (EMC) =20 Missing devices --------------- @@ -56,7 +57,7 @@ Missing devices * Shared memory (SHM) * eSPI slave interface =20 - * Ethernet controllers (GMAC and EMC) + * Ethernet controller (GMAC) * USB device (USBD) * SMBus controller (SMBF) * Peripheral SPI controller (PSPI) diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index f6227aa8aa8..3bfc75aafed 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -25,6 +25,7 @@ #include "hw/misc/npcm7xx_gcr.h" #include "hw/misc/npcm7xx_pwm.h" #include "hw/misc/npcm7xx_rng.h" +#include "hw/net/npcm7xx_emc.h" #include "hw/nvram/npcm7xx_otp.h" #include "hw/timer/npcm7xx_timer.h" #include "hw/ssi/npcm7xx_fiu.h" @@ -88,6 +89,7 @@ typedef struct NPCM7xxState { EHCISysBusState ehci; OHCISysBusState ohci; NPCM7xxFIUState fiu[2]; + NPCM7xxEMCState emc[2]; } NPCM7xxState; =20 #define TYPE_NPCM7XX "npcm7xx" diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index d1fe9bd1df6..6186ac52772 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -82,6 +82,8 @@ enum NPCM7xxInterrupt { NPCM7XX_UART1_IRQ, NPCM7XX_UART2_IRQ, NPCM7XX_UART3_IRQ, + NPCM7XX_EMC1RX_IRQ =3D 15, + NPCM7XX_EMC1TX_IRQ, NPCM7XX_TIMER0_IRQ =3D 32, /* Timer Module 0 */ NPCM7XX_TIMER1_IRQ, NPCM7XX_TIMER2_IRQ, @@ -104,6 +106,8 @@ enum NPCM7xxInterrupt { NPCM7XX_OHCI_IRQ =3D 62, NPCM7XX_PWM0_IRQ =3D 93, /* PWM module 0 */ NPCM7XX_PWM1_IRQ, /* PWM module 1 */ + NPCM7XX_EMC2RX_IRQ =3D 114, + NPCM7XX_EMC2TX_IRQ, NPCM7XX_GPIO0_IRQ =3D 116, NPCM7XX_GPIO1_IRQ, NPCM7XX_GPIO2_IRQ, @@ -152,6 +156,12 @@ static const hwaddr npcm7xx_pwm_addr[] =3D { 0xf0104000, }; =20 +/* Register base address for each EMC Module */ +static const hwaddr npcm7xx_emc_addr[] =3D { + 0xf0825000, + 0xf0826000, +}; + static const struct { hwaddr regs_addr; uint32_t unconnected_pins; @@ -365,6 +375,10 @@ static void npcm7xx_init(Object *obj) for (i =3D 0; i < ARRAY_SIZE(s->pwm); i++) { object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PW= M); } + + for (i =3D 0; i < ARRAY_SIZE(s->emc); i++) { + object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EM= C); + } } =20 static void npcm7xx_realize(DeviceState *dev, Error **errp) @@ -537,6 +551,40 @@ static void npcm7xx_realize(DeviceState *dev, Error **= errp) sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i)); } =20 + /* + * EMC Modules. Cannot fail. + * The mapping of the device to its netdev backend works as follows: + * emc[i] =3D nd_table[i] + * This works around the inability to specify the netdev property for = the + * emc device: it's not pluggable and thus the -device option can't be + * used. + */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_emc_addr) !=3D ARRAY_SIZE(s->emc)= ); + QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->emc) !=3D 2); + for (i =3D 0; i < ARRAY_SIZE(s->emc); i++) { + s->emc[i].emc_num =3D i; + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->emc[i]); + if (nd_table[i].used) { + qemu_check_nic_model(&nd_table[i], TYPE_NPCM7XX_EMC); + qdev_set_nic_properties(DEVICE(sbd), &nd_table[i]); + } + /* + * The device exists regardless of whether it's connected to a QEMU + * netdev backend. So always instantiate it even if there is no + * backend. + */ + sysbus_realize(sbd, &error_abort); + sysbus_mmio_map(sbd, 0, npcm7xx_emc_addr[i]); + int tx_irq =3D i =3D=3D 0 ? NPCM7XX_EMC1TX_IRQ : NPCM7XX_EMC2TX_IR= Q; + int rx_irq =3D i =3D=3D 0 ? NPCM7XX_EMC1RX_IRQ : NPCM7XX_EMC2RX_IR= Q; + /* + * N.B. The values for the second argument sysbus_connect_irq are + * chosen to match the registration order in npcm7xx_emc_realize. + */ + sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, tx_irq)); + sysbus_connect_irq(sbd, 1, npcm7xx_irq(s, rx_irq)); + } + /* * Flash Interface Unit (FIU). Can fail if incorrect number of chip se= lects * specified, but this is a programming error. @@ -613,8 +661,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **e= rrp) create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * = KiB); create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * = KiB); create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * = KiB); - create_unimplemented_device("npcm7xx.emc1", 0xf0825000, 4 * = KiB); - create_unimplemented_device("npcm7xx.emc2", 0xf0826000, 4 * = KiB); create_unimplemented_device("npcm7xx.usbd[0]", 0xf0830000, 4 * = KiB); create_unimplemented_device("npcm7xx.usbd[1]", 0xf0831000, 4 * = KiB); create_unimplemented_device("npcm7xx.usbd[2]", 0xf0832000, 4 * = KiB); --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613051643; cv=none; d=zohomail.com; s=zohoarc; b=Y1PFcA0AEqsNs88v5NdfITbi5eM1YKuOpLEYlWwQPz8DClFIGKqwY136991B7CT9BnyRlM84V4pMQWyG/TDn7CvKfBI0sh++bDBNsPYtplgS3hX4MfM3XXYt5GbVaKZ53Q6+xTEMxNdFyMMu6pG9ag49ALq53hFMiDAOUehHeXg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613051643; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Hmo22ALV22wG8XZloeyEi/PQVtNXbj1+ipXSRv6tgbo=; b=Ld99hFZe36QP4oHK7S2FSS8LP+lUkZu8/iNTlMwUnRwleOTA183M/WSCeCcmXTmYCojaFgtXV4d0YXauajVb+OxvU24MSNPkMS6I1+jAtxpEtPaR9UWT87GYi/reD4K5loSp92WRRhyr9QaLUaKn13T1HsLZ86eIFF8pZDfMViQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613051642947709.9056413331473; Thu, 11 Feb 2021 05:54:02 -0800 (PST) Received: from localhost ([::1]:50480 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lACPx-0007tT-Oi for importer@patchew.org; Thu, 11 Feb 2021 08:54:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33944) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZW-0000FD-1m for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:51 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:35637) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZJ-000086-Da for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:49 -0500 Received: by mail-wm1-x32e.google.com with SMTP id n10so3780241wmq.0 for ; Thu, 11 Feb 2021 04:59:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Hmo22ALV22wG8XZloeyEi/PQVtNXbj1+ipXSRv6tgbo=; b=LSKOFmIwf7sSg2J1CUwYh4agxm/0vH9IuXl7oAiV9DJns/i0Biz9DIGZXegHeN3JT/ yXXYUuXZRaHij0D6TaiP5Zz+ko34cZOK6rcVuTTvLuFbkPxEX/b/T0iHbsRhheenVjSr ZNPWm5QHVjFZRJtDbQt3ho8N0jjLzfyVuyKzNV8rHfLZpbTKNQvdmuGZ7OEzu4k3ov5/ SERLkVp8ZlT1p/F1X5a7pDLasQcW/jsa0CXQ2SaOnOjrBfiuq81DMwICWiPz3Lrg0TS7 tpv2MAjVlG6wjqt9PZn2zBIfV8M+wIv8gI1LajOhP77g0GzOXNJ8Z7Lyp0Ht08V0YEie nsAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Hmo22ALV22wG8XZloeyEi/PQVtNXbj1+ipXSRv6tgbo=; b=ZVMgoitMH0E5i8/8Ko/67j1d43r/cUTItRU6OcCwWW1aYsvXCMjzQctRRNNYoP1T1H ViO4GvRV7vSlUl+k5GkmGHTK8XJV0ICKAMK35XhbOI9xtDdsExbQ4J1uuImUesOGmEM2 EuZP5kTLm9/33U69P0MczbOUlbSb5wZ4To9kOo0YdQ6fGzP3M0Zh2/zKc5++kBXhCmsf +VEqJpObff7gsTm5R4cOKGgEgED2UHMZwer5Jd3lJxeDjKiH41lux3E8mPol0gz98lrk eiUDONPamg6r1m7MNmDLRfsgQTg7eqn57Osx/Ayn49RC/lfB5iYQJzaiCqlf0mQOQVZC MKHw== X-Gm-Message-State: AOAM532m9d5K4FcAKbkUmXVS+wQxNcC7ywO7d+PEULvFXDVmvfsquyCO KP3myyZTy+erZZ6zEJLu09SS/xlAXxQ/2A== X-Google-Smtp-Source: ABdhPJySuMolgZ9MVjg/fK/wsv5d4IkeIuWwQEwkk54hvw69pcKkZsIiJDAvMdypVfoe5/IsiuKPUg== X-Received: by 2002:a05:600c:3588:: with SMTP id p8mr5131926wmq.71.1613048375694; Thu, 11 Feb 2021 04:59:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 43/45] tests/qtests: Add npcm7xx emc model test Date: Thu, 11 Feb 2021 12:58:58 +0000 Message-Id: <20210211125900.22777-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Doug Evans Reviewed-by: Hao Wu Reviewed-by: Avi Fishman Reviewed-by: Peter Maydell Signed-off-by: Doug Evans Message-id: 20210209015541.778833-4-dje@google.com Signed-off-by: Peter Maydell --- tests/qtest/npcm7xx_emc-test.c | 812 +++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 2 files changed, 813 insertions(+) create mode 100644 tests/qtest/npcm7xx_emc-test.c diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c new file mode 100644 index 00000000000..95712dc3b57 --- /dev/null +++ b/tests/qtest/npcm7xx_emc-test.c @@ -0,0 +1,812 @@ +/* + * QTests for Nuvoton NPCM7xx EMC Modules. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "libqos/libqos.h" +#include "qapi/qmp/qdict.h" +#include "qapi/qmp/qnum.h" +#include "qemu/bitops.h" +#include "qemu/iov.h" + +/* Name of the emc device. */ +#define TYPE_NPCM7XX_EMC "npcm7xx-emc" + +/* Timeout for various operations, in seconds. */ +#define TIMEOUT_SECONDS 10 + +/* Address in memory of the descriptor. */ +#define DESC_ADDR (1 << 20) /* 1 MiB */ + +/* Address in memory of the data packet. */ +#define DATA_ADDR (DESC_ADDR + 4096) + +#define CRC_LENGTH 4 + +#define NUM_TX_DESCRIPTORS 3 +#define NUM_RX_DESCRIPTORS 2 + +/* Size of tx,rx test buffers. */ +#define TX_DATA_LEN 64 +#define RX_DATA_LEN 64 + +#define TX_STEP_COUNT 10000 +#define RX_STEP_COUNT 10000 + +/* 32-bit register indices. */ +typedef enum NPCM7xxPWMRegister { + /* Control registers. */ + REG_CAMCMR, + REG_CAMEN, + + /* There are 16 CAMn[ML] registers. */ + REG_CAMM_BASE, + REG_CAML_BASE, + + REG_TXDLSA =3D 0x22, + REG_RXDLSA, + REG_MCMDR, + REG_MIID, + REG_MIIDA, + REG_FFTCR, + REG_TSDR, + REG_RSDR, + REG_DMARFC, + REG_MIEN, + + /* Status registers. */ + REG_MISTA, + REG_MGSTA, + REG_MPCNT, + REG_MRPC, + REG_MRPCC, + REG_MREPC, + REG_DMARFS, + REG_CTXDSA, + REG_CTXBSA, + REG_CRXDSA, + REG_CRXBSA, + + NPCM7XX_NUM_EMC_REGS, +} NPCM7xxPWMRegister; + +enum { NUM_CAMML_REGS =3D 16 }; + +/* REG_CAMCMR fields */ +/* Enable CAM Compare */ +#define REG_CAMCMR_ECMP (1 << 4) +/* Accept Unicast Packet */ +#define REG_CAMCMR_AUP (1 << 0) + +/* REG_MCMDR fields */ +/* Software Reset */ +#define REG_MCMDR_SWR (1 << 24) +/* Frame Transmission On */ +#define REG_MCMDR_TXON (1 << 8) +/* Accept Long Packet */ +#define REG_MCMDR_ALP (1 << 1) +/* Frame Reception On */ +#define REG_MCMDR_RXON (1 << 0) + +/* REG_MIEN fields */ +/* Enable Transmit Completion Interrupt */ +#define REG_MIEN_ENTXCP (1 << 18) +/* Enable Transmit Interrupt */ +#define REG_MIEN_ENTXINTR (1 << 16) +/* Enable Receive Good Interrupt */ +#define REG_MIEN_ENRXGD (1 << 4) +/* ENable Receive Interrupt */ +#define REG_MIEN_ENRXINTR (1 << 0) + +/* REG_MISTA fields */ +/* Transmit Bus Error Interrupt */ +#define REG_MISTA_TXBERR (1 << 24) +/* Transmit Descriptor Unavailable Interrupt */ +#define REG_MISTA_TDU (1 << 23) +/* Transmit Completion Interrupt */ +#define REG_MISTA_TXCP (1 << 18) +/* Transmit Interrupt */ +#define REG_MISTA_TXINTR (1 << 16) +/* Receive Bus Error Interrupt */ +#define REG_MISTA_RXBERR (1 << 11) +/* Receive Descriptor Unavailable Interrupt */ +#define REG_MISTA_RDU (1 << 10) +/* DMA Early Notification Interrupt */ +#define REG_MISTA_DENI (1 << 9) +/* Maximum Frame Length Interrupt */ +#define REG_MISTA_DFOI (1 << 8) +/* Receive Good Interrupt */ +#define REG_MISTA_RXGD (1 << 4) +/* Packet Too Long Interrupt */ +#define REG_MISTA_PTLE (1 << 3) +/* Receive Interrupt */ +#define REG_MISTA_RXINTR (1 << 0) + +typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc; +typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc; + +struct NPCM7xxEMCTxDesc { + uint32_t flags; + uint32_t txbsa; + uint32_t status_and_length; + uint32_t ntxdsa; +}; + +struct NPCM7xxEMCRxDesc { + uint32_t status_and_length; + uint32_t rxbsa; + uint32_t reserved; + uint32_t nrxdsa; +}; + +/* NPCM7xxEMCTxDesc.flags values */ +/* Owner: 0 =3D cpu, 1 =3D emc */ +#define TX_DESC_FLAG_OWNER_MASK (1 << 31) +/* Transmit interrupt enable */ +#define TX_DESC_FLAG_INTEN (1 << 2) + +/* NPCM7xxEMCTxDesc.status_and_length values */ +/* Transmission complete */ +#define TX_DESC_STATUS_TXCP (1 << 19) +/* Transmit interrupt */ +#define TX_DESC_STATUS_TXINTR (1 << 16) + +/* NPCM7xxEMCRxDesc.status_and_length values */ +/* Owner: 0b00 =3D cpu, 0b10 =3D emc */ +#define RX_DESC_STATUS_OWNER_SHIFT 30 +#define RX_DESC_STATUS_OWNER_MASK 0xc0000000 +/* Frame Reception Complete */ +#define RX_DESC_STATUS_RXGD (1 << 20) +/* Packet too long */ +#define RX_DESC_STATUS_PTLE (1 << 19) +/* Receive Interrupt */ +#define RX_DESC_STATUS_RXINTR (1 << 16) + +#define RX_DESC_PKT_LEN(word) ((uint32_t) (word) & 0xffff) + +typedef struct EMCModule { + int rx_irq; + int tx_irq; + uint64_t base_addr; +} EMCModule; + +typedef struct TestData { + const EMCModule *module; +} TestData; + +static const EMCModule emc_module_list[] =3D { + { + .rx_irq =3D 15, + .tx_irq =3D 16, + .base_addr =3D 0xf0825000 + }, + { + .rx_irq =3D 114, + .tx_irq =3D 115, + .base_addr =3D 0xf0826000 + } +}; + +/* Returns the index of the EMC module. */ +static int emc_module_index(const EMCModule *mod) +{ + ptrdiff_t diff =3D mod - emc_module_list; + + g_assert_true(diff >=3D 0 && diff < ARRAY_SIZE(emc_module_list)); + + return diff; +} + +static void packet_test_clear(void *sockets) +{ + int *test_sockets =3D sockets; + + close(test_sockets[0]); + g_free(test_sockets); +} + +static int *packet_test_init(int module_num, GString *cmd_line) +{ + int *test_sockets =3D g_new(int, 2); + int ret =3D socketpair(PF_UNIX, SOCK_STREAM, 0, test_sockets); + g_assert_cmpint(ret, !=3D , -1); + + /* + * KISS and use -nic. We specify two nics (both emc{0,1}) because ther= e's + * currently no way to specify only emc1: The driver implicitly relies= on + * emc[i] =3D=3D nd_table[i]. + */ + if (module_num =3D=3D 0) { + g_string_append_printf(cmd_line, + " -nic socket,fd=3D%d,model=3D" TYPE_NPCM7X= X_EMC " " + " -nic user,model=3D" TYPE_NPCM7XX_EMC " ", + test_sockets[1]); + } else { + g_string_append_printf(cmd_line, + " -nic user,model=3D" TYPE_NPCM7XX_EMC " " + " -nic socket,fd=3D%d,model=3D" TYPE_NPCM7X= X_EMC " ", + test_sockets[1]); + } + + g_test_queue_destroy(packet_test_clear, test_sockets); + return test_sockets; +} + +static uint32_t emc_read(QTestState *qts, const EMCModule *mod, + NPCM7xxPWMRegister regno) +{ + return qtest_readl(qts, mod->base_addr + regno * sizeof(uint32_t)); +} + +static void emc_write(QTestState *qts, const EMCModule *mod, + NPCM7xxPWMRegister regno, uint32_t value) +{ + qtest_writel(qts, mod->base_addr + regno * sizeof(uint32_t), value); +} + +/* + * Reset the EMC module. + * The module must be reset before, e.g., TXDLSA,RXDLSA are changed. + */ +static bool emc_soft_reset(QTestState *qts, const EMCModule *mod) +{ + uint32_t val; + uint64_t end_time; + + emc_write(qts, mod, REG_MCMDR, REG_MCMDR_SWR); + + /* + * Wait for device to reset as the linux driver does. + * During reset the AHB reads 0 for all registers. So first wait for + * something that resets to non-zero, and then wait for SWR becoming 0. + */ + end_time =3D g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SE= COND; + + do { + qtest_clock_step(qts, 100); + val =3D emc_read(qts, mod, REG_FFTCR); + } while (val =3D=3D 0 && g_get_monotonic_time() < end_time); + if (val !=3D 0) { + do { + qtest_clock_step(qts, 100); + val =3D emc_read(qts, mod, REG_MCMDR); + if ((val & REG_MCMDR_SWR) =3D=3D 0) { + /* + * N.B. The CAMs have been reset here, so macaddr matching= of + * incoming packets will not work. + */ + return true; + } + } while (g_get_monotonic_time() < end_time); + } + + g_message("%s: Timeout expired", __func__); + return false; +} + +/* Check emc registers are reset to default value. */ +static void test_init(gconstpointer test_data) +{ + const TestData *td =3D test_data; + const EMCModule *mod =3D td->module; + QTestState *qts =3D qtest_init("-machine quanta-gsj"); + int i; + +#define CHECK_REG(regno, value) \ + do { \ + g_assert_cmphex(emc_read(qts, mod, (regno)), =3D=3D, (value)); \ + } while (0) + + CHECK_REG(REG_CAMCMR, 0); + CHECK_REG(REG_CAMEN, 0); + CHECK_REG(REG_TXDLSA, 0xfffffffc); + CHECK_REG(REG_RXDLSA, 0xfffffffc); + CHECK_REG(REG_MCMDR, 0); + CHECK_REG(REG_MIID, 0); + CHECK_REG(REG_MIIDA, 0x00900000); + CHECK_REG(REG_FFTCR, 0x0101); + CHECK_REG(REG_DMARFC, 0x0800); + CHECK_REG(REG_MIEN, 0); + CHECK_REG(REG_MISTA, 0); + CHECK_REG(REG_MGSTA, 0); + CHECK_REG(REG_MPCNT, 0x7fff); + CHECK_REG(REG_MRPC, 0); + CHECK_REG(REG_MRPCC, 0); + CHECK_REG(REG_MREPC, 0); + CHECK_REG(REG_DMARFS, 0); + CHECK_REG(REG_CTXDSA, 0); + CHECK_REG(REG_CTXBSA, 0); + CHECK_REG(REG_CRXDSA, 0); + CHECK_REG(REG_CRXBSA, 0); + +#undef CHECK_REG + + for (i =3D 0; i < NUM_CAMML_REGS; ++i) { + g_assert_cmpuint(emc_read(qts, mod, REG_CAMM_BASE + i * 2), =3D=3D, + 0); + g_assert_cmpuint(emc_read(qts, mod, REG_CAML_BASE + i * 2), =3D=3D, + 0); + } + + qtest_quit(qts); +} + +static bool emc_wait_irq(QTestState *qts, const EMCModule *mod, int step, + bool is_tx) +{ + uint64_t end_time =3D + g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND; + + do { + if (qtest_get_irq(qts, is_tx ? mod->tx_irq : mod->rx_irq)) { + return true; + } + qtest_clock_step(qts, step); + } while (g_get_monotonic_time() < end_time); + + g_message("%s: Timeout expired", __func__); + return false; +} + +static bool emc_wait_mista(QTestState *qts, const EMCModule *mod, int step, + uint32_t flag) +{ + uint64_t end_time =3D + g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND; + + do { + uint32_t mista =3D emc_read(qts, mod, REG_MISTA); + if (mista & flag) { + return true; + } + qtest_clock_step(qts, step); + } while (g_get_monotonic_time() < end_time); + + g_message("%s: Timeout expired", __func__); + return false; +} + +static bool wait_socket_readable(int fd) +{ + fd_set read_fds; + struct timeval tv; + int rv; + + FD_ZERO(&read_fds); + FD_SET(fd, &read_fds); + tv.tv_sec =3D TIMEOUT_SECONDS; + tv.tv_usec =3D 0; + rv =3D select(fd + 1, &read_fds, NULL, NULL, &tv); + if (rv =3D=3D -1) { + perror("select"); + } else if (rv =3D=3D 0) { + g_message("%s: Timeout expired", __func__); + } + return rv =3D=3D 1; +} + +static void init_tx_desc(NPCM7xxEMCTxDesc *desc, size_t count, + uint32_t desc_addr) +{ + g_assert(count >=3D 2); + memset(&desc[0], 0, sizeof(*desc) * count); + /* Leave the last one alone, owned by the cpu -> stops transmission. */ + for (size_t i =3D 0; i < count - 1; ++i) { + desc[i].flags =3D + cpu_to_le32(TX_DESC_FLAG_OWNER_MASK | /* owner =3D 1: emc */ + TX_DESC_FLAG_INTEN | + 0 | /* crc append =3D 0 */ + 0 /* padding enable =3D 0 */); + desc[i].status_and_length =3D + cpu_to_le32(0 | /* collision count =3D 0 */ + 0 | /* SQE =3D 0 */ + 0 | /* PAU =3D 0 */ + 0 | /* TXHA =3D 0 */ + 0 | /* LC =3D 0 */ + 0 | /* TXABT =3D 0 */ + 0 | /* NCS =3D 0 */ + 0 | /* EXDEF =3D 0 */ + 0 | /* TXCP =3D 0 */ + 0 | /* DEF =3D 0 */ + 0 | /* TXINTR =3D 0 */ + 0 /* length filled in later */); + desc[i].ntxdsa =3D cpu_to_le32(desc_addr + (i + 1) * sizeof(*desc)= ); + } +} + +static void enable_tx(QTestState *qts, const EMCModule *mod, + const NPCM7xxEMCTxDesc *desc, size_t count, + uint32_t desc_addr, uint32_t mien_flags) +{ + /* Write the descriptors to guest memory. */ + qtest_memwrite(qts, desc_addr, desc, sizeof(*desc) * count); + + /* Trigger sending the packet. */ + /* The module must be reset before changing TXDLSA. */ + g_assert(emc_soft_reset(qts, mod)); + emc_write(qts, mod, REG_TXDLSA, desc_addr); + emc_write(qts, mod, REG_CTXDSA, ~0); + emc_write(qts, mod, REG_MIEN, REG_MIEN_ENTXCP | mien_flags); + { + uint32_t mcmdr =3D emc_read(qts, mod, REG_MCMDR); + mcmdr |=3D REG_MCMDR_TXON; + emc_write(qts, mod, REG_MCMDR, mcmdr); + } + + /* Prod the device to send the packet. */ + emc_write(qts, mod, REG_TSDR, 1); +} + +static void emc_send_verify1(QTestState *qts, const EMCModule *mod, int fd, + bool with_irq, uint32_t desc_addr, + uint32_t next_desc_addr, + const char *test_data, int test_size) +{ + NPCM7xxEMCTxDesc result_desc; + uint32_t expected_mask, expected_value, recv_len; + int ret; + char buffer[TX_DATA_LEN]; + + g_assert(wait_socket_readable(fd)); + + /* Read the descriptor back. */ + qtest_memread(qts, desc_addr, &result_desc, sizeof(result_desc)); + /* Descriptor should be owned by cpu now. */ + g_assert((result_desc.flags & TX_DESC_FLAG_OWNER_MASK) =3D=3D 0); + /* Test the status bits, ignoring the length field. */ + expected_mask =3D 0xffff << 16; + expected_value =3D TX_DESC_STATUS_TXCP; + if (with_irq) { + expected_value |=3D TX_DESC_STATUS_TXINTR; + } + g_assert_cmphex((result_desc.status_and_length & expected_mask), =3D= =3D, + expected_value); + + /* Check data sent to the backend. */ + recv_len =3D ~0; + ret =3D qemu_recv(fd, &recv_len, sizeof(recv_len), MSG_DONTWAIT); + g_assert_cmpint(ret, =3D=3D , sizeof(recv_len)); + + g_assert(wait_socket_readable(fd)); + memset(buffer, 0xff, sizeof(buffer)); + ret =3D qemu_recv(fd, buffer, test_size, MSG_DONTWAIT); + g_assert_cmpmem(buffer, ret, test_data, test_size); +} + +static void emc_send_verify(QTestState *qts, const EMCModule *mod, int fd, + bool with_irq) +{ + NPCM7xxEMCTxDesc desc[NUM_TX_DESCRIPTORS]; + uint32_t desc_addr =3D DESC_ADDR; + static const char test1_data[] =3D "TEST1"; + static const char test2_data[] =3D "Testing 1 2 3 ..."; + uint32_t data1_addr =3D DATA_ADDR; + uint32_t data2_addr =3D data1_addr + sizeof(test1_data); + bool got_tdu; + uint32_t end_desc_addr; + + /* Prepare test data buffer. */ + qtest_memwrite(qts, data1_addr, test1_data, sizeof(test1_data)); + qtest_memwrite(qts, data2_addr, test2_data, sizeof(test2_data)); + + init_tx_desc(&desc[0], NUM_TX_DESCRIPTORS, desc_addr); + desc[0].txbsa =3D cpu_to_le32(data1_addr); + desc[0].status_and_length |=3D sizeof(test1_data); + desc[1].txbsa =3D cpu_to_le32(data2_addr); + desc[1].status_and_length |=3D sizeof(test2_data); + + enable_tx(qts, mod, &desc[0], NUM_TX_DESCRIPTORS, desc_addr, + with_irq ? REG_MIEN_ENTXINTR : 0); + + /* + * It's problematic to observe the interrupt for each packet. + * Instead just wait until all the packets go out. + */ + got_tdu =3D false; + while (!got_tdu) { + if (with_irq) { + g_assert_true(emc_wait_irq(qts, mod, TX_STEP_COUNT, + /*is_tx=3D*/true)); + } else { + g_assert_true(emc_wait_mista(qts, mod, TX_STEP_COUNT, + REG_MISTA_TXINTR)); + } + got_tdu =3D !!(emc_read(qts, mod, REG_MISTA) & REG_MISTA_TDU); + /* If we don't have TDU yet, reset the interrupt. */ + if (!got_tdu) { + emc_write(qts, mod, REG_MISTA, + emc_read(qts, mod, REG_MISTA) & 0xffff0000); + } + } + + end_desc_addr =3D desc_addr + 2 * sizeof(desc[0]); + g_assert_cmphex(emc_read(qts, mod, REG_CTXDSA), =3D=3D, end_desc_addr); + g_assert_cmphex(emc_read(qts, mod, REG_MISTA), =3D=3D, + REG_MISTA_TXCP | REG_MISTA_TXINTR | REG_MISTA_TDU); + + emc_send_verify1(qts, mod, fd, with_irq, + desc_addr, end_desc_addr, + test1_data, sizeof(test1_data)); + emc_send_verify1(qts, mod, fd, with_irq, + desc_addr + sizeof(desc[0]), end_desc_addr, + test2_data, sizeof(test2_data)); +} + +static void init_rx_desc(NPCM7xxEMCRxDesc *desc, size_t count, + uint32_t desc_addr, uint32_t data_addr) +{ + g_assert_true(count >=3D 2); + memset(desc, 0, sizeof(*desc) * count); + desc[0].rxbsa =3D cpu_to_le32(data_addr); + desc[0].status_and_length =3D + cpu_to_le32(0b10 << RX_DESC_STATUS_OWNER_SHIFT | /* owner =3D 10: = emc */ + 0 | /* RP =3D 0 */ + 0 | /* ALIE =3D 0 */ + 0 | /* RXGD =3D 0 */ + 0 | /* PTLE =3D 0 */ + 0 | /* CRCE =3D 0 */ + 0 | /* RXINTR =3D 0 */ + 0 /* length (filled in later) */); + /* Leave the last one alone, owned by the cpu -> stops transmission. */ + desc[0].nrxdsa =3D cpu_to_le32(desc_addr + sizeof(*desc)); +} + +static void enable_rx(QTestState *qts, const EMCModule *mod, + const NPCM7xxEMCRxDesc *desc, size_t count, + uint32_t desc_addr, uint32_t mien_flags, + uint32_t mcmdr_flags) +{ + /* + * Write the descriptor to guest memory. + * FWIW, IWBN if the docs said the buffer needs to be at least DMARFC + * bytes. + */ + qtest_memwrite(qts, desc_addr, desc, sizeof(*desc) * count); + + /* Trigger receiving the packet. */ + /* The module must be reset before changing RXDLSA. */ + g_assert(emc_soft_reset(qts, mod)); + emc_write(qts, mod, REG_RXDLSA, desc_addr); + emc_write(qts, mod, REG_MIEN, REG_MIEN_ENRXGD | mien_flags); + + /* + * We don't know what the device's macaddr is, so just accept all + * unicast packets (AUP). + */ + emc_write(qts, mod, REG_CAMCMR, REG_CAMCMR_AUP); + emc_write(qts, mod, REG_CAMEN, 1 << 0); + { + uint32_t mcmdr =3D emc_read(qts, mod, REG_MCMDR); + mcmdr |=3D REG_MCMDR_RXON | mcmdr_flags; + emc_write(qts, mod, REG_MCMDR, mcmdr); + } + + /* Prod the device to accept a packet. */ + emc_write(qts, mod, REG_RSDR, 1); +} + +static void emc_recv_verify(QTestState *qts, const EMCModule *mod, int fd, + bool with_irq) +{ + NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS]; + uint32_t desc_addr =3D DESC_ADDR; + uint32_t data_addr =3D DATA_ADDR; + int ret; + uint32_t expected_mask, expected_value; + NPCM7xxEMCRxDesc result_desc; + + /* Prepare test data buffer. */ + const char test[RX_DATA_LEN] =3D "TEST"; + int len =3D htonl(sizeof(test)); + const struct iovec iov[] =3D { + { + .iov_base =3D &len, + .iov_len =3D sizeof(len), + },{ + .iov_base =3D (char *) test, + .iov_len =3D sizeof(test), + }, + }; + + /* + * Reset the device BEFORE sending a test packet, otherwise the packet + * may get swallowed by an active device of an earlier test. + */ + init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr); + enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr, + with_irq ? REG_MIEN_ENRXINTR : 0, 0); + + /* Send test packet to device's socket. */ + ret =3D iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test)); + g_assert_cmpint(ret, =3D=3D , sizeof(test) + sizeof(len)); + + /* Wait for RX interrupt. */ + if (with_irq) { + g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=3D*/fa= lse)); + } else { + g_assert_true(emc_wait_mista(qts, mod, RX_STEP_COUNT, REG_MISTA_RX= GD)); + } + + g_assert_cmphex(emc_read(qts, mod, REG_CRXDSA), =3D=3D, + desc_addr + sizeof(desc[0])); + + expected_mask =3D 0xffff; + expected_value =3D (REG_MISTA_DENI | + REG_MISTA_RXGD | + REG_MISTA_RXINTR); + g_assert_cmphex((emc_read(qts, mod, REG_MISTA) & expected_mask), + =3D=3D, expected_value); + + /* Read the descriptor back. */ + qtest_memread(qts, desc_addr, &result_desc, sizeof(result_desc)); + /* Descriptor should be owned by cpu now. */ + g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) = =3D=3D 0); + /* Test the status bits, ignoring the length field. */ + expected_mask =3D 0xffff << 16; + expected_value =3D RX_DESC_STATUS_RXGD; + if (with_irq) { + expected_value |=3D RX_DESC_STATUS_RXINTR; + } + g_assert_cmphex((result_desc.status_and_length & expected_mask), =3D= =3D, + expected_value); + g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), =3D=3D, + RX_DATA_LEN + CRC_LENGTH); + + { + char buffer[RX_DATA_LEN]; + qtest_memread(qts, data_addr, buffer, sizeof(buffer)); + g_assert_cmpstr(buffer, =3D=3D , "TEST"); + } +} + +static void emc_test_ptle(QTestState *qts, const EMCModule *mod, int fd) +{ + NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS]; + uint32_t desc_addr =3D DESC_ADDR; + uint32_t data_addr =3D DATA_ADDR; + int ret; + NPCM7xxEMCRxDesc result_desc; + uint32_t expected_mask, expected_value; + + /* Prepare test data buffer. */ +#define PTLE_DATA_LEN 1600 + char test_data[PTLE_DATA_LEN]; + int len =3D htonl(sizeof(test_data)); + const struct iovec iov[] =3D { + { + .iov_base =3D &len, + .iov_len =3D sizeof(len), + },{ + .iov_base =3D (char *) test_data, + .iov_len =3D sizeof(test_data), + }, + }; + memset(test_data, 42, sizeof(test_data)); + + /* + * Reset the device BEFORE sending a test packet, otherwise the packet + * may get swallowed by an active device of an earlier test. + */ + init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr); + enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr, + REG_MIEN_ENRXINTR, REG_MCMDR_ALP); + + /* Send test packet to device's socket. */ + ret =3D iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test_data)); + g_assert_cmpint(ret, =3D=3D , sizeof(test_data) + sizeof(len)); + + /* Wait for RX interrupt. */ + g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=3D*/false)= ); + + /* Read the descriptor back. */ + qtest_memread(qts, desc_addr, &result_desc, sizeof(result_desc)); + /* Descriptor should be owned by cpu now. */ + g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) = =3D=3D 0); + /* Test the status bits, ignoring the length field. */ + expected_mask =3D 0xffff << 16; + expected_value =3D (RX_DESC_STATUS_RXGD | + RX_DESC_STATUS_PTLE | + RX_DESC_STATUS_RXINTR); + g_assert_cmphex((result_desc.status_and_length & expected_mask), =3D= =3D, + expected_value); + g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), =3D=3D, + PTLE_DATA_LEN + CRC_LENGTH); + + { + char buffer[PTLE_DATA_LEN]; + qtest_memread(qts, data_addr, buffer, sizeof(buffer)); + g_assert(memcmp(buffer, test_data, PTLE_DATA_LEN) =3D=3D 0); + } +} + +static void test_tx(gconstpointer test_data) +{ + const TestData *td =3D test_data; + GString *cmd_line =3D g_string_new("-machine quanta-gsj"); + int *test_sockets =3D packet_test_init(emc_module_index(td->module), + cmd_line); + QTestState *qts =3D qtest_init(cmd_line->str); + + /* + * TODO: For pedantic correctness test_sockets[0] should be closed aft= er + * the fork and before the exec, but that will require some harness + * improvements. + */ + close(test_sockets[1]); + /* Defensive programming */ + test_sockets[1] =3D -1; + + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + + emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=3D*/false= ); + emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=3D*/true); + + qtest_quit(qts); +} + +static void test_rx(gconstpointer test_data) +{ + const TestData *td =3D test_data; + GString *cmd_line =3D g_string_new("-machine quanta-gsj"); + int *test_sockets =3D packet_test_init(emc_module_index(td->module), + cmd_line); + QTestState *qts =3D qtest_init(cmd_line->str); + + /* + * TODO: For pedantic correctness test_sockets[0] should be closed aft= er + * the fork and before the exec, but that will require some harness + * improvements. + */ + close(test_sockets[1]); + /* Defensive programming */ + test_sockets[1] =3D -1; + + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + + emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=3D*/false= ); + emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=3D*/true); + emc_test_ptle(qts, td->module, test_sockets[0]); + + qtest_quit(qts); +} + +static void emc_add_test(const char *name, const TestData* td, + GTestDataFunc fn) +{ + g_autofree char *full_name =3D g_strdup_printf( + "npcm7xx_emc/emc[%d]/%s", emc_module_index(td->module), name); + qtest_add_data_func(full_name, td, fn); +} +#define add_test(name, td) emc_add_test(#name, td, test_##name) + +int main(int argc, char **argv) +{ + TestData test_data_list[ARRAY_SIZE(emc_module_list)]; + + g_test_init(&argc, &argv, NULL); + + for (int i =3D 0; i < ARRAY_SIZE(emc_module_list); ++i) { + TestData *td =3D &test_data_list[i]; + + td->module =3D &emc_module_list[i]; + + add_test(init, td); + add_test(tx, td); + add_test(rx, td); + } + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index c83bc211b6a..f7c369f3d54 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -136,6 +136,7 @@ qtests_sparc64 =3D \ =20 qtests_npcm7xx =3D \ ['npcm7xx_adc-test', + 'npcm7xx_emc-test', 'npcm7xx_gpio-test', 'npcm7xx_pwm-test', 'npcm7xx_rng-test', --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ixe3xEWCLqFO6/uGt+eEF2dyjdPefbmj6m2Mbhi11Aw=; b=AeZvTcMGHb5fzCkW5DySJRIJzub/Zj0F29idykz90LbYya9B3zTuG7CcAp4ROSXOg8 CsGb25HnlbqSPqFAKS/Hd7r51AuHragMHIBLd5IsQZhqyUHVcgqcddwdr63SI+orY8FI hefQNySdZFOZ6AClwfVDQ9sBA/mMTNuq/0Oxnys5RF3cfQSuYaaKJEa8m64z2lnovsAv A+uBoUk6GvNFJ0B6mVrPPsumHp2ylVruTH1MJLRDyDgBAmJfXcBHT249D9lb/4RAPOxS D0MKNljqMVTW/qC+TzagjIAH0pqCCpGpGELm7DYK6hwqC86RcyIgk378WotKMYeswJrj xzyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ixe3xEWCLqFO6/uGt+eEF2dyjdPefbmj6m2Mbhi11Aw=; b=qJPJ8Yrz+tpc52riwCHjs2MLgAR7k/Mvqm618I6hPj0P31hHn0WyudYMvBhGgIovjK K9Gam6DY3Vqhb0I8RgSP8mDh3zY7plWeuuxqlnxFRdjez7nGAVLIrO5f1f73J9VuMc9T O2KQ4eu1hM34Bic501Cmnwj8PuylCe/nQKerd/GucoG1HXMIFl6IFkyLsoPuUD6QarCU j/2ztxIvazQjpssXnIxZrUuF97QDGgnAPmuDv2q+zusT8UXP39nlm9MyzIKsuA2Sypfx 0KIfSwk8I6nPpIrtrBFBB0k7c85UW3yNfJL6XOPl9UZeUhFtRClZSw3r+qRV7zmLGG7r cQYw== X-Gm-Message-State: AOAM53085rfHTUSeWVMoGfRjXn+wEcNfxn6KT6xTkN8nY0hHFd7Bhuu9 dR/QFMh8lm0MQPbMOflC6fCDsqbTS4HoCw== X-Google-Smtp-Source: ABdhPJxRQ0BfEHbkmkbR7XhtkrgMNl410q+QDpwycZ07PV3tB1er/aKT2tWj0GEF3anRcEq0dOnYmA== X-Received: by 2002:a1c:6289:: with SMTP id w131mr5263405wmb.0.1613048376297; Thu, 11 Feb 2021 04:59:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 44/45] hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2 Date: Thu, 11 Feb 2021 12:58:59 +0000 Message-Id: <20210211125900.22777-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: "Edgar E. Iglesias" Use nr_apu_cpus in favor of hard coding 2. Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Luc Michel Message-id: 20210210142048.3125878-2-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/arm/xlnx-versal.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index b0777166e89..628e77ef660 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -67,10 +67,10 @@ static void versal_create_apu_gic(Versal *s, qemu_irq *= pic) gicbusdev =3D SYS_BUS_DEVICE(&s->fpd.apu.gic); gicdev =3D DEVICE(&s->fpd.apu.gic); qdev_prop_set_uint32(gicdev, "revision", 3); - qdev_prop_set_uint32(gicdev, "num-cpu", 2); + qdev_prop_set_uint32(gicdev, "num-cpu", nr_apu_cpus); qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32); qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1); - qdev_prop_set_uint32(gicdev, "redist-region-count[0]", 2); + qdev_prop_set_uint32(gicdev, "redist-region-count[0]", nr_apu_cpus); qdev_prop_set_bit(gicdev, "has-security-extensions", true); =20 sysbus_realize(SYS_BUS_DEVICE(&s->fpd.apu.gic), &error_fatal); --=20 2.20.1 From nobody Fri May 3 05:07:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613051484; cv=none; d=zohomail.com; s=zohoarc; b=aOr3Txi8OXi/XTG+tJgnRO+68zQbJwkpDbb7NKlWL+frD2+RXQu1DpBjeFQq0kifEu9gJUBTSCLX/ZMJjxqT1SXJxTMAn/5zVhUFDNZHzVA1Fr3xNiIfPlmtMjsRORNlZHMA9ofUDV4ZRq2zsGnCM0ckByasquNsPFN7mt54ymg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613051484; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+xKp4USF8HdcDvFONqzcb5CsKSqkOk9RvnsPo2dYa6Q=; b=etw24weiSKnaTRiSWl5bUnUroRoHY2blSpWEPbC2K+LmGVvzEmH5CE7MGjJOm5zWYJrcCjcnV3zvyDrl6MW6Wn74SxOoJmxgid8PsZFuwh/8ZAPZRIJPLBBsLs8Hr0dfxHm8pjmPPiqAcOOM/VuXwezPQWwwpIUrumj2iI9aPyc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613051483911545.6880649939503; Thu, 11 Feb 2021 05:51:23 -0800 (PST) Received: from localhost ([::1]:41782 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lACNO-0004C0-OC for importer@patchew.org; Thu, 11 Feb 2021 08:51:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33916) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lABZT-0000D8-R1 for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:47 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:52378) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lABZK-00009r-2z for qemu-devel@nongnu.org; Thu, 11 Feb 2021 07:59:47 -0500 Received: by mail-wm1-x32e.google.com with SMTP id l17so3920269wmq.2 for ; Thu, 11 Feb 2021 04:59:37 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g15sm4955716wrx.1.2021.02.11.04.59.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 04:59:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+xKp4USF8HdcDvFONqzcb5CsKSqkOk9RvnsPo2dYa6Q=; b=K90Ye++pe7OxoQFaKHP+ll2MmniIflL5xVIXePq9EReK/1wqllO67vhif1NDKJyI3S /mIhIhkekGpjAoEE8KzLTHExh19vMKd7vqb9TJW9T0BOsbpMROUlWbinRa7iR2burrEP DLcXVHD02dtxLp3KJtoEX+NvZK+5Lig2hrESIfBKF2Pk5ZbMjenr5FoHq8K63UnR+JLz EtYWHw10SNajeYZgbuWF1I2dJZ+pT8N8WprMHNxCqX9MWT/4FLxAuYJZiTN5fQRDNfZv C31JFYVwrZhCZvGeg6MidzfQDaD012exzt0K49qxzLiXpNSS8ZpWZ1MTvHtLVTiAwYPX h13Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+xKp4USF8HdcDvFONqzcb5CsKSqkOk9RvnsPo2dYa6Q=; b=i2nnfbGQcusFP92XEq5m2bgLwJTm8YeQ0NZ77rSpSWHVb1XP1r1wX0xnAaPJtDmkR7 5LhW60+ZB03VMJojKoIfuJQLrZglKs6HyEWrxm+15KWIcIOQV2HnAZl2CuxwZNldDq6r Y4DPcR+4e1taVra85lrK1n7GyYNQSijeSZRcIajDNHM+2oh04OIK+oVhlikdAr5DTaT/ RJRHlzbPp3brYmQPuftRpxo5kyAiYIbNLWD/RwLsScln8uP+N121OaBYLb6rYvsIw1FE 8JKF4v/jMcLbB4ugvRonJ/PZbybQMpQ5dihK5aB2hlj0VJfjjyjy7v+bdopnlhlgE3Rk CiVg== X-Gm-Message-State: AOAM530/tOA2pwcXO7u78op3GWDasPDsGyCMz08x9Z6S764IoaANfsyK AAi/wV0rufVIWhq/U+FEJSU9s3+6OuYi0Q== X-Google-Smtp-Source: ABdhPJz81L3a4r7sV9o8BOMITShIp9jyH6oyuZSnsPxXpP4Ppur92HCjuPJnd+ucoI37qGdos2egjw== X-Received: by 2002:a7b:c04c:: with SMTP id u12mr5133746wmc.185.1613048376951; Thu, 11 Feb 2021 04:59:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 45/45] target/arm: Correctly initialize MDCR_EL2.HPMN Date: Thu, 11 Feb 2021 12:59:00 +0000 Message-Id: <20210211125900.22777-46-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210211125900.22777-1-peter.maydell@linaro.org> References: <20210211125900.22777-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Daniel M=C3=BCller When working with performance monitoring counters, we look at MDCR_EL2.HPMN as part of the check whether a counter is enabled. This check fails, because MDCR_EL2.HPMN is reset to 0, meaning that no counters are "enabled" for < EL2. That's in violation of the Arm specification, which states that > On a Warm reset, this field [MDCR_EL2.HPMN] resets to the value in > PMCR_EL0.N That's also what a comment in the code acknowledges, but the necessary adjustment seems to have been forgotten when support for more counters was added. This change fixes the issue by setting the reset value to PMCR.N, which is four. Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2c27077fb2d..0e1a3b94211 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -38,6 +38,7 @@ #endif =20 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ +#define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */ =20 #ifndef CONFIG_USER_ONLY =20 @@ -5735,13 +5736,11 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .writefn =3D gt_hyp_ctl_write, .raw_writefn =3D raw_write }, #endif /* The only field of MDCR_EL2 that has a defined architectural reset v= alue - * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but= we - * don't implement any PMU event counters, so using zero as a reset - * value for MDCR_EL2 is okay + * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N. */ { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .resetvalue =3D 0, + .access =3D PL2_RW, .resetvalue =3D PMCR_NUM_COUNTERS, .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr_el2), }, { .name =3D "HPFAR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, @@ -6672,7 +6671,7 @@ static void define_pmu_regs(ARMCPU *cpu) * field as main ID register, and we implement four counters in * addition to the cycle count register. */ - unsigned int i, pmcrn =3D 4; + unsigned int i, pmcrn =3D PMCR_NUM_COUNTERS; ARMCPRegInfo pmcr =3D { .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 0, .access =3D PL0_RW, --=20 2.20.1