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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.21; envelope-from=its@irrelevant.dk; helo=wout5-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Gollu Appalanaidu , Max Reitz , Klaus Jensen , Keith Busch Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Gollu Appalanaidu Add the 'oncs' nvme device parameter to allow optional features to be enabled/disabled explicitly. Since most of these are optional commands, make the CSE log pages dynamic to account for the value of ONCS. Signed-off-by: Gollu Appalanaidu Signed-off-by: Klaus Jensen Reviewed-by: Minwoo Im --- hw/block/nvme.h | 7 ++++ hw/block/nvme.c | 101 ++++++++++++++++++++++++++++++++---------------- 2 files changed, 74 insertions(+), 34 deletions(-) diff --git a/hw/block/nvme.h b/hw/block/nvme.h index cb2b5175f1a1..98082b2dfba3 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -9,6 +9,7 @@ =20 #define NVME_DEFAULT_ZONE_SIZE (128 * MiB) #define NVME_DEFAULT_MAX_ZA_SIZE (128 * KiB) +#define NVME_MAX_COMMANDS 0x100 =20 typedef struct NvmeParams { char *serial; @@ -22,6 +23,7 @@ typedef struct NvmeParams { bool use_intel_id; uint32_t zasl_bs; bool legacy_cmb; + uint16_t oncs; } NvmeParams; =20 typedef struct NvmeAsyncEvent { @@ -183,6 +185,11 @@ typedef struct NvmeCtrl { NvmeCQueue admin_cq; NvmeIdCtrl id_ctrl; NvmeFeatureVal features; + + struct { + uint32_t nvm[NVME_MAX_COMMANDS]; + uint32_t zoned[NVME_MAX_COMMANDS]; + } iocs; } NvmeCtrl; =20 static inline NvmeNamespace *nvme_ns(NvmeCtrl *n, uint32_t nsid) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 93345bf3c1fc..e5f6666725d7 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -71,6 +71,11 @@ * data size being in effect. By setting this property to 0, users can m= ake * ZASL to be equal to MDTS. This property only affects zoned namespaces. * + * - `oncs` + * This field indicates the optional NVM commands and features supported + * by the controller. To add support for the optional feature, needs to + * set the corresponding support indicated bit. + * * nvme namespace device parameters * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ * - `subsys` @@ -165,7 +170,7 @@ static const uint32_t nvme_feature_cap[NVME_FID_MAX] = =3D { [NVME_TIMESTAMP] =3D NVME_FEAT_CAP_CHANGE, }; =20 -static const uint32_t nvme_cse_acs[256] =3D { +static const uint32_t nvme_cse_acs[NVME_MAX_COMMANDS] =3D { [NVME_ADM_CMD_DELETE_SQ] =3D NVME_CMD_EFF_CSUPP, [NVME_ADM_CMD_CREATE_SQ] =3D NVME_CMD_EFF_CSUPP, [NVME_ADM_CMD_GET_LOG_PAGE] =3D NVME_CMD_EFF_CSUPP, @@ -178,30 +183,7 @@ static const uint32_t nvme_cse_acs[256] =3D { [NVME_ADM_CMD_ASYNC_EV_REQ] =3D NVME_CMD_EFF_CSUPP, }; =20 -static const uint32_t nvme_cse_iocs_none[256]; - -static const uint32_t nvme_cse_iocs_nvm[256] =3D { - [NVME_CMD_FLUSH] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_WRITE_ZEROES] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_WRITE] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_READ] =3D NVME_CMD_EFF_CSUPP, - [NVME_CMD_DSM] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_COPY] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_COMPARE] =3D NVME_CMD_EFF_CSUPP, -}; - -static const uint32_t nvme_cse_iocs_zoned[256] =3D { - [NVME_CMD_FLUSH] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_WRITE_ZEROES] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_WRITE] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_READ] =3D NVME_CMD_EFF_CSUPP, - [NVME_CMD_DSM] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_COPY] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_COMPARE] =3D NVME_CMD_EFF_CSUPP, - [NVME_CMD_ZONE_APPEND] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_ZONE_MGMT_SEND] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, - [NVME_CMD_ZONE_MGMT_RECV] =3D NVME_CMD_EFF_CSUPP, -}; +static const uint32_t nvme_cse_iocs_none[NVME_MAX_COMMANDS]; =20 static void nvme_process_sq(void *opaque); =20 @@ -2884,17 +2866,17 @@ static uint16_t nvme_cmd_effects(NvmeCtrl *n, uint8= _t csi, uint32_t buf_len, =20 switch (NVME_CC_CSS(n->bar.cc)) { case NVME_CC_CSS_NVM: - src_iocs =3D nvme_cse_iocs_nvm; + src_iocs =3D n->iocs.nvm; /* fall through */ case NVME_CC_CSS_ADMIN_ONLY: break; case NVME_CC_CSS_CSI: switch (csi) { case NVME_CSI_NVM: - src_iocs =3D nvme_cse_iocs_nvm; + src_iocs =3D n->iocs.nvm; break; case NVME_CSI_ZONED: - src_iocs =3D nvme_cse_iocs_zoned; + src_iocs =3D n->iocs.zoned; break; } } @@ -3422,6 +3404,10 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeRe= quest *req) return NVME_INVALID_FIELD | NVME_DNR; } =20 + if (!(le16_to_cpu(n->id_ctrl.oncs) & NVME_ONCS_FEATURES) && sel) { + return NVME_INVALID_FIELD | NVME_DNR; + } + if (nvme_feature_cap[fid] & NVME_FEAT_CAP_NS) { if (!nvme_nsid_valid(n, nsid) || nsid =3D=3D NVME_NSID_BROADCAST) { /* @@ -3503,6 +3489,9 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeReq= uest *req) result =3D n->features.async_config; goto out; case NVME_TIMESTAMP: + if (!(le16_to_cpu(n->id_ctrl.oncs) & NVME_ONCS_TIMESTAMP)) { + return NVME_INVALID_FIELD | NVME_DNR; + } return nvme_get_feature_timestamp(n, req); default: break; @@ -3585,6 +3574,10 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeRe= quest *req) return NVME_FID_NOT_SAVEABLE | NVME_DNR; } =20 + if (!(le16_to_cpu(n->id_ctrl.oncs) & NVME_ONCS_FEATURES) && save) { + return NVME_INVALID_FIELD | NVME_DNR; + } + if (!nvme_feature_support[fid]) { return NVME_INVALID_FIELD | NVME_DNR; } @@ -3697,6 +3690,9 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeReq= uest *req) n->features.async_config =3D dw11; break; case NVME_TIMESTAMP: + if (!(le16_to_cpu(n->id_ctrl.oncs) & NVME_ONCS_TIMESTAMP)) { + return NVME_INVALID_FIELD | NVME_DNR; + } return nvme_set_feature_timestamp(n, req); case NVME_COMMAND_SET_PROFILE: if (dw11 & 0x1ff) { @@ -3875,14 +3871,14 @@ static void nvme_select_ns_iocs(NvmeCtrl *n) switch (ns->csi) { case NVME_CSI_NVM: if (NVME_CC_CSS(n->bar.cc) !=3D NVME_CC_CSS_ADMIN_ONLY) { - ns->iocs =3D nvme_cse_iocs_nvm; + ns->iocs =3D n->iocs.nvm; } break; case NVME_CSI_ZONED: if (NVME_CC_CSS(n->bar.cc) =3D=3D NVME_CC_CSS_CSI) { - ns->iocs =3D nvme_cse_iocs_zoned; + ns->iocs =3D n->iocs.zoned; } else if (NVME_CC_CSS(n->bar.cc) =3D=3D NVME_CC_CSS_NVM) { - ns->iocs =3D nvme_cse_iocs_nvm; + ns->iocs =3D n->iocs.nvm; } break; } @@ -4510,6 +4506,40 @@ static void nvme_check_constraints(NvmeCtrl *n, Erro= r **errp) } } =20 +static void nvme_init_cse_iocs(NvmeCtrl *n) +{ + uint16_t oncs =3D n->params.oncs; + + n->iocs.nvm[NVME_CMD_FLUSH] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC; + n->iocs.nvm[NVME_CMD_WRITE] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC; + n->iocs.nvm[NVME_CMD_READ] =3D NVME_CMD_EFF_CSUPP; + + if (oncs & NVME_ONCS_WRITE_ZEROES) { + n->iocs.nvm[NVME_CMD_WRITE_ZEROES] =3D NVME_CMD_EFF_CSUPP | + NVME_CMD_EFF_LBCC; + } + + if (oncs & NVME_ONCS_COMPARE) { + n->iocs.nvm[NVME_CMD_COMPARE] =3D NVME_CMD_EFF_CSUPP; + } + + if (oncs & NVME_ONCS_DSM) { + n->iocs.nvm[NVME_CMD_DSM] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LB= CC; + } + + if (oncs & NVME_ONCS_COPY) { + n->iocs.nvm[NVME_CMD_COPY] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_L= BCC; + } + + memcpy(n->iocs.zoned, n->iocs.nvm, sizeof(n->iocs.nvm)); + + n->iocs.zoned[NVME_CMD_ZONE_APPEND] =3D NVME_CMD_EFF_CSUPP | + NVME_CMD_EFF_LBCC; + n->iocs.zoned[NVME_CMD_ZONE_MGMT_SEND] =3D NVME_CMD_EFF_CSUPP | + NVME_CMD_EFF_LBCC; + n->iocs.zoned[NVME_CMD_ZONE_MGMT_RECV] =3D NVME_CMD_EFF_CSUPP; +} + static void nvme_init_state(NvmeCtrl *n) { n->num_namespaces =3D NVME_MAX_NAMESPACES; @@ -4522,6 +4552,8 @@ static void nvme_init_state(NvmeCtrl *n) n->features.temp_thresh_hi =3D NVME_TEMPERATURE_WARNING; n->starttime_ms =3D qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); n->aer_reqs =3D g_new0(NvmeRequest *, n->params.aerl + 1); + + nvme_init_cse_iocs(n); } =20 int nvme_register_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **errp) @@ -4720,9 +4752,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pc= i_dev) id->sqes =3D (0x6 << 4) | 0x6; id->cqes =3D (0x4 << 4) | 0x4; id->nn =3D cpu_to_le32(n->num_namespaces); - id->oncs =3D cpu_to_le16(NVME_ONCS_WRITE_ZEROES | NVME_ONCS_TIMESTAMP | - NVME_ONCS_FEATURES | NVME_ONCS_DSM | - NVME_ONCS_COMPARE | NVME_ONCS_COPY); + id->oncs =3D cpu_to_le16(n->params.oncs); =20 id->vwc =3D (0x2 << 1) | 0x1; id->ocfs =3D cpu_to_le16(NVME_OCFS_COPY_FORMAT_0); @@ -4857,6 +4887,9 @@ static Property nvme_props[] =3D { DEFINE_PROP_BOOL("legacy-cmb", NvmeCtrl, params.legacy_cmb, false), DEFINE_PROP_SIZE32("zoned.append_size_limit", NvmeCtrl, params.zasl_bs, NVME_DEFAULT_MAX_ZA_SIZE), + DEFINE_PROP_UINT16("oncs", NvmeCtrl, params.oncs, NVME_ONCS_WRITE_ZERO= ES | + NVME_ONCS_TIMESTAMP | NVME_ONCS_DSM | + NVME_ONCS_COMPARE | NVME_ONCS_FEATURES | NVME_ONCS_= COPY), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.30.0 From nobody Sat May 18 18:58:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1612941189; cv=none; d=zohomail.com; s=zohoarc; b=P2FlVxzBpFzi8S9tY4KEa1dW6r4ktSkLFEz7OJrhOCDa6jB0CL7xMxK8cqnnBgs7QrygBPKPvwA6PxVcR/F1VkgdblguDbUT5ubGKRj80tq7bDN+soGxnasT3aGz6U95pyw/bgCNNAzV6ozybh/nCChYdFsrhUd2L2RYfn0Sf7E= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.21; envelope-from=its@irrelevant.dk; helo=wout5-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Gollu Appalanaidu , Max Reitz , Klaus Jensen , Keith Busch Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Gollu Appalanaidu Add support for marking blocks invalid with the Write Uncorrectable command. Block status is tracked in a (non-persistent) bitmap that is checked on all reads and written to on all writes. This is potentially expensive, so keep Write Uncorrectable disabled by default. Signed-off-by: Gollu Appalanaidu Signed-off-by: Klaus Jensen Reviewed-by: Minwoo Im --- docs/specs/nvme.txt | 3 ++ hw/block/nvme-ns.h | 2 ++ hw/block/nvme.h | 1 + hw/block/nvme-ns.c | 2 ++ hw/block/nvme.c | 65 +++++++++++++++++++++++++++++++++++++------ hw/block/trace-events | 1 + 6 files changed, 66 insertions(+), 8 deletions(-) diff --git a/docs/specs/nvme.txt b/docs/specs/nvme.txt index 56d393884e7a..88f9cc278d4c 100644 --- a/docs/specs/nvme.txt +++ b/docs/specs/nvme.txt @@ -19,5 +19,8 @@ Known issues =20 * The accounting numbers in the SMART/Health are reset across power cycles =20 +* Marking blocks invalid with the Write Uncorrectable is not persisted acr= oss + power cycles. + * Interrupt Coalescing is not supported and is disabled by default in vola= tion of the specification. diff --git a/hw/block/nvme-ns.h b/hw/block/nvme-ns.h index 7af6884862b5..15fa422ded03 100644 --- a/hw/block/nvme-ns.h +++ b/hw/block/nvme-ns.h @@ -72,6 +72,8 @@ typedef struct NvmeNamespace { struct { uint32_t err_rec; } features; + + unsigned long *uncorrectable; } NvmeNamespace; =20 static inline uint32_t nvme_nsid(NvmeNamespace *ns) diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 98082b2dfba3..9b8f85b9cf16 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -68,6 +68,7 @@ static inline const char *nvme_io_opc_str(uint8_t opc) case NVME_CMD_FLUSH: return "NVME_NVM_CMD_FLUSH"; case NVME_CMD_WRITE: return "NVME_NVM_CMD_WRITE"; case NVME_CMD_READ: return "NVME_NVM_CMD_READ"; + case NVME_CMD_WRITE_UNCOR: return "NVME_CMD_WRITE_UNCOR"; case NVME_CMD_COMPARE: return "NVME_NVM_CMD_COMPARE"; case NVME_CMD_WRITE_ZEROES: return "NVME_NVM_CMD_WRITE_ZEROES"; case NVME_CMD_DSM: return "NVME_NVM_CMD_DSM"; diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c index ade46e2f3739..742bbc4b4b62 100644 --- a/hw/block/nvme-ns.c +++ b/hw/block/nvme-ns.c @@ -72,6 +72,8 @@ static int nvme_ns_init(NvmeNamespace *ns, Error **errp) id_ns->mcl =3D cpu_to_le32(ns->params.mcl); id_ns->msrc =3D ns->params.msrc; =20 + ns->uncorrectable =3D bitmap_new(id_ns->nsze); + return 0; } =20 diff --git a/hw/block/nvme.c b/hw/block/nvme.c index e5f6666725d7..56048046c193 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1112,6 +1112,20 @@ static uint16_t nvme_check_dulbe(NvmeNamespace *ns, = uint64_t slba, return NVME_SUCCESS; } =20 +static inline uint16_t nvme_check_uncor(NvmeNamespace *ns, uint64_t slba, + uint32_t nlb) +{ + uint64_t elba =3D nlb + slba; + + if (ns->uncorrectable) { + if (find_next_bit(ns->uncorrectable, elba, slba) < elba) { + return NVME_UNRECOVERED_READ | NVME_DNR; + } + } + + return NVME_SUCCESS; +} + static void nvme_aio_err(NvmeRequest *req, int ret) { uint16_t status =3D NVME_SUCCESS; @@ -1423,14 +1437,24 @@ static void nvme_rw_cb(void *opaque, int ret) BlockAcctCookie *acct =3D &req->acct; BlockAcctStats *stats =3D blk_get_stats(blk); =20 + bool is_write =3D nvme_is_write(req); + trace_pci_nvme_rw_cb(nvme_cid(req), blk_name(blk)); =20 - if (ns->params.zoned && nvme_is_write(req)) { + if (ns->params.zoned && is_write) { nvme_finalize_zoned_write(ns, req); } =20 if (!ret) { block_acct_done(stats, acct); + + if (is_write) { + NvmeRwCmd *rw =3D (NvmeRwCmd *)&req->cmd; + uint64_t slba =3D le64_to_cpu(rw->slba); + uint32_t nlb =3D le16_to_cpu(rw->nlb) + 1; + + bitmap_clear(ns->uncorrectable, slba, nlb); + } } else { block_acct_failed(stats, acct); nvme_aio_err(req, ret); @@ -1521,13 +1545,13 @@ static void nvme_copy_cb(void *opaque, int ret) { NvmeRequest *req =3D opaque; NvmeNamespace *ns =3D req->ns; + NvmeCopyCmd *copy =3D (NvmeCopyCmd *)&req->cmd; + uint64_t sdlba =3D le64_to_cpu(copy->sdlba); struct nvme_copy_ctx *ctx =3D req->opaque; =20 trace_pci_nvme_copy_cb(nvme_cid(req)); =20 if (ns->params.zoned) { - NvmeCopyCmd *copy =3D (NvmeCopyCmd *)&req->cmd; - uint64_t sdlba =3D le64_to_cpu(copy->sdlba); NvmeZone *zone =3D nvme_get_zone_by_slba(ns, sdlba); =20 __nvme_advance_zone_wp(ns, zone, ctx->nlb); @@ -1535,6 +1559,7 @@ static void nvme_copy_cb(void *opaque, int ret) =20 if (!ret) { block_acct_done(blk_get_stats(ns->blkconf.blk), &req->acct); + bitmap_clear(ns->uncorrectable, sdlba, ctx->nlb); } else { block_acct_failed(blk_get_stats(ns->blkconf.blk), &req->acct); nvme_aio_err(req, ret); @@ -1953,6 +1978,12 @@ static uint16_t nvme_read(NvmeCtrl *n, NvmeRequest *= req) goto invalid; } =20 + status =3D nvme_check_uncor(ns, slba, nlb); + if (status) { + trace_pci_nvme_err_unrecoverable_read(slba, nlb); + return status; + } + if (ns->params.zoned) { status =3D nvme_check_zone_read(ns, slba, nlb); if (status) { @@ -1992,7 +2023,7 @@ invalid: } =20 static uint16_t nvme_do_write(NvmeCtrl *n, NvmeRequest *req, bool append, - bool wrz) + bool wrz, bool uncor) { NvmeRwCmd *rw =3D (NvmeRwCmd *)&req->cmd; NvmeNamespace *ns =3D req->ns; @@ -2008,7 +2039,7 @@ static uint16_t nvme_do_write(NvmeCtrl *n, NvmeReques= t *req, bool append, trace_pci_nvme_write(nvme_cid(req), nvme_io_opc_str(rw->opcode), nvme_nsid(ns), nlb, data_size, slba); =20 - if (!wrz) { + if (!wrz && !uncor) { status =3D nvme_check_mdts(n, data_size); if (status) { trace_pci_nvme_err_mdts(nvme_cid(req), data_size); @@ -2055,6 +2086,11 @@ static uint16_t nvme_do_write(NvmeCtrl *n, NvmeReque= st *req, bool append, zone->w_ptr +=3D nlb; } =20 + if (uncor) { + bitmap_set(ns->uncorrectable, slba, nlb); + return NVME_SUCCESS; + } + data_offset =3D nvme_l2b(ns, slba); =20 if (!wrz) { @@ -2087,17 +2123,22 @@ invalid: =20 static inline uint16_t nvme_write(NvmeCtrl *n, NvmeRequest *req) { - return nvme_do_write(n, req, false, false); + return nvme_do_write(n, req, false, false, false); } =20 static inline uint16_t nvme_write_zeroes(NvmeCtrl *n, NvmeRequest *req) { - return nvme_do_write(n, req, false, true); + return nvme_do_write(n, req, false, true, false); } =20 static inline uint16_t nvme_zone_append(NvmeCtrl *n, NvmeRequest *req) { - return nvme_do_write(n, req, true, false); + return nvme_do_write(n, req, true, false, false); +} + +static inline uint16_t nvme_write_uncor(NvmeCtrl *n, NvmeRequest *req) +{ + return nvme_do_write(n, req, false, false, true); } =20 static uint16_t nvme_get_mgmt_zone_slba_idx(NvmeNamespace *ns, NvmeCmd *c, @@ -2596,6 +2637,8 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest = *req) return nvme_flush(n, req); case NVME_CMD_WRITE_ZEROES: return nvme_write_zeroes(n, req); + case NVME_CMD_WRITE_UNCOR: + return nvme_write_uncor(n, req); case NVME_CMD_ZONE_APPEND: return nvme_zone_append(n, req); case NVME_CMD_WRITE: @@ -4514,6 +4557,11 @@ static void nvme_init_cse_iocs(NvmeCtrl *n) n->iocs.nvm[NVME_CMD_WRITE] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC; n->iocs.nvm[NVME_CMD_READ] =3D NVME_CMD_EFF_CSUPP; =20 + if (oncs & NVME_ONCS_WRITE_UNCORR) { + n->iocs.nvm[NVME_CMD_WRITE_UNCOR] =3D NVME_CMD_EFF_CSUPP | + NVME_CMD_EFF_LBCC; + } + if (oncs & NVME_ONCS_WRITE_ZEROES) { n->iocs.nvm[NVME_CMD_WRITE_ZEROES] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC; @@ -4853,6 +4901,7 @@ static void nvme_exit(PCIDevice *pci_dev) } =20 nvme_ns_cleanup(ns); + g_free(ns->uncorrectable); } =20 g_free(n->cq); diff --git a/hw/block/trace-events b/hw/block/trace-events index 4b5ee04024f4..f30ef220c26a 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -128,6 +128,7 @@ pci_nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is= not page aligned: 0x%"PR pci_nvme_err_invalid_opc(uint8_t opc) "invalid opcode 0x%"PRIx8"" pci_nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx= 8"" pci_nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limi= t) "Invalid LBA start=3D%"PRIu64" len=3D%"PRIu64" limit=3D%"PRIu64"" +pci_nvme_err_unrecoverable_read(uint64_t start, uint32_t nlb) "islba 0x%"P= RIx64" nlb %"PRIu32"" pci_nvme_err_invalid_log_page_offset(uint64_t ofs, uint64_t size) "must be= <=3D %"PRIu64", got %"PRIu64"" pci_nvme_err_cmb_invalid_cba(uint64_t cmbmsc) "cmbmsc 0x%"PRIx64"" pci_nvme_err_cmb_not_enabled(uint64_t cmbmsc) "cmbmsc 0x%"PRIx64"" --=20 2.30.0