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s=mta-01; t= 1612879049; x=1614693450; bh=54yn9wGwhewtmlsigr2i4DLu8msIcXhiu81 ro63Ambc=; b=LlnbuuRYZ3giMvf6J/bfxtr46OkoJnObxNYP0zwSlcToAKGlSot 8jWfmF+Q+FDgfmYLgAJCMJpq51dpXsWgzsPTvSJvX86y4tLHwuqdfTArhOqVrXje 5qy59p/d9h6BrN3VFiw0poYlhpzK66MYN70PKku16KRj84FLJ4WPtdaM= X-Virus-Scanned: amavisd-new at yadro.com From: Roman Bolshakov To: , Paolo Bonzini Subject: [PULL hvf 4/5] target/i386/hvf: add rdmsr 35H MSR_CORE_THREAD_COUNT Date: Tue, 9 Feb 2021 16:57:21 +0300 Message-ID: <20210209135722.4891-5-r.bolshakov@yadro.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210209135722.4891-1-r.bolshakov@yadro.com> References: <20210209135722.4891-1-r.bolshakov@yadro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [172.17.204.212] X-ClientProxiedBy: T-EXCH-01.corp.yadro.com (172.17.10.101) To T-EXCH-03.corp.yadro.com (172.17.100.103) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=89.207.88.252; envelope-from=r.bolshakov@yadro.com; helo=mta-01.yadro.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Cameron Esfahani , Roman Bolshakov , Richard Henderson , Eduardo Habkost , Vladislav Yaroshchuk Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @yadro.com) Content-Type: text/plain; charset="utf-8" From: Vladislav Yaroshchuk Some guests (ex. Darwin-XNU) can attemp to read this MSR to retrieve and validate CPU topology comparing it to ACPI MADT content MSR description from Intel Manual: 35H: MSR_CORE_THREAD_COUNT: Configured State of Enabled Processor Core Count and Logical Processor Count Bits 15:0 THREAD_COUNT The number of logical processors that are currently enabled in the physical package Bits 31:16 Core_COUNT The number of processor cores that are currently enabled in the physical package Bits 63:32 Reserved Signed-off-by: Vladislav Yaroshchuk Message-Id: <20210113205323.33310-1-yaroshchuk2000@gmail.com> [RB: reordered MSR definition and dropped u suffix from shift offset] Signed-off-by: Roman Bolshakov --- target/i386/cpu.h | 1 + target/i386/hvf/x86_emu.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d23a5b340a..e2fe0689cc 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -366,6 +366,7 @@ typedef enum X86Seg { =20 #define MSR_IA32_SMBASE 0x9e #define MSR_SMI_COUNT 0x34 +#define MSR_CORE_THREAD_COUNT 0x35 #define MSR_MTRRcap 0xfe #define MSR_MTRRcap_VCNT 8 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index da570e352b..e52c39ddb1 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -668,6 +668,7 @@ void simulate_rdmsr(struct CPUState *cpu) { X86CPU *x86_cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86_cpu->env; + CPUState *cs =3D env_cpu(env); uint32_t msr =3D ECX(env); uint64_t val =3D 0; =20 @@ -745,6 +746,10 @@ void simulate_rdmsr(struct CPUState *cpu) case MSR_MTRRdefType: val =3D env->mtrr_deftype; break; + case MSR_CORE_THREAD_COUNT: + val =3D cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0= */ + val |=3D ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..1= 6 */ + break; default: /* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */ val =3D 0; --=20 2.30.0