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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y11sm34752472wrh.16.2021.02.09.05.20.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Feb 2021 05:20:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L8nRGDuLm0XhHIDoUPVlYDNSmVNNdKUyvfQL0Hch34Q=; b=wmjSuyrOfIAqNgUUmHKgLa/4uUWCXOYMR31IkoBDIsUe1QDO70wSjgUEtmg14lI9Ms 4Q8OzgLyEhuveBi+7YvrrB/epF9viXf6B2YShA7CsA2h4TToZY7JBhXoTF6ZtDL3jBCx qIc6bkuVdYaBVRXOi9j2fZLt9eOVYaw7BYmHKL11if1E+lpMSY2Q8g32eyA3wsB8y/TY QxKcleKZOqP0x3TZJ7odwzlfRv4uaBt0raWmUYgPgdtzZaGefJXk1oOZf+Bb0nsIV05X q5foGaUM2bKP/8V1Ah1mvYnZl+5mOWaM2oU/pAs7KwsbKOsGCRYkRnBS9Ui2IUPCqmv5 HxPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L8nRGDuLm0XhHIDoUPVlYDNSmVNNdKUyvfQL0Hch34Q=; b=t762fTC2ky0NG9697Qy//lyy+RC0QbUcTxLxHXSfXHRAy8/+YCF/r9g3j85v1Evuzb k641IGoLw02iH1iEpn1JL0BOw3bEBnAQzyKTiiHJqn6CFuE+420Xb/HCd1alZyTje+cz MAqW18ERuPdQO+ULAPHIfRHaApK1t3fLnoDCbNkapjbY9idG9Rl/x4qBV4DTwS3/rzc4 8JtbflG/5BaJfiEagRp8/NHSBM9IMvxg0CoOzV6A0yVGz6EWbjPymRDWDBAqF9nQC1az c+XSRbSJO/HX1K5HV9BeqpaP6wzy7lwV4HiuyBXvkdaC0NT6az/WlEmQVdMuzvpOJsA3 lmdA== X-Gm-Message-State: AOAM530jpmNbnxz/z/A7SW6nOUIncMV81Q/iwGgPDxWXpzz9vOYB8Y+r pYRD1cNfZeEytpke0PQt4AfPtg== X-Google-Smtp-Source: ABdhPJxVRUwp0CH1bWVBzNE/blKsLOfMX+RS3vkk0e7MgRhb1uYhc6Ug8KrMQ8XQGKD1rctDhiHTjQ== X-Received: by 2002:a5d:690b:: with SMTP id t11mr25602602wru.12.1612876844394; Tue, 09 Feb 2021 05:20:44 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 1/4] clock: Add ClockEvent parameter to callbacks Date: Tue, 9 Feb 2021 13:20:37 +0000 Message-Id: <20210209132040.5091-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210209132040.5091-1-peter.maydell@linaro.org> References: <20210209132040.5091-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , Tyrone Ting , Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Havard Skinnemoen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The Clock framework allows users to specify a callback which is called after the clock's period has been updated. Some users need to also have a callback which is called before the clock period is updated. As the first step in adding support for notifying Clock users on pre-update events, add an argument to the ClockCallback to specify what event is being notified, and add an argument to the various functions for registering a callback to specify which events are of interest to that callback. Note that the documentation update renders correct the previously incorrect claim in 'Adding a new clock' that callbacks "will be explained in a following section". Signed-off-by: Peter Maydell Reviewed-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- v1->v2: (suggested by Luc) instead of making callback functions check whether 'event' is one they are interested in, specify mask of interesting events at callback registration time. --- docs/devel/clocks.rst | 52 +++++++++++++++++++++++++++----- include/hw/clock.h | 21 +++++++++++-- include/hw/qdev-clock.h | 17 ++++++++--- hw/adc/npcm7xx_adc.c | 2 +- hw/arm/armsse.c | 9 +++--- hw/char/cadence_uart.c | 4 +-- hw/char/ibex_uart.c | 4 +-- hw/char/pl011.c | 5 +-- hw/core/clock.c | 20 +++++++++--- hw/core/qdev-clock.c | 8 +++-- hw/mips/cps.c | 2 +- hw/misc/bcm2835_cprman.c | 23 ++++++++------ hw/misc/npcm7xx_clk.c | 26 +++++++++++++--- hw/misc/npcm7xx_pwm.c | 2 +- hw/misc/zynq_slcr.c | 5 +-- hw/timer/cmsdk-apb-dualtimer.c | 5 +-- hw/timer/cmsdk-apb-timer.c | 4 +-- hw/timer/npcm7xx_timer.c | 2 +- hw/watchdog/cmsdk-apb-watchdog.c | 5 +-- target/mips/cpu.c | 2 +- 20 files changed, 160 insertions(+), 58 deletions(-) diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst index c54bbb82409..cd344e3fe5d 100644 --- a/docs/devel/clocks.rst +++ b/docs/devel/clocks.rst @@ -80,11 +80,12 @@ Adding clocks to a device must be done during the init = method of the Device instance. =20 To add an input clock to a device, the function ``qdev_init_clock_in()`` -must be used. It takes the name, a callback and an opaque parameter -for the callback (this will be explained in a following section). +must be used. It takes the name, a callback, an opaque parameter +for the callback and a mask of events when the callback should be +called (this will be explained in a following section). Output is simpler; only the name is required. Typically:: =20 - qdev_init_clock_in(DEVICE(dev), "clk_in", clk_in_callback, dev); + qdev_init_clock_in(DEVICE(dev), "clk_in", clk_in_callback, dev, ClockU= pdate); qdev_init_clock_out(DEVICE(dev), "clk_out"); =20 Both functions return the created Clock pointer, which should be saved in = the @@ -113,7 +114,7 @@ output. * callback for the input clock (see "Callback on input clock * change" section below for more information). */ - static void clk_in_callback(void *opaque); + static void clk_in_callback(void *opaque, ClockEvent event); =20 /* * static array describing clocks: @@ -124,7 +125,7 @@ output. * the clk_out field of a MyDeviceState structure. */ static const ClockPortInitArray mydev_clocks =3D { - QDEV_CLOCK_IN(MyDeviceState, clk_in, clk_in_callback), + QDEV_CLOCK_IN(MyDeviceState, clk_in, clk_in_callback, ClockUpdate), QDEV_CLOCK_OUT(MyDeviceState, clk_out), QDEV_CLOCK_END }; @@ -153,6 +154,40 @@ nothing else to do. This value will be propagated to o= ther clocks when connecting the clocks together and devices will fetch the right value duri= ng the first reset. =20 +Clock callbacks +--------------- + +You can give a clock a callback function in several ways: + + * by passing it as an argument to ``qdev_init_clock_in()`` + * as an argument to the ``QDEV_CLOCK_IN()`` macro initializing an + array to be passed to ``qdev_init_clocks()`` + * by directly calling the ``clock_set_callback()`` function + +The callback function must be of this type: + +.. code-block:: c + + typedef void ClockCallback(void *opaque, ClockEvent event); + +The ``opaque`` argument is the pointer passed to ``qdev_init_clock_in()`` +or ``clock_set_callback()``; for ``qdev_init_clocks()`` it is the +``dev`` device pointer. + +The ``event`` argument specifies why the callback has been called. +When you register the callback you specify a mask of ClockEvent values +that you are interested in. The callback will only be called for those +events. + +The events currently supported are: + + * ``ClockUpdate`` : called after the input clock's period has changed + +Note that a clock only has one callback: it is not possible to register +different functions for different events. You must register a single +callback which listens for all of the events you are interested in, +and use the ``event`` argument to identify which event has happened. + Retrieving clocks from a device ------------------------------- =20 @@ -231,7 +266,7 @@ object during device instance init. For example: .. code-block:: c =20 clk =3D qdev_init_clock_in(DEVICE(dev), "clk-in", clk_in_callback, - dev); + dev, ClockUpdate); /* set initial value to 10ns / 100MHz */ clock_set_ns(clk, 10); =20 @@ -267,11 +302,12 @@ next lowest integer. This implies some inaccuracy due= to the rounding, so be cautious about using it in calculations. =20 It is also possible to register a callback on clock frequency changes. -Here is an example: +Here is an example, which assumes that ``clock_callback`` has been +specified as the callback for the ``ClockUpdate`` event: =20 .. code-block:: c =20 - void clock_callback(void *opaque) { + void clock_callback(void *opaque, ClockEvent event) { MyDeviceState *s =3D (MyDeviceState *) opaque; /* * 'opaque' is the argument passed to qdev_init_clock_in(); diff --git a/include/hw/clock.h b/include/hw/clock.h index e5f45e2626d..5c73b4e7ae9 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -22,7 +22,17 @@ #define TYPE_CLOCK "clock" OBJECT_DECLARE_SIMPLE_TYPE(Clock, CLOCK) =20 -typedef void ClockCallback(void *opaque); +/* + * Argument to ClockCallback functions indicating why the callback + * has been called. A mask of these values logically ORed together + * is used to specify which events are interesting when the callback + * is registered, so these values must all be different bit values. + */ +typedef enum ClockEvent { + ClockUpdate =3D 1, /* Clock period has just updated */ +} ClockEvent; + +typedef void ClockCallback(void *opaque, ClockEvent event); =20 /* * clock store a value representing the clock's period in 2^-32ns unit. @@ -50,6 +60,7 @@ typedef void ClockCallback(void *opaque); * @canonical_path: clock path string cache (used for trace purpose) * @callback: called when clock changes * @callback_opaque: argument for @callback + * @callback_events: mask of events when callback should be called * @source: source (or parent in clock tree) of the clock * @children: list of clocks connected to this one (it is their source) * @sibling: structure used to form a clock list @@ -67,6 +78,7 @@ struct Clock { char *canonical_path; ClockCallback *callback; void *callback_opaque; + int callback_events; =20 /* Clocks are organized in a clock tree */ Clock *source; @@ -114,10 +126,15 @@ Clock *clock_new(Object *parent, const char *name); * @clk: the clock to register the callback into * @cb: the callback function * @opaque: the argument to the callback + * @events: the events the callback should be called for + * (logical OR of ClockEvent enum values) * * Register a callback called on every clock update. + * Note that a clock has only one callback: you cannot register + * different callback functions for different events. */ -void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque); +void clock_set_callback(Clock *clk, ClockCallback *cb, + void *opaque, int events); =20 /** * clock_clear_callback: diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h index 64ca4d266f2..348ec363525 100644 --- a/include/hw/qdev-clock.h +++ b/include/hw/qdev-clock.h @@ -22,6 +22,8 @@ * @name: the name of the clock (can't be NULL). * @callback: optional callback to be called on update or NULL. * @opaque: argument for the callback + * @events: the events the callback should be called for + * (logical OR of ClockEvent enum values) * @returns: a pointer to the newly added clock * * Add an input clock to device @dev as a clock named @name. @@ -29,7 +31,8 @@ * The callback will be called with @opaque as opaque parameter. */ Clock *qdev_init_clock_in(DeviceState *dev, const char *name, - ClockCallback *callback, void *opaque); + ClockCallback *callback, void *opaque, + int events); =20 /** * qdev_init_clock_out: @@ -105,6 +108,7 @@ void qdev_finalize_clocklist(DeviceState *dev); * @output: indicates whether the clock is input or output * @callback: for inputs, optional callback to be called on clock's update * with device as opaque + * @callback_events: mask of ClockEvent values for when callback is called * @offset: optional offset to store the ClockIn or ClockOut pointer in de= vice * state structure (0 means unused) */ @@ -112,6 +116,7 @@ struct ClockPortInitElem { const char *name; bool is_output; ClockCallback *callback; + int callback_events; size_t offset; }; =20 @@ -119,10 +124,11 @@ struct ClockPortInitElem { (offsetof(devstate, field) + \ type_check(Clock *, typeof_field(devstate, field))) =20 -#define QDEV_CLOCK(out_not_in, devstate, field, cb) { \ +#define QDEV_CLOCK(out_not_in, devstate, field, cb, cbevents) { \ .name =3D (stringify(field)), \ .is_output =3D out_not_in, \ .callback =3D cb, \ + .callback_events =3D cbevents, \ .offset =3D clock_offset_value(devstate, field), \ } =20 @@ -133,14 +139,15 @@ struct ClockPortInitElem { * @field: a field in @_devstate (must be Clock*) * @callback: (for input only) callback (or NULL) to be called with the de= vice * state as argument + * @cbevents: (for input only) ClockEvent mask for when callback is called * * The name of the clock will be derived from @field */ -#define QDEV_CLOCK_IN(devstate, field, callback) \ - QDEV_CLOCK(false, devstate, field, callback) +#define QDEV_CLOCK_IN(devstate, field, callback, cbevents) \ + QDEV_CLOCK(false, devstate, field, callback, cbevents) =20 #define QDEV_CLOCK_OUT(devstate, field) \ - QDEV_CLOCK(true, devstate, field, NULL) + QDEV_CLOCK(true, devstate, field, NULL, 0) =20 #define QDEV_CLOCK_END { .name =3D NULL } =20 diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c index 870a6d50c27..573f4876dc6 100644 --- a/hw/adc/npcm7xx_adc.c +++ b/hw/adc/npcm7xx_adc.c @@ -238,7 +238,7 @@ static void npcm7xx_adc_init(Object *obj) memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s, TYPE_NPCM7XX_ADC, 4 * KiB); sysbus_init_mmio(sbd, &s->iomem); - s->clock =3D qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL); + s->clock =3D qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL, ClockU= pdate); =20 for (i =3D 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) { object_property_add_uint32_ptr(obj, "adci[*]", diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 26e1a8c95b6..fa155b72022 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -230,9 +230,10 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s) qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); } =20 -static void armsse_mainclk_update(void *opaque) +static void armsse_mainclk_update(void *opaque, ClockEvent event) { ARMSSE *s =3D ARM_SSE(opaque); + /* * Set system_clock_scale from our Clock input; this is what * controls the tick rate of the CPU SysTick timer. @@ -251,8 +252,8 @@ static void armsse_init(Object *obj) assert(info->num_cpus <=3D SSE_MAX_CPUS); =20 s->mainclk =3D qdev_init_clock_in(DEVICE(s), "MAINCLK", - armsse_mainclk_update, s); - s->s32kclk =3D qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL); + armsse_mainclk_update, s, ClockUpdate); + s->s32kclk =3D qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL, 0); =20 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); =20 @@ -1120,7 +1121,7 @@ static void armsse_realize(DeviceState *dev, Error **= errp) sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); =20 /* Set initial system_clock_scale from MAINCLK */ - armsse_mainclk_update(s); + armsse_mainclk_update(s, ClockUpdate); } =20 static void armsse_idau_check(IDAUInterface *ii, uint32_t address, diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index c603e14012a..ceb677bc5a8 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -519,7 +519,7 @@ static void cadence_uart_realize(DeviceState *dev, Erro= r **errp) uart_event, NULL, s, NULL, true); } =20 -static void cadence_uart_refclk_update(void *opaque) +static void cadence_uart_refclk_update(void *opaque, ClockEvent event) { CadenceUARTState *s =3D opaque; =20 @@ -537,7 +537,7 @@ static void cadence_uart_init(Object *obj) sysbus_init_irq(sbd, &s->irq); =20 s->refclk =3D qdev_init_clock_in(DEVICE(obj), "refclk", - cadence_uart_refclk_update, s); + cadence_uart_refclk_update, s, ClockUpd= ate); /* initialize the frequency in case the clock remains unconnected */ clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK); =20 diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c index 89f1182c9bf..edcaa30aded 100644 --- a/hw/char/ibex_uart.c +++ b/hw/char/ibex_uart.c @@ -396,7 +396,7 @@ static void ibex_uart_write(void *opaque, hwaddr addr, } } =20 -static void ibex_uart_clk_update(void *opaque) +static void ibex_uart_clk_update(void *opaque, ClockEvent event) { IbexUartState *s =3D opaque; =20 @@ -466,7 +466,7 @@ static void ibex_uart_init(Object *obj) IbexUartState *s =3D IBEX_UART(obj); =20 s->f_clk =3D qdev_init_clock_in(DEVICE(obj), "f_clock", - ibex_uart_clk_update, s); + ibex_uart_clk_update, s, ClockUpdate); clock_set_hz(s->f_clk, IBEX_UART_CLOCK); =20 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_watermark); diff --git a/hw/char/pl011.c b/hw/char/pl011.c index ea4a4e52356..c5621a195ff 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -309,7 +309,7 @@ static void pl011_event(void *opaque, QEMUChrEvent even= t) pl011_put_fifo(opaque, 0x400); } =20 -static void pl011_clock_update(void *opaque) +static void pl011_clock_update(void *opaque, ClockEvent event) { PL011State *s =3D PL011(opaque); =20 @@ -378,7 +378,8 @@ static void pl011_init(Object *obj) sysbus_init_irq(sbd, &s->irq[i]); } =20 - s->clk =3D qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, = s); + s->clk =3D qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, = s, + ClockUpdate); =20 s->read_trigger =3D 1; s->ifl =3D 0x12; diff --git a/hw/core/clock.c b/hw/core/clock.c index 76b5f468b6e..71dc1f4de65 100644 --- a/hw/core/clock.c +++ b/hw/core/clock.c @@ -39,15 +39,16 @@ Clock *clock_new(Object *parent, const char *name) return clk; } =20 -void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque) +void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque, int e= vents) { clk->callback =3D cb; clk->callback_opaque =3D opaque; + clk->callback_events =3D events; } =20 void clock_clear_callback(Clock *clk) { - clock_set_callback(clk, NULL, NULL); + clock_set_callback(clk, NULL, NULL, 0); } =20 bool clock_set(Clock *clk, uint64_t period) @@ -62,6 +63,17 @@ bool clock_set(Clock *clk, uint64_t period) return true; } =20 +static void clock_call_callback(Clock *clk, ClockEvent event) +{ + /* + * Call the Clock's callback for this event, if it has one and + * is interested in this event. + */ + if (clk->callback && (clk->callback_events & event)) { + clk->callback(clk->callback_opaque, event); + } +} + static void clock_propagate_period(Clock *clk, bool call_callbacks) { Clock *child; @@ -72,8 +84,8 @@ static void clock_propagate_period(Clock *clk, bool call_= callbacks) trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk), CLOCK_PERIOD_TO_HZ(clk->period), call_callbacks); - if (call_callbacks && child->callback) { - child->callback(child->callback_opaque); + if (call_callbacks) { + clock_call_callback(child, ClockUpdate); } clock_propagate_period(child, call_callbacks); } diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c index eb05f2a13ca..9c55ddc23ee 100644 --- a/hw/core/qdev-clock.c +++ b/hw/core/qdev-clock.c @@ -111,7 +111,8 @@ Clock *qdev_init_clock_out(DeviceState *dev, const char= *name) } =20 Clock *qdev_init_clock_in(DeviceState *dev, const char *name, - ClockCallback *callback, void *opaque) + ClockCallback *callback, void *opaque, + int events) { NamedClockList *ncl; =20 @@ -120,7 +121,7 @@ Clock *qdev_init_clock_in(DeviceState *dev, const char = *name, ncl =3D qdev_init_clocklist(dev, name, false, NULL); =20 if (callback) { - clock_set_callback(ncl->clock, callback, opaque); + clock_set_callback(ncl->clock, callback, opaque, events); } return ncl->clock; } @@ -137,7 +138,8 @@ void qdev_init_clocks(DeviceState *dev, const ClockPort= InitArray clocks) if (elem->is_output) { *clkp =3D qdev_init_clock_out(dev, elem->name); } else { - *clkp =3D qdev_init_clock_in(dev, elem->name, elem->callback, = dev); + *clkp =3D qdev_init_clock_in(dev, elem->name, elem->callback, = dev, + elem->callback_events); } } } diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 7a0d289efaf..2b436700ce6 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -39,7 +39,7 @@ static void mips_cps_init(Object *obj) SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); MIPSCPSState *s =3D MIPS_CPS(obj); =20 - s->clock =3D qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, NULL); + s->clock =3D qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, NULL, 0); /* * Cover entire address space as there do not seem to be any * constraints for the base address of CPC and GIC. diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index 7e415a017c9..75e6c574d46 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -107,7 +107,7 @@ static void pll_update(CprmanPllState *pll) clock_update_hz(pll->out, freq); } =20 -static void pll_xosc_update(void *opaque) +static void pll_xosc_update(void *opaque, ClockEvent event) { pll_update(CPRMAN_PLL(opaque)); } @@ -116,7 +116,8 @@ static void pll_init(Object *obj) { CprmanPllState *s =3D CPRMAN_PLL(obj); =20 - s->xosc_in =3D qdev_init_clock_in(DEVICE(s), "xosc-in", pll_xosc_updat= e, s); + s->xosc_in =3D qdev_init_clock_in(DEVICE(s), "xosc-in", pll_xosc_updat= e, + s, ClockUpdate); s->out =3D qdev_init_clock_out(DEVICE(s), "out"); } =20 @@ -209,7 +210,7 @@ static void pll_update_all_channels(BCM2835CprmanState = *s, } } =20 -static void pll_channel_pll_in_update(void *opaque) +static void pll_channel_pll_in_update(void *opaque, ClockEvent event) { pll_channel_update(CPRMAN_PLL_CHANNEL(opaque)); } @@ -219,7 +220,8 @@ static void pll_channel_init(Object *obj) CprmanPllChannelState *s =3D CPRMAN_PLL_CHANNEL(obj); =20 s->pll_in =3D qdev_init_clock_in(DEVICE(s), "pll-in", - pll_channel_pll_in_update, s); + pll_channel_pll_in_update, s, + ClockUpdate); s->out =3D qdev_init_clock_out(DEVICE(s), "out"); } =20 @@ -303,7 +305,7 @@ static void clock_mux_update(CprmanClockMuxState *mux) clock_update_hz(mux->out, freq); } =20 -static void clock_mux_src_update(void *opaque) +static void clock_mux_src_update(void *opaque, ClockEvent event) { CprmanClockMuxState **backref =3D opaque; CprmanClockMuxState *s =3D *backref; @@ -335,7 +337,8 @@ static void clock_mux_init(Object *obj) s->backref[i] =3D s; s->srcs[i] =3D qdev_init_clock_in(DEVICE(s), name, clock_mux_src_update, - &s->backref[i]); + &s->backref[i], + ClockUpdate); g_free(name); } =20 @@ -380,7 +383,7 @@ static void dsi0hsck_mux_update(CprmanDsi0HsckMuxState = *s) clock_update(s->out, clock_get(src)); } =20 -static void dsi0hsck_mux_in_update(void *opaque) +static void dsi0hsck_mux_in_update(void *opaque, ClockEvent event) { dsi0hsck_mux_update(CPRMAN_DSI0HSCK_MUX(opaque)); } @@ -390,8 +393,10 @@ static void dsi0hsck_mux_init(Object *obj) CprmanDsi0HsckMuxState *s =3D CPRMAN_DSI0HSCK_MUX(obj); DeviceState *dev =3D DEVICE(obj); =20 - s->plla_in =3D qdev_init_clock_in(dev, "plla-in", dsi0hsck_mux_in_upda= te, s); - s->plld_in =3D qdev_init_clock_in(dev, "plld-in", dsi0hsck_mux_in_upda= te, s); + s->plla_in =3D qdev_init_clock_in(dev, "plla-in", dsi0hsck_mux_in_upda= te, + s, ClockUpdate); + s->plld_in =3D qdev_init_clock_in(dev, "plld-in", dsi0hsck_mux_in_upda= te, + s, ClockUpdate); s->out =3D qdev_init_clock_out(DEVICE(s), "out"); } =20 diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c index 0bcae9ce957..a1ee67dc9a1 100644 --- a/hw/misc/npcm7xx_clk.c +++ b/hw/misc/npcm7xx_clk.c @@ -586,15 +586,26 @@ static const DividerInitInfo divider_init_info_list[]= =3D { }, }; =20 +static void npcm7xx_clk_update_pll_cb(void *opaque, ClockEvent event) +{ + npcm7xx_clk_update_pll(opaque); +} + static void npcm7xx_clk_pll_init(Object *obj) { NPCM7xxClockPLLState *pll =3D NPCM7XX_CLOCK_PLL(obj); =20 pll->clock_in =3D qdev_init_clock_in(DEVICE(pll), "clock-in", - npcm7xx_clk_update_pll, pll); + npcm7xx_clk_update_pll_cb, pll, + ClockUpdate); pll->clock_out =3D qdev_init_clock_out(DEVICE(pll), "clock-out"); } =20 +static void npcm7xx_clk_update_sel_cb(void *opaque, ClockEvent event) +{ + npcm7xx_clk_update_sel(opaque); +} + static void npcm7xx_clk_sel_init(Object *obj) { int i; @@ -603,16 +614,23 @@ static void npcm7xx_clk_sel_init(Object *obj) for (i =3D 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) { sel->clock_in[i] =3D qdev_init_clock_in(DEVICE(sel), g_strdup_printf("clock-in[%d]", i), - npcm7xx_clk_update_sel, sel); + npcm7xx_clk_update_sel_cb, sel, ClockUpdate); } sel->clock_out =3D qdev_init_clock_out(DEVICE(sel), "clock-out"); } + +static void npcm7xx_clk_update_divider_cb(void *opaque, ClockEvent event) +{ + npcm7xx_clk_update_divider(opaque); +} + static void npcm7xx_clk_divider_init(Object *obj) { NPCM7xxClockDividerState *div =3D NPCM7XX_CLOCK_DIVIDER(obj); =20 div->clock_in =3D qdev_init_clock_in(DEVICE(div), "clock-in", - npcm7xx_clk_update_divider, div); + npcm7xx_clk_update_divider_cb, + div, ClockUpdate); div->clock_out =3D qdev_init_clock_out(DEVICE(div), "clock-out"); } =20 @@ -875,7 +893,7 @@ static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLK= State *s) { int i; =20 - s->clkref =3D qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL); + s->clkref =3D qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL, 0); =20 /* First pass: init all converter modules */ QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) !=3D NPCM7XX_CLOCK_NR= _PLLS); diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c index dabcb6c0f95..ce192bb2741 100644 --- a/hw/misc/npcm7xx_pwm.c +++ b/hw/misc/npcm7xx_pwm.c @@ -493,7 +493,7 @@ static void npcm7xx_pwm_init(Object *obj) memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s, TYPE_NPCM7XX_PWM, 4 * KiB); sysbus_init_mmio(sbd, &s->iomem); - s->clock =3D qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL); + s->clock =3D qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL, 0); =20 for (i =3D 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { object_property_add_uint32_ptr(obj, "freq[*]", diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 66504a9d3ab..c66d7db177d 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -307,9 +307,10 @@ static void zynq_slcr_propagate_clocks(ZynqSLCRState *= s) clock_propagate(s->uart1_ref_clk); } =20 -static void zynq_slcr_ps_clk_callback(void *opaque) +static void zynq_slcr_ps_clk_callback(void *opaque, ClockEvent event) { ZynqSLCRState *s =3D (ZynqSLCRState *) opaque; + zynq_slcr_compute_clocks(s); zynq_slcr_propagate_clocks(s); } @@ -576,7 +577,7 @@ static const MemoryRegionOps slcr_ops =3D { }; =20 static const ClockPortInitArray zynq_slcr_clocks =3D { - QDEV_CLOCK_IN(ZynqSLCRState, ps_clk, zynq_slcr_ps_clk_callback), + QDEV_CLOCK_IN(ZynqSLCRState, ps_clk, zynq_slcr_ps_clk_callback, ClockU= pdate), QDEV_CLOCK_OUT(ZynqSLCRState, uart0_ref_clk), QDEV_CLOCK_OUT(ZynqSLCRState, uart1_ref_clk), QDEV_CLOCK_END diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c index ef49f5852d3..d4a509c798e 100644 --- a/hw/timer/cmsdk-apb-dualtimer.c +++ b/hw/timer/cmsdk-apb-dualtimer.c @@ -449,7 +449,7 @@ static void cmsdk_apb_dualtimer_reset(DeviceState *dev) s->timeritop =3D 0; } =20 -static void cmsdk_apb_dualtimer_clk_update(void *opaque) +static void cmsdk_apb_dualtimer_clk_update(void *opaque, ClockEvent event) { CMSDKAPBDualTimer *s =3D CMSDK_APB_DUALTIMER(opaque); int i; @@ -478,7 +478,8 @@ static void cmsdk_apb_dualtimer_init(Object *obj) sysbus_init_irq(sbd, &s->timermod[i].timerint); } s->timclk =3D qdev_init_clock_in(DEVICE(s), "TIMCLK", - cmsdk_apb_dualtimer_clk_update, s); + cmsdk_apb_dualtimer_clk_update, s, + ClockUpdate); } =20 static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index ee51ce3369c..68aa1a76360 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -204,7 +204,7 @@ static void cmsdk_apb_timer_reset(DeviceState *dev) ptimer_transaction_commit(s->timer); } =20 -static void cmsdk_apb_timer_clk_update(void *opaque) +static void cmsdk_apb_timer_clk_update(void *opaque, ClockEvent event) { CMSDKAPBTimer *s =3D CMSDK_APB_TIMER(opaque); =20 @@ -223,7 +223,7 @@ static void cmsdk_apb_timer_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->timerint); s->pclk =3D qdev_init_clock_in(DEVICE(s), "pclk", - cmsdk_apb_timer_clk_update, s); + cmsdk_apb_timer_clk_update, s, ClockUpdat= e); } =20 static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c index 36e2c07db26..4efdf135b82 100644 --- a/hw/timer/npcm7xx_timer.c +++ b/hw/timer/npcm7xx_timer.c @@ -627,7 +627,7 @@ static void npcm7xx_timer_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); qdev_init_gpio_out_named(dev, &w->reset_signal, NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1); - s->clock =3D qdev_init_clock_in(dev, "clock", NULL, NULL); + s->clock =3D qdev_init_clock_in(dev, "clock", NULL, NULL, 0); } =20 static const VMStateDescription vmstate_npcm7xx_base_timer =3D { diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watch= dog.c index 302f1711738..5a2cd46eb76 100644 --- a/hw/watchdog/cmsdk-apb-watchdog.c +++ b/hw/watchdog/cmsdk-apb-watchdog.c @@ -310,7 +310,7 @@ static void cmsdk_apb_watchdog_reset(DeviceState *dev) ptimer_transaction_commit(s->timer); } =20 -static void cmsdk_apb_watchdog_clk_update(void *opaque) +static void cmsdk_apb_watchdog_clk_update(void *opaque, ClockEvent event) { CMSDKAPBWatchdog *s =3D CMSDK_APB_WATCHDOG(opaque); =20 @@ -329,7 +329,8 @@ static void cmsdk_apb_watchdog_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->wdogint); s->wdogclk =3D qdev_init_clock_in(DEVICE(s), "WDOGCLK", - cmsdk_apb_watchdog_clk_update, s); + cmsdk_apb_watchdog_clk_update, s, + ClockUpdate); =20 s->is_luminary =3D false; s->id =3D cmsdk_apb_watchdog_id; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index ad163ead625..2f3d9d2ce2c 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -636,7 +636,7 @@ static void mips_cpu_initfn(Object *obj) MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(obj); =20 cpu_set_cpustate_pointers(cpu); - cpu->clock =3D qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu); + cpu->clock =3D qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0); env->cpu_model =3D mcc->cpu_def; } =20 --=20 2.20.1 From nobody Wed May 22 03:28:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y11sm34752472wrh.16.2021.02.09.05.20.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Feb 2021 05:20:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v42h+/gUC/c3GqgbqA5jD8JSk9/EEyzsdB3W6E1Nn8k=; b=N8uu5k/v3/P+C0n1YKAMNItFrfsWkQHVBcmxzp0jIMagS+1Ldk2l5vQrjXZ5juGb5s juhn+lJOY0mOZBT2+Mytw1WwDwSEIXD+vYnpnshe6ZogN12lUegyWXmmg5vwN3zOChuy SGzcJGgcoa/ZUMmk5Nr9duXR2/CDGH7d2E/3eRxosIMCOrgxLHS3DR0O6o+U0E1aZ+iY pWIcaXay9gxukfzB5v9EatN7+H4rlfpd6efjfRk+FmLyJBekOWlXMN2G7i0qnlorrfmj XPmSWQKHVLPuNO7o4bidNx10hbYsp9de/v7aZ6V7HVkyFIwEa1ngyJACv94tmsPQC9Jo 0oLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v42h+/gUC/c3GqgbqA5jD8JSk9/EEyzsdB3W6E1Nn8k=; b=Y2oQs+sSK3bogw4m68lQeEBqnX+620ReKrpJbNpN6BvEP58lKry5FLmOV24flZdYqS DOtpOAllgTTXEvaEFNrwFHBkynhvoh3ab+W4H4Aq/iEXjIOONpKkuq2zOOwhisLtyx2q sNkLlKVdtQDU0UDULfJydpsAOqzmUlbSGjYg8y9snGiX59pTwkakSdDSJl6SNh9wSSRa c5sqWf0tGx54K4NxJh9033DNWmn68ZXHCQtyMxf1HWc44R+fRt/20W7B91YSSNmQEdMR K4sqbUO/W7IHKcQR9csH4tnDZYi48YE0mX+eNJtjLu9Ure0lzCiAiqyC47PFKb5vLOtf wWNw== X-Gm-Message-State: AOAM530ykRP5AfytBFax4O5rLEOcsm0kfV2AuAxdPsnVrr+kXIOJpv1u UUhsnoQprSbkJBqazh4Ihr5npQ== X-Google-Smtp-Source: ABdhPJziVZ8+yOo9xPVU+H6KWkkMrsMchc3BZBTELLW3fVP4G6hYAARs7a8GEXuDgb5hgFQnrYWFcQ== X-Received: by 2002:a1c:c6:: with SMTP id 189mr3498907wma.128.1612876845507; Tue, 09 Feb 2021 05:20:45 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 2/4] clock: Add ClockPreUpdate callback event type Date: Tue, 9 Feb 2021 13:20:38 +0000 Message-Id: <20210209132040.5091-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210209132040.5091-1-peter.maydell@linaro.org> References: <20210209132040.5091-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , Tyrone Ting , Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Havard Skinnemoen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add a new callback event type ClockPreUpdate, which is called on period changes before the period is updated. Signed-off-by: Peter Maydell Reviewed-by: Hao Wu Reviewed-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- docs/devel/clocks.rst | 9 ++++++++- include/hw/clock.h | 1 + hw/core/clock.c | 3 +++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst index cd344e3fe5d..f0391e76b4f 100644 --- a/docs/devel/clocks.rst +++ b/docs/devel/clocks.rst @@ -181,7 +181,14 @@ events. =20 The events currently supported are: =20 - * ``ClockUpdate`` : called after the input clock's period has changed + * ``ClockPreUpdate`` : called when the input clock's period is about to + update. This is useful if the device needs to do some action for + which it needs to know the old value of the clock period. During + this callback, Clock API functions like ``clock_get()`` or + ``clock_ticks_to_ns()`` will use the old period. + * ``ClockUpdate`` : called after the input clock's period has changed. + During this callback, Clock API functions like ``clock_ticks_to_ns()`` + will use the new period. =20 Note that a clock only has one callback: it is not possible to register different functions for different events. You must register a single diff --git a/include/hw/clock.h b/include/hw/clock.h index 5c73b4e7ae9..d7a6673c29e 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -30,6 +30,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(Clock, CLOCK) */ typedef enum ClockEvent { ClockUpdate =3D 1, /* Clock period has just updated */ + ClockPreUpdate =3D 2, /* Clock period is about to update */ } ClockEvent; =20 typedef void ClockCallback(void *opaque, ClockEvent event); diff --git a/hw/core/clock.c b/hw/core/clock.c index 71dc1f4de65..2c86091d8a3 100644 --- a/hw/core/clock.c +++ b/hw/core/clock.c @@ -80,6 +80,9 @@ static void clock_propagate_period(Clock *clk, bool call_= callbacks) =20 QLIST_FOREACH(child, &clk->children, sibling) { if (child->period !=3D clk->period) { + if (call_callbacks) { + clock_call_callback(child, ClockPreUpdate); + } child->period =3D clk->period; trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk), CLOCK_PERIOD_TO_HZ(clk->period), --=20 2.20.1 From nobody Wed May 22 03:28:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612877040; cv=none; d=zohomail.com; s=zohoarc; b=XlzkYmlBofLqeUtW2A197/F7Hj68UoU9J5VZ6vVnmZPKt7sFLYELMe4GEaYfeOKKUOKqUZlPvSX8wWFB2Opdq1F+CXuDOhScp9/a182dDv+z9JVODZiOk0pr/i4gugBe6nuiHIko6ZA0oCgHkr7YQ4tjFUF9GBK0Fao14ncxXHo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612877040; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Rxyrp77KmAHOUvHPnjORQdoPirQElENHA7YXjs2ljS4=; b=EeCaWOkxlFz2caZz/Ocq31zYmBNDxc6sFD1TReKmgb/mfwSolqPcCQaiohoW9KYSvA8c2idAGWh0PJLej/vMJ6QRQBncZjKgIiJDLzJCg9glzAolbw9/OKIgJs5U03yqcIuGpsC9y9DzyjXi9cEEGFfTeWY0AWOK/RzzrcFh/XM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612877040007202.07379658766922; Tue, 9 Feb 2021 05:24:00 -0800 (PST) Received: from localhost ([::1]:53566 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l9Szm-0005NS-UT for importer@patchew.org; Tue, 09 Feb 2021 08:23:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33926) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l9Swt-0002ua-Qi for qemu-devel@nongnu.org; Tue, 09 Feb 2021 08:20:59 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:34911) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l9Swj-0000kw-Cc for qemu-devel@nongnu.org; Tue, 09 Feb 2021 08:20:59 -0500 Received: by mail-wr1-x42e.google.com with SMTP id l12so21740745wry.2 for ; Tue, 09 Feb 2021 05:20:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y11sm34752472wrh.16.2021.02.09.05.20.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Feb 2021 05:20:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Rxyrp77KmAHOUvHPnjORQdoPirQElENHA7YXjs2ljS4=; b=ITaT59/2Agi28mJA6dajnkYezkweLT7DZBvipjA0e7HR2jgTChVcL1ruovowKjK9FM ir3iyPy0Ipwg0/KDLnE+2vH0lcqGPhMxzA7mISAMMwTn++03zahxcGcA6RzGrEVMOuUs FhkcnZSgMm/YFjYiCJI9HS42SWaF0nPpLvcojt3qstmCp1y6n7HKrqAg63KCycWy9Jnj anOO09XWlKhGK/eMPvl8eOGe0EptGjtmw6/5LNLv4IqBXWCUrySmjPmF5BDqNC+wbjU4 kodHZr0pcr0ZVmqQyAn3n5D0bDgzf+5Mv6R/ppElDsOr7uu4P8ulPfc9hX/1O4qkTRzI CssA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Rxyrp77KmAHOUvHPnjORQdoPirQElENHA7YXjs2ljS4=; b=lPIBzFUmtMVL1E+uys6mcka2gMK0FnQOgcVkfZbaREX1dBOJ7fjO/iqXGaE5JA4zLr QSzBE5ky23PFWD331gnG/W79aA/3PvCwWpoQL9Exkh3K9Rd+vjb5AX4Ch4ovEX3SVB2V byXAuLUa3jf5SrPfy3wfYKxctMihoJdi3TVYqlvjvrvyfKOeO6wYeKFLPp7CTEYqKChP oBg21LVc9+3arwhZT9VW5CwIUu3hA9CropERqu3G9/rcYnRjUyoEC48e+VegOkB9WRoe rdg+mVPkvgIymHt/nsL9/oftl7XJiw3uGfzqpryoFMw/vhEDkBoHtISw9jk6jEmGxVgJ rJAA== X-Gm-Message-State: AOAM532QKB5hGfevUtSRZ81Rz6q2lrmfzof1BlM5pGKzX7DMkV2asjEw 5Q6EHMRhmoDVR1vR6nttucMrDw== X-Google-Smtp-Source: ABdhPJwhGkd0lBbm4VivMenu3spztRUp+gQXLWrq2nj4qXaqYEasSOBanG7UfAGHjbkQ9BUqfxup+g== X-Received: by 2002:adf:f647:: with SMTP id x7mr24739995wrp.160.1612876846608; Tue, 09 Feb 2021 05:20:46 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 3/4] clock: Add clock_ns_to_ticks() function Date: Tue, 9 Feb 2021 13:20:39 +0000 Message-Id: <20210209132040.5091-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210209132040.5091-1-peter.maydell@linaro.org> References: <20210209132040.5091-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , Tyrone Ting , Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Havard Skinnemoen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add a clock_ns_to_ticks() function which does the opposite of clock_ticks_to_ns(): given a duration in nanoseconds, it returns the number of clock ticks that would happen in that time. This is useful for devices that have a free running counter register whose value can be calculated when it is read. Signed-off-by: Peter Maydell Reviewed-by: Hao Wu Reviewed-by: Luc Michel Tested-by: Philippe Mathieu-Daud=C3=A9 --- I have made the overflow behaviour here be "wrap", with justification as per the comment; but I'm not 100% set on this. --- docs/devel/clocks.rst | 12 ++++++++++++ include/hw/clock.h | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst index f0391e76b4f..956bd147ea0 100644 --- a/docs/devel/clocks.rst +++ b/docs/devel/clocks.rst @@ -360,6 +360,18 @@ rather than simply passing it to a QEMUTimer function = like ``timer_mod_ns()`` then you should be careful to avoid overflow in those calculations, of course.) =20 +Obtaining tick counts +--------------------- + +For calculations where you need to know the number of ticks in +a given duration, use ``clock_ns_to_ticks()``. This function handles +possible non-whole-number-of-nanoseconds periods and avoids +potential rounding errors. It will return '0' if the clock is stopped +(i.e. it has period zero). If the inputs imply a tick count that +overflows a 64-bit value (a very long duration for a clock with a +very short period) the output value is truncated, so effectively +the 64-bit output wraps around. + Changing a clock period ----------------------- =20 diff --git a/include/hw/clock.h b/include/hw/clock.h index d7a6673c29e..79c3b7ebe40 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -286,6 +286,47 @@ static inline uint64_t clock_ticks_to_ns(const Clock *= clk, uint64_t ticks) return ns_low >> 32 | ns_high << 32; } =20 +/** + * clock_ns_to_ticks: + * @clk: the clock to query + * @ns: duration in nanoseconds + * + * Returns the number of ticks this clock would make in the given + * number of nanoseconds. Because a clock can have a period which + * is not a whole number of nanoseconds, it is important to use this + * function rather than attempting to obtain a "period in nanoseconds" + * value and then dividing the duration by that value. + * + * If the clock is stopped (ie it has period zero), returns 0. + * + * For some inputs the result could overflow a 64-bit value (because + * the clock's period is short and the duration is long). In these + * cases we truncate the result to a 64-bit value. This is on the + * assumption that generally the result is going to be used to report + * a 32-bit or 64-bit guest register value, so wrapping either cannot + * happen or is the desired behaviour. + */ +static inline uint64_t clock_ns_to_ticks(const Clock *clk, uint64_t ns) +{ + /* + * ticks =3D duration_in_ns / period_in_ns + * =3D ns / (period / 2^32) + * =3D (ns * 2^32) / period + * The hi, lo inputs to divu128() are (ns << 32) as a 128 bit value. + */ + uint64_t lo =3D ns << 32; + uint64_t hi =3D ns >> 32; + if (clk->period =3D=3D 0) { + return 0; + } + /* + * Ignore divu128() return value as we've caught div-by-zero and don't + * need different behaviour for overflow. + */ + divu128(&lo, &hi, clk->period); + return lo; +} + /** * clock_is_enabled: * @clk: a clock --=20 2.20.1 From nobody Wed May 22 03:28:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612877001; cv=none; d=zohomail.com; s=zohoarc; b=bQByAVob3lwk+eQs6yyz7v2jWIsm5m2w/g2oFcr65rEw/yM3BJ4dCxnI+mUGarLtKEMbCGlWsCi9SQ/2L7Q9JMspiiiFHAtaegz4U+ELm9B0SWOmzvHvaB22vs2gwyBLnFHCHsnRib42Jndc40oaNP3bjYPmMaPVcStcGG7tB34= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612877001; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RQnHSU5URki5Eoi1GvfEMafAg4qrSv6IwWbelkI4His=; b=RY2cM2YyXmyzsleMSUZ3/BZ9z7jZxaVH/nlX2xEUSpvmCuIfc/srfL7gR6aV6BW0yQLKyJw+yAKAz0WMPPEfhUYU5rrsSi/H149whkkVvN0lSKX5wvTgGSgW6yb1YIxqWs7jlmSVAlz4kbUFHSyUvjFEOuKpPLa9FfvPwlQT4Fc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612877001063379.7676642187081; Tue, 9 Feb 2021 05:23:21 -0800 (PST) Received: from localhost ([::1]:51440 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l9Sz9-0004UU-Qa for importer@patchew.org; Tue, 09 Feb 2021 08:23:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33880) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l9Swp-0002mJ-U6 for qemu-devel@nongnu.org; Tue, 09 Feb 2021 08:20:55 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:55070) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l9Swj-0000lw-Bz for qemu-devel@nongnu.org; Tue, 09 Feb 2021 08:20:55 -0500 Received: by mail-wm1-x32f.google.com with SMTP id w4so3097428wmi.4 for ; Tue, 09 Feb 2021 05:20:48 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y11sm34752472wrh.16.2021.02.09.05.20.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Feb 2021 05:20:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RQnHSU5URki5Eoi1GvfEMafAg4qrSv6IwWbelkI4His=; b=eekVPp/C9p6r8Vv1bvidh5JjtT5UYSt+vsgApr3nfh84RAaSvnD/6OKfx3K+tcCuCR riuYCYES6FN+KlUeWd83JvS/tlphQg1PkS38P3epX/v/0GBcxhHKxwfMtsiigjF6aq2+ lbSRL4Pe8v+tiAopoakCQKbNveVHmaSx6Uj5rUXIcxIucOJyBzbFWh3adDJnHWRXHqNM 1Up7NyRhMsMXmPewbucxS7K0Uuac2p5i1ttMOFqpqBWPTlHKI0SAvEq8iF/97cHi+h+c WTwWof2XitOZhCetL6ccuau3YcbooBsqPDMTmD/f6T/sbHbs+OwmNnNCHxSeXchVcOJq G2Yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RQnHSU5URki5Eoi1GvfEMafAg4qrSv6IwWbelkI4His=; b=DYQFcntspE307xO2YsLeSmvqmOa+hvcXqvbiUCSsIsORjY7oRC8F9tLihTjGFqz31E eh571K1GUP7dg1PT/uDVRozVPn81AG6rbzYGyv0mDLQLPaNouCno8pPAnjpjGmceLpkg LUaYyNXR/iw25yijJ6D9iuaiFeukk7OV1Q3Doq+Dl9n4TdN9dw5QMl76nN7QARchGSmT a+41uXHyFniQ7yEQWYR4mxNysA2tGYmypSGeX0BWyRSclKNMYDMJbBbSC/4689GHST/4 Ikpu4XdZdvupzHBrRt8p4GcLbPzDyreNc2L1AVoNwNDZsaBwnuVwqZoZB7ljBCNwxq20 tNyQ== X-Gm-Message-State: AOAM533WGRfxJ+2+606B6/BIezvXbbXa4omVouqcfU0Nm0Gozj12s9AE tQMJzGlgWcPoAZioW3n01Zhd+w== X-Google-Smtp-Source: ABdhPJytVUwz6gtklifhSQuu0z5ZSOjp5w5MFnrIR3N+idNQhCEHAeCMVr+g/HRyzzwNkyWswYk8iw== X-Received: by 2002:a1c:1d8b:: with SMTP id d133mr3431989wmd.172.1612876847751; Tue, 09 Feb 2021 05:20:47 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 4/4] hw/timer/npcm7xx_timer: Use new clock_ns_to_ticks() Date: Tue, 9 Feb 2021 13:20:40 +0000 Message-Id: <20210209132040.5091-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210209132040.5091-1-peter.maydell@linaro.org> References: <20210209132040.5091-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , Tyrone Ting , Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Havard Skinnemoen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Use the new clock_ns_to_ticks() function in npcm7xx_timer where appropriate. Signed-off-by: Peter Maydell Reviewed-by: Hao Wu Reviewed-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/timer/npcm7xx_timer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c index 4efdf135b82..32f5e021f85 100644 --- a/hw/timer/npcm7xx_timer.c +++ b/hw/timer/npcm7xx_timer.c @@ -138,8 +138,8 @@ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *= t, uint32_t count) /* Convert a time interval in nanoseconds to a timer cycle count. */ static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns) { - return ns / clock_ticks_to_ns(t->ctrl->clock, - npcm7xx_tcsr_prescaler(t->tcsr)); + return clock_ns_to_ticks(t->ctrl->clock, ns) / + npcm7xx_tcsr_prescaler(t->tcsr); } =20 static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTime= r *t) --=20 2.20.1