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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id c19sm8335904ile.17.2021.02.07.22.57.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 22:57:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Uvwq/YN8u5pObjxC65tOZ2S//OAZBWD2Zjjr6qZSwlg=; b=i/+jHsfz07pxGGD3iV9YN6SbHZgujCMhMh/M5dDcotF69Lf7IGTs9AvBWa5VVUHDx7 zW846vc1E01fTXG4BwvfftOvDYIbp1LTe/a7ndmMgT6wH+FPvZI2jsSr1QhfVeZVcrH1 x2+tNWrQdR5H+oKyKtoEcO/mWo7DSBsNwNZNqZaOoXvVCpOx6qeB1K/Yj812W5EaubOn lsksxCSA1GCv7XN6JCsKhcTQxbJbEhcBOxLGbbrGHt/wPMVWxpiHV2s4A/Gj1pdEFAby C/ECi0Kr2/cxIy4tiU2YI9sw/CFC7sFz4ecILIZDY/HvwD3OzCZ8h0k+YCSFKchVL9j+ BkwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Uvwq/YN8u5pObjxC65tOZ2S//OAZBWD2Zjjr6qZSwlg=; b=fC+6tcHmZQiWgsObHT3NwXmLCMiv7mLFFEmXdqW0Dzvohi0F+vDth8VWA08Ve4wsYs r2P+9hm48z9C498UM2edVrHUgfHjcYDsfFi/O3wSssdGbq7A+j20l1CBDDszMy43amL0 1zc1kt4O/G7sVqxaDuHgGJtlaZuioYN2tlJlCnWNA9kKYgjpipyWdcsSvr2FNvALwOeC 3NA32udczLUYz6QzvM5VJkPbVJxvPnqfle8/wPvXsRIvoH2YF6BzCiRo5sFWPpYlN0QA QZKXuM6k0o20SYrZeUr+2aHYV3KpFSQy741hh76I53wOoCfdwFGr8XnmI5L7cNrfZ7pp xevQ== X-Gm-Message-State: AOAM5328SvXAixiar3pD5gMnDq+7DgF5Bh1MrfqtBz2KQ9OcIsmVSKKX eEdsFKrXcJDDKVfADAV8gZ//nZyp2YusOC/uiPnCWp6OqFMgEvk4k4YJ6uuzqVsxBo2ssjpWauA 2r+Tq+S9sDeWMxpLJ84R3rswdCQB4hV+T1Fze4iHRgYBouUwdEKDzO1dOuyJ18a2FO5LM+ZA= X-Google-Smtp-Source: ABdhPJxHcgfDbG7isD+tfoFGpf4zI89UsvcG7fImEhPCbqEnuClDR7MJQn0odD0Ej1yYAzmMqKDbQQ== X-Received: by 2002:a6b:fc16:: with SMTP id r22mr13510234ioh.102.1612767424468; Sun, 07 Feb 2021 22:57:04 -0800 (PST) From: Rebecca Cran To: qemu-devel@nongnu.org Subject: [PATCH v5 1/4] target/arm: Add support for FEAT_DIT, Data Independent Timing Date: Sun, 7 Feb 2021 23:56:57 -0700 Message-Id: <20210208065700.19454-2-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210208065700.19454-1-rebecca@nuviainc.com> References: <20210208065700.19454-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::d31; envelope-from=rebecca@nuviainc.com; helo=mail-io1-xd31.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Rebecca Cran , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add support for FEAT_DIT. DIT (Data Independent Timing) is a required feature for ARMv8.4. Since virtual machine execution is largely nondeterministic and TCG is outside of the security domain, it's implemented as a NOP. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu.h | 12 +++++++++++ target/arm/helper.c | 22 ++++++++++++++++++++ target/arm/internals.h | 6 ++++++ target/arm/translate-a64.c | 12 +++++++++++ 4 files changed, 52 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d080239863c0..2e5853928474 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1243,6 +1243,7 @@ void pmu_init(ARMCPU *cpu); #define CPSR_IT_2_7 (0xfc00U) #define CPSR_GE (0xfU << 16) #define CPSR_IL (1U << 20) +#define CPSR_DIT (1U << 21) #define CPSR_PAN (1U << 22) #define CPSR_J (1U << 24) #define CPSR_IT_0_1 (3U << 25) @@ -1310,6 +1311,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_SS (1U << 21) #define PSTATE_PAN (1U << 22) #define PSTATE_UAO (1U << 23) +#define PSTATE_DIT (1U << 24) #define PSTATE_TCO (1U << 25) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) @@ -3876,6 +3878,11 @@ static inline bool isar_feature_aa32_tts2uxn(const A= RMISARegisters *id) return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) !=3D 0; } =20 +static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) !=3D 0; +} + /* * 64-bit feature tests via id registers. */ @@ -4120,6 +4127,11 @@ static inline bool isar_feature_aa64_tts2uxn(const A= RMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) !=3D 0; } =20 +static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) !=3D 0; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 1a64bd748ce5..ce6965b50d42 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4419,6 +4419,24 @@ static const ARMCPRegInfo uao_reginfo =3D { .readfn =3D aa64_uao_read, .writefn =3D aa64_uao_write }; =20 +static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_DIT; +} + +static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate =3D (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT); +} + +static const ARMCPRegInfo dit_reginfo =3D { + .name =3D "DIT", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 5, + .type =3D ARM_CP_NO_RAW, .access =3D PL0_RW, + .readfn =3D aa64_dit_read, .writefn =3D aa64_dit_write +}; + static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -8212,6 +8230,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &uao_reginfo); } =20 + if (cpu_isar_feature(aa64_dit, cpu)) { + define_one_arm_cp_reg(cpu, &dit_reginfo); + } + if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { define_arm_cp_regs(cpu, vhe_reginfo); } diff --git a/target/arm/internals.h b/target/arm/internals.h index 448982dd2f9f..b251fe44506b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1228,6 +1228,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64= _t features, if (isar_feature_aa32_pan(id)) { valid |=3D CPSR_PAN; } + if (isar_feature_aa32_dit(id)) { + valid |=3D CPSR_DIT; + } =20 return valid; } @@ -1246,6 +1249,9 @@ static inline uint32_t aarch64_pstate_valid_mask(cons= t ARMISARegisters *id) if (isar_feature_aa64_uao(id)) { valid |=3D PSTATE_UAO; } + if (isar_feature_aa64_dit(id)) { + valid |=3D PSTATE_DIT; + } if (isar_feature_aa64_mte(id)) { valid |=3D PSTATE_TCO; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ffc060e5d70c..1c4b8d02f3b8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1700,6 +1700,18 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, tcg_temp_free_i32(t1); break; =20 + case 0x1a: /* DIT */ + if (!dc_isar_feature(aa64_dit, s)) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_DIT); + } else { + clear_pstate_bits(PSTATE_DIT); + } + /* There's no need to rebuild hflags because DIT is a nop */ + break; + case 0x1e: /* DAIFSet */ t1 =3D tcg_const_i32(crm); gen_helper_msr_i_daifset(cpu_env, t1); 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id c19sm8335904ile.17.2021.02.07.22.57.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 22:57:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Qb40yI/NeM085UbMxmgujwgw1843nw7bVshyCKXfzbw=; b=hTmcpVM/9gtDYNq/qHRJJFfpjlHnT+7KgESKNtieG9QkoyuRC/gYS8jhoTJydDmtiT 7+UMPLLZD6IuuLVcMtnPgNHQkWc9PxvJ8ucQP1nZ6b1151Tu2JVq7B/3VAikpiY7U9oc W+mm7NuSu1jKHGVuEMw6jJ9Nc9p7ITvv0Fu+YbFW+bxSMlkk0lOMmYbsCjgNqDmnrP/f qGsaOurUNyCwVfAHxljaOaj2ZEFn4DwUr5gmYF100Bli3vUtyf1hw4qGDYAyFri+CdYp m9pH2k4W4McWEft/Rj90TQtz3xmJC5fH9bIFcAZ+CE6x7n+0K6vWw52wto29vHZ3Zgwv JDJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Qb40yI/NeM085UbMxmgujwgw1843nw7bVshyCKXfzbw=; b=qc8dLoN0CiRxROpemN9Dw4xtCm3WZ/GNnkLDQW+0nDX943v9C0qjUlLDDZbyejYjFe 2wFyjmDwAjhqKgQRYLjyaHGc8gUZnvLIqHqdvZgBB1rYO4izmLivba2ZlgFjKQ8KweWU W95LF/+r4q7PR3AuayBKmEq/NTQ19nJ23R70HeLLHNxUNEvPb3Z+J744gkiZT6r6RR0k 601UZbXcbvuNIoG3Bhgd3q0mOc5zpSTvGVjH8gANSsEoOTvXt3weouM23OiVMpI+La+6 OCO6c12QAkTo9YAMUkQzgM3m//YkiXRjjHMxuR4YkwLInuG+3KB0P1tWlzei6ICJbKg5 RDtQ== X-Gm-Message-State: AOAM532bf1jDBuL9SnGnd7njrSInPZyH7nVxd0R72dQoyeJvYGKxqHQM Msc/CqoC0+pSSxxGSJAZ41bqaA880PuJK6MsmU4ubJy/Nl9p9JK8hb7ZQyVVqbtKHWMCxgLJZrO Q0tFau8Xdy2vDJDWmWypBwrkgFv3MfMnT/zAdOa6gizq4CncsJggc04ctTw9LRFPq3xQ5XzY= X-Google-Smtp-Source: ABdhPJw6Gp4PKMvyC371auM0rXFpMInPxi55CDICGVGrjisHQ2b5O1fKp89toKTEZHLh3E/m7Iyb2Q== X-Received: by 2002:a92:bd06:: with SMTP id c6mr15487869ile.158.1612767425918; Sun, 07 Feb 2021 22:57:05 -0800 (PST) From: Rebecca Cran To: qemu-devel@nongnu.org Subject: [PATCH v5 2/4] target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate Date: Sun, 7 Feb 2021 23:56:58 -0700 Message-Id: <20210208065700.19454-3-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210208065700.19454-1-rebecca@nuviainc.com> References: <20210208065700.19454-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::129; envelope-from=rebecca@nuviainc.com; helo=mail-il1-x129.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Rebecca Cran , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" cpsr has been treated as being the same as spsr, but it isn't. Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate. This allows us to add support for CPSR_DIT, adding helper functions to merge SPSR_ELx to and from CPSR. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/helper-a64.c | 27 +++++++++++++++++--- target/arm/helper.c | 24 ++++++++++++----- target/arm/op_helper.c | 9 +------ 3 files changed, 42 insertions(+), 18 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index c426c23d2c4e..ae611d73c2c4 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -945,11 +945,31 @@ static int el_from_spsr(uint32_t spsr) } } =20 +static void cpsr_write_from_spsr_elx(CPUARMState *env, + uint32_t val) +{ + uint32_t mask; + + /* Save SPSR_ELx.SS into PSTATE. */ + env->pstate =3D (env->pstate & ~PSTATE_SS) | (val & PSTATE_SS); + val &=3D ~PSTATE_SS; + + /* Move DIT to the correct location for CPSR */ + if (val & PSTATE_DIT) { + val &=3D ~PSTATE_DIT; + val |=3D CPSR_DIT; + } + + mask =3D aarch32_cpsr_valid_mask(env->features, \ + &env_archcpu(env)->isar); + cpsr_write(env, val, mask, CPSRWriteRaw); +} + void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) { int cur_el =3D arm_current_el(env); unsigned int spsr_idx =3D aarch64_banked_spsr_index(cur_el); - uint32_t mask, spsr =3D env->banked_spsr[spsr_idx]; + uint32_t spsr =3D env->banked_spsr[spsr_idx]; int new_el; bool return_to_aa64 =3D (spsr & PSTATE_nRW) =3D=3D 0; =20 @@ -998,10 +1018,9 @@ void HELPER(exception_return)(CPUARMState *env, uint6= 4_t new_pc) * will sort the register banks out for us, and we've already * caught all the bad-mode cases in el_from_spsr(). */ - mask =3D aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)-= >isar); - cpsr_write(env, spsr, mask, CPSRWriteRaw); + cpsr_write_from_spsr_elx(env, spsr); if (!arm_singlestep_active(env)) { - env->uncached_cpsr &=3D ~PSTATE_SS; + env->pstate &=3D ~PSTATE_SS; } aarch64_sync_64_to_32(env); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index ce6965b50d42..fd6902c890f5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9433,7 +9433,7 @@ static void take_aarch32_exception(CPUARMState *env, = int new_mode, * For exceptions taken to AArch32 we must clear the SS bit in both * PSTATE and in the old-state value we save to SPSR_, so zero i= t now. */ - env->uncached_cpsr &=3D ~PSTATE_SS; + env->pstate &=3D ~PSTATE_SS; env->spsr =3D cpsr_read(env); /* Clear IT bits. */ env->condexec_bits =3D 0; @@ -9789,6 +9789,21 @@ static int aarch64_regnum(CPUARMState *env, int aarc= h32_reg) } } =20 +static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env) +{ + uint32_t ret =3D cpsr_read(env); + + /* Move DIT to the correct location for SPSR_ELx */ + if (ret & CPSR_DIT) { + ret &=3D ~CPSR_DIT; + ret |=3D PSTATE_DIT; + } + /* Merge PSTATE.SS into SPSR_ELx */ + ret |=3D env->pstate & PSTATE_SS; + + return ret; +} + /* Handle exception entry to a target EL which is using AArch64 */ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) { @@ -9911,7 +9926,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) aarch64_save_sp(env, arm_current_el(env)); env->elr_el[new_el] =3D env->pc; } else { - old_mode =3D cpsr_read(env); + old_mode =3D cpsr_read_for_spsr_elx(env); env->elr_el[new_el] =3D env->regs[15]; =20 aarch64_sync_32_to_64(env); @@ -13205,7 +13220,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, target_ulong *cs_base, uint32_t *pflags) { uint32_t flags =3D env->hflags; - uint32_t pstate_for_ss; =20 *cs_base =3D 0; assert_hflags_rebuild_correctly(env); @@ -13215,7 +13229,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags =3D FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } - pstate_for_ss =3D env->pstate; } else { *pc =3D env->regs[15]; =20 @@ -13263,7 +13276,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, =20 flags =3D FIELD_DP32(flags, TBFLAG_AM32, THUMB, env->thumb); flags =3D FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_b= its); - pstate_for_ss =3D env->uncached_cpsr; } =20 /* @@ -13276,7 +13288,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. */ if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) && - (pstate_for_ss & PSTATE_SS)) { + (env->pstate & PSTATE_SS)) { flags =3D FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); } =20 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 5e0f123043b5..65cb37d088f8 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -389,14 +389,7 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uin= t32_t syndrome) =20 uint32_t HELPER(cpsr_read)(CPUARMState *env) { - /* - * We store the ARMv8 PSTATE.SS bit in env->uncached_cpsr. - * This is convenient for populating SPSR_ELx, but must be - * hidden from aarch32 mode, where it is not visible. - * - * TODO: ARMv8.4-DIT -- need to move SS somewhere else. - */ - return cpsr_read(env) & ~(CPSR_EXEC | PSTATE_SS); + return cpsr_read(env) & ~CPSR_EXEC; } =20 void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) --=20 2.26.2 From nobody Tue May 21 03:05:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1612784460; cv=none; d=zohomail.com; s=zohoarc; b=FMdGCy3hiBfqhym6LWSyxyQtrbYstqYU4RBdiezbH+0T68adxCFMUXs3ix0jTQwPnnOfFUmuRrmQLnIHx0bgSyGVNfPC2t5Ji1JQh+nCSSsoaU5/tq6+oEApsiIhPPyCOMgXsjEAdxSX9WmrBJlo/sDWP04nxGnH+ngopLkDpzE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612784460; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BKWB7YexJnaUit3BNYa9SGu8rC7g3Cy8dSqEGGB8qus=; b=mpGLSxOGvqQkgi8ZROGiOgviHATMAJ32SLtRNX/6OaHlbQe+qflYA7B8q6cdaq/jlkCFlBldLfJChWiWBrJ3Sz0ic4bcf1THs5cw5HWiPynYW/kHZrh5Fat10CXSVUK/l2+O7pFFvoGMt5Gqfv4pwY02MFF4n22u+0gyK1tZysA= ARC-Authentication-Results: i=1; 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id c19sm8335904ile.17.2021.02.07.22.57.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 22:57:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BKWB7YexJnaUit3BNYa9SGu8rC7g3Cy8dSqEGGB8qus=; b=NARtokfaqFyTefE19kVvZqx9lXdNA1zFZppJrp1sfEAYvqK3lPx/j16ryoA5v29YDU tpQXbPSflOSNoXih0MMe/5fwvBAzPiDgEYmHaoarfeL/qnxaw4fvqRq7rSw9Z2pPAB9i RZF5ZyTj0Vt0ahnnnKOwPxlMcGtVhYqQKtBPZqday2izF1RVY+8f2BXRvE2WRTcCfXM8 asT/7ZhAPIjBjzcZcw6++zGioKiDB3AlodqazJa/mSoRG1TXuabIOj2oC9WOQjX9eIq7 1SE53aYZtdH+VDi05Ur4LBovZJOFLXPVbWM3zjiUZPT73H0Bsvc+12NQXx/b4yjFMGYr oW6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BKWB7YexJnaUit3BNYa9SGu8rC7g3Cy8dSqEGGB8qus=; b=SIFobXKTe5s31or3sQcO+zPAUggmUWYVEMEOvMf5pe3ckYIcaQCvYOI5zuXGAQROFs DkiadIDuTXS8dgXMkYLR4Pfg3MAH0WTXkAoxHAhr0tKdUcXVBT+qL/Yqe69NPwj5mPso O4w/ZFS8e+zCLJ0uISeNApVIPYhGcBUYhfApHC8mc+EYwe6mpaS0kjrE6CYDC+5Xqpgi L4aWbgvI7mh+NLMFhckNhj3CZBG3Ignnzb0yCp6yFaKnh9PFeTjth98Eqqj4IRkLT580 KeZr1BV1cB84PO2uR/Tb+gHVhyl1APig0+tyDskVw46knsTw8lsOvNyMUOQ10InZVi/3 E20A== X-Gm-Message-State: AOAM5316ayTqBJAT+TMCLXvibDz39foXGFoHSpKaEKvE9Mluj9IN7i3M vjdQCkCxSoZOsphtfwA7+YMDbcbLMEaldhRP7vLcQUoQGsMUejjQT8Agvn4kVIzcduCjxFvKcKH gieLfA3eke5mLNi6I5xc11D3HQnov+Fu2bl+Fkukw5OOGoIaK2iQvnDa9YLCugVd579l+c04= X-Google-Smtp-Source: ABdhPJxIK+E3LufGnuth41YOkoE5kfLkzGv1UElXLCtSkXDWLknb2h8CHbhLXrDG67kbPQewVT4a9Q== X-Received: by 2002:a05:6e02:b46:: with SMTP id f6mr13271322ilu.230.1612767427183; Sun, 07 Feb 2021 22:57:07 -0800 (PST) From: Rebecca Cran To: qemu-devel@nongnu.org Subject: [PATCH v5 3/4] target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU Date: Sun, 7 Feb 2021 23:56:59 -0700 Message-Id: <20210208065700.19454-4-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210208065700.19454-1-rebecca@nuviainc.com> References: <20210208065700.19454-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::136; envelope-from=rebecca@nuviainc.com; helo=mail-il1-x136.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Rebecca Cran , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Enable FEAT_DIT for the "max" AARCH64 CPU. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 10c51181767d..c255f1bcc393 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -669,6 +669,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; @@ -718,6 +719,10 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 =3D u; =20 + u =3D cpu->isar.id_pfr0; + u =3D FIELD_DP32(u, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D u; + u =3D cpu->isar.id_mmfr3; u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ cpu->isar.id_mmfr3 =3D u; --=20 2.26.2 From nobody Tue May 21 03:05:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1612798081; cv=none; d=zohomail.com; s=zohoarc; b=NJvRGPHZ7yJ6qzNpqVeXXPm6G/0RzClwTVWsP02OcG33SyjImLNr0IDkd11A/0DwoDwpeede/aoqF0i+SKpL4WuvUVRMerTXV+I1eLWBeDRTQIIyh+sTBkF2ZmfqEab2J605U+8LA+gSgZ8XrF9kzStK/NnwZxHJvFFtDLZ2//c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612798081; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RzKZuoyEuNW82NcVhGHHTiOVySuGgC0h+4EIBJuvWAA=; b=KAyDtxO5g60RQr8ODyZJfktwg5SbL68PlPJR/iFfO9QEWE+iJnLhQMrBiqpj0qOnfFdoVdE1XmbsFOhkzwOIxwIwqrpvHMvDhtnIwGMW3dTv3A5YBI5MeAyBbs1g25xmeu61au1HQcgA5J3u23twu4fXKXl2XYHTf5CPOM2ZyNo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612798081168341.4461183217204; Mon, 8 Feb 2021 07:28:01 -0800 (PST) Received: from localhost ([::1]:32884 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l98SG-0008Ld-2j for importer@patchew.org; Mon, 08 Feb 2021 10:28:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45642) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l90Uw-0005CS-F0 for qemu-devel@nongnu.org; Mon, 08 Feb 2021 01:58:20 -0500 Received: from mail-io1-xd2d.google.com ([2607:f8b0:4864:20::d2d]:35656) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l90Ua-0003xp-0H for qemu-devel@nongnu.org; Mon, 08 Feb 2021 01:58:10 -0500 Received: by mail-io1-xd2d.google.com with SMTP id f2so1969374ioq.2 for ; Sun, 07 Feb 2021 22:57:09 -0800 (PST) Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id c19sm8335904ile.17.2021.02.07.22.57.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 22:57:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RzKZuoyEuNW82NcVhGHHTiOVySuGgC0h+4EIBJuvWAA=; b=ApmOQnUBQtN8W8NkpFFYcWgIAEuQdvVSz7hB0ouVRpiurcllSAQQGqDX7xO5DUvR7U ocV69CFnJFk0FVcdJlh8epGW4RwHdW+/Ku5fl/1BGu8exk/MUrZDzcHpROcfTGmrtY5z AvNyYBAwxS0H2rDq0qM6IF2wMa9uma+f6lnQlV1vlKHjVKqFfE+N/mFn1OWcE+J86M9p irPaBNhA63TeYNsCcOrNUNuX/arQuZCGbklqe8DVnKqo2cbwIN3D9PRkmHy9JxzwipYK yGlNQ1n9jtoBkVPfCZ62m1+kkIA/rNW665Vis19ZhX8SYFu2HdSi/12JQtcZWTu+Sbyp 1KgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RzKZuoyEuNW82NcVhGHHTiOVySuGgC0h+4EIBJuvWAA=; b=ZLhZJ5JYh4yspJEnCEYSq1HbwAZlBVsvuKrvbOcSsC8B/ixSGjo20BnemCCmU0XKL6 AIwe0eCV64CMbr3JnhIR1A+CoTilXyyAnV77asrv2fPmj5zZ0CN+mlwMrIOw3dTWgogY HvfDh1hsSsHktNFI7JOV4/tEb3iZx/CjzjEfXmXxxvOeQwB46psfL6LbZGfGCjn7y3JG D5pE9kyBRTstIvNY58BCz/JzCDfgdx8HAyU6igz3RUxUrce5gsWU5058egpRpV5fQVGp PNyqN8ld3SEBNWrA+RGQyvaWe7TF/vyIRpr3ErpIdQ2SRybSzIV9D464SVrYsm6bD2l7 qvlQ== X-Gm-Message-State: AOAM531RiiHifj0tqt93zjBYHEf/r1INZETsrOkE8Dq3byVr6S4mS5MT PB1/gU0NH9g+02B812k7yc4L9gsz5j8N2ID+jI9E87lhEPvSNNtk6PlplsFLxTGrTIUPtpmn1Os ddA0efUlle6ER2b+CaIkhMkEFK3AbKFJntGo08jwEeOMw2cxDZYZ909hNK+p7tErq19nTZH8= X-Google-Smtp-Source: ABdhPJzE0Hrq484IjWXCmFWSFiuY7RxfrSGb3lEJxT8rRROAYohX6pIUxkV3Rc99Rf4G1x8Tub/MYw== X-Received: by 2002:a05:6602:1541:: with SMTP id h1mr13659630iow.171.1612767428349; Sun, 07 Feb 2021 22:57:08 -0800 (PST) From: Rebecca Cran To: qemu-devel@nongnu.org Subject: [PATCH v5 4/4] target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU Date: Sun, 7 Feb 2021 23:57:00 -0700 Message-Id: <20210208065700.19454-5-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210208065700.19454-1-rebecca@nuviainc.com> References: <20210208065700.19454-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::d2d; envelope-from=rebecca@nuviainc.com; helo=mail-io1-xd2d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Rebecca Cran , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Enable FEAT_DIT for the "max" 32-bit CPU. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8ddb2556f8cf..5cf6c056c50f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2202,6 +2202,10 @@ static void arm_max_initfn(Object *obj) t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ cpu->isar.id_mmfr4 =3D t; + + t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D t; } #endif } --=20 2.26.2