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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YmDqe/82SlyxP6c0GtyFsHwbtixl9cebfPdkUT3Hqik=; b=sqW2NuHdeWSvl9peDLcZqRFFhp7RNNX/W1Kl3JLWCTk5q9zSRxnyIMWNWtWORKJ3J+ r/y70tujYk1MKL0RbO5KuyMICRm8gVVWoKAB0hrQVN4WXWO/1Qc2Pf9CCfG6pVtwvFWS vQS4tSd7KJOvNgvxD23DwWbapGWKfOjFwow4ys91y9AtxrUn0qttpBZRF5Vn7YFGjJud UQxWSnhWRd/CGu01Aio4rYbr12g51OXKwnkB2bK6p6JB3H8i8fNq7DU0koQ1Z1GYxYPi xhgN+lJ/EGRv2WKEpF4gFsBKktRUW7ih3xlAY7UqhpZugjcLEv80fO+bbCchgiazQnzg PNeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YmDqe/82SlyxP6c0GtyFsHwbtixl9cebfPdkUT3Hqik=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 20 ++++++++++++++++++++ 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 49b98f33b9..426dd92e51 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -26,6 +26,7 @@ C_O1_I2(r, r, ri) C_O1_I2(r, rZ, r) C_O1_I2(v, v, r) C_O1_I2(v, v, v) +C_O1_I3(v, v, v, v) C_O1_I4(r, r, ri, r, 0) C_O1_I4(r, r, ri, rI, 0) C_O2_I2(b, a, 0, r) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index efa32f348c..127ccd30af 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -154,7 +154,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 1 -#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 1 #define TCG_TARGET_HAS_cmpsel_vec 0 =20 /* used for function call generation */ diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index d4877dcf67..3c86b233b0 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -296,6 +296,7 @@ typedef enum S390Opcode { VRRa_VUPH =3D 0xe7d7, VRRa_VUPL =3D 0xe7d6, VRRc_VX =3D 0xe76d, + VRRe_VSEL =3D 0xe78d, VRRf_VLVGP =3D 0xe762, =20 VRSa_VERLL =3D 0xe733, @@ -635,6 +636,18 @@ static void tcg_out_insn_VRRc(TCGContext *s, S390Opcod= e op, tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12)); } =20 +static void tcg_out_insn_VRRe(TCGContext *s, S390Opcode op, + TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) +{ + tcg_debug_assert(v1 >=3D TCG_REG_V0 && v1 <=3D TCG_REG_V31); + tcg_debug_assert(v2 >=3D TCG_REG_V0 && v2 <=3D TCG_REG_V31); + tcg_debug_assert(v3 >=3D TCG_REG_V0 && v3 <=3D TCG_REG_V31); + tcg_debug_assert(v4 >=3D TCG_REG_V0 && v4 <=3D TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v2 & 15)); + tcg_out16(s, v3 << 12); + tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, v4) | ((v4 & 15) << 12)); +} + static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, TCGReg v1, TCGReg r2, TCGReg r3) { @@ -2752,6 +2765,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece); break; =20 + case INDEX_op_bitsel_vec: + tcg_out_insn(s, VRRe, VSEL, a0, a1, a2, args[3]); + break; + case INDEX_op_cmp_vec: switch ((TCGCond)args[3]) { case TCG_COND_EQ: @@ -2792,6 +2809,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_add_vec: case INDEX_op_and_vec: case INDEX_op_andc_vec: + case INDEX_op_bitsel_vec: case INDEX_op_neg_vec: case INDEX_op_not_vec: case INDEX_op_or_vec: @@ -3133,6 +3151,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_shrs_vec: case INDEX_op_sars_vec: return C_O1_I2(v, v, r); + case INDEX_op_bitsel_vec: + return C_O1_I3(v, v, v, v); =20 default: g_assert_not_reached(); --=20 2.25.1