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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XkT/fAMq7fP12/ZBZ5fx+qLL9TNYOIdrJVXalZ7l+Is=; b=uf1pwVbep8YNkZbsl2Sir0qok6hEreYkSr4vHtfBVwZSSWsHyLqHpR1TYhY+3EjNRh iGx/atXFuuQBUfVfiuWhHUhJBzxvFVg7yBI90kj6BEVeIaq//WY316xPjelrYEYOBmqG Duv3/YSYFAcUXyKTOtmRgHFWr0iAx6SIZIrIug4MJzw1bkYLv3wZ9O5sa0VoMVWuo4PY L+12NYFnT/C3h7C0cCXpxO50jGSfBMxSKGb2lkpAksGIko+mpozFi4W+l1AFifVTbfMy R/PnWMCYTaoM5U6EgGYGNusNyqLJKDD7teTImKq0w2O+UulojNSBkU8TXBVR2K9FcpdS /IzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XkT/fAMq7fP12/ZBZ5fx+qLL9TNYOIdrJVXalZ7l+Is=; b=U26ioJQaLA906DYAOICEFSRm4CmphTUv+QaUK1cuKRoMh0hQUmEpQCz8d6GgzoADUr 8vyFmlDKePxfeXp+CyB2zaiFK4H9x0eTKWNUM7Ltw5Z4S04p094PFw4F6peOBoMYg9Vs 78Hz69HPbCNQ3DCzf1Wq1Xek6/KkxZgAli1jS0tVDYYjm6NvLdSRTN9djr+NPBCoJR2g 4u3H0qYl2SAWpqXpiC9gOrNCtAvN/ibUnVKiCI2TYa+M2I4IVE5Q4yKSh/Xwbs09jfv8 1NTYg/2Yh/MNaqaQGAKccV82mgZqdvYz1uZ9eyoeeegTNI2bngoyYMxvHKYgD1JnoLT7 pz4w== X-Gm-Message-State: AOAM530ZDMOCHUEckmY+P0VNGjZE+o4it+pBVDGhcd4hIUKBhD8w6XD2 yMxpW3ASmfkgXynlDSISj7RJuv8BoBhMpQ== X-Google-Smtp-Source: ABdhPJw/iewNzSZB8wXkab2aZ2oR9QRA1BTXIKzEwZJlct3UN3I6f+CM6WdDfEvY3JBduJ7lU8olkw== X-Received: by 2002:a17:902:a9ca:b029:e1:b3e:406c with SMTP id b10-20020a170902a9cab02900e10b3e406cmr14421443plr.84.1612752673469; Sun, 07 Feb 2021 18:51:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 09/16] tcg/s390x: Implement andc, orc, abs, neg, not vector operations Date: Sun, 7 Feb 2021 18:50:54 -0800 Message-Id: <20210208025101.271726-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These logical and arithmetic operations are optional but trivial. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 10 +++++----- tcg/s390x/tcg-target.c.inc | 34 +++++++++++++++++++++++++++++++++- 3 files changed, 39 insertions(+), 6 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index ce9432cfe3..cb953896d5 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -17,6 +17,7 @@ C_O0_I2(v, r) C_O1_I1(r, L) C_O1_I1(r, r) C_O1_I1(v, r) +C_O1_I1(v, v) C_O1_I1(v, vr) C_O1_I2(r, 0, ri) C_O1_I2(r, 0, rI) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index e8659bf576..dd11972ed2 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -140,11 +140,11 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_v128 HAVE_FACILITY(VECTOR) #define TCG_TARGET_HAS_v256 0 =20 -#define TCG_TARGET_HAS_andc_vec 0 -#define TCG_TARGET_HAS_orc_vec 0 -#define TCG_TARGET_HAS_not_vec 0 -#define TCG_TARGET_HAS_neg_vec 0 -#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_andc_vec 1 +#define TCG_TARGET_HAS_orc_vec 1 +#define TCG_TARGET_HAS_not_vec 1 +#define TCG_TARGET_HAS_neg_vec 1 +#define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rotv_vec 0 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 08315c7b05..23c25ff619 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -270,13 +270,18 @@ typedef enum S390Opcode { VRIb_VGM =3D 0xe746, VRIc_VREP =3D 0xe74d, =20 + VRRa_VLC =3D 0xe7de, + VRRa_VLP =3D 0xe7df, VRRa_VLR =3D 0xe756, VRRc_VA =3D 0xe7f3, VRRc_VCEQ =3D 0xe7f8, /* we leave the m5 cs field 0 */ VRRc_VCH =3D 0xe7fb, /* " */ VRRc_VCHL =3D 0xe7f9, /* " */ VRRc_VN =3D 0xe768, + VRRc_VNC =3D 0xe769, + VRRc_VNO =3D 0xe76b, VRRc_VO =3D 0xe76a, + VRRc_VOC =3D 0xe76f, VRRc_VS =3D 0xe7f7, VRRc_VX =3D 0xe76d, VRRf_VLVGP =3D 0xe762, @@ -2634,6 +2639,16 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, tcg_out_dupm_vec(s, type, vece, a0, a1, a2); break; =20 + case INDEX_op_abs_vec: + tcg_out_insn(s, VRRa, VLP, a0, a1, vece); + break; + case INDEX_op_neg_vec: + tcg_out_insn(s, VRRa, VLC, a0, a1, vece); + break; + case INDEX_op_not_vec: + tcg_out_insn(s, VRRc, VNO, a0, a1, a1, 0); + break; + case INDEX_op_add_vec: tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece); break; @@ -2643,9 +2658,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_and_vec: tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0); break; + case INDEX_op_andc_vec: + tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0); + break; case INDEX_op_or_vec: tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0); break; + case INDEX_op_orc_vec: + tcg_out_insn(s, VRRc, VOC, a0, a1, a2, 0); + break; case INDEX_op_xor_vec: tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); break; @@ -2676,10 +2697,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode= opc, int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { switch (opc) { + case INDEX_op_abs_vec: case INDEX_op_add_vec: - case INDEX_op_sub_vec: case INDEX_op_and_vec: + case INDEX_op_andc_vec: + case INDEX_op_neg_vec: + case INDEX_op_not_vec: case INDEX_op_or_vec: + case INDEX_op_orc_vec: + case INDEX_op_sub_vec: case INDEX_op_xor_vec: return 1; case INDEX_op_cmp_vec: @@ -2908,10 +2934,16 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) return C_O1_I1(v, r); case INDEX_op_dup_vec: return C_O1_I1(v, vr); + case INDEX_op_abs_vec: + case INDEX_op_neg_vec: + case INDEX_op_not_vec: + return C_O1_I1(v, v); case INDEX_op_add_vec: case INDEX_op_sub_vec: case INDEX_op_and_vec: + case INDEX_op_andc_vec: case INDEX_op_or_vec: + case INDEX_op_orc_vec: case INDEX_op_xor_vec: case INDEX_op_cmp_vec: return C_O1_I2(v, v, v); --=20 2.25.1