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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nvbfT9FlFh307EBqHKObJFDpc/YAbcER3B44sbw1RyQ=; b=x8cI8JrTyYoCjpTke8J9pCpzHXomZgZegkQ0xyWrd/7hCw9WQvbHz2whJp5lognnGy eFZGiNETW5L3QlBnHPE3/5Jst1OTPhaGWR+np5lgC9/62Srs92FFPwfVUJKzXesU0OWo SXsPGrUc1NBXYToR6lFyG1nRtpwUa4GUZaHHeEcj6gw/XRsLbDB+Wjm32JVLlY6A7B/s 0BZAEp606ZgY6q52G60/QtILAhTrWnZma3SK3QzLO5pS61oUq8P1D/DkmBHmR9QCrcuP SxzvIOpg8wKbHpd5VljGI+AeXeeagTrsfmFXlSeZ0B4MZrfbpny6stIePymyzfjM8pos XadA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nvbfT9FlFh307EBqHKObJFDpc/YAbcER3B44sbw1RyQ=; b=k4xDP9FmKFLlL0WhWdeMuADQoGDMfxJx6PyccmRdNMlnHKcSihDCv8DJqQ8Dg3dnCQ +fKk5svAMOT3rWudT0IuBj39jTZVLUd0r/iQODMr2tcBApRnfXhCsHS3+ojKHkErpZJq +ATAZy3q2Fy2pl+22BHMgu8O6o/zi7pafdSs9fNr+R5eIFMxjz0wDKqWTRvfOTaqzMwg nEgc2oFdYzyf2qFaQ9xMQqi5SAJYVOQsrIKBO8OVjxiJT0/ApXrZh1Td/Xe4xn+LguDq FOEO3leOx8fYSy6JCvLRBGZ2zgNLfsffJ+NGUrNsyPJ08sTICmW/rJNTLt+uwaGdIryI SfTw== X-Gm-Message-State: AOAM532LP876NK+AelChi/ZXzOW0uaJ62I2D1tLuX2R03KzYiAhQIWPc KWzhkJPxjY0+bvFRMnNvru+2eegNShrd/w== X-Google-Smtp-Source: ABdhPJztAR8oW7jqz5yQZuWUHI58CTQua/Cab0k7hiBoyw1Dd+1+zymRY+bUXc6ocV53uLu1b0UQkA== X-Received: by 2002:a65:4906:: with SMTP id p6mr14896976pgs.419.1612752664611; Sun, 07 Feb 2021 18:51:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 01/16] tcg/s390x: Rename from tcg/s390 Date: Sun, 7 Feb 2021 18:50:46 -0800 Message-Id: <20210208025101.271726-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) This emphasizes that we don't support s390, only 64-bit s390x hosts. Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- meson.build | 2 -- tcg/{s390 =3D> s390x}/tcg-target-con-set.h | 0 tcg/{s390 =3D> s390x}/tcg-target-con-str.h | 0 tcg/{s390 =3D> s390x}/tcg-target.h | 0 tcg/{s390 =3D> s390x}/tcg-target.c.inc | 0 5 files changed, 2 deletions(-) rename tcg/{s390 =3D> s390x}/tcg-target-con-set.h (100%) rename tcg/{s390 =3D> s390x}/tcg-target-con-str.h (100%) rename tcg/{s390 =3D> s390x}/tcg-target.h (100%) rename tcg/{s390 =3D> s390x}/tcg-target.c.inc (100%) diff --git a/meson.build b/meson.build index 2d8b433ff0..d6ddf88b00 100644 --- a/meson.build +++ b/meson.build @@ -233,8 +233,6 @@ if not get_option('tcg').disabled() tcg_arch =3D 'tci' elif config_host['ARCH'] =3D=3D 'sparc64' tcg_arch =3D 'sparc' - elif config_host['ARCH'] =3D=3D 's390x' - tcg_arch =3D 's390' elif config_host['ARCH'] in ['x86_64', 'x32'] tcg_arch =3D 'i386' elif config_host['ARCH'] =3D=3D 'ppc64' diff --git a/tcg/s390/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h similarity index 100% rename from tcg/s390/tcg-target-con-set.h rename to tcg/s390x/tcg-target-con-set.h diff --git a/tcg/s390/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h similarity index 100% rename from tcg/s390/tcg-target-con-str.h rename to tcg/s390x/tcg-target-con-str.h diff --git a/tcg/s390/tcg-target.h b/tcg/s390x/tcg-target.h similarity index 100% rename from tcg/s390/tcg-target.h rename to tcg/s390x/tcg-target.h diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc similarity index 100% rename from tcg/s390/tcg-target.c.inc rename to tcg/s390x/tcg-target.c.inc --=20 2.25.1 From nobody Tue Nov 18 19:47:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612757254; cv=none; d=zohomail.com; s=zohoarc; b=QqiuOrjfGxMgWmmQbILqPoYmfnb8AQ3YQDVW7GfafnFbPC1qW6UNAsBqyhgqg8VqYVbjG6Rj1UYfQyDqzz5pZ4P4YoyFGmuD4mCkGNlFdGAjGzf7c5uOHUwkVajxMQeMcQ45j28guu9tU58/q011OS0LIJM3dvUBPfo2T20BBsQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612757254; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mFFYC/bBe+aX80StY3T1pSBCo00lrevoIYEo9VDtg20=; b=c/Jy7M0bQfLd7b4L/5gFz6I7Nn4Pa1wLxOsSfXRjEAPQdlh0aQLt+6CJLB6KQGurF7za0DIEs74IXdLTw9dlFx0AMMm1XgKi/ePZ/deAH2vpqUYP/TTT3jC1YXjo4MDC973gIpFo+Xi+T38J5S6lxhjClxNtgmpWyEEqkgn0v1c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612757254513592.2184843254125; Sun, 7 Feb 2021 20:07:34 -0800 (PST) Received: from localhost ([::1]:44466 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8xpf-0004fR-AC for importer@patchew.org; Sun, 07 Feb 2021 23:07:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60132) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wds-00080s-DR for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:51:12 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:43565) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wdp-0001JQ-9z for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:51:12 -0500 Received: by mail-pf1-x435.google.com with SMTP id q131so8755079pfq.10 for ; Sun, 07 Feb 2021 18:51:06 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mFFYC/bBe+aX80StY3T1pSBCo00lrevoIYEo9VDtg20=; b=z66+h93tATJ0pHV4DNpEYzWtTaJpV5uFHF63KZSzIkCKAzke7boREZ7ZAKnznWA0sz 2jm3rIwWmDmpePgA2lZbijFSCXwYGU1OUWVwNT7haw9/BsjrvgPtPQvr/OwbpsQ9MCyL r8EA5PIeXgcaKE6T8DjJIh120tn9whDjIWkVw/uUGJT2x+9ebhVE8zlIY95BII6DCu2N csgQPEkgd+bHayrODibBn8PCOdYtY/nGlKr4CNo57MLGyUh0l/vTBEFgoCj+uOaCc1Db T5kO+EAV8x8qQuNCnsIlu1zYB/ViAtJh3g0BCERjK4hjJJtGhnxqpUKkgpoahJ6A8za6 1J+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mFFYC/bBe+aX80StY3T1pSBCo00lrevoIYEo9VDtg20=; b=rjlo/QODAtgG3Ikyfi/gRjM1h/lTrfGfs0Yi732FJB84rBethipHlp9N4F+N+k4lp3 PqsGeUDA9nEmMoTYI02HYkf4rkY5C9xwdl+qkWVXY89ibi7KvK6Iy85TsBzHoZqnAupu N3buRG1VdRqzihoU37ATlqn/HcKv5W2OGcywQ93s92v8FtbtXrvNp07euU4piCZvQPea w/KiNjIct3ns+RnLe4UGRk/tqRoXyOcjSEQsle6R8M+eb/vkGMS3p63HeE6bJ8OIPxMg F1lAgoZKTCR01+OT5RFCGcIRPIi6Ah+lsFBHPjAS+Koj7nM2phrOe3yX9007GoUKCbMq HcYA== X-Gm-Message-State: AOAM533B95+LxRIkzxeyupDX2f5SHKcLfarQcvMPFl1y8lDAMG2gXjbb qQbussvAVpcxOSo03KA6go6Y0Z+ikbo3DQ== X-Google-Smtp-Source: ABdhPJxJ4Q9Ib3Msm5m9zzZ3fva6HRKn3hXkLb7YoWfBAzfhNCbsUcuhsVugnzLFz7+yGlmwbn/joA== X-Received: by 2002:a63:5116:: with SMTP id f22mr14807314pgb.162.1612752665605; Sun, 07 Feb 2021 18:51:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 02/16] tcg/s390x: Change FACILITY representation Date: Sun, 7 Feb 2021 18:50:47 -0800 Message-Id: <20210208025101.271726-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) We will shortly need to be able to check facilities beyond the first 64. Instead of explicitly masking against s390_facilities, create a HAVE_FACILITY macro that indexes an array. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- v2: Change name to HAVE_FACILITY (david) --- tcg/s390x/tcg-target.h | 29 ++++++++------- tcg/s390x/tcg-target.c.inc | 74 +++++++++++++++++++------------------- 2 files changed, 52 insertions(+), 51 deletions(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 641464eea4..c612d24803 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -52,16 +52,19 @@ typedef enum TCGReg { /* A list of relevant facilities used by this translator. Some of these are required for proper operation, and these are checked at startup. */ =20 -#define FACILITY_ZARCH_ACTIVE (1ULL << (63 - 2)) -#define FACILITY_LONG_DISP (1ULL << (63 - 18)) -#define FACILITY_EXT_IMM (1ULL << (63 - 21)) -#define FACILITY_GEN_INST_EXT (1ULL << (63 - 34)) -#define FACILITY_LOAD_ON_COND (1ULL << (63 - 45)) +#define FACILITY_ZARCH_ACTIVE 2 +#define FACILITY_LONG_DISP 18 +#define FACILITY_EXT_IMM 21 +#define FACILITY_GEN_INST_EXT 34 +#define FACILITY_LOAD_ON_COND 45 #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND #define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND -#define FACILITY_LOAD_ON_COND2 (1ULL << (63 - 53)) +#define FACILITY_LOAD_ON_COND2 53 =20 -extern uint64_t s390_facilities; +extern uint64_t s390_facilities[1]; + +#define HAVE_FACILITY(X) \ + ((s390_facilities[FACILITY_##X / 64] >> (63 - FACILITY_##X % 64)) & 1) =20 /* optional instructions */ #define TCG_TARGET_HAS_div2_i32 1 @@ -82,8 +85,8 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_clz_i32 0 #define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_ctpop_i32 0 -#define TCG_TARGET_HAS_deposit_i32 (s390_facilities & FACILITY_GEN_INST= _EXT) -#define TCG_TARGET_HAS_extract_i32 (s390_facilities & FACILITY_GEN_INST= _EXT) +#define TCG_TARGET_HAS_deposit_i32 HAVE_FACILITY(GEN_INST_EXT) +#define TCG_TARGET_HAS_extract_i32 HAVE_FACILITY(GEN_INST_EXT) #define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_movcond_i32 1 @@ -96,7 +99,7 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_extrl_i64_i32 0 #define TCG_TARGET_HAS_extrh_i64_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 -#define TCG_TARGET_HAS_direct_jump (s390_facilities & FACILITY_GEN_INST= _EXT) +#define TCG_TARGET_HAS_direct_jump HAVE_FACILITY(GEN_INST_EXT) #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 #define TCG_TARGET_HAS_div2_i64 1 @@ -117,11 +120,11 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_eqv_i64 0 #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nor_i64 0 -#define TCG_TARGET_HAS_clz_i64 (s390_facilities & FACILITY_EXT_IMM) +#define TCG_TARGET_HAS_clz_i64 HAVE_FACILITY(EXT_IMM) #define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_ctpop_i64 0 -#define TCG_TARGET_HAS_deposit_i64 (s390_facilities & FACILITY_GEN_INST= _EXT) -#define TCG_TARGET_HAS_extract_i64 (s390_facilities & FACILITY_GEN_INST= _EXT) +#define TCG_TARGET_HAS_deposit_i64 HAVE_FACILITY(GEN_INST_EXT) +#define TCG_TARGET_HAS_extract_i64 HAVE_FACILITY(GEN_INST_EXT) #define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_movcond_i64 1 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 695d7ee652..3b632d8b24 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -66,7 +66,7 @@ We don't need this when we have pc-relative loads with the general instructions extension facility. */ #define TCG_REG_TB TCG_REG_R12 -#define USE_REG_TB (!(s390_facilities & FACILITY_GEN_INST_EXT)) +#define USE_REG_TB (!HAVE_FACILITY(GEN_INST_EXT)) =20 #ifndef CONFIG_SOFTMMU #define TCG_GUEST_BASE_REG TCG_REG_R13 @@ -377,7 +377,7 @@ static void * const qemu_st_helpers[16] =3D { #endif =20 static const tcg_insn_unit *tb_ret_addr; -uint64_t s390_facilities; +uint64_t s390_facilities[1]; =20 static bool patch_reloc(tcg_insn_unit *src_rw, int type, intptr_t value, intptr_t addend) @@ -580,7 +580,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, } =20 /* Try all 48-bit insns that can load it in one go. */ - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { if (sval =3D=3D (int32_t)sval) { tcg_out_insn(s, RIL, LGFI, ret, sval); return; @@ -623,7 +623,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, } =20 /* Otherwise, stuff it in the constant pool. */ - if (s390_facilities & FACILITY_GEN_INST_EXT) { + if (HAVE_FACILITY(GEN_INST_EXT)) { tcg_out_insn(s, RIL, LGRL, ret, 0); new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2); } else if (USE_REG_TB && !in_prologue) { @@ -709,7 +709,7 @@ static void tcg_out_ld_abs(TCGContext *s, TCGType type, { intptr_t addr =3D (intptr_t)abs; =20 - if ((s390_facilities & FACILITY_GEN_INST_EXT) && !(addr & 1)) { + if (HAVE_FACILITY(GEN_INST_EXT) && !(addr & 1)) { ptrdiff_t disp =3D tcg_pcrel_diff(s, abs) >> 1; if (disp =3D=3D (int32_t)disp) { if (type =3D=3D TCG_TYPE_I32) { @@ -743,7 +743,7 @@ static inline void tcg_out_risbg(TCGContext *s, TCGReg = dest, TCGReg src, =20 static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg sr= c) { - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { tcg_out_insn(s, RRE, LGBR, dest, src); return; } @@ -763,7 +763,7 @@ static void tgen_ext8s(TCGContext *s, TCGType type, TCG= Reg dest, TCGReg src) =20 static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg sr= c) { - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { tcg_out_insn(s, RRE, LLGCR, dest, src); return; } @@ -783,7 +783,7 @@ static void tgen_ext8u(TCGContext *s, TCGType type, TCG= Reg dest, TCGReg src) =20 static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg s= rc) { - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { tcg_out_insn(s, RRE, LGHR, dest, src); return; } @@ -803,7 +803,7 @@ static void tgen_ext16s(TCGContext *s, TCGType type, TC= GReg dest, TCGReg src) =20 static void tgen_ext16u(TCGContext *s, TCGType type, TCGReg dest, TCGReg s= rc) { - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { tcg_out_insn(s, RRE, LLGHR, dest, src); return; } @@ -891,7 +891,7 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGR= eg dest, uint64_t val) tgen_ext32u(s, dest, dest); return; } - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { if ((val & valid) =3D=3D 0xff) { tgen_ext8u(s, TCG_TYPE_I64, dest, dest); return; @@ -912,7 +912,7 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGR= eg dest, uint64_t val) } =20 /* Try all 48-bit insns that can perform it in one go. */ - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { for (i =3D 0; i < 2; i++) { tcg_target_ulong mask =3D ~(0xffffffffull << i*32); if (((val | ~valid) & mask) =3D=3D mask) { @@ -921,7 +921,7 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGR= eg dest, uint64_t val) } } } - if ((s390_facilities & FACILITY_GEN_INST_EXT) && risbg_mask(val)) { + if (HAVE_FACILITY(GEN_INST_EXT) && risbg_mask(val)) { tgen_andi_risbg(s, dest, dest, val); return; } @@ -970,7 +970,7 @@ static void tgen_ori(TCGContext *s, TCGType type, TCGRe= g dest, uint64_t val) } =20 /* Try all 48-bit insns that can perform it in one go. */ - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { for (i =3D 0; i < 2; i++) { tcg_target_ulong mask =3D (0xffffffffull << i*32); if ((val & mask) !=3D 0 && (val & ~mask) =3D=3D 0) { @@ -995,7 +995,7 @@ static void tgen_ori(TCGContext *s, TCGType type, TCGRe= g dest, uint64_t val) /* Perform the OR via sequential modifications to the high and low parts. Do this via recursion to handle 16-bit vs 32-bit masks in each half. */ - tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM); + tcg_debug_assert(HAVE_FACILITY(EXT_IMM)); tgen_ori(s, type, dest, val & 0x00000000ffffffffull); tgen_ori(s, type, dest, val & 0xffffffff00000000ull); } @@ -1004,7 +1004,7 @@ static void tgen_ori(TCGContext *s, TCGType type, TCG= Reg dest, uint64_t val) static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t v= al) { /* Try all 48-bit insns that can perform it in one go. */ - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { if ((val & 0xffffffff00000000ull) =3D=3D 0) { tcg_out_insn(s, RIL, XILF, dest, val); return; @@ -1028,7 +1028,7 @@ static void tgen_xori(TCGContext *s, TCGType type, TC= GReg dest, uint64_t val) tcg_tbrel_diff(s, NULL)); } else { /* Perform the xor by parts. */ - tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM); + tcg_debug_assert(HAVE_FACILITY(EXT_IMM)); if (val & 0xffffffff) { tcg_out_insn(s, RIL, XILF, dest, val); } @@ -1062,7 +1062,7 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGC= ond c, TCGReg r1, goto exit; } =20 - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { if (type =3D=3D TCG_TYPE_I32) { op =3D (is_unsigned ? RIL_CLFI : RIL_CFI); tcg_out_insn_RIL(s, op, r1, c2); @@ -1125,7 +1125,7 @@ static void tgen_setcond(TCGContext *s, TCGType type,= TCGCond cond, bool have_loc; =20 /* With LOC2, we can always emit the minimum 3 insns. */ - if (s390_facilities & FACILITY_LOAD_ON_COND2) { + if (HAVE_FACILITY(LOAD_ON_COND2)) { /* Emit: d =3D 0, d =3D (cc ? 1 : d). */ cc =3D tgen_cmp(s, type, cond, c1, c2, c2const, false); tcg_out_movi(s, TCG_TYPE_I64, dest, 0); @@ -1133,7 +1133,7 @@ static void tgen_setcond(TCGContext *s, TCGType type,= TCGCond cond, return; } =20 - have_loc =3D (s390_facilities & FACILITY_LOAD_ON_COND) !=3D 0; + have_loc =3D HAVE_FACILITY(LOAD_ON_COND); =20 /* For HAVE_LOC, only the paths through GTU/GT/LEU/LE are smaller. */ restart: @@ -1219,7 +1219,7 @@ static void tgen_movcond(TCGContext *s, TCGType type,= TCGCond c, TCGReg dest, TCGArg v3, int v3const) { int cc; - if (s390_facilities & FACILITY_LOAD_ON_COND) { + if (HAVE_FACILITY(LOAD_ON_COND)) { cc =3D tgen_cmp(s, type, c, c1, c2, c2const, false); if (v3const) { tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc); @@ -1252,7 +1252,7 @@ static void tgen_clz(TCGContext *s, TCGReg dest, TCGR= eg a1, } else { tcg_out_mov(s, TCG_TYPE_I64, dest, a2); } - if (s390_facilities & FACILITY_LOAD_ON_COND) { + if (HAVE_FACILITY(LOAD_ON_COND)) { /* Emit: if (one bit found) dest =3D r0. */ tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2); } else { @@ -1328,7 +1328,7 @@ static void tgen_brcond(TCGContext *s, TCGType type, = TCGCond c, { int cc; =20 - if (s390_facilities & FACILITY_GEN_INST_EXT) { + if (HAVE_FACILITY(GEN_INST_EXT)) { bool is_unsigned =3D is_unsigned_cond(c); bool in_range; S390Opcode opc; @@ -1522,7 +1522,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg = addr_reg, MemOp opc, cross pages using the address of the last byte of the access. */ a_off =3D (a_bits >=3D s_bits ? 0 : s_mask - a_mask); tlb_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; - if ((s390_facilities & FACILITY_GEN_INST_EXT) && a_off =3D=3D 0) { + if (HAVE_FACILITY(GEN_INST_EXT) && a_off =3D=3D 0) { tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask); } else { tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off); @@ -1812,7 +1812,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, tcg_out_insn(s, RI, AHI, a0, a2); break; } - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { tcg_out_insn(s, RIL, AFI, a0, a2); break; } @@ -2036,7 +2036,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, tcg_out_insn(s, RI, AGHI, a0, a2); break; } - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { if (a2 =3D=3D (int32_t)a2) { tcg_out_insn(s, RIL, AGFI, a0, a2); break; @@ -2261,8 +2261,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, /* The host memory model is quite strong, we simply need to serialize the instruction stream. */ if (args[0] & TCG_MO_ST_LD) { - tcg_out_insn(s, RR, BCR, - s390_facilities & FACILITY_FAST_BCR_SER ? 14 : 15= , 0); + tcg_out_insn(s, RR, BCR, HAVE_FACILITY(FAST_BCR_SER) ? 14 : 15= , 0); } break; =20 @@ -2325,7 +2324,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: - return (s390_facilities & FACILITY_DISTINCT_OPS + return (HAVE_FACILITY(DISTINCT_OPS) ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ri)); =20 @@ -2333,19 +2332,19 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) /* If we have the general-instruction-extensions, then we have MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ - return (s390_facilities & FACILITY_GEN_INST_EXT + return (HAVE_FACILITY(GEN_INST_EXT) ? C_O1_I2(r, 0, ri) : C_O1_I2(r, 0, rI)); =20 case INDEX_op_mul_i64: - return (s390_facilities & FACILITY_GEN_INST_EXT + return (HAVE_FACILITY(GEN_INST_EXT) ? C_O1_I2(r, 0, rJ) : C_O1_I2(r, 0, rI)); =20 case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: - return (s390_facilities & FACILITY_DISTINCT_OPS + return (HAVE_FACILITY(DISTINCT_OPS) ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ri)); =20 @@ -2389,7 +2388,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) =20 case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return (s390_facilities & FACILITY_LOAD_ON_COND2 + return (HAVE_FACILITY(LOAD_ON_COND2) ? C_O1_I4(r, r, ri, rI, 0) : C_O1_I4(r, r, ri, r, 0)); =20 @@ -2404,13 +2403,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - return (s390_facilities & FACILITY_EXT_IMM + return (HAVE_FACILITY(EXT_IMM) ? C_O2_I4(r, r, 0, 1, ri, r) : C_O2_I4(r, r, 0, 1, r, r)); =20 case INDEX_op_add2_i64: case INDEX_op_sub2_i64: - return (s390_facilities & FACILITY_EXT_IMM + return (HAVE_FACILITY(EXT_IMM) ? C_O2_I4(r, r, 0, 1, rA, r) : C_O2_I4(r, r, 0, 1, r, r)); =20 @@ -2426,13 +2425,12 @@ static void query_s390_facilities(void) /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this is present on all 64-bit systems, but let's check for it anyway. */ if (hwcap & HWCAP_S390_STFLE) { - register int r0 __asm__("0"); - register void *r1 __asm__("1"); + register int r0 __asm__("0") =3D ARRAY_SIZE(s390_facilities) - 1; + register void *r1 __asm__("1") =3D s390_facilities; =20 /* stfle 0(%r1) */ - r1 =3D &s390_facilities; asm volatile(".word 0xb2b0,0x1000" - : "=3Dr"(r0) : "0"(0), "r"(r1) : "memory", "cc"); + : "=3Dr"(r0) : "r"(r0), "r"(r1) : "memory", "cc"); } } =20 --=20 2.25.1 From nobody Tue Nov 18 19:47:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612755613; cv=none; d=zohomail.com; s=zohoarc; b=nqJbwsb6DNyl3ayulhQgx5SN8pzTdoZs3Y9fRY619hgLnx+QIWYifTc8n0anrPsp8Hrplh9YGKazlUyHlwmToWXwppgYCFFET0CVEdoTXljr8LjVIKYaSIDh+UyOjPuqxCw7cqwl6Zh5r3AeGy64usZYH6XUzjQsrMAQWV/WVSM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612755613; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SRq7hg6Vj1nHDtcJzgW8chIU3xuJIIPY1S3vOosE/88=; b=dyWEknpUL7Nn7eDsclJEUD5QiJUnkfHDrqKr2/mVOshlkIOWDuv5lo429U+JAiWdi2Tv0qUd2B8uOBi0qZ77yOYfTNWrBBjuvd234p3FT+s0nwzDE/k9vKhoN9i7+TSPvIxBJnTfIH63xwSt1D6Hn3NXy4VLu4L2jsU4axgla4k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612755613641952.1286011593163; Sun, 7 Feb 2021 19:40:13 -0800 (PST) Received: from localhost ([::1]:59918 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8xPI-00084M-86 for importer@patchew.org; Sun, 07 Feb 2021 22:40:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60116) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wdr-00080d-Py for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:51:12 -0500 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:46713) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wdp-0001Jb-AO for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:51:11 -0500 Received: by mail-pg1-x533.google.com with SMTP id r38so9241049pgk.13 for ; Sun, 07 Feb 2021 18:51:07 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SRq7hg6Vj1nHDtcJzgW8chIU3xuJIIPY1S3vOosE/88=; b=eaHP7OIBxnormXq1xbNgkGqC2uLhOa+WJFD6d8BZ9+b8mfJgUgCdb2bJHJQRulmvVc dkD0twko/i0hFfFUv+dDR56sGZGe0x2ZxrF66mBAGfO+elvQnd5L+P81ymb7kdkEYqPr 1eRYFOlIqHhoIHMI8I5HHtR1NxGHgGT8dVtJ08ywdQCGSRPsPL3ljrYAA4QmG2Ksok1h 8Jky31QstuwnC9gyBFcRPfl6oA0ZFjKHWuo5ga/dH53BiLsbAcAL4T+GWUo8wJudNUxp T3mTJ8H+/hbvQDRUF/VdIcM/3ZGSGHH5s+E5YmlxaJzMX02bYgM9knAJbuo5nr3fb8l8 a7ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SRq7hg6Vj1nHDtcJzgW8chIU3xuJIIPY1S3vOosE/88=; b=HDzeKncEYP1kRsdpmrlJl5/fb6qm4nCRS8Ivt4RlHNzhZqw5omGzt0rgil35yXKmNg V4BQKcXZxvQ/pL/huShM8Rbv21Qixu///n/cB9OpUpXEvdvG/MjIqhQ3aBe9yA9Y1sJU uNYnfy/hznb5nmvK015p32cm7Y7M67uAYUZ94+DRGqcdjgt1qsyGtYQ+OF3tf4NXBzmu ifW7oPutGNIC0sAXt/oesC6uwvW3OlfGdc1T+y8mjdoJ0B2tEGRf5MfYc6IV7E7d5H5y r5UlEQYTPJnGaniVHchdhj0/oLRFK4zGmYDG9X7+zaGyBdYMbZhDo1OAVVHuYhU+CAog bxyw== X-Gm-Message-State: AOAM532WfnkGTVGQ9JlUjJxlAfo3yWPiQeImqVUVLnr/fFrvAbFcHbyq OxsYIixbSeRB2Pj3w/+DavqINwfEaYchhw== X-Google-Smtp-Source: ABdhPJzLC+7WgU+hYvklHWBlPFi9xpnQYN5cIF4KF+S71dedaVtef0O/YBTp0rGo/POzqPOUWZ85/A== X-Received: by 2002:a63:a804:: with SMTP id o4mr15487987pgf.67.1612752666724; Sun, 07 Feb 2021 18:51:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 03/16] tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg Date: Sun, 7 Feb 2021 18:50:48 -0800 Message-Id: <20210208025101.271726-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) They are rightly values in the same enumeration. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index c612d24803..3a701d9256 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -29,22 +29,13 @@ #define TCG_TARGET_TLB_DISPLACEMENT_BITS 19 =20 typedef enum TCGReg { - TCG_REG_R0 =3D 0, - TCG_REG_R1, - TCG_REG_R2, - TCG_REG_R3, - TCG_REG_R4, - TCG_REG_R5, - TCG_REG_R6, - TCG_REG_R7, - TCG_REG_R8, - TCG_REG_R9, - TCG_REG_R10, - TCG_REG_R11, - TCG_REG_R12, - TCG_REG_R13, - TCG_REG_R14, - TCG_REG_R15 + TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, + TCG_REG_R4, TCG_REG_R5, TCG_REG_R6, TCG_REG_R7, + TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11, + TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, + + TCG_AREG0 =3D TCG_REG_R10, + TCG_REG_CALL_STACK =3D TCG_REG_R15 } TCGReg; =20 #define TCG_TARGET_NB_REGS 16 @@ -136,7 +127,6 @@ extern uint64_t s390_facilities[1]; #define TCG_TARGET_HAS_mulsh_i64 0 =20 /* used for function call generation */ -#define TCG_REG_CALL_STACK TCG_REG_R15 #define TCG_TARGET_STACK_ALIGN 8 #define TCG_TARGET_CALL_STACK_OFFSET 160 =20 @@ -145,10 +135,6 @@ extern uint64_t s390_facilities[1]; =20 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 -enum { - TCG_AREG0 =3D TCG_REG_R10, -}; - static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jm= p_rx, uintptr_t jmp_rw, uintptr_t ad= dr) { --=20 2.25.1 From nobody Tue Nov 18 19:47:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612757331; cv=none; d=zohomail.com; s=zohoarc; b=KYnh//VZU2BfH/Hhp6ZJH6Tu76P2Lf6U+5OSzfhvbep3WApcwDpDlsS0i7rP7EHjBFfzc8dpxsl58/DIkv5u9aKmGohYQSUEe76l7voyjcBAznErIeSV16GmC19G7rS+/qXPJkTzQF8RW59vdkAOzgvJ8JD/z6ZKEhPeGN53TTM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612757331; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1ZP9rcz+bqyMzUuxz4tto926+fSJHcTzu1HPZk7aj5Q=; b=VaDfDPB1FDAu6Y3cj96PRFgJZJs7As7TELgSGa5xi77urwzRsYDyWscBtXReexkq5SYtAWW/BVR/2+esfyGi3inns3ze+D/K9yrOo4FzvFIbZJC7j6u0TXuYo6FRMdEA0m5BdpfOtjEq0EuqPo9FuxA/ZGRNoyRFoeDVaVTm3Fw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612757331257809.1978274271971; Sun, 7 Feb 2021 20:08:51 -0800 (PST) Received: from localhost ([::1]:46540 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8xqz-0005Z0-RC for importer@patchew.org; Sun, 07 Feb 2021 23:08:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60168) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wdu-000820-0y for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:51:14 -0500 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:34509) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wdp-0001KS-EE for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:51:13 -0500 Received: by mail-pg1-x52a.google.com with SMTP id o7so9294426pgl.1 for ; Sun, 07 Feb 2021 18:51:09 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1ZP9rcz+bqyMzUuxz4tto926+fSJHcTzu1HPZk7aj5Q=; b=qFQIsHnX2XBQ/I+EIOijOOYayewJGJAnDrRh5pxCVLkYFFbj7jouLNby1H7B8ZvEtu 1D8bdzLLGKhggquj+Pn2lOJKlL5zco3UD33e9wO3xuh0BpateCqDtYxfPTiMIYaPnIVq mqGeY6sAE3zWBq8J5vHrgrsTH63xbDzdZbBKEijR/ZYCotP4cimozYOOjFQCLu3sHdEX /eGoDDlw0l/FvdUnH+DjLXo+TLBYv+x8Hao6Z+gyqPLBoZ/bL2X+Oi/25rxg0bi4IDot 6oaNXchbTiKlWbrtnnth8NxNXLv4gT8LMp3uOMs42huGaSb8ULISUdOiEiUlLivvMYV9 ZYiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1ZP9rcz+bqyMzUuxz4tto926+fSJHcTzu1HPZk7aj5Q=; b=lQXFJzJ2/c4B4yvXmJ6hMSFMp6o4L42eCZkXfR2k136wGCeusD/v5BWajVG1ftHXIU hWWPL75GpnXFV1Au4cLWKBpj2iThE458hvLIqZSYv+uQ3/2g6jknYXy+ZDfDL+vXCIZt n/N6wf5KgZHXrTT4HlVHP+3Ieg18QmjenqF27nsvU68Ra8GaUp1DWmidMy3PMQnGQyxx xWq/0qtauhXPDU56wODEzEtyFaWsyN6rHsBtC+5q3Gp/4y2KxwTyGopkM4usziGjTvfP BpOvkuyipWK8bMi0rT477BGb5F/jtB0WuxijkZ7p5Xv1n0YMx3pBQfGc7N7kTIFcI4tc LjsA== X-Gm-Message-State: AOAM533pzLe/1/HHD5y+P8X8Cy0ZXrBUQMNBUWY2q1WN9e6N+YyIr66E JjL5BM4y2lSInoq8zgPpTgEWz/5wxdL5bw== X-Google-Smtp-Source: ABdhPJwNa19H8FAbVjo9i/ge/smU8RiSztt8kxPoiipWDvUls8vwbWzIM5nCfYgyOra0AQ5CfsPT4w== X-Received: by 2002:a63:e10b:: with SMTP id z11mr14946391pgh.40.1612752668065; Sun, 07 Feb 2021 18:51:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 04/16] tcg/s390x: Add host vector framework Date: Sun, 7 Feb 2021 18:50:49 -0800 Message-Id: <20210208025101.271726-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Add registers and function stubs. The functionality is disabled via squashing s390_facilities[2] to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 4 + tcg/s390x/tcg-target-con-str.h | 1 + tcg/s390x/tcg-target.h | 35 ++++++++- tcg/s390x/tcg-target.opc.h | 12 +++ tcg/s390x/tcg-target.c.inc | 137 ++++++++++++++++++++++++++++++++- 5 files changed, 184 insertions(+), 5 deletions(-) create mode 100644 tcg/s390x/tcg-target.opc.h diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 31985e4903..ce9432cfe3 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -13,13 +13,17 @@ C_O0_I1(r) C_O0_I2(L, L) C_O0_I2(r, r) C_O0_I2(r, ri) +C_O0_I2(v, r) C_O1_I1(r, L) C_O1_I1(r, r) +C_O1_I1(v, r) +C_O1_I1(v, vr) C_O1_I2(r, 0, ri) C_O1_I2(r, 0, rI) C_O1_I2(r, 0, rJ) C_O1_I2(r, r, ri) C_O1_I2(r, rZ, r) +C_O1_I2(v, v, v) C_O1_I4(r, r, ri, r, 0) C_O1_I4(r, r, ri, rI, 0) C_O2_I2(b, a, 0, r) diff --git a/tcg/s390x/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h index 892d8f8c06..8bb0358ae5 100644 --- a/tcg/s390x/tcg-target-con-str.h +++ b/tcg/s390x/tcg-target-con-str.h @@ -10,6 +10,7 @@ */ REGS('r', ALL_GENERAL_REGS) REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) +REGS('v', ALL_VECTOR_REGS) /* * A (single) even/odd pair for division. * TODO: Add something to the register allocator to allow diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 3a701d9256..e8659bf576 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -34,11 +34,20 @@ typedef enum TCGReg { TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11, TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, =20 + TCG_REG_V0 =3D 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, + TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, + TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, + TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, + TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, + TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, + TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, + TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, + TCG_AREG0 =3D TCG_REG_R10, TCG_REG_CALL_STACK =3D TCG_REG_R15 } TCGReg; =20 -#define TCG_TARGET_NB_REGS 16 +#define TCG_TARGET_NB_REGS 64 =20 /* A list of relevant facilities used by this translator. Some of these are required for proper operation, and these are checked at startup. */ @@ -51,8 +60,9 @@ typedef enum TCGReg { #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND #define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND #define FACILITY_LOAD_ON_COND2 53 +#define FACILITY_VECTOR 129 =20 -extern uint64_t s390_facilities[1]; +extern uint64_t s390_facilities[3]; =20 #define HAVE_FACILITY(X) \ ((s390_facilities[FACILITY_##X / 64] >> (63 - FACILITY_##X % 64)) & 1) @@ -126,6 +136,27 @@ extern uint64_t s390_facilities[1]; #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 =20 +#define TCG_TARGET_HAS_v64 HAVE_FACILITY(VECTOR) +#define TCG_TARGET_HAS_v128 HAVE_FACILITY(VECTOR) +#define TCG_TARGET_HAS_v256 0 + +#define TCG_TARGET_HAS_andc_vec 0 +#define TCG_TARGET_HAS_orc_vec 0 +#define TCG_TARGET_HAS_not_vec 0 +#define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rots_vec 0 +#define TCG_TARGET_HAS_rotv_vec 0 +#define TCG_TARGET_HAS_shi_vec 0 +#define TCG_TARGET_HAS_shs_vec 0 +#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_cmpsel_vec 0 + /* used for function call generation */ #define TCG_TARGET_STACK_ALIGN 8 #define TCG_TARGET_CALL_STACK_OFFSET 160 diff --git a/tcg/s390x/tcg-target.opc.h b/tcg/s390x/tcg-target.opc.h new file mode 100644 index 0000000000..67afc82a93 --- /dev/null +++ b/tcg/s390x/tcg-target.opc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021 Linaro + * + * This work is licensed under the terms of the GNU GPL, version 2 or + * (at your option) any later version. + * + * See the COPYING file in the top-level directory for details. + * + * Target-specific opcodes for host vector expansion. These will be + * emitted by tcg_expand_vec_op. For those familiar with GCC internals, + * consider these to be UNSPEC with names. + */ diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 3b632d8b24..4656efea83 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -43,6 +43,8 @@ #define TCG_CT_CONST_ZERO 0x800 =20 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16) +#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) + /* * For softmmu, we need to avoid conflicts with the first 3 * argument registers to perform the tlb lookup, and to call @@ -268,8 +270,13 @@ typedef enum S390Opcode { =20 #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { - "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", - "%r8", "%r9", "%r10" "%r11" "%r12" "%r13" "%r14" "%r15" + "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", + "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", + "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", + "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", + "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", }; #endif =20 @@ -295,6 +302,32 @@ static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_R4, TCG_REG_R3, TCG_REG_R2, + + /* V8-V15 are call saved, and omitted. */ + TCG_REG_V0, + TCG_REG_V1, + TCG_REG_V2, + TCG_REG_V3, + TCG_REG_V4, + TCG_REG_V5, + TCG_REG_V6, + TCG_REG_V7, + TCG_REG_V16, + TCG_REG_V17, + TCG_REG_V18, + TCG_REG_V19, + TCG_REG_V20, + TCG_REG_V21, + TCG_REG_V22, + TCG_REG_V23, + TCG_REG_V24, + TCG_REG_V25, + TCG_REG_V26, + TCG_REG_V27, + TCG_REG_V28, + TCG_REG_V29, + TCG_REG_V30, + TCG_REG_V31, }; =20 static const int tcg_target_call_iarg_regs[] =3D { @@ -377,7 +410,7 @@ static void * const qemu_st_helpers[16] =3D { #endif =20 static const tcg_insn_unit *tb_ret_addr; -uint64_t s390_facilities[1]; +uint64_t s390_facilities[3]; =20 static bool patch_reloc(tcg_insn_unit *src_rw, int type, intptr_t value, intptr_t addend) @@ -2273,6 +2306,42 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, } } =20 +static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, TCGReg src) +{ + g_assert_not_reached(); +} + +static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, TCGReg base, intptr_t offset) +{ + g_assert_not_reached(); +} + +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, int64_t val) +{ + g_assert_not_reached(); +} + +static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg *args, const int *const_args) +{ + g_assert_not_reached(); +} + +int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) +{ + return 0; +} + +void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, + TCGArg a0, ...) +{ + g_assert_not_reached(); +} + static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { switch (op) { @@ -2413,11 +2482,34 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) ? C_O2_I4(r, r, 0, 1, rA, r) : C_O2_I4(r, r, 0, 1, r, r)); =20 + case INDEX_op_st_vec: + return C_O0_I2(v, r); + case INDEX_op_ld_vec: + case INDEX_op_dupm_vec: + return C_O1_I1(v, r); + case INDEX_op_dup_vec: + return C_O1_I1(v, vr); + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_cmp_vec: + return C_O1_I2(v, v, v); + default: g_assert_not_reached(); } } =20 +/* + * Mainline glibc added HWCAP_S390_VX before it was kernel abi. + * Some distros have fixed this up locally, others have not. + */ +#ifndef HWCAP_S390_VXRS +#define HWCAP_S390_VXRS 2048 +#endif + static void query_s390_facilities(void) { unsigned long hwcap =3D qemu_getauxval(AT_HWCAP); @@ -2432,6 +2524,16 @@ static void query_s390_facilities(void) asm volatile(".word 0xb2b0,0x1000" : "=3Dr"(r0) : "r"(r0), "r"(r1) : "memory", "cc"); } + + /* + * Use of vector registers requires os support beyond the facility bit. + * If the kernel does not advertise support, disable the facility bits. + * There is nothing else we currently care about in the 3rd word, so + * disable VECTOR with one store. + */ + if (1 || !(hwcap & HWCAP_S390_VXRS)) { + s390_facilities[2] =3D 0; + } } =20 static void tcg_target_init(TCGContext *s) @@ -2440,6 +2542,10 @@ static void tcg_target_init(TCGContext *s) =20 tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffff; tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffff; + if (HAVE_FACILITY(VECTOR)) { + tcg_target_available_regs[TCG_TYPE_V64] =3D 0xffffffff00000000ull; + tcg_target_available_regs[TCG_TYPE_V128] =3D 0xffffffff00000000ull; + } =20 tcg_target_call_clobber_regs =3D 0; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); @@ -2454,6 +2560,31 @@ static void tcg_target_init(TCGContext *s) /* The return register can be considered call-clobbered. */ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); =20 + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V20); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V21); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V22); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V23); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V24); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V25); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V26); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V27); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V28); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V29); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V30); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V31); + s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* XXX many insns can't be used with R0, so we better avoid it for now= */ --=20 2.25.1 From nobody Tue Nov 18 19:47:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612755785; cv=none; d=zohomail.com; s=zohoarc; b=erMN/E8Beno1QqCoEkxnwAwfFQwJIHNWv6oug345JcENU7JyYll8+MyB2Nff6GgUWswOulln+IdT5KMCn26lkoscdSq/I4vKnZhiZV8/jWhzrXaPA16ypSzs/x/PpftmrNcxg3yMYv0ISqV/B5LL3Sp0pcRIzdALlzEHQebAddY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 117 +++++++++++++++++++++++++++++++++---- 1 file changed, 105 insertions(+), 12 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 4656efea83..df10ee0feb 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -265,6 +265,12 @@ typedef enum S390Opcode { RX_STC =3D 0x42, RX_STH =3D 0x40, =20 + VRX_VL =3D 0xe706, + VRX_VLLEZ =3D 0xe704, + VRX_VST =3D 0xe70e, + VRX_VSTEF =3D 0xe70b, + VRX_VSTEG =3D 0xe70a, + NOP =3D 0x0707, } S390Opcode; =20 @@ -532,6 +538,26 @@ static void tcg_out_insn_RSY(TCGContext *s, S390Opcode= op, TCGReg r1, #define tcg_out_insn_RX tcg_out_insn_RS #define tcg_out_insn_RXY tcg_out_insn_RSY =20 +static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) +{ + return ((v1 & 16) << (7 - 3)) + | ((v2 & 16) << (6 - 3)) + | ((v3 & 16) << (5 - 3)) + | ((v4 & 16) << (4 - 3)); +} + +static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1, + TCGReg b2, TCGReg x2, intptr_t d2, int m3) +{ + tcg_debug_assert(v1 >=3D TCG_REG_V0 && v1 <=3D TCG_REG_V31); + tcg_debug_assert(d2 >=3D 0 && d2 <=3D 0xfff); + tcg_debug_assert(x2 <=3D TCG_REG_R15); + tcg_debug_assert(b2 <=3D TCG_REG_R15); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | x2); + tcg_out16(s, (b2 << 12) | d2); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); +} + /* Emit an opcode with "type-checking" of the format. */ #define tcg_out_insn(S, FMT, OP, ...) \ glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__) @@ -708,25 +734,92 @@ static void tcg_out_mem(TCGContext *s, S390Opcode opc= _rx, S390Opcode opc_rxy, } } =20 +static void tcg_out_vrx_mem(TCGContext *s, S390Opcode opc_vrx, + TCGReg data, TCGReg base, TCGReg index, + tcg_target_long ofs, int m3) +{ + if (ofs < 0 || ofs >=3D 0x1000) { + if (ofs >=3D -0x80000 && ofs < 0x80000) { + tcg_out_insn(s, RXY, LAY, TCG_TMP0, base, index, ofs); + base =3D TCG_TMP0; + index =3D TCG_REG_NONE; + ofs =3D 0; + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs); + if (index !=3D TCG_REG_NONE) { + tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); + } + index =3D TCG_TMP0; + ofs =3D 0; + } + } + tcg_out_insn_VRX(s, opc_vrx, data, base, index, ofs, m3); +} =20 /* load data without address translation or endianness conversion */ -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data, - TCGReg base, intptr_t ofs) +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data, + TCGReg base, intptr_t ofs) { - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs); - } else { - tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs); + switch (type) { + case TCG_TYPE_I32: + if (likely(data < 16)) { + tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs); + break; + } + tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_32= ); + break; + + case TCG_TYPE_I64: + if (likely(data < 16)) { + tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs); + break; + } + /* fallthru */ + + case TCG_TYPE_V64: + tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_64= ); + break; + + case TCG_TYPE_V128: + /* Hint quadword aligned. */ + tcg_out_vrx_mem(s, VRX_VL, data, base, TCG_REG_NONE, ofs, 4); + break; + + default: + g_assert_not_reached(); } } =20 -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg data, - TCGReg base, intptr_t ofs) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg data, + TCGReg base, intptr_t ofs) { - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs); - } else { - tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs); + switch (type) { + case TCG_TYPE_I32: + if (likely(data < 16)) { + tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs); + } else { + tcg_out_vrx_mem(s, VRX_VSTEF, data, base, TCG_REG_NONE, ofs, 1= ); + } + break; + + case TCG_TYPE_I64: + if (likely(data < 16)) { + tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs); + break; + } + /* fallthru */ + + case TCG_TYPE_V64: + tcg_out_vrx_mem(s, VRX_VSTEG, data, base, TCG_REG_NONE, ofs, 0); + break; + + case TCG_TYPE_V128: + /* Hint quadword aligned. */ + tcg_out_vrx_mem(s, VRX_VST, data, base, TCG_REG_NONE, ofs, 4); + break; + + default: + g_assert_not_reached(); } } =20 --=20 2.25.1 From nobody Tue Nov 18 19:47:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612755400; cv=none; d=zohomail.com; s=zohoarc; b=ch+lxcZfOny/WQ5NFYd7pE7wWO5egku3xFu9nZV3RMouQv7xNKOO+ZOSWwriI1h9QM0j0TsGTD4vxVKU6czdaFizoIsmiMN+wK4dJvOWiIj9Vnr/vBWA6Kpp2w8ZbQkwzvS1N7cyrcLS7/f8mPe2NiqoywecCGmvMbeZ/RqdulY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612755400; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 72 +++++++++++++++++++++++++++++++++++--- 1 file changed, 68 insertions(+), 4 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index df10ee0feb..fdf7475b2d 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -265,6 +265,11 @@ typedef enum S390Opcode { RX_STC =3D 0x42, RX_STH =3D 0x40, =20 + VRRa_VLR =3D 0xe756, + + VRSb_VLVG =3D 0xe722, + VRSc_VLGV =3D 0xe721, + VRX_VL =3D 0xe706, VRX_VLLEZ =3D 0xe704, VRX_VST =3D 0xe70e, @@ -546,6 +551,39 @@ static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg= v4) | ((v4 & 16) << (4 - 3)); } =20 +static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, + TCGReg v1, TCGReg v2, int m3) +{ + tcg_debug_assert(v1 >=3D TCG_REG_V0 && v1 <=3D TCG_REG_V31); + tcg_debug_assert(v2 >=3D TCG_REG_V0 && v2 <=3D TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v2 & 15)); + tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12)); +} + +static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, + intptr_t d2, TCGReg b2, TCGReg r3, int m4) +{ + tcg_debug_assert(v1 >=3D TCG_REG_V0 && v1 <=3D TCG_REG_V31); + tcg_debug_assert(d2 >=3D 0 && d2 <=3D 0xfff); + tcg_debug_assert(b2 <=3D TCG_REG_R15); + tcg_debug_assert(r3 <=3D TCG_REG_R15); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | r3); + tcg_out16(s, b2 << 12 | d2); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); +} + +static void tcg_out_insn_VRSc(TCGContext *s, S390Opcode op, TCGReg r1, + intptr_t d2, TCGReg b2, TCGReg v3, int m4) +{ + tcg_debug_assert(r1 <=3D TCG_REG_R15); + tcg_debug_assert(d2 >=3D 0 && d2 <=3D 0xfff); + tcg_debug_assert(b2 <=3D TCG_REG_R15); + tcg_debug_assert(v3 >=3D TCG_REG_V0 && v3 <=3D TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | (r1 << 4) | (v3 & 15)); + tcg_out16(s, b2 << 12 | d2); + tcg_out16(s, (op & 0x00ff) | RXB(0, 0, v3, 0) | (m4 << 12)); +} + static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1, TCGReg b2, TCGReg x2, intptr_t d2, int m3) { @@ -579,12 +617,38 @@ static void tcg_out_sh32(TCGContext* s, S390Opcode op= , TCGReg dest, =20 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg sr= c) { - if (src !=3D dst) { - if (type =3D=3D TCG_TYPE_I32) { + if (src =3D=3D dst) { + return true; + } + switch (type) { + case TCG_TYPE_I32: + if (likely(dst < 16 && src < 16)) { tcg_out_insn(s, RR, LR, dst, src); - } else { - tcg_out_insn(s, RRE, LGR, dst, src); + break; } + /* fallthru */ + + case TCG_TYPE_I64: + if (likely(dst < 16)) { + if (likely(src < 16)) { + tcg_out_insn(s, RRE, LGR, dst, src); + } else { + tcg_out_insn(s, VRSc, VLGV, dst, 0, 0, src, 3); + } + break; + } else if (src < 16) { + tcg_out_insn(s, VRSb, VLVG, dst, 0, 0, src, 3); + break; + } + /* fallthru */ + + case TCG_TYPE_V64: + case TCG_TYPE_V128: + tcg_out_insn(s, VRRa, VLR, dst, src, 0); + break; + + default: + g_assert_not_reached(); } return true; } --=20 2.25.1 From nobody Tue Nov 18 19:47:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612755195; cv=none; d=zohomail.com; s=zohoarc; b=hJRLb/71imPPQ+4m+/sgN3iSOnnzHzAYw6ocZU7NJwQ2O0wjv2b7wxK/lJ4KPc9dJCRklMXzfJsMqoyDB6hZSAYFKe8BpuFqJ874bjeGzOjvUuNmyVg9Sk4t0lYvyVzjr7J/zW9c/evTZCzUuHse+VOA2yX4WTMMcEdNh3Z2qv4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612755195; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 122 ++++++++++++++++++++++++++++++++++++- 1 file changed, 119 insertions(+), 3 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index fdf7475b2d..01118d9993 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -265,13 +265,20 @@ typedef enum S390Opcode { RX_STC =3D 0x42, RX_STH =3D 0x40, =20 + VRIa_VGBM =3D 0xe744, + VRIa_VREPI =3D 0xe745, + VRIb_VGM =3D 0xe746, + VRIc_VREP =3D 0xe74d, + VRRa_VLR =3D 0xe756, + VRRf_VLVGP =3D 0xe762, =20 VRSb_VLVG =3D 0xe722, VRSc_VLGV =3D 0xe721, =20 VRX_VL =3D 0xe706, VRX_VLLEZ =3D 0xe704, + VRX_VLREP =3D 0xe705, VRX_VST =3D 0xe70e, VRX_VSTEF =3D 0xe70b, VRX_VSTEG =3D 0xe70a, @@ -551,6 +558,34 @@ static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg= v4) | ((v4 & 16) << (4 - 3)); } =20 +static void tcg_out_insn_VRIa(TCGContext *s, S390Opcode op, + TCGReg v1, uint16_t i2, int m3) +{ + tcg_debug_assert(v1 >=3D TCG_REG_V0 && v1 <=3D TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4)); + tcg_out16(s, i2); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); +} + +static void tcg_out_insn_VRIb(TCGContext *s, S390Opcode op, + TCGReg v1, uint8_t i2, uint8_t i3, int m4) +{ + tcg_debug_assert(v1 >=3D TCG_REG_V0 && v1 <=3D TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4)); + tcg_out16(s, (i2 << 8) | (i3 & 0xff)); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); +} + +static void tcg_out_insn_VRIc(TCGContext *s, S390Opcode op, + TCGReg v1, uint16_t i2, TCGReg v3, int m4) +{ + tcg_debug_assert(v1 >=3D TCG_REG_V0 && v1 <=3D TCG_REG_V31); + tcg_debug_assert(v3 >=3D TCG_REG_V0 && v3 <=3D TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v3 & 15)); + tcg_out16(s, i2); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12)); +} + static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, TCGReg v1, TCGReg v2, int m3) { @@ -560,6 +595,17 @@ static void tcg_out_insn_VRRa(TCGContext *s, S390Opcod= e op, tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12)); } =20 +static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, + TCGReg v1, TCGReg r2, TCGReg r3) +{ + tcg_debug_assert(v1 >=3D TCG_REG_V0 && v1 <=3D TCG_REG_V31); + tcg_debug_assert(r2 <=3D TCG_REG_R15); + tcg_debug_assert(r3 <=3D TCG_REG_R15); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | r2); + tcg_out16(s, r3 << 12); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0)); +} + static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, intptr_t d2, TCGReg b2, TCGReg r3, int m4) { @@ -2466,19 +2512,89 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src) { - g_assert_not_reached(); + if (src < 16) { + /* Replicate general register into two MO_64. */ + tcg_out_insn(s, VRRf, VLVGP, dst, src, src); + if (vece =3D=3D MO_64) { + return true; + } + } + + /* + * Recall that the "standard" integer, within a vector, is the + * rightmost element of the leftmost doubleword, a-la VLLEZ. + */ + tcg_out_insn(s, VRIc, VREP, dst, (8 >> vece) - 1, src, vece); + return true; } =20 static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg base, intptr_t offset) { - g_assert_not_reached(); + tcg_out_vrx_mem(s, VRX_VLREP, dst, base, TCG_REG_NONE, offset, vece); + return true; } =20 static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, int64_t val) { - g_assert_not_reached(); + int i, mask, msb, lsb; + + /* Look for int16_t elements. */ + if (vece <=3D MO_16 || + (vece =3D=3D MO_32 ? (int32_t)val : val) =3D=3D (int16_t)val) { + tcg_out_insn(s, VRIa, VREPI, dst, val, vece); + return; + } + + /* Look for bit masks. */ + if (vece =3D=3D MO_32) { + if (risbg_mask((int32_t)val)) { + /* Handle wraparound by swapping msb and lsb. */ + if ((val & 0x80000001u) =3D=3D 0x80000001u) { + msb =3D 32 - ctz32(~val); + lsb =3D clz32(~val) - 1; + } else { + msb =3D clz32(val); + lsb =3D 31 - ctz32(val); + } + tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_32); + return; + } + } else { + if (risbg_mask(val)) { + /* Handle wraparound by swapping msb and lsb. */ + if ((val & 0x8000000000000001ull) =3D=3D 0x8000000000000001ull= ) { + /* Handle wraparound by swapping msb and lsb. */ + msb =3D 64 - ctz64(~val); + lsb =3D clz64(~val) - 1; + } else { + msb =3D clz64(val); + lsb =3D 63 - ctz64(val); + } + tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_64); + return; + } + } + + /* Look for all bytes 0x00 or 0xff. */ + for (i =3D mask =3D 0; i < 8; i++) { + uint8_t byte =3D val >> (i * 8); + if (byte =3D=3D 0xff) { + mask |=3D 1 << i; + } else if (byte !=3D 0) { + break; + } + } + if (i =3D=3D 8) { + tcg_out_insn(s, VRIa, VGBM, dst, mask * 0x0101, 0); + return; + } + + /* Otherwise, stuff it in the constant pool. */ + tcg_out_insn(s, RIL, LARL, TCG_TMP0, 0); + new_pool_label(s, val, R_390_PC32DBL, s->code_ptr - 2, 2); + tcg_out_insn(s, VRX, VLREP, dst, TCG_TMP0, TCG_REG_NONE, 0, MO_64); } =20 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, --=20 2.25.1 From nobody Tue Nov 18 19:47:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612755841; cv=none; d=zohomail.com; s=zohoarc; b=ek/jzJWo1zB4lxeY3ZiO/jtSB5+wDwNk5sqbLDPksVuC3mwrG1n+9lDv47+eef89xN2XVeV5YzW3RmYrWf6BHcYjomuxLoU3iIOWVWDkGzHVovmtyprNQWyGEkD9zJtXmU/InARMVZXC5gsIxb9MmPCP41Mus60gWrz6+WebhPM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612755841; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NFbhYgQUsjaFE+5Iajc9BElBoc4cCgBaEW1XyF0baro=; b=dL3S+BgqwQluN4B5TdjXsNpK7Kv8WxGjYdCU5kEbzsjgV9fZuE80TvIGQYkWFKmTLSonFLf1ZOsmVFZYQHzaBEf7s49OfRhUEjpUpPHP77CpzvWVzjGffog7stD6g6j0ZiUAJhCJ4OMqJqoqWSBTvLbWC6avHQJxC+zkUEc6b4I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612755841113960.7943659467335; Sun, 7 Feb 2021 19:44:01 -0800 (PST) Received: from localhost ([::1]:43058 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8xSx-0004OX-TJ for importer@patchew.org; Sun, 07 Feb 2021 22:43:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60216) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wdw-00089u-V6 for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:51:16 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:36518) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wdt-0001M0-Oi for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:51:16 -0500 Received: by mail-pj1-x1033.google.com with SMTP id gx20so7956526pjb.1 for ; Sun, 07 Feb 2021 18:51:13 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NFbhYgQUsjaFE+5Iajc9BElBoc4cCgBaEW1XyF0baro=; b=zRpQYT2o2A1pq9r2ImC4wY0dBkhTjV4OZ4w8oarRjhnTO8OwXoaAp+g/u3f0G9gfu6 1OXeu3QewiM2eL1SU4HFgd5J9xO2yrAMskoOtc1MUJKrshoy7f/l+/G+qRHkMC/mhzBN sfDGoXPU5PeN1E1HaJB5917J5Jt3Y9pWxiIoHhNunq0a7yE3aLaKv3uv+ntU1l9XcPfu qMKsbBsdGNQvUXNQF4be7GVoVk3YLIvCy644pHZRyv6GjSaFf3gxcEt5YlGrJ39ax5S8 nmiS2njKCenvVJrOxQhDH4qcgEqaKTGgDly2El+IYxTCri5EIc7/hkbHIhF2iz/UKpd2 FWmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NFbhYgQUsjaFE+5Iajc9BElBoc4cCgBaEW1XyF0baro=; b=DPBOi1wsTu27bjQSDcgBYB7ts3mNSB3ltm4KGRCwV7t3f8M+vB5aJ08a5Ydd/VfqWG no1VD8tmwwTsbZk8/kS4xmLkjtbmKgd5HaP8dJMetJ9+qrRnllCX+jABAM8nhHFbYM+S fRi3DwwGR8mRbrgQ85aLNsq+zVR91jih/9hGFWYye9tquu7nKhFmijqJdXvLTRZDQz5d dL4dVAYsGMASByKlBtLX2qppezsobPJEpBUotx6z6/xeLjLIMFZoyZ6pfDDqdAvMQ9wg hwxAf7ddtOdExPi5Ij67BYrMwLzBS7SclZQFXPI3kIEqpTMyEZU0hrFrbsRB4D0nLQH0 MiMA== X-Gm-Message-State: AOAM530qyt67WQjGv0jYlmzblhx9jJJsO3xGLMHFsGToDmemHkEqqDA5 ueqExdsDJEkeFKNtwrC7kFFZ7Pi4YuaY3Q== X-Google-Smtp-Source: ABdhPJzqVceXwLDB8FNADoy46GD+EyxG9/FDBelbtXwP8UGyDvopu+jIUV1SZs3jNKCN8Hliu5+05Q== X-Received: by 2002:a17:902:8c97:b029:e2:8c58:153f with SMTP id t23-20020a1709028c97b02900e28c58153fmr14277996plo.79.1612752672194; Sun, 07 Feb 2021 18:51:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 08/16] tcg/s390x: Implement minimal vector operations Date: Sun, 7 Feb 2021 18:50:53 -0800 Message-Id: <20210208025101.271726-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implementing add, sub, and, or, xor as the minimal set. This allows us to actually enable vectors in query_s390_facilities. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 154 ++++++++++++++++++++++++++++++++++++- 1 file changed, 150 insertions(+), 4 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 01118d9993..08315c7b05 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -271,6 +271,14 @@ typedef enum S390Opcode { VRIc_VREP =3D 0xe74d, =20 VRRa_VLR =3D 0xe756, + VRRc_VA =3D 0xe7f3, + VRRc_VCEQ =3D 0xe7f8, /* we leave the m5 cs field 0 */ + VRRc_VCH =3D 0xe7fb, /* " */ + VRRc_VCHL =3D 0xe7f9, /* " */ + VRRc_VN =3D 0xe768, + VRRc_VO =3D 0xe76a, + VRRc_VS =3D 0xe7f7, + VRRc_VX =3D 0xe76d, VRRf_VLVGP =3D 0xe762, =20 VRSb_VLVG =3D 0xe722, @@ -595,6 +603,17 @@ static void tcg_out_insn_VRRa(TCGContext *s, S390Opcod= e op, tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12)); } =20 +static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op, + TCGReg v1, TCGReg v2, TCGReg v3, int m4) +{ + tcg_debug_assert(v1 >=3D TCG_REG_V0 && v1 <=3D TCG_REG_V31); + tcg_debug_assert(v2 >=3D TCG_REG_V0 && v2 <=3D TCG_REG_V31); + tcg_debug_assert(v3 >=3D TCG_REG_V0 && v3 <=3D TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v2 & 15)); + tcg_out16(s, v3 << 12); + tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12)); +} + static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, TCGReg v1, TCGReg r2, TCGReg r3) { @@ -2601,18 +2620,145 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcod= e opc, unsigned vecl, unsigned vece, const TCGArg *args, const int *const_args) { - g_assert_not_reached(); + TCGType type =3D vecl + TCG_TYPE_V64; + TCGArg a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; + + switch (opc) { + case INDEX_op_ld_vec: + tcg_out_ld(s, type, a0, a1, a2); + break; + case INDEX_op_st_vec: + tcg_out_st(s, type, a0, a1, a2); + break; + case INDEX_op_dupm_vec: + tcg_out_dupm_vec(s, type, vece, a0, a1, a2); + break; + + case INDEX_op_add_vec: + tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece); + break; + case INDEX_op_sub_vec: + tcg_out_insn(s, VRRc, VS, a0, a1, a2, vece); + break; + case INDEX_op_and_vec: + tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0); + break; + case INDEX_op_or_vec: + tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0); + break; + case INDEX_op_xor_vec: + tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); + break; + + case INDEX_op_cmp_vec: + switch ((TCGCond)args[3]) { + case TCG_COND_EQ: + tcg_out_insn(s, VRRc, VCEQ, a0, a1, a2, vece); + break; + case TCG_COND_GT: + tcg_out_insn(s, VRRc, VCH, a0, a1, a2, vece); + break; + case TCG_COND_GTU: + tcg_out_insn(s, VRRc, VCHL, a0, a1, a2, vece); + break; + default: + g_assert_not_reached(); + } + break; + + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ + case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ + default: + g_assert_not_reached(); + } } =20 int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { - return 0; + switch (opc) { + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + return 1; + case INDEX_op_cmp_vec: + return -1; + default: + return 0; + } +} + +static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2, TCGCond cond) +{ + bool need_swap =3D false, need_inv =3D false; + + switch (cond) { + case TCG_COND_EQ: + case TCG_COND_GT: + case TCG_COND_GTU: + break; + case TCG_COND_NE: + case TCG_COND_LE: + case TCG_COND_LEU: + need_inv =3D true; + break; + case TCG_COND_LT: + case TCG_COND_LTU: + need_swap =3D true; + break; + case TCG_COND_GE: + case TCG_COND_GEU: + need_swap =3D need_inv =3D true; + break; + default: + g_assert_not_reached(); + } + + if (need_inv) { + cond =3D tcg_invert_cond(cond); + } + if (need_swap) { + TCGv_vec t1; + t1 =3D v1, v1 =3D v2, v2 =3D t1; + cond =3D tcg_swap_cond(cond); + } + + vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); + + return need_inv; +} + +static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2, TCGCond cond) +{ + if (expand_vec_cmp_noinv(type, vece, v0, v1, v2, cond)) { + tcg_gen_not_vec(vece, v0, v0); + } } =20 void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { - g_assert_not_reached(); + va_list va; + TCGv_vec v0, v1, v2; + + va_start(va, a0); + v0 =3D temp_tcgv_vec(arg_temp(a0)); + v1 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + v2 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + + switch (opc) { + case INDEX_op_cmp_vec: + expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); + break; + + default: + g_assert_not_reached(); + } + va_end(va); } =20 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) @@ -2804,7 +2950,7 @@ static void query_s390_facilities(void) * There is nothing else we currently care about in the 3rd word, so * disable VECTOR with one store. */ - if (1 || !(hwcap & HWCAP_S390_VXRS)) { + if (!(hwcap & HWCAP_S390_VXRS)) { s390_facilities[2] =3D 0; } } --=20 2.25.1 From nobody Tue Nov 18 19:47:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XkT/fAMq7fP12/ZBZ5fx+qLL9TNYOIdrJVXalZ7l+Is=; b=uf1pwVbep8YNkZbsl2Sir0qok6hEreYkSr4vHtfBVwZSSWsHyLqHpR1TYhY+3EjNRh iGx/atXFuuQBUfVfiuWhHUhJBzxvFVg7yBI90kj6BEVeIaq//WY316xPjelrYEYOBmqG Duv3/YSYFAcUXyKTOtmRgHFWr0iAx6SIZIrIug4MJzw1bkYLv3wZ9O5sa0VoMVWuo4PY L+12NYFnT/C3h7C0cCXpxO50jGSfBMxSKGb2lkpAksGIko+mpozFi4W+l1AFifVTbfMy R/PnWMCYTaoM5U6EgGYGNusNyqLJKDD7teTImKq0w2O+UulojNSBkU8TXBVR2K9FcpdS /IzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XkT/fAMq7fP12/ZBZ5fx+qLL9TNYOIdrJVXalZ7l+Is=; b=U26ioJQaLA906DYAOICEFSRm4CmphTUv+QaUK1cuKRoMh0hQUmEpQCz8d6GgzoADUr 8vyFmlDKePxfeXp+CyB2zaiFK4H9x0eTKWNUM7Ltw5Z4S04p094PFw4F6peOBoMYg9Vs 78Hz69HPbCNQ3DCzf1Wq1Xek6/KkxZgAli1jS0tVDYYjm6NvLdSRTN9djr+NPBCoJR2g 4u3H0qYl2SAWpqXpiC9gOrNCtAvN/ibUnVKiCI2TYa+M2I4IVE5Q4yKSh/Xwbs09jfv8 1NTYg/2Yh/MNaqaQGAKccV82mgZqdvYz1uZ9eyoeeegTNI2bngoyYMxvHKYgD1JnoLT7 pz4w== X-Gm-Message-State: AOAM530ZDMOCHUEckmY+P0VNGjZE+o4it+pBVDGhcd4hIUKBhD8w6XD2 yMxpW3ASmfkgXynlDSISj7RJuv8BoBhMpQ== X-Google-Smtp-Source: ABdhPJw/iewNzSZB8wXkab2aZ2oR9QRA1BTXIKzEwZJlct3UN3I6f+CM6WdDfEvY3JBduJ7lU8olkw== X-Received: by 2002:a17:902:a9ca:b029:e1:b3e:406c with SMTP id b10-20020a170902a9cab02900e10b3e406cmr14421443plr.84.1612752673469; Sun, 07 Feb 2021 18:51:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 09/16] tcg/s390x: Implement andc, orc, abs, neg, not vector operations Date: Sun, 7 Feb 2021 18:50:54 -0800 Message-Id: <20210208025101.271726-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These logical and arithmetic operations are optional but trivial. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 10 +++++----- tcg/s390x/tcg-target.c.inc | 34 +++++++++++++++++++++++++++++++++- 3 files changed, 39 insertions(+), 6 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index ce9432cfe3..cb953896d5 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -17,6 +17,7 @@ C_O0_I2(v, r) C_O1_I1(r, L) C_O1_I1(r, r) C_O1_I1(v, r) +C_O1_I1(v, v) C_O1_I1(v, vr) C_O1_I2(r, 0, ri) C_O1_I2(r, 0, rI) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index e8659bf576..dd11972ed2 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -140,11 +140,11 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_v128 HAVE_FACILITY(VECTOR) #define TCG_TARGET_HAS_v256 0 =20 -#define TCG_TARGET_HAS_andc_vec 0 -#define TCG_TARGET_HAS_orc_vec 0 -#define TCG_TARGET_HAS_not_vec 0 -#define TCG_TARGET_HAS_neg_vec 0 -#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_andc_vec 1 +#define TCG_TARGET_HAS_orc_vec 1 +#define TCG_TARGET_HAS_not_vec 1 +#define TCG_TARGET_HAS_neg_vec 1 +#define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rotv_vec 0 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 08315c7b05..23c25ff619 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -270,13 +270,18 @@ typedef enum S390Opcode { VRIb_VGM =3D 0xe746, VRIc_VREP =3D 0xe74d, =20 + VRRa_VLC =3D 0xe7de, + VRRa_VLP =3D 0xe7df, VRRa_VLR =3D 0xe756, VRRc_VA =3D 0xe7f3, VRRc_VCEQ =3D 0xe7f8, /* we leave the m5 cs field 0 */ VRRc_VCH =3D 0xe7fb, /* " */ VRRc_VCHL =3D 0xe7f9, /* " */ VRRc_VN =3D 0xe768, + VRRc_VNC =3D 0xe769, + VRRc_VNO =3D 0xe76b, VRRc_VO =3D 0xe76a, + VRRc_VOC =3D 0xe76f, VRRc_VS =3D 0xe7f7, VRRc_VX =3D 0xe76d, VRRf_VLVGP =3D 0xe762, @@ -2634,6 +2639,16 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, tcg_out_dupm_vec(s, type, vece, a0, a1, a2); break; =20 + case INDEX_op_abs_vec: + tcg_out_insn(s, VRRa, VLP, a0, a1, vece); + break; + case INDEX_op_neg_vec: + tcg_out_insn(s, VRRa, VLC, a0, a1, vece); + break; + case INDEX_op_not_vec: + tcg_out_insn(s, VRRc, VNO, a0, a1, a1, 0); + break; + case INDEX_op_add_vec: tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece); break; @@ -2643,9 +2658,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_and_vec: tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0); break; + case INDEX_op_andc_vec: + tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0); + break; case INDEX_op_or_vec: tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0); break; + case INDEX_op_orc_vec: + tcg_out_insn(s, VRRc, VOC, a0, a1, a2, 0); + break; case INDEX_op_xor_vec: tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); break; @@ -2676,10 +2697,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode= opc, int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { switch (opc) { + case INDEX_op_abs_vec: case INDEX_op_add_vec: - case INDEX_op_sub_vec: case INDEX_op_and_vec: + case INDEX_op_andc_vec: + case INDEX_op_neg_vec: + case INDEX_op_not_vec: case INDEX_op_or_vec: + case INDEX_op_orc_vec: + case INDEX_op_sub_vec: case INDEX_op_xor_vec: return 1; case INDEX_op_cmp_vec: @@ -2908,10 +2934,16 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) return C_O1_I1(v, r); case INDEX_op_dup_vec: return C_O1_I1(v, vr); + case INDEX_op_abs_vec: + case INDEX_op_neg_vec: + case INDEX_op_not_vec: + return C_O1_I1(v, v); case INDEX_op_add_vec: case INDEX_op_sub_vec: case INDEX_op_and_vec: + case INDEX_op_andc_vec: case INDEX_op_or_vec: + case INDEX_op_orc_vec: case INDEX_op_xor_vec: case INDEX_op_cmp_vec: return C_O1_I2(v, v, v); --=20 2.25.1 From nobody Tue Nov 18 19:47:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612757675; cv=none; d=zohomail.com; s=zohoarc; b=XXpQh3fqq1ANM7dqfSWpofFn1KT8qoRzNw8VdwZEh7b6a6PoqnhFDdfHP1k0P1n1kYLB/VgxFMHBXeQKD3faqgReaVL9PmRYETff/KgerOSPgdoP+Z+ygfol3f8jxTh1JD4T85P8aM2aoQSiuO5rTxzXETy0Egvo1sbdMcTdFcg= ARC-Message-Signature: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Z/Pfli3ijYHnlJT4Xorth9mXRem8tBvM4t0H60tFmKU=; b=v2HaG7EsCrktMOJen8adWq3ajlTBFgxotqxPFjsD+QybIht/DZQoBZ/e5S3IIXKpgo WG/CScWAV+AwsFCtJ5rRIghfbLsB5FjFqHmYTs8c9FGiCVNeR9+Y/Di9PyTqMmPnXY1f gf5rVVrRwMaE/7ipYyaHR9u5JtBUdS7nGHZ+wnbXheeJX0P6GtScMW6QVNlbN2Qj1x9N kg2/fJ11sPvZUyJuODwijSk8FcXHOB9GjdPZ0rjX1n93k2n22fq5aQkCtpecZO7tR4up 6tV5WGihGBr0PuQaGVEG129fJntYeG4t7/l0fWO1aLgKFggCOmdAxuTp+RaMjmi365sK R9Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z/Pfli3ijYHnlJT4Xorth9mXRem8tBvM4t0H60tFmKU=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index dd11972ed2..13b9918276 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -151,7 +151,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 -#define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 0 #define TCG_TARGET_HAS_bitsel_vec 0 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 23c25ff619..53d86268b6 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -277,6 +277,7 @@ typedef enum S390Opcode { VRRc_VCEQ =3D 0xe7f8, /* we leave the m5 cs field 0 */ VRRc_VCH =3D 0xe7fb, /* " */ VRRc_VCHL =3D 0xe7f9, /* " */ + VRRc_VML =3D 0xe7a2, VRRc_VN =3D 0xe768, VRRc_VNC =3D 0xe769, VRRc_VNO =3D 0xe76b, @@ -2661,6 +2662,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_andc_vec: tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0); break; + case INDEX_op_mul_vec: + tcg_out_insn(s, VRRc, VML, a0, a1, a2, vece); + break; case INDEX_op_or_vec: tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0); break; @@ -2710,6 +2714,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) return 1; case INDEX_op_cmp_vec: return -1; + case INDEX_op_mul_vec: + return vece < MO_64; default: return 0; } @@ -2946,6 +2952,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_orc_vec: case INDEX_op_xor_vec: case INDEX_op_cmp_vec: + case INDEX_op_mul_vec: return C_O1_I2(v, v, v); =20 default: --=20 2.25.1 From nobody Tue Nov 18 19:47:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612757766; cv=none; d=zohomail.com; s=zohoarc; b=nXojgS2tCc2637gXZHLTr47RnRxE5/WtE8mY6Vbjoz5zDYr+GXYcwVT2f10n36+1JuGH6n+cL9cK6N9L74YVAjIhVfQTnOrkRTgZyJ3mVr4RM49LEGpnIKj7DrOBzqOixMs7At3BduHELiTgekRT9g5hMYRO77h4HonlyZmYM/M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 12 ++--- tcg/s390x/tcg-target.c.inc | 93 +++++++++++++++++++++++++++++++++- 3 files changed, 99 insertions(+), 7 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index cb953896d5..49b98f33b9 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -24,6 +24,7 @@ C_O1_I2(r, 0, rI) C_O1_I2(r, 0, rJ) C_O1_I2(r, r, ri) C_O1_I2(r, rZ, r) +C_O1_I2(v, v, r) C_O1_I2(v, v, v) C_O1_I4(r, r, ri, r, 0) C_O1_I4(r, r, ri, rI, 0) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 13b9918276..3026a4d8c4 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -145,12 +145,12 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 1 #define TCG_TARGET_HAS_abs_vec 1 -#define TCG_TARGET_HAS_roti_vec 0 -#define TCG_TARGET_HAS_rots_vec 0 -#define TCG_TARGET_HAS_rotv_vec 0 -#define TCG_TARGET_HAS_shi_vec 0 -#define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_roti_vec 1 +#define TCG_TARGET_HAS_rots_vec 1 +#define TCG_TARGET_HAS_rotv_vec 1 +#define TCG_TARGET_HAS_shi_vec 1 +#define TCG_TARGET_HAS_shs_vec 1 +#define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 0 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 53d86268b6..22a6f18cc4 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -277,6 +277,10 @@ typedef enum S390Opcode { VRRc_VCEQ =3D 0xe7f8, /* we leave the m5 cs field 0 */ VRRc_VCH =3D 0xe7fb, /* " */ VRRc_VCHL =3D 0xe7f9, /* " */ + VRRc_VERLLV =3D 0xe773, + VRRc_VESLV =3D 0xe770, + VRRc_VESRAV =3D 0xe77a, + VRRc_VESRLV =3D 0xe778, VRRc_VML =3D 0xe7a2, VRRc_VN =3D 0xe768, VRRc_VNC =3D 0xe769, @@ -287,6 +291,10 @@ typedef enum S390Opcode { VRRc_VX =3D 0xe76d, VRRf_VLVGP =3D 0xe762, =20 + VRSa_VERLL =3D 0xe733, + VRSa_VESL =3D 0xe730, + VRSa_VESRA =3D 0xe73a, + VRSa_VESRL =3D 0xe738, VRSb_VLVG =3D 0xe722, VRSc_VLGV =3D 0xe721, =20 @@ -631,6 +639,18 @@ static void tcg_out_insn_VRRf(TCGContext *s, S390Opcod= e op, tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0)); } =20 +static void tcg_out_insn_VRSa(TCGContext *s, S390Opcode op, TCGReg v1, + intptr_t d2, TCGReg b2, TCGReg v3, int m4) +{ + tcg_debug_assert(v1 >=3D TCG_REG_V0 && v1 <=3D TCG_REG_V31); + tcg_debug_assert(d2 >=3D 0 && d2 <=3D 0xfff); + tcg_debug_assert(b2 <=3D TCG_REG_R15); + tcg_debug_assert(v3 >=3D TCG_REG_V0 && v3 <=3D TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v3 & 15)); + tcg_out16(s, b2 << 12 | d2); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12)); +} + static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, intptr_t d2, TCGReg b2, TCGReg r3, int m4) { @@ -2675,6 +2695,43 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); break; =20 + case INDEX_op_shli_vec: + tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece); + break; + case INDEX_op_shri_vec: + tcg_out_insn(s, VRSa, VESRL, a0, a2, TCG_REG_NONE, a1, vece); + break; + case INDEX_op_sari_vec: + tcg_out_insn(s, VRSa, VESRA, a0, a2, TCG_REG_NONE, a1, vece); + break; + case INDEX_op_rotli_vec: + tcg_out_insn(s, VRSa, VERLL, a0, a2, TCG_REG_NONE, a1, vece); + break; + case INDEX_op_shls_vec: + tcg_out_insn(s, VRSa, VESL, a0, 0, a2, a1, vece); + break; + case INDEX_op_shrs_vec: + tcg_out_insn(s, VRSa, VESRL, a0, 0, a2, a1, vece); + break; + case INDEX_op_sars_vec: + tcg_out_insn(s, VRSa, VESRA, a0, 0, a2, a1, vece); + break; + case INDEX_op_rotls_vec: + tcg_out_insn(s, VRSa, VERLL, a0, 0, a2, a1, vece); + break; + case INDEX_op_shlv_vec: + tcg_out_insn(s, VRRc, VESLV, a0, a1, a2, vece); + break; + case INDEX_op_shrv_vec: + tcg_out_insn(s, VRRc, VESRLV, a0, a1, a2, vece); + break; + case INDEX_op_sarv_vec: + tcg_out_insn(s, VRRc, VESRAV, a0, a1, a2, vece); + break; + case INDEX_op_rotlv_vec: + tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece); + break; + case INDEX_op_cmp_vec: switch ((TCGCond)args[3]) { case TCG_COND_EQ: @@ -2709,10 +2766,23 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type= , unsigned vece) case INDEX_op_not_vec: case INDEX_op_or_vec: case INDEX_op_orc_vec: + case INDEX_op_rotli_vec: + case INDEX_op_rotls_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_sari_vec: + case INDEX_op_sars_vec: + case INDEX_op_sarv_vec: + case INDEX_op_shli_vec: + case INDEX_op_shls_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shri_vec: + case INDEX_op_shrs_vec: + case INDEX_op_shrv_vec: case INDEX_op_sub_vec: case INDEX_op_xor_vec: return 1; case INDEX_op_cmp_vec: + case INDEX_op_rotrv_vec: return -1; case INDEX_op_mul_vec: return vece < MO_64; @@ -2775,7 +2845,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, u= nsigned vece, TCGArg a0, ...) { va_list va; - TCGv_vec v0, v1, v2; + TCGv_vec v0, v1, v2, t0; =20 va_start(va, a0); v0 =3D temp_tcgv_vec(arg_temp(a0)); @@ -2787,6 +2857,13 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); break; =20 + case INDEX_op_rotrv_vec: + t0 =3D tcg_temp_new_vec(type); + tcg_gen_neg_vec(vece, t0, v2); + tcg_gen_rotlv_vec(vece, v0, v1, t0); + tcg_temp_free_vec(t0); + break; + default: g_assert_not_reached(); } @@ -2943,6 +3020,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_abs_vec: case INDEX_op_neg_vec: case INDEX_op_not_vec: + case INDEX_op_rotli_vec: + case INDEX_op_sari_vec: + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: return C_O1_I1(v, v); case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -2953,7 +3034,17 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_xor_vec: case INDEX_op_cmp_vec: case INDEX_op_mul_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return C_O1_I2(v, v, v); + case INDEX_op_rotls_vec: + case INDEX_op_shls_vec: + case INDEX_op_shrs_vec: + case INDEX_op_sars_vec: + return C_O1_I2(v, v, r); =20 default: g_assert_not_reached(); --=20 2.25.1 From nobody Tue Nov 18 19:47:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612756010; cv=none; d=zohomail.com; s=zohoarc; b=B8IwWc9f1HReS+vx924juQpfoHXZggYLMPVTzVAVZoGUJF+Jxz6mFbCDokmA8N8NCLG00zOXl2UTNyNbRdMWGHlIelOvOR7hmBLlWzl/1yWod732wq7cp3f3nBM1dRh+zbH4e9hbrp70+QL1NF3WeiNWZI/jlvORboqP1N7drCQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612756010; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bmajfo6ax0mEWHKQooz62P4LLatAA1i50E2HiY5O+rQ=; b=JTstdp7+PExM2THqeNbti1bDT0/KE0TfHYnYyt6LQOVGsqI1k6Ma+8Zj/2bnHnyeAv RIAocpgfXvbweDSpC7+XUzKQtTt66fHkeIGkgshphrNSnkJLIB8jLOoqSV2vAAhwsa0Q UbSbsYPREi+xBtTceJ8IMtdtaHrVefJhCX7BSAqYcyKPAiOVfC+OnoGZuQuAczVAEEWv M+sz1jhAj8II6sXe0TNudJwLAkfX4LO2mMQp16WbptIalt3+4CsHz48O35KkGskYEeOw fB36MRWnoO5kDqTnWQCjoPR0Ir2hfKMuiB6i0ITsqhPMQkd9VmPTTctEojVg2yUDks/x 2utA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bmajfo6ax0mEWHKQooz62P4LLatAA1i50E2HiY5O+rQ=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 3026a4d8c4..efa32f348c 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -153,7 +153,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 0 -#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 0 =20 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 22a6f18cc4..3bf49e6c90 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -282,6 +282,10 @@ typedef enum S390Opcode { VRRc_VESRAV =3D 0xe77a, VRRc_VESRLV =3D 0xe778, VRRc_VML =3D 0xe7a2, + VRRc_VMN =3D 0xe7fe, + VRRc_VMNL =3D 0xe7fc, + VRRc_VMX =3D 0xe7ff, + VRRc_VMXL =3D 0xe7fd, VRRc_VN =3D 0xe768, VRRc_VNC =3D 0xe769, VRRc_VNO =3D 0xe76b, @@ -2732,6 +2736,19 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece); break; =20 + case INDEX_op_smin_vec: + tcg_out_insn(s, VRRc, VMN, a0, a1, a2, vece); + break; + case INDEX_op_smax_vec: + tcg_out_insn(s, VRRc, VMX, a0, a1, a2, vece); + break; + case INDEX_op_umin_vec: + tcg_out_insn(s, VRRc, VMNL, a0, a1, a2, vece); + break; + case INDEX_op_umax_vec: + tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece); + break; + case INDEX_op_cmp_vec: switch ((TCGCond)args[3]) { case TCG_COND_EQ: @@ -2778,7 +2795,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_shri_vec: case INDEX_op_shrs_vec: case INDEX_op_shrv_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: case INDEX_op_sub_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: case INDEX_op_xor_vec: return 1; case INDEX_op_cmp_vec: @@ -3039,6 +3060,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: return C_O1_I2(v, v, v); case INDEX_op_rotls_vec: case INDEX_op_shls_vec: --=20 2.25.1 From nobody Tue Nov 18 19:47:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FnMPyDvv8qty8IO8qnH26ldICiCh5lihNUWEYMvpptg=; b=yoHpBcbKKvkGr/i2BhZ6r6txdvgIkf9a2j0+qxbnBZNnvcVi93/tMvVPogMT2QWj69 IAwJTzEbuFrr1gdB3rhjCz5P+73jTxaNwFWMyYx7XOQ2Z4hm9Jn1WpyPP4CDmxiNUj1t w7vNZtGyEhM+sZ0V4auPAvdh4cYv3AilfjAvkVuRWGYo5ZENRkKnbhgubiucrcKY78hk So550p+wqiToPsMFt1XueT2FC2L6iIRnXeRLzxcat2bOsmj52xKCsbaGHhdNDdDEl3s7 k/EZw7Divpg6rrWVKVfOwVxfRwU7SIPMcFy3ojjUxnaMB7oY35r9ttllQJXtRBDg00YN aKag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FnMPyDvv8qty8IO8qnH26ldICiCh5lihNUWEYMvpptg=; b=B6Yf+p0d6b5lWBaHyQNZdWULC3Ubb5A7h2xIS+IsnF1ZFQfxEly+Ag+M4SzOlx4sja I7p5C/ipZ4LXR6KRLobH43O8Ko4Qq45sD5/HJ74xDyMaH0VymtocM6oCY212cLhjCPty 7YUTVzkEP/SXyuJLeWbumiuoueoubrBGGJagZkYjdAWIu4NfFHJnmLl1BYu5c+ZblGTX cv+NWbxgBiFqCjt/HKZcgP/IYDilyn0l1mFB/HiQreRldkOi49Pq/8VtcDO7wRk5B7uv +OrodgWfszMAoVq2MeCq5bA2QlmEQl8f1Gfwy7dta9klwoWiG+XdyYKeoG8Q6f/scHUq BssA== X-Gm-Message-State: AOAM531gDZqf9emnejY9s6Wh+9PyIYVDYyv73I++2fIOdV1fpzcwwqK7 zjehUHDQPQ2ZzbkYtlVwqGi0RJmDE8ZUnA== X-Google-Smtp-Source: ABdhPJwUX+G3B9lIce4NIqkaiRq9oOhpYWbm5tqa3YLZB7++LOtDc2a3Jj6hHdtX9OoERk14kv3p5Q== X-Received: by 2002:a17:90a:e292:: with SMTP id d18mr14684029pjz.66.1612752677803; Sun, 07 Feb 2021 18:51:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 13/16] tcg: Expand usadd/ussub with umin/umax Date: Sun, 7 Feb 2021 18:50:58 -0800 Message-Id: <20210208025101.271726-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For usadd, we only have to consider overflow. Since ~B + B =3D=3D -1, the maximum value for A that saturates is ~B. For ussub, we only have to consider underflow. The minimum value that saturates to 0 from A - B is B. Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 37 +++++++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index d19aa7373e..9747b7bb06 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -120,6 +120,18 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, continue; } break; + case INDEX_op_usadd_vec: + if (tcg_can_emit_vec_op(INDEX_op_umin_vec, type, vece) || + tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)) { + continue; + } + break; + case INDEX_op_ussub_vec: + if (tcg_can_emit_vec_op(INDEX_op_umax_vec, type, vece) || + tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)) { + continue; + } + break; case INDEX_op_cmpsel_vec: case INDEX_op_smin_vec: case INDEX_op_smax_vec: @@ -604,7 +616,18 @@ void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv= _vec a, TCGv_vec b) =20 void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3_nofail(vece, r, a, b, INDEX_op_usadd_vec); + if (!do_op3(vece, r, a, b, INDEX_op_usadd_vec)) { + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(NULL); + TCGv_vec t =3D tcg_temp_new_vec_matching(r); + + /* usadd(a, b) =3D min(a, ~b) + b */ + tcg_gen_not_vec(vece, t, b); + tcg_gen_umin_vec(vece, t, t, a); + tcg_gen_add_vec(vece, r, r, b); + + tcg_temp_free_vec(t); + tcg_swap_vecop_list(hold_list); + } } =20 void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) @@ -614,7 +637,17 @@ void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv= _vec a, TCGv_vec b) =20 void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3_nofail(vece, r, a, b, INDEX_op_ussub_vec); + if (!do_op3(vece, r, a, b, INDEX_op_ussub_vec)) { + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(NULL); + TCGv_vec t =3D tcg_temp_new_vec_matching(r); + + /* ussub(a, b) =3D max(a, b) - b */ + tcg_gen_umax_vec(vece, t, a, b); + tcg_gen_sub_vec(vece, r, t, b); + + tcg_temp_free_vec(t); + tcg_swap_vecop_list(hold_list); + } } =20 static void do_minmax(unsigned vece, TCGv_vec r, TCGv_vec a, --=20 2.25.1 From nobody Tue Nov 18 19:47:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612757870; cv=none; d=zohomail.com; s=zohoarc; b=ilgFL/Auh3dSocXHl0zATJIzt8yr0p/FigjjXr3XS8qXVl+BfUYIwbVS3V7KTJ6+HLTEUh7epF2vwMu+oCy9S6yarMB8ec0lbf/LSqtDA4qTIhLNQK17ukjG0T53lLp8f9chHpFb4nDNN091Z+QUHO6Z7kJNSR4/NkcieWcdmbw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612757870; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oMSoefukScEf8fPG2WpWUUHe7GtaNiNm3/VqmCKdoJ0=; b=ROnz6pxlq7poFvfwebT+Xl39HusDrCyzCpC+rN6nRPUj5KMKpQZ4RgSoGt+UFfN8vMwjKZnmwRrbWN1CYazjzXNAkrieCN1vf0zWcK10BfsjhwSIUfvcBjMIB9OfON4RRBhNnP8Y5W7CFeW9+dpPXOMtMGtXb/Xa5U1e9C32F5g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612757870904490.77666890041087; Sun, 7 Feb 2021 20:17:50 -0800 (PST) Received: from localhost ([::1]:58030 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8xzh-0002HX-N6 for importer@patchew.org; Sun, 07 Feb 2021 23:17:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60280) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8we1-0008Mm-Kp for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:51:21 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:33269) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wdz-0001Pl-UH for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:51:21 -0500 Received: by mail-pf1-x431.google.com with SMTP id o20so8801067pfu.0 for ; Sun, 07 Feb 2021 18:51:19 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oMSoefukScEf8fPG2WpWUUHe7GtaNiNm3/VqmCKdoJ0=; b=t+Q4Nvr6ukeb2ufunrRoGgD05wo9w6eGemP9c6kWKp5EXPdY+XuMwYQw8dglF3sleB kOJ9Q/rux1Fz2KyLwAlDZqq8gDUhSNxDGQm016n9s+RJQRDxsw2SXYWYgbUYGnAQlgdA SYj80G9RzpmJfviLR5zMnSzEnvqLbkW9CkQ+04gZfAiaweq7IJUeMvdEJ+yfYjpath6j zyXUBT21bU/Kj4qNnBj0Nu2O9i9vA7QQ2MPejRzEEod4DpMa1WMtG/6ZjlRYmnOnbN7Q F+mvO5HBSg62SpRwUhe5EhhJ+Z0FYbdU2rb3F3i0tPO8i7TohH8s90C4If//HZP4i7es huyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oMSoefukScEf8fPG2WpWUUHe7GtaNiNm3/VqmCKdoJ0=; b=O1wxeSkMwldSDKNUG8dZKZfZsqrboMiGTPcOf/EcrrEpxrHALK0Rc1Y8BrhMCwtblS Utg6mycN4xOpvv/RBWehOqkcFuZZ84kMJZ9LI06ltf/MTK1774NGfN1arqoMHmwbORBE SKu8rT4nC0gN2NbDnW+ZLzBUTaenJ/Z1Hwy/rSgUNETI6+JQdOmQs2OoJkM9nE89iBHw 5LVJdrp+FiNKiTn17Qd7ExaLNM3p5DAzxarPoMs1+d16dqYNAOaYbuztTYf3B353g0LN BO73nsnE3rACiO/R+h6B6XT9GBpSxfULH5Z0wNG6Wy+Po6JVz9LT+DVV4SbVGQb2n2UM uYsQ== X-Gm-Message-State: AOAM5302NXSrDR3h2Wm2J17QOBNhpUZwP8XNip0hPWKlev398Zy57Sw9 aoOIHxtYS8IkgRxUqZ8ER0yDTQjQ69zIiw== X-Google-Smtp-Source: ABdhPJwRxqFqHxcGHSiDEkj0aPpRT2jZz/ovebYnrfbs4xg2+IQPh/pbNyElhWtz9ihgpijPuqOfXw== X-Received: by 2002:a63:214e:: with SMTP id s14mr685798pgm.101.1612752678644; Sun, 07 Feb 2021 18:51:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 14/16] tcg/s390x: Implement TCG_TARGET_HAS_sat_vec Date: Sun, 7 Feb 2021 18:50:59 -0800 Message-Id: <20210208025101.271726-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The unsigned saturations are handled via generic code using min/max. The signed saturations are expanded using double-sized arithmetic and a saturating pack. Since all operations are done via expansion, do not actually set TCG_TARGET_HAS_sat_vec. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.opc.h | 3 ++ tcg/s390x/tcg-target.c.inc | 63 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/tcg/s390x/tcg-target.opc.h b/tcg/s390x/tcg-target.opc.h index 67afc82a93..0eb2350fb3 100644 --- a/tcg/s390x/tcg-target.opc.h +++ b/tcg/s390x/tcg-target.opc.h @@ -10,3 +10,6 @@ * emitted by tcg_expand_vec_op. For those familiar with GCC internals, * consider these to be UNSPEC with names. */ +DEF(s390_vuph_vec, 1, 1, 0, IMPLVEC) +DEF(s390_vupl_vec, 1, 1, 0, IMPLVEC) +DEF(s390_vpks_vec, 1, 2, 0, IMPLVEC) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 3bf49e6c90..d4877dcf67 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -291,7 +291,10 @@ typedef enum S390Opcode { VRRc_VNO =3D 0xe76b, VRRc_VO =3D 0xe76a, VRRc_VOC =3D 0xe76f, + VRRc_VPKS =3D 0xe797, /* we leave the m5 cs field 0 */ VRRc_VS =3D 0xe7f7, + VRRa_VUPH =3D 0xe7d7, + VRRa_VUPL =3D 0xe7d6, VRRc_VX =3D 0xe76d, VRRf_VLVGP =3D 0xe762, =20 @@ -2765,6 +2768,16 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, } break; =20 + case INDEX_op_s390_vuph_vec: + tcg_out_insn(s, VRRa, VUPH, a0, a1, vece); + break; + case INDEX_op_s390_vupl_vec: + tcg_out_insn(s, VRRa, VUPL, a0, a1, vece); + break; + case INDEX_op_s390_vpks_vec: + tcg_out_insn(s, VRRc, VPKS, a0, a1, a2, vece); + break; + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: @@ -2807,6 +2820,9 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) return -1; case INDEX_op_mul_vec: return vece < MO_64; + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + return vece < MO_64 ? -1 : 0; default: return 0; } @@ -2862,6 +2878,43 @@ static void expand_vec_cmp(TCGType type, unsigned ve= ce, TCGv_vec v0, } } =20 +static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc) +{ + TCGv_vec h1 =3D tcg_temp_new_vec(type); + TCGv_vec h2 =3D tcg_temp_new_vec(type); + TCGv_vec l1 =3D tcg_temp_new_vec(type); + TCGv_vec l2 =3D tcg_temp_new_vec(type); + + tcg_debug_assert (vece < MO_64); + + /* Unpack with sign-extension. */ + vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, + tcgv_vec_arg(h1), tcgv_vec_arg(v1)); + vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, + tcgv_vec_arg(h2), tcgv_vec_arg(v2)); + + vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, + tcgv_vec_arg(l1), tcgv_vec_arg(v1)); + vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, + tcgv_vec_arg(l2), tcgv_vec_arg(v2)); + + /* Arithmetic on a wider element size. */ + vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(h1), + tcgv_vec_arg(h1), tcgv_vec_arg(h2)); + vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(l1), + tcgv_vec_arg(l1), tcgv_vec_arg(l2)); + + /* Pack with saturation. */ + vec_gen_3(INDEX_op_s390_vpks_vec, type, vece + 1, + tcgv_vec_arg(v0), tcgv_vec_arg(h1), tcgv_vec_arg(l1)); + + tcg_temp_free_vec(h1); + tcg_temp_free_vec(h2); + tcg_temp_free_vec(l1); + tcg_temp_free_vec(l2); +} + void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { @@ -2885,6 +2938,13 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, tcg_temp_free_vec(t0); break; =20 + case INDEX_op_ssadd_vec: + expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_add_vec); + break; + case INDEX_op_sssub_vec: + expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_sub_vec); + break; + default: g_assert_not_reached(); } @@ -3045,6 +3105,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_sari_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: + case INDEX_op_s390_vuph_vec: + case INDEX_op_s390_vupl_vec: return C_O1_I1(v, v); case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -3064,6 +3126,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_s390_vpks_vec: return C_O1_I2(v, v, v); case INDEX_op_rotls_vec: case INDEX_op_shls_vec: --=20 2.25.1 From nobody Tue Nov 18 19:47:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612755557; cv=none; d=zohomail.com; s=zohoarc; b=htCRE2Dv50za1rjwElj3sRC3DhlWc+nlh0/Bd9BIzBj3mVK5cVglZIgCDjRpNy8mx/661J3HZiyrZCIOfE64d/ww7IGIc3c9x1cvsoGaS2tvJXngOpQQxCtVNtWfVkSO7K/54k94mNzai00G54JJ4OpsuzI71H5HCqyKfBqSjWw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612755557; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YmDqe/82SlyxP6c0GtyFsHwbtixl9cebfPdkUT3Hqik=; b=bdHby+AC+rbzdHPsrkGhNHo/Dc2C8HWuzAKLzSO0QkdUjIIs81RqbG85Oz5gfU3B6GhJoumSEo3bt3Hj3kJ56ukDv6SE88Oz/7Uaz0mw7vcYe29/5CWWbIYBUiFkuTht+8LLz8aJCDjfQZtZ2lwoEq1F9OniyTiHVRiJKWGuU1Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612755557729552.9588811403207; Sun, 7 Feb 2021 19:39:17 -0800 (PST) Received: from localhost ([::1]:57336 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8xOM-0006yj-Vb for importer@patchew.org; Sun, 07 Feb 2021 22:39:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60294) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8we2-0008Pz-Rg for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:51:22 -0500 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:42998) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8we1-0001Pu-4H for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:51:22 -0500 Received: by mail-pf1-x42d.google.com with SMTP id w18so8766765pfu.9 for ; Sun, 07 Feb 2021 18:51:20 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 20 ++++++++++++++++++++ 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 49b98f33b9..426dd92e51 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -26,6 +26,7 @@ C_O1_I2(r, r, ri) C_O1_I2(r, rZ, r) C_O1_I2(v, v, r) C_O1_I2(v, v, v) +C_O1_I3(v, v, v, v) C_O1_I4(r, r, ri, r, 0) C_O1_I4(r, r, ri, rI, 0) C_O2_I2(b, a, 0, r) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index efa32f348c..127ccd30af 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -154,7 +154,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 1 -#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 1 #define TCG_TARGET_HAS_cmpsel_vec 0 =20 /* used for function call generation */ diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index d4877dcf67..3c86b233b0 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -296,6 +296,7 @@ typedef enum S390Opcode { VRRa_VUPH =3D 0xe7d7, VRRa_VUPL =3D 0xe7d6, VRRc_VX =3D 0xe76d, + VRRe_VSEL =3D 0xe78d, VRRf_VLVGP =3D 0xe762, =20 VRSa_VERLL =3D 0xe733, @@ -635,6 +636,18 @@ static void tcg_out_insn_VRRc(TCGContext *s, S390Opcod= e op, tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12)); } =20 +static void tcg_out_insn_VRRe(TCGContext *s, S390Opcode op, + TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) +{ + tcg_debug_assert(v1 >=3D TCG_REG_V0 && v1 <=3D TCG_REG_V31); + tcg_debug_assert(v2 >=3D TCG_REG_V0 && v2 <=3D TCG_REG_V31); + tcg_debug_assert(v3 >=3D TCG_REG_V0 && v3 <=3D TCG_REG_V31); + tcg_debug_assert(v4 >=3D TCG_REG_V0 && v4 <=3D TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v2 & 15)); + tcg_out16(s, v3 << 12); + tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, v4) | ((v4 & 15) << 12)); +} + static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, TCGReg v1, TCGReg r2, TCGReg r3) { @@ -2752,6 +2765,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece); break; =20 + case INDEX_op_bitsel_vec: + tcg_out_insn(s, VRRe, VSEL, a0, a1, a2, args[3]); + break; + case INDEX_op_cmp_vec: switch ((TCGCond)args[3]) { case TCG_COND_EQ: @@ -2792,6 +2809,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_add_vec: case INDEX_op_and_vec: case INDEX_op_andc_vec: + case INDEX_op_bitsel_vec: case INDEX_op_neg_vec: case INDEX_op_not_vec: case INDEX_op_or_vec: @@ -3133,6 +3151,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_shrs_vec: case INDEX_op_sars_vec: return C_O1_I2(v, v, r); + case INDEX_op_bitsel_vec: + return C_O1_I3(v, v, v, v); =20 default: g_assert_not_reached(); --=20 2.25.1 From nobody Tue Nov 18 19:47:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612756118; cv=none; d=zohomail.com; s=zohoarc; b=Qy0l766vLsFaM3ryO6XAJK2IU0jh+WCGtesySpssMXCbEyCVeIyNoDgtMy9E4kaBN69enN6iNLUMvMg/7cktHufS7G2WBxhj1dw3bA709vPO9I3uJcNbxDnk0jBdjd5jHmZwVb6gQ3KT7kG+VQ07ZQnPRreUZSad5+Ul72KHpsg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612756118; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CLrUDTIhbtGAsWgOYvJT4xjXL39Hm5cBXAIplJGdRpg=; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CLrUDTIhbtGAsWgOYvJT4xjXL39Hm5cBXAIplJGdRpg=; b=vlRnMGPJVEmDLno5B6/hvrOGcBHqwJjgdgsd1JtSSC1+s0SeEbO26ZNTitLxyQtCyU pcEUEEzlZrJQNIRMksC7/ILCQAr35lOUvmfI8oJUvhRdgPdxc7vYhKArzpT7DP5kExqY NnShh2EtEfvSLemCoM61/sUFGFXubwsXx4sEomgLAQozvFwHaxtapX59kTYdF0jDFexZ tjMSQF754o4b6OPKSyf3/xeVkfrZkj89y9Fjf+K6kmAbhcfCjKgCx9utuJ9J6OZ6unbd fsdfcf2sbX3k3T6SHYoD3Rgy/MoGybaS7YRcrosfMfJo/NFuFAARjstPEAcwVCO/ftdz gNXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CLrUDTIhbtGAsWgOYvJT4xjXL39Hm5cBXAIplJGdRpg=; b=WZTic0tBHlxrJxAgId0b55julq203CPF1R6laosPjI0Ibx32SmYd4vmcwkcIbKzZQp 0ZGI81D2KWi5PvvXVvnAAA43YLUcJpkEkPhZckNfAkZNY0UDNhsaFxl01sEbf71nO0gZ kKST/AfJNiw6FFEeKuUE/Zr0ajskJpgETm/eWqLaSaTFj12KNhmF/ZLab1pwA0xoZIaa 5g6j3HUbQFRrv+jfUyIEcphB5wXsLOAd9cMnIntl8u8YBTr9VbmTKbOq7IZ7SiBVsiMG a/ODV+2lWk0hILVTNLUAK7psJZrFJERoPvmAKgMxe3bzXMHWXVx2MKM72F7m3suCVIy3 zFCg== X-Gm-Message-State: AOAM533gR1aZrbZQ4ekIkeGOCO9TpQij3FMu0wb2UjWqCzwJbFp3bDKY 9xUjiv+OjHeJ5YoP8Jr3mqJ4NexX5bNgnw== X-Google-Smtp-Source: ABdhPJwdiRjib49t0S2xyLkeyac54AfR+6uaSs/RQp9wrqrp86i803E/Y8TQ6Tb1jDrgbT9vJhqLgw== X-Received: by 2002:a17:90b:4a02:: with SMTP id kk2mr15009184pjb.115.1612752681072; Sun, 07 Feb 2021 18:51:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 16/16] tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec Date: Sun, 7 Feb 2021 18:51:01 -0800 Message-Id: <20210208025101.271726-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This is via expansion; don't actually set TCG_TARGET_HAS_cmpsel_vec. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 3c86b233b0..1888c7a5b4 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -2834,6 +2834,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_xor_vec: return 1; case INDEX_op_cmp_vec: + case INDEX_op_cmpsel_vec: case INDEX_op_rotrv_vec: return -1; case INDEX_op_mul_vec: @@ -2896,6 +2897,21 @@ static void expand_vec_cmp(TCGType type, unsigned ve= ce, TCGv_vec v0, } } =20 +static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec c1, TCGv_vec c2, + TCGv_vec v3, TCGv_vec v4, TCGCond cond) +{ + TCGv_vec t =3D tcg_temp_new_vec(type); + + if (expand_vec_cmp_noinv(type, vece, t, c1, c2, cond)) { + /* Invert the sense of the compare by swapping arguments. */ + tcg_gen_bitsel_vec(vece, v0, t, v4, v3); + } else { + tcg_gen_bitsel_vec(vece, v0, t, v3, v4); + } + tcg_temp_free_vec(t); +} + static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc) { @@ -2937,7 +2953,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, u= nsigned vece, TCGArg a0, ...) { va_list va; - TCGv_vec v0, v1, v2, t0; + TCGv_vec v0, v1, v2, v3, v4, t0; =20 va_start(va, a0); v0 =3D temp_tcgv_vec(arg_temp(a0)); @@ -2949,6 +2965,12 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); break; =20 + case INDEX_op_cmpsel_vec: + v3 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + v4 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGAr= g)); + break; + case INDEX_op_rotrv_vec: t0 =3D tcg_temp_new_vec(type); tcg_gen_neg_vec(vece, t0, v2); --=20 2.25.1