From nobody Tue Nov 18 07:46:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612755091; cv=none; d=zohomail.com; s=zohoarc; b=WBEx70wKqf7fTlEARsMXS5BUk2iDZJ7UZSpWtKDbVw1ngBlnuS7bGVXrlVzplZkeWuVAyaJ5nULGT0Gc/RGrBZEepnEE/oIdxExlcrShHgI12w2nTPqZc9BGOV0v1+b7qwxq82FqWV+QjWYN4574Cn9bPTrrSWE/arF7uOFNJB0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612755091; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=I7geR9l1CU0gdZRN3d0rsGPXzyzt1jqfcdVWXDuwgz4=; b=jxqj0GG4mMArNx7ms/KEizDnctHBsoGyFvoVF9HP/piDuLgDI6aFbQrwC7kWl2/bJOHjzzKtCOUHd5c5DKDAmNK5ceseeiLPkciaWkgd5k8XJu1Dbv7XcBlUB/PQgFryISTp5R6Rw1F04F7vBaHd9D8by5aTSZ/inqhqx4v1waQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612755091924659.3016661427364; Sun, 7 Feb 2021 19:31:31 -0800 (PST) Received: from localhost ([::1]:33196 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8xGs-0005PH-Jm for importer@patchew.org; Sun, 07 Feb 2021 22:31:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59370) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wZL-0003jH-Fs for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:46:31 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:40879) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wZI-0008VY-VI for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:46:31 -0500 Received: by mail-pl1-x633.google.com with SMTP id y10so7028318plk.7 for ; Sun, 07 Feb 2021 18:46:28 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id h8sm8966092pfv.154.2021.02.07.18.46.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:46:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=I7geR9l1CU0gdZRN3d0rsGPXzyzt1jqfcdVWXDuwgz4=; b=G4I/g17AiFwEQY1v1SjW7xUCytCPDKpR6zi0DWR3+/qrIiSFnNhsFik11SemTZa+OO xTKlrSPUM6WVDbTW4ElnwKF9sFkdzZULtSmEsY7hdHkcaetFAvVzhu/+rHUXwxrTUDcp CVAXH9iEfgEfW18Oi44YpTOlGvjgqK/dsAWFjBB8nuDjgrad8QnQgWxIwYbSV5GYjsIA 602FBe0Gu2VRegb/5edAWSrIbVyxwvkxAChfk75WNSeykW0L+gEmu/0NCWi9rfFNAktj 1G1ymLt8gHcjkyoLGijUuM2fTaKfxQCo5jd3Wk1G3kXH/VtH3wWXIqMPoSonYL3sIJ0Y /8hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I7geR9l1CU0gdZRN3d0rsGPXzyzt1jqfcdVWXDuwgz4=; b=ZacB6VHUZsU/IjxkPNFCfMrli7wiju7BsiBtXUIHKKWuj8oLYh03/H6vytyTG1LO9R VUuszc3LXfk66DBuy96rTUQ96EIzpYQ1j6dD1HpyDIBoGxxdUAqv6R4E2SEnEBilK4xL WoaWQdUKxoQ5N/GVLpVHfiLn/gHCHjujK0tfWtA8WYs4fdw2kYT2e9R8Ta53ZLD+10Um W4eRfKllkFFnU/rN/96VjOUiFuqBMP59BnkX5YGvQ6SN3tuO1yHDGp/6/lJfIir1pFZh 7CGlcEYgKNJjVPdsu9S7C/+bvVrrPrA4plDwEIxCiMYT2LvWmM4BCA+vSYFps+GZJZ22 Otlg== X-Gm-Message-State: AOAM530PT9gslZml19bYgKfwQRWpjKiGzMjTUa+Djhk2cGI7mpWgcE7M EgsEDiMEdt3X9NQoof2W66BX3e+G40mvYA== X-Google-Smtp-Source: ABdhPJys5ToFw5Smt4IUZkDTg4HKPRlfIsMFetlTZXacfU1Q8txHPVU9wdL0pJixh1MD+zrkb4Zc2w== X-Received: by 2002:a17:902:ecc4:b029:e1:5a03:87b5 with SMTP id a4-20020a170902ecc4b02900e15a0387b5mr4161195plh.39.1612752387590; Sun, 07 Feb 2021 18:46:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 01/15] tcg: Change parameters for tcg_target_const_match Date: Sun, 7 Feb 2021 18:46:11 -0800 Message-Id: <20210208024625.271018-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208024625.271018-1-richard.henderson@linaro.org> References: <20210208024625.271018-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Change the return value to bool, because that's what is should have been from the start. Pass the ct mask instead of the whole TCGArgConstraint, as that's the only part that's relevant. Change the value argument to int64_t. We will need the extra width for 32-bit hosts wanting to match vector constants. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/tcg.c | 5 ++--- tcg/aarch64/tcg-target.c.inc | 5 +---- tcg/arm/tcg-target.c.inc | 5 +---- tcg/i386/tcg-target.c.inc | 4 +--- tcg/mips/tcg-target.c.inc | 5 +---- tcg/ppc/tcg-target.c.inc | 4 +--- tcg/riscv/tcg-target.c.inc | 4 +--- tcg/s390/tcg-target.c.inc | 5 +---- tcg/sparc/tcg-target.c.inc | 5 +---- tcg/tci/tcg-target.c.inc | 6 ++---- 10 files changed, 12 insertions(+), 36 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 63a12b197b..2f06477a67 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -147,8 +147,7 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCG= Reg arg, TCGReg arg1, static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, TCGReg base, intptr_t ofs); static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target); -static int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct); +static bool tcg_target_const_match(int64_t val, TCGType type, int ct); #ifdef TCG_TARGET_NEED_LDST_LABELS static int tcg_out_ldst_finalize(TCGContext *s); #endif @@ -4054,7 +4053,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) ts =3D arg_temp(arg); =20 if (ts->val_type =3D=3D TEMP_VAL_CONST - && tcg_target_const_match(ts->val, ts->type, arg_ct)) { + && tcg_target_const_match(ts->val, ts->type, arg_ct->ct)) { /* constant is OK for instruction */ const_args[i] =3D 1; new_args[i] =3D ts->val; diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 1376cdc404..35d3d3c12a 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -277,11 +277,8 @@ static bool is_shimm1632(uint32_t v32, int *cmode, int= *imm8) } } =20 -static int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) +static bool tcg_target_const_match(int64_t val, TCGType type, int ct) { - int ct =3D arg_ct->ct; - if (ct & TCG_CT_CONST) { return 1; } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 8457108a87..eb4f42e53d 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -301,11 +301,8 @@ static inline int check_fit_imm(uint32_t imm) * mov operand2: values represented with x << (2 * y), x < 0x100 * add, sub, eor...: ditto */ -static inline int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) +static bool tcg_target_const_match(int64_t val, TCGType type, int ct) { - int ct; - ct =3D arg_ct->ct; if (ct & TCG_CT_CONST) { return 1; } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 40326c2806..999dddc059 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -210,10 +210,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, } =20 /* test if a constant matches the constraint */ -static inline int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) +static bool tcg_target_const_match(int64_t val, TCGType type, int ct) { - int ct =3D arg_ct->ct; if (ct & TCG_CT_CONST) { return 1; } diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index ab55f3109b..3a9333d5cf 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -193,11 +193,8 @@ static inline bool is_p2m1(tcg_target_long val) } =20 /* test if a constant matches the constraint */ -static inline int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) +static bool tcg_target_const_match(int64_t val, TCGType type, int ct) { - int ct; - ct =3D arg_ct->ct; if (ct & TCG_CT_CONST) { return 1; } else if ((ct & TCG_CT_CONST_ZERO) && val =3D=3D 0) { diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 4377d15d62..41358c5018 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -238,10 +238,8 @@ static bool reloc_pc14(tcg_insn_unit *src_rw, const tc= g_insn_unit *target) } =20 /* test if a constant matches the constraint */ -static int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) +static bool tcg_target_const_match(int64_t val, TCGType type, int ct) { - int ct =3D arg_ct->ct; if (ct & TCG_CT_CONST) { return 1; } diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index e700c52067..043921cee5 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -145,10 +145,8 @@ static inline tcg_target_long sextreg(tcg_target_long = val, int pos, int len) } =20 /* test if a constant matches the constraint */ -static int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) +static bool tcg_target_const_match(int64_t val, TCGType type, int ct) { - int ct =3D arg_ct->ct; if (ct & TCG_CT_CONST) { return 1; } diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 695d7ee652..433061cfee 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -417,11 +417,8 @@ static bool patch_reloc(tcg_insn_unit *src_rw, int typ= e, } =20 /* Test if a constant matches the constraint. */ -static int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) +static bool tcg_target_const_match(int64_t val, TCGType type, int ct) { - int ct =3D arg_ct->ct; - if (ct & TCG_CT_CONST) { return 1; } diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 3d50f985c6..ce39ac2d86 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -341,11 +341,8 @@ static bool patch_reloc(tcg_insn_unit *src_rw, int typ= e, } =20 /* test if a constant matches the constraint */ -static inline int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) +static bool tcg_target_const_match(int64_t val, TCGType type, int ct) { - int ct =3D arg_ct->ct; - if (ct & TCG_CT_CONST) { return 1; } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index feac4659cc..59b4e833bb 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -671,11 +671,9 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType = type, TCGArg val, } =20 /* Test if a constant matches the constraint. */ -static int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) +static bool tcg_target_const_match(int64_t val, TCGType type, int ct) { - /* No need to return 0 or 1, 0 or !=3D 0 is good enough. */ - return arg_ct->ct & TCG_CT_CONST; + return ct & TCG_CT_CONST; } =20 static void tcg_target_init(TCGContext *s) --=20 2.25.1 From nobody Tue Nov 18 07:46:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id h8sm8966092pfv.154.2021.02.07.18.46.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:46:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PQ/mcK25Lt7IM0FgKHVU+2fV9f7uyIn3mrXWXKeuLCM=; b=Fc0Rs/m8TFs4eglQumk06SmI4IpqsgTYYOVSlzN6UXaC0TXVj9eTDhalBJzNa3toCY c8v7kGCfhZcUgdV4P5YUJ3Dga+CV5aEIUho2cbYe6w0KOwavkx65VqxFosdoA/AhUY9E EKu1WxHWcD3nqrzkt8EhEUY+qvMAV1R/evfI9ZJ2nbOv6DUoz3WIw4qPx4AS7szKAXEt LPUXJvthFBxud19oVLLWTs6dEl0SGBHfSufmn2fd8C4wYrGlmLz6Tlz9ZkSmYnnmHbEM ctYhk7fc81WlmWCERJSN+TsGuOf+qjH1Zsak4oKcPX7W/Hqvzho8x2rsbEuhfzVZFBLQ Jsuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PQ/mcK25Lt7IM0FgKHVU+2fV9f7uyIn3mrXWXKeuLCM=; b=jgKRyVgt1ix2trw1YYJrWkIJftY4AVNZo70r0Ixk3LNdbFLEmXx4AsMHuHKVlWVu4u jdL6+ZCTrE1qwpgRDPDtqUBwutBDVHVz/qv894RV2E3/nqqpWhqJTrSW2IEX0PK351jl /M7JvtucvIF9nn1/7Qv3it+A0TG75nXCN7CMvt527Rb/QdIlNlIHHvglIkB6/vSvdny4 nHBazK+oDEMGW57GL2m3cZ10awwtuir/3yQKnDdlQ8++RYPb7zoWl1JM3+vU2Ah1tiw1 XVzSQ3t733tIUNxAlSaY+ig4MoCR5cA5Mj3anXeCElVJyPifTN3jnhLF7CGFGJBSbBX6 Rn1Q== X-Gm-Message-State: AOAM530yAw7Ep7pDv9CuwWl40tsVWiFgcl8vo6tPVezjJ+slIoQcWHsq P0rqxGimNtakVviYcocCeLJhzmV8t63y7A== X-Google-Smtp-Source: ABdhPJyJmrCSMA56pJPeAfpgmEtFcocp0B/dJGZTcEPYL0x7iUbPfmbRNXtKmDs5IB5e4iJlsiBnlg== X-Received: by 2002:a63:2001:: with SMTP id g1mr14787435pgg.83.1612752388642; Sun, 07 Feb 2021 18:46:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 02/15] tcg/arm: Add host vector framework Date: Sun, 7 Feb 2021 18:46:12 -0800 Message-Id: <20210208024625.271018-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208024625.271018-1-richard.henderson@linaro.org> References: <20210208024625.271018-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Add registers and function stubs. The functionality is disabled via use_neon_instructions defined to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target-con-set.h | 4 ++ tcg/arm/tcg-target-con-str.h | 1 + tcg/arm/tcg-target.h | 48 ++++++++++++-- tcg/arm/tcg-target.opc.h | 12 ++++ tcg/arm/tcg-target.c.inc | 124 ++++++++++++++++++++++++++++++----- 5 files changed, 165 insertions(+), 24 deletions(-) create mode 100644 tcg/arm/tcg-target.opc.h diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h index ab63e089c2..27aced5391 100644 --- a/tcg/arm/tcg-target-con-set.h +++ b/tcg/arm/tcg-target-con-set.h @@ -13,11 +13,14 @@ C_O0_I1(r) C_O0_I2(r, r) C_O0_I2(r, rIN) C_O0_I2(s, s) +C_O0_I2(w, r) C_O0_I3(s, s, s) C_O0_I4(r, r, rI, rI) C_O0_I4(s, s, s, s) C_O1_I1(r, l) C_O1_I1(r, r) +C_O1_I1(w, r) +C_O1_I1(w, wr) C_O1_I2(r, 0, rZ) C_O1_I2(r, l, l) C_O1_I2(r, r, r) @@ -26,6 +29,7 @@ C_O1_I2(r, r, rIK) C_O1_I2(r, r, rIN) C_O1_I2(r, r, ri) C_O1_I2(r, rZ, rZ) +C_O1_I2(w, w, w) C_O1_I4(r, r, r, rI, rI) C_O1_I4(r, r, rIN, rIK, 0) C_O2_I1(r, r, l) diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h index a0ab7747db..255a1ae0e2 100644 --- a/tcg/arm/tcg-target-con-str.h +++ b/tcg/arm/tcg-target-con-str.h @@ -11,6 +11,7 @@ REGS('r', ALL_GENERAL_REGS) REGS('l', ALL_QLOAD_REGS) REGS('s', ALL_QSTORE_REGS) +REGS('w', ALL_VECTOR_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 8d1fee6327..a9dc09bd08 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -78,19 +78,38 @@ typedef enum { TCG_REG_R13, TCG_REG_R14, TCG_REG_PC, + + TCG_REG_Q0, + TCG_REG_Q1, + TCG_REG_Q2, + TCG_REG_Q3, + TCG_REG_Q4, + TCG_REG_Q5, + TCG_REG_Q6, + TCG_REG_Q7, + TCG_REG_Q8, + TCG_REG_Q9, + TCG_REG_Q10, + TCG_REG_Q11, + TCG_REG_Q12, + TCG_REG_Q13, + TCG_REG_Q14, + TCG_REG_Q15, + + TCG_AREG0 =3D TCG_REG_R6, + TCG_REG_CALL_STACK =3D TCG_REG_R13, } TCGReg; =20 -#define TCG_TARGET_NB_REGS 16 +#define TCG_TARGET_NB_REGS 32 =20 #ifdef __ARM_ARCH_EXT_IDIV__ #define use_idiv_instructions 1 #else extern bool use_idiv_instructions; #endif - +#define use_neon_instructions 0 =20 /* used for function call generation */ -#define TCG_REG_CALL_STACK TCG_REG_R13 #define TCG_TARGET_STACK_ALIGN 8 #define TCG_TARGET_CALL_ALIGN_ARGS 1 #define TCG_TARGET_CALL_STACK_OFFSET 0 @@ -128,9 +147,26 @@ extern bool use_idiv_instructions; #define TCG_TARGET_HAS_direct_jump 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 -enum { - TCG_AREG0 =3D TCG_REG_R6, -}; +#define TCG_TARGET_HAS_v64 use_neon_instructions +#define TCG_TARGET_HAS_v128 use_neon_instructions +#define TCG_TARGET_HAS_v256 0 + +#define TCG_TARGET_HAS_andc_vec 0 +#define TCG_TARGET_HAS_orc_vec 0 +#define TCG_TARGET_HAS_not_vec 0 +#define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rots_vec 0 +#define TCG_TARGET_HAS_rotv_vec 0 +#define TCG_TARGET_HAS_shi_vec 0 +#define TCG_TARGET_HAS_shs_vec 0 +#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_cmpsel_vec 0 =20 #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h new file mode 100644 index 0000000000..7a4578e9b4 --- /dev/null +++ b/tcg/arm/tcg-target.opc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2019 Linaro + * + * This work is licensed under the terms of the GNU GPL, version 2 or + * (at your option) any later version. + * + * See the COPYING file in the top-level directory for details. + * + * Target-specific opcodes for host vector expansion. These will be + * emitted by tcg_expand_vec_op. For those familiar with GCC internals, + * consider these to be UNSPEC with names. + */ diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index eb4f42e53d..9bb354abce 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -40,22 +40,10 @@ bool use_idiv_instructions; =20 #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { - "%r0", - "%r1", - "%r2", - "%r3", - "%r4", - "%r5", - "%r6", - "%r7", - "%r8", - "%r9", - "%r10", - "%r11", - "%r12", - "%r13", - "%r14", - "%pc", + "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", + "%r8", "%r9", "%r10", "%r11", "%r12", "%sp", "%r14", "%pc", + "%q0", "%q1", "%q2", "%q3", "%q4", "%q5", "%q6", "%q7", + "%q8", "%q9", "%q10", "%q11", "%q12", "%q13", "%q14", "%q15", }; #endif =20 @@ -75,6 +63,23 @@ static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_R3, TCG_REG_R12, TCG_REG_R14, + + TCG_REG_Q0, + TCG_REG_Q1, + TCG_REG_Q2, + TCG_REG_Q3, + TCG_REG_Q4, + TCG_REG_Q5, + TCG_REG_Q6, + TCG_REG_Q7, + TCG_REG_Q8, + TCG_REG_Q9, + TCG_REG_Q10, + TCG_REG_Q11, + TCG_REG_Q12, + TCG_REG_Q13, + TCG_REG_Q14, + TCG_REG_Q15, }; =20 static const int tcg_target_call_iarg_regs[4] =3D { @@ -85,6 +90,7 @@ static const int tcg_target_call_oarg_regs[2] =3D { }; =20 #define TCG_REG_TMP TCG_REG_R12 +#define TCG_VEC_TMP TCG_REG_Q15 =20 enum arm_cond_code_e { COND_EQ =3D 0x0, @@ -238,6 +244,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int ty= pe, #define TCG_CT_CONST_ZERO 0x800 =20 #define ALL_GENERAL_REGS 0xffffu +#define ALL_VECTOR_REGS 0xffff0000u =20 /* * r0-r2 will be overwritten when reading the tlb entry (softmmu only) @@ -2117,6 +2124,22 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_qemu_st_i64: return TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, = s, s, s); =20 + case INDEX_op_st_vec: + return C_O0_I2(w, r); + case INDEX_op_ld_vec: + case INDEX_op_dupm_vec: + return C_O1_I1(w, r); + case INDEX_op_dup_vec: + return C_O1_I1(w, wr); + case INDEX_op_dup2_vec: + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_xor_vec: + case INDEX_op_or_vec: + case INDEX_op_and_vec: + case INDEX_op_cmp_vec: + return C_O1_I2(w, w, w); + default: g_assert_not_reached(); } @@ -2126,12 +2149,18 @@ static void tcg_target_init(TCGContext *s) { /* Only probe for the platform and capabilities if we havn't already determined maximum values at compile time. */ -#ifndef use_idiv_instructions +#if !defined(use_idiv_instructions) || !defined(use_neon_instructions) { unsigned long hwcap =3D qemu_getauxval(AT_HWCAP); +#ifndef use_idiv_instructions use_idiv_instructions =3D (hwcap & HWCAP_ARM_IDIVA) !=3D 0; +#endif +#ifndef use_neon_instructions + use_neon_instructions =3D (hwcap & HWCAP_ARM_NEON) !=3D 0; +#endif } #endif + if (__ARM_ARCH < 7) { const char *pl =3D (const char *)qemu_getauxval(AT_PLATFORM); if (pl !=3D NULL && pl[0] =3D=3D 'v' && pl[1] >=3D '4' && pl[1] <= =3D '9') { @@ -2139,7 +2168,7 @@ static void tcg_target_init(TCGContext *s) } } =20 - tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffff; + tcg_target_available_regs[TCG_TYPE_I32] =3D ALL_GENERAL_REGS; =20 tcg_target_call_clobber_regs =3D 0; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); @@ -2149,10 +2178,33 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); =20 + if (use_neon_instructions) { + tcg_target_available_regs[TCG_TYPE_V64] =3D ALL_VECTOR_REGS; + tcg_target_available_regs[TCG_TYPE_V128] =3D ALL_VECTOR_REGS; + + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q4); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q5); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q6); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q7); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15); + } + s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); + tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); } =20 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, @@ -2186,6 +2238,42 @@ static inline void tcg_out_movi(TCGContext *s, TCGTy= pe type, tcg_out_movi32(s, COND_AL, ret, arg); } =20 +static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg rd, TCGReg rs) +{ + g_assert_not_reached(); +} + +static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg rd, TCGReg base, intptr_t offset) +{ + g_assert_not_reached(); +} + +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg rd, int64_t v64) +{ + g_assert_not_reached(); +} + +static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg *args, const int *const_args) +{ + g_assert_not_reached(); +} + +int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) +{ + return 0; +} + +void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, + TCGArg a0, ...) +{ + g_assert_not_reached(); +} + static void tcg_out_nop_fill(tcg_insn_unit *p, int count) { int i; --=20 2.25.1 From nobody Tue Nov 18 07:46:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id h8sm8966092pfv.154.2021.02.07.18.46.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:46:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9bijHvwBQCD14g7ZYkVUD/H8VwEqKYEjAl6bbEzCNaE=; b=hxdxnbLiLpfzxsjOC26i7Ae+oEYcniiarqUCQwyYnyXnHTZTjDQI5rvN7MeM921gOi vG5UYXCOWG3CwaGA2TrRMDJ8No9gN1Ov68yyAJXYtaHxZ3U00tu4Td2kaZb1cr3z+Kuy 8hmGrRKcpwv60YE8yjvoUh5jHM3eM8DU/bqLTwkwABNxLdXL49IZUe/EWSN8G4GYGj9/ m/ZJkGJv3kPRp0BB5btAMQKydYioREirBLZc1qOkm7SdIQnvTmkN+zC1yccJrP4qST9W OwaSDccZt4cU3fdxz/QaIh4p6NKz1hfFw4CzHY2qiSXo+MLB7CyYglGi0M9HBe19G74N EC5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9bijHvwBQCD14g7ZYkVUD/H8VwEqKYEjAl6bbEzCNaE=; b=NK9vqOaK0BYQsf/t3oqjibplRZWzLYtgkCGhh2IqThKKIQDoqTBREcLQP1utd9vhCr MSsIJ8/6LDnMVBQ1A3J04l8sseFQiXQUECVLA0otvzObggEfgWz04gK1nPPd5zPIMnLs AyTE79mly9yqyJo1EGHiOZq8fTse+HxSDnVA8CSVVCmkO1fb6TNU7c+EYlnRAgcayxUY WOOddFhvJMpAIV21Vi6W1JETgCHQA8zMehRonwShb8zdus9dlk7wGjHJVYEYOAAcKUnf tJLDDQJoVrCSQH3dwEnRiJapQ+PJoEzI6JhUZPrth2K8HuGX3ssjajAYYZnUGOzv4nSJ 3Wlw== X-Gm-Message-State: AOAM531poN73YmgmCjCNWhCUmGSB6Nc5rE3Fq76pH4oeKB2LTLu6ggPp 6BVPRLcwe4Ug4Xd6QzTAnFz1GFWtgGdxCA== X-Google-Smtp-Source: ABdhPJwnZZ5BmZjn7RoHzrVlT4S4xsqtwarfg26Kj5rUVZOL+yA4GA7u3rL4p6DjF43FK0z4Kv7Zkw== X-Received: by 2002:a17:902:724c:b029:e1:4aae:c72 with SMTP id c12-20020a170902724cb02900e14aae0c72mr14193565pll.81.1612752389825; Sun, 07 Feb 2021 18:46:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 03/15] tcg/arm: Implement tcg_out_ld/st for vector types Date: Sun, 7 Feb 2021 18:46:13 -0800 Message-Id: <20210208024625.271018-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208024625.271018-1-richard.henderson@linaro.org> References: <20210208024625.271018-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.c.inc | 70 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 64 insertions(+), 6 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 9bb354abce..ca9a71ca64 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -175,6 +175,9 @@ typedef enum { INSN_NOP_v6k =3D 0xe320f000, /* Otherwise the assembler uses mov r0,r0 */ INSN_NOP_v4 =3D (COND_AL << 28) | ARITH_MOV, + + INSN_VLD1 =3D 0xf4200000, /* VLD1 (multiple single elements) */ + INSN_VST1 =3D 0xf4000000, /* VST1 (multiple single elements) */ } ARMInsn; =20 #define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) @@ -1096,6 +1099,33 @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCG= Arg *args, } } =20 +/* + * Note that TCGReg references Q-registers. + * Q-regno =3D 2 * D-regno, so shift left by 1 whlie inserting. + */ +static uint32_t encode_vd(TCGReg rd) +{ + tcg_debug_assert(rd >=3D TCG_REG_Q0); + return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13); +} + +static void tcg_out_vldst(TCGContext *s, ARMInsn insn, + TCGReg rd, TCGReg rn, int offset) +{ + if (offset !=3D 0) { + if (check_fit_imm(offset) || check_fit_imm(-offset)) { + tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, + TCG_REG_TMP, rn, offset, true); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, + TCG_REG_TMP, TCG_REG_TMP, rn, 0); + } + rn =3D TCG_REG_TMP; + } + tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); +} + #ifdef CONFIG_SOFTMMU #include "../tcg-ldst.c.inc" =20 @@ -2207,16 +2237,44 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); } =20 -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) { - tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); + switch (type) { + case TCG_TYPE_I32: + tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); + return; + case TCG_TYPE_V64: + /* regs 1; size 8; align 8 */ + tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); + return; + case TCG_TYPE_V128: + /* regs 2; size 8; align 16 */ + tcg_out_vldst(s, INSN_VLD1 | 0xae0, arg, arg1, arg2); + return; + default: + g_assert_not_reached(); + } } =20 -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) { - tcg_out_st32(s, COND_AL, arg, arg1, arg2); + switch (type) { + case TCG_TYPE_I32: + tcg_out_st32(s, COND_AL, arg, arg1, arg2); + return; + case TCG_TYPE_V64: + /* regs 1; size 8; align 8 */ + tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); + return; + case TCG_TYPE_V128: + /* regs 2; size 8; align 16 */ + tcg_out_vldst(s, INSN_VST1 | 0xae0, arg, arg1, arg2); + return; + default: + g_assert_not_reached(); + } } =20 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, --=20 2.25.1 From nobody Tue Nov 18 07:46:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612755423; cv=none; d=zohomail.com; s=zohoarc; b=EC9krO0ZNdbf56HWQyfRnxTjI/8KMugcQfGoWKNj4tBvUkqOh9Dk7iLeQDFDD7qZi822ROKjtxlIkuMIeNY4lsSEfE6cM71qHQf/ppCg9xpyZsSxnroP0M6mIelNkdvc7ysa7rATMlhHarknt06TSe6pS1siEz/i6fgoPdB1fUQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612755423; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yE3f2/oY1Ir+OoAlm4KxbjGgymDSzAcdp4+YBVGpF4Q=; b=U7x+nwbp7+cZVqlikTklBKpZI2xnctZpQVhW8jlWMhDx6mhmeW33c48nL72fVelFxCjaJWmEC7N34UHc6SzoW1kXcA/ajUR5DuqQvJOzt+fuF1dBCmWDWnXWod3hYu5s80csy/eMld8l2/XJvjKmsQ1ANdlOc6y3FXA/pLHchy8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612755423591563.7492275811707; Sun, 7 Feb 2021 19:37:03 -0800 (PST) Received: from localhost ([::1]:50496 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8xME-0004Ct-FF for importer@patchew.org; Sun, 07 Feb 2021 22:37:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59418) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wZO-0003ou-BY for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:46:34 -0500 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:38268) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wZM-0008WP-FD for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:46:33 -0500 Received: by mail-pg1-x531.google.com with SMTP id m2so2533709pgq.5 for ; Sun, 07 Feb 2021 18:46:31 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id h8sm8966092pfv.154.2021.02.07.18.46.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:46:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=yE3f2/oY1Ir+OoAlm4KxbjGgymDSzAcdp4+YBVGpF4Q=; b=Vd+LXf0uGVHaSbYrvU8h5yCXuFtF8X024oeLxHjvIUDGeW1YhgfWyXdaAh9/fFNF4P G7WXT3n9EjgV+cui7E7OTM/efff/3xSDlJU8stcJ27+OGQRtuxjqW87hQIsiyh7Yh7LI yzTKtPlyZ+SlXobq7ckzn7z1YVZPTn4FZvevJaZl/2uDoocN80S4ZhYac/Xb311qhY3M 3XSbYgFBsYTkZ8O0p/OfQ1sNTx0Sqh9yBIBApRXpJlQqjIxNCsCBzZHtOjoyYBYH30MO 2RkkZXVNGRmSBYQ3/1xSoa2bDMfQdXo0PMIPfnO+BkEDIgg8uY3qc31pmdqFqadN9vpm 6Plg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yE3f2/oY1Ir+OoAlm4KxbjGgymDSzAcdp4+YBVGpF4Q=; b=nL0c/8Inu7AO7mAbnjtcoILZ6tisUaGvl5gMUR6NMiMyVi1VD4rzhVcq15By9BEx9a bubdWeHM6B3RTEMaxYunc/vKz+F0/lejbCtBVlMQNqkGk1YXRtAUE/bjA5/fQDILW3f8 UoNyJnaLXTZfaljmqiIHmFnDtxA8lWPbBniQXRj20xzacq/nz/PQw1EfZ7ABU0pPNNxZ Izo51eqPtlSn1jC84Euj39PmM1Hb5P3DyAKf6VCD0afdl2cv2uv8LFaZNIlaYy43e9h+ oc8TQFmrjE8uVF4Vh4GMyKXyDoIGtkVFo8zbFd+l5UnHQXzq0wqiVzmP3QvZCU48b8N5 XjzQ== X-Gm-Message-State: AOAM532QxzCp5DnnJ7gSk7UIG62rcB/CkE5gskKCXe4ID+Nxn55aj9Ik Ge5vdjGO/NDewcgSheC3FzpJZ5lm5QOnIA== X-Google-Smtp-Source: ABdhPJz5Rk+Es4Mp7johpb2LXs49jdM5IvLj9YEYGF0fnoCPmMnfz77S5g/k3Zz7vSds1L01PtiJ9w== X-Received: by 2002:a63:4d41:: with SMTP id n1mr15398565pgl.147.1612752390839; Sun, 07 Feb 2021 18:46:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 04/15] tcg/arm: Implement tcg_out_mov for vector types Date: Sun, 7 Feb 2021 18:46:14 -0800 Message-Id: <20210208024625.271018-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208024625.271018-1-richard.henderson@linaro.org> References: <20210208024625.271018-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.c.inc | 50 +++++++++++++++++++++++++++++++++++----- 1 file changed, 44 insertions(+), 6 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index ca9a71ca64..20088ac61a 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -178,6 +178,7 @@ typedef enum { =20 INSN_VLD1 =3D 0xf4200000, /* VLD1 (multiple single elements) */ INSN_VST1 =3D 0xf4000000, /* VST1 (multiple single elements) */ + INSN_VMOV =3D 0xf2200110, /* VMOV (register) */ } ARMInsn; =20 #define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) @@ -1109,6 +1110,25 @@ static uint32_t encode_vd(TCGReg rd) return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13); } =20 +static uint32_t encode_vn(TCGReg rn) +{ + tcg_debug_assert(rn >=3D TCG_REG_Q0); + return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17); +} + +static uint32_t encode_vm(TCGReg rm) +{ + tcg_debug_assert(rm >=3D TCG_REG_Q0); + return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1); +} + +static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece, + TCGReg d, TCGReg n, TCGReg m) +{ + tcg_out32(s, insn | (vece << 20) | (q << 6) | + encode_vd(d) | encode_vn(n) | encode_vm(m)); +} + static void tcg_out_vldst(TCGContext *s, ARMInsn insn, TCGReg rd, TCGReg rn, int offset) { @@ -2283,16 +2303,34 @@ static inline bool tcg_out_sti(TCGContext *s, TCGTy= pe type, TCGArg val, return false; } =20 -static inline bool tcg_out_mov(TCGContext *s, TCGType type, - TCGReg ret, TCGReg arg) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { - tcg_out_mov_reg(s, COND_AL, ret, arg); - return true; + if (ret =3D=3D arg) { + return true; + } + switch (type) { + case TCG_TYPE_I32: + if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) { + tcg_out_mov_reg(s, COND_AL, ret, arg); + return true; + } + return false; + + case TCG_TYPE_V64: + case TCG_TYPE_V128: + tcg_out_vreg3(s, INSN_VMOV, type - TCG_TYPE_V64, 0, ret, arg, arg); + return true; + + default: + g_assert_not_reached(); + } } =20 -static inline void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) { + tcg_debug_assert(type =3D=3D TCG_TYPE_I32); + tcg_debug_assert(ret < TCG_REG_Q0); tcg_out_movi32(s, COND_AL, ret, arg); } =20 --=20 2.25.1 From nobody Tue Nov 18 07:46:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612756204; cv=none; d=zohomail.com; s=zohoarc; b=H5vygHtq+0WShwyVf+yY1j9H+kwugJwCc/PZQB2+V9aoxEImnXXvVuW6ilegnT0j5tPdPkW3rL9rKk/S0KAAXgq/PlK/j8OnM1aKX6WTuyZrtSMsXRVyD8jiBd/7Mdee/VNDXklQKFKJyJZI+JuM0ZBkQlRmJ6g32JG3rttW/K8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612756204; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wN62ETAcw8ExmjA+92DaijqMLuMPGunZDBeY6m82h+E=; b=NLgShrx02EyqDFvGXMKX4Eh5DiQiqLWyJW8TAEmmSiZQ7LbmUCB070RM9zTd5+gD8/Hj7KbomlMptjZO0oRwzNZTEht5WNLEjf2AtoBa7J4yVhUUUZV+Svb+Td5KLlM0h5Hj5/0J+DXc8swBADeXIb3sMqYB/iZi4zABO3xW2vk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612756204728289.18470408366363; Sun, 7 Feb 2021 19:50:04 -0800 (PST) Received: from localhost ([::1]:34636 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8xYp-0004QA-ER for importer@patchew.org; Sun, 07 Feb 2021 22:50:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59460) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wZQ-0003u6-Dm for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:46:36 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:45389) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wZN-00005s-SD for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:46:36 -0500 Received: by mail-pl1-x629.google.com with SMTP id b8so7011637plh.12 for ; Sun, 07 Feb 2021 18:46:33 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id h8sm8966092pfv.154.2021.02.07.18.46.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:46:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wN62ETAcw8ExmjA+92DaijqMLuMPGunZDBeY6m82h+E=; b=peI7jvjkWUbz1UKmd59eagM3gP/Ok1cpe2aY3FJ6JccEKbyHEFRR2mjpgIaY5fYn6c ZuS5uBXvkSQbJUzynMtxf8xHULLAUQIBAomuLqsyFMmYk8kimcoabBdrkLgsudQx4iBb kYOu11MtcksnxYxKhw4W0KOk9ZSR2i5Wv47u8vVqHoZNMF+qW421B74vekNN8RVxQ5rr UJUSEuAwHz3rWidN9ETTPC5hSKRkSVDjbjxYyRdyBtjzI3Iwbl9oG1KwzoCfMgNzMHzY XH6QrbWw7DTAVufWeNxQDX5pIuTk85ODXC+ErjHhcLnanYeEFA3V51XkFmfiADEzZ0WO dkXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wN62ETAcw8ExmjA+92DaijqMLuMPGunZDBeY6m82h+E=; b=T+WZlCVfHpB3s94yYj2trtuLe0VYT91+3nNOTpAu2yu73gOaxDv9SM5Nj1DA/UC3OM 3nvIyxyxLz7jHegNES+AABanPcQeQLS8sypRZ2zvBDbBOxqBde9JRhC5qP52kVLblPcj Yj+1qGQeVZbNTTQg5DAmnvKzYTuzEonRnginWp4v06mMNcllHa1LgxJgcLomEBkrF9nj U06hPFO1PwQXTbKfsZ9QUAaSK6M4hsh6wR1bLWuQS4lTu1l56jNs4dvTuy1bl6rnskk5 EJzT4YNRVJyDHlHAGGfhQQBxA21OI4S2T/WBmrffwVdp95MNC2gkbjLo+nLxfSuopbOo HUTg== X-Gm-Message-State: AOAM53379UfEXfRE7WXu2XqZsY5+avAdjopq3ySmJUwfjyXM8O7ckmtV MPEzYHGMOQW7dKO9XpssG3YhmR2FmQRcmg== X-Google-Smtp-Source: ABdhPJxEmnmjUCY4GZi4DKFttbmURec0Hewzy0yxcT8PAq/2LYLUaIE35iQI0CYwOKKUDWb83kJThA== X-Received: by 2002:a17:902:c144:b029:e2:e579:2afa with SMTP id 4-20020a170902c144b02900e2e5792afamr1038048plj.64.1612752392196; Sun, 07 Feb 2021 18:46:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 05/15] tcg/arm: Implement tcg_out_dup*_vec Date: Sun, 7 Feb 2021 18:46:15 -0800 Message-Id: <20210208024625.271018-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208024625.271018-1-richard.henderson@linaro.org> References: <20210208024625.271018-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Most of dupi is copied from tcg/aarch64, which has the same encoding for AdvSimdExpandImm. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.c.inc | 283 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 275 insertions(+), 8 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 20088ac61a..73a4d50a4a 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -176,9 +176,14 @@ typedef enum { /* Otherwise the assembler uses mov r0,r0 */ INSN_NOP_v4 =3D (COND_AL << 28) | ARITH_MOV, =20 + INSN_VDUP_G =3D 0xee800b10, /* VDUP (ARM core register) */ + INSN_VDUP_S =3D 0xf3b00c00, /* VDUP (scalar) */ + INSN_VLDR_D =3D 0xed100b00, /* VLDR.64 */ INSN_VLD1 =3D 0xf4200000, /* VLD1 (multiple single elements) */ + INSN_VLD1R =3D 0xf4a00c00, /* VLD1 (single element to all lanes) = */ INSN_VST1 =3D 0xf4000000, /* VST1 (multiple single elements) */ INSN_VMOV =3D 0xf2200110, /* VMOV (register) */ + INSN_VMOVI =3D 0xf2800010, /* VMOV (immediate) */ } ARMInsn; =20 #define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) @@ -197,6 +202,14 @@ static const uint8_t tcg_cond_to_arm_cond[] =3D { [TCG_COND_GTU] =3D COND_HI, }; =20 +static int encode_imm(uint32_t imm); + +/* TCG private relocation type: add with pc+imm8 */ +#define R_ARM_PC8 11 + +/* TCG private relocation type: vldr with imm8 << 2 */ +#define R_ARM_PC11 12 + static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { const tcg_insn_unit *src_rx =3D tcg_splitwx_to_rx(src_rw); @@ -228,16 +241,52 @@ static bool reloc_pc13(tcg_insn_unit *src_rw, const t= cg_insn_unit *target) return false; } =20 +static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target) +{ + const tcg_insn_unit *src_rx =3D tcg_splitwx_to_rx(src_rw); + ptrdiff_t offset =3D (tcg_ptr_byte_diff(target, src_rx) - 8) / 4; + + if (offset >=3D -0xff && offset <=3D 0xff) { + tcg_insn_unit insn =3D *src_rw; + bool u =3D (offset >=3D 0); + if (!u) { + offset =3D -offset; + } + insn =3D deposit32(insn, 23, 1, u); + insn =3D deposit32(insn, 0, 8, offset); + *src_rw =3D insn; + return true; + } + return false; +} + +static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target) +{ + const tcg_insn_unit *src_rx =3D tcg_splitwx_to_rx(src_rw); + ptrdiff_t offset =3D tcg_ptr_byte_diff(target, src_rx) - 8; + int rot =3D encode_imm(offset); + + if (rot >=3D 0) { + *src_rw =3D deposit32(*src_rw, 0, 12, rol32(offset, rot) | (rot <<= 7)); + return true; + } + return false; +} + static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { tcg_debug_assert(addend =3D=3D 0); - - if (type =3D=3D R_ARM_PC24) { + switch (type) { + case R_ARM_PC24: return reloc_pc24(code_ptr, (const tcg_insn_unit *)value); - } else if (type =3D=3D R_ARM_PC13) { + case R_ARM_PC13: return reloc_pc13(code_ptr, (const tcg_insn_unit *)value); - } else { + case R_ARM_PC11: + return reloc_pc11(code_ptr, (const tcg_insn_unit *)value); + case R_ARM_PC8: + return reloc_pc8(code_ptr, (const tcg_insn_unit *)value); + default: g_assert_not_reached(); } } @@ -277,7 +326,7 @@ static inline uint32_t rotl(uint32_t val, int n) =20 /* ARM immediates for ALU instructions are made of an unsigned 8-bit right-rotated by an even amount between 0 and 30. */ -static inline int encode_imm(uint32_t imm) +static int encode_imm(uint32_t imm) { int shift; =20 @@ -304,6 +353,79 @@ static inline int check_fit_imm(uint32_t imm) return encode_imm(imm) >=3D 0; } =20 +/* Return true if v16 is a valid 16-bit shifted immediate. */ +static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) +{ + if (v16 =3D=3D (v16 & 0xff)) { + *cmode =3D 0x8; + *imm8 =3D v16 & 0xff; + return true; + } else if (v16 =3D=3D (v16 & 0xff00)) { + *cmode =3D 0xa; + *imm8 =3D v16 >> 8; + return true; + } + return false; +} + +/* Return true if v32 is a valid 32-bit shifted immediate. */ +static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) +{ + if (v32 =3D=3D (v32 & 0xff)) { + *cmode =3D 0x0; + *imm8 =3D v32 & 0xff; + return true; + } else if (v32 =3D=3D (v32 & 0xff00)) { + *cmode =3D 0x2; + *imm8 =3D (v32 >> 8) & 0xff; + return true; + } else if (v32 =3D=3D (v32 & 0xff0000)) { + *cmode =3D 0x4; + *imm8 =3D (v32 >> 16) & 0xff; + return true; + } else if (v32 =3D=3D (v32 & 0xff000000)) { + *cmode =3D 0x6; + *imm8 =3D v32 >> 24; + return true; + } + return false; +} + +/* Return true if v32 is a valid 32-bit shifting ones immediate. */ +static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) +{ + if ((v32 & 0xffff00ff) =3D=3D 0xff) { + *cmode =3D 0xc; + *imm8 =3D (v32 >> 8) & 0xff; + return true; + } else if ((v32 & 0xff00ffff) =3D=3D 0xffff) { + *cmode =3D 0xd; + *imm8 =3D (v32 >> 16) & 0xff; + return true; + } + return false; +} + +/* + * Return non-zero if v32 can be formed by MOVI+ORR. + * Place the parameters for MOVI in (cmode, imm8). + * Return the cmode for ORR; the imm8 can be had via extraction from v32. + */ +static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) +{ + int i; + + for (i =3D 6; i > 0; i -=3D 2) { + /* Mask out one byte we can add with ORR. */ + uint32_t tmp =3D v32 & ~(0xffu << (i * 4)); + if (is_shimm32(tmp, cmode, imm8) || + is_soimm32(tmp, cmode, imm8)) { + break; + } + } + return i; +} + /* Test if a constant matches the constraint. * TODO: define constraints for: * @@ -1129,6 +1251,15 @@ static void tcg_out_vreg3(TCGContext *s, ARMInsn ins= n, int q, int vece, encode_vd(d) | encode_vn(n) | encode_vm(m)); } =20 +static void tcg_out_vmovi(TCGContext *s, TCGReg rd, + int q, int op, int cmode, uint8_t imm8) +{ + tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5) + | (cmode << 8) | extract32(imm8, 0, 4) + | (extract32(imm8, 4, 3) << 16) + | (extract32(imm8, 7, 1) << 24)); +} + static void tcg_out_vldst(TCGContext *s, ARMInsn insn, TCGReg rd, TCGReg rn, int offset) { @@ -2334,22 +2465,158 @@ static void tcg_out_movi(TCGContext *s, TCGType ty= pe, tcg_out_movi32(s, COND_AL, ret, arg); } =20 +/* Type is always V128, with I64 elements. */ +static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg r= h) +{ + /* Move high element into place first. */ + /* VMOV Dd+1, Ds */ + tcg_out_vreg3(s, INSN_VMOV | (1 << 12), 0, 0, rd, rh, rh); + /* Move low element into place; tcg_out_mov will check for nop. */ + tcg_out_mov(s, TCG_TYPE_V64, rd, rl); +} + static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg rd, TCGReg rs) { - g_assert_not_reached(); + int q =3D type - TCG_TYPE_V64; + + if (vece =3D=3D MO_64) { + if (type =3D=3D TCG_TYPE_V128) { + tcg_out_dup2_vec(s, rd, rs, rs); + } else { + tcg_out_mov(s, TCG_TYPE_V64, rd, rs); + } + } else if (rs < TCG_REG_Q0) { + int b =3D (vece =3D=3D MO_8); + int e =3D (vece =3D=3D MO_16); + tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) | + encode_vn(rd) | (rs << 12)); + } else { + int imm4 =3D 1 << vece; + tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) | + encode_vd(rd) | encode_vm(rs)); + } + return true; } =20 static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg rd, TCGReg base, intptr_t offset) { - g_assert_not_reached(); + if (vece =3D=3D MO_64) { + tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset); + if (type =3D=3D TCG_TYPE_V128) { + tcg_out_dup2_vec(s, rd, rd, rd); + } + } else { + int q =3D type - TCG_TYPE_V64; + tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5), + rd, base, offset); + } + return true; } =20 static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg rd, int64_t v64) { - g_assert_not_reached(); + int q =3D type - TCG_TYPE_V64; + int cmode, imm8, i; + + /* Test all bytes equal first. */ + if (vece =3D=3D MO_8) { + tcg_out_vmovi(s, rd, q, 0, 0xe, v64); + return; + } + + /* + * Test all bytes 0x00 or 0xff second. This can match cases that + * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. + */ + for (i =3D imm8 =3D 0; i < 8; i++) { + uint8_t byte =3D v64 >> (i * 8); + if (byte =3D=3D 0xff) { + imm8 |=3D 1 << i; + } else if (byte !=3D 0) { + goto fail_bytes; + } + } + tcg_out_vmovi(s, rd, q, 1, 0xe, imm8); + return; + fail_bytes: + + /* + * Tests for various replications. For each element width, if we + * cannot find an expansion there's no point checking a larger + * width because we already know by replication it cannot match. + */ + if (vece =3D=3D MO_16) { + uint16_t v16 =3D v64; + + if (is_shimm16(v16, &cmode, &imm8)) { + tcg_out_vmovi(s, rd, q, 0, cmode, imm8); + return; + } + if (is_shimm16(~v16, &cmode, &imm8)) { + tcg_out_vmovi(s, rd, q, 1, cmode, imm8); + return; + } + + /* + * Otherwise, all remaining constants can be loaded in two insns: + * rd =3D v16 & 0xff, rd |=3D v16 & 0xff00. + */ + tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff); + tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORR */ + return; + } + + if (vece =3D=3D MO_32) { + uint32_t v32 =3D v64; + + if (is_shimm32(v32, &cmode, &imm8) || + is_soimm32(v32, &cmode, &imm8)) { + tcg_out_vmovi(s, rd, q, 0, cmode, imm8); + return; + } + if (is_shimm32(~v32, &cmode, &imm8) || + is_soimm32(~v32, &cmode, &imm8)) { + tcg_out_vmovi(s, rd, q, 1, cmode, imm8); + return; + } + + /* + * Restrict the set of constants to those we can load with + * two instructions. Others we load from the pool. + */ + i =3D is_shimm32_pair(v32, &cmode, &imm8); + if (i) { + tcg_out_vmovi(s, rd, q, 0, cmode, imm8); + tcg_out_vmovi(s, rd, q, 0, i, extract32(v32, i * 4, 8)); + return; + } + i =3D is_shimm32_pair(~v32, &cmode, &imm8); + if (i) { + tcg_out_vmovi(s, rd, q, 1, cmode, imm8); + tcg_out_vmovi(s, rd, q, 1, i, extract32(~v32, i * 4, 8)); + return; + } + } + + /* + * As a last resort, load from the constant pool. + */ + if (!q || vece =3D=3D MO_64) { + new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32); + /* VLDR Dd, [pc + offset] */ + tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16)); + if (q) { + tcg_out_dup2_vec(s, rd, rd, rd); + } + } else { + new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0); + /* add tmp, pc, offset */ + tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0); + tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0); + } } =20 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, --=20 2.25.1 From nobody Tue Nov 18 07:46:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612756366; cv=none; d=zohomail.com; s=zohoarc; b=ZN8E2F2njZv51chPqi6NzF6ptBhhHP/QWgaF0IaGFuQMrRkfnqK5NgXiRv7BMTGKGFWeTOa0gQEFUeKnizR45hkcRRNmJa2Dk7tbH9AH+/ZvxB0MtD4/lsuJHZlwTls3rhBmXeYXt3lpc8jCYspOoIaeNILyJEK7eRRsu8WPGzw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612756366; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=W75wfXsr5vHgZ/Xw8pIcOkmJZCyvCV19MqhyS7btZ5M=; b=AlKbtHgZMC6qP60jijcAyStrj2yZqpARoF55dpn+5xQ8nQSnvQoUBoUXYKdr7gVvp4K6oIHyBj0/0ocd9XJ5fZBM95Q/QkIIKDxFPNbWIiNcNhibySM6ymgvMTxfaj7qk41gD1IjE7A8vN6zhJmzbWVif4IP9OASusNJOm6cKYU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612756366900654.9213040359705; Sun, 7 Feb 2021 19:52:46 -0800 (PST) Received: from localhost ([::1]:43552 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8xbR-0008Jt-Lp for importer@patchew.org; Sun, 07 Feb 2021 22:52:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59466) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wZQ-0003vK-Ro for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:46:36 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:43545) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wZO-00006I-In for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:46:36 -0500 Received: by mail-pf1-x431.google.com with SMTP id q131so8749690pfq.10 for ; Sun, 07 Feb 2021 18:46:34 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id h8sm8966092pfv.154.2021.02.07.18.46.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:46:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=W75wfXsr5vHgZ/Xw8pIcOkmJZCyvCV19MqhyS7btZ5M=; b=NQ5Kb0iBQ45v+G2qvZ/oYd/xPkJvOraM4cZ3QDWQedZcAWzgRfJ7HNiYMIaQjHmM2H 9vFRhGRVdDxTPCU9bH/C3ixmnuvKY9N5WTtteJqrVjLPMmfqSqrlDsEB6KB0Do8Lbszj 71yQC5PbuwXgYj7boMXymD/KOzPeOevGZ57KoVSIS7tCAPheo7roxwA3GY4Rb7Bt8ofI pBHbyiVIiZHWChH8hbQB9OU81UdRcAC7eZknXbcOhQN0PuExFKiBPL4IZUi6LzW0KyuC d6F6QBPQB8Bh8xZ+fr0nKfvrrWRUUxO4CRAeolTtloAF6OZTLrr6jNti02/RGmxmNQTH xQVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W75wfXsr5vHgZ/Xw8pIcOkmJZCyvCV19MqhyS7btZ5M=; b=ZHcp4kCeOQxMi+I5Lwe6LQVlB1x/hwPMe+MsQh4iifmZcv3/91Iy/PjzRX6C+ln4ke QtwEE++fjnIbtDFWhJkUYatF8vFbyLI7PNAZ9sa4/tmEDMaj5pjvgtGUulFleEKrPc/c Sj5Lybwz9aDtC8Cwd289R6MJleWyPclgaD5410fIPPSS0aOv2sRpskP+zxHVKwRXhw/O lVJGUFE9SJLf76Oorhra1LYdxuXDXmVLGykg1/c613WqTJMP8aIDQ91Ow0sqjpBNUm0a eSl5lEazQ4tNd/6cNWbntvfk+izvZk3uPAnn7VQwBsNL+CMPi4kl7+VTATy2qxLEcItH woYw== X-Gm-Message-State: AOAM532w05MYK3dZfMKvVso2mcevPpcrbO3/b/ms1L/59NwTewWKDZSf W0JrPO2beFMLr9kI41z8nu6BDmA8TuMjjg== X-Google-Smtp-Source: ABdhPJxZpqxfbrclV++3zAmSKL/sCd60wUaWBZmOm6e2jA07jMDM4t9aZQDFpT4ljmrUPLOAYHbbHw== X-Received: by 2002:a63:c70c:: with SMTP id n12mr15370632pgg.347.1612752393105; Sun, 07 Feb 2021 18:46:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 06/15] tcg/arm: Implement minimal vector operations Date: Sun, 7 Feb 2021 18:46:16 -0800 Message-Id: <20210208024625.271018-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208024625.271018-1-richard.henderson@linaro.org> References: <20210208024625.271018-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implementing dup2, add, sub, and, or, xor as the minimal set. This allows us to actually enable neon in the header file. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target-con-set.h | 3 + tcg/arm/tcg-target-con-str.h | 2 + tcg/arm/tcg-target.h | 6 +- tcg/arm/tcg-target.c.inc | 203 +++++++++++++++++++++++++++++++++-- 4 files changed, 206 insertions(+), 8 deletions(-) diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h index 27aced5391..f30b3900e0 100644 --- a/tcg/arm/tcg-target-con-set.h +++ b/tcg/arm/tcg-target-con-set.h @@ -30,6 +30,9 @@ C_O1_I2(r, r, rIN) C_O1_I2(r, r, ri) C_O1_I2(r, rZ, rZ) C_O1_I2(w, w, w) +C_O1_I2(w, w, wO) +C_O1_I2(w, w, wV) +C_O1_I2(w, w, wZ) C_O1_I4(r, r, r, rI, rI) C_O1_I4(r, r, rIN, rIK, 0) C_O2_I1(r, r, l) diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h index 255a1ae0e2..8f501149e1 100644 --- a/tcg/arm/tcg-target-con-str.h +++ b/tcg/arm/tcg-target-con-str.h @@ -20,4 +20,6 @@ REGS('w', ALL_VECTOR_REGS) CONST('I', TCG_CT_CONST_ARM) CONST('K', TCG_CT_CONST_INV) CONST('N', TCG_CT_CONST_NEG) +CONST('O', TCG_CT_CONST_ORRI) +CONST('V', TCG_CT_CONST_ANDI) CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index a9dc09bd08..48993636ea 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -107,7 +107,11 @@ typedef enum { #else extern bool use_idiv_instructions; #endif -#define use_neon_instructions 0 +#ifdef __ARM_NEON__ +#define use_neon_instructions 1 +#else +extern bool use_neon_instructions; +#endif =20 /* used for function call generation */ #define TCG_TARGET_STACK_ALIGN 8 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 73a4d50a4a..ae91b959f0 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -30,6 +30,9 @@ int arm_arch =3D __ARM_ARCH; #ifndef use_idiv_instructions bool use_idiv_instructions; #endif +#ifndef use_neon_instructions +bool use_neon_instructions; +#endif =20 /* ??? Ought to think about changing CONFIG_SOFTMMU to always defined. */ #ifdef CONFIG_SOFTMMU @@ -176,6 +179,28 @@ typedef enum { /* Otherwise the assembler uses mov r0,r0 */ INSN_NOP_v4 =3D (COND_AL << 28) | ARITH_MOV, =20 + INSN_VADD =3D 0xf2000800, + INSN_VAND =3D 0xf2000110, + INSN_VEOR =3D 0xf3000110, + INSN_VORR =3D 0xf2200110, + INSN_VSUB =3D 0xf3000800, + + INSN_VMVN =3D 0xf3b00580, + + INSN_VCEQ0 =3D 0xf3b10100, + INSN_VCGT0 =3D 0xf3b10000, + INSN_VCGE0 =3D 0xf3b10080, + INSN_VCLE0 =3D 0xf3b10180, + INSN_VCLT0 =3D 0xf3b10200, + + INSN_VCEQ =3D 0xf3000810, + INSN_VCGE =3D 0xf2000310, + INSN_VCGT =3D 0xf2000300, + INSN_VCGE_U =3D 0xf3000310, + INSN_VCGT_U =3D 0xf3000300, + + INSN_VTST =3D 0xf2000810, + INSN_VDUP_G =3D 0xee800b10, /* VDUP (ARM core register) */ INSN_VDUP_S =3D 0xf3b00c00, /* VDUP (scalar) */ INSN_VLDR_D =3D 0xed100b00, /* VLDR.64 */ @@ -295,6 +320,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int ty= pe, #define TCG_CT_CONST_INV 0x200 #define TCG_CT_CONST_NEG 0x400 #define TCG_CT_CONST_ZERO 0x800 +#define TCG_CT_CONST_ORRI 0x1000 +#define TCG_CT_CONST_ANDI 0x2000 =20 #define ALL_GENERAL_REGS 0xffffu #define ALL_VECTOR_REGS 0xffff0000u @@ -426,6 +453,16 @@ static int is_shimm32_pair(uint32_t v32, int *cmode, i= nt *imm8) return i; } =20 +/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ +static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) +{ + if (v32 =3D=3D deposit32(v32, 16, 16, v32)) { + return is_shimm16(v32, cmode, imm8); + } else { + return is_shimm32(v32, cmode, imm8); + } +} + /* Test if a constant matches the constraint. * TODO: define constraints for: * @@ -446,9 +483,26 @@ static bool tcg_target_const_match(int64_t val, TCGTyp= e type, int ct) return 1; } else if ((ct & TCG_CT_CONST_ZERO) && val =3D=3D 0) { return 1; - } else { - return 0; } + + switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { + case 0: + break; + case TCG_CT_CONST_ANDI: + val =3D ~val; + /* fallthru */ + case TCG_CT_CONST_ORRI: + if (val =3D=3D deposit64(val, 32, 32, val)) { + int cmode, imm8; + return is_shimm1632(val, &cmode, &imm8); + } + break; + default: + /* Both bits should not be set for the same insn. */ + g_assert_not_reached(); + } + + return 0; } =20 static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset) @@ -1244,6 +1298,13 @@ static uint32_t encode_vm(TCGReg rm) return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1); } =20 +static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece, + TCGReg d, TCGReg m) +{ + tcg_out32(s, insn | (vece << 18) | (q << 6) | + encode_vd(d) | encode_vm(m)); +} + static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece, TCGReg d, TCGReg n, TCGReg m) { @@ -2316,10 +2377,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) case INDEX_op_add_vec: case INDEX_op_sub_vec: case INDEX_op_xor_vec: - case INDEX_op_or_vec: - case INDEX_op_and_vec: - case INDEX_op_cmp_vec: return C_O1_I2(w, w, w); + case INDEX_op_or_vec: + return C_O1_I2(w, w, wO); + case INDEX_op_and_vec: + return C_O1_I2(w, w, wV); + case INDEX_op_cmp_vec: + return C_O1_I2(w, w, wZ); =20 default: g_assert_not_reached(); @@ -2619,16 +2683,141 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGTyp= e type, unsigned vece, } } =20 +static const ARMInsn vec_cmp_insn[16] =3D { + [TCG_COND_EQ] =3D INSN_VCEQ, + [TCG_COND_GT] =3D INSN_VCGT, + [TCG_COND_GE] =3D INSN_VCGE, + [TCG_COND_GTU] =3D INSN_VCGT_U, + [TCG_COND_GEU] =3D INSN_VCGE_U, +}; + +static const ARMInsn vec_cmp0_insn[16] =3D { + [TCG_COND_EQ] =3D INSN_VCEQ0, + [TCG_COND_GT] =3D INSN_VCGT0, + [TCG_COND_GE] =3D INSN_VCGE0, + [TCG_COND_LT] =3D INSN_VCLT0, + [TCG_COND_LE] =3D INSN_VCLE0, +}; + static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg *args, const int *const_args) { - g_assert_not_reached(); + TCGType type =3D vecl + TCG_TYPE_V64; + unsigned q =3D vecl; + TCGArg a0, a1, a2; + int cmode, imm8; + + a0 =3D args[0]; + a1 =3D args[1]; + a2 =3D args[2]; + + switch (opc) { + case INDEX_op_ld_vec: + tcg_out_ld(s, type, a0, a1, a2); + return; + case INDEX_op_st_vec: + tcg_out_st(s, type, a0, a1, a2); + return; + case INDEX_op_dupm_vec: + tcg_out_dupm_vec(s, type, vece, a0, a1, a2); + return; + case INDEX_op_dup2_vec: + tcg_out_dup2_vec(s, a0, a1, a2); + return; + case INDEX_op_add_vec: + tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); + return; + case INDEX_op_sub_vec: + tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); + return; + case INDEX_op_xor_vec: + tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); + return; + + case INDEX_op_and_vec: + if (const_args[2]) { + is_shimm1632(~a2, &cmode, &imm8); + if (a0 =3D=3D a1) { + tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */ + return; + } + tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */ + a2 =3D a0; + } + tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2); + return; + + case INDEX_op_or_vec: + if (const_args[2]) { + is_shimm1632(a2, &cmode, &imm8); + if (a0 =3D=3D a1) { + tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORI */ + return; + } + tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */ + a2 =3D a0; + } + tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2); + return; + + case INDEX_op_cmp_vec: + { + TCGCond cond =3D args[3]; + + if (cond =3D=3D TCG_COND_NE) { + if (const_args[2]) { + tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1); + } else { + tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2); + tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); + } + } else { + ARMInsn insn; + + if (const_args[2]) { + insn =3D vec_cmp0_insn[cond]; + if (insn) { + tcg_out_vreg2(s, insn, q, vece, a0, a1); + return; + } + tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); + a2 =3D TCG_VEC_TMP; + } + insn =3D vec_cmp_insn[cond]; + if (insn =3D=3D 0) { + TCGArg t; + t =3D a1, a1 =3D a2, a2 =3D t; + cond =3D tcg_swap_cond(cond); + insn =3D vec_cmp_insn[cond]; + tcg_debug_assert(insn !=3D 0); + } + tcg_out_vreg3(s, insn, q, vece, a0, a1, a2); + } + } + return; + + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ + case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ + default: + g_assert_not_reached(); + } } =20 int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { - return 0; + switch (opc) { + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + return 1; + case INDEX_op_cmp_vec: + return vece < MO_64; + default: + return 0; + } } =20 void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, --=20 2.25.1 From nobody Tue Nov 18 07:46:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id h8sm8966092pfv.154.2021.02.07.18.46.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:46:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6rVYVBn5WKWjGPZSc0x/bTtwmPwu+ICbCV3yAi6cRKw=; b=WqYVjtFZKPdk0fHAYzeYEdQOvGjcZCn8XpufHLnVB/Th9V+9t3hskk2sA7BMVl1bFq B/XTlIEIS8Oi8+xPp0qiwBixQGiM56t+W96egetlzLFePqIc8f0ax5j3Kp1VWmGFIv1f aJtpX0ldHiBgYymAM2ZY/oTjUDEBhdpYwqZj5ITsKGO4oAfA3Ni+/f3UFS8HchTFZukt h1oytjTJMu7nvI8RBhs+Q17fvfDXSxZPHDximDMRiYaK+kLR3lETUG1cgD8hotwOYkav asVVBG2/kXRoerRlAjVHELoDHc0HPcwY3LpMeO7f9z6qRBdlp4nIwI4XCJmmcVYrHzQE kOGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6rVYVBn5WKWjGPZSc0x/bTtwmPwu+ICbCV3yAi6cRKw=; b=nxVSJpMTnJluOAxSF4jBDbARX1WkRX22Id5Wp2XnW6feMyLHWdG4eR12Qs61zHBWSy V0ZlJRiRONuAD3SIi3W1nUJ/OCM42HCl6sr+8QjZ43bGr2f4TJAaxyE7LKppzUZHhaw2 lFHN4V61G5fpJY8iQdC5r8iOhqQqxfhdiL6Q+4igSF2GsvSewUbE45oEMa+n/xbQ7q+V /vZ4PvVz3mFQ5orpJRBrhHh3WhUzj9NNyhzqODhe6jkhYsUW8FC5tvtaASUm9A2UN/uB u1PZU22a+9tVRqXx4sghbDHM6HZl4yo/Z6PcTJ4EwLNLvQIMIl+Y+Id+FJ7UA1rrCjJA N+jg== X-Gm-Message-State: AOAM530tYVFTzsVaZddsPnSOaW8j2i67KV965XS0uud95KYIcJClZaUS 1/T/4jrKD13bDxXoBqNPXjX+9iPkhAXDag== X-Google-Smtp-Source: ABdhPJyom5XhGhpGDDH9z9FBsdN/5RNfdBMgMgFxIQIIBM/314HkFCbnwfyQAM8avNwA5nNfLCdccQ== X-Received: by 2002:aa7:93ad:0:b029:1d5:d9c5:cc08 with SMTP id x13-20020aa793ad0000b02901d5d9c5cc08mr15515054pff.37.1612752394347; Sun, 07 Feb 2021 18:46:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 07/15] tcg/arm: Implement andc, orc, abs, neg, not vector operations Date: Sun, 7 Feb 2021 18:46:17 -0800 Message-Id: <20210208024625.271018-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208024625.271018-1-richard.henderson@linaro.org> References: <20210208024625.271018-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These logical and arithmetic operations are optional, but are trivial to accomplish with the existing infrastructure. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target-con-set.h | 1 + tcg/arm/tcg-target.h | 10 +++++----- tcg/arm/tcg-target.c.inc | 38 ++++++++++++++++++++++++++++++++++++ 3 files changed, 44 insertions(+), 5 deletions(-) diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h index f30b3900e0..cc006f99cd 100644 --- a/tcg/arm/tcg-target-con-set.h +++ b/tcg/arm/tcg-target-con-set.h @@ -20,6 +20,7 @@ C_O0_I4(s, s, s, s) C_O1_I1(r, l) C_O1_I1(r, r) C_O1_I1(w, r) +C_O1_I1(w, w) C_O1_I1(w, wr) C_O1_I2(r, 0, rZ) C_O1_I2(r, l, l) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 48993636ea..6ac9fc6b9b 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -155,11 +155,11 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_v128 use_neon_instructions #define TCG_TARGET_HAS_v256 0 =20 -#define TCG_TARGET_HAS_andc_vec 0 -#define TCG_TARGET_HAS_orc_vec 0 -#define TCG_TARGET_HAS_not_vec 0 -#define TCG_TARGET_HAS_neg_vec 0 -#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_andc_vec 1 +#define TCG_TARGET_HAS_orc_vec 1 +#define TCG_TARGET_HAS_not_vec 1 +#define TCG_TARGET_HAS_neg_vec 1 +#define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rotv_vec 0 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index ae91b959f0..1b31f11f6c 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -181,11 +181,15 @@ typedef enum { =20 INSN_VADD =3D 0xf2000800, INSN_VAND =3D 0xf2000110, + INSN_VBIC =3D 0xf2100110, INSN_VEOR =3D 0xf3000110, + INSN_VORN =3D 0xf2300110, INSN_VORR =3D 0xf2200110, INSN_VSUB =3D 0xf3000800, =20 + INSN_VABS =3D 0xf3b10300, INSN_VMVN =3D 0xf3b00580, + INSN_VNEG =3D 0xf3b10380, =20 INSN_VCEQ0 =3D 0xf3b10100, INSN_VCGT0 =3D 0xf3b10000, @@ -2373,14 +2377,20 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) return C_O1_I1(w, r); case INDEX_op_dup_vec: return C_O1_I1(w, wr); + case INDEX_op_abs_vec: + case INDEX_op_neg_vec: + case INDEX_op_not_vec: + return C_O1_I1(w, w); case INDEX_op_dup2_vec: case INDEX_op_add_vec: case INDEX_op_sub_vec: case INDEX_op_xor_vec: return C_O1_I2(w, w, w); case INDEX_op_or_vec: + case INDEX_op_andc_vec: return C_O1_I2(w, w, wO); case INDEX_op_and_vec: + case INDEX_op_orc_vec: return C_O1_I2(w, w, wV); case INDEX_op_cmp_vec: return C_O1_I2(w, w, wZ); @@ -2725,6 +2735,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_dup2_vec: tcg_out_dup2_vec(s, a0, a1, a2); return; + case INDEX_op_abs_vec: + tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1); + return; + case INDEX_op_neg_vec: + tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1); + return; + case INDEX_op_not_vec: + tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1); + return; case INDEX_op_add_vec: tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); return; @@ -2735,6 +2754,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); return; =20 + case INDEX_op_andc_vec: + if (!const_args[2]) { + tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2); + return; + } + a2 =3D ~a2; + /* fall through */ case INDEX_op_and_vec: if (const_args[2]) { is_shimm1632(~a2, &cmode, &imm8); @@ -2748,6 +2774,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2); return; =20 + case INDEX_op_orc_vec: + if (!const_args[2]) { + tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2); + return; + } + a2 =3D ~a2; + /* fall through */ case INDEX_op_or_vec: if (const_args[2]) { is_shimm1632(a2, &cmode, &imm8); @@ -2810,10 +2843,15 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type= , unsigned vece) case INDEX_op_add_vec: case INDEX_op_sub_vec: case INDEX_op_and_vec: + case INDEX_op_andc_vec: case INDEX_op_or_vec: + case INDEX_op_orc_vec: case INDEX_op_xor_vec: + case INDEX_op_not_vec: return 1; + case INDEX_op_abs_vec: case INDEX_op_cmp_vec: + case INDEX_op_neg_vec: return vece < MO_64; default: return 0; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id h8sm8966092pfv.154.2021.02.07.18.46.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:46:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=gowexwenP0ZkS0ebio3iaGH39rk+PDid2Xbx2FaWzPQ=; b=ozu6WKxaUcgQFi+smw5JwAvyCn75MN9ycWL0nDl6ygTdJYya7Ua6T8S0zIZXd0Ifav hJsghoiLmLlNYp7+tLRKSSuIAt+6ZRG0a1xfsLhAkXGNWRMQaNNatTyX12cbRwN0Hu7X o7l3r0rY6koyx+jgTniX6AudQkzkgYVOTASd7aTBn376fVXgF2gSYa86OwuRIl1vqAma +QlQiHjyLR0WSCZ0w2+t1u5UAPXW4pGi1eYRPfGqAfLlEBxOAQUQRbjU5Y7p5bLROTB0 Re1Fonj6VHCblxrdpruS2rGNVCioAyCi07hOzB1UtsmA9D30562cwbtkF/js4tVclxjg EzrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gowexwenP0ZkS0ebio3iaGH39rk+PDid2Xbx2FaWzPQ=; b=fdjACJAICHUfvs33I/YdE5hzh+hWV7Hfb3KFPkq81dNmk81oONGcPSv1qwh4Vjibh8 o4tushswA5D8avApdG2fwFxWEt8qjtHvSQ+PTafSNY5rXNmZEbnZ41SngvIjS6Go89tX I6yQrTC23pR6W1RsDWF09EJyLE4on4EO2Ioflj+Fg60ig/ARkrDgjuD1zOgL78HI5GUT C/jMuZ3wVjvvyLU/I/OBBYt1nem68pu8WaN8+j94ocCxxeEXlY1c+FH0ahYV8dk38f3l lnhVvs9acBVT0CtYncea5KRIRtZv4NAkBjHYXmYNtM+LZA/CgJ5iWuxAxpFXRj1Yvl2h CAow== X-Gm-Message-State: AOAM532n4JiM3Qt1L36BmbMJJM06jzlsPXzXbjmVoQagmZWtREJfRPz2 HouAci45tZM2ecKAcLZbFYEhR7KRt6YO4g== X-Google-Smtp-Source: ABdhPJy/GbMzIwhDyZ4iENheOA6KYP1tESC0U4d0ovkSRXw92EpYsgya0B9TO2j1iatK+TX3VZKBGg== X-Received: by 2002:a17:902:a517:b029:de:79a7:48d9 with SMTP id s23-20020a170902a517b02900de79a748d9mr14174678plq.45.1612752395555; Sun, 07 Feb 2021 18:46:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 08/15] tcg/arm: Implement TCG_TARGET_HAS_shi_vec Date: Sun, 7 Feb 2021 18:46:18 -0800 Message-Id: <20210208024625.271018-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208024625.271018-1-richard.henderson@linaro.org> References: <20210208024625.271018-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This consists of the three immediate shifts: shli, shri, sari. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 6ac9fc6b9b..cfbadad72c 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -163,7 +163,7 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rotv_vec 0 -#define TCG_TARGET_HAS_shi_vec 0 +#define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_mul_vec 0 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 1b31f11f6c..22cf44263c 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -203,6 +203,10 @@ typedef enum { INSN_VCGE_U =3D 0xf3000310, INSN_VCGT_U =3D 0xf3000300, =20 + INSN_VSHLI =3D 0xf2800510, /* VSHL (immediate) */ + INSN_VSARI =3D 0xf2800010, /* VSHR.S */ + INSN_VSHRI =3D 0xf3800010, /* VSHR.U */ + INSN_VTST =3D 0xf2000810, =20 INSN_VDUP_G =3D 0xee800b10, /* VDUP (ARM core register) */ @@ -1325,6 +1329,14 @@ static void tcg_out_vmovi(TCGContext *s, TCGReg rd, | (extract32(imm8, 7, 1) << 24)); } =20 +static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q, + TCGReg rd, TCGReg rm, int l_imm6) +{ + tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) | + (extract32(l_imm6, 6, 1) << 7) | + (extract32(l_imm6, 0, 6) << 16)); +} + static void tcg_out_vldst(TCGContext *s, ARMInsn insn, TCGReg rd, TCGReg rn, int offset) { @@ -2380,6 +2392,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_abs_vec: case INDEX_op_neg_vec: case INDEX_op_not_vec: + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + case INDEX_op_sari_vec: return C_O1_I1(w, w); case INDEX_op_dup2_vec: case INDEX_op_add_vec: @@ -2753,6 +2768,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_xor_vec: tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); return; + case INDEX_op_shli_vec: + tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece)); + return; + case INDEX_op_shri_vec: + tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2); + return; + case INDEX_op_sari_vec: + tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2); + return; =20 case INDEX_op_andc_vec: if (!const_args[2]) { @@ -2848,6 +2872,9 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_orc_vec: case INDEX_op_xor_vec: case INDEX_op_not_vec: + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + case INDEX_op_sari_vec: return 1; case INDEX_op_abs_vec: case INDEX_op_cmp_vec: --=20 2.25.1 From nobody Tue Nov 18 07:46:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612755239; cv=none; d=zohomail.com; s=zohoarc; b=EtpTcPgDxzwTt8rGXWzWKXJQnjEUbGjQ1NZqB2+Of1aaxVQhP9mlchOppg+u4EycFmbm22cErYiZoHup5kBxxLIVKZ6EkxZWRWy4PN8mMRwnlyk0tBB1qvBhVbWaK7hs7qPNuj9e5YL7qzFQodyXiJDXjLJJlh/AKebFL9lmDXw= ARC-Message-Signature: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id h8sm8966092pfv.154.2021.02.07.18.46.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:46:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/AzDllaOuL4/tCcbjroolDQHo5rSKdBK4IPEUTo/Uds=; b=SeY4KXchtT4+uv9ayHeamUlIclt3KOlghHukNVX+9Rst/9+koKJPeVaEF11uSEttll wsWM0vN/SSt+jxQTHeCYCx8wREGNDk8mkXWm2MNd3OhM2bcoWDrnurjM2t6kcepqwXeV rYVWljj4KzlCzJBTsHVIPCttFLbA/QAgI9Yqi8Bu5dVwrSQEdJHqdSX7pJKYtmZFbPd2 zqvHefTMelRmMpXBguPVUw4ar0SUrVd3LDgu0hiIQV40jMZGz0TUkyegibTKzoFeGIvC U9iECSooEX/uB3OllecCaOaqeeBv41Bi8PlNcuxEqGvFb/L41cqVjVhjAraZmUe7rEaY JUYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/AzDllaOuL4/tCcbjroolDQHo5rSKdBK4IPEUTo/Uds=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index cfbadad72c..94d768f249 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -166,7 +166,7 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 -#define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 0 #define TCG_TARGET_HAS_bitsel_vec 0 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 22cf44263c..104da57828 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -186,6 +186,7 @@ typedef enum { INSN_VORN =3D 0xf2300110, INSN_VORR =3D 0xf2200110, INSN_VSUB =3D 0xf3000800, + INSN_VMUL =3D 0xf2000910, =20 INSN_VABS =3D 0xf3b10300, INSN_VMVN =3D 0xf3b00580, @@ -2398,6 +2399,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) return C_O1_I1(w, w); case INDEX_op_dup2_vec: case INDEX_op_add_vec: + case INDEX_op_mul_vec: case INDEX_op_sub_vec: case INDEX_op_xor_vec: return C_O1_I2(w, w, w); @@ -2762,6 +2764,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_add_vec: tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); return; + case INDEX_op_mul_vec: + tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2); + return; case INDEX_op_sub_vec: tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); return; @@ -2878,6 +2883,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) return 1; case INDEX_op_abs_vec: case INDEX_op_cmp_vec: + case INDEX_op_mul_vec: case INDEX_op_neg_vec: return vece < MO_64; default: --=20 2.25.1 From nobody Tue Nov 18 07:46:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612756742; cv=none; d=zohomail.com; s=zohoarc; b=hQqYBY03DSVUrOThsLHiFXI+raohQd6Gdk2zq8MhWnX5x5Aimx5t4r2ziB2GErCdcKffn5KpFMhRFcE7ZyQk1QHuKOQU6MyJU2oaim+U6z6PUnk1LCXwQwGQtkSrw1b2+O+gGiYotbq76VJgX5bqSQEbB+eBW4yRdHifYVJUFXc= ARC-Message-Signature: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id h8sm8966092pfv.154.2021.02.07.18.46.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:46:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vQVeOmFmuH7vnw0L5xO4yDxlWUnTVLCXCuC+IDDzYS0=; b=Xc5m/PrMeSKhVl8JJ26ORsr/n743LPgenP/zxVC2ZI/Ne3yfXsRkgrNJS+L0A2WtJf BX/Kw8PmE1E27+QaM53IdJdFZXkMOb6ZBqh15Ii6Paj0Dw530ymuAPDksZZY52fOqgDd Dgdx/TALjM0XJ/8fGauJNj6njQmXxHfRBpl24RtYLVQ8dGMrbvkZpIqkwLhSihl2sIvT tEMehkfZfFfzMiEHFyRlgWEvAvVCiYgqwWVukTQQTSZ2WAgVP6qCnWHcSaNyfzfKdnoo lv3AqSBCBljd0Ila+gsBDHj8wungRImmqWT6F3IEndRz7EzgsJhiSZq2py+EAB0YxpG0 NH0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vQVeOmFmuH7vnw0L5xO4yDxlWUnTVLCXCuC+IDDzYS0=; b=r+C5kHeXihSZSos5xtLoaJ8mL1kwBDd17d3fTPN7x+Yj1WcJVg0SQjhI5A0JaQ/L5h HPZsmKRcrtjdlZLuYAmzZNPTZwzbjgU6u3NU/Jh56SUqq24MCoDFUaHEsWiDUUBj5XPa pHIa2n9InZSZr8J0X2EwD6hWNykTrg1rpaYvXIRR0R2W3xc6VEbB9nLPFAUVENNwnaxP wdPox/IAWVMAzadyBy/O8Kg4RtZe9jGDAQQihyJemdG76RJ2955jNbC4bfzrwRvcqraI 0ulmhnoervd/uL3YgufLtfI/DPQw7SLcgerairaQ5ZtkCsQwOzTczulHzaSgYRAqFQhe VSgg== X-Gm-Message-State: AOAM531RXEBhL2+cJuMv7EsEYPPFfFhWrcowQBik8gOW0KGfA5IH5d4B hghBqBZHMko21VC4i9bPdAUm3HN5kWhJPQ== X-Google-Smtp-Source: ABdhPJxZmfaAODcvBnBlPUc+29Q9srI8JZtV5UlhAZSXNWIAjUl5HNQr+a6/Xuyy6uVwW6p2JLtR2w== X-Received: by 2002:a17:902:b285:b029:e1:5b44:454 with SMTP id u5-20020a170902b285b02900e15b440454mr14353285plr.54.1612752397611; Sun, 07 Feb 2021 18:46:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 10/15] tcg/arm: Implement TCG_TARGET_HAS_sat_vec Date: Sun, 7 Feb 2021 18:46:20 -0800 Message-Id: <20210208024625.271018-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208024625.271018-1-richard.henderson@linaro.org> References: <20210208024625.271018-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This is saturating add and subtract, signed and unsigned. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 94d768f249..71621f28e9 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -167,7 +167,7 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_mul_vec 1 -#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 0 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 0 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 104da57828..a4c398417a 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -187,6 +187,10 @@ typedef enum { INSN_VORR =3D 0xf2200110, INSN_VSUB =3D 0xf3000800, INSN_VMUL =3D 0xf2000910, + INSN_VQADD =3D 0xf2000010, + INSN_VQADD_U =3D 0xf3000010, + INSN_VQSUB =3D 0xf2000210, + INSN_VQSUB_U =3D 0xf3000210, =20 INSN_VABS =3D 0xf3b10300, INSN_VMVN =3D 0xf3b00580, @@ -2400,7 +2404,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_dup2_vec: case INDEX_op_add_vec: case INDEX_op_mul_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: case INDEX_op_sub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: case INDEX_op_xor_vec: return C_O1_I2(w, w, w); case INDEX_op_or_vec: @@ -2770,6 +2778,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_sub_vec: tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); return; + case INDEX_op_ssadd_vec: + tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2); + return; + case INDEX_op_sssub_vec: + tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2); + return; + case INDEX_op_usadd_vec: + tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2); + return; + case INDEX_op_ussub_vec: + tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2); + return; case INDEX_op_xor_vec: tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); return; @@ -2880,6 +2900,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: return 1; case INDEX_op_abs_vec: case INDEX_op_cmp_vec: --=20 2.25.1 From nobody Tue Nov 18 07:46:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612755658; cv=none; d=zohomail.com; s=zohoarc; b=e9LT9GKP8CBz1kABxSrMRvqUMhFlFF3oAYSeKBiExSUMW8NTrBt1txdqraMZbeMbmXyxwjpDMpWPhqg59i/MdRH8XWaMQLglalLYLvQI7ciQMjyh+2R9qkD/SsBiQ9nHfSk4z6/sshC9MR65/9bn2hnCrGtejShml2bLj04JCFE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612755658; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EMZ7TabXdfCn73maN16PxI+M4OLz/pJ2bqfuMrXpBLc=; b=HppvXNNeFrRbSSyQViwRCD1fs9HVE1w3qP+GQsTMqYzhKzGsEha7ADtH+sgQspEuw2PWJPUavKj06CpfR9wv3AjpRrXXNdUiZzkWcTK1eOYP8zDFGKQkVowbQRDNO0trvfV8vjCusR3My9qbPMZklk9uMNrf5HJoFcTg20fexlo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612755658288495.4719884058653; Sun, 7 Feb 2021 19:40:58 -0800 (PST) Received: from localhost ([::1]:34132 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8xQ1-0000da-5U for importer@patchew.org; Sun, 07 Feb 2021 22:40:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59560) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wZY-00041h-C0 for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:46:46 -0500 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:36583) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wZU-00008I-26 for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:46:44 -0500 Received: by mail-pg1-x529.google.com with SMTP id c132so9269263pga.3 for ; Sun, 07 Feb 2021 18:46:39 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id h8sm8966092pfv.154.2021.02.07.18.46.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:46:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=EMZ7TabXdfCn73maN16PxI+M4OLz/pJ2bqfuMrXpBLc=; b=FcRNeNXlhHbuBRuhOAU9enL3+K809LEkyZoFFWxJrDudHlRLyy6Pk5p8tWfmkziDi0 AcKO42tG5RQyxmSPd3G4cM6pmMGy11DGCyrK+KdVqYBJYwGGhKBQaWXV9GXUxAeLXSbj Taip3f8dKkZcJn3vBImeDUndM4TKevEsgS8/aKdQJyJxQEQsj7+6mJ11AjNKlpqyhIiq +UcueSaax+AoDd9mwelwrOfHl9h4j9wIe0o+hujyYCVn9cUi4YW2Iyu/LT785wwxGiyT 4oeetqu/RDvrhLdReVEnhjEl6i/sNvpX94gpU3kZAyDSz3y13Jtkpnkv8aXBH3zu5uVc SQqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EMZ7TabXdfCn73maN16PxI+M4OLz/pJ2bqfuMrXpBLc=; b=OlBIuxhljWzXgGpt6XmFt297+pkGrnqvSjiTqeeWvmhfOGpwEcp/K4DwhlBtFmXySQ +fesIRo8kAnFMuyumih3xe39+dgaABxui9qiHY9CJ3LUOrWt3LrIdspGl1wZBXcom0o8 IDE1geuwpogFjII6KwRAjdNFJnmr6ybYF0dekoXAXGdbfEA62RKR7F2+fpacCu0mqW2e tHezjgqh4oumx388cWPXeZ7AIsCVPXDHIM+8/nvId6JNNn58pdOAJ+HTlsl1GWEA5si/ Zdr+9xLSUTrLBLbNkdYGeUmfst0POSYIRR2jsJa5pTNbZ2D9u6GEb1ZtyeQVI5IANOcc aX0Q== X-Gm-Message-State: AOAM530iNZnDS9sqREkdxLVgKFiYVMvzFe8OFtkr91L+TX4+e/wo3EPJ 4tA8N38UJDM6lWvawLyNePLHt09GQpKx3g== X-Google-Smtp-Source: ABdhPJzGv3gYKg9JFUfNjRyis+F1zICVjdPY6fGE+ia/5doEF76A7fKDXKFpbmpGATkjutrW2dGwiA== X-Received: by 2002:a65:520d:: with SMTP id o13mr15061464pgp.57.1612752398641; Sun, 07 Feb 2021 18:46:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 11/15] tcg/arm: Implement TCG_TARGET_HAS_minmax_vec Date: Sun, 7 Feb 2021 18:46:21 -0800 Message-Id: <20210208024625.271018-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208024625.271018-1-richard.henderson@linaro.org> References: <20210208024625.271018-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This is minimum and maximu, signed and unsigned. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 71621f28e9..4815a34e75 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -168,7 +168,7 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 -#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 0 =20 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index a4c398417a..afd2807c09 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -191,6 +191,10 @@ typedef enum { INSN_VQADD_U =3D 0xf3000010, INSN_VQSUB =3D 0xf2000210, INSN_VQSUB_U =3D 0xf3000210, + INSN_VMAX =3D 0xf2000600, + INSN_VMAX_U =3D 0xf3000600, + INSN_VMIN =3D 0xf2000610, + INSN_VMIN_U =3D 0xf3000610, =20 INSN_VABS =3D 0xf3b10300, INSN_VMVN =3D 0xf3b00580, @@ -2404,9 +2408,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_dup2_vec: case INDEX_op_add_vec: case INDEX_op_mul_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: case INDEX_op_ssadd_vec: case INDEX_op_sssub_vec: case INDEX_op_sub_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: case INDEX_op_xor_vec: @@ -2775,6 +2783,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_mul_vec: tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2); return; + case INDEX_op_smax_vec: + tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2); + return; + case INDEX_op_smin_vec: + tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2); + return; case INDEX_op_sub_vec: tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); return; @@ -2784,6 +2798,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_sssub_vec: tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2); return; + case INDEX_op_umax_vec: + tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2); + return; + case INDEX_op_umin_vec: + tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2); + return; case INDEX_op_usadd_vec: tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2); return; @@ -2909,6 +2929,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_cmp_vec: case INDEX_op_mul_vec: case INDEX_op_neg_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: return vece < MO_64; default: return 0; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id h8sm8966092pfv.154.2021.02.07.18.46.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:46:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=reRP6xWNArAQ4z5/WchJHcoykmUgBZ0MZ2SwzFhH+TE=; b=Rrbo5Auuq4amiBLWlaQ7fIgoe5UzJbmVnTX818tJ04dnbvMvKOmFq8PhTFUeNuRHPk V0dfuzbvmzulhkgEio63ZIWQyImz/82ln3F1tCXRXAMspH/fMGBbyvEE8q2u0Lj/XAZo xCXgnJD/BvGjXuX1bnsEIpVHQBVTllsGT8PRaoaMYhd4u/OWZsWEC3LzH89c6pr/5woH stAnyu4PrXyDJpiRONPA4HlvpoCwJj+2MxEV2eHvtnwWa4iwhW/m60jF5AdBiToKMxpR 1AAHiLqz/FtopaDft4qaAybOGWbnfIj+jB3MYIkDRa0XLAIIEYaQhdo2wbqULSg35sRA vNxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=reRP6xWNArAQ4z5/WchJHcoykmUgBZ0MZ2SwzFhH+TE=; b=jazx8U+bjvRzXumLF0c1iMncqsUPqS+iN6Wu+dTJX3/ZB8qbCBaHy58YsNfNU53wiT OHtjSuu4e5f0ks9NAJfQXgfZvVYbNesIAmMADGMGmfuRC7LSdVkiQiNCiXkgQZxrg1rg cPMYPfVPZeU3eMkUwiQrk972cgse7Ifd+UNefR96I/c8Osui+n9PgFlzQB4eqyWe658t cVxajsqiS44LVgGzXlM2wC6yywGaFW3wqGe7UHYPCxskSsq6ld5u7eQdyRBK7bVQozHW CrLhGjP7huequXqNkXkX2BzUNaHHTTnUje/eiJYp8efpzKei5pzemtQ2xw/pE04eZjqF nmaw== X-Gm-Message-State: AOAM530XCyRBNP2rXo0D0VbJzkuw84p8eh2g2SKoh9wBMZeo4SWrtb1e QB1brtB4tuQ/rHYglFk4xCpItWIp5xg/+A== X-Google-Smtp-Source: ABdhPJzyIy+keRemuIT97mFPHLElHh0bbXg42ifWK4P0sBASyF4fD73dHoAcNz9Hf3DZspXXdfxIng== X-Received: by 2002:a17:90a:654a:: with SMTP id f10mr14634755pjs.202.1612752399578; Sun, 07 Feb 2021 18:46:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 12/15] tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec Date: Sun, 7 Feb 2021 18:46:22 -0800 Message-Id: <20210208024625.271018-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208024625.271018-1-richard.henderson@linaro.org> References: <20210208024625.271018-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" NEON has 3 instructions implementing this 4 argument operation, with each insn overlapping a different logical input onto the destination register. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target-con-set.h | 1 + tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 22 ++++++++++++++++++++-- 3 files changed, 22 insertions(+), 3 deletions(-) diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h index cc006f99cd..d02797cbf4 100644 --- a/tcg/arm/tcg-target-con-set.h +++ b/tcg/arm/tcg-target-con-set.h @@ -34,6 +34,7 @@ C_O1_I2(w, w, w) C_O1_I2(w, w, wO) C_O1_I2(w, w, wV) C_O1_I2(w, w, wZ) +C_O1_I3(w, w, w, w) C_O1_I4(r, r, r, rI, rI) C_O1_I4(r, r, rIN, rIK, 0) C_O2_I1(r, r, l) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 4815a34e75..d6222ba2db 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -169,7 +169,7 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 -#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 1 #define TCG_TARGET_HAS_cmpsel_vec 0 =20 #define TCG_TARGET_DEFAULT_MO (0) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index afd2807c09..875d975d4b 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -216,6 +216,10 @@ typedef enum { INSN_VSARI =3D 0xf2800010, /* VSHR.S */ INSN_VSHRI =3D 0xf3800010, /* VSHR.U */ =20 + INSN_VBSL =3D 0xf3100110, + INSN_VBIT =3D 0xf3200110, + INSN_VBIF =3D 0xf3300110, + INSN_VTST =3D 0xf2000810, =20 INSN_VDUP_G =3D 0xee800b10, /* VDUP (ARM core register) */ @@ -2427,7 +2431,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) return C_O1_I2(w, w, wV); case INDEX_op_cmp_vec: return C_O1_I2(w, w, wZ); - + case INDEX_op_bitsel_vec: + return C_O1_I3(w, w, w, w); default: g_assert_not_reached(); } @@ -2748,7 +2753,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, { TCGType type =3D vecl + TCG_TYPE_V64; unsigned q =3D vecl; - TCGArg a0, a1, a2; + TCGArg a0, a1, a2, a3; int cmode, imm8; =20 a0 =3D args[0]; @@ -2899,6 +2904,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, } return; =20 + case INDEX_op_bitsel_vec: + a3 =3D args[3]; + if (a0 =3D=3D a3) { + tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1); + } else if (a0 =3D=3D a2) { + tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1); + } else { + tcg_out_mov(s, type, a0, a1); + tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3); + } + return; + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: @@ -2924,6 +2941,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: + case INDEX_op_bitsel_vec: return 1; case INDEX_op_abs_vec: case INDEX_op_cmp_vec: --=20 2.25.1 From nobody Tue Nov 18 07:46:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612754878; cv=none; d=zohomail.com; s=zohoarc; b=FSNYcLOQyjayhQe0kwkdyROUgLYXjhwEZHkZ7dYNJQEyU1aMLG0aEDVLSKFwaVEPmoYL29sLLTLpZxexPV3nEI+wk5bYKHmPL0+2MtDGSYhKSX7I0sjQWKQpTezXRJCmS8OkPA/QNLl4GTTrgGzwDIsDixfo2UCdOsh4zywKKKY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612754878; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=o5M8c9V3AKnIe0DJJe/R5zY18kqg2FwjGsxkh/FIP60=; b=iZxdn0mOUUD6kzSf5vYfa56/BM7EYLZAKQlQUHu7+6QEy++mZwqHFVWDHXNaS0BIoVINTbhlX5Xk76R5RRJW2YIlrvycEcYEVMxjsBeXqHmU8FCLwC1tDGxV47HoUooaGMnLMMS4kOktEoZITZ4YLWU0HkiVDB/fH91Cg2lqe1c= ARC-Authentication-Results: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id h8sm8966092pfv.154.2021.02.07.18.46.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:46:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=o5M8c9V3AKnIe0DJJe/R5zY18kqg2FwjGsxkh/FIP60=; b=xGV06RrPsXuQvy+iiKH+wcoOijOES1ekSy8TmRz+IltkQHKq2HS+NZzM+NrA80mPOV Iy7KGSAXXC2LeqHjuqyx0JSrUtlfjQmmSubPmNr5DLuQMVa46V1f4hcqptfWBC7QWDYQ P3IPlQ8w5eCZ0nyRTIakae42wZ99r40qKX4Gb1406Zr7ByKdB2lenGK9NFJK9myDTTil HgLZfGlMWVc05KwedDyrhFZEPARPOoR+aPxWkoVzp9lrwIAppUmeyqFZrRDHX2BQczND U3OSuH3z6XJJhoE93tkqHlrXrcIl8NBGkUxCb0vCiMFsa/mbGbSFvq5NGn6Y2TVX7aKU Ls9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o5M8c9V3AKnIe0DJJe/R5zY18kqg2FwjGsxkh/FIP60=; b=mdLCBvi4HK64yGNQEN5obMboeCUiJg0vSYWLLn/qJ/0BoepGDb756Fj18Ki3WuiG5H S1/Sb7a+hLOrIbyzRBhP8QZzfgVn9CumF0aDOU+jC3UugvAOm5cS4pXxQ5yCI27Jk7K4 mbvpa9qsvfQFUDT+lUXbOJvaVtZmgaNkCiHBBgsH360DU18HVzBap866fhrIu/CB0I7W XoPB87HK9lcv2rJwLV4zgObdM9QfaV5w1AxtsuGdmyMVE5wSf68laHKFjpligL9vMHu6 7BLHkxQWyJi/UNP14+flG5cEwS1MGcJfGrueUrqWd3IeDXNU2K32xw0Y9CwJy2Iq5+5z QASg== X-Gm-Message-State: AOAM533RFGJyc5lwx1Zgu1CcbUR2e6+X43nbf19Y5DWtnXV53qQCMjug 2GVkyRo5eZxDPzDUgK+tAiLtZFmAj0xDew== X-Google-Smtp-Source: ABdhPJy0MVYQlC2HO6XysCHIeX/Xq7qSFnw+YO8dwffQdnX5buPxbyefRKZ3lPTjvtMRUoBZRxHfyw== X-Received: by 2002:a17:90b:104c:: with SMTP id gq12mr14709964pjb.11.1612752400727; Sun, 07 Feb 2021 18:46:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 13/15] tcg/arm: Implement TCG_TARGET_HAS_shv_vec Date: Sun, 7 Feb 2021 18:46:23 -0800 Message-Id: <20210208024625.271018-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208024625.271018-1-richard.henderson@linaro.org> References: <20210208024625.271018-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The three vector shift by vector operations are all implemented via expansion. Therefore do not actually set TCG_TARGET_HAS_shv_vec, as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the instruction stream, and therefore also do not appear in tcg_target_op_def. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.opc.h | 3 ++ tcg/arm/tcg-target.c.inc | 61 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 63 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h index 7a4578e9b4..d19153dcb9 100644 --- a/tcg/arm/tcg-target.opc.h +++ b/tcg/arm/tcg-target.opc.h @@ -10,3 +10,6 @@ * emitted by tcg_expand_vec_op. For those familiar with GCC internals, * consider these to be UNSPEC with names. */ + +DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC) +DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 875d975d4b..b088f61a99 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -215,6 +215,8 @@ typedef enum { INSN_VSHLI =3D 0xf2800510, /* VSHL (immediate) */ INSN_VSARI =3D 0xf2800010, /* VSHR.S */ INSN_VSHRI =3D 0xf3800010, /* VSHR.U */ + INSN_VSHL_S =3D 0xf2000400, /* VSHL.S (register) */ + INSN_VSHL_U =3D 0xf3000400, /* VSHL.U (register) */ =20 INSN_VBSL =3D 0xf3100110, INSN_VBIT =3D 0xf3200110, @@ -2422,6 +2424,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: case INDEX_op_xor_vec: + case INDEX_op_arm_sshl_vec: + case INDEX_op_arm_ushl_vec: return C_O1_I2(w, w, w); case INDEX_op_or_vec: case INDEX_op_andc_vec: @@ -2818,6 +2822,17 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_xor_vec: tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); return; + case INDEX_op_arm_sshl_vec: + /* + * Note that Vm is the data and Vn is the shift count, + * therefore the arguments appear reversed. + */ + tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1); + return; + case INDEX_op_arm_ushl_vec: + /* See above. */ + tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1); + return; case INDEX_op_shli_vec: tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece)); return; @@ -2952,6 +2967,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_umax_vec: case INDEX_op_umin_vec: return vece < MO_64; + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: + return -1; default: return 0; } @@ -2960,7 +2979,47 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { - g_assert_not_reached(); + va_list va; + TCGv_vec v0, v1, v2, t1; + TCGArg a2; + + va_start(va, a0); + v0 =3D temp_tcgv_vec(arg_temp(a0)); + v1 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + a2 =3D va_arg(va, TCGArg); + va_end(va); + + switch (opc) { + case INDEX_op_shlv_vec: + /* + * Merely propagate shlv_vec to arm_ushl_vec. + * In this way we don't set TCG_TARGET_HAS_shv_vec + * because everything is done via expansion. + */ + v2 =3D temp_tcgv_vec(arg_temp(a2)); + vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + break; + + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: + /* Right shifts are negative left shifts for NEON. */ + v2 =3D temp_tcgv_vec(arg_temp(a2)); + t1 =3D tcg_temp_new_vec(type); + tcg_gen_neg_vec(vece, t1, v2); + if (opc =3D=3D INDEX_op_shrv_vec) { + opc =3D INDEX_op_arm_ushl_vec; + } else { + opc =3D INDEX_op_arm_sshl_vec; + } + vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + tcg_temp_free_vec(t1); + break; + + default: + g_assert_not_reached(); + } } =20 static void tcg_out_nop_fill(tcg_insn_unit *p, int count) --=20 2.25.1 From nobody Tue Nov 18 07:46:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id h8sm8966092pfv.154.2021.02.07.18.46.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:46:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=mlQccIEWwj2YtWlnEgH22wmiL/pAMfX41rEpRSECFmw=; b=Jgz/R8BVZ8QuJECkHbDoeTQ8nkoy7pyDqZevCzvZNCo1jvaGlBKmdeOoK5poYN1+QY xOsfsJAEuN+Vcr+zX0d+g9Ahj0EKDnVBkuLCZfOws1wh5CSu63l0BelneE6EyL5usY5u QlrWuFxUYuVYkavYXPzJyPc/sFxnVtxaFDAiJMkUyxrqofUZcrk+lL1+z3OpRbFJ/ApR gR5ZJ8uvcWOC9fA/1KukjpsEI9d9QGa8F54gC5tTwUUZ7ay73WoY9mJFpDc9BQLRjsyy dvsyEPtswxl1uylrC997GU4kcaBNLpHmamY4UbKHHaXzsIPGcgVWxnhr2wEMYOFM6Yom aXQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mlQccIEWwj2YtWlnEgH22wmiL/pAMfX41rEpRSECFmw=; b=HXYkGqAgdwl1QtiaLFxLXNSGXVlwTSBJYP+KSrcNgVvFFkaWe7wljz161TD4gK3vzr 0fO4Pv9GwmPYn+u5qFYZ0EJ6MnuwqwPBfDbLxaHeuJZzdyxfnEbPGY5UEjP8YeyYPIOo v7vU3Q+3A2sAccTA++6igxxfCHaN2zzkmK23kHpnTrV28lUs51P/x3tmVTe7fD4vRa3W LE6Ep5ZI7kCAdEKNWdAk7Fww34MNqxqkIkIqzax62/QDExJ5dPkn5stv/nM2wa38ofDc Ddzy7YfSXCjd2i101W9/ZEPB9FlM+Ox2zZeKtQjG/3aPG3if+LLL2loIFSmqV61tRWqW ozuw== X-Gm-Message-State: AOAM533God5dNQAJQkqCNNwHoDSUEFXIsoPhUFi6ElI7eqOHBFf6i1vG Qyf6E1/oX3XPcQKr1LYcLTVYHpiVuOZiUA== X-Google-Smtp-Source: ABdhPJzk6C5+XIAF5kCIg1hJA/uOAWoZKJF8giWdwjenjZ9n8N1OGbpb/UcCl7vwSe8CcNcU56LCNQ== X-Received: by 2002:a63:ff5d:: with SMTP id s29mr15530397pgk.133.1612752401897; Sun, 07 Feb 2021 18:46:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 14/15] tcg/arm: Implement TCG_TARGET_HAS_roti_vec Date: Sun, 7 Feb 2021 18:46:24 -0800 Message-Id: <20210208024625.271018-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208024625.271018-1-richard.henderson@linaro.org> References: <20210208024625.271018-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec. For NEON, this is shift-right followed by shift-left-and-insert. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target-con-set.h | 1 + tcg/arm/tcg-target.opc.h | 1 + tcg/arm/tcg-target.c.inc | 15 +++++++++++++++ 3 files changed, 17 insertions(+) diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h index d02797cbf4..3685e1786a 100644 --- a/tcg/arm/tcg-target-con-set.h +++ b/tcg/arm/tcg-target-con-set.h @@ -30,6 +30,7 @@ C_O1_I2(r, r, rIK) C_O1_I2(r, r, rIN) C_O1_I2(r, r, ri) C_O1_I2(r, rZ, rZ) +C_O1_I2(w, 0, w) C_O1_I2(w, w, w) C_O1_I2(w, w, wO) C_O1_I2(w, w, wV) diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h index d19153dcb9..d38af9a808 100644 --- a/tcg/arm/tcg-target.opc.h +++ b/tcg/arm/tcg-target.opc.h @@ -11,5 +11,6 @@ * consider these to be UNSPEC with names. */ =20 +DEF(arm_sli_vec, 1, 2, 1, IMPLVEC) DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC) DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index b088f61a99..3150aae8d6 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -215,6 +215,7 @@ typedef enum { INSN_VSHLI =3D 0xf2800510, /* VSHL (immediate) */ INSN_VSARI =3D 0xf2800010, /* VSHR.S */ INSN_VSHRI =3D 0xf3800010, /* VSHR.U */ + INSN_VSLI =3D 0xf3800510, INSN_VSHL_S =3D 0xf2000400, /* VSHL.S (register) */ INSN_VSHL_U =3D 0xf3000400, /* VSHL.U (register) */ =20 @@ -2427,6 +2428,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_arm_sshl_vec: case INDEX_op_arm_ushl_vec: return C_O1_I2(w, w, w); + case INDEX_op_arm_sli_vec: + return C_O1_I2(w, 0, w); case INDEX_op_or_vec: case INDEX_op_andc_vec: return C_O1_I2(w, w, wO); @@ -2842,6 +2845,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_sari_vec: tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2); return; + case INDEX_op_arm_sli_vec: + tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece)); + return; =20 case INDEX_op_andc_vec: if (!const_args[2]) { @@ -2970,6 +2976,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_rotli_vec: return -1; default: return 0; @@ -3017,6 +3024,14 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, tcg_temp_free_vec(t1); break; =20 + case INDEX_op_rotli_vec: + t1 =3D tcg_temp_new_vec(type); + tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); + vec_gen_4(INDEX_op_arm_sli_vec, type, vece, + tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2= ); + tcg_temp_free_vec(t1); + break; + default: g_assert_not_reached(); } --=20 2.25.1 From nobody Tue Nov 18 07:46:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612756989; cv=none; d=zohomail.com; s=zohoarc; b=HVqbwnmsz+GRYlca7i/bgx6J/I6GtCrLue3IOylB+ybeGRrk3rmTgpUP0tnvAlA+GWr/76CpnL38LMjPBfks1Sqrl/xU4/6WNR07MeryEL9zA14fJfuOKM+Bwxvy9aXE9/6DAHN5tl5oHhRa7f9OdJoJe+4FV1/O3ybQS6FJ1cE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612756989; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pW9wjxLXorRLCkTNii0jQEnXahS9j0N+pGdhyNQW8cQ=; b=HsI8v26F8LmfML/+IKtbiYHasy/egqloV7bax7qQWcYXYGghYLoJMdHwIBsUy7eAAwwef+94rRv6UIglD4lWK5QniWJvHqvZw4ujPW80WX0L2WsJGzilkK013AtfQQI6pBcv8m+gxrUEpg0MkXWDFwbwuz4By62qIvbcIqFr5Js= ARC-Authentication-Results: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id h8sm8966092pfv.154.2021.02.07.18.46.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:46:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=pW9wjxLXorRLCkTNii0jQEnXahS9j0N+pGdhyNQW8cQ=; b=zxSaogKH3uce2RhD6UFHeC4yLzI/Gyu+Pe1SwLVSl9Xp0jueHItRls0qVVEAELTJXF CY/8y5/B4V+nmgTU5TxI8gyP5WJh21RqE/YF9bGC+C+rSzGgiT5pPfzKEewVIHiVaOoq z6+H00806Hd5g8IKi+wo89pEvZ4Ajn6F/s5eu90Zvj45RK0aoDGjYH0jvVYi+PiBqtqG eLjzSL47hMubQKWjlrUHC/YSUMw3JfhzQu7LciS9jOZUEQCWwMdnkhiglWScF4qKgE3v EsQ7vSShcU6f6Od7OCaN452ZbM3RqS3wiejPw+Ilw209eTGw6WIN6Fx/YAxaZ+I+LWuJ MWRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pW9wjxLXorRLCkTNii0jQEnXahS9j0N+pGdhyNQW8cQ=; b=L4oI6GCa/xxq8QuDUvNfzJGQGTZywtMWHQJGMSf8RroRq51H/xOwdQqNxl4HaQgrkv lAlISyRFz9U7Fn4qmFfs0O1I45b+hqjLcgtGhXWmQBn+l5WHuz6AUGytE4Rq/4geB6S5 Wx/tQuBPCLjWz8xi3wLFbq8Hm4RU3DGXRXnRkQEbgXn21IHCqPloLxw+kTHJu++nnH3T wOfRV74t9XXWA83Fr1S70w+BzxFVoTH7HACDWGvYSOJqa7lgvTuXU//zFTr5xRvrw2dm WW1DoUFqtsHHqV6zF/ydq/isbe0XkpKbcZ0rTIan5RjXjz0nnJQGLJcFLqz480yLBM6F LMQg== X-Gm-Message-State: AOAM533/y2hKhWgCXl7/d2ADTtkE/gk0NhLzD7elfZmshLnISF/YUa4l YRfdSTmJi4shm3m+sp5ko+v34VQn9c8Hrw== X-Google-Smtp-Source: ABdhPJwdIPSUSTFtxZEfG1ErhMNH1EdSkLN5CyG/WZbfElUM0nmTtwDuGylcdWkq70dWhMcSeq4fAg== X-Received: by 2002:a17:90a:4606:: with SMTP id w6mr15086913pjg.205.1612752403133; Sun, 07 Feb 2021 18:46:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 15/15] tcg/arm: Implement TCG_TARGET_HAS_rotv_vec Date: Sun, 7 Feb 2021 18:46:25 -0800 Message-Id: <20210208024625.271018-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208024625.271018-1-richard.henderson@linaro.org> References: <20210208024625.271018-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement via expansion, so don't actually set TCG_TARGET_HAS_rotv_vec. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.c.inc | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 3150aae8d6..a930d51e92 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2977,6 +2977,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: case INDEX_op_rotli_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: return -1; default: return 0; @@ -2987,7 +2989,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, u= nsigned vece, TCGArg a0, ...) { va_list va; - TCGv_vec v0, v1, v2, t1; + TCGv_vec v0, v1, v2, t1, t2, c1; TCGArg a2; =20 va_start(va, a0); @@ -3032,6 +3034,37 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, tcg_temp_free_vec(t1); break; =20 + case INDEX_op_rotlv_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); + t1 =3D tcg_temp_new_vec(type); + c1 =3D tcg_constant_vec(type, vece, 8 << vece); + tcg_gen_sub_vec(vece, t1, v2, c1); + /* Right shifts are negative left shifts for NEON. */ + vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + tcg_gen_or_vec(vece, v0, v0, t1); + tcg_temp_free_vec(t1); + break; + + case INDEX_op_rotrv_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); + t1 =3D tcg_temp_new_vec(type); + t2 =3D tcg_temp_new_vec(type); + c1 =3D tcg_constant_vec(type, vece, 8 << vece); + tcg_gen_neg_vec(vece, t1, v2); + tcg_gen_sub_vec(vece, t2, c1, v2); + /* Right shifts are negative left shifts for NEON. */ + vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2), + tcgv_vec_arg(v1), tcgv_vec_arg(t2)); + tcg_gen_or_vec(vece, v0, t1, t2); + tcg_temp_free_vec(t1); + tcg_temp_free_vec(t2); + break; + default: g_assert_not_reached(); } --=20 2.25.1