From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752003; cv=none; d=zohomail.com; s=zohoarc; b=hsPQ+KW0FH/mbP3e+6Dovlx2Zd2ZefhU7mQRJV5N8kmltsWoltIwkTetsaLTl07pFdeEpBAwvWG5M1QMzotuA5p8l4onAdfdPd9Csa8rpvMUtKbeOuoKr+wXKd+e3C9K1HS+ijZNJN8nnuauCseA4xY3Ceciy2gyHLOk8B9tctE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612752003; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=06H8W/q0v8WI5yMb4Dgc4NhHzAw8roTrWJkM0Lw1UXA=; b=AY2edJNHwEvbRMaG4xi5NqQMfleeBgepxHkvDqpYRb2yRzyFCkhW5Ge9Qwfl1ush4pc2EU4ZPS2oacehCYz3y+PmXhnJc90Ax54qbL7XvtT+DLsP5QGHYOke2DfLZmAEAqqpqeJRfCJdV1X/yjfdynHFAwYAq8ATrTw5IWtfWxU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612752003428520.3900818035296; Sun, 7 Feb 2021 18:40:03 -0800 (PST) Received: from localhost ([::1]:57368 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wT3-0002o2-Rd for importer@patchew.org; Sun, 07 Feb 2021 21:40:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57616) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wR6-00010e-Lk for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:00 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:42322) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wR3-0005gB-MP for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:00 -0500 Received: by mail-pl1-x631.google.com with SMTP id s15so7010339plr.9 for ; Sun, 07 Feb 2021 18:37:57 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.37.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:37:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=06H8W/q0v8WI5yMb4Dgc4NhHzAw8roTrWJkM0Lw1UXA=; b=Ifk6btvJv/vvkD9V1CnOdmEiAIpE7+ILWRn41HqaD1WH2XW21yCuyBSFJDBzJBqh5j 00I1CDs1c8iemez7ANp3M+wvB/6XVgwGsAYvIIiddHyBBABt96IbmFzZwmLLs/HV0TYP 2YNXvUEwP6Qk57RoHozMcBwl+3VjA5KPpJTvTAvOZE9s2J9Kg06nNgOXsuUFu54pY98M /+spc/NhBrDKiCfMNPNWCxOrhxu6iReq1hjtgF5qKzLU25Xu+Qfb01wItc/jmAfXIunS nIuRzVCsvFc4pgJ3JvhQnZ/r1gD3cFDlkaDmCcvwnrz2c9aMBWlxM3S3srK7qolz4KSE YqZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=06H8W/q0v8WI5yMb4Dgc4NhHzAw8roTrWJkM0Lw1UXA=; b=Df2UvuiHyKCavgO9rpFDDz9n/P9ZnvN4Bu2/E8E52kN76LCMjFPWdG+D+F7fyBMhwI ebn3ouFxm4pDy7oFic5YuE0kJYcImu49wiW8QRLOtQKjUNQ0qGSfbSvoYepbVKTQsoI/ 6OdTfeD5UiIpuAxV6TWwn+MQVlwhKIa0o3gL0rzJxkohQPTcRzyr0XxV0SKI4Dyv687s JUJxyi5TAL2IqniJvcyjlSPS1xEPPo2oZFEi+MO0oNl1mBF+WpEaS50bAj9CGXeeRpow /hBD2RAUsRDsEyK45F2LNwCvb0M+xbZriffAQpx6aJ/j8dfJEsnSc4aZ+bRjYBUqpRQY 8V7Q== X-Gm-Message-State: AOAM5304ZWX5y0nAbofJLc8RFCirvCul6nQ4uO/RPP6qa85mosnnbgPp ygetihnfKe1pnvClp4wckGs4U6whpub+2A== X-Google-Smtp-Source: ABdhPJxlbqHh/DBmPqUPFsis7rPukv6s9ISHtUwEVKUZZEvrtKXQRA8iW2zWHL6mxxlRAU/IdY86gA== X-Received: by 2002:a17:90b:350b:: with SMTP id ls11mr14676243pjb.166.1612751876427; Sun, 07 Feb 2021 18:37:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 01/70] gdbstub: Fix handle_query_xfer_auxv Date: Sun, 7 Feb 2021 18:36:43 -0800 Message-Id: <20210208023752.270606-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The main problem was that we were treating a guest address as a host address with a mere cast. Use the correct interface for accessing guest memory. Do not allow offset =3D=3D auxv_len, which would result in an empty packet. Fixes: 51c623b0de1 ("gdbstub: add support to Xfer:auxv:read: packet") Signed-off-by: Richard Henderson --- gdbstub.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index c7ca7e9f88..759bb00bcf 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -2245,7 +2245,6 @@ static void handle_query_xfer_auxv(GdbCmdContext *gdb= _ctx, void *user_ctx) { TaskState *ts; unsigned long offset, len, saved_auxv, auxv_len; - const char *mem; =20 if (gdb_ctx->num_params < 2) { put_packet("E22"); @@ -2257,8 +2256,8 @@ static void handle_query_xfer_auxv(GdbCmdContext *gdb= _ctx, void *user_ctx) ts =3D gdbserver_state.c_cpu->opaque; saved_auxv =3D ts->info->saved_auxv; auxv_len =3D ts->info->auxv_len; - mem =3D (const char *)(saved_auxv + offset); - if (offset > auxv_len) { + + if (offset >=3D auxv_len) { put_packet("E00"); return; } @@ -2269,12 +2268,20 @@ static void handle_query_xfer_auxv(GdbCmdContext *g= db_ctx, void *user_ctx) =20 if (len < auxv_len - offset) { g_string_assign(gdbserver_state.str_buf, "m"); - memtox(gdbserver_state.str_buf, mem, len); } else { g_string_assign(gdbserver_state.str_buf, "l"); - memtox(gdbserver_state.str_buf, mem, auxv_len - offset); + len =3D auxv_len - offset; } =20 + g_byte_array_set_size(gdbserver_state.mem_buf, len); + if (target_memory_rw_debug(gdbserver_state.g_cpu, saved_auxv + offset, + gdbserver_state.mem_buf->data, len, false))= { + put_packet("E14"); + return; + } + + memtox(gdbserver_state.str_buf, + (const char *)gdbserver_state.mem_buf->data, len); put_packet_binary(gdbserver_state.str_buf->str, gdbserver_state.str_buf->len, true); } --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752181; cv=none; d=zohomail.com; s=zohoarc; b=GS9cQCGHA3ZRuBPMayKBneO8Tbe0RZRdT5f9zglXCN6U4hae8Zdpt1L7MTH7iJtjzUL3Wobf3CrF7+0d6O38JVljYgFY1J54h6ucqPjVm/yK3LwTWP1E67cghXPvC3kHYmLKBTIn99ehVwNI0rzbRc57JhzjvCNj+cAJrsm6gzE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612752181; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rTk7Zu1K9am+nHTK4Qgzw1qdbWz4Og49PpMunTWLZww=; b=Yq5TqtzPwWBJsLXG8yoV/IAf/EQG3L0lLlFTyNVIDZ8DnBXub3tCgFRmeIZF06+1jbsEw1TSDG3I6yPpSc/rwnCvs+bnGk1sXIias0V4uAiaSUgLn6j4FHNISWKHpwc4B79r2NMqC7Vg9khQ8zv5L/ZhxW8w4qwSGC7D6Mt3wRU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612752181619427.58422717543976; Sun, 7 Feb 2021 18:43:01 -0800 (PST) Received: from localhost ([::1]:37606 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wVw-0006PN-94 for importer@patchew.org; Sun, 07 Feb 2021 21:43:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57624) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wR7-00010w-9W for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:01 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:32987) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wR5-0005gH-3O for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:01 -0500 Received: by mail-pl1-x633.google.com with SMTP id d13so7034662plg.0 for ; Sun, 07 Feb 2021 18:37:58 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.37.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:37:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rTk7Zu1K9am+nHTK4Qgzw1qdbWz4Og49PpMunTWLZww=; b=qsKurlwuF1Sziob0r/Jut42Pv1j1M6EDjm6SmvdzCSA4QGdv3U3GoII8FRRcO3SxR2 ctb957mgB3SjJbH4oQXxSOOvffYwpPaxre39HtRD6vRJWX9OWD/bD0vMHiLtGEC099xr D3PvKSGhq7lm4lkr5TeE2q25UDp5FnNtf+ugydSnEhgF/8SL/OUUgN4zjq//5MdkYpp1 fqAntENs4fW3H3L7PN6mvfhsZagTL36a1NQSQt6OlAgkp8APMZgHIkefF51j6dGqOYBC 9O9O3y+mQ9Fd2Bfkmg6KPpRY3uZgPuBQ8VQPRjvDbYpEf8BdgUbH405BmcFxH883hH4a 6qZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rTk7Zu1K9am+nHTK4Qgzw1qdbWz4Og49PpMunTWLZww=; b=F4R7WuAdf2oJ3AYCv5oYcTxgSLvikEuGAsHv8nlUETTqTOcp+1luFObRCD6uRMZ8dI ER8N1XlTGJTCDcwdN20ku4bG5LH3MPhYa8GAB20LHeYKBdDydhBSHR5+2365H7RGaXjM 6Nvctxjnb9OtH1z9DH6rJmvczPwbG14I2rc8FJdNYrby+EqcsfQT/P46j//KRcevNhJ5 i4vKIXV/9QDre6mtSgMf4FbSDBfihFi+H7xz6caI24y6OgHNj9JsFkFhC6mp+K29+6GB /eSoMUMXSClBd2RaP2xpYLDqD/p90IPXcJ4qMpkByWLRUX62C/7Hyz7BjxtWja+Vopc3 W8pA== X-Gm-Message-State: AOAM5331ogDzQPDRFvE6cOpp7brq+i2IPRqSAPMB0AdHSGBhonP7ihuN vDcmJ71GmXqX8F6QquIPXbMrMF0BxfdHTQ== X-Google-Smtp-Source: ABdhPJxfInwqNYAqbNVHnfK0hbUYy7MGRJV3eAVhbxKqriS2TcBAV8izkTvtnja+hDhL2rG8AHWGBA== X-Received: by 2002:a17:902:be0e:b029:e0:5b2:659e with SMTP id r14-20020a170902be0eb02900e005b2659emr14362854pls.74.1612751877654; Sun, 07 Feb 2021 18:37:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 02/70] tcg: Split out tcg_raise_tb_overflow Date: Sun, 7 Feb 2021 18:36:44 -0800 Message-Id: <20210208023752.270606-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Allow other places in tcg to restart with a smaller tb. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tcg.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 63a12b197b..bbe3dcee03 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -346,6 +346,12 @@ static void set_jmp_reset_offset(TCGContext *s, int wh= ich) s->tb_jmp_reset_offset[which] =3D tcg_current_code_size(s); } =20 +/* Signal overflow, starting over with fewer guest insns. */ +static void QEMU_NORETURN tcg_raise_tb_overflow(TCGContext *s) +{ + siglongjmp(s->jmp_trans, -2); +} + #define C_PFX1(P, A) P##A #define C_PFX2(P, A, B) P##A##_##B #define C_PFX3(P, A, B, C) P##A##_##B##_##C @@ -1310,8 +1316,7 @@ static TCGTemp *tcg_temp_alloc(TCGContext *s) int n =3D s->nb_temps++; =20 if (n >=3D TCG_MAX_TEMPS) { - /* Signal overflow, starting over with fewer guest insns. */ - siglongjmp(s->jmp_trans, -2); + tcg_raise_tb_overflow(s); } return memset(&s->temps[n], 0, sizeof(TCGTemp)); } --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752184; cv=none; d=zohomail.com; s=zohoarc; b=HlZwHpuICLn4VCqqdNSVrCLAZOEy1D2Qjn9o39DsxfsuOo6rJu/MUEkHIeasraXeuBbhKsAtqAXAF7QdlF8dRlVMHfNzwiehFbilSVAfFOlF5y3tUOqG+Mj6KunVpGHVS0CrdozZwxW//ZU6hKfUnYHhZYufLeQuImRdL9AKAGU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612752184; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xzKpOz1dnkvT+2F/uu8BRDtdRIBrUsrfNHwaFpPfXw4=; b=GqeY4ip6BUG4bbEumLXuWjfmyby4hPpd7wvBtZcvXCRe+e09X1fyj7YlFtYZ7YUpjWEUCva3y5a2aCCd+DXZZuvPVFOVypDhZOE3vFv8F4ZurIlpuNgFQoQM+PY5KbW7Q7s7EtQKHBgrvj3quNVtDTV/qnfKqwVccndvKoAxMk4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612752184267459.3216080686549; Sun, 7 Feb 2021 18:43:04 -0800 (PST) Received: from localhost ([::1]:37902 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wVz-0006Wa-0V for importer@patchew.org; Sun, 07 Feb 2021 21:43:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57632) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wR8-00011h-2R for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:02 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:42327) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wR6-0005gk-7W for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:01 -0500 Received: by mail-pl1-x636.google.com with SMTP id s15so7010382plr.9 for ; Sun, 07 Feb 2021 18:37:59 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.37.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:37:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xzKpOz1dnkvT+2F/uu8BRDtdRIBrUsrfNHwaFpPfXw4=; b=pFn+PW2KH3Ms6I3BPS81TCc4ymj5ilOeRWtMvXPXkRYKKSbMn+uJk/SiSydUWLzXZQ 50XhEpAKCBl1S6/+4bue/UKvR0tsHHJYqMZsE0z9SkCVlbgnH3/JZUhoD8DaZYJTZLXK vAUWpnay+EqNciexnlIa/DlY1bFTt0s4Ik4HlAcDWhUL7WN+lab4VC5jKVjwzBJT1HkD jq8BAOEIQfkg8xd5yUPWtYXXZBaU0hU+3kauljMGqQ6M3mxbeeURBZxBzxYCo4BNKeou TVCeENp4e5GdP8rHECP8a7fGC0Ghh615CxLrCns0hPDOta9lkIoZHgl0hpoRxVx8ZIvU uKlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xzKpOz1dnkvT+2F/uu8BRDtdRIBrUsrfNHwaFpPfXw4=; b=OSoaZ7qumIbIhgIj9qcT5vS0KWM5tl/rLqAVImL8t2+OZwYvdIxU1yaFPNmgeGxzff vBHkirD4KxRmHvA2lNl9QICWapwXuz+YK0Ne/cE6f6NSo9a4CJR9ZcxwcBVtUEEmv489 s50W5QpXoT0jO2fIDS8TOKrYM6lkMxMR+Y82BMYaDiWg108qKHkrxEbzUrS2KG6fEUin 6Yg0dCMepkw8VlQxpbubYuXP4PV4Fm2qHTJxm01HyD9olLmlOt3q83jyLge/VM1ExzrF Kgoa8DFfUbsYajxLFRdsIkF1zzFz9k2Ef0x0H5cpLWG5zoR0nV3nWiwkGECAK5F5rQ9j 8Nmg== X-Gm-Message-State: AOAM531u7RXkhYrZ77jDGt7h58T6K+KTW6eEjgG4GmP2tA/Ew6+MRRTV wkuXrySBQNvSpEx3S6sCZtpDkV9jZV8XSw== X-Google-Smtp-Source: ABdhPJx4DejinH/VguX7tkwqcEjsv1PvmVAUBOF+U3w4iZOaAQWAAtyMIX514z/KY7Xbocm7u1bHTg== X-Received: by 2002:a17:90a:4141:: with SMTP id m1mr13007844pjg.34.1612751878971; Sun, 07 Feb 2021 18:37:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 03/70] tcg: Manage splitwx in tc_ptr_to_region_tree by hand Date: Sun, 7 Feb 2021 18:36:45 -0800 Message-Id: <20210208023752.270606-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The use in tcg_tb_lookup is given a random pc that comes from the pc of a signal handler. Do not assert that the pointer is already within the code gen buffer at all, much less the writable mirror of it. Fixes: db0c51a3803 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- For TCI, this indicates a bug in handle_cpu_signal, in that we are taking PC from the host signal frame. Which is, nearly, unrelated to TCI at all. The TCI "pc" is tci_tb_ptr (fixed in the next patch to at least be thread-local). We update this only on calls, since we don't expect SEGV during the interpretation loop. Which works ok for softmmu, in which we pass down pc by hand to the helpers, but is not ok for user-only, where we simply perform the raw memory operation. I don't know how to fix this, exactly. Probably by storing to tci_tb_ptr before each qemu_ld/qemu_st operation, with barriers. Then Doing the Right Thing in handle_cpu_signal. And perhaps by clearing tci_tb_ptr whenever we're not expecting a SEGV on behalf of the guest (and thus anything left is a qemu host bug). --- v2: Retain full struct initialization --- tcg/tcg.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index bbe3dcee03..2991112829 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -513,11 +513,21 @@ static void tcg_region_trees_init(void) } } =20 -static struct tcg_region_tree *tc_ptr_to_region_tree(const void *cp) +static struct tcg_region_tree *tc_ptr_to_region_tree(const void *p) { - void *p =3D tcg_splitwx_to_rw(cp); size_t region_idx; =20 + /* + * Like tcg_splitwx_to_rw, with no assert. The pc may come from + * a signal handler over which the caller has no control. + */ + if (!in_code_gen_buffer(p)) { + p -=3D tcg_splitwx_diff; + if (!in_code_gen_buffer(p)) { + return NULL; + } + } + if (p < region.start_aligned) { region_idx =3D 0; } else { @@ -536,6 +546,7 @@ void tcg_tb_insert(TranslationBlock *tb) { struct tcg_region_tree *rt =3D tc_ptr_to_region_tree(tb->tc.ptr); =20 + g_assert(rt !=3D NULL); qemu_mutex_lock(&rt->lock); g_tree_insert(rt->tree, &tb->tc, tb); qemu_mutex_unlock(&rt->lock); @@ -545,6 +556,7 @@ void tcg_tb_remove(TranslationBlock *tb) { struct tcg_region_tree *rt =3D tc_ptr_to_region_tree(tb->tc.ptr); =20 + g_assert(rt !=3D NULL); qemu_mutex_lock(&rt->lock); g_tree_remove(rt->tree, &tb->tc); qemu_mutex_unlock(&rt->lock); @@ -561,6 +573,10 @@ TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr) TranslationBlock *tb; struct tb_tc s =3D { .ptr =3D (void *)tc_ptr }; =20 + if (rt =3D=3D NULL) { + return NULL; + } + qemu_mutex_lock(&rt->lock); tb =3D g_tree_lookup(rt->tree, &s); qemu_mutex_unlock(&rt->lock); --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752326; cv=none; d=zohomail.com; s=zohoarc; b=PguUkUEpYs2yf4ionHtDPBE8i1tvAoNrzfead9TBtvuVq31p7LMJ+6gK9UfIPcbBix5TahV9IyA2KuqDVoZevs2GtCvdeK9ioD0aRgK03TnJf6MdJyJi7QrB6yZRAKFN8aAiIaOxKJbu91Dcg1/HFDixMGW0FyPY3xqprWOU8rk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612752326; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VvjDH0d9yENa4ecfbUN1MGRyNECdD1MomwyxKEWSk7s=; b=VomdyS3EIv4rKlfDA4Gwm9kgokkdQVNzbqCtIP74NsZ390HQShYvuahWpUMQuQvQABjji3wpyoPyGwVVh5MGm+LeeKXvDDlO1fTMYNUMdeQ0vAU1LTprgvDDQqq7BeiNQjKTZ26s0hMzxBHs2IUq+dBvybHTuiHW9L0guQdtrGs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161275232650543.09272625193046; Sun, 7 Feb 2021 18:45:26 -0800 (PST) Received: from localhost ([::1]:46186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wYH-0001T9-5A for importer@patchew.org; Sun, 07 Feb 2021 21:45:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57654) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wR9-00014n-P7 for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:03 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:37573) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wR7-0005hK-HG for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:03 -0500 Received: by mail-pj1-x1030.google.com with SMTP id t2so2758809pjq.2 for ; Sun, 07 Feb 2021 18:38:01 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.37.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:37:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VvjDH0d9yENa4ecfbUN1MGRyNECdD1MomwyxKEWSk7s=; b=TGsb+7jckFxk/Zx7PDs+hYGpc4OWlLs8a4L/o7VlSjWo5Wwmt2bboljgZYmDbcZi/4 9viipVBcTqRdd22xD0gSToSdPn9FCA7nJENvZ1a5kswHJthhCPxtPs2HNv/9tU4bc9Jg mSCFY/vuStgxWSSfGeeaZqibCaZdLkKAZm9YphK23mG4klgICr7dZqmoqiZm4shsBZCN Brcw6RuGwUP2HcZTdob7wve84ZX5rtmYT1j0L4VsMTLa4BODs+VzTFI2qwqP6tb33IND gSQaaIwdSDFPS+RIEiQCdqmJxZMAtCmhcgMJV2+uSeKq7riO6Z0oNzqY5HpdSEgZdicG FwXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VvjDH0d9yENa4ecfbUN1MGRyNECdD1MomwyxKEWSk7s=; b=SqFTRudfxc/OWtvvjh7+CEcqD/RgLNKrI7bSD1vt6EJnU3mzYyED0ToPpRm06YrPXy hXSb2ukIOj3pTDgj9NtJfhs+pFDIDlIwOXvXbi5wRUnjRoK1CNKA2+lnKF7Ia/0nRJZP Uu6eYpH1gfssvZSd4Jh+xQqDH9bof8cQrBn5v2rtWPsASY9/6pdNOnNss8HK0v/mpFIX 1VYXjJFtHHHFrr5Bja2rdjbwlDHIMEXTK2zywUB61ghdPo9CqNEK7mHgBu9DRecE0Xol xi6IEtJCoonVf2cm3R+MXxO5zRqSkbEklkJLdxzCeBcKW52oHJWulsb2Bvl8Xb+QbG7c JIHw== X-Gm-Message-State: AOAM531pRAz1ib5+yp7Y/JHgHojvjB5nMAvoYyvFF6PSmOEePwH8bDZr Iemr4/8BBOiLHmT9ZXwmTYOe56i7lvuwWw== X-Google-Smtp-Source: ABdhPJyU2N5m8mTr6EonR402FvHKqznszH9nRohGj/5AVrkKXsmb6SHUsd1xOWB29qZIHmf6CzR6Xg== X-Received: by 2002:a17:90a:657:: with SMTP id q23mr15212296pje.192.1612751880053; Sun, 07 Feb 2021 18:38:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 04/70] tcg/tci: Merge identical cases in generation Date: Sun, 7 Feb 2021 18:36:46 -0800 Message-Id: <20210208023752.270606-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tci/tcg-target.c.inc | 204 ++++++++++++++------------------------- 1 file changed, 73 insertions(+), 131 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index feac4659cc..c79f9c32d8 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -380,6 +380,18 @@ static inline void tcg_out_call(TCGContext *s, const t= cg_insn_unit *arg) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +#if TCG_TARGET_REG_BITS =3D=3D 64 +# define CASE_32_64(x) \ + case glue(glue(INDEX_op_, x), _i64): \ + case glue(glue(INDEX_op_, x), _i32): +# define CASE_64(x) \ + case glue(glue(INDEX_op_, x), _i64): +#else +# define CASE_32_64(x) \ + case glue(glue(INDEX_op_, x), _i32): +# define CASE_64(x) +#endif + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { @@ -391,6 +403,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, case INDEX_op_exit_tb: tcg_out64(s, args[0]); break; + case INDEX_op_goto_tb: if (s->tb_jmp_insn_offset) { /* Direct jump method. */ @@ -404,15 +417,18 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, } set_jmp_reset_offset(s, args[0]); break; + case INDEX_op_br: tci_out_label(s, arg_label(args[0])); break; - case INDEX_op_setcond_i32: + + CASE_32_64(setcond) tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out8(s, args[3]); /* condition */ break; + #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */ @@ -423,60 +439,54 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, tcg_out_r(s, args[4]); tcg_out8(s, args[5]); /* condition */ break; -#elif TCG_TARGET_REG_BITS =3D=3D 64 - case INDEX_op_setcond_i64: - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out8(s, args[3]); /* condition */ - break; #endif - case INDEX_op_ld8u_i32: - case INDEX_op_ld8s_i32: - case INDEX_op_ld16u_i32: - case INDEX_op_ld16s_i32: + + CASE_32_64(ld8u) + CASE_32_64(ld8s) + CASE_32_64(ld16u) + CASE_32_64(ld16s) case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: + CASE_64(ld32u) + CASE_64(ld32s) + CASE_64(ld) + CASE_32_64(st8) + CASE_32_64(st16) case INDEX_op_st_i32: - case INDEX_op_ld8u_i64: - case INDEX_op_ld8s_i64: - case INDEX_op_ld16u_i64: - case INDEX_op_ld16s_i64: - case INDEX_op_ld32u_i64: - case INDEX_op_ld32s_i64: - case INDEX_op_ld_i64: - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: + CASE_64(st32) + CASE_64(st) stack_bounds_check(args[1], args[2]); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_debug_assert(args[2] =3D=3D (int32_t)args[2]); tcg_out32(s, args[2]); break; - case INDEX_op_add_i32: - case INDEX_op_sub_i32: - case INDEX_op_mul_i32: - case INDEX_op_and_i32: - case INDEX_op_andc_i32: /* Optional (TCG_TARGET_HAS_andc_i32). */ - case INDEX_op_eqv_i32: /* Optional (TCG_TARGET_HAS_eqv_i32). */ - case INDEX_op_nand_i32: /* Optional (TCG_TARGET_HAS_nand_i32). */ - case INDEX_op_nor_i32: /* Optional (TCG_TARGET_HAS_nor_i32). */ - case INDEX_op_or_i32: - case INDEX_op_orc_i32: /* Optional (TCG_TARGET_HAS_orc_i32). */ - case INDEX_op_xor_i32: - case INDEX_op_shl_i32: - case INDEX_op_shr_i32: - case INDEX_op_sar_i32: - case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ - case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ + + CASE_32_64(add) + CASE_32_64(sub) + CASE_32_64(mul) + CASE_32_64(and) + CASE_32_64(or) + CASE_32_64(xor) + CASE_32_64(andc) /* Optional (TCG_TARGET_HAS_andc_*). */ + CASE_32_64(orc) /* Optional (TCG_TARGET_HAS_orc_*). */ + CASE_32_64(eqv) /* Optional (TCG_TARGET_HAS_eqv_*). */ + CASE_32_64(nand) /* Optional (TCG_TARGET_HAS_nand_*). */ + CASE_32_64(nor) /* Optional (TCG_TARGET_HAS_nor_*). */ + CASE_32_64(shl) + CASE_32_64(shr) + CASE_32_64(sar) + CASE_32_64(rotl) /* Optional (TCG_TARGET_HAS_rot_*). */ + CASE_32_64(rotr) /* Optional (TCG_TARGET_HAS_rot_*). */ + CASE_32_64(div) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); break; - case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). = */ + + CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); @@ -486,79 +496,30 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, tcg_out8(s, args[4]); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 - case INDEX_op_add_i64: - case INDEX_op_sub_i64: - case INDEX_op_mul_i64: - case INDEX_op_and_i64: - case INDEX_op_andc_i64: /* Optional (TCG_TARGET_HAS_andc_i64). */ - case INDEX_op_eqv_i64: /* Optional (TCG_TARGET_HAS_eqv_i64). */ - case INDEX_op_nand_i64: /* Optional (TCG_TARGET_HAS_nand_i64). */ - case INDEX_op_nor_i64: /* Optional (TCG_TARGET_HAS_nor_i64). */ - case INDEX_op_or_i64: - case INDEX_op_orc_i64: /* Optional (TCG_TARGET_HAS_orc_i64). */ - case INDEX_op_xor_i64: - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ - case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ - case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - break; - case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). = */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_debug_assert(args[3] <=3D UINT8_MAX); - tcg_out8(s, args[3]); - tcg_debug_assert(args[4] <=3D UINT8_MAX); - tcg_out8(s, args[4]); - break; - case INDEX_op_brcond_i64: + CASE_32_64(brcond) tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out8(s, args[2]); /* condition */ tci_out_label(s, arg_label(args[3])); break; - case INDEX_op_bswap16_i64: /* Optional (TCG_TARGET_HAS_bswap16_i64). = */ - case INDEX_op_bswap32_i64: /* Optional (TCG_TARGET_HAS_bswap32_i64). = */ - case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). = */ - case INDEX_op_not_i64: /* Optional (TCG_TARGET_HAS_not_i64). */ - case INDEX_op_neg_i64: /* Optional (TCG_TARGET_HAS_neg_i64). */ - case INDEX_op_ext8s_i64: /* Optional (TCG_TARGET_HAS_ext8s_i64). */ - case INDEX_op_ext8u_i64: /* Optional (TCG_TARGET_HAS_ext8u_i64). */ - case INDEX_op_ext16s_i64: /* Optional (TCG_TARGET_HAS_ext16s_i64). */ - case INDEX_op_ext16u_i64: /* Optional (TCG_TARGET_HAS_ext16u_i64). */ - case INDEX_op_ext32s_i64: /* Optional (TCG_TARGET_HAS_ext32s_i64). */ - case INDEX_op_ext32u_i64: /* Optional (TCG_TARGET_HAS_ext32u_i64). */ - case INDEX_op_ext_i32_i64: - case INDEX_op_extu_i32_i64: -#endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ - case INDEX_op_neg_i32: /* Optional (TCG_TARGET_HAS_neg_i32). */ - case INDEX_op_not_i32: /* Optional (TCG_TARGET_HAS_not_i32). */ - case INDEX_op_ext8s_i32: /* Optional (TCG_TARGET_HAS_ext8s_i32). */ - case INDEX_op_ext16s_i32: /* Optional (TCG_TARGET_HAS_ext16s_i32). */ - case INDEX_op_ext8u_i32: /* Optional (TCG_TARGET_HAS_ext8u_i32). */ - case INDEX_op_ext16u_i32: /* Optional (TCG_TARGET_HAS_ext16u_i32). */ - case INDEX_op_bswap16_i32: /* Optional (TCG_TARGET_HAS_bswap16_i32). = */ - case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). = */ + + CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ + CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */ + CASE_32_64(ext8s) /* Optional (TCG_TARGET_HAS_ext8s_*). */ + CASE_32_64(ext8u) /* Optional (TCG_TARGET_HAS_ext8u_*). */ + CASE_32_64(ext16s) /* Optional (TCG_TARGET_HAS_ext16s_*). */ + CASE_32_64(ext16u) /* Optional (TCG_TARGET_HAS_ext16u_*). */ + CASE_64(ext32s) /* Optional (TCG_TARGET_HAS_ext32s_i64). */ + CASE_64(ext32u) /* Optional (TCG_TARGET_HAS_ext32u_i64). */ + CASE_64(ext_i32) + CASE_64(extu_i32) + CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ + CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ + CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); break; - case INDEX_op_div_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - case INDEX_op_divu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - break; + #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: @@ -584,31 +545,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, tcg_out_r(s, args[3]); break; #endif - case INDEX_op_brcond_i32: - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out8(s, args[2]); /* condition */ - tci_out_label(s, arg_label(args[3])); - break; + case INDEX_op_qemu_ld_i32: - tcg_out_r(s, *args++); - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out_i(s, *args++); - break; - case INDEX_op_qemu_ld_i64: - tcg_out_r(s, *args++); - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_r(s, *args++); - } - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out_i(s, *args++); - break; case INDEX_op_qemu_st_i32: tcg_out_r(s, *args++); tcg_out_r(s, *args++); @@ -617,6 +555,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, } tcg_out_i(s, *args++); break; + + case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: tcg_out_r(s, *args++); if (TCG_TARGET_REG_BITS =3D=3D 32) { @@ -628,8 +568,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, } tcg_out_i(s, *args++); break; + case INDEX_op_mb: break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YWPrxfItN4c65pZ/52Q4dTydvUr4VWbYL6z0GHLhLqg=; b=ky+rgAlw+9vYV5TxoHx5fVMBLP6FeQVBZqfdx7cUcgd7ARLCZVLyNNyZV7gWhL5aPM WKM48C3JTrzRL3pBtUhE+UNeRayodQBEYwZx1qhF1EbYyuWfCHL4AESy3IcIcgW+N+Wh fNFoE8DJ6lSUjgD4sdc5iY+W7VXKC5Yxea38uUnrWQNyAIpnupQeECdjUz3akmbbVHf6 KJphoXOk5rcRMrzW+0bUNvF2hj7Y7krnHRiVQJcp7P2hwUVXe/fGn1IzpOUbGfzaKEC3 Q6n+Lh+RVJaBffayRRS2VESg0PFBHLOZXaeJDpokKzVcIm31p1L9I5XhjZz+0iNfz6dd T2Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YWPrxfItN4c65pZ/52Q4dTydvUr4VWbYL6z0GHLhLqg=; b=jtOtfURTCe5NQkTuz/3vOXheby2yXdL2W0MkABAdtD7K7pwjWCxJmzCQZrRlvTasDZ ytAFVdLYauqMGyCkC5LlfhBl98VmC3ZzqG+t5aJ+RbD6PUsvq0ZLmXiKIqk7qCxMF6XD WePF26Q6oM/nELvKIRdeGYsj5oEknjxsTSLqnbFaMJjTAnjpWWK5MUQNmiQ3MIDlXLOU UyW6T6AJfRDpjh6HxltfjhXCcBQzxcLdzUPIGAr6i4JhkDhC8uIKx0sLBZdKejMB5HD6 UJIA0/4V8IGCUM3axa0k+qbSXHs1WBmMufYgiZrYpuTcbxTpyAdjenzcAJcKZOEplSbP JGqw== X-Gm-Message-State: AOAM531GU9EE7p8fHcs+MWnFrXZ80gpz3le4o2HH2mTcVf0DXlV2RnTr 6h6oMkmCHq1pSjQicCxwOOJ1CuBw6UO58g== X-Google-Smtp-Source: ABdhPJwsIbEg/JxfBhddaoXdd8sYlieunDd6HQjV3mbJALnSL0RWxkzHAU+88H0RyAfV72gM9fXjJA== X-Received: by 2002:a65:44c5:: with SMTP id g5mr15209542pgs.295.1612751881155; Sun, 07 Feb 2021 18:38:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 05/70] tcg/tci: Remove tci_read_r8 Date: Sun, 7 Feb 2021 18:36:47 -0800 Message-Id: <20210208023752.270606-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use explicit casts for ext8u opcodes, and allow truncation to happen with the store for st8 opcodes. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tci.c | 23 +++++------------------ 1 file changed, 5 insertions(+), 18 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index fb3c97aaf1..c44a4aec7b 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -78,11 +78,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *r= egs, TCGReg index) } #endif =20 -static uint8_t tci_read_reg8(const tcg_target_ulong *regs, TCGReg index) -{ - return (uint8_t)tci_read_reg(regs, index); -} - static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index) { return (uint16_t)tci_read_reg(regs, index); @@ -169,14 +164,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t= **tb_ptr) return value; } =20 -/* Read indexed register (8 bit) from bytecode. */ -static uint8_t tci_read_r8(const tcg_target_ulong *regs, const uint8_t **t= b_ptr) -{ - uint8_t value =3D tci_read_reg8(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} - #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 /* Read indexed register (8 bit signed) from bytecode. */ static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **t= b_ptr) @@ -550,7 +537,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); break; CASE_32_64(st8) - t0 =3D tci_read_r8(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) =3D t0; @@ -739,8 +726,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext8u_i32 case INDEX_op_ext8u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16u_i32 @@ -933,8 +920,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext8u_i64 case INDEX_op_ext8u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint8_t)t1); break; #endif #if TCG_TARGET_HAS_ext8s_i64 --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752007; cv=none; d=zohomail.com; s=zohoarc; b=covJNs3AJgwcPdZn/QvpBVoiNhCYehQ4DwwVBpH6gyOmspzhEgDPcYav16HM+6/cVZnMlDhxPTLpZRLPETuqoAZVgVg72bX4mxefc0LA+Oq4GsuhiYmiDlpIjdfwBCXxZ1lXIbKxiq9X9vU3BdOd4botUznokuCv99xv2AEttjk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612752007; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=r7Bqt7XeLpJxFziax4YcAvS468lSm4SfB1qZvFnNDEY=; b=NGEhzZj6AZIwHs3y+BWRFKylSdK1lMSqK+XuKpfMZd59mrSXsS69+vpbUF9Z73jJwE3AelHRISFV86WCo2SL1T2eZfJuKMOHaqE9XTyl8/xiqgEgjqcXxITSEyXggVQYeRlpGBKdKPFor17D/OF86/Wf54NRBl0Vf3n/ffxZmBA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612752007822117.28321283791092; Sun, 7 Feb 2021 18:40:07 -0800 (PST) Received: from localhost ([::1]:58064 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wT8-00037D-EI for importer@patchew.org; Sun, 07 Feb 2021 21:40:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57674) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wRB-00017b-9l for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:05 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:40849) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wR9-0005iK-Lk for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:05 -0500 Received: by mail-pl1-x62a.google.com with SMTP id y10so7018885plk.7 for ; Sun, 07 Feb 2021 18:38:03 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=r7Bqt7XeLpJxFziax4YcAvS468lSm4SfB1qZvFnNDEY=; b=kUgTCcYQ0K/MS0zvZUBPNlcNLrKrsRDQN11BeVg84JX29lK5q4ErlNDB+xXwhOAVuy p+9SOjmsWtTU9odnzsPVPtU/iXHN87SgIG5BSZPuh0ywjed61xvs0F4IiqQcqJWh74aq ZLVn4wOwi/6JOZInD5m1aQkLDtqF6WNftdvLju0tI0OuXZyo8WDCvR0kSv223QoG7jbj dol6seKxyNkKE5Spq6S9X1UZpymYejcnhTZv1aldhoWo1EjxMllBRsLgj9LXlSyP3wGb ee8wVfOO120+MAld89lyEBQYUV5u6X5VtmzrinndjXt7XumhONs9bxVZ8kPiYFOXgAYT +yvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r7Bqt7XeLpJxFziax4YcAvS468lSm4SfB1qZvFnNDEY=; b=muRPUtqNf5uyPHfbFjHwpyYty7LqpgFwvi1139wVYEZV2Yz779kIJioFe5W+dNPTpP jo9BCTCvAAhl/4W4tA+AvFMbjPyOFDntSXPaqs3FA42RsOVw7HU2HHjHxkBiBd15xLrF JaLCpN3YEs2FbHYZlu/Wr4q9SfvmcDlvRyNNxWkHyIi2FNx8zCOt7QeNXs/yED96pqDs beKr3mFx8KTkNVdhnEOzqVl6KK4GBAZtw5b7tHduT24BWq9ND6cRBpiPzB2lmbAwARCD PU41Vo88Y9RZTeMHN7DdG89Pu9NM9RS2ZhYahR3jS097lP64aq60rpMMTPCtYidyWUPn G8dA== X-Gm-Message-State: AOAM530K8YYohnlbtEQOGIPOYKd0nYcLnfgARHInbWLJxoF4tO8IoP2l 8eTtS72KOdAH+09cNmc+UFFI34FQwbaRUQ== X-Google-Smtp-Source: ABdhPJyqwM3UEf0WHYD8h/fuWSPyl0hlflK/ayo+aBOASOEFXYiJkyLoaGhmR6F9KLLBIvFMjG9VfQ== X-Received: by 2002:a17:90a:d34b:: with SMTP id i11mr14627214pjx.235.1612751882411; Sun, 07 Feb 2021 18:38:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 06/70] tcg/tci: Remove tci_read_r8s Date: Sun, 7 Feb 2021 18:36:48 -0800 Message-Id: <20210208023752.270606-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use explicit casts for ext8s opcodes. Signed-off-by: Richard Henderson --- tcg/tci.c | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index c44a4aec7b..25db479e62 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ul= ong *regs, TCGReg index) return regs[index]; } =20 -#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -static int8_t tci_read_reg8s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int8_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) { @@ -164,16 +157,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t= **tb_ptr) return value; } =20 -#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -/* Read indexed register (8 bit signed) from bytecode. */ -static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **t= b_ptr) -{ - int8_t value =3D tci_read_reg8s(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} -#endif - /* Read indexed register (16 bit) from bytecode. */ static uint16_t tci_read_r16(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -712,8 +695,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext8s_i32 case INDEX_op_ext8s_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 @@ -927,8 +910,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext8s_i64 case INDEX_op_ext8s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i64 --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752010; cv=none; d=zohomail.com; s=zohoarc; b=A0UrSi6A9u2tUCmYgrIKNyGA71sj7rJuNAqzAgNtPcP/S/ipQXOxuXw9WPqFgO5y0M0cRVYnK1+onQAMb2pUEd97jiZck1kKFrEGDo0mbmb3TSleyqG1nQ7ozEx0PfNgt/P4TmQLLQpmOb56ShDiAhad/UwxvH/50dLoGRJdS6o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612752010; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0czCalkGz4G3rt/KJuGxDoZrx0T/yMn7B2Kkowe9hTk=; b=nHOsU9Ms6bnFF60tLTkn3m3nRwbUqSub2l2NBFymGw0jHyD4XdMVCRBt1Avn8HIYqcDzzt1QfZ4Pcif6KmPtsfRwYcFKZ27NAldjU+mkNJyWYA7EZgS8eLxBU8DNpuaJcJiFK6Qmw1evT9hbImzm+SJsmKfacjD1TjAHecUKa7s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612752010569594.7135571077134; Sun, 7 Feb 2021 18:40:10 -0800 (PST) Received: from localhost ([::1]:58134 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wTB-000398-CF for importer@patchew.org; Sun, 07 Feb 2021 21:40:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57688) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wRC-00019e-Hd for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:06 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:37576) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wRA-0005iY-T6 for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:06 -0500 Received: by mail-pj1-x1033.google.com with SMTP id t2so2758873pjq.2 for ; Sun, 07 Feb 2021 18:38:04 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0czCalkGz4G3rt/KJuGxDoZrx0T/yMn7B2Kkowe9hTk=; b=dNo8LMZ0qTgPXS4viJ3SsOETzX+m0qzkl+fDfEWJzhHLu5yAX+P38TIjsM9rVGBIut hRnf+jN4hNqdXVUdOSavOOrIXkIOZ5eoqqCum8AV+As9rAvbkSXLx+0/M/7TqaYUz4vv vb7QeN+Aua8tzQgME+mFGPapGsTMtZ90pncfKxxf8PUYR0tNazQgjR7TOsI8j+lv4JKr CPAhch6QkeDTQig72G7t88RPEPbbe28/EL4MSkb99WSVHAvbpDqtY4Nor+qmYRju9ApV xx2PhpxUu+ccuiN3450AhcSxbXQ9bFIZU4jX4rwI1mjTIT089AUXAv9YhIvSvepS6TeN uMJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0czCalkGz4G3rt/KJuGxDoZrx0T/yMn7B2Kkowe9hTk=; b=KIrLWKDctPGBHBioO9nywzHm46RLV52oQv9KegUmTSCcAHZw4Nm3Xnl8jsHTgPgXkJ N/oreQRzownli3QEgQvRvy1Wl3xjMKaFjVUyU5f40IJ+ymOmAwVeLdZt9p6EeCkM7htc ov3swapRjmu/lcJSoTxDIvyAq/D7EcqYXDnPFJDe8jtc96+abqCcvjATifUNd6o+LTQV fT86/mrf4oOWtBaEhnHs374NyAxawKjTnwMYFiyPuzjDPRCAvCv4O8EJKa6dKkILGn0/ eWsvX3Mh0dTmX/sMySEJMdvXXDuCJG5PlkurI5fWukbAhauz44XvUm2CFjq2pbno0yGV it8A== X-Gm-Message-State: AOAM531iT0XEpakBD27PWq1V6dWd7Ts0Wo/XrKSu+2+HYSqflyV2hzKK ruN+6aReHcPV9/j4GmOq0PTixJb7zZlsHQ== X-Google-Smtp-Source: ABdhPJzu2eEFQxTaoOxnq8ao4o8+ZhEGAx/dskJ7KSReZosaZww4T07TmG4HCCNcMVESwvJnWoahhw== X-Received: by 2002:a17:90a:6342:: with SMTP id v2mr14284492pjs.150.1612751883683; Sun, 07 Feb 2021 18:38:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 07/70] tcg/tci: Remove tci_read_r16 Date: Sun, 7 Feb 2021 18:36:49 -0800 Message-Id: <20210208023752.270606-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use explicit casts for ext16u opcodes, and allow truncation to happen with the store for st16 opcodes, and with the call for bswap16 opcodes. Signed-off-by: Richard Henderson --- tcg/tci.c | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 25db479e62..547be0c2f0 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -71,11 +71,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *r= egs, TCGReg index) } #endif =20 -static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index) -{ - return (uint16_t)tci_read_reg(regs, index); -} - static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index) { return (uint32_t)tci_read_reg(regs, index); @@ -157,15 +152,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t= **tb_ptr) return value; } =20 -/* Read indexed register (16 bit) from bytecode. */ -static uint16_t tci_read_r16(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - uint16_t value =3D tci_read_reg16(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} - #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 /* Read indexed register (16 bit signed) from bytecode. */ static int16_t tci_read_r16s(const tcg_target_ulong *regs, @@ -526,7 +512,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, *(uint8_t *)(t1 + t2) =3D t0; break; CASE_32_64(st16) - t0 =3D tci_read_r16(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) =3D t0; @@ -716,14 +702,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #if TCG_TARGET_HAS_ext16u_i32 case INDEX_op_ext16u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint16_t)t1); break; #endif #if TCG_TARGET_HAS_bswap16_i32 case INDEX_op_bswap16_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif @@ -924,8 +910,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext16u_i64 case INDEX_op_ext16u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint16_t)t1); break; #endif #if TCG_TARGET_HAS_ext32s_i64 @@ -947,7 +933,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_bswap16_i64 case INDEX_op_bswap16_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752189; cv=none; d=zohomail.com; s=zohoarc; b=IZuFnQhfAv3ahsgzhzwy1PEqNBkd/OJEujsxgZI1fJcgpJMBj6dAKD42RE1iQ90/6WysGNdz8mrE39vChdunYt+LN5h4Z2Ejn4STfpH7tCO/OgUF++FhwFRqPEAEyTb6Gw0ZtjGr9ufBZ4KGvUVXLKx+z3r+2EmEAeTJHJ+6fU0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612752189; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bftKwEjBKL55PhIU9GHzhO+7UtwI+bC8nwnUqZAh2tk=; b=QvtErDVuCTQU0f2tpCLxqCBE2+8Avw4M9p39NLpVCuTNd877lgVsA6ICK2Tai7pViFjT0Mi6bj4FrZJCLjzyF0Yg2O4fuhZOTNp1LEtTeuZcPv+PUsr9NShMqHfWgawMWh3DxY/aiyYfESnWCrZgH3e+90gkLReBKuYhMhTbZzk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16127521894721001.148159858242; Sun, 7 Feb 2021 18:43:09 -0800 (PST) Received: from localhost ([::1]:38486 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wW4-0006km-CG for importer@patchew.org; Sun, 07 Feb 2021 21:43:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57702) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wRD-0001Bp-Of for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:07 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:34881) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wRC-0005in-3E for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:07 -0500 Received: by mail-pl1-x62c.google.com with SMTP id g3so7034923plp.2 for ; Sun, 07 Feb 2021 18:38:05 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bftKwEjBKL55PhIU9GHzhO+7UtwI+bC8nwnUqZAh2tk=; b=QRpDU5oCcinbKxqZtGfTQGF7tqIeDWBfznDkZewcBhZXMlCmji9aArq1oRGbMjkIIx ACsXKaVzK/g2CmPWJ7BzQ19VYdQhwjkZlCRLRdF+F/aNNz/sSfMz4Ju9PBoO1xA7VAhp MTf1pCW85Gf0asjWiPXHM938KiEYUC839lGorqm0RwjMFBJG2cvE3t3F0iAUib6acmh7 KRi0wW2/i28yDkGJD7itX+ETlTNdZWBhEBFHIkKj46xixbZ3PIvR9NX2cHygQ3+2ljX/ rGFEg5EUynsOEW81q5eUVPLADzL/aytFS0ilDR8G64Gy55cF8Qfqh9O3BBoeBBw6GXB0 Xq0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bftKwEjBKL55PhIU9GHzhO+7UtwI+bC8nwnUqZAh2tk=; b=pAyKJpdlajv9CnhgN7rdiFEm3jJPU1RnW6IkLuixiiFH3VZkaVQAW8snqrtuHQAp3/ CDYUdffDdufyraFFArznV3kPDR94zQF5hI37g0eOi8mXQhGzD4n43GIHqRj6K6pxbV/0 Auu5KNURUHng5M8KD2IPFC8EHMwDultz4QOe4KvNsuk32DUtiXXWEln875hBBW/MtGva zPsKq5rj9DrpyJEmELXeqNR7rO8S1rl09uPpkEcvNPQFbPCA591yTavY54adpqmR/jtI +lmmoRqd82CEwAoQFQFuDaAyv3RJOn4i78pXGc/w0VdviAzbOVqWDmdV6K7ZXh3W3Q2k bm4g== X-Gm-Message-State: AOAM533jWbW/EYP0S7FaaoBbi4enEt3XQfw/7rwS0VenlC7mAMDJqapC sgsTRX0JCZLtpQ9W71lj3WVVYgwOdjewag== X-Google-Smtp-Source: ABdhPJzprUQ5igeMUGWAc32G6/6rRg5C0RFuswuKbUBTgwC+3Hhr5iERrT7e5y4+0iFJ0Lo9L2Bofg== X-Received: by 2002:a17:90a:aa85:: with SMTP id l5mr15237938pjq.230.1612751884856; Sun, 07 Feb 2021 18:38:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 08/70] tcg/tci: Remove tci_read_r16s Date: Sun, 7 Feb 2021 18:36:50 -0800 Message-Id: <20210208023752.270606-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use explicit casts for ext16s opcodes. Signed-off-by: Richard Henderson --- tcg/tci.c | 26 ++++---------------------- 1 file changed, 4 insertions(+), 22 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 547be0c2f0..d2bfcb3c93 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ul= ong *regs, TCGReg index) return regs[index]; } =20 -#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int16_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_REG_BITS =3D=3D 64 static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) { @@ -152,17 +145,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t= **tb_ptr) return value; } =20 -#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -/* Read indexed register (16 bit signed) from bytecode. */ -static int16_t tci_read_r16s(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - int16_t value =3D tci_read_reg16s(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} -#endif - /* Read indexed register (32 bit) from bytecode. */ static uint32_t tci_read_r32(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -688,8 +670,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext16s_i32 case INDEX_op_ext16s_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int16_t)t1); break; #endif #if TCG_TARGET_HAS_ext8u_i32 @@ -903,8 +885,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext16s_i64 case INDEX_op_ext16s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int16_t)t1); break; #endif #if TCG_TARGET_HAS_ext16u_i64 --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752336; cv=none; d=zohomail.com; s=zohoarc; b=XDD++s3zkPWRPNafRcgq7Zw2TIbQvv+nREoJd80LR0HszK+89YY2KAMU8pcEQtCxHqYbDfkdTVD5j5FrNpwD/3wHoufCI3s4lPlTR8Yk0aG3HKRqQpXxEjI/mEufpVoEbah61coUtwSo6twoJVyq67YbGawqXplEt/emRmp52us= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612752336; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2u2lbOSRco87Z5Lz8RFNE5CKuXtUEmG/NCJRjRL/uNk=; b=FzLT8zkHfcA1fZUhMicCbfUu1Euq0V94VyGeq0Q35EXua+kf3K3XiBV/GgDGye2jJGWbIHRPFGQAeLvnaT/h64nPnaw5VBuaq1ppeZGYxUo4M+fIAD2TwyL4Iad5ok53SRT/yEEKDC8aRGzcLYWPl1IiGWz/TeQXus15Nc/uHE4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612752336753306.5288499154826; Sun, 7 Feb 2021 18:45:36 -0800 (PST) Received: from localhost ([::1]:47112 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wYR-0001rK-JE for importer@patchew.org; Sun, 07 Feb 2021 21:45:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57724) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wRF-0001Fb-8d for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:10 -0500 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:44647) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wRD-0005je-6f for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:08 -0500 Received: by mail-pg1-x532.google.com with SMTP id j5so451818pgb.11 for ; Sun, 07 Feb 2021 18:38:06 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2u2lbOSRco87Z5Lz8RFNE5CKuXtUEmG/NCJRjRL/uNk=; b=yLWQ7yC3JWxnfJoMhCx53AMaBrifeh69Ycg8crIRiB4Mt8SDBaRAEcSPB6S5l0x+jA 1c2aBBWZCOT5wS/kXizktyZl+sUjfQnWtVaAZ+ViDg075ZxMsfCl1wz92UMITMiY5FvJ HtlSiF2f8zfcf7H2X6RR4qWn/xSQmn1i/MQ+b2RGcVUamf61rTLQ1gDwqG+/U6Wq7XiD JEv6RqGr2WtyruNIzcdvqV7s9IHvi21CYzLtsiqOr+q+SihimGBU02wYHlj8WDSbDdcn OOorXo6o7PYAj9aPkH6898190bjGqnQjlWTtLfV+cqxe0djfj7qwOOH0HPpp7ipv3UFv tS0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2u2lbOSRco87Z5Lz8RFNE5CKuXtUEmG/NCJRjRL/uNk=; b=hlZ9s/AGRPmTSSzuPkLvgH9fbNKWs8L3vV86x5qJdWcZi1e8rwWfvTzr5V8DJwOd/E jlBB5ZYltxeLbuc2m3GctUbdYLS4QV95YqWmfqwec/wriEg0UxPiGaML6PTuQCx5wG92 j01z6qM0kNTBejqCyntSzcx3m8B3Iq/J61mKkl1H5nwAJsc/TRJTz52F62dOu+xbHc+e JVqzmVF2W6ByEBkDKciQVLC3v8wIqJ5UVjQUKeG9SXlD9EHLaTftCcqiXpQHpNlQYu0C HW5Ai5mmqzqsj0Kc19yq7EW6HS4Zs1M/M+vXAFiADYu39YDWwSDWGx4pK/tEgMFQ90Nw uUOQ== X-Gm-Message-State: AOAM5314ZwU+j8Dm8vaCUteqLlBYMlehRKeYmqRWW+e/ul+flLUMxEdA TKHnhZlO5KOHARnnfY9BGgcbJKRQxua/uA== X-Google-Smtp-Source: ABdhPJyV4Osvy2y5lpdf17II/Wwgo3qpo52LgXfZJzyr13IGnvTQt+eNrgKVY0CoTZAPMPnUCNK71g== X-Received: by 2002:a63:dc56:: with SMTP id f22mr15036459pgj.106.1612751885845; Sun, 07 Feb 2021 18:38:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 09/70] tcg/tci: Remove tci_read_r32 Date: Sun, 7 Feb 2021 18:36:51 -0800 Message-Id: <20210208023752.270606-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use explicit casts for ext32u opcodes, and allow truncation to happen for other users. Signed-off-by: Richard Henderson --- tcg/tci.c | 122 ++++++++++++++++++++++++------------------------------ 1 file changed, 54 insertions(+), 68 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index d2bfcb3c93..72ec63e18e 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -64,11 +64,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *r= egs, TCGReg index) } #endif =20 -static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index) -{ - return (uint32_t)tci_read_reg(regs, index); -} - #if TCG_TARGET_REG_BITS =3D=3D 64 static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) { @@ -145,22 +140,13 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_= t **tb_ptr) return value; } =20 -/* Read indexed register (32 bit) from bytecode. */ -static uint32_t tci_read_r32(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - uint32_t value =3D tci_read_reg32(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} - #if TCG_TARGET_REG_BITS =3D=3D 32 /* Read two indexed registers (2 * 32 bit) from bytecode. */ static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - uint32_t low =3D tci_read_r32(regs, tb_ptr); - return tci_uint64(tci_read_r32(regs, tb_ptr), low); + uint32_t low =3D tci_read_r(regs, tb_ptr); + return tci_uint64(tci_read_r(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 /* Read indexed register (32 bit signed) from bytecode. */ @@ -421,8 +407,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, continue; case INDEX_op_setcond_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); condition =3D *tb_ptr++; tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); break; @@ -445,7 +431,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif case INDEX_op_mov_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i32: @@ -501,7 +487,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; case INDEX_op_st_i32: CASE_64(st32) - t0 =3D tci_read_r32(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint32_t *)(t1 + t2) =3D t0; @@ -511,62 +497,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_add_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; case INDEX_op_sub_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; case INDEX_op_mul_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; case INDEX_op_div_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); break; case INDEX_op_divu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 / t2); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2); break; case INDEX_op_rem_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); break; case INDEX_op_remu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 % t2); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); break; case INDEX_op_and_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 & t2); break; case INDEX_op_or_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 | t2); break; case INDEX_op_xor_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 ^ t2); break; =20 @@ -574,41 +560,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_shl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 << (t2 & 31)); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31)); break; case INDEX_op_shr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 >> (t2 & 31)); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31)); break; case INDEX_op_sar_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, ((int32_t)t1 >> (t2 & 31))); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31)); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, rol32(t1, t2 & 31)); break; case INDEX_op_rotr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ror32(t1, t2 & 31)); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp32 =3D (((1 << tmp8) - 1) << tmp16); @@ -616,8 +602,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i32: - t0 =3D tci_read_r32(regs, &tb_ptr); - t1 =3D tci_read_r32(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare32(t0, t1, condition)) { @@ -655,9 +641,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_mulu2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - t2 =3D tci_read_r32(regs, &tb_ptr); - tmp64 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, t2 * tmp64); + t2 =3D tci_read_r(regs, &tb_ptr); + tmp64 =3D (uint32_t)tci_read_r(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 @@ -698,21 +684,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #if TCG_TARGET_HAS_bswap32_i32 case INDEX_op_bswap32_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_not_i32 case INDEX_op_not_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i32 case INDEX_op_neg_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif @@ -909,8 +895,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif case INDEX_op_extu_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1); break; #if TCG_TARGET_HAS_bswap16_i64 case INDEX_op_bswap16_i64: @@ -922,7 +908,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_bswap32_i64 case INDEX_op_bswap32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); break; #endif --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752328; cv=none; d=zohomail.com; s=zohoarc; b=eeVrepn65UClj2X6M+t5mvzijFGacXYpZ0BPLga/VJCTCcbkJf9wNLuhqvkmB7Yp+gshCA7s8X+IVlfGXtKJJ8LZZTHoIIIU/J0fQOj9160DUe8vjzK45g6Tb13R2IY9kRr0JfXDBqVTyVMV4vnkr2V1Y9ucbPoxY5VYp1Eu/DU= ARC-Message-Signature: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ybRVe+0cbcMgdImiuixof8hM4eoxKsh03sT+tgpyyEY=; b=cAi50Qf84e7nSx599Ea0JBKI7RNk32ZqRh46M7ZyXA3wqsmCFgu7W+s4EQ5/9j3chI 650fY7eVAD0G2dYn9grBVIezjjJj7NroZCgYsnuoqBnlywodg6d67omJZ72dxtAKTPTa jL0fjCd5T/JzTMqE63NIbYu/RgWvr39Ui1zeQMX/V2kLb/hzJMh0OTgB2l6MRM1fIJqf DiuPVn47BRGnbld4ryLFImaLR5y2Af+268fcC3+RpukIoZ4cBg0FiT3wpjl7Oviplepy bzyqH/u1Yz2r+8F34T/HY76VUEB5qOOlb9F7k+rROL6FA9LF6vAbZW/KwG2NiTmLqTdh O88w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ybRVe+0cbcMgdImiuixof8hM4eoxKsh03sT+tgpyyEY=; b=T1vPfNVqfPN6E2YSVLB+PA2sezVxHiGRfDBN2zJ8oy4EIkjMMsXn9hkpzxwcDynd0Q njIKXFH5D3D3J0vslukbbtfjYXXdkdrAoTTdRjRBH8tY3lAs6twYiVova5vb0Wql8x7b vgkUCg9b1QlBCNctpKVBhWFKj8mOz2NJNayswQkAO/HXJINIYf9p+VsHBqWd+lGq5kA3 0HbCpyxwKfQX1ZDcjBd8xC0oxz51kp/H2UpmW8LchhOP1WouMLdqoxUJzbRGBohBEJjr Ewotqc6JFWIcsySSTjEaGjSYVxVKo1yiPfuBWbuLvFhqw3XkpnFMrS2O9m18h6mzfQqV /X8Q== X-Gm-Message-State: AOAM532tFn8Gr2WxllQm41os894/wlNrA5JjYDPufYKgZ7DL7Mucn8NB eOCQUkjvAGdOdxXvi+kVnmM91Fti8eat3g== X-Google-Smtp-Source: ABdhPJwV2BXmlb6tf6qy+gCpOoLDOimqQ/RiCNtvBKjdZjwMygEcinRgXUYN+eDeYG4i6/hWBcNgHA== X-Received: by 2002:a63:1f21:: with SMTP id f33mr15477808pgf.31.1612751887028; Sun, 07 Feb 2021 18:38:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 10/70] tcg/tci: Remove tci_read_r32s Date: Sun, 7 Feb 2021 18:36:52 -0800 Message-Id: <20210208023752.270606-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use explicit casts for ext32s opcodes. Signed-off-by: Richard Henderson --- tcg/tci.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 72ec63e18e..9c8395397a 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ul= ong *regs, TCGReg index) return regs[index]; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int32_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_REG_BITS =3D=3D 64 static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) { @@ -149,15 +142,6 @@ static uint64_t tci_read_r64(const tcg_target_ulong *r= egs, return tci_uint64(tci_read_r(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 -/* Read indexed register (32 bit signed) from bytecode. */ -static int32_t tci_read_r32s(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - int32_t value =3D tci_read_reg32s(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} - /* Read indexed register (64 bit) from bytecode. */ static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -887,8 +871,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif case INDEX_op_ext_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int32_t)t1); break; #if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752766; cv=none; d=zohomail.com; s=zohoarc; b=H6VBw5eeKU9EYXUzuVKm5C/22peJWeh0W3wkK6bY4AQ6Lsy2cGWnGJg6iT2pdBg7ZHeiV2kGndffBY765rxgtpCJQkV5qHJlvU5h5IiaJgZyyU9Zo59wfmBcB3CF+iGo4xw3XrKPS1KSjqAuj+P3szW8h25cyC2ZP3svNccNQ/8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612752766; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rPMFB2Q7bqmshseEZXdi4DH7vz7QmPfw5K/IzP922xY=; b=ExpP7ie+6qS2V+koABSdZB84ykqTtB/SFBmFNh52BN8Frb/hGl3b/661imtpVJAOiAq77skDCd+CPiJcYu48Wy1qporGSDjP383JPvghvWRjbtDIlrWmQUjvkFUHSmAJzIqT1JqEq10JGsCLjtPiwFrj9IfPtnCLtRgsL6OhnXg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612752766018883.787841476396; Sun, 7 Feb 2021 18:52:46 -0800 (PST) Received: from localhost ([::1]:35016 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wfM-0000NM-9s for importer@patchew.org; Sun, 07 Feb 2021 21:52:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57756) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wRH-0001H0-PI for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:11 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:37988) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wRF-0005jt-88 for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:11 -0500 Received: by mail-pl1-x62d.google.com with SMTP id x9so7025838plb.5 for ; Sun, 07 Feb 2021 18:38:08 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rPMFB2Q7bqmshseEZXdi4DH7vz7QmPfw5K/IzP922xY=; b=qu7eNuks6726v8OOMHl8PZoy0qeqLKKGuWn4UB/jMjbdJ30LZ/WKv3dXAdeMVxzdCU ZQtHTD3jr86kkyq7ok8ORCzzQp+K2EnAGUDBDIu/5kgM251xJxY9gxK6mXgRS47E3oJS UtWGaPNTAxptAU3OQO5laV3v6EvJHx36H8R1rxMr+HM0XiYnwJHE8FJf/wvUDRSTdXZW l/Fzzkog+JfjsU9w0mDegI+cd42Y+w3GG3O7BP+qJThdHItN3mAuFWsfpckbpuyItAbo 43wlerD+8v+SHxaqdbRRPsQjvr1BBjMC6jtMEyGEytMEdEf2THXBeGMt2uO603iOvURU l1Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rPMFB2Q7bqmshseEZXdi4DH7vz7QmPfw5K/IzP922xY=; b=rhurFPmHzN9ftOPBNYMe/PiVxBfwd/PJz3j0tj7SnPjcwPkKL9l/WOCU4/JuNfoTeD leAQKGo3cWaJW+YUBXN9lelCy4/aWcQ4KLawAAJQQ8ibALYOXha4K8DuN+DjH9xlZkrI XYWUvNIA/QXJxydTgryYprrahLwZP9EDgV6qr5/YX6AE/3WAe/dHD+ZqkkOG7zbtLHU3 ByHgxeDSke4L1rDrRAZXW97mqH+2w3LC0Rk9Xh+juRV5sqJX0yhUfS1tprIXGSLEAB5C CY+51PFb9SZiekrLCKVtDGm1PG2fGA2mWWvfVOHH5uLlYI3xLNxAlLUt0IkcsA3f2q2o eOyg== X-Gm-Message-State: AOAM533Uy0EfUKXdExJa+ARpx3EVAwNJ3R/b6DI7L7yS6Sm6y9+cb2X1 sw0c0OH/yodi3eifh32Rr63zO9P6z9Fklw== X-Google-Smtp-Source: ABdhPJw8l/kAgNwean6hcuBLhSBx/2LMqrGVmi6LokCk1f9NMgXbLWH1nkpKBFFfW37sBRyFPF2Bmg== X-Received: by 2002:a17:90a:6a07:: with SMTP id t7mr14649215pjj.194.1612751887931; Sun, 07 Feb 2021 18:38:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 11/70] tcg/tci: Reduce use of tci_read_r64 Date: Sun, 7 Feb 2021 18:36:53 -0800 Message-Id: <20210208023752.270606-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In all cases restricted to 64-bit hosts, tcg_read_r is identical. We retain the 64-bit symbol for the single case of INDEX_op_qemu_st_i64. Signed-off-by: Richard Henderson --- tcg/tci.c | 93 +++++++++++++++++++++++++------------------------------ 1 file changed, 42 insertions(+), 51 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 9c8395397a..0246e663a3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ul= ong *regs, TCGReg index) return regs[index]; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) -{ - return tci_read_reg(regs, index); -} -#endif - static void tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) { @@ -146,9 +139,7 @@ static uint64_t tci_read_r64(const tcg_target_ulong *re= gs, static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - uint64_t value =3D tci_read_reg64(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; + return tci_read_r(regs, tb_ptr); } #endif =20 @@ -407,8 +398,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); condition =3D *tb_ptr++; tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; @@ -689,7 +680,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_mov_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i64: @@ -713,7 +704,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st_i64: - t0 =3D tci_read_r64(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint64_t *)(t1 + t2) =3D t0; @@ -723,62 +714,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_add_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; case INDEX_op_sub_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; case INDEX_op_mul_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; case INDEX_op_div_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); break; case INDEX_op_divu_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); break; case INDEX_op_rem_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); break; case INDEX_op_remu_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; case INDEX_op_and_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 & t2); break; case INDEX_op_or_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 | t2); break; case INDEX_op_xor_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 ^ t2); break; =20 @@ -786,41 +777,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_shl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp64 =3D (((1ULL << tmp8) - 1) << tmp16); @@ -828,8 +819,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i64: - t0 =3D tci_read_r64(regs, &tb_ptr); - t1 =3D tci_read_r64(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { @@ -899,21 +890,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap64(t1)); break; #endif #if TCG_TARGET_HAS_not_i64 case INDEX_op_not_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i64 case INDEX_op_neg_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DTK4SJ5LYtJuHvuHu8AwQw2u8TQxf0ZzT7dsGBYnc0Y=; b=yY+M2DBVqN7G7/N0ierStD/e3CHeouNVaH65ToWfywhl2JB9DqWzOhDeVsSzKJzN2S FgQYusjqoIURH6Z3/XJyD99fS1u1P8bVtZNEpRQti8B32UP92EaIen8vWqVCmwDZQn8H ByJY7aw2B0EvxZOeIOlc8CmLTfrno7bBUclJ8vVZJDtOLk9X1YVbMEShHo7zy2r95/zI eXIKl9Aq7S+ZX+YvF+WdU4i2djGYKo1XRDboYaUqCPLLH6QFQYTxdu4YrYPNh83YC8yP QhILm6Nmc4jK/13VTQlTC0vw+azmCrounFEypUu+5zuz14R2CoC9ZjzJVhV8+gr0JlPj CUfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DTK4SJ5LYtJuHvuHu8AwQw2u8TQxf0ZzT7dsGBYnc0Y=; b=XuG6MViTtTnvJ0EEcQPPdTHJzewWwW/2TjDUo4DYrlDu0cNzaqJoOTp5aHRgqy01SK atXeux3a24SRrTNh4RNiiJXqwbCQJuTtfGF6tv6R6kxC59WRjMGYFA3/xxmy82AJcBfF XM625tvcYfr/tah/4z7sABWcW92XiG65eadiXgx3svIPytvvXPpJmzqnwf2lVxIl+rtB HZAEjHbbno5iUrrO02sNeURUYxw6Fm5tOgXxiV3jdUOew+9xGJ4wVrjaSPXaqTs3qt8/ UJZrNQ3I/fKA3HWlw6KXTf4THOljPqE2PZxZvyNsrgQkiINBXbqEYz+XSOGqMUvorw3z lFUQ== X-Gm-Message-State: AOAM5306Rjfiv7c3zEZhPnOIUBKNn5KCX4IDvgGQH3/9OcEPTgzxAi1E Gsbp20VYA9E4Bu4HTRyrmeu6iThTbnEMmA== X-Google-Smtp-Source: ABdhPJxmmhp3+/Hqf+2pyfVDogQvkGrkRuxLCN83gU+nVF7o/Lu+84SPKuYcjg8z8WCjKzFZQI0swQ== X-Received: by 2002:a63:587:: with SMTP id 129mr4300992pgf.233.1612751889120; Sun, 07 Feb 2021 18:38:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 12/70] tcg/tci: Merge basic arithmetic operations Date: Sun, 7 Feb 2021 18:36:54 -0800 Message-Id: <20210208023752.270606-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This includes add, sub, mul, and, or, xor. Signed-off-by: Richard Henderson --- tcg/tci.c | 83 +++++++++++++++++-------------------------------------- 1 file changed, 25 insertions(+), 58 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 0246e663a3..894e87e1b0 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -468,26 +468,47 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, *(uint32_t *)(t1 + t2) =3D t0; break; =20 - /* Arithmetic operations (32 bit). */ + /* Arithmetic operations (mixed 32/64 bit). */ =20 - case INDEX_op_add_i32: + CASE_32_64(add) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; - case INDEX_op_sub_i32: + CASE_32_64(sub) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; - case INDEX_op_mul_i32: + CASE_32_64(mul) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; + CASE_32_64(and) + t0 =3D *tb_ptr++; + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, t1 & t2); + break; + CASE_32_64(or) + t0 =3D *tb_ptr++; + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, t1 | t2); + break; + CASE_32_64(xor) + t0 =3D *tb_ptr++; + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, t1 ^ t2); + break; + + /* Arithmetic operations (32 bit). */ + case INDEX_op_div_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); @@ -512,24 +533,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); break; - case INDEX_op_and_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); - break; - case INDEX_op_or_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); - break; - case INDEX_op_xor_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); - break; =20 /* Shift/rotate operations (32 bit). */ =20 @@ -712,24 +715,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, =20 /* Arithmetic operations (64 bit). */ =20 - case INDEX_op_add_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 + t2); - break; - case INDEX_op_sub_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 - t2); - break; - case INDEX_op_mul_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 * t2); - break; case INDEX_op_div_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); @@ -754,24 +739,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; - case INDEX_op_and_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); - break; - case INDEX_op_or_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); - break; - case INDEX_op_xor_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); - break; =20 /* Shift/rotate operations (64 bit). */ =20 --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752564; cv=none; d=zohomail.com; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b0OZ8HZNEJw4TVjXNMfY9ukiBorqmrftQz6h6YJ1/P4=; b=hFk2RcxsCbAnQ8rgRutcBjlLBtpYCeFzCIpyow2O6uZ3rnQ9f6aS2bpiz19BvAWSyb ebT+8aX8OIgb2DOMcO84AIVbHQjtWkIvrfeLXqfsHMix8axRrT+vTmUNpCJbRM8NMgo1 o9mW5z7wd+hIEWqP+AVe1JDwaKIcoRPfsRgdKsy9BCz6c+NQfmQMkgcVF4dEqxylV/yQ lPRpf2529t2H9qXFIRL6qD4uXfMEsEuFZTV4s3Ce4BcfriisrxvA7IwiIf4aYs5vMVy0 YwT5XjOM8mcEhMOAt5foqB/+JJ9y9Xe2WaMHoniEiAkPbPNfwBXndEw3s2KuNCSO/umh IMeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b0OZ8HZNEJw4TVjXNMfY9ukiBorqmrftQz6h6YJ1/P4=; b=TWCm8hMx/YQBbj0WB33pxLqRthrksSEwrb3TV/y+D+TC4wJQO36APFD6QCzTARvPB1 ytiiWUUuMroSA5tC0wmmd+q3AornnYRjz8Oj7sHrKw+P7O4upZE+EY46BP1m6NI7dd7d xeEUpSzznDiYqiD3wAkT0dApjX/Pjto20B8tfafMfqnL8S22G6slEW4U//WSdPh94ZY3 xuldtCeX06c55FCEQZncfyW9YKtIayBXqjF5QDEega6iarA/a4Rdu308O0ZsLexwdj/7 89P0FjuOZ2Jo0VruVhxGbRikvPEjoIa8PK5cEoYqKxcpdMQCrr2RSIMohfwNRIgeXcSZ GiHQ== X-Gm-Message-State: AOAM5324KCCSQakhbs/l9lgSAZ3tVGHgh5xpket8qcEabO41Yn1oSxiF RSSFl0YofrjsiMh2abLzA94x4PvXU4as0w== X-Google-Smtp-Source: ABdhPJzzHnnCp+VOrBXgb74JGQGNFefO42dsEuxpYwK6unjr72D1+cSw1KvSm9XqW8pKaEwcvJNH4w== X-Received: by 2002:a17:90a:7343:: with SMTP id j3mr9665566pjs.169.1612751890352; Sun, 07 Feb 2021 18:38:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 13/70] tcg/tci: Merge extension operations Date: Sun, 7 Feb 2021 18:36:55 -0800 Message-Id: <20210208023752.270606-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This includes ext8s, ext8u, ext16s, ext16u. Signed-off-by: Richard Henderson --- tcg/tci.c | 44 ++++++++------------------------------------ 1 file changed, 8 insertions(+), 36 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 894e87e1b0..cdfd9b7af8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -624,29 +624,29 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ -#if TCG_TARGET_HAS_ext8s_i32 - case INDEX_op_ext8s_i32: +#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 + CASE_32_64(ext8s) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int8_t)t1); break; #endif -#if TCG_TARGET_HAS_ext16s_i32 - case INDEX_op_ext16s_i32: +#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 + CASE_32_64(ext16s) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int16_t)t1); break; #endif -#if TCG_TARGET_HAS_ext8u_i32 - case INDEX_op_ext8u_i32: +#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 + CASE_32_64(ext8u) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint8_t)t1); break; #endif -#if TCG_TARGET_HAS_ext16u_i32 - case INDEX_op_ext16u_i32: +#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 + CASE_32_64(ext16u) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint16_t)t1); @@ -796,34 +796,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, continue; } break; -#if TCG_TARGET_HAS_ext8u_i64 - case INDEX_op_ext8u_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint8_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext8s_i64 - case INDEX_op_ext8s_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (int8_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext16s_i64 - case INDEX_op_ext16s_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (int16_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext16u_i64 - case INDEX_op_ext16u_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint16_t)t1); - break; -#endif #if TCG_TARGET_HAS_ext32s_i64 case INDEX_op_ext32s_i64: #endif --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752187; cv=none; d=zohomail.com; s=zohoarc; b=RABR3dW319PhaWV4U5/LM1FjuigDqZ8OGuQx2G2nGcGGG79l4Zcet43Tyuvue7rb2Lu4q4EvbOcOngatZcPWZscW1jj+8HKadSLU/avB4jRrWMyQ0X3alkLw0eSAApgcQIEB8fKU5waXMim9kHTUnfUP8iJvVqF0hrOZalk/tjE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612752187; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MfW3tSMzNg4i1sVQnx6Ri1BGJD02W5/7jILfn3srnPM=; b=GAvZeecVoFQ0S3XxcPWngFPoRgKtAAI5d8LPo7Zdxh0nasrsStCX4j7yS8JnFLP/UY19JY7YNyP6h0GFekrlcut02iX2NXSorurGuABmzjB1g+3ndXIbgaOpHRc3ivz/Sx5jMKKcDLoH9lhBIC0BCCPB5A8UIx1aKM34Ky5kWnM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612752187333677.0304242193904; Sun, 7 Feb 2021 18:43:07 -0800 (PST) Received: from localhost ([::1]:38238 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wW2-0006eu-4O for importer@patchew.org; Sun, 07 Feb 2021 21:43:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57784) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wRK-0001JS-Fl for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:14 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:40745) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wRI-0005l3-K2 for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:14 -0500 Received: by mail-pj1-x1029.google.com with SMTP id z9so7926443pjl.5 for ; Sun, 07 Feb 2021 18:38:12 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MfW3tSMzNg4i1sVQnx6Ri1BGJD02W5/7jILfn3srnPM=; b=VS0waLwYeGHq6EcvrcZIgqfjf4sgCZyhNkWKtePxMAJQ4N9Iu5//tuz9HZM7xC9RcP IU80zF8rUa7pWAp6wAIZnXNfI5KenyatFcqhG5PPNwppPq56g0OSBiUqiNRhPGc0xT9J sFknPKTUYjyx62jAFYLhHK9K7O78QOZcuqw/8Gn7oUyXEQQLaHwxnvRg1muq4Zuj1kVC ayi5txQPhTYhVzdsdmDMNoTuCWu7l8wyCIB2hATuEtkLusoIYIaL1ffJwri9dBkdq+BM S0+WfTzgFneB04l440VAGs7clGtaTcm9eqBKBmtoKZTnNLCmiA6YfIasci1r4dWz5RLY aUBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MfW3tSMzNg4i1sVQnx6Ri1BGJD02W5/7jILfn3srnPM=; b=ptC64DZTEmjavzLVXbv1a2LBLPiikkc+Y8tQK46n9FfJ8lnjEQfI7JsWT9i2WkqsiY 7CdKuSTBbjvbYF4O76g8TFuPEk2ZHzOgko8IGMXwwBKyw3npf9aEiJBsDb4OezdfNgMb PL6A7A462VuFxJRFqY9zBUydS+JuljnMnSXOuWK5BwFdourW6IMSYjinbhO3ou/U60/R EOEbzU/oARMS7pmC8JCaSEPFdDhERPxjCeTsrDw4/RK0d2Ud4MwId7e/eV5Uxag3cKTD aFSDFPGq5zsAKSyH3d3TcTaXfUaNPOppTkrtbNM1RPMjcQ49nZp+s7a6QaERyAzJqa65 5VHg== X-Gm-Message-State: AOAM5329anHkKEgbwjUdcaWJ3gi+ZW4WbqUDaVK71pqw5e2Gfq5oXtMm /RpgD5osvW8x1V/subKKDInD+SY45Npw7w== X-Google-Smtp-Source: ABdhPJx3VfMqYjQL/Bu36qZFw293H/sLKB0h+fE+HACxeE3Ol06XPuHgpLxWOmNX9/wlwDHL/GeGYQ== X-Received: by 2002:a17:90a:4588:: with SMTP id v8mr14486510pjg.58.1612751891373; Sun, 07 Feb 2021 18:38:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 14/70] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64 Date: Sun, 7 Feb 2021 18:36:56 -0800 Message-Id: <20210208023752.270606-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These operations are always available under different names: INDEX_op_ext_i32_i64 and INDEX_op_extu_i32_i64, so we remove no code with the ifdef. Signed-off-by: Richard Henderson --- tcg/tci.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index cdfd9b7af8..1819652c5a 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -796,17 +796,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, continue; } break; -#if TCG_TARGET_HAS_ext32s_i64 case INDEX_op_ext32s_i64: -#endif case INDEX_op_ext_i32_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1); break; -#if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: -#endif case INDEX_op_extu_i32_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752333; cv=none; d=zohomail.com; s=zohoarc; b=dxSX8MUszTXj08VJEWKv5m9WEZYJ781NnpUH2br8rPNQh2nHEigNeP4e2GPHWiOKeDSi0TpaG3QR50J0pkHRg84GXju03QKP19aZYwy8EUu9tY/WekaghOPsxweGepebLhXjzJI2S2fCVa2jm9rOsGtmoYhsofyRtVkm+trLbH8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612752333; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KcXtBKnullZQYp/0sBEeRm33/576gXQq0HPnlvclX78=; b=JdteXYjCksrh2GWpbJMZvwvZ+f2igeznAyFu5lB2nZ7WSi8osTN4DyHlch9niL63kyU1Kilejnu9cQjxwMjzoA6K+hLMDUfGPQb0hJxDnob/Mt0EZZ+gITdCLimTZmNCVN/qetodguYcdmZQL+cy6nNWABmEGRlmv0Tm8bHsxm8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161275233304828.621420249309494; Sun, 7 Feb 2021 18:45:33 -0800 (PST) Received: from localhost ([::1]:46700 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wYN-0001ff-F3 for importer@patchew.org; Sun, 07 Feb 2021 21:45:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57812) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wRM-0001QF-Vj for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:17 -0500 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:43571) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wRK-0005lu-2x for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:16 -0500 Received: by mail-pg1-x52f.google.com with SMTP id n10so9242944pgl.10 for ; Sun, 07 Feb 2021 18:38:13 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KcXtBKnullZQYp/0sBEeRm33/576gXQq0HPnlvclX78=; b=qhwLowwvWpw7Pi31T3PQdv1IxxWtx9tynLB8wu6+JZMxuTI22fvf8i+Ap4Ol/60KDU luq6iVqhVCB+CDj/PhISFOBvdOap4Y7vvXHdbajQU8MV/VOL+bjgi8m4PcjPEaArL464 NQkK8cs6GIleY6E5X3S5o7FLN8r7NLGveaUuR+yAAAm8fO6EBelLBSqMBCBM8VHFfvDy 51SYEBawGClTj30+vgheVmWYo9Q0w9LDBhQritRJLBAOiCsbYlrKk0mgLpRI4hh4I8OB ZQNQldC6kpGijvqjs7EDICz+0HQYxqfS6R7OogNEHzf1NJ4f6RSdC3fSyEPU4CrY9Iwx MI/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KcXtBKnullZQYp/0sBEeRm33/576gXQq0HPnlvclX78=; b=oCyUbRWjFSxu0vqv482ME0tvJ9JY9Ap2K7y2IYrQh8vppS+hNrI5LTQhpq5mPcymCR AiKD5LA+cq1FwBFJeP9DvCn26KoG+bqVR2Nu7f/qMaKoZb4xL31ni5MGjh3KoAdYv/iQ 7cQKn50eqBdFEGxezVchoyFCYSV5XCnTBODTmldV8OCqdREGASRmUQvpYHFh1qIXgriG zp/ohHwvH0BpqIBBYGtO4CTnnp989CGRk+Q6KdFetURBOCwuIrimW0I0vokBmSNCMRkb wytBGqB0lAKPAaZVYzTy5PdwXRLUAW/UtNWURVZ3oz3A+/r0RfEpjbDfIl0tVYUB+JJ0 z4gw== X-Gm-Message-State: AOAM531g+zRF7wDe7BN2E3Ybb41BDlBzyA54u1W8kGJ2lBdixo2P52Rk WZhEsAk28mKD2NhGw3ayCIGgyFzRN1KlQw== X-Google-Smtp-Source: ABdhPJyknVvG31B2A6Y7BRdPA9S3RmVenyPcZY/vAYVAPq3xE7QDlz/QhN+jwzm++Mi90BZkU4Q7kg== X-Received: by 2002:a63:4082:: with SMTP id n124mr15332554pga.340.1612751892753; Sun, 07 Feb 2021 18:38:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 15/70] tcg/tci: Merge bswap operations Date: Sun, 7 Feb 2021 18:36:57 -0800 Message-Id: <20210208023752.270606-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This includes bswap16 and bswap32. Signed-off-by: Richard Henderson --- tcg/tci.c | 22 ++++------------------ 1 file changed, 4 insertions(+), 18 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 1819652c5a..c979215332 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -652,15 +652,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tci_write_reg(regs, t0, (uint16_t)t1); break; #endif -#if TCG_TARGET_HAS_bswap16_i32 - case INDEX_op_bswap16_i32: +#if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 + CASE_32_64(bswap16) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif -#if TCG_TARGET_HAS_bswap32_i32 - case INDEX_op_bswap32_i32: +#if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 + CASE_32_64(bswap32) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); @@ -808,20 +808,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1); break; -#if TCG_TARGET_HAS_bswap16_i64 - case INDEX_op_bswap16_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap16(t1)); - break; -#endif -#if TCG_TARGET_HAS_bswap32_i64 - case INDEX_op_bswap32_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap32(t1)); - break; -#endif #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 =3D *tb_ptr++; --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752792; cv=none; d=zohomail.com; s=zohoarc; b=UpPd8420NqBZgWKOUwJUfQ4P5Nx7hiodEC5pB0ESl5tLjtlDv6pxj4F9CpOsZmoHw0slylDU7D2hSYLciK6o6NZwj6luPypfwH0Po5LAsbizV2aAhBtorKwykg1BHguayOFUr9ZE9XkJ3V0u6/Ey8DXLAnH4UPpHE+mUUtZ7ToA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612752792; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=v8YBF7O/DOHSCTIsDFGzgG9s+eMvXezLyegZpBv+3f8=; b=Ms+0+yK8FY4QhCs3J4sekLk15GOfsxnximdRCNttOQjXzvoJuZUA884gjtVnZyvqR3Y2PMwRf6Lz8DGQht2CwkZREfyWIeBYyuJJYYKBhpD72Eiy0JfyTXAew348iDoql8hKe93/KkoVKdvkjir8zznyJEMqF+GrXC1bHuAxmXI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612752792436227.36380856659468; Sun, 7 Feb 2021 18:53:12 -0800 (PST) Received: from localhost ([::1]:35970 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wfm-0000lx-Se for importer@patchew.org; Sun, 07 Feb 2021 21:53:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57814) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wRN-0001RR-GW for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:17 -0500 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:38455) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wRL-0005n8-J7 for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:17 -0500 Received: by mail-pf1-x42c.google.com with SMTP id d26so7523461pfn.5 for ; Sun, 07 Feb 2021 18:38:14 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v8YBF7O/DOHSCTIsDFGzgG9s+eMvXezLyegZpBv+3f8=; b=kwSt+kSIEAVd/qpw2OwWcTB5GK85di23YNDvGoGbQnglhTOOkm9MPb1FuKoxLwD42Y /azfxI3Ol0uQk0sZNL2Y+o02mYkzfpUcGTAyemD2UUwOUhqg7t2sF8xWxAPiVcKIx2L+ 1ngD+l8UAC5nGgOyI8on7D/dLbsk3VXTlzytZjmOhA4Y8SBgo0o2ZJMherLVLcpZI9Sf c6yKAe7/EjDhhxECBmJ1xUR8lem9MdKftjF10DqVmvSp+2k8/sYgS/zRR73vcKcCLM63 zMZS5jRmCd1XkbpB7wna16jcnHUVUo/MooLXvV6YSED61iQYPhQWyDKtWcz8FWf0exTH zSow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v8YBF7O/DOHSCTIsDFGzgG9s+eMvXezLyegZpBv+3f8=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 29 +++++------------------------ 1 file changed, 5 insertions(+), 24 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index c979215332..225cb698e8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -404,7 +404,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; #endif - case INDEX_op_mov_i32: + CASE_32_64(mov) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1); @@ -666,26 +666,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tci_write_reg(regs, t0, bswap32(t1)); break; #endif -#if TCG_TARGET_HAS_not_i32 - case INDEX_op_not_i32: +#if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 + CASE_32_64(not) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif -#if TCG_TARGET_HAS_neg_i32 - case INDEX_op_neg_i32: +#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 + CASE_32_64(neg) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif #if TCG_TARGET_REG_BITS =3D=3D 64 - case INDEX_op_mov_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); - break; case INDEX_op_tci_movi_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_i64(&tb_ptr); @@ -815,20 +810,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_write_reg(regs, t0, bswap64(t1)); break; #endif -#if TCG_TARGET_HAS_not_i64 - case INDEX_op_not_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, ~t1); - break; -#endif -#if TCG_TARGET_HAS_neg_i64 - case INDEX_op_neg_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, -t1); - break; -#endif #endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ =20 /* QEMU specific operations. */ --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752839; cv=none; d=zohomail.com; s=zohoarc; b=lVQzkBhvbzc5jL7Hnrk6hh3XWxJcpGqVgUdh7f8kOtaOZ1cDgc8OQ2wd9e4uVeoKivEnypn5LsJ8gLAbbc1KIzfL1/3r/4LDlYy0dc05JGL0U8rvA0903n3T3PJUjyRnfvnIDE9j9KKEGwkLfScJPVcsYYRSTme7IGHO/82UrLQ= ARC-Message-Signature: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rgDo7IsNPQk1k4dENPTgVxVYE0qud9+qjI7vIiyJakQ=; b=F3OKCEpaBFDzMeSW/DoMXAoHBPh7743QYc4/JZtQhoNNCmc4vOXfA13QUPwpYKOYiS 6UIqqn1dXwRBA5ofbeVQOCDRXKeCDCzqYVFCR8RJcvICfcHwd94eRZFucPTehAFh3a0t XhIY8DrIIFaqVb7BSr9jAOav1pCrVndZFudYpN3KS/+/rFgcjnxlxaTviqt4FYr6+zeP admA9WPRZ3zpsTX+4krwnEcxX0gbjjQ7YCq/EmpjicoifTZDAgtRkkiXQ9UhZoG47yU2 rH2M+yIEmzw4Nq2BZJne2Xg4wTL2jWMkCAiZqamoHfrEF8WIRhgojp0+JYpZ6a76QevI m3uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rgDo7IsNPQk1k4dENPTgVxVYE0qud9+qjI7vIiyJakQ=; b=cyp35FuIjVJQmgUZlapiTV719cfYLbFoUeBget4BpfOlh6IJgmgM9MjmvzPHi4Cree 4WHbCbQ8Ej8MssKFmqNyfq19RTesUVftcglKC2MIgLrcz0lG7NEMzLtn+Q8AhoXzgVA3 PBLVXdioGV7bqZMQnzYxDv9iWxL+IiNloCJBQ5+asFrNLqqpDOU/Q6TjGpmM5qLOExVL XplOmr/lGwi9NeU1kLevw8DXReFJfSGovXvnxKeKG6lBfb8azjkolRIpBaRHwULcNxRE A5m82qyis8eyleaRu16FCFUCQdh71/oTJn1O9j4D91F7dTatj4LtWqgyNJ7OzRqrcmVe 7hmg== X-Gm-Message-State: AOAM531bWvRz/udfQMvaQAC61JI1l5c072qa1CZMOOeu80dUYvEErOCS Wucl1h1grVhA6H4hZAwIDwSNK3+6lAF4bQ== X-Google-Smtp-Source: ABdhPJxYSoES8zFbpn8xgcf3vCUwdewNDCtJs/LfWXVCuMUsLeYNXbU4Fi62lZmoFPbP+eUhM+7jAw== X-Received: by 2002:a17:902:7408:b029:e1:63d0:75e5 with SMTP id g8-20020a1709027408b02900e163d075e5mr14239472pll.20.1612751895057; Sun, 07 Feb 2021 18:38:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 17/70] tcg/tci: Rename tci_read_r to tci_read_rval Date: Sun, 7 Feb 2021 18:36:59 -0800 Message-Id: <20210208023752.270606-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In the next patches, we want to use tci_read_r to return the raw register number. So rename the existing function, which returns the register value, to tci_read_rval. Signed-off-by: Richard Henderson --- tcg/tci.c | 192 +++++++++++++++++++++++++++--------------------------- 1 file changed, 96 insertions(+), 96 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 225cb698e8..20aaaca959 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -119,7 +119,7 @@ static uint64_t tci_read_i64(const uint8_t **tb_ptr) =20 /* Read indexed register (native size) from bytecode. */ static tcg_target_ulong -tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) +tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { tcg_target_ulong value =3D tci_read_reg(regs, **tb_ptr); *tb_ptr +=3D 1; @@ -131,15 +131,15 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_= t **tb_ptr) static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - uint32_t low =3D tci_read_r(regs, tb_ptr); - return tci_uint64(tci_read_r(regs, tb_ptr), low); + uint32_t low =3D tci_read_rval(regs, tb_ptr); + return tci_uint64(tci_read_rval(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 /* Read indexed register (64 bit) from bytecode. */ static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - return tci_read_r(regs, tb_ptr); + return tci_read_rval(regs, tb_ptr); } #endif =20 @@ -147,9 +147,9 @@ static uint64_t tci_read_r64(const tcg_target_ulong *re= gs, static target_ulong tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - target_ulong taddr =3D tci_read_r(regs, tb_ptr); + target_ulong taddr =3D tci_read_rval(regs, tb_ptr); #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - taddr +=3D (uint64_t)tci_read_r(regs, tb_ptr) << 32; + taddr +=3D (uint64_t)tci_read_rval(regs, tb_ptr) << 32; #endif return taddr; } @@ -382,8 +382,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, continue; case INDEX_op_setcond_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); condition =3D *tb_ptr++; tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); break; @@ -398,15 +398,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); condition =3D *tb_ptr++; tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; #endif CASE_32_64(mov) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i32: @@ -419,51 +419,51 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 CASE_32_64(ld8u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2)); break; CASE_32_64(ld8s) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); break; CASE_32_64(ld16u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2)); break; CASE_32_64(ld16s) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(int16_t *)(t1 + t2)); break; case INDEX_op_ld_i32: CASE_64(ld32u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); break; CASE_32_64(st8) - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) =3D t0; break; CASE_32_64(st16) - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) =3D t0; break; case INDEX_op_st_i32: CASE_64(st32) - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint32_t *)(t1 + t2) =3D t0; break; @@ -472,38 +472,38 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 CASE_32_64(add) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; CASE_32_64(sub) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; CASE_32_64(mul) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; CASE_32_64(and) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 & t2); break; CASE_32_64(or) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 | t2); break; CASE_32_64(xor) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 ^ t2); break; =20 @@ -511,26 +511,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_div_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); break; case INDEX_op_divu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2); break; case INDEX_op_rem_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); break; case INDEX_op_remu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); break; =20 @@ -538,41 +538,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_shl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31)); break; case INDEX_op_shr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31)); break; case INDEX_op_sar_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31)); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, rol32(t1, t2 & 31)); break; case INDEX_op_rotr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ror32(t1, t2 & 31)); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp32 =3D (((1 << tmp8) - 1) << tmp16); @@ -580,8 +580,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i32: - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare32(t0, t1, condition)) { @@ -619,64 +619,64 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, case INDEX_op_mulu2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - t2 =3D tci_read_r(regs, &tb_ptr); - tmp64 =3D (uint32_t)tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); + tmp64 =3D (uint32_t)tci_read_rval(regs, &tb_ptr); tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 CASE_32_64(ext16s) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int16_t)t1); break; #endif #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 CASE_32_64(ext8u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 CASE_32_64(ext16u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint16_t)t1); break; #endif #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 CASE_32_64(bswap16) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 CASE_32_64(bswap32) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 CASE_32_64(not) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 CASE_32_64(neg) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif @@ -691,19 +691,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_ld32s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(int32_t *)(t1 + t2)); break; case INDEX_op_ld_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st_i64: - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint64_t *)(t1 + t2) =3D t0; break; @@ -712,26 +712,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_div_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); break; case INDEX_op_divu_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); break; case INDEX_op_rem_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); break; case INDEX_op_remu_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; =20 @@ -739,41 +739,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_shl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp64 =3D (((1ULL << tmp8) - 1) << tmp16); @@ -781,8 +781,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i64: - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { @@ -794,19 +794,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, case INDEX_op_ext32s_i64: case INDEX_op_ext_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1); break; case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1); break; #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, bswap64(t1)); break; #endif @@ -913,7 +913,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, } break; case INDEX_op_qemu_st_i32: - t0 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6L5nwfntHiBbAqZT7vmSHngxEhaJDXVbwdQCQHJ8TTo=; b=e9Q5xk4jmSZ/9Mdafdi3C561NRDVb/Jxq2EuD8W9AzzzocjX4Govg57GB9xwEp3LFh DmVU8dxLWzd/noyqAzgo6Ihw3ExkXjWovEtxDt/efB0PLqi5EQfWyJZ8pBindjwr3QKC 66qS4SWiMCWK+xltN2GS8avig5tBwex6emJR/Dhy9X2wQUY0/zbPQcZKRkYSHbg2bvwY TOJj+jVIgalYq1wFcnfbtcOIwYJ6BLgCqb4G5hHpuZN6gmybg81AUx+3XOAqMKDDti6U IIgBDpCegxz8vGvMQrMcuo583do0hc29XgrIJp7UMzwJb2AkssEa7wrkIDN7X4y/xNQ4 v+MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6L5nwfntHiBbAqZT7vmSHngxEhaJDXVbwdQCQHJ8TTo=; b=C78zkXVBD4wafOxZSz55CyPqv1mISqbDy4O10xC8FMllcC6BdLBEXT50KnwRkwvrla AdbRb9bnjfeMsY99Bz331JInh/MviFUJ1IAAJ8FFTg1StmenFJiB9kglGXhDZsWY8648 F8w6vws0SpLzz/xxJsY2qvrpjWjjG0gd8e9NLCPDjuX9ABvC/iXx9f76eEtpurgi7efw f/oUIGsrDrJtCYkz3VzHM/fnZJK2U7RnMV4Pe/nnhMBDvEJMgXWKFnQzcuoFGTCHfIRe w5lZr/Kj0aiDYIEAie4PV1IbJBfIUCEEUFmq01WpEBk6Yj8OAfHI9kbc3vRJFRBUAyar Kiug== X-Gm-Message-State: AOAM530paD3Rte5KDmdjnXcKYKS+XJMfwXLZGXGXmlKDTzKo/kWU7spK 5aUk9e3gJZkl0mv6GqUap8mfAxm+W2Z6sA== X-Google-Smtp-Source: ABdhPJzov+RCLVYD2gU5JwR4c3j46d0/cOujgmBvvV3iYfTK9JtlEsGTS+4RqI1LoePokMYw61KmfQ== X-Received: by 2002:aa7:9356:0:b029:1dd:644a:d904 with SMTP id 22-20020aa793560000b02901dd644ad904mr2893382pfn.18.1612751896377; Sun, 07 Feb 2021 18:38:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 18/70] tcg/tci: Split out tci_args_rrs Date: Sun, 7 Feb 2021 18:37:00 -0800 Message-Id: <20210208023752.270606-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Begin splitting out functions that do pure argument decode, without actually loading values from the register set. This means that decoding need not concern itself between input and output registers. We can assert that the register number is in range during decode, so that it is safe to simply dereference from regs[] later. Signed-off-by: Richard Henderson --- tcg/tci.c | 111 ++++++++++++++++++++++++++++++++---------------------- 1 file changed, 67 insertions(+), 44 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 20aaaca959..be298ae39d 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -83,6 +83,20 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low) } #endif =20 +/* Read constant byte from bytecode. */ +static uint8_t tci_read_b(const uint8_t **tb_ptr) +{ + return *(tb_ptr[0]++); +} + +/* Read register number from bytecode. */ +static TCGReg tci_read_r(const uint8_t **tb_ptr) +{ + uint8_t regno =3D tci_read_b(tb_ptr); + tci_assert(regno < TCG_TARGET_NB_REGS); + return regno; +} + /* Read constant (native size) from bytecode. */ static tcg_target_ulong tci_read_i(const uint8_t **tb_ptr) { @@ -161,6 +175,23 @@ static tcg_target_ulong tci_read_label(const uint8_t *= *tb_ptr) return label; } =20 +/* + * Load sets of arguments all at once. The naming convention is: + * tci_args_ + * where arguments is a sequence of + * + * r =3D register + * s =3D signed ldst offset + */ + +static void tci_args_rrs(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, int32_t *i2) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *i2 =3D tci_read_s32(tb_ptr); +} + static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { bool result =3D false; @@ -328,6 +359,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint8_t op_size =3D tb_ptr[1]; const uint8_t *old_code_ptr =3D tb_ptr; #endif + TCGReg r0, r1; tcg_target_ulong t0; tcg_target_ulong t1; tcg_target_ulong t2; @@ -342,6 +374,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint64_t v64; #endif TCGMemOpIdx oi; + int32_t ofs; + void *ptr; =20 /* Skip opcode and size entry. */ tb_ptr +=3D 2; @@ -418,54 +452,46 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, /* Load/store operations (32 bit). */ =20 CASE_32_64(ld8u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint8_t *)ptr; break; CASE_32_64(ld8s) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(int8_t *)ptr; break; CASE_32_64(ld16u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint16_t *)ptr; break; CASE_32_64(ld16s) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(int16_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(int16_t *)ptr; break; case INDEX_op_ld_i32: CASE_64(ld32u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint32_t *)ptr; break; CASE_32_64(st8) - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - *(uint8_t *)(t1 + t2) =3D t0; + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + *(uint8_t *)ptr =3D regs[r0]; break; CASE_32_64(st16) - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - *(uint16_t *)(t1 + t2) =3D t0; + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + *(uint16_t *)ptr =3D regs[r0]; break; case INDEX_op_st_i32: CASE_64(st32) - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - *(uint32_t *)(t1 + t2) =3D t0; + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + *(uint32_t *)ptr =3D regs[r0]; break; =20 /* Arithmetic operations (mixed 32/64 bit). */ @@ -690,22 +716,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, /* Load/store operations (64 bit). */ =20 case INDEX_op_ld32s_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(int32_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(int32_t *)ptr; break; case INDEX_op_ld_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint64_t *)ptr; break; case INDEX_op_st_i64: - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - *(uint64_t *)(t1 + t2) =3D t0; + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + *(uint64_t *)ptr =3D regs[r0]; break; =20 /* Arithmetic operations (64 bit). */ --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752910; cv=none; d=zohomail.com; s=zohoarc; b=SVEqWCS8NWZ8vAtpqGE53a/gQIEVjCr5yXV2vkeTcdS0wQZeg0Sir4bDWjH6h/7AOHiW68qGijBA8ob4NSHsebAPt/jy/BTagcqFcIC73BpFyXRw3vV2tseJ7ukLOM2W+trTMaCIcl41cXL+NzZTL/3Bj2/tBhgXdStVn+blpHg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612752910; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SycMd2jWeSgxswrzk2jq/EmJnAdi6ZgvEeestJkdRLA=; b=u+DHUausGSg2Zb5HYzAPBdVlGVT7Mw3m2Q6EO/akMZKT7SPOvSFpdGLR7mLqzNtkjS WBF85W9rOTnWly+GxiSvt0p3cl2eQZtqZLP0U7wAgbj11XmTwn2GLswlzSooUm9t6ghp bhJrpIf1V/ap0/Iqj4RLPztHY1DHGJsk8Z5M0/IBv5TC/dr2nnwp32TJoQy6gUHAHxQk 7louWn/ne8qRtmDVATluP2MmM+Yzs/aUZzOIef+dRIFuUMA5UQ4/M4CioSD3OMmW4yl1 /Xf/sc/sHcOsKqolDVhtqUCnzH4c/db8zOlyYgpHETnokhfb3ox8o0L4J5zG2aI3urp2 rBtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SycMd2jWeSgxswrzk2jq/EmJnAdi6ZgvEeestJkdRLA=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 67 +++++++++++++++++++++++++------------------------------ 1 file changed, 31 insertions(+), 36 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index be298ae39d..0bc5294e8b 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -184,6 +184,13 @@ static tcg_target_ulong tci_read_label(const uint8_t *= *tb_ptr) * s =3D signed ldst offset */ =20 +static void tci_args_rr(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); +} + static void tci_args_rrs(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, int32_t *i2) { @@ -439,9 +446,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif CASE_32_64(mov) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D regs[r1]; break; case INDEX_op_tci_movi_i32: t0 =3D *tb_ptr++; @@ -652,58 +658,50 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int8_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (int8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 CASE_32_64(ext16s) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int16_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (int16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 CASE_32_64(ext8u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint8_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (uint8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 CASE_32_64(ext16u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint16_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (uint16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 CASE_32_64(bswap16) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap16(t1)); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D bswap16(regs[r1]); break; #endif #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 CASE_32_64(bswap32) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap32(t1)); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D bswap32(regs[r1]); break; #endif #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 CASE_32_64(not) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, ~t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D ~regs[r1]; break; #endif #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 CASE_32_64(neg) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, -t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D -regs[r1]; break; #endif #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -816,21 +814,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; case INDEX_op_ext32s_i64: case INDEX_op_ext_i32_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (int32_t)regs[r1]; break; case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (uint32_t)regs[r1]; break; #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap64(t1)); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D bswap64(regs[r1]); break; #endif #endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752793; cv=none; d=zohomail.com; s=zohoarc; b=Kq5O9hZUIpC8q3ISKzzxmrqQLfPzTrFH+ybAP3A/nBGQKOStZaH9D2+CU2VqvOA07fa8cvqO3VCmgnKcjy+wiZ0yq+fZOsU3vbAO0BbcgoG5RX90M1puAKYAVIrLxqIK3h/ZRUC+s7Lz4si0YtQ8Q4fKlQ+btdjTPyRHDANr2Q0= ARC-Message-Signature: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0x6yAz9IWt//DqIhrZQq1lj8QzyPzdXLy5ti7im2Qlc=; b=ms9hPp+xNSRHOyFZBZTroCbE/SPWwzW+5nbNgmt0rSohoysYtiLF6E+IeDD+YW7nWu 1QNAJHO69KvXRJpjInebJQxGuQazZMb4zhXMRsVZOIVr522++WosWQ7wT2adfcQB1bsg uTKX0JPyQ7PClNpZJ7NvfhaWpvzFbNdy+IVWSWAgnIf8LZ2xtdsRclsoxYJ3GKbXYSnJ +Oa2vCZik/fnZHJ/jYf8PJFPxtuGwRRgUg1PFmga2lDccrvzhnYiGzW7h6iuRn1V3rhZ wmUivQzILtdz5ZVIXixtQnF0g7E/xdtXFLfAuWhSDUbMpDXKRqv9QtJ3CGCEL9C5UYZe f5rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0x6yAz9IWt//DqIhrZQq1lj8QzyPzdXLy5ti7im2Qlc=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 154 ++++++++++++++++++++---------------------------------- 1 file changed, 57 insertions(+), 97 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 0bc5294e8b..1736234bfd 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -191,6 +191,14 @@ static void tci_args_rr(const uint8_t **tb_ptr, *r1 =3D tci_read_r(tb_ptr); } =20 +static void tci_args_rrr(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); +} + static void tci_args_rrs(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, int32_t *i2) { @@ -366,7 +374,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint8_t op_size =3D tb_ptr[1]; const uint8_t *old_code_ptr =3D tb_ptr; #endif - TCGReg r0, r1; + TCGReg r0, r1, r2; tcg_target_ulong t0; tcg_target_ulong t1; tcg_target_ulong t2; @@ -503,101 +511,71 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchS= tate *env, /* Arithmetic operations (mixed 32/64 bit). */ =20 CASE_32_64(add) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 + t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] + regs[r2]; break; CASE_32_64(sub) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 - t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] - regs[r2]; break; CASE_32_64(mul) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 * t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] * regs[r2]; break; CASE_32_64(and) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] & regs[r2]; break; CASE_32_64(or) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] | regs[r2]; break; CASE_32_64(xor) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] ^ regs[r2]; break; =20 /* Arithmetic operations (32 bit). */ =20 case INDEX_op_div_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int32_t)regs[r1] / (int32_t)regs[r2]; break; case INDEX_op_divu_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint32_t)regs[r1] / (uint32_t)regs[r2]; break; case INDEX_op_rem_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int32_t)regs[r1] % (int32_t)regs[r2]; break; case INDEX_op_remu_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint32_t)regs[r1] % (uint32_t)regs[r2]; break; =20 /* Shift/rotate operations (32 bit). */ =20 case INDEX_op_shl_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint32_t)regs[r1] << (regs[r2] & 31); break; case INDEX_op_shr_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint32_t)regs[r1] >> (regs[r2] & 31); break; case INDEX_op_sar_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int32_t)regs[r1] >> (regs[r2] & 31); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, rol32(t1, t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D rol32(regs[r1], regs[r2] & 31); break; case INDEX_op_rotr_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, ror32(t1, t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D ror32(regs[r1], regs[r2] & 31); break; #endif #if TCG_TARGET_HAS_deposit_i32 @@ -732,62 +710,44 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, /* Arithmetic operations (64 bit). */ =20 case INDEX_op_div_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int64_t)regs[r1] / (int64_t)regs[r2]; break; case INDEX_op_divu_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint64_t)regs[r1] / (uint64_t)regs[r2]; break; case INDEX_op_rem_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int64_t)regs[r1] % (int64_t)regs[r2]; break; case INDEX_op_remu_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint64_t)regs[r1] % (uint64_t)regs[r2]; break; =20 /* Shift/rotate operations (64 bit). */ =20 case INDEX_op_shl_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 << (t2 & 63)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] << (regs[r2] & 63); break; case INDEX_op_shr_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 >> (t2 & 63)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] >> (regs[r2] & 63); break; case INDEX_op_sar_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int64_t)regs[r1] >> (regs[r2] & 63); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, rol64(t1, t2 & 63)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D rol64(regs[r1], regs[r2] & 63); break; case INDEX_op_rotr_i64: - t0 =3D *tb_ptr++; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 1736234bfd..86625061f1 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -207,6 +207,15 @@ static void tci_args_rrs(const uint8_t **tb_ptr, *i2 =3D tci_read_s32(tb_ptr); } =20 +static void tci_args_rrrc(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *c3 =3D tci_read_b(tb_ptr); +} + static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { bool result =3D false; @@ -430,11 +439,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tb_ptr =3D (uint8_t *)label; continue; case INDEX_op_setcond_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - condition =3D *tb_ptr++; - tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); + tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + regs[r0] =3D tci_compare32(regs[r1], regs[r2], condition); break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: @@ -446,11 +452,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, break; #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - condition =3D *tb_ptr++; - tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); + tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + regs[r0] =3D tci_compare64(regs[r1], regs[r2], condition); break; #endif CASE_32_64(mov) --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752946; cv=none; d=zohomail.com; s=zohoarc; b=VC0VNajE7HCcI08QsQLOHOTGoJG3Lx0q9D83UbRNlGwiWYowA3nzXA5KGgs0ovh9TqeV5eNyYcpZr9Xz6Q0AP1tvK3ttxLgjxyTYA87lzAdwqC2B7GbKgIMKGk2Qf4k25xjswvkfX5CF0XCWG7/+gv5MNmN+Lp47tYIwc0ab/24= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612752946; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v4sc5nm0f4c/U5WbNEJOfl++DRfDxzP3f+V/F9gDHfw=; b=PiAOY4PiU2BNuaZMc0bTeLzUS+1tGo6zQ9e3oMxctkh7egbO6OY/M8rbjpF4QIptXe G3rmKB/T/dpefo/z9989+yqTaf4GSSm8qym70PPT2CGH/x/tS4bTHDbrEw+G0RvcooEj 1wdirOzjvup9il/RCS4VFmu+Dkbf3Bo9y4x5++28rchxfzutriNK3q5bm3bxxuY7D5Ic 0adpx1rUCYQ27X4JmL8Uh18CEea6xilTf5ikYrP3NKHduPgI9NZEpF9r3qLxQcVTdVJT rKD+YxjbeShfp8JloV0Z5z9qvClXpDKvZJvXonmevIy6Fd2uVeK3alnoMb9Jhg5sS2g+ 7Q/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v4sc5nm0f4c/U5WbNEJOfl++DRfDxzP3f+V/F9gDHfw=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 86625061f1..8bc9dd27b0 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -184,6 +184,11 @@ static tcg_target_ulong tci_read_label(const uint8_t *= *tb_ptr) * s =3D signed ldst offset */ =20 +static void tci_args_l(const uint8_t **tb_ptr, void **l0) +{ + *l0 =3D (void *)tci_read_label(tb_ptr); +} + static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { @@ -434,9 +439,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif break; case INDEX_op_br: - label =3D tci_read_label(&tb_ptr); + tci_args_l(&tb_ptr, &ptr); tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr =3D (uint8_t *)label; + tb_ptr =3D ptr; continue; case INDEX_op_setcond_i32: tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612753120; cv=none; d=zohomail.com; s=zohoarc; b=AaLtEQDvb2igV9jYRZxY+NYcK4b+8uxGRD75FaUbiPbEZ29T+00wx9RrbBrg3S+8hjpann9G9r706Sz3rXdZY+3reqmzOX0NRiLfjyaT/Ng3xG5Yb3moSzdoWVJzCpMBn1a69rEeUMN5EJ0FXor1+0HsPlsNirphlTWjK80niIc= ARC-Message-Signature: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EjI7Jfr8LIthM/+Hr8pg5fY2MZ87PA6SSlhcAVNxWvA=; b=ehoIZkeAb719YXFMwoUAIjjvhbq9QnwM5Ih2E202BX3rSyf7bymjQ0lTH2FJfFKz+u zIyYxWB9voY/ASs1koqJtWUoPaJYSZMgHuBgUnyLY50j4n9DXwQJ7P8QnDWfWJ+Es3ah kz0WmDCnLVEzSW/zxTgPVQV/VcbE22tDWp2BCFuSystWQEAfeCzti7bqUU+UH30A4ev5 1I31/CHI9wmGjCHn+H7xr75XTC3WEJuw5MqKGZi2+tTrntgWlBwRfjJ1ZK9kVY2533pf x5NfvBQpD+6tpfIeVeLcWDH8WRjYvR/ei9ZIMO3yYNhLlpyIu210N3dDuecBRnA1wXCn Zirw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EjI7Jfr8LIthM/+Hr8pg5fY2MZ87PA6SSlhcAVNxWvA=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 8bc9dd27b0..692b95b5c2 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -221,6 +221,19 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, *c3 =3D tci_read_b(tb_ptr); } =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 +static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); + *r4 =3D tci_read_r(tb_ptr); + *c5 =3D tci_read_b(tb_ptr); +} +#endif + static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { bool result =3D false; @@ -400,7 +413,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 - uint64_t v64; + TCGReg r3, r4; + uint64_t v64, T1, T2; #endif TCGMemOpIdx oi; int32_t ofs; @@ -449,11 +463,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: - t0 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(regs, &tb_ptr); - v64 =3D tci_read_r64(regs, &tb_ptr); - condition =3D *tb_ptr++; - tci_write_reg(regs, t0, tci_compare64(tmp64, v64, condition)); + tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &condition); + T1 =3D tci_uint64(regs[r2], regs[r1]); + T2 =3D tci_uint64(regs[r4], regs[r3]); + regs[r0] =3D tci_compare64(T1, T2, condition); break; #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612753122; cv=none; d=zohomail.com; s=zohoarc; b=jRVnSgbUupMcZgWoZvsMRAggHKS5pviFsqdj4q05ygRqQM3enmxO8eNhc+AVd/70p9g4mARib/UOdZFu7GwNX3K7BwsoE6yPSei7e3YWe6t3vssWaEYW653GfwcMpI3km9h67tmYukWWdAt3vkCFjYm8mUk0GesS8Qq8Uu0VNJE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612753122; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 52 ++++++++++++++++++++++++++++++++-------------------- 1 file changed, 32 insertions(+), 20 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 692b95b5c2..1e2f78a9f9 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -212,6 +212,15 @@ static void tci_args_rrs(const uint8_t **tb_ptr, *i2 =3D tci_read_s32(tb_ptr); } =20 +static void tci_args_rrcl(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *c2 =3D tci_read_b(tb_ptr); + *l3 =3D (void *)tci_read_label(tb_ptr); +} + static void tci_args_rrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { @@ -222,6 +231,17 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 +static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); + *c4 =3D tci_read_b(tb_ptr); + *l5 =3D (void *)tci_read_label(tb_ptr); +} + static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) { @@ -405,7 +425,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tcg_target_ulong t0; tcg_target_ulong t1; tcg_target_ulong t2; - tcg_target_ulong label; TCGCond condition; target_ulong taddr; uint8_t tmp8; @@ -414,7 +433,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 TCGReg r3, r4; - uint64_t v64, T1, T2; + uint64_t T1, T2; #endif TCGMemOpIdx oi; int32_t ofs; @@ -611,13 +630,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; #endif case INDEX_op_brcond_i32: - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - condition =3D *tb_ptr++; - label =3D tci_read_label(&tb_ptr); - if (tci_compare32(t0, t1, condition)) { + tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); + if (tci_compare32(regs[r0], regs[r1], condition)) { tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr =3D (uint8_t *)label; + tb_ptr =3D ptr; continue; } break; @@ -637,13 +653,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tci_write_reg64(regs, t1, t0, tmp64); break; case INDEX_op_brcond2_i32: - tmp64 =3D tci_read_r64(regs, &tb_ptr); - v64 =3D tci_read_r64(regs, &tb_ptr); - condition =3D *tb_ptr++; - label =3D tci_read_label(&tb_ptr); - if (tci_compare64(tmp64, v64, condition)) { + tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr); + T1 =3D tci_uint64(regs[r1], regs[r0]); + T2 =3D tci_uint64(regs[r3], regs[r2]); + if (tci_compare64(T1, T2, condition)) { tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr =3D (uint8_t *)label; + tb_ptr =3D ptr; continue; } break; @@ -783,13 +798,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; #endif case INDEX_op_brcond_i64: - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - condition =3D *tb_ptr++; - label =3D tci_read_label(&tb_ptr); - if (tci_compare64(t0, t1, condition)) { + tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); + if (tci_compare64(regs[r0], regs[r1], condition)) { tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr =3D (uint8_t *)label; + tb_ptr =3D ptr; continue; } break; --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612753633; cv=none; d=zohomail.com; s=zohoarc; b=jI1DF7D+xnImiEq8D2s5Yt1YAfbU93yV8G9/yQpmQAHFpjnnqD6zqfNpkNbyciC1Nqi2Ml9qGnEENd5LKERHaQcZmEhv4GzdpRhr/EoPcRiglUr4V8glszi8fnjknDbrwhh6uEq0ducK/G5wVPLIp1ROCOuuY2hsD30neF9G1N0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612753633; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eSQe6U/PGZwTawoh3F37z3+OGlTxy4qNiRyYKdayrlc=; b=XhTOSQBD4PQ5TQof30METOLzzy/nwFlRZLXp0xpnwXBpjMz0TrorG8C3fnjzc4i77Fa2y/s3aqz9Ehrg6X/ZrxJ9G4QtWh0IV35nLF7c1Iz942Ya1DBMdVE8JcEXyb0GqJeH+jLq/zRYXNgFe8/fVltEwDZh1cNGjzaDL3HdTVk= ARC-Authentication-Results: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 1e2f78a9f9..5cc05fa554 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -121,16 +121,6 @@ static int32_t tci_read_s32(const uint8_t **tb_ptr) return value; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -/* Read constant (64 bit) from bytecode. */ -static uint64_t tci_read_i64(const uint8_t **tb_ptr) -{ - uint64_t value =3D *(const uint64_t *)(*tb_ptr); - *tb_ptr +=3D sizeof(value); - return value; -} -#endif - /* Read indexed register (native size) from bytecode. */ static tcg_target_ulong tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -180,6 +170,8 @@ static tcg_target_ulong tci_read_label(const uint8_t **= tb_ptr) * tci_args_ * where arguments is a sequence of * + * i =3D immediate (uint32_t) + * I =3D immediate (tcg_target_ulong) * r =3D register * s =3D signed ldst offset */ @@ -196,6 +188,22 @@ static void tci_args_rr(const uint8_t **tb_ptr, *r1 =3D tci_read_r(tb_ptr); } =20 +static void tci_args_ri(const uint8_t **tb_ptr, + TCGReg *r0, tcg_target_ulong *i1) +{ + *r0 =3D tci_read_r(tb_ptr); + *i1 =3D tci_read_i32(tb_ptr); +} + +#if TCG_TARGET_REG_BITS =3D=3D 64 +static void tci_args_rI(const uint8_t **tb_ptr, + TCGReg *r0, tcg_target_ulong *i1) +{ + *r0 =3D tci_read_r(tb_ptr); + *i1 =3D tci_read_i(tb_ptr); +} +#endif + static void tci_args_rrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2) { @@ -498,9 +506,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, regs[r0] =3D regs[r1]; break; case INDEX_op_tci_movi_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_i32(&tb_ptr); - tci_write_reg(regs, t0, t1); + tci_args_ri(&tb_ptr, &r0, &t1); + regs[r0] =3D t1; break; =20 /* Load/store operations (32 bit). */ @@ -720,9 +727,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif #if TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_tci_movi_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_i64(&tb_ptr); - tci_write_reg(regs, t0, t1); + tci_args_rI(&tb_ptr, &r0, &t1); + regs[r0] =3D t1; break; =20 /* Load/store operations (64 bit). */ --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 5cc05fa554..92b13829c3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -452,30 +452,30 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 switch (opc) { case INDEX_op_call: - t0 =3D tci_read_i(&tb_ptr); + tci_args_l(&tb_ptr, &ptr); tci_tb_ptr =3D (uintptr_t)tb_ptr; #if TCG_TARGET_REG_BITS =3D=3D 32 - tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5), - tci_read_reg(regs, TCG_REG_R6), - tci_read_reg(regs, TCG_REG_R7), - tci_read_reg(regs, TCG_REG_R8), - tci_read_reg(regs, TCG_REG_R9), - tci_read_reg(regs, TCG_REG_R10), - tci_read_reg(regs, TCG_REG_R11)); + tmp64 =3D ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0= ), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R4), + tci_read_reg(regs, TCG_REG_R5), + tci_read_reg(regs, TCG_REG_R6), + tci_read_reg(regs, TCG_REG_R7), + tci_read_reg(regs, TCG_REG_R8), + tci_read_reg(regs, TCG_REG_R9), + tci_read_reg(regs, TCG_REG_R10), + tci_read_reg(regs, TCG_REG_R11)= ); tci_write_reg(regs, TCG_REG_R0, tmp64); tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); #else - tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5)); + tmp64 =3D ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0= ), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R4), + tci_read_reg(regs, TCG_REG_R5)); tci_write_reg(regs, TCG_REG_R0, tmp64); #endif break; --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612753388; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SiXlz8iU8i8mL6XFtS7HcVMO8xC61iquHDNUAoO7sPU=; b=i5OdUspvMMPqenMeMkiA84dVMCe4fKMTMEDCFInX2YOSWrei35xVv62fj6hAE2Z+cf njBTlBa+awiy6WacZhggBnWU4DsROOrvJSKLK65MaORyCEvOoavxtADvItNxo1D5Vytz XD9k48gLuDfFhkSi1eh3PASFxMO4DV0jnzQ8hGEgIQDhsW7V/PYKoeppmjKRBhrV6RXR aUSwMGeFpp4VNHAAy0muAWuneN4uxNrLv4W6OJE6av327d1ud5BLhxMiAHHGTH85LXt/ 766gHAP+NVb+OzjnSoWN5wo1xx/5Z5JoA5dL+S89WQ5KUvVmGrOKYcZYdCtzWXiEPcfh eNtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SiXlz8iU8i8mL6XFtS7HcVMO8xC61iquHDNUAoO7sPU=; b=KW4T00zcaP5MUQcY6lQ2S6BR4YHfmwdU8veGvh0t9bimBVJOzMmX/n1m0RpMak96gJ qOBfbTrO0S53+kF1Z3INGcFQ+5n+XpIXZvhIH0+TIPrXa0gFYwIsq34td0yva2YMQAgQ bp43/aYKK32eJJ63niRizoK0xA+cUc8oBmhIZRpGfrK8SeDxqFx/R/9W0GZvxpMY+rVI 0xPYx8VLjtXBNpmdb1xBrUz7lcVNb1txvUfAvot2RNj0Z2NXW2NYUBJAKpT30IT0GRG4 cvFxT++gC7dW+w7Puq9J9K4Ie4EsNTPa2zSEDmZke+GkBf+UZRhCfC4BV3C+rlMXtwEI aKOg== X-Gm-Message-State: AOAM530lY2MFHoOXcZcSnGwNm7O7mVkd+Td+e8cSKioCM+Wx9ndAUaXJ 4oUhAJElpGYHbp6W8cH4gL8mQ/qZGFPYnw== X-Google-Smtp-Source: ABdhPJwWEInjTsVP65suz6N/fai0VB8uiS0AuVIsaS1ffZ/uUnWHnW+bNOQq/PsH8ZzWda4k3yt1xA== X-Received: by 2002:a63:5416:: with SMTP id i22mr15432214pgb.43.1612751907573; Sun, 07 Feb 2021 18:38:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 27/70] tcg/tci: Reuse tci_args_l for exit_tb Date: Sun, 7 Feb 2021 18:37:09 -0800 Message-Id: <20210208023752.270606-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Do not emit a uint64_t, but a tcg_target_ulong, aka uintptr_t. This reduces the size of the constant on 32-bit hosts. The assert for label !=3D NULL has to be removed because that is a valid value for exit_tb. Signed-off-by: Richard Henderson --- tcg/tci.c | 13 ++++--------- tcg/tci/tcg-target.c.inc | 2 +- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 92b13829c3..57b6defe09 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -160,9 +160,7 @@ tci_read_ulong(const tcg_target_ulong *regs, const uint= 8_t **tb_ptr) =20 static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) { - tcg_target_ulong label =3D tci_read_i(tb_ptr); - tci_assert(label !=3D 0); - return label; + return tci_read_i(tb_ptr); } =20 /* @@ -417,7 +415,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tcg_target_ulong regs[TCG_TARGET_NB_REGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS]; uintptr_t sp_value =3D (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); - uintptr_t ret =3D 0; =20 regs[TCG_AREG0] =3D (tcg_target_ulong)env; regs[TCG_REG_CALL_STACK] =3D sp_value; @@ -832,9 +829,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, /* QEMU specific operations. */ =20 case INDEX_op_exit_tb: - ret =3D *(uint64_t *)tb_ptr; - goto exit; - break; + tci_args_l(&tb_ptr, &ptr); + return (uintptr_t)ptr; + case INDEX_op_goto_tb: /* Jump address is aligned */ tb_ptr =3D QEMU_ALIGN_PTR_UP(tb_ptr, 4); @@ -992,6 +989,4 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, } tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); } -exit: - return ret; } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c79f9c32d8..ff8040510f 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -401,7 +401,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, =20 switch (opc) { case INDEX_op_exit_tb: - tcg_out64(s, args[0]); + tcg_out_i(s, args[0]); break; =20 case INDEX_op_goto_tb: --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612753396; cv=none; d=zohomail.com; s=zohoarc; b=EkakFzpvGFOoydb9UrzTbf8w4iywCYan1VqhlKctq4gCf5hesfNgBS0j8pcnhsz9/1br5RR53sLYepNa7VFd5LZGCfaRP4LETotMhEX6C448WMBCmn7tZfK1rvC5Hvnpf04wHojUfvRW2/1pkNEQVpQ0ePafHmivZYT146jsgKM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612753396; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1LT2MbDB8DSsnJ6nk4ZYA0KuSI+0ipd9FJnZcTxjPRQ=; b=j2BJApEyo6u8YfNMQ85M/qA1zxKQL+L5ZtRTwzprM5ijDL4Yk14jYUJIO5IBWqdYKvE3yF80iRUNvhzTXkbgoa/Mwyb+eV/mf/pYVKbPE6pceXYDu7+S/2CWmiS8ijLkMVZjDXspn2ROGVoBuHFknYrNG2zjps9hf+IzyouHHXQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612753395980817.1180887190901; Sun, 7 Feb 2021 19:03:15 -0800 (PST) Received: from localhost ([::1]:32928 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wpW-0003FI-Q4 for importer@patchew.org; Sun, 07 Feb 2021 22:03:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58086) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wRm-0001cg-QI for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:42 -0500 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:44649) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wRa-0005rw-Tg for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:42 -0500 Received: by mail-pg1-x533.google.com with SMTP id j5so452245pgb.11 for ; Sun, 07 Feb 2021 18:38:29 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1LT2MbDB8DSsnJ6nk4ZYA0KuSI+0ipd9FJnZcTxjPRQ=; b=jXWHc1qZH5MYycwjIKu/DBrEd8ebULK5J3dQR5ZkPe6JOYugGVlzVHKc2A7YCIEkMF NS9iRINg3hL6rMUL/a74F/1VEt3LuV4pegYrOY9MaOMIkyUTk2mBKBR8gTH8DFq/OgmU TXxLA9Boj8+sjh3cCxZMWlxfa+Be9xy5HdfTN+Wo1Y8JmKnq1OmIs5OTzETVyum8HYs2 TCHXdoZVjMTpoZAVgbsnpnoLHWazczA/6R5IkPvIyoxROyfxMV9KRD+q7R5g5tw9UXS4 eaXcXhBDlOuwen2vM8ltoKQDGt3f+J0W4HDQDzDezDGSnjGlurkgw3hJR+RmAIxkqSsv bJGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1LT2MbDB8DSsnJ6nk4ZYA0KuSI+0ipd9FJnZcTxjPRQ=; b=KI5NcDJQTKcnnbVRSG/RSsaWIj9eW842Cw5jzsEGrvGiQMPUfeCP31JkiTDmhe7y+H QFyN/6VSQ7YWbBut4C50UeWPLU29cZAWvlpzRoxRKUlnxtKL0VVoAkcJ/fPTnKKZSVG+ OeymgDauK3Pn06olUU8N1BBXRke/B+RqgMMYg5gbEYv4evT001M5diW1td9gL4nTt7Sf ka7r5cIIdnQnnn41Z3oDxj5bgcUKfgduXfpQzUxL3LA4Olzd5KeX4xe5oLbei2gm8LrT klfcf2wQSGE7oOwdH6JZV1tAUUO4sMlc8uzV0Tfo5YyuSesGVJpZWNnG78OyKlJ0kC3w ZblQ== X-Gm-Message-State: AOAM533MFBK9tOkYAJ6acYfb+t9Yq3dYNqyZBP8GgKrnb3MCX0ChA+nq YWGUB9koNzcJhuoSCOMXpahmgZMF+/a1Zw== X-Google-Smtp-Source: ABdhPJwjuHVuBK5dFlG8kSbDSe8ewDOoMXMQmlOkI19cOHaVENBhw02RP560MkzzQA9g0DoBZYsD9w== X-Received: by 2002:a63:551e:: with SMTP id j30mr6013449pgb.376.1612751908835; Sun, 07 Feb 2021 18:38:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 28/70] tcg/tci: Reuse tci_args_l for goto_tb Date: Sun, 7 Feb 2021 18:37:10 -0800 Message-Id: <20210208023752.270606-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert to indirect jumps, as it's less complicated. Then we just have a pointer to the tb address at which the chain is stored, from which we read. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 11 +++-------- tcg/tci.c | 8 +++----- tcg/tci/tcg-target.c.inc | 13 +++---------- 3 files changed, 9 insertions(+), 23 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 9c0021a26f..9285c930a2 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -87,7 +87,7 @@ #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 0 -#define TCG_TARGET_HAS_direct_jump 1 +#define TCG_TARGET_HAS_direct_jump 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -174,12 +174,7 @@ void tci_disas(uint8_t opc); =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 -static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jm= p_rx, - uintptr_t jmp_rw, uintptr_t ad= dr) -{ - /* patch the branch destination */ - qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4)); - /* no need to flush icache explicitly */ -} +/* not defined -- call should be eliminated at compile time */ +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 #endif /* TCG_TARGET_H */ diff --git a/tcg/tci.c b/tcg/tci.c index 57b6defe09..0301ee63a7 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -833,13 +833,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, return (uintptr_t)ptr; =20 case INDEX_op_goto_tb: - /* Jump address is aligned */ - tb_ptr =3D QEMU_ALIGN_PTR_UP(tb_ptr, 4); - t0 =3D qatomic_read((int32_t *)tb_ptr); - tb_ptr +=3D sizeof(int32_t); + tci_args_l(&tb_ptr, &ptr); tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr +=3D (int32_t)t0; + tb_ptr =3D *(void **)ptr; continue; + case INDEX_op_qemu_ld_i32: t0 =3D *tb_ptr++; taddr =3D tci_read_ulong(regs, &tb_ptr); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index ff8040510f..2c64b4f617 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -405,16 +405,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, break; =20 case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset) { - /* Direct jump method. */ - /* Align for atomic patching and thread safety */ - s->code_ptr =3D QEMU_ALIGN_PTR_UP(s->code_ptr, 4); - s->tb_jmp_insn_offset[args[0]] =3D tcg_current_code_size(s); - tcg_out32(s, 0); - } else { - /* Indirect jump method. */ - TODO(); - } + tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); + /* indirect jump method. */ + tcg_out_i(s, (uintptr_t)(s->tb_jmp_target_addr + args[0])); set_jmp_reset_offset(s, args[0]); break; =20 --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612752988; cv=none; d=zohomail.com; s=zohoarc; b=QKY4wJkTtB2ZSBvvGTSDpTtFX7gugYiqAedTQjBrwA0d65fYj0VZ2Y6ldhkYPKQjzi7utXyBK4td7TsOmiXnodD/ws4Jjw+cbPYZ62uFmJ3/8dZV1yJDmTLi9cPRcNdXUNYrBYrG4dhqv2+UOKY7RbrRRWvzBAzm3gcdk2IpKqY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612752988; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CAFEcBhH5Bm/1S+hn6Be2S25m9MyX50Fw2Tvsr0CL7s=; b=PHN1jSHb6sdKNGwYcBoF4debQFZF7dnfFcmL0Zu2qCMs19GGFW8uSCAgWIfP4p11DNeNi/RP1agrjm0EvfPmenZ0LSuqbJ5sNQd36foH1fBDfR8G1f3QYGd1BPzlseapBcAEqgi178kFLMFBIkjNIxxLl6aXhKGc4tkkbGzuqHQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612752988348986.6347624607233; Sun, 7 Feb 2021 18:56:28 -0800 (PST) Received: from localhost ([::1]:47092 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wix-0005VA-2z for importer@patchew.org; Sun, 07 Feb 2021 21:56:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58088) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wRm-0001cv-Se for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:42 -0500 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:35310) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wRb-0005s2-8Z for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:42 -0500 Received: by mail-pg1-x536.google.com with SMTP id t25so9272123pga.2 for ; Sun, 07 Feb 2021 18:38:30 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CAFEcBhH5Bm/1S+hn6Be2S25m9MyX50Fw2Tvsr0CL7s=; b=YTQPY1rmM84LAE7Mf2LydjmwlauK1HhfGkR/DHCBvgNlEH34qwByYLh8PYQwe2eHj/ 7Ic299818C+mKJAZKYQm9vTm/n7lSkviQqtSO0IEnTkBMgaHoZCZnYC24n1zA4m+s7oT aHlayLiyViqo1DvgMyFlV57MuNGdxLNLnSRgU01/w9iUtAu5xIrwlMQM1lFBwbP8h62B PaZSB9aqGCDg9BG8JpbHNiodFC0OaFBYryLLhBeacFFO5Nm3rkZLndNiLB7WJdDrkb8u +wizuCp2tcooUtYdzh2doYoz9/3moRLhMahg5DAUB4+QNc8WETNMs7e9VhLYdo8Q5iV9 TznQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CAFEcBhH5Bm/1S+hn6Be2S25m9MyX50Fw2Tvsr0CL7s=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 0301ee63a7..84d77855ee 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -258,6 +258,17 @@ static void tci_args_rrrrrc(const uint8_t **tb_ptr, TC= GReg *r0, TCGReg *r1, *r4 =3D tci_read_r(tb_ptr); *c5 =3D tci_read_b(tb_ptr); } + +static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); + *r4 =3D tci_read_r(tb_ptr); + *r5 =3D tci_read_r(tb_ptr); +} #endif =20 static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) @@ -437,7 +448,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r3, r4; + TCGReg r3, r4, r5; uint64_t T1, T2; #endif TCGMemOpIdx oi; @@ -643,18 +654,16 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: - t0 =3D *tb_ptr++; - t1 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(regs, &tb_ptr); - tmp64 +=3D tci_read_r64(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, tmp64); + tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + T1 =3D tci_uint64(regs[r3], regs[r2]); + T2 =3D tci_uint64(regs[r5], regs[r4]); + tci_write_reg64(regs, r1, r0, T1 + T2); break; case INDEX_op_sub2_i32: - t0 =3D *tb_ptr++; - t1 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(regs, &tb_ptr); - tmp64 -=3D tci_read_r64(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, tmp64); + tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + T1 =3D tci_uint64(regs[r3], regs[r2]); + T2 =3D tci_uint64(regs[r5], regs[r4]); + tci_write_reg64(regs, r1, r0, T1 - T2); break; case INDEX_op_brcond2_i32: tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr); --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612753352; cv=none; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 84d77855ee..cb24295cd9 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -237,6 +237,15 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 +static void tci_args_rrrr(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); +} + static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) { @@ -676,11 +685,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, } break; case INDEX_op_mulu2_i32: - t0 =3D *tb_ptr++; - t1 =3D *tb_ptr++; - t2 =3D tci_read_rval(regs, &tb_ptr); - tmp64 =3D (uint32_t)tci_read_rval(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); + tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wOvkZ0sAbeq0kMMHx/GBq6hm2tymswKeRwzIJ0G9jzI=; b=DgcCHug/M2uULdTogyMNGY0ZQNznIvwJcHVmw1Fs2SHZPByN8VIdjNK0dfP0M4J1Kl Z1lYqbRv973FShU8dux2pYUnKy8gvsNBn+krckSMKVQUEbxlK99d20gBV27dvWwUWQYU 495nU7rXqG+goRCZnss9pPlMXPab/QVfD7pUC7KqHGQU41lhcPLXPWa4lBK0lhOxEM7s iELrF3jfci1/w7xRLRY64AzdfqJVxx1OMuKcgPKHiXBpn1t4czuevzxsb8tjlcgwgddZ GK6pUmBck5YAq0qya/+3eu3IhBJc2fOqEslL+Md1TUMoYCiymqVQpnfxJqEC9WEHycYr U/tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wOvkZ0sAbeq0kMMHx/GBq6hm2tymswKeRwzIJ0G9jzI=; b=AxKsoevgC4fAxosqEklxM9nGdG+Vdp8JFwlMa9WbYzJ1O26D5YXRzDY8r5qpJU9wxQ ScHLQiyIn7E+r/C/nmWWxSguIHy8yc/czveoYoECVhtjuH/DmfBXop4XlTSPTYJVBBGM AXIblpUZx0eDId1xgYcxtCTKl15YtKQAa4nSC11NYTQ4wV1rDGVz6zaqxjTml6zlaWBr gKps3tnDEWU4Q8kI7nCHNf5y+DDsL6kNxWGVWGx8Ys7Jy3SSr1pH7FPTbVz/ZnxCEJ1T QDoPHpEVK/wbkomTHuwcJKoqkLAzSeIjDjWSOjR7AN/Kz1F3DOnqa59SRUAtmxCrgGbE r6TQ== X-Gm-Message-State: AOAM5320MS8Eacxap1nIYk6iWlejiNH6+OPNZXI/c2pYXzbu4/AL9Pbi v208W1sPH4UYQsfSB2IFcM/IQEb/cJBg0A== X-Google-Smtp-Source: ABdhPJwLJvMgLrsxc/UL0di9ZvMODpTIAXZuTk3KE5Loe14m7WvTRmMqlwq8HOZ+PWk08Mn36Wa7gw== X-Received: by 2002:a63:fc48:: with SMTP id r8mr14659281pgk.300.1612751912535; Sun, 07 Feb 2021 18:38:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 31/70] tcg/tci: Clean up deposit operations Date: Sun, 7 Feb 2021 18:37:13 -0800 Message-Id: <20210208023752.270606-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use the correct set of asserts during code generation. We do not require the first input to overlap the output; the existing interpreter already supported that. Split out tci_args_rrrbb in the translator. Use the deposit32/64 functions rather than inline expansion. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-con-set.h | 1 - tcg/tci.c | 33 ++++++++++++++++----------------- tcg/tci/tcg-target.c.inc | 24 ++++++++++++++---------- 3 files changed, 30 insertions(+), 28 deletions(-) diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h index f51b7bcb13..316730f32c 100644 --- a/tcg/tci/tcg-target-con-set.h +++ b/tcg/tci/tcg-target-con-set.h @@ -13,7 +13,6 @@ C_O0_I2(r, r) C_O0_I3(r, r, r) C_O0_I4(r, r, r, r) C_O1_I1(r, r) -C_O1_I2(r, 0, r) C_O1_I2(r, r, r) C_O1_I4(r, r, r, r, r) C_O2_I1(r, r, r) diff --git a/tcg/tci.c b/tcg/tci.c index cb24295cd9..e10ccfc344 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -168,6 +168,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **= tb_ptr) * tci_args_ * where arguments is a sequence of * + * b =3D immediate (bit position) * i =3D immediate (uint32_t) * I =3D immediate (tcg_target_ulong) * r =3D register @@ -236,6 +237,16 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, *c3 =3D tci_read_b(tb_ptr); } =20 +static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, uint8_t *i3, uint8_t *i4) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *i3 =3D tci_read_b(tb_ptr); + *i4 =3D tci_read_b(tb_ptr); +} + #if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) @@ -449,11 +460,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, TCGReg r0, r1, r2; tcg_target_ulong t0; tcg_target_ulong t1; - tcg_target_ulong t2; TCGCond condition; target_ulong taddr; - uint8_t tmp8; - uint16_t tmp16; + uint8_t pos, len; uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 @@ -644,13 +653,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tmp16 =3D *tb_ptr++; - tmp8 =3D *tb_ptr++; - tmp32 =3D (((1 << tmp8) - 1) << tmp16); - tci_write_reg(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32= )); + tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + regs[r0] =3D deposit32(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i32: @@ -806,13 +810,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tmp16 =3D *tb_ptr++; - tmp8 =3D *tb_ptr++; - tmp64 =3D (((1ULL << tmp8) - 1) << tmp16); - tci_write_reg(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64= )); + tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + regs[r0] =3D deposit64(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i64: diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 2c64b4f617..640407b4a8 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -126,11 +126,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpco= de op) case INDEX_op_rotr_i64: case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - return C_O1_I2(r, r, r); - case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return C_O1_I2(r, 0, r); + return C_O1_I2(r, r, r); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: @@ -480,13 +478,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, break; =20 CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_debug_assert(args[3] <=3D UINT8_MAX); - tcg_out8(s, args[3]); - tcg_debug_assert(args[4] <=3D UINT8_MAX); - tcg_out8(s, args[4]); + { + TCGArg pos =3D args[3], len =3D args[4]; + TCGArg max =3D opc =3D=3D INDEX_op_deposit_i32 ? 32 : 64; + + tcg_debug_assert(pos < max); + tcg_debug_assert(pos + len <=3D max); + + tcg_out_r(s, args[0]); + tcg_out_r(s, args[1]); + tcg_out_r(s, args[2]); + tcg_out8(s, pos); + tcg_out8(s, len); + } break; =20 CASE_32_64(brcond) --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612753169; cv=none; d=zohomail.com; s=zohoarc; b=ajt7PtvvccQvrQdq8JqCicm3cVIhzcPOguKwOorjAeOq8lqngzm82iEkByp3ddBRuucUEWO48hyBNmhlkVUT4+grilfIuZtU7KL6qdOzDvnqoqctYwNJqL+yuLS7bAeHpkboLHt4zq8AWIQ3i13MfqyrLNM+A9Zo34fGMbamp68= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612753169; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fkXespGLacfat/Oc2ATzIf/ZqfIgEJ0vqqLFj00td/k=; b=AoLmqwzp1T3kwKOYw5l4wh+aFMw39mC/Mq7nS01rost9/hHx5bvokYpXtx26Q091cV2YPFqOsURE79VQKkc8dFU3mJH/L7tDwNI+lMVoP/tSnqrVBWB5+pHIgc/fiC8Yvcrbt047Zosm691DHXRue3/GJ8h6eiM6JBnAJURQiwg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612753169568574.0419215735326; Sun, 7 Feb 2021 18:59:29 -0800 (PST) Received: from localhost ([::1]:55386 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wlr-0000cs-E0 for importer@patchew.org; Sun, 07 Feb 2021 21:59:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58100) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wRn-0001eB-Co for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:43 -0500 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:44120) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wRf-0005sT-GD for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:43 -0500 Received: by mail-pf1-x432.google.com with SMTP id t29so8739554pfg.11 for ; Sun, 07 Feb 2021 18:38:34 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fkXespGLacfat/Oc2ATzIf/ZqfIgEJ0vqqLFj00td/k=; b=jnyhXBjL7SsXxqCxxTeOCUnsXsj16nxluFPCHJSXeUgsY/WJtGr4ApvW3fvlPEU+cq 2S9eW1LoqCjxZ4XoOmWO1K3K5wacSCo4MgAC8ASbakEliKwag5oZfP952Hgmyu9ya0/i /wjdlvICzUoqVd3AIO+lKNYnPAZMG84e9xlzL2jwUdeB6dCD1ta1eAps7vZfuOohKokX VAhCOY+OpX+AJap8EoCxxwnCJetvN/RH33wPDorodyPL5Grw9qdzd8v2HeegZ0ANurmD F54wrNg6QfWwpJxBdCp+O8jSogB+iU8tBuqOVJlJhkN17Zs4mC9mr2vbXBhYSqwYMfii rQPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fkXespGLacfat/Oc2ATzIf/ZqfIgEJ0vqqLFj00td/k=; b=Rwaq4A2OoIpAjtSs3wKb5PHZB8wd52Btx0M3tT7rEXFMB7EswWgrReAAxTLSytfQ/8 /d1TeqD9kMnGxpU/26hAZ5aRCAzZYpt3wFXyffJl5loiHr0fEbZl+w5+HwqQb6bsrMlJ udUsPJdLobOXZNFiv1Bclex5mbAvVpmShOpHlL5d0fH0IE/Kdk7M6tyg4QQemOXKwZ+/ OGDOwL3dPA8F/ddt6U+eaPbLmhG/+dzLtvjIUvJKT/4B6wlgmnEwmkoxZ+ljZw28s3Ul q0VL0NJPQvPA9X+KUFqO6a/eMhYn7j2x99+oR1my2XDoCk9d9NprRyFqH6Nl2QQ1Mh5O i2tA== X-Gm-Message-State: AOAM531DiGVTmgaKEb+YueAQrSjFq6Ml9ZuUCGG8AlGEnHZ9pgWrlITP amXrKqDeObFku1uolR/ANPun+ms3ScuofQ== X-Google-Smtp-Source: ABdhPJzkhFPa1foaPe5kX+LuiNp6DlBPo5w2LTXxB9Qss6mW6qoS5yL1gEQHPDUMbY8NNmBJ1usSbg== X-Received: by 2002:a62:76d3:0:b029:1d9:8e88:9276 with SMTP id r202-20020a6276d30000b02901d98e889276mr10334499pfc.71.1612751913704; Sun, 07 Feb 2021 18:38:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 32/70] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits Date: Sun, 7 Feb 2021 18:37:14 -0800 Message-Id: <20210208023752.270606-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We are currently using the "natural" size routine, which uses 64-bits on a 64-bit host. The TCGMemOpIdx operand has 11 bits, so we can safely reduce to 32-bits. Signed-off-by: Richard Henderson --- tcg/tci.c | 8 ++++---- tcg/tci/tcg-target.c.inc | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index e10ccfc344..ddc138359b 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -855,7 +855,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_qemu_ld_i32: t0 =3D *tb_ptr++; taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i(&tb_ptr); + oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp32 =3D qemu_ld_ub; @@ -892,7 +892,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t1 =3D *tb_ptr++; } taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i(&tb_ptr); + oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp64 =3D qemu_ld_ub; @@ -941,7 +941,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_qemu_st_i32: t0 =3D tci_read_rval(regs, &tb_ptr); taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i(&tb_ptr); + oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: qemu_st_b(t0); @@ -965,7 +965,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_qemu_st_i64: tmp64 =3D tci_read_r64(regs, &tb_ptr); taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i(&tb_ptr); + oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: qemu_st_b(tmp64); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 640407b4a8..6c187a25cc 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -550,7 +550,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { tcg_out_r(s, *args++); } - tcg_out_i(s, *args++); + tcg_out32(s, *args++); break; =20 case INDEX_op_qemu_ld_i64: @@ -563,7 +563,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { tcg_out_r(s, *args++); } - tcg_out_i(s, *args++); + tcg_out32(s, *args++); break; =20 case INDEX_op_mb: --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612753643; cv=none; d=zohomail.com; s=zohoarc; b=FgMkkXaz9Eeek9eCpOrcAPJQjpUpD6lg0D0uRBb6hynqILN9mvTCoiyRdT7a6+jUaQsGWSd2FQHszP/ixXfX2RbtAk1236JLCWnF4IfmUfJHxCVHRFXhyeZf7xfPYQPPAwrUaOwpf6KzJdgjWU9r2b5NL4pKZR9MVG1bRO+jKGA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612753643; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Q08wWJmkpMRbD1uCLvdIthjIJ7wpxGIx6PIRtX9sdqE=; b=YPKk2FyZ8fWnyaE4pAXIaV3uu6EI6USCAI6p8aNZ3P9nng4Ynlhrq77foWnTBkSlw9u6P0/tBpb1IteTrBAKtGf6KR1YAIo2+S3hxoeWvP63DStfT5Llb6EzUL/Y+nYFn1eGBzX/mqeXAbvdFn5DqNjRW0jf4Dt/i8qcGj8nXYQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612753643781864.9064769238205; Sun, 7 Feb 2021 19:07:23 -0800 (PST) Received: from localhost ([::1]:41302 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wtW-0007R1-Jg for importer@patchew.org; Sun, 07 Feb 2021 22:07:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58128) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wRo-0001hn-DJ for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:44 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:56139) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wRg-0005sX-C5 for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:44 -0500 Received: by mail-pj1-x1033.google.com with SMTP id s24so7393489pjp.5 for ; Sun, 07 Feb 2021 18:38:35 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 147 ++++++++++++++++++++++++++++++------------------------ 1 file changed, 81 insertions(+), 66 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index ddc138359b..a1846825ea 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -66,22 +66,18 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg= _target_ulong value) regs[index] =3D value; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, uint32_t low_index, uint64_t value) { tci_write_reg(regs, low_index, value); tci_write_reg(regs, high_index, value >> 32); } -#endif =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 /* Create a 64 bit value from two 32 bit values. */ static uint64_t tci_uint64(uint32_t high, uint32_t low) { return ((uint64_t)high << 32) + low; } -#endif =20 /* Read constant byte from bytecode. */ static uint8_t tci_read_b(const uint8_t **tb_ptr) @@ -121,43 +117,6 @@ static int32_t tci_read_s32(const uint8_t **tb_ptr) return value; } =20 -/* Read indexed register (native size) from bytecode. */ -static tcg_target_ulong -tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr) -{ - tcg_target_ulong value =3D tci_read_reg(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} - -#if TCG_TARGET_REG_BITS =3D=3D 32 -/* Read two indexed registers (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_r64(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - uint32_t low =3D tci_read_rval(regs, tb_ptr); - return tci_uint64(tci_read_rval(regs, tb_ptr), low); -} -#elif TCG_TARGET_REG_BITS =3D=3D 64 -/* Read indexed register (64 bit) from bytecode. */ -static uint64_t tci_read_r64(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - return tci_read_rval(regs, tb_ptr); -} -#endif - -/* Read indexed register(s) with target address from bytecode. */ -static target_ulong -tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr) -{ - target_ulong taddr =3D tci_read_rval(regs, tb_ptr); -#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - taddr +=3D (uint64_t)tci_read_rval(regs, tb_ptr) << 32; -#endif - return taddr; -} - static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) { return tci_read_i(tb_ptr); @@ -171,6 +130,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **= tb_ptr) * b =3D immediate (bit position) * i =3D immediate (uint32_t) * I =3D immediate (tcg_target_ulong) + * m =3D immediate (TCGMemOpIdx) * r =3D register * s =3D signed ldst offset */ @@ -203,6 +163,14 @@ static void tci_args_rI(const uint8_t **tb_ptr, } #endif =20 +static void tci_args_rrm(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *m2 =3D tci_read_i32(tb_ptr); +} + static void tci_args_rrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2) { @@ -237,6 +205,15 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, *c3 =3D tci_read_b(tb_ptr); } =20 +static void tci_args_rrrm(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx = *m3) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *m3 =3D tci_read_i32(tb_ptr); +} + static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, uint8_t *i3, uint8_t *i4) { @@ -247,6 +224,16 @@ static void tci_args_rrrbb(const uint8_t **tb_ptr, TCG= Reg *r0, TCGReg *r1, *i4 =3D tci_read_b(tb_ptr); } =20 +static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); + *m4 =3D tci_read_i32(tb_ptr); +} + #if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) @@ -457,8 +444,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint8_t op_size =3D tb_ptr[1]; const uint8_t *old_code_ptr =3D tb_ptr; #endif - TCGReg r0, r1, r2; - tcg_target_ulong t0; + TCGReg r0, r1, r2, r3; tcg_target_ulong t1; TCGCond condition; target_ulong taddr; @@ -466,7 +452,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r3, r4, r5; + TCGReg r4, r5; uint64_t T1, T2; #endif TCGMemOpIdx oi; @@ -853,9 +839,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, continue; =20 case INDEX_op_qemu_ld_i32: - t0 =3D *tb_ptr++; - taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i32(&tb_ptr); + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr =3D regs[r1]; + } else { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr =3D tci_uint64(regs[r2], regs[r1]); + } switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp32 =3D qemu_ld_ub; @@ -884,15 +874,20 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, default: g_assert_not_reached(); } - tci_write_reg(regs, t0, tmp32); + regs[r0] =3D tmp32; break; + case INDEX_op_qemu_ld_i64: - t0 =3D *tb_ptr++; - if (TCG_TARGET_REG_BITS =3D=3D 32) { - t1 =3D *tb_ptr++; + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr =3D regs[r1]; + } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr =3D regs[r2]; + } else { + tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + taddr =3D tci_uint64(regs[r3], regs[r2]); } - taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp64 =3D qemu_ld_ub; @@ -933,39 +928,58 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, default: g_assert_not_reached(); } - tci_write_reg(regs, t0, tmp64); if (TCG_TARGET_REG_BITS =3D=3D 32) { - tci_write_reg(regs, t1, tmp64 >> 32); + tci_write_reg64(regs, r1, r0, tmp64); + } else { + regs[r0] =3D tmp64; } break; + case INDEX_op_qemu_st_i32: - t0 =3D tci_read_rval(regs, &tb_ptr); - taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i32(&tb_ptr); + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr =3D regs[r1]; + } else { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr =3D tci_uint64(regs[r2], regs[r1]); + } + tmp32 =3D regs[r0]; switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: - qemu_st_b(t0); + qemu_st_b(tmp32); break; case MO_LEUW: - qemu_st_lew(t0); + qemu_st_lew(tmp32); break; case MO_LEUL: - qemu_st_lel(t0); + qemu_st_lel(tmp32); break; case MO_BEUW: - qemu_st_bew(t0); + qemu_st_bew(tmp32); break; case MO_BEUL: - qemu_st_bel(t0); + qemu_st_bel(tmp32); break; default: g_assert_not_reached(); } break; + case INDEX_op_qemu_st_i64: - tmp64 =3D tci_read_r64(regs, &tb_ptr); - taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i32(&tb_ptr); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr =3D regs[r1]; + tmp64 =3D regs[r0]; + } else { + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr =3D regs[r2]; + } else { + tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + taddr =3D tci_uint64(regs[r3], regs[r2]); + } + tmp64 =3D tci_uint64(regs[r1], regs[r0]); + } switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: qemu_st_b(tmp64); @@ -992,6 +1006,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, g_assert_not_reached(); } break; + case INDEX_op_mb: /* Ensure ordering for all kinds */ smp_mb(); --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hRHyPEsiO/sbh2eomZAl+YTq7kTrdOg7LphtzyHDt9Q=; b=X7PiBnB8GJWeHdO6UjB8VDz2hxdjAKcqnbMeBvQuOVwueHwrfnFTIshM7GQ3EI+7Wx ZjayPtvteTpLJJKVkZiukCHpv7tCwtTF2AImWPTpRjw5e65dl/ujji58NWyoG+8Wy4gn Zf6waWijlZlr/QzVMV7SNDda3mOlW1+L36FdZTSAx6R3X4FO6Liru+Z8CYHvTFDwI+2t sc4yRVZhEV/l/wQxYni9TrcrOagYwh4KIb1rCd3My4XJBVhvDS/Eha+npDZH/tWHT5nP V6M9LpoakZoRmzQ+f49jBJVdqAYelirFn18rOs8101CeoanOaSpU/OCteWTy9yhuqCdl EkUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hRHyPEsiO/sbh2eomZAl+YTq7kTrdOg7LphtzyHDt9Q=; b=tMTNodXnIZyIsGF/wtfG6TXLfEbw61UWLZYgiPpV9ndjvu1PE7RzAt3zlJf/KUonGy 9TogXC9LFw1yBCQ8n6ZpvzJHPji8mqir3V5GYMwbpoXBBEddss59g3X/KHUFfnUbNRW3 McM+uK2DnHYXpzb1IrKLGeoEzNWfwRlJ+YbfuZc06TN16eOlRykwXU0RfJn4aqYRYee8 G150BUum9UhAn3OaYxN8zHXxPTTpP3q83I/t+jlN5dw+nTFad66T50ad84dKo1UoWl/1 x+2EkbK1k9qYSC2UhawEWnsDDRo4q1EQdvCkDVsTt1V5dmG7y3uOKDhycf6kFC28NRpX KpeQ== X-Gm-Message-State: AOAM53298lBOzmGL3ixEmBeicNlfqtwCfxaFNR6Ogxy5dMTHHaOogPSm GHiZXg61do+5zcJ315rX0RsXoH4IMndWXA== X-Google-Smtp-Source: ABdhPJzDiMZIcBmaH5MCQ9lHYt9QmQ4EizX14DaUZKz8m9lMsBTdDxw8NLpem1nyWKRMdbU33z8xqw== X-Received: by 2002:a17:90a:ad81:: with SMTP id s1mr14655918pjq.9.1612751916230; Sun, 07 Feb 2021 18:38:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 34/70] tcg/tci: Hoist op_size checking into tci_args_* Date: Sun, 7 Feb 2021 18:37:16 -0800 Message-Id: <20210208023752.270606-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This performs the size check while reading the arguments, which means that we don't have to arrange for it to be done after the operation. Which tidies all of the branches. Signed-off-by: Richard Henderson --- tcg/tci.c | 87 ++++++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 73 insertions(+), 14 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index a1846825ea..3dc89ed829 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -24,7 +24,7 @@ #if defined(CONFIG_DEBUG_TCG) # define tci_assert(cond) assert(cond) #else -# define tci_assert(cond) ((void)0) +# define tci_assert(cond) ((void)(cond)) #endif =20 #include "qemu-common.h" @@ -135,146 +135,217 @@ static tcg_target_ulong tci_read_label(const uint8_= t **tb_ptr) * s =3D signed ldst offset */ =20 +static void check_size(const uint8_t *start, const uint8_t **tb_ptr) +{ + const uint8_t *old_code_ptr =3D start - 2; + uint8_t op_size =3D old_code_ptr[1]; + tci_assert(*tb_ptr =3D=3D old_code_ptr + op_size); +} + static void tci_args_l(const uint8_t **tb_ptr, void **l0) { + const uint8_t *start =3D *tb_ptr; + *l0 =3D (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_ri(const uint8_t **tb_ptr, TCGReg *r0, tcg_target_ulong *i1) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *i1 =3D tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 static void tci_args_rI(const uint8_t **tb_ptr, TCGReg *r0, tcg_target_ulong *i1) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *i1 =3D tci_read_i(tb_ptr); + + check_size(start, tb_ptr); } #endif =20 static void tci_args_rrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *m2 =3D tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrs(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, int32_t *i2) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *i2 =3D tci_read_s32(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *c2 =3D tci_read_b(tb_ptr); *l3 =3D (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *c3 =3D tci_read_b(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx = *m3) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *m3 =3D tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, uint8_t *i3, uint8_t *i4) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *i3 =3D tci_read_b(tb_ptr); *i4 =3D tci_read_b(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); *m4 =3D tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); *c4 =3D tci_read_b(tb_ptr); *l5 =3D (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); *r4 =3D tci_read_r(tb_ptr); *c5 =3D tci_read_b(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); *r4 =3D tci_read_r(tb_ptr); *r5 =3D tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } #endif =20 @@ -440,10 +511,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, =20 for (;;) { TCGOpcode opc =3D tb_ptr[0]; -#if defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG) - uint8_t op_size =3D tb_ptr[1]; - const uint8_t *old_code_ptr =3D tb_ptr; -#endif TCGReg r0, r1, r2, r3; tcg_target_ulong t1; TCGCond condition; @@ -493,7 +560,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; case INDEX_op_br: tci_args_l(&tb_ptr, &ptr); - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D ptr; continue; case INDEX_op_setcond_i32: @@ -646,9 +712,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_brcond_i32: tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); if (tci_compare32(regs[r0], regs[r1], condition)) { - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D ptr; - continue; } break; #if TCG_TARGET_REG_BITS =3D=3D 32 @@ -669,7 +733,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, T1 =3D tci_uint64(regs[r1], regs[r0]); T2 =3D tci_uint64(regs[r3], regs[r2]); if (tci_compare64(T1, T2, condition)) { - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D ptr; continue; } @@ -803,9 +866,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_brcond_i64: tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); if (tci_compare64(regs[r0], regs[r1], condition)) { - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D ptr; - continue; } break; case INDEX_op_ext32s_i64: @@ -834,9 +895,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, =20 case INDEX_op_goto_tb: tci_args_l(&tb_ptr, &ptr); - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D *(void **)ptr; - continue; + break; =20 case INDEX_op_qemu_ld_i32: if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { @@ -1014,6 +1074,5 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, default: g_assert_not_reached(); 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7AU7AuzkprD1DzoX758oP/Mpq/Dm/wXzaoKexxvkWBk=; b=uMn0beYeaB+5lQdHNlFqUIk37mVB0MKh01C34RfNp8vdNo8pAFzbd6zLDL2Tj5sM/Q YSLa4iWE1pIYtYn0I8XmjP6Av1o/smEU6LyfdvOW+Xm0kTc0k+6Pujp4euif9TCNeIC8 QLdpOIV9b3+IrVKFGIB6GdUnTqQvqHU7tMtDLh1sq0TFM6aJDXfIdbLf9QJV8GR30vGM Bz3hN8pdNSaWbRrHD8beMOfwViz88xX90ldtJR6gkBEPI0DnxrASsYl4TullTxkTwV94 l+hAy5o2rv1Ii9BAsATVeRJPg8e2r8SZ/w7xZ22DxTo2AxxV7omg0ziIT89B4o0vWjNH 09jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7AU7AuzkprD1DzoX758oP/Mpq/Dm/wXzaoKexxvkWBk=; b=FOWMXhOsOJl408/g5TUFLDpC+xMBl9RseWYNcW4QtlLb8atyOwuJnumbgdW9j1vRAY cLi1IPSxez+XY7/D1DvjidnuwnHtTsmonqqaf+CxBeyEDLrXiU3esY6kG0pWqo40Rrr/ wWQKYvAxgrUyt3ChzAEiybvh7AvAJvbfWRDTkZ7qg3/serLEQ7Y88ATLKTQKC36LADmT Au3IYEuLAVDM2dWD9ZQXwvIXwA+4E3gf7DKw+xDKYO9M17DhumrikhZ70/wRseov+5u6 Nbm5apZ0l1Jtr+LVlCca1C6N6Eri/sDVV1Jna0RRfgjuUiq1yzSN1JcEP3eFbnasF6td kHig== X-Gm-Message-State: AOAM532JHSTH7Y8Nn4lVJiJq2Uu9FiMvfQkRPvtUiPkYChkAK5/96IsN p/Z6pfjE0CtSWywYYBodmAFb4MSdmWrbmQ== X-Google-Smtp-Source: ABdhPJx4LEejdjmYERTaZsE/OqMsCd//+vm2+BkLbvcHqidAPVGBWUzzIX7f09/+iTiprodE93HxCw== X-Received: by 2002:a63:884a:: with SMTP id l71mr14735259pgd.75.1612751917403; Sun, 07 Feb 2021 18:38:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 35/70] tcg/tci: Remove tci_disas Date: Sun, 7 Feb 2021 18:37:17 -0800 Message-Id: <20210208023752.270606-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This function is unused. It's not even the disassembler, which is print_insn_tci, located in disas/tci.c. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 2 -- tcg/tci/tcg-target.c.inc | 10 ---------- 2 files changed, 12 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 9285c930a2..52af6d8bc5 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -163,8 +163,6 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_STACK_ALIGN 16 =20 -void tci_disas(uint8_t opc); - #define HAVE_TCG_QEMU_TB_EXEC =20 /* We could notice __i386__ or __s390x__ and reduce the barriers depending diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 6c187a25cc..7fb3b04eaf 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -253,16 +253,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, return true; } =20 -#if defined(CONFIG_DEBUG_TCG_INTERPRETER) -/* Show current bytecode. Used by tcg interpreter. */ -void tci_disas(uint8_t opc) -{ - const TCGOpDef *def =3D &tcg_op_defs[opc]; - fprintf(stderr, "TCG %s %u, %u, %u\n", - def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs); -} -#endif - /* Write value (native size). */ static void tcg_out_i(TCGContext *s, tcg_target_ulong v) { --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612753870; cv=none; d=zohomail.com; s=zohoarc; b=huHz6GI4UqEf5hJmS0BX/qjo75r3nYgSMyL5W4Xg0TJymHUcW5Dbu1ahqXS+OnO8yAaJFthVHAMx8pFNy/1NzTxVayKGFhgXk/RBLtjB5K2lmWg6cQ1Yu9qv6XPUc5+ukCelRIk8N3U5x9ibzPjV0NqJ9pfdofLvlzGriUNT/2U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612753870; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iToOwgtlkbg5FQ3YOPz2xSqBMcKCFQNo9DwZ3Jeszk0=; b=StqfOPzmt0BDTumNWKyp6kw9nkuRDScvOOp1OKndwTV5PlPQTn7lWUHEdJ9h/pTWn9CaCdIjOT5+gDNAXm2eqIWGbdGay1dL7miCbjCb2DLm97uVn1h+jebm3nF/pPC0a064rHu50zTIBFxL32L+0oMOAvNeD4Hwayi21WPrsZI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612753870826926.0578259996836; Sun, 7 Feb 2021 19:11:10 -0800 (PST) Received: from localhost ([::1]:49848 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wxB-0002e5-GG for importer@patchew.org; Sun, 07 Feb 2021 22:11:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58154) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wRp-0001kr-GZ for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:45 -0500 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:39822) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wRk-0005tn-8D for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:45 -0500 Received: by mail-pg1-x531.google.com with SMTP id o63so9260703pgo.6 for ; Sun, 07 Feb 2021 18:38:39 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iToOwgtlkbg5FQ3YOPz2xSqBMcKCFQNo9DwZ3Jeszk0=; b=Zl8rtTksHCDcc0RL3NHYJNzg7kvPqPytRpojdK14eYhoP4URTPzOJy1aYvxQWy4Uvq bazXzgxcr6XYKJFE49yAh6siswaGzRHrK1NojriLDrwPsLSqxwu/HjQBr7RA31Ip5+Fw d14mxtand1Mx+HrHVhpdCWaAQcbevxl9jPGUuWM8Yvh2NJAtH7bAw2pcAydKy+foLBhZ vyaRIbha/wVpfC7uUeLbh+IIuLT5CasTJjsywTYRmrcGlKjoHmWDWujygLaSBVbSKquI vf4zA0ux1YYJnffBJuvvk8ur0VjFOcQsXoSdMoqB5zCprXEhGiOmBKBbNrlxnEU3zcgq i7/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iToOwgtlkbg5FQ3YOPz2xSqBMcKCFQNo9DwZ3Jeszk0=; b=AG0w21sEc86AwK0mTGcB0J4nta46EdcOmLKxptdyQ4jEod1Bl6q0ovzBpW5Llz0np/ glyAu7NK2BX4rcAhDXFaBoJWqHm5fShnEc4qmqTvuHfX0whah24QYcmP12eREKoz1Rxu 2E8uhvhCpw7930kXoagZNI3yQx59pqAa4ldAY0nEgFC7pBcaLP7wzyQVuA6UWgNwKpI4 3dpz010jaTg2+pRzmKZcRisH+GUMMdjiYmCbN4fcVjoPdLX0wjvnhwu047RNXViOCMLE gwwEYMyZeCUp8HXViILzBNxBI6c+QlUP7qA4HjEo5q4FZ+Ocx7W9cojY7xyNmUp83fGq 9S3g== X-Gm-Message-State: AOAM533PbgmN7v4hbdsxr65LyGB2euI04HJFWC8pB6eo6emIoLIOeOp3 plzYlKI5JZrt7SxDm+/9INQE7xAdPimslg== X-Google-Smtp-Source: ABdhPJzk7HVpUEpD4rhamaB45Cs1icFVrnR+0Bco49vYe8u33ddMnUmCYQcntdkP5UBce4YGTt9jgw== X-Received: by 2002:a65:5c48:: with SMTP id v8mr15295938pgr.400.1612751918434; Sun, 07 Feb 2021 18:38:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 36/70] tcg/tci: Implement the disassembler properly Date: Sun, 7 Feb 2021 18:37:18 -0800 Message-Id: <20210208023752.270606-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Actually print arguments as opposed to simply the opcodes and, uselessly, the argument counts. Reuse all of the helpers developed as part of the interpreter. Signed-off-by: Richard Henderson --- meson.build | 2 +- include/tcg/tcg-opc.h | 2 - disas/tci.c | 61 --------- tcg/tci.c | 283 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 284 insertions(+), 64 deletions(-) delete mode 100644 disas/tci.c diff --git a/meson.build b/meson.build index 2d8b433ff0..475d8a94ea 100644 --- a/meson.build +++ b/meson.build @@ -1901,7 +1901,7 @@ specific_ss.add(when: 'CONFIG_TCG', if_true: files( 'tcg/tcg-op.c', 'tcg/tcg.c', )) -specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('disas/tci.= c', 'tcg/tci.c')) +specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('tcg/tci.c'= )) =20 subdir('backends') subdir('disas') diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 900984c005..bbb0884af8 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -278,10 +278,8 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) #ifdef TCG_TARGET_INTERPRETER /* These opcodes are only for use between the tci generator and interprete= r. */ DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) -#if TCG_TARGET_REG_BITS =3D=3D 64 DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) #endif -#endif =20 #undef TLADDR_ARGS #undef DATA64_ARGS diff --git a/disas/tci.c b/disas/tci.c deleted file mode 100644 index f1d6c6b469..0000000000 --- a/disas/tci.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Tiny Code Interpreter for QEMU - disassembler - * - * Copyright (c) 2011 Stefan Weil - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "qemu/osdep.h" -#include "qemu-common.h" -#include "disas/dis-asm.h" -#include "tcg/tcg.h" - -/* Disassemble TCI bytecode. */ -int print_insn_tci(bfd_vma addr, disassemble_info *info) -{ - int length; - uint8_t byte; - int status; - TCGOpcode op; - - status =3D info->read_memory_func(addr, &byte, 1, info); - if (status !=3D 0) { - info->memory_error_func(status, addr, info); - return -1; - } - op =3D byte; - - addr++; - status =3D info->read_memory_func(addr, &byte, 1, info); - if (status !=3D 0) { - info->memory_error_func(status, addr, info); - return -1; - } - length =3D byte; - - if (op >=3D tcg_op_defs_max) { - info->fprintf_func(info->stream, "illegal opcode %d", op); - } else { - const TCGOpDef *def =3D &tcg_op_defs[op]; - int nb_oargs =3D def->nb_oargs; - int nb_iargs =3D def->nb_iargs; - int nb_cargs =3D def->nb_cargs; - /* TODO: Improve disassembler output. */ - info->fprintf_func(info->stream, "%s\to=3D%d i=3D%d c=3D%d", - def->name, nb_oargs, nb_iargs, nb_cargs); - } - - return length; -} diff --git a/tcg/tci.c b/tcg/tci.c index 3dc89ed829..6843e837ae 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -1076,3 +1076,286 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArch= State *env, } } } + +/* + * Disassembler that matches the interpreter + */ + +static const char *str_r(TCGReg r) +{ + static const char regs[TCG_TARGET_NB_REGS][4] =3D { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "env", "sp" + }; + + QEMU_BUILD_BUG_ON(TCG_AREG0 !=3D TCG_REG_R14); + QEMU_BUILD_BUG_ON(TCG_REG_CALL_STACK !=3D TCG_REG_R15); + + assert((unsigned)r < TCG_TARGET_NB_REGS); + return regs[r]; +} + +static const char *str_c(TCGCond c) +{ + static const char cond[16][8] =3D { + [TCG_COND_NEVER] =3D "never", + [TCG_COND_ALWAYS] =3D "always", + [TCG_COND_EQ] =3D "eq", + [TCG_COND_NE] =3D "ne", + [TCG_COND_LT] =3D "lt", + [TCG_COND_GE] =3D "ge", + [TCG_COND_LE] =3D "le", + [TCG_COND_GT] =3D "gt", + [TCG_COND_LTU] =3D "ltu", + [TCG_COND_GEU] =3D "geu", + [TCG_COND_LEU] =3D "leu", + [TCG_COND_GTU] =3D "gtu", + }; + + assert((unsigned)c < ARRAY_SIZE(cond)); + assert(cond[c][0] !=3D 0); + return cond[c]; +} + +/* Disassemble TCI bytecode. */ +int print_insn_tci(bfd_vma addr, disassemble_info *info) +{ + uint8_t buf[256]; + int length, status; + const TCGOpDef *def; + const char *op_name; + TCGOpcode op; + TCGReg r0, r1, r2, r3; +#if TCG_TARGET_REG_BITS =3D=3D 32 + TCGReg r4, r5; +#endif + tcg_target_ulong i1; + int32_t s2; + TCGCond c; + TCGMemOpIdx oi; + uint8_t pos, len; + void *ptr; + const uint8_t *tb_ptr; + + status =3D info->read_memory_func(addr, buf, 2, info); + if (status !=3D 0) { + info->memory_error_func(status, addr, info); + return -1; + } + op =3D buf[0]; + length =3D buf[1]; + + if (length < 2) { + info->fprintf_func(info->stream, "invalid length %d", length); + return 1; + } + + status =3D info->read_memory_func(addr + 2, buf + 2, length - 2, info); + if (status !=3D 0) { + info->memory_error_func(status, addr + 2, info); + return -1; + } + + def =3D &tcg_op_defs[op]; + op_name =3D def->name; + tb_ptr =3D buf + 2; + + switch (op) { + case INDEX_op_br: + case INDEX_op_call: + case INDEX_op_exit_tb: + case INDEX_op_goto_tb: + tci_args_l(&tb_ptr, &ptr); + info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); + break; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%p", + op_name, str_r(r0), str_r(r1), str_c(c), ptr); + break; + + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &c); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", + op_name, str_r(r0), str_r(r1), str_r(r2), str_c= (c)); + break; + + case INDEX_op_tci_movi_i32: + tci_args_ri(&tb_ptr, &r0, &i1); + info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "", + op_name, str_r(r0), i1); + break; + +#if TCG_TARGET_REG_BITS =3D=3D 64 + case INDEX_op_tci_movi_i64: + tci_args_rI(&tb_ptr, &r0, &i1); + info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "", + op_name, str_r(r0), i1); + break; +#endif + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i32: + case INDEX_op_ld_i64: + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i32: + case INDEX_op_st_i64: + tci_args_rrs(&tb_ptr, &r0, &r1, &s2); + info->fprintf_func(info->stream, "%-12s %s,%s,%d", + op_name, str_r(r0), str_r(r1), s2); + break; + + case INDEX_op_mov_i32: + case INDEX_op_mov_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + case INDEX_op_not_i32: + case INDEX_op_not_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + tci_args_rr(&tb_ptr, &r0, &r1); + info->fprintf_func(info->stream, "%-12s %s,%s", + op_name, str_r(r0), str_r(r1)); + break; + + case INDEX_op_add_i32: + case INDEX_op_add_i64: + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + case INDEX_op_and_i32: + case INDEX_op_and_i64: + case INDEX_op_or_i32: + case INDEX_op_or_i64: + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + case INDEX_op_div_i32: + case INDEX_op_div_i64: + case INDEX_op_rem_i32: + case INDEX_op_rem_i64: + case INDEX_op_divu_i32: + case INDEX_op_divu_i64: + case INDEX_op_remu_i32: + case INDEX_op_remu_i64: + case INDEX_op_shl_i32: + case INDEX_op_shl_i64: + case INDEX_op_shr_i32: + case INDEX_op_shr_i64: + case INDEX_op_sar_i32: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + info->fprintf_func(info->stream, "%-12s %s,%s,%s", + op_name, str_r(r0), str_r(r1), str_r(r2)); + break; + + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%d,%d", + op_name, str_r(r0), str_r(r1), str_r(r2), pos, = len); + break; + +#if TCG_TARGET_REG_BITS =3D=3D 32 + case INDEX_op_setcond2_i32: + tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &c); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", + op_name, str_r(r0), str_r(r1), str_r(r2), + str_r(r3), str_r(r4), str_c(c)); + break; + + case INDEX_op_brcond2_i32: + tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &c, &ptr); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%p", + op_name, str_r(r0), str_r(r1), + str_r(r2), str_r(r3), str_c(c), ptr); + break; + + case INDEX_op_mulu2_i32: + tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", + op_name, str_r(r0), str_r(r1), + str_r(r2), str_r(r3)); + break; + + case INDEX_op_add2_i32: + case INDEX_op_sub2_i32: + tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", + op_name, str_r(r0), str_r(r1), str_r(r2), + str_r(r3), str_r(r4), str_r(r5)); + break; +#endif + + case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_st_i64: + len =3D DIV_ROUND_UP(64, TCG_TARGET_REG_BITS); + goto do_qemu_ldst; + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_st_i32: + len =3D 1; + do_qemu_ldst: + len +=3D DIV_ROUND_UP(TARGET_LONG_BITS, TCG_TARGET_REG_BITS); + switch (len) { + case 2: + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + info->fprintf_func(info->stream, "%-12s %s,%s,%x", + op_name, str_r(r0), str_r(r1), oi); + break; + case 3: + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%x", + op_name, str_r(r0), str_r(r1), str_r(r2), o= i); + break; + case 4: + tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%x", + op_name, str_r(r0), str_r(r1), + str_r(r2), str_r(r3), oi); + break; + default: + g_assert_not_reached(); + } + break; + + default: + info->fprintf_func(info->stream, "illegal opcode %d", op); + break; + } + + return length; +} --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=grvYIe5/Gge3fEjJZ+Bf2tCoajmCwbWXSaPGURmUcZ8=; b=gL1pLnpDesm63sifvKLPt+YEL0u3sDFCOyQ+s4jj3qE197VuPG6Q/SuLkvUlelFK5f aBiWtxdNznDBRAqe45Vx6OGps+NM5toPgGkkSHYXPeSEI77tjzplqGPnRKBYzBwSyWmQ 19QFg9ecROe4cUCDpLcMNcRXa9ZRlnTyrG5EUxBvHa4y3kYUaGU+M+oBxUURKn4qUtV3 7MQ3gHwsQR5qLYTO2MeQQCsKICEbYY6NvHVFoUXQe7jejylPyC49++bbJHYUzgvn/haO uaQjr5MyH+ri9PaHX5kOMTsfc+BGaB/PmoPViol7dEHWwkfSNXiGafkWgLo31bD5g6up yDUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=grvYIe5/Gge3fEjJZ+Bf2tCoajmCwbWXSaPGURmUcZ8=; b=LS10y7bgyvUncOcNMtnMKYlNlhVcfhH4t626OzzeyAbGYIy9JjSIWGHFBOy27ksgDN NJzZqStfEOqjUD0FcB907zyCxll1QVDIUU8pLUQaSy4u3HjrE08xKw9/9Kj1v1SGgk3o jeBNFuF9LXxYj4R6cD492VF768qPLXzlxaULNQFcFSGiOY4P2w7Pn9A+wmLPGeEIMuSC J/oif381cTSTgebVRIlaeGJibYlSyodMoBIumpvYF1265Va2ssIkDPKR/84NQ2yeedfy eEGGDtbHup9CU2dXoHvXQ8UqCevEuzmMWtInWzEd3BSO+Kv2fSX4OZSZBozS+XiPIxPe tEGw== X-Gm-Message-State: AOAM531hziAf7AEx9tH/sHrRwsRuJDEYTF34dsgYuh5n2GxjTr/2Cjek Vrw09hNdICxmUNbPPIgeaIWsfUhR9Xq6TQ== X-Google-Smtp-Source: ABdhPJx0vDt83ldblRNu8Q1bMgVkfNArUCtJm2ZZJ47vZc6pcf4Xs65FZsi4tJHrNRqE8O/wTAnoOw== X-Received: by 2002:a17:90a:9414:: with SMTP id r20mr14962341pjo.158.1612751919644; Sun, 07 Feb 2021 18:38:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 37/70] tcg: Build ffi data structures for helpers Date: Sun, 7 Feb 2021 18:37:19 -0800 Message-Id: <20210208023752.270606-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We will shortly use libffi for tci, as that is the only portable way of calling arbitrary functions. Signed-off-by: Richard Henderson --- meson.build | 9 +- include/exec/helper-ffi.h | 115 +++++++++++++++++++++++++ include/exec/helper-tcg.h | 24 ++++-- target/hppa/helper.h | 2 + target/i386/ops_sse_header.h | 6 ++ target/m68k/helper.h | 1 + target/ppc/helper.h | 3 + tcg/tcg.c | 20 +++++ tests/docker/dockerfiles/fedora.docker | 1 + 9 files changed, 172 insertions(+), 9 deletions(-) create mode 100644 include/exec/helper-ffi.h diff --git a/meson.build b/meson.build index 475d8a94ea..fc08f15a00 100644 --- a/meson.build +++ b/meson.build @@ -1901,7 +1901,14 @@ specific_ss.add(when: 'CONFIG_TCG', if_true: files( 'tcg/tcg-op.c', 'tcg/tcg.c', )) -specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('tcg/tci.c'= )) + +if get_option('tcg_interpreter') + libffi =3D dependency('libffi', version: '>=3D3.0', + static: enable_static, method: 'pkg-config', + required: true) + specific_ss.add(libffi) + specific_ss.add(files('tcg/tci.c')) +endif =20 subdir('backends') subdir('disas') diff --git a/include/exec/helper-ffi.h b/include/exec/helper-ffi.h new file mode 100644 index 0000000000..3af1065af3 --- /dev/null +++ b/include/exec/helper-ffi.h @@ -0,0 +1,115 @@ +/* + * Helper file for declaring TCG helper functions. + * This one defines data structures private to tcg.c. + */ + +#ifndef HELPER_FFI_H +#define HELPER_FFI_H 1 + +#include "exec/helper-head.h" + +#define dh_ffitype_i32 &ffi_type_uint32 +#define dh_ffitype_s32 &ffi_type_sint32 +#define dh_ffitype_int &ffi_type_sint +#define dh_ffitype_i64 &ffi_type_uint64 +#define dh_ffitype_s64 &ffi_type_sint64 +#define dh_ffitype_f16 &ffi_type_uint32 +#define dh_ffitype_f32 &ffi_type_uint32 +#define dh_ffitype_f64 &ffi_type_uint64 +#ifdef TARGET_LONG_BITS +# if TARGET_LONG_BITS =3D=3D 32 +# define dh_ffitype_tl &ffi_type_uint32 +# else +# define dh_ffitype_tl &ffi_type_uint64 +# endif +#endif +#define dh_ffitype_ptr &ffi_type_pointer +#define dh_ffitype_cptr &ffi_type_pointer +#define dh_ffitype_void &ffi_type_void +#define dh_ffitype_noreturn &ffi_type_void +#define dh_ffitype_env &ffi_type_pointer +#define dh_ffitype(t) glue(dh_ffitype_, t) + +#define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 0, \ + }; + +#define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \ + static ffi_type *glue(cif_args_,NAME)[1] =3D { dh_ffitype(t1) }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 1, = \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \ + static ffi_type *glue(cif_args_,NAME)[2] =3D { \ + dh_ffitype(t1), dh_ffitype(t2) \ + }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 2, \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \ + static ffi_type *glue(cif_args_,NAME)[3] =3D { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3) \ + }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 3, \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \ + static ffi_type *glue(cif_args_,NAME)[4] =3D { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), dh_ffitype(t4) \ + }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 4, = \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \ + static ffi_type *glue(cif_args_,NAME)[5] =3D { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), \ + dh_ffitype(t4), dh_ffitype(t5) \ + }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 5, = \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \ + static ffi_type *glue(cif_args_,NAME)[6] =3D { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), \ + dh_ffitype(t4), dh_ffitype(t5), dh_ffitype(t6) \ + }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 6, = \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \ + static ffi_type *glue(cif_args_,NAME)[7] =3D { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), \ + dh_ffitype(t4), dh_ffitype(t5), dh_ffitype(t6), dh_ffitype(t7) \ + }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 7, = \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#include "helper.h" +#include "trace/generated-helpers.h" +#include "tcg-runtime.h" + +#undef DEF_HELPER_FLAGS_0 +#undef DEF_HELPER_FLAGS_1 +#undef DEF_HELPER_FLAGS_2 +#undef DEF_HELPER_FLAGS_3 +#undef DEF_HELPER_FLAGS_4 +#undef DEF_HELPER_FLAGS_5 +#undef DEF_HELPER_FLAGS_6 +#undef DEF_HELPER_FLAGS_7 + +#endif /* HELPER_FFI_H */ diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h index 27870509a2..a71b848576 100644 --- a/include/exec/helper-tcg.h +++ b/include/exec/helper-tcg.h @@ -10,50 +10,57 @@ to get all the macros expanded first. */ #define str(s) #s =20 +#ifdef CONFIG_TCG_INTERPRETER +# define DO_CIF(NAME) .cif =3D &cif_##NAME, +#else +# define DO_CIF(NAME) +#endif + #define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) }, =20 #define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) }, =20 #define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) }, =20 #define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) }, =20 #define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) }, =20 #define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | dh_sizemask(t5, 5) }, =20 #define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) }, =20 #define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), .flags =3D FLAGS, \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ + .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) | dh_sizemask(t7, 7) }, @@ -64,6 +71,7 @@ #include "plugin-helpers.h" =20 #undef str +#undef DO_CIF #undef DEF_HELPER_FLAGS_0 #undef DEF_HELPER_FLAGS_1 #undef DEF_HELPER_FLAGS_2 diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 2d483aab58..35c612f09d 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -1,9 +1,11 @@ #if TARGET_REGISTER_BITS =3D=3D 64 # define dh_alias_tr i64 # define dh_is_64bit_tr 1 +# define dh_ffitype_tr dh_ffitype_i64 #else # define dh_alias_tr i32 # define dh_is_64bit_tr 0 +# define dh_ffitype_tr dh_ffitype_i32 #endif #define dh_ctype_tr target_ureg #define dh_is_signed_tr 0 diff --git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h index 6c0c849347..cae50f77eb 100644 --- a/target/i386/ops_sse_header.h +++ b/target/i386/ops_sse_header.h @@ -27,13 +27,19 @@ #define dh_alias_Reg ptr #define dh_alias_ZMMReg ptr #define dh_alias_MMXReg ptr + #define dh_ctype_Reg Reg * #define dh_ctype_ZMMReg ZMMReg * #define dh_ctype_MMXReg MMXReg * + #define dh_is_signed_Reg dh_is_signed_ptr #define dh_is_signed_ZMMReg dh_is_signed_ptr #define dh_is_signed_MMXReg dh_is_signed_ptr =20 +#define dh_ffitype_Reg dh_ffitype_ptr +#define dh_ffitype_ZMMReg dh_ffitype_ptr +#define dh_ffitype_MMXReg dh_ffitype_ptr + DEF_HELPER_3(glue(psrlw, SUFFIX), void, env, Reg, Reg) DEF_HELPER_3(glue(psraw, SUFFIX), void, env, Reg, Reg) DEF_HELPER_3(glue(psllw, SUFFIX), void, env, Reg, Reg) diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 77808497a9..672c99d5de 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -18,6 +18,7 @@ DEF_HELPER_4(cas2l_parallel, void, env, i32, i32, i32) #define dh_alias_fp ptr #define dh_ctype_fp FPReg * #define dh_is_signed_fp dh_is_signed_ptr +#define dh_ffitype_fp dh_ffitype_ptr =20 DEF_HELPER_3(exts32, void, env, fp, s32) DEF_HELPER_3(extf32, void, env, fp, f32) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 6a4dccf70c..bbd4700064 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -108,10 +108,12 @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i= 64) #define dh_alias_avr ptr #define dh_ctype_avr ppc_avr_t * #define dh_is_signed_avr dh_is_signed_ptr +#define dh_ffitype_avr dh_ffitype_ptr =20 #define dh_alias_vsr ptr #define dh_ctype_vsr ppc_vsr_t * #define dh_is_signed_vsr dh_is_signed_ptr +#define dh_ffitype_vsr dh_ffitype_ptr =20 DEF_HELPER_3(vavgub, void, avr, avr, avr) DEF_HELPER_3(vavguh, void, avr, avr, avr) @@ -696,6 +698,7 @@ DEF_HELPER_3(store_601_batu, void, env, i32, tl) #define dh_alias_fprp ptr #define dh_ctype_fprp ppc_fprp_t * #define dh_is_signed_fprp dh_is_signed_ptr +#define dh_ffitype_fprp dh_ffitype_ptr =20 DEF_HELPER_4(dadd, void, env, fprp, fprp, fprp) DEF_HELPER_4(daddq, void, env, fprp, fprp, fprp) diff --git a/tcg/tcg.c b/tcg/tcg.c index 2991112829..6382112215 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -66,6 +66,10 @@ #include "exec/log.h" #include "sysemu/sysemu.h" =20 +#ifdef CONFIG_TCG_INTERPRETER +#include +#endif + /* Forward declarations for functions declared in tcg-target.c.inc and used here. */ static void tcg_target_init(TCGContext *s); @@ -1082,6 +1086,9 @@ void tcg_pool_reset(TCGContext *s) =20 typedef struct TCGHelperInfo { void *func; +#ifdef CONFIG_TCG_INTERPRETER + ffi_cif *cif; +#endif const char *name; unsigned flags; unsigned sizemask; @@ -1089,6 +1096,10 @@ typedef struct TCGHelperInfo { =20 #include "exec/helper-proto.h" =20 +#ifdef CONFIG_TCG_INTERPRETER +#include "exec/helper-ffi.h" +#endif + static const TCGHelperInfo all_helpers[] =3D { #include "exec/helper-tcg.h" }; @@ -1136,6 +1147,15 @@ void tcg_context_init(TCGContext *s) (gpointer)&all_helpers[i]); } =20 +#ifdef CONFIG_TCG_INTERPRETER + for (i =3D 0; i < ARRAY_SIZE(all_helpers); ++i) { + ffi_cif *cif =3D all_helpers[i].cif; + ffi_status ok =3D ffi_prep_cif(cif, FFI_DEFAULT_ABI, cif->nargs, + cif->rtype, cif->arg_types); + tcg_debug_assert(ok =3D=3D FFI_OK); + } +#endif + tcg_target_init(s); process_op_defs(s); =20 diff --git a/tests/docker/dockerfiles/fedora.docker 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vBr7vhN4PGwbH1KaQVzNdMhftTOwE1A/EapiaKgFiUE=; b=E3Yy6xpk8gfiWVxzG9e1PrW3F7YCZoGlzAbVHJIf3TjYyOH5t22e2BbipFyGD/0ENj t473LFlXUAt4lKIql7dzDag8F9T9GTbLwBkDEe9UJfasCkZytGmzpRtzz0hjh0Gr+EVG EA1Hbj421doRiB8vRPE0EoLppn7QmfFaDcWxRJTIutvIHPged1Vt8pzZgrqO/ElAcE70 jbUILebwhEr85VwRjGDDeGS5T7e/YR7OxmChWbsffKGH6HLeAmb0O4+SqgFxTZs8Qh9q YSxn7XUUCDTFx78DVqr1LKLtar5iNJiFXHDn98K1FmcqowjTpZLUgyUPjBJJhiViVyoz Bsow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vBr7vhN4PGwbH1KaQVzNdMhftTOwE1A/EapiaKgFiUE=; b=hCaM4usth6Le1dvdARscDbvXiAd96dhPeuPaWT6Fa/mNoBvKxtoFPqApB655zFexIl WDYoxlYQICMia4OZ+7fj+1O4tBrtiRvH4iCZj1TI1U+QcOLh5orYAatE3tohvAGbtLFO iSnx7LPnWsS2sugzgr0o2OqypF0GUV7EHYJbnITmJJKViAZVebFtsYRMohvrvuGyarHe 8EfRjKm30pNgz6E9b5hcwg0TaTx3iEnU7gMywKmhdBljQKtbXAOXp552573LUIVv6f4z coYalmi8of0vUP7kx+PZ3BCIFelnq5MvdQqMcTTDcKLgzJxhtvEXW6KXxv3K+GMZLGPS iRoQ== X-Gm-Message-State: AOAM533xdrmMg/LlcGtyTv8lHsqOpUYEfQ5nRWZ2Vql8wUpAKJcCBSZj nx/zbdJEcEfnjqpeYkYE3x4x8yhrH/g9dg== X-Google-Smtp-Source: ABdhPJyBydnKjgStJIAmkBRRfURpq560k8e/xO80osMVHl7K0A39MT5lNQt5vDkubLBz5vR5zGkv2A== X-Received: by 2002:a17:90a:b895:: with SMTP id o21mr5330653pjr.200.1612751920854; Sun, 07 Feb 2021 18:38:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 38/70] tcg/tci: Use ffi for calls Date: Sun, 7 Feb 2021 18:37:20 -0800 Message-Id: <20210208023752.270606-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This requires adjusting where arguments are stored. Place them on the stack at left-aligned positions. Adjust the stack frame to be at entirely positive offsets. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 + tcg/tci/tcg-target.h | 2 +- tcg/tcg.c | 72 ++++++++++++--------- tcg/tci.c | 131 ++++++++++++++++++++++----------------- tcg/tci/tcg-target.c.inc | 50 +++++++-------- 5 files changed, 143 insertions(+), 113 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 0f0695e90d..e5573a9877 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -53,6 +53,7 @@ #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) =20 #define CPU_TEMP_BUF_NLONGS 128 +#define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) =20 /* Default target word size to pointer size. */ #ifndef TCG_TARGET_REG_BITS diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 52af6d8bc5..4df10e2e83 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -161,7 +161,7 @@ typedef enum { =20 /* Used for function call generation. */ #define TCG_TARGET_CALL_STACK_OFFSET 0 -#define TCG_TARGET_STACK_ALIGN 16 +#define TCG_TARGET_STACK_ALIGN 8 =20 #define HAVE_TCG_QEMU_TB_EXEC =20 diff --git a/tcg/tcg.c b/tcg/tcg.c index 6382112215..92aec0d238 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -208,6 +208,18 @@ static size_t tree_size; static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT]; static TCGRegSet tcg_target_call_clobber_regs; =20 +typedef struct TCGHelperInfo { + void *func; +#ifdef CONFIG_TCG_INTERPRETER + ffi_cif *cif; +#endif + const char *name; + unsigned flags; + unsigned sizemask; +} TCGHelperInfo; + +static GHashTable *helper_table; + #if TCG_TARGET_INSN_UNIT_SIZE =3D=3D 1 static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t= v) { @@ -1084,16 +1096,6 @@ void tcg_pool_reset(TCGContext *s) s->pool_current =3D NULL; } =20 -typedef struct TCGHelperInfo { - void *func; -#ifdef CONFIG_TCG_INTERPRETER - ffi_cif *cif; -#endif - const char *name; - unsigned flags; - unsigned sizemask; -} TCGHelperInfo; - #include "exec/helper-proto.h" =20 #ifdef CONFIG_TCG_INTERPRETER @@ -1103,7 +1105,6 @@ typedef struct TCGHelperInfo { static const TCGHelperInfo all_helpers[] =3D { #include "exec/helper-tcg.h" }; -static GHashTable *helper_table; =20 static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)= ]; static void process_op_defs(TCGContext *s); @@ -2081,25 +2082,38 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int na= rgs, TCGTemp **args) =20 real_args =3D 0; for (i =3D 0; i < nargs; i++) { - int is_64bit =3D sizemask & (1 << (i+1)*2); - if (TCG_TARGET_REG_BITS < 64 && is_64bit) { -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - /* some targets want aligned 64 bit args */ - if (real_args & 1) { - op->args[pi++] =3D TCG_CALL_DUMMY_ARG; - real_args++; - } + bool is_64bit =3D sizemask & (1 << (i+1)*2); + bool want_align =3D false; + +#if defined(CONFIG_TCG_INTERPRETER) + /* + * Align all arguments, so that they land in predictable places + * for passing off to ffi_call. + */ + want_align =3D true; +#elif defined(TCG_TARGET_CALL_ALIGN_ARGS) + /* Some targets want aligned 64 bit args */ + want_align =3D is_64bit; #endif - /* If stack grows up, then we will be placing successive - arguments at lower addresses, which means we need to - reverse the order compared to how we would normally - treat either big or little-endian. For those arguments - that will wind up in registers, this still works for - HPPA (the only current STACK_GROWSUP target) since the - argument registers are *also* allocated in decreasing - order. If another such target is added, this logic may - have to get more complicated to differentiate between - stack arguments and register arguments. */ + + if (TCG_TARGET_REG_BITS < 64 && want_align && (real_args & 1)) { + op->args[pi++] =3D TCG_CALL_DUMMY_ARG; + real_args++; + } + + if (TCG_TARGET_REG_BITS < 64 && is_64bit) { + /* + * If stack grows up, then we will be placing successive + * arguments at lower addresses, which means we need to + * reverse the order compared to how we would normally + * treat either big or little-endian. For those arguments + * that will wind up in registers, this still works for + * HPPA (the only current STACK_GROWSUP target) since the + * argument registers are *also* allocated in decreasing + * order. If another such target is added, this logic may + * have to get more complicated to differentiate between + * stack arguments and register arguments. + */ #if defined(HOST_WORDS_BIGENDIAN) !=3D defined(TCG_TARGET_STACK_GROWSUP) op->args[pi++] =3D temp_arg(args[i] + 1); op->args[pi++] =3D temp_arg(args[i]); diff --git a/tcg/tci.c b/tcg/tci.c index 6843e837ae..d27db9f720 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -18,6 +18,13 @@ */ =20 #include "qemu/osdep.h" +#include "qemu-common.h" +#include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */ +#include "exec/cpu_ldst.h" +#include "tcg/tcg-op.h" +#include "qemu/compiler.h" +#include + =20 /* Enable TCI assertions only when debugging TCG (and without NDEBUG defin= ed). * Without assertions, the interpreter runs much faster. */ @@ -27,36 +34,8 @@ # define tci_assert(cond) ((void)(cond)) #endif =20 -#include "qemu-common.h" -#include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */ -#include "exec/cpu_ldst.h" -#include "tcg/tcg-op.h" -#include "qemu/compiler.h" - -#if MAX_OPC_PARAM_IARGS !=3D 6 -# error Fix needed, number of supported input arguments changed! -#endif -#if TCG_TARGET_REG_BITS =3D=3D 32 -typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong); -#else -typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong); -#endif - __thread uintptr_t tci_tb_ptr; =20 -static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg = index) -{ - tci_assert(index < TCG_TARGET_NB_REGS); - return regs[index]; -} - static void tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) { @@ -131,6 +110,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **= tb_ptr) * i =3D immediate (uint32_t) * I =3D immediate (tcg_target_ulong) * m =3D immediate (TCGMemOpIdx) + * n =3D immediate (call return length) * r =3D register * s =3D signed ldst offset */ @@ -151,6 +131,16 @@ static void tci_args_l(const uint8_t **tb_ptr, void **= l0) check_size(start, tb_ptr); } =20 +static void tci_args_nl(const uint8_t **tb_ptr, uint8_t *n0, void **l1) +{ + const uint8_t *start =3D *tb_ptr; + + *n0 =3D tci_read_b(tb_ptr); + *l1 =3D (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); +} + static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { @@ -491,6 +481,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCG= Cond condition) # define CASE_64(x) #endif =20 + /* Interpret pseudo code in tb. */ /* * Disable CFI checks. @@ -502,11 +493,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, { const uint8_t *tb_ptr =3D v_tb_ptr; tcg_target_ulong regs[TCG_TARGET_NB_REGS]; - long tcg_temps[CPU_TEMP_BUF_NLONGS]; - uintptr_t sp_value =3D (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); + uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) + / sizeof(uint64_t)]; + void *call_slots[TCG_STATIC_CALL_ARGS_SIZE / sizeof(uint64_t)]; =20 regs[TCG_AREG0] =3D (tcg_target_ulong)env; - regs[TCG_REG_CALL_STACK] =3D sp_value; + regs[TCG_REG_CALL_STACK] =3D (uintptr_t)stack; + call_slots[0] =3D NULL; tci_assert(tb_ptr); =20 for (;;) { @@ -531,33 +524,53 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 switch (opc) { case INDEX_op_call: - tci_args_l(&tb_ptr, &ptr); + /* + * We are passed a pointer to the TCGHelperInfo, which contains + * the function pointer followed by the ffi_cif pointer. + */ + tci_args_nl(&tb_ptr, &len, &ptr); + + /* Helper functions may need to access the "return address" */ tci_tb_ptr =3D (uintptr_t)tb_ptr; -#if TCG_TARGET_REG_BITS =3D=3D 32 - tmp64 =3D ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0= ), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5), - tci_read_reg(regs, TCG_REG_R6), - tci_read_reg(regs, TCG_REG_R7), - tci_read_reg(regs, TCG_REG_R8), - tci_read_reg(regs, TCG_REG_R9), - tci_read_reg(regs, TCG_REG_R10), - tci_read_reg(regs, TCG_REG_R11)= ); - tci_write_reg(regs, TCG_REG_R0, tmp64); - tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); -#else - tmp64 =3D ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0= ), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5)); - tci_write_reg(regs, TCG_REG_R0, tmp64); -#endif + + /* + * Set up the ffi_avalue array once, delayed until now + * because many TB's do not make any calls. In tcg_gen_callN, + * we arranged for every real argument to be "left-aligned" + * in each 64-bit slot. + */ + if (call_slots[0] =3D=3D NULL) { + for (int i =3D 0; i < ARRAY_SIZE(call_slots); ++i) { + call_slots[i] =3D &stack[i]; + } + } + + /* + * Call the helper function. Any result winds up + * "left-aligned" in the stack[0] slot. + */ + { + void **pptr =3D ptr; + ffi_call(pptr[1], pptr[0], stack, call_slots); + } + switch (len) { + case 0: /* void */ + break; + case 1: /* uint32_t */ + regs[TCG_REG_R0] =3D *(uint32_t *)stack; + break; + case 2: /* uint64_t */ + if (TCG_TARGET_REG_BITS =3D=3D 32) { + tci_write_reg64(regs, TCG_REG_R1, TCG_REG_R0, stack[0]= ); + } else { + regs[TCG_REG_R0] =3D stack[0]; + } + break; + default: + g_assert_not_reached(); + } break; + case INDEX_op_br: tci_args_l(&tb_ptr, &ptr); tb_ptr =3D ptr; @@ -1162,13 +1175,17 @@ int print_insn_tci(bfd_vma addr, disassemble_info *= info) =20 switch (op) { case INDEX_op_br: - case INDEX_op_call: case INDEX_op_exit_tb: case INDEX_op_goto_tb: tci_args_l(&tb_ptr, &ptr); info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); break; =20 + case INDEX_op_call: + tci_args_nl(&tb_ptr, &len, &ptr); + info->fprintf_func(info->stream, "%-12s %d,%p", op_name, len, ptr= ); + break; + case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 7fb3b04eaf..8d75482546 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -192,23 +192,8 @@ static const int tcg_target_reg_alloc_order[] =3D { # error Fix needed, number of supported input arguments changed! #endif =20 -static const int tcg_target_call_iarg_regs[] =3D { - TCG_REG_R0, - TCG_REG_R1, - TCG_REG_R2, - TCG_REG_R3, - TCG_REG_R4, - TCG_REG_R5, -#if TCG_TARGET_REG_BITS =3D=3D 32 - /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */ - TCG_REG_R6, - TCG_REG_R7, - TCG_REG_R8, - TCG_REG_R9, - TCG_REG_R10, - TCG_REG_R11, -#endif -}; +/* No call arguments via registers. All will be stored on the "stack". */ +static const int tcg_target_call_iarg_regs[] =3D { }; =20 static const int tcg_target_call_oarg_regs[] =3D { TCG_REG_R0, @@ -292,8 +277,9 @@ static void tci_out_label(TCGContext *s, TCGLabel *labe= l) static void stack_bounds_check(TCGReg base, target_long offset) { if (base =3D=3D TCG_REG_CALL_STACK) { - tcg_debug_assert(offset < 0); - tcg_debug_assert(offset >=3D -(CPU_TEMP_BUF_NLONGS * sizeof(long))= ); + tcg_debug_assert(offset >=3D 0); + tcg_debug_assert(offset < (TCG_STATIC_CALL_ARGS_SIZE + + TCG_STATIC_FRAME_SIZE)); } } =20 @@ -360,11 +346,25 @@ static void tcg_out_movi(TCGContext *s, TCGType type, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 -static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { uint8_t *old_code_ptr =3D s->code_ptr; + const TCGHelperInfo *info; + uint8_t which; + + info =3D g_hash_table_lookup(helper_table, (gpointer)arg); + if (info->cif->rtype =3D=3D &ffi_type_void) { + which =3D 0; + } else if (info->cif->rtype->size =3D=3D 4) { + which =3D 1; + } else { + tcg_debug_assert(info->cif->rtype->size =3D=3D 8); + which =3D 2; + } tcg_out_op_t(s, INDEX_op_call); - tcg_out_i(s, (uintptr_t)arg); + tcg_out8(s, which); + tcg_out_i(s, (uintptr_t)info); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 @@ -629,11 +629,9 @@ static void tcg_target_init(TCGContext *s) s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); =20 - /* We use negative offsets from "sp" so that we can distinguish - stores that might pretend to be call arguments. */ - tcg_set_frame(s, TCG_REG_CALL_STACK, - -CPU_TEMP_BUF_NLONGS * sizeof(long), - CPU_TEMP_BUF_NLONGS * sizeof(long)); + /* The call arguments come first, followed by the temp storage. */ + tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, + TCG_STATIC_FRAME_SIZE); } =20 /* Generate global QEMU prologue and epilogue code. */ --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612753943; cv=none; d=zohomail.com; s=zohoarc; b=gKT8HZmZT2qbqcJuDTAJD2RaFDGtILmIYgrscXfYYBoIdICnzed4ghvfiM+ttnf7xcKWM8uKiJ24JhJHTmI2VdqQN4zAc/Oh7DEc/5Rrk3HXVWDEv2v3HVze45DDK/ubUtVISZiLhMqZrgguYy/HOLzrFiIz/FVDgo498FZRlWg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612753943; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YQBNB7jLXwaZJSYBL0BvoU6n3wPE6zwxayv+Hpeg13U=; b=DlTMzIJjWuND9gXYkm5ANwhd8uVvshfR/l/UR+W28K94QcqUOeBxjUgfQcaIpwgG8QTS7w1nmV+4sv21ZGGzuEalDUaFKg7P8uqbuajB3b2Ix0u/spKCPCY1dsIBmd5rXDbSTsozkutZfmIjDTeqGba3e4N5pkFcYvV3sK5MaeM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16127539432991002.7318613740288; Sun, 7 Feb 2021 19:12:23 -0800 (PST) Received: from localhost ([::1]:52454 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wyM-0003om-3u for importer@patchew.org; Sun, 07 Feb 2021 22:12:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58164) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wRq-0001m9-1u for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:46 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:38465) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wRn-0005ul-4i for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:38:45 -0500 Received: by mail-pf1-x435.google.com with SMTP id d26so7523957pfn.5 for ; Sun, 07 Feb 2021 18:38:42 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YQBNB7jLXwaZJSYBL0BvoU6n3wPE6zwxayv+Hpeg13U=; b=BKmkc3L+y2YKo9x6+3VASigGz1F93P3W0BTkZgKmCoCjzlZvCkap6NtC+cFlpn9TKi 8FK7+WTjMbyGLT1WBDUOOUVsJZmaLgkVbP5YTtpbx4y1CqHTuSc0nqwR7chtc/G/wxj6 iTiZesgAnBRW96qIQEz+hxSaRy34xoQEpo58u3+gdc5kvkWVkiKByTLBXvAu+jq3Bxfh KuGQcHx/loiBNSgCFAsmlMJTv5zTFOVW/4e8zsHSPhlgIeS/P3LH7BVoS2IFgTNdOKgp p8qlBBnxORbgrSv2WmcgwsvPl72AnPhaAkO1Yt8Zyc5ua5TLd7cO2LbYvWraV8gZX+3M owcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YQBNB7jLXwaZJSYBL0BvoU6n3wPE6zwxayv+Hpeg13U=; b=stBtyPhHeQSL0KZNxE9wdPKHwitCe6WnkGYgGQM/rVTYwvuc9D5bWT6jIq1YEB9cK5 5T2Vfl+Q4LI8SCaw/oN+UH5sBT4+k7YqT+nHhrp2hPwO0cns+DvOgM46rt8hjiqTGyoy g4SxEjzBZqXNt9pf/0t/a3U2Mx+791Vh/tt8XB1hXogCnTPXQpvLoy9Lzu4vpnWFSexK WYJ3C3O0JecpXyG8BYLOAUFw408tSJsc6ZKawhz5DUdOddUFiWvmv9Uvc4Xe0wxobMdw d4NjX0LamJF47nsnl/PywQYn9rzyCSfI6tqRxDjYD9wfw/8Tl/mey+eMzId8oXWJJGrs oMug== X-Gm-Message-State: AOAM533WI2WhFsuzNw6apVlDgMO156qK1z1giz0phv1diRmTsb1afi4M Sv57xc/WfKKrU14tvNezZoQ7veHUib/uHQ== X-Google-Smtp-Source: ABdhPJxWUen4CYsc0ID1q4cCUA9YZxNSLL4UyKPBdLs7DmxDquyYS/XfX4Tx988ORu7JaJ7EdAKhYg== X-Received: by 2002:a63:d446:: with SMTP id i6mr15074741pgj.446.1612751921883; Sun, 07 Feb 2021 18:38:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 39/70] tcg/tci: Improve tcg_target_call_clobber_regs Date: Sun, 7 Feb 2021 18:37:21 -0800 Message-Id: <20210208023752.270606-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The current setting is much too pessimistic. Indicating only the one or two registers that are actually assigned after a call should avoid unnecessary movement between the register array and the stack array. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8d75482546..4dae09deda 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -623,8 +623,14 @@ static void tcg_target_init(TCGContext *s) tcg_target_available_regs[TCG_TYPE_I32] =3D BIT(TCG_TARGET_NB_REGS) - = 1; /* Registers available for 64 bit operations. */ tcg_target_available_regs[TCG_TYPE_I64] =3D BIT(TCG_TARGET_NB_REGS) - = 1; - /* TODO: Which registers should be set here? */ - tcg_target_call_clobber_regs =3D BIT(TCG_TARGET_NB_REGS) - 1; + /* + * The interpreter "registers" are in the local stack frame and + * cannot be clobbered by the called helper functions. However, + * the interpreter assumes a 64-bit return value and assigns to + * the return value registers. + */ + tcg_target_call_clobber_regs =3D + MAKE_64BIT_MASK(TCG_REG_R0, 64 / TCG_TARGET_REG_BITS); =20 s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612753633; cv=none; d=zohomail.com; s=zohoarc; b=Oks81LSWfKUpPTlRbidIMt2Cuu9iNG6Ttgvt7eiUqcIU9PuZ+JP39z5amKzKf0UadID2ykS954vGWgi9gpDM0m5Q58GUA0WxiBz9qf50GBKBO+zfsnuVqNx8m+vcN5T6ki5eUFCDEXwHo8tprRLyGewmPo8Xuv9S3awYpbFiVBE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612753633; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LAWykP8xawhD0n2LEjnvxt6U+It9ZnMCGaTxxtC6jn0=; b=LNe/bVDkQv4HSYdPIosuNQUAwWRYzXoBGdPaO5Bqux8Yj2io/BabnT84Vr6BUxO3q6Mu5c6qQ+3DeJigEczqekw0cY/wQEMqAEdI9vRxq06LeoLMOjvkddWKV4nxej00cAmTROCTQ/a+KmcYzjCe7N14imrI7i62gI9X7nIk0so= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612753633462868.9027472104792; Sun, 7 Feb 2021 19:07:13 -0800 (PST) Received: from localhost ([::1]:40590 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8wtM-00078a-7B for importer@patchew.org; Sun, 07 Feb 2021 22:07:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58210) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wSL-0002He-Cf for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:17 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:56143) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wSJ-00065O-Qd for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:17 -0500 Received: by mail-pj1-x1036.google.com with SMTP id s24so7394145pjp.5 for ; Sun, 07 Feb 2021 18:39:15 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LAWykP8xawhD0n2LEjnvxt6U+It9ZnMCGaTxxtC6jn0=; b=Phli01Bxq6KD+pBdsGwXvjiRxxg49Nmd1gdPgGnsveVpNhPqc3McMLFEvdcgEuggJ9 BGVqR7vy1tQ5RYWpCRLmoteeNKLrW4dSf8keB/oI1joXqqk7y2c8PjpdpeMO+JLzwQjk M/jc8PER7Kip0mQBV2NJp+SZg0SSGtHQivaeG/W57TfqiRweEO+57ZTqWdlRCnypFtuY PFSzwcKW63TdpREgWbw7qpAo95m/kBMlFURMnC5i8aixGrBBrEeg+7rOKTetVqYLg6nV JBbi0ctRukoij3RYFehLAZnltm8SCBCinvEjMnYtF5KCDeRNFu9jNEAHqzjxO+aflhyB nvxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LAWykP8xawhD0n2LEjnvxt6U+It9ZnMCGaTxxtC6jn0=; b=B3QaHepPPw6j4mf63T2ImTX4Vsu9zpG573lmaFsoXEW/N10+PhGuNzDCmLrih+tyf3 c+kuqMS0h/7vEAMzP10G8LUZMrpMHDbUOF7PfJsbglgzYfV7k6BDIki5sYtTLpTtuLy4 /0dKXC1CXpqkgXa6bLcs5zP21iDaV3Mnj6tqNEHWhXzr3WUGObr1UyYEiBRXp4ttzd0R +UzHxqGiyqulBL0CyoobNbD0lxCRHc0SRGkO/WSwe/vCitN4xvFGRTlBK34Dk1bYBHSx Z/z9YnqZkIcpnstyDhxm3KXJgmb6DO1dRtJEqnqllbGeR13d2oiqPNsI82jF2G77wLc8 hHYQ== X-Gm-Message-State: AOAM5316AWs6SYUnOYUu7+pWFnkiN+vfaX0CSlULtyX+nXtRxiHZneTa oo45DZJ9xsd8lWLeTZYOZ66Xt1yrVJkTMQ== X-Google-Smtp-Source: ABdhPJxM/vLNKZgoXxXksLEYJjTQjEYZ2lZ+r57HdUM3VPGi8gaLkxzTCEJtBQVdpHoqpUphyrNq2g== X-Received: by 2002:a17:902:b18c:b029:da:fc41:baf8 with SMTP id s12-20020a170902b18cb02900dafc41baf8mr14332449plr.58.1612751953587; Sun, 07 Feb 2021 18:39:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 40/70] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Date: Sun, 7 Feb 2021 18:37:22 -0800 Message-Id: <20210208023752.270606-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" As the only call-clobbered regs for TCI, these should receive the least priority. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 4dae09deda..53edc50a3b 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -170,8 +170,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcod= e op) } =20 static const int tcg_target_reg_alloc_order[] =3D { - TCG_REG_R0, - TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, TCG_REG_R4, @@ -186,6 +184,8 @@ static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, + TCG_REG_R1, + TCG_REG_R0, }; =20 #if MAX_OPC_PARAM_IARGS !=3D 6 --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612754390; cv=none; d=zohomail.com; s=zohoarc; b=fDebO8Dub4DfZklRudiagKEowTm67P2w2qF/6R0PKmj72GX0p3Oo6GzmPDiFoNDgj6EBMRjXfyPa/Ct/jkEqoKLQlBKCLeGpq6Igsij7FxD8Y4kE9/otjmsvlnqS6hywqrPSZjOMQg3K+csFSRcHiBY2Vtj8fRW+I+5YpYNbpsQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612754390; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=akuogNqTsRbdFKyineyOU7+0wNNNt+eZ2/k7lVk1LqY=; b=WhVUMVIanSmhhM6KZDInuVFPhfofSB9HJt/n2P5igHD7vaAD9L3hnN9hefQ2MY1cP+9HXld4dEKSDZKpwp6BNtdzwzUcRyMTbr84rXNatZTTs3JilVzatwgXrbzGJB9Vbzk7JCVbmMn0R9EqaK+bCD+VXx1CVQ5kc57e+IqYt6I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612754390020944.7314183401786; Sun, 7 Feb 2021 19:19:50 -0800 (PST) Received: from localhost ([::1]:50166 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8x5Y-00062n-N0 for importer@patchew.org; Sun, 07 Feb 2021 22:19:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58212) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wSL-0002Hl-MQ for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:17 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:35893) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wSJ-00065Q-SJ for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:17 -0500 Received: by mail-pl1-x62a.google.com with SMTP id e9so7029480plh.3 for ; Sun, 07 Feb 2021 18:39:15 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=akuogNqTsRbdFKyineyOU7+0wNNNt+eZ2/k7lVk1LqY=; b=Fj5U1zneqN1qiULdpE1elJx5/4nCGZJReVOf4YKyuDE1dS5vE/jyfz4BKY2u0JA4x9 QRc14V3ZM1HoVqAbcQ+cJfvO91nLqp8fSiJiYrImtMxfmjSp3GAKpbRYe10tdQrLhcWp NkbNV/YVgEfPbvuBcVrZHZJ1fNj9QELiZLg9r8M+EnKBbKGo5pcwHF+OSAljv31ouqEc vF58flh5ltugEqlUx05W3sJFIvQuN5LM+M3ds0y7TVhi1TygDe2sA0jCxA1XKqL0CbmS 6aAWNEV/8NS3QaDmP/SxejA9XYKxJCt7wamguPRFR6MWp+WCKrTkRsQD6hT/9oZsABV0 GM1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=akuogNqTsRbdFKyineyOU7+0wNNNt+eZ2/k7lVk1LqY=; b=GHxsbkj0h7rpruSUv1KLLrq7A0LF9b4+w+ahuNAAGta2v8YCSsqIrkQ/EKVgip4B8h z5TdE1mjFwAsEdW9QdWOv3rlZ9aEusfgKM3RTLcEg5SLWtbx2+okFl3mduvD0KWNO7oh t7yEMcpZe+ut9cstSUGMlo8Sszek2EAOMJo+cWb5f1+RheBPeYWZYzaN+Ek9WSRJYX8t kjoHCz3ikmlPzmCNv2Ij1aJc01Sfiq1bSHZRkrTTz1SQd1bds/s/IwOsUeA+oxwWmGrc Ggu6g3++ijWfMCmrnprbdpfL6lTcUoyHudO7Tx+lJamXSuAwRCfe5h7wMDisVnqhb4+m GKOQ== X-Gm-Message-State: AOAM5321Za9/i0YEgfAI/GhSxSnElsLTsg8jWZfk7SrPfogt8siiPZ+4 uDBp+iMhuXVvgPtajspHk26vuMSkmligbQ== X-Google-Smtp-Source: ABdhPJwNzslcns1l/qLnNsUwqnwQkYIsJt3fxpgtALIJFvMqMTzqV40KirXjQqlmDaA4YDcEQDwr+g== X-Received: by 2002:a17:902:ced2:b029:e2:8db8:266f with SMTP id d18-20020a170902ced2b02900e28db8266fmr14596207plg.34.1612751954631; Sun, 07 Feb 2021 18:39:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 41/70] tcg/tci: Push opcode emit into each case Date: Sun, 7 Feb 2021 18:37:23 -0800 Message-Id: <20210208023752.270606-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We're about to split out bytecode output into helpers, but we can't do that one at a time if tcg_out_op_t is being done outside of the switch. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 53edc50a3b..050d514853 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -385,40 +385,48 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, { uint8_t *old_code_ptr =3D s->code_ptr; =20 - tcg_out_op_t(s, opc); - switch (opc) { case INDEX_op_exit_tb: + tcg_out_op_t(s, opc); tcg_out_i(s, args[0]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_goto_tb: tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); /* indirect jump method. */ + tcg_out_op_t(s, opc); tcg_out_i(s, (uintptr_t)(s->tb_jmp_target_addr + args[0])); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; set_jmp_reset_offset(s, args[0]); break; =20 case INDEX_op_br: + tcg_out_op_t(s, opc); tci_out_label(s, arg_label(args[0])); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(setcond) + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out8(s, args[3]); /* condition */ + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */ + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); tcg_out_r(s, args[4]); tcg_out8(s, args[5]); /* condition */ + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; #endif =20 @@ -436,10 +444,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, CASE_64(st32) CASE_64(st) stack_bounds_check(args[1], args[2]); + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_debug_assert(args[2] =3D=3D (int32_t)args[2]); tcg_out32(s, args[2]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(add) @@ -462,12 +472,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ + tcg_out_op_t(s, opc); { TCGArg pos =3D args[3], len =3D args[4]; TCGArg max =3D opc =3D=3D INDEX_op_deposit_i32 ? 32 : 64; @@ -481,13 +494,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, tcg_out8(s, pos); tcg_out8(s, len); } + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(brcond) + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out8(s, args[2]); /* condition */ tci_out_label(s, arg_label(args[3])); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ @@ -503,48 +519,59 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); tcg_out_r(s, args[4]); tcg_out_r(s, args[5]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; case INDEX_op_brcond2_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); tcg_out8(s, args[4]); /* condition */ tci_out_label(s, arg_label(args[5])); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; case INDEX_op_mulu2_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; #endif =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_st_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, *args++); tcg_out_r(s, *args++); if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { tcg_out_r(s, *args++); } tcg_out32(s, *args++); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: + tcg_out_op_t(s, opc); tcg_out_r(s, *args++); if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_out_r(s, *args++); @@ -554,9 +581,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, tcg_out_r(s, *args++); } tcg_out32(s, *args++); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_mb: + tcg_out_op_t(s, opc); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ @@ -565,7 +595,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, default: tcg_abort(); } - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg= 1, --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 84 +++++++++++++++++++--------------------- 1 file changed, 39 insertions(+), 45 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 050d514853..707f801099 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -283,32 +283,38 @@ static void stack_bounds_check(TCGReg base, target_lo= ng offset) } } =20 -static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg= 1, - intptr_t arg2) +static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, intptr_t i2) { uint8_t *old_code_ptr =3D s->code_ptr; =20 - stack_bounds_check(arg1, arg2); - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_op_t(s, INDEX_op_ld_i32); - tcg_out_r(s, ret); - tcg_out_r(s, arg1); - tcg_out32(s, arg2); - } else { - tcg_debug_assert(type =3D=3D TCG_TYPE_I64); -#if TCG_TARGET_REG_BITS =3D=3D 64 - tcg_out_op_t(s, INDEX_op_ld_i64); - tcg_out_r(s, ret); - tcg_out_r(s, arg1); - tcg_debug_assert(arg2 =3D=3D (int32_t)arg2); - tcg_out32(s, arg2); -#else - TODO(); -#endif - } + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_debug_assert(i2 =3D=3D (int32_t)i2); + tcg_out32(s, i2); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, + intptr_t offset) +{ + stack_bounds_check(base, offset); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_rrs(s, INDEX_op_ld_i32, val, base, offset); + break; +#if TCG_TARGET_REG_BITS =3D=3D 64 + case TCG_TYPE_I64: + tcg_out_op_rrs(s, INDEX_op_ld_i64, val, base, offset); + break; +#endif + default: + g_assert_not_reached(); + } +} + static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { uint8_t *old_code_ptr =3D s->code_ptr; @@ -444,12 +450,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, CASE_64(st32) CASE_64(st) stack_bounds_check(args[1], args[2]); - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_debug_assert(args[2] =3D=3D (int32_t)args[2]); - tcg_out32(s, args[2]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrs(s, opc, args[0], args[1], args[2]); break; =20 CASE_32_64(add) @@ -597,29 +598,22 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, } } =20 -static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg= 1, - intptr_t arg2) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, + intptr_t offset) { - uint8_t *old_code_ptr =3D s->code_ptr; - - stack_bounds_check(arg1, arg2); - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_op_t(s, INDEX_op_st_i32); - tcg_out_r(s, arg); - tcg_out_r(s, arg1); - tcg_out32(s, arg2); - } else { - tcg_debug_assert(type =3D=3D TCG_TYPE_I64); + stack_bounds_check(base, offset); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_rrs(s, INDEX_op_st_i32, val, base, offset); + break; #if TCG_TARGET_REG_BITS =3D=3D 64 - tcg_out_op_t(s, INDEX_op_st_i64); - tcg_out_r(s, arg); - tcg_out_r(s, arg1); - tcg_out32(s, arg2); -#else - TODO(); + case TCG_TYPE_I64: + tcg_out_op_rrs(s, INDEX_op_st_i64, val, base, offset); + break; #endif + default: + g_assert_not_reached(); } - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 707f801099..1e3f2c4049 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -283,6 +283,16 @@ static void stack_bounds_check(TCGReg base, target_lon= g offset) } } =20 +static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tci_out_label(s, l0); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -408,9 +418,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, break; =20 case INDEX_op_br: - tcg_out_op_t(s, opc); - tci_out_label(s, arg_label(args[0])); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_l(s, opc, arg_label(args[0])); break; =20 CASE_32_64(setcond) --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612754054; cv=none; d=zohomail.com; s=zohoarc; b=aRn40iC+3rgOEGluF5fJINDeVa/m2qGoEG0l7dCQPI7vDfjDTyMi4vV9RqytLM7VuKJwTd6ueYInk0TRZ86GjlK4LVRjsSjEUmlceYnA57HmHyhYP+llGZXL/g2ycedGjiahStNdcGCxNoxCTani3grKBJvae8WvC0SGf10j5YE= ARC-Message-Signature: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=06Y+cyMxl+dC1AQMaIsueXy7S/PiohsOvXqBqGkx3uw=; b=rXxC+wdq/sBJHlDndYVHNKoZkRxYVRDWJJ7FUhJiMWjXvg74TxD3BeIVSqZYMI4Qet ujRlU/7L+ErrbIZNE0vMWGPZG3nyevzDo3L0u0+0K1ohTJUMtlRjL772D/YTH/Sini7J JXj1mZ9b6Sh3uPyUE2KgSNUFfGUW3LMkDTw9lM/cHgxl5ipINx9IfdFlQMQd0W8bGEK5 Z++tb4ixlarIu//tY83k0nnGxS3zjzD3dPjaV29OtHHXgQyqHt8sYctvui1BQdTJwbUD MwuHeawJ27Xb2+sR4Hf7D72zuV8738bljUTnIb8vCVB55GVB/WJtQqd+rwEiXlFPEu1V anqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=06Y+cyMxl+dC1AQMaIsueXy7S/PiohsOvXqBqGkx3uw=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 1e3f2c4049..cb0cbbb8da 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -293,6 +293,16 @@ static void tcg_out_op_l(TCGContext *s, TCGOpcode op, = TCGLabel *l0) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_i(s, (uintptr_t)p0); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -403,17 +413,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, =20 switch (opc) { case INDEX_op_exit_tb: - tcg_out_op_t(s, opc); - tcg_out_i(s, args[0]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_p(s, opc, (void *)args[0]); break; =20 case INDEX_op_goto_tb: tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); /* indirect jump method. */ - tcg_out_op_t(s, opc); - tcg_out_i(s, (uintptr_t)(s->tb_jmp_target_addr + args[0])); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_p(s, opc, s->tb_jmp_target_addr + args[0]); set_jmp_reset_offset(s, args[0]); break; =20 --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Kpfe6JZmwXM15Cw7O9Ulgnnkm0DVoqv1s4+DGCwKajc=; b=CHCg94PKYsAHOhHjvVNKvl9AEgIOuie4U17Vx2j1Q0mXW+daJtzBHL870wV52I/1Jk wP7qGCipx7ORUnIfFMz01mJAX7qTqWSRcAHYFSauUxUyyMWXm8+BGOOLoVjCtKcNs3W1 y1rMhh/Z/tYpsdV3cbfeXG/hB8jynlm79B0gXRfIzatk/VSUjbPCbZRljz7JrhenC4ja v8TNSyAEez60lpQVyUfQ4kIT7zFhzOEt0Xnr5o5Mb+gL2yWSIJBYPTbUX0qI3MU//9EY PUCtKq3AWsGmP5UF+LsD68eN0BEWayRy0MMt0TGtxr/qe2eJ+dU07dxdhn3kHQZI7jVU /lVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Kpfe6JZmwXM15Cw7O9Ulgnnkm0DVoqv1s4+DGCwKajc=; b=A9Q7OAl6JPzTNIrnY8FKHCfEVYnbx+E/AfQKNN/P3roYg9DSIQohcT6RMfLKwYr1kM XdxpBL/Ku3rYNQ4aA6bAHrs2T6QfayI/5wamXUUpWfHfXQrb8uIfVxPMHgZF3+dsGJGY 5WedijyAlDU09gUOdXe+zFWOxpRHGIktQY0WarxP8J0SNqAfR/QmBeHMPaloQpZoAf1K 2DxvR2lqiqAoADiiPJLWZB6G8f/B3OQA/hKQSnUC4nosC6BkAKqAF9U8evBsoI4DoN87 x81ZposmJwlzVZDMgBo7Wz5YGHos1XCM1k0zBZiBcgej3G+fDdvtufR0rEZhMjNYNUzE P2uQ== X-Gm-Message-State: AOAM530SpMsepchMUp8Y/6rYt1BZ2unb0T20pNP87OuleXVu1KR6cnSD SdSHTcsKuWGK+u/lKXtgpeJSOHxLPNGRUg== X-Google-Smtp-Source: ABdhPJz9cDuFtiE6ZXqnrSLEys6PC6HYJ/TOA4IO6T8bSxr9lRGQ0cprfXhcFEH2n1LzWqBrcmMOtQ== X-Received: by 2002:a17:902:724c:b029:e2:d560:30b6 with SMTP id c12-20020a170902724cb02900e2d56030b6mr3497583pll.60.1612751959257; Sun, 07 Feb 2021 18:39:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 45/70] tcg/tci: Split out tcg_out_op_rr Date: Sun, 7 Feb 2021 18:37:27 -0800 Message-Id: <20210208023752.270606-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" At the same time, validate the type argument in tcg_out_mov. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index cb0cbbb8da..272e3ca70b 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -303,6 +303,17 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, = void *p0) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -337,16 +348,18 @@ static void tcg_out_ld(TCGContext *s, TCGType type, T= CGReg val, TCGReg base, =20 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { - uint8_t *old_code_ptr =3D s->code_ptr; - tcg_debug_assert(ret !=3D arg); -#if TCG_TARGET_REG_BITS =3D=3D 32 - tcg_out_op_t(s, INDEX_op_mov_i32); -#else - tcg_out_op_t(s, INDEX_op_mov_i64); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_rr(s, INDEX_op_mov_i32, ret, arg); + break; +#if TCG_TARGET_REG_BITS =3D=3D 64 + case TCG_TYPE_I64: + tcg_out_op_rr(s, INDEX_op_mov_i64, ret, arg); + break; #endif - tcg_out_r(s, ret); - tcg_out_r(s, arg); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + default: + g_assert_not_reached(); + } return true; } =20 @@ -534,10 +547,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rr(s, opc, args[0], args[1]); break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612754579; cv=none; d=zohomail.com; s=zohoarc; b=CmbNO9km0zBjpBCitOcfzdCi6NzWgSBM8CBqlMcnlrJ63ejsW5N7vGYN8r7V1CNnLJ5LtheTHn5lj846BxLSLRN8Yy0Z3D+zZZ0PxfNas17duFFdqp9kWQ55kpIYuvuu9c5TPT2aGtiJOh+WC/ZxC4yipUtoiQ+sO8vXS4fcJqA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612754579; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RzFAVc3cWW3yr0pGO36GqM64ymG+VJfs9mt8bjfFgIQ=; b=OCKzI6TLL2n5ATgn0dqU2ieDBWpYaMXdFfqZPDL3tHa+4cPBoflaxpoE61Xqo0cLCjZ+dbhV9R+/g9qmREVvG1WEM9Ryk+oq0e5kFsUvvwElgJNA7VfVKciWNJMz9gp/d42ijauIeXfO7+UrMvvAQonfk1BIYMmIOL7J5hKKg5I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612754579268872.0572454595546; Sun, 7 Feb 2021 19:22:59 -0800 (PST) Received: from localhost ([::1]:33408 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8x8c-0002NQ-34 for importer@patchew.org; Sun, 07 Feb 2021 22:22:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58304) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wSR-0002TM-TC for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:23 -0500 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:33181) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wSP-00067d-TT for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:23 -0500 Received: by mail-pg1-x534.google.com with SMTP id e7so315447pge.0 for ; Sun, 07 Feb 2021 18:39:21 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 272e3ca70b..546424c2bd 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -314,6 +314,19 @@ static void tcg_out_op_rr(TCGContext *s, TCGOpcode op,= TCGReg r0, TCGReg r1) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -500,11 +513,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrr(s, opc, args[0], args[1], args[2]); break; =20 CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QUs6bZlAERttu34ccVgcqABRUHJrBFMHH0LXLYX1oZo=; b=kwL9jfvkVVzinCWqxz1Fba+rriKLCzyyngLg2EWfvqiBt7RyeeYHj4na1K8bnsub48 JnALOSHFYgverRL+/NCyxL850XJksxaG/1bti9qNQMTCOtSCcOVPTusMpCVRuVE+vDzy +hFf16XFU/gGajr+aKyQjAi7T+iAvydAvfwG9xsJd0OrPgzxW1//3YSB1klWZdR2CWlY ejzR/t7ApG6OlOjrS/YK+/OyVeYMmDzaY8nChBeJ03xM3THtG39eYSfMsafHZyignG3W U0KSDfBxxdoBeKUR/OkGuzEyX6sTJudjxi76zyOpQsuXw4Fi1meYQ2Aw32poMj6pSi+s xxqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QUs6bZlAERttu34ccVgcqABRUHJrBFMHH0LXLYX1oZo=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 546424c2bd..5848779208 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -341,6 +341,20 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out8(s, c3); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, intptr_t offset) { @@ -454,12 +468,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, break; =20 CASE_32_64(setcond) - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out8(s, args[3]); /* condition */ - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrc(s, opc, args[0], args[1], args[2], args[3]); break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 5848779208..8eda159dde 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -355,6 +355,25 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 +static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, + TCGReg r3, TCGReg r4, TCGCond c5) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out_r(s, r4); + tcg_out8(s, c5); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} +#endif + static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, intptr_t offset) { @@ -473,15 +492,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, =20 #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: - /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */ - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - tcg_out_r(s, args[4]); - tcg_out8(s, args[5]); /* condition */ - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrrrc(s, opc, args[0], args[1], args[2], + args[3], args[4], args[5]); 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6fN3MzHzuWIrC3R6bdCZxAnV3xyNnPemffGo42IAOp8=; b=jjwViyRrNl58tmryjYGRcWOvjbYFlTUAjjBMKPwitjRs02MEbJPWqu8vlhmTDPplOo wA4mHWi1Mk6EeytJGOpR319PJY/Jur7IsGwJCPGAF21Q3ODL7tnJyCgD0AbD/L9HEjbf sFPmTOxb7A6+IqDqrmptUQ2ZZT3+S/MKkwCeWje8/oLnbKMBbnfbf7k+kvwqsNVHEF6i pDBvot/AaibRxKUfELBOa5URnKXiHI7TSswza/yp42rKajA9/oPu/CTcSzNjypXfm7/I aJ/HfcbEKAQ9/V1eElnqOmbQZJkWY8g/Bpthe04UAEP/5eNnVRqu4LLbTifZKOt7vqEt 6CnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6fN3MzHzuWIrC3R6bdCZxAnV3xyNnPemffGo42IAOp8=; b=PTGK7zqfHfbStEOCs+hHblO2i+UA1ONayQdA0tQW0/GmQQWUMB34wX65WXD2USa2NB DmqKjIxw2qPqx/kFVj+Par/8mq5aWzb+zWexZwZl+Cfuu65y5MtHJk1lBizbRe5uQrL1 qWQWgD+PQJR4yvAZasaH0Zd2gF+FIGu1xIiPDE14KCgTQGE/cePnAONT7vHL27g/ZfxB x+1EnRgkkeEaRqvqMiOkf2zMWwSYV3fWuGiEBrqb2Ptzc5wNL0QLft/BbQKU7XJ/riTb 3CWCDfTOJ8nhiUDcNh+CZXTHo3moCarnj4ZgUOiorp4uCT+gFuqaahr2MZzEQZktr5ps ELOA== X-Gm-Message-State: AOAM530dJ/C2fn9uV8zroAdE9/HLOxYuXBPp1Zh3Yj2isezEVYM+6I9r oqKIoKyS8L3rsqcyVg3tpgJYNPhdpDwL1g== X-Google-Smtp-Source: ABdhPJxgmolnM6n4OjIdwc7d0JQR+hPwywQNHIECgi6h8h1bzms3QJBzffI3g3XNd3pqmxGOVOo3tg== X-Received: by 2002:a17:90a:f302:: with SMTP id ca2mr15188455pjb.233.1612751963443; Sun, 07 Feb 2021 18:39:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 49/70] tcg/tci: Split out tcg_out_op_rrrbb Date: Sun, 7 Feb 2021 18:37:31 -0800 Message-Id: <20210208023752.270606-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8eda159dde..6c743a8fbd 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -355,6 +355,21 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out8(s, b3); + tcg_out8(s, b4); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + #if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, @@ -538,7 +553,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, break; =20 CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ - tcg_out_op_t(s, opc); { TCGArg pos =3D args[3], len =3D args[4]; TCGArg max =3D opc =3D=3D INDEX_op_deposit_i32 ? 32 : 64; @@ -546,13 +560,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, tcg_debug_assert(pos < max); tcg_debug_assert(pos + len <=3D max); =20 - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out8(s, pos); - tcg_out8(s, len); + tcg_out_op_rrrbb(s, opc, args[0], args[1], args[2], pos, len); } - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(brcond) --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612754339; cv=none; d=zohomail.com; s=zohoarc; b=W8x0MKcRb2qhFKkLGP7r70hV9wIAIQV3+wRWG4gWncnOY62M+cRZ4pA7H8P04s+IcOO3AFIUvGCs20L9XdN24eTrbdHqXQ89yrxzYLA/+jHc69jBtTu1FI0DqW7oWBcjC4lwk0W9n8cZYC+hXtvQDhSN9wzTqJRDKzOQgK6HWbo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612754339; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=p6E9LDuPBslW5lnZ+lbP25axObg1A1JUNAlm8q5oVbA=; b=nEIGCfSV4HF76ObN4uvcyh5t2z3lzm9APlZbLNCD0ieqyHLy+9eUi3dKKQbuq76CWiiDO4enQlipTVrKp+XAqna1URIT9LEVPZCdZxZz9tNK6t78+qmbHN3Cv7OZwOGSoSifJpVwm9rVgp29pJjgnPYGJCSRYrPqOjz4MBmQn3o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612754339068644.4828237667001; Sun, 7 Feb 2021 19:18:59 -0800 (PST) Received: from localhost ([::1]:46208 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8x4j-0004SI-Rt for importer@patchew.org; Sun, 07 Feb 2021 22:18:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58358) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wSV-0002bE-Pe for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:27 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:36475) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wSU-000694-0c for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:27 -0500 Received: by mail-pj1-x102b.google.com with SMTP id gx20so7943122pjb.1 for ; Sun, 07 Feb 2021 18:39:25 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=p6E9LDuPBslW5lnZ+lbP25axObg1A1JUNAlm8q5oVbA=; b=lWbvihMLWbvxLpQTBO/Xiy39ZtN3Z2mLTqZbmsRrxNh1hc+2A1iXrAPAZTiHu8BFdb XVCBzbxHOnqcWTVYncmMd246xkCKzePuZaH1qEongB2ghXmMX1HwHfBVxZqmjHSYf4qF v93RUORdCdZBWCjaLgVJZ15EEP0UQpfELyk/oNE8+nfPQmtdPRC5KW/dfJwvuOdljq2V lO0MRQk8kl9W9PdQVve2HVgHKWQoF4WLFkVrsR2q4KXjeR9OL3DMePqfl7rr/QzBQ64L CMHOkYhYdxIe8x1Vpfhk1bOI4MVatDazEzZPdDjesEC7QLOwBDIKiCI9V2aQu5y24Tqw zPJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=p6E9LDuPBslW5lnZ+lbP25axObg1A1JUNAlm8q5oVbA=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 6c743a8fbd..8cc63124d4 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -341,6 +341,20 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrcl(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGCond c2, TCGLabel *l3) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out8(s, c2); + tci_out_label(s, l3); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { @@ -565,12 +579,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, break; =20 CASE_32_64(brcond) - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out8(s, args[2]); /* condition */ - tci_out_label(s, arg_label(args[3])); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrcl(s, opc, args[0], args[1], args[2], arg_label(args[= 3])); break; =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Muk10JaSTB/BV2ItdFkgjXJDIa6PJidFm2ztv5V4ygc=; b=rrlg6FZEjBsEIe0zEJH2VzluoLMglPdLZsvwD2g11dOcCvSM/60MDteMSIfboGC8gY 1mb+wbh4G9fh7dglxV8SW5/Yf5QruVM6snRuaDp8C/Ql0Ok3GBNygiFslCh/h60004PN TiMpY+LNeE5lqE/GRF9L3D91sYZhZ5dhL8YU7Ba6iek0+btTltL46v2SICbbsTtDrGRE EWFANAxqHw2RMrXxFPeDtAjsxz32EuqKEJ7IjWcWoi8wiv6HC7vc5thn4TbXVwi6z5Go KwLOY1sY1uL8J7Lm8gLKPTF0ZgU6rUL+DHr2BugWmWVCAfvmrYR76uwctlJenvopEn0I tJsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Muk10JaSTB/BV2ItdFkgjXJDIa6PJidFm2ztv5V4ygc=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8cc63124d4..f7595fbd65 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -401,6 +401,23 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode= op, =20 old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } + +static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, + TCGReg r3, TCGReg r4, TCGReg r5) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out_r(s, r4); + tcg_out_r(s, r5); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} #endif =20 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, @@ -601,14 +618,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - tcg_out_r(s, args[4]); - tcg_out_r(s, args[5]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2], + args[3], args[4], args[5]); break; case INDEX_op_brcond2_i32: tcg_out_op_t(s, opc); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f7595fbd65..c2bbd85130 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -385,6 +385,20 @@ static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode = op, TCGReg r0, } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 +static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) @@ -632,12 +646,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; case INDEX_op_mulu2_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); break; #endif =20 --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c2bbd85130..fb4aacaca3 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -399,6 +399,23 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrrcl(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, + TCGCond c4, TCGLabel *l5) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out8(s, c4); + tci_out_label(s, l5); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) @@ -636,14 +653,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, args[3], args[4], args[5]); break; case INDEX_op_brcond2_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - tcg_out8(s, args[4]); /* condition */ - tci_out_label(s, arg_label(args[5])); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrrcl(s, opc, args[0], args[1], args[2], + args[3], args[4], arg_label(args[5])); break; case INDEX_op_mulu2_i32: tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612754628; cv=none; d=zohomail.com; s=zohoarc; b=R5fopyJ4bkEPx8noarwbaT4clCeXmmzYV9wI0ZdI5F2+wDKIWbcoLCk8OZXcWjTas6/omOL7MsbnC16hQHwRi1nj/F6dKa5PY/AOmvWo/+Y5GoVVq/KU8N9cPLPSjNqikALXkNEN/OTft59SlYpSmgMepwxGiVWFiicVlO07j0g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612754628; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UtDE8Pm65Grc/U22TwT0AwuyG4b+N8yR6xVz8cz41eM=; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UtDE8Pm65Grc/U22TwT0AwuyG4b+N8yR6xVz8cz41eM=; b=AOplEWi9iVKeLJiKb5R1Zxw9IuUZ18qYjbAv6LZ6F+drllUpyFCArhzW09N0GR1Mvc IV7/lYLoUU7hQbn8TgNwv4NmuLVDPTFLFlA9VXiCaO7GwrwuXdcTDV6M0b/RL8EnvVar TbcWen8nqdRFpvOKnFAqygD4nRgAAI7aqWjD8r4NwcZdGRiR28VUbN7jg38YXlrv+Ekw fZ/DXfMfGv5jogfHuToqeTToeD8WMYUasmA4cB/AGuvNHtTnQDU/GUYycKvEJNyg01YK SeqjMiEDvD8mBOfR0JaGcU9NlknX8C/84SWaBSrYlsVtUh/saVye98M6CA/raJ72HhkS /9OA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UtDE8Pm65Grc/U22TwT0AwuyG4b+N8yR6xVz8cz41eM=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 70 ++++++++++++++++++++++++++++++---------- 1 file changed, 53 insertions(+), 17 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index fb4aacaca3..f93772f01f 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -314,6 +314,19 @@ static void tcg_out_op_rr(TCGContext *s, TCGOpcode op,= TCGReg r0, TCGReg r1) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrm(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGArg m2) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out32(s, m2); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2) { @@ -369,6 +382,20 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrm(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGArg m3) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out32(s, m3); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4) { @@ -384,6 +411,21 @@ static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode = op, TCGReg r0, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrrm(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, TCGReg r2, TCGReg r3, TCGArg m4) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out32(s, m4); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + #if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) @@ -663,29 +705,23 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_st_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, *args++); - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); + } else { + tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); } - tcg_out32(s, *args++); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: - tcg_out_op_t(s, opc); - tcg_out_r(s, *args++); - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_r(s, *args++); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); + } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); + } else { + tcg_out_op_rrrrm(s, opc, args[0], args[1], + args[2], args[3], args[4]); } - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out32(s, *args++); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_mb: --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f93772f01f..eeafec6d44 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -303,6 +303,15 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, = void *p0) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_v(TCGContext *s, TCGOpcode op) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { uint8_t *old_code_ptr =3D s->code_ptr; @@ -587,8 +596,6 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_= unit *arg) static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { - uint8_t *old_code_ptr =3D s->code_ptr; - switch (opc) { case INDEX_op_exit_tb: tcg_out_op_p(s, opc, (void *)args[0]); @@ -725,8 +732,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, break; =20 case INDEX_op_mb: - tcg_out_op_t(s, opc); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_v(s, opc); break; =20 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index eeafec6d44..e4a5872b2a 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -312,6 +312,18 @@ static void tcg_out_op_v(TCGContext *s, TCGOpcode op) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_np(TCGContext *s, TCGOpcode op, + uint8_t n0, const void *p1) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out8(s, n0); + tcg_out_i(s, (uintptr_t)p1); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { uint8_t *old_code_ptr =3D s->code_ptr; @@ -561,7 +573,6 @@ static void tcg_out_movi(TCGContext *s, TCGType type, =20 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { - uint8_t *old_code_ptr =3D s->code_ptr; const TCGHelperInfo *info; uint8_t which; =20 @@ -574,11 +585,8 @@ static void tcg_out_call(TCGContext *s, const tcg_insn= _unit *arg) tcg_debug_assert(info->cif->rtype->size =3D=3D 8); which =3D 2; } - tcg_out_op_t(s, INDEX_op_call); - tcg_out8(s, which); - tcg_out_i(s, (uintptr_t)info); =20 - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_np(s, INDEX_op_call, which, info); } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nbzdCRnUzVvHAlHdm0W/U/kL5Ps02KKsV67u0VtR3Rc=; b=aI1MZUadjl7beKap6OTg2bPVbWJTAAde2E9trzg6HvoDaW8G5LL++TMpyceLhPhnwR 1yVcrUnUrdZkDzTTSse2XTzarjfyO4qS22jzCHLWMQcd/zMJW8I1GmCA1XXzitIheczZ 9Gmk03jUFnXjGQXoQ53TSPD8z+ze6UkY+SI0+MU9N5azW/X4lt6/sAqVHHhPONyPszKn P4g677zeUMkbBhHOX09lsZnSQjbEAe10OL7kefFSVrO01Qbz+IHocKNaakUQdlnv9Nyc FHSGZfL5bS7WiAv5lzWSVDxLIAp8HZs+jYhRl34NNtelJBAofObQXSqBxhV6f/js4Evt tRtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nbzdCRnUzVvHAlHdm0W/U/kL5Ps02KKsV67u0VtR3Rc=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 50 ++++++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 15 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index e4a5872b2a..c2d2bd24d7 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -324,6 +324,31 @@ static void tcg_out_op_np(TCGContext *s, TCGOpcode op, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t = i1) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out32(s, i1); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + +#if TCG_TARGET_REG_BITS =3D=3D 64 +static void tcg_out_op_rI(TCGContext *s, TCGOpcode op, + TCGReg r0, uint64_t i1) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out64(s, i1); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} +#endif + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { uint8_t *old_code_ptr =3D s->code_ptr; @@ -550,25 +575,20 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, = TCGReg ret, TCGReg arg) } =20 static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg t0, tcg_target_long arg) + TCGReg ret, tcg_target_long arg) { - uint8_t *old_code_ptr =3D s->code_ptr; - uint32_t arg32 =3D arg; - if (type =3D=3D TCG_TYPE_I32 || arg =3D=3D arg32) { - tcg_out_op_t(s, INDEX_op_tci_movi_i32); - tcg_out_r(s, t0); - tcg_out32(s, arg32); - } else { - tcg_debug_assert(type =3D=3D TCG_TYPE_I64); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_ri(s, INDEX_op_tci_movi_i32, ret, arg); + break; #if TCG_TARGET_REG_BITS =3D=3D 64 - tcg_out_op_t(s, INDEX_op_tci_movi_i64); - tcg_out_r(s, t0); - tcg_out64(s, arg); -#else - TODO(); + case TCG_TYPE_I64: + tcg_out_op_rI(s, INDEX_op_tci_movi_i64, ret, arg); + break; #endif + default: + g_assert_not_reached(); } - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612754380; cv=none; d=zohomail.com; s=zohoarc; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=j84CVB2/9NSVvHC05jyj/ExvjNOevKnlsYLw94URCgw=; b=eL56fdB7dyq1paBQrTFlHCnfzDliZniJhBuOY3z1M63RLg4nGFW2pZCxafS2V7kDbI /jK2HJthMJfLLCXmUDMYDw+PItlVbQWNj/5HpPXLA9JvqEaAoMac0xho7Mr+AG/RBeCU WcD+A2qBMwV5Zg4A7wAfPKwCQCuEUViH8OU+ZtbiCRZYZAkN3vu3+tTue/huHbbKHfVu 1loX7SAsYPQGb88jSE1L007sGZUcXJxN7RdGh/1XHRoneG3loudrgZIQy6zocFuqItwy 0tnQ0ogSN2pxyVpZGjNgxHjvQKRqxOpTk8bb4sUHvGcD/1Ftykb0YDY3YDDSXAUYiprl rybw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j84CVB2/9NSVvHC05jyj/ExvjNOevKnlsYLw94URCgw=; b=gwoZUoqMUW5mBENnj6wTOtug9lQEDKu7F/72ys6/D7LzhUTAcAx14sn/r72fkxHGOq 6DBZlWjF0N6akROnEyz1/XB8PS24EQAMLv5yOjtz5E89nmkhKULxTuGRF/MM2hu3KF/4 xTTtD1OadlbI+kdck87f0Rn1iayll/BGEYViOoJtT20wYD2IyU3NnqOGqaCIwhdlHovL sWW6EJ+bZsKztfWj6FVqI6UgvKeL4oQtb7vixgJRdSePeXkjNA/w8QV/qObcjwnrdOdF Rep20cZInyIMWDyU4L/gocXz5kO4FOe7cObd9rdrjg5HwF+QchXf3lg1QOmKincSIOWh CHcQ== X-Gm-Message-State: AOAM533uDOufuRfCNYUjHWFt6tO8ACkdN8hso6ep96QqAQ8qzOeOXOkq crtH6qISfcv/Znx4BwazJ6C7ZJOawH6J9Q== X-Google-Smtp-Source: ABdhPJxu48cQ3QZpw9ml+tipO7mMneeXUTlapQmt+Wg8x7YAzp1Ahf/ZqWY0lHxSsXwzBxXC2T+4pg== X-Received: by 2002:a17:90a:e646:: with SMTP id ep6mr8310147pjb.218.1612751973862; Sun, 07 Feb 2021 18:39:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 58/70] tcg/tci: Reserve r13 for a temporary Date: Sun, 7 Feb 2021 18:37:40 -0800 Message-Id: <20210208023752.270606-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We're about to adjust the offset range on host memory ops, and the format of branches. Both will require a temporary. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 1 + tcg/tci/tcg-target.c.inc | 1 + 2 files changed, 2 insertions(+) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 4df10e2e83..1558a6e44e 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -155,6 +155,7 @@ typedef enum { TCG_REG_R14, TCG_REG_R15, =20 + TCG_REG_TMP =3D TCG_REG_R13, TCG_AREG0 =3D TCG_REG_R14, TCG_REG_CALL_STACK =3D TCG_REG_R15, } TCGReg; diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c2d2bd24d7..b29e75425d 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -829,6 +829,7 @@ static void tcg_target_init(TCGContext *s) MAKE_64BIT_MASK(TCG_REG_R0, 64 / TCG_TARGET_REG_BITS); =20 s->reserved_regs =3D 0; + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); =20 /* The call arguments come first, followed by the temp storage. */ --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612754521; cv=none; d=zohomail.com; s=zohoarc; b=ZidiYPA2lKNb0qhIfwuh+786KY/4RcTJ477wYeesoQuqpgWfTZNCywWUAi2BMSqiDWx/6xhG0S740gq65K0dD3nbsXvbINr8JBo9Ov38cQ64YeN+W0z3KJC8TE/UNWBG1EiPJwUDG8JvhqVBuE5CqfsONmytNRlOgIJaHNpY5i4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612754521; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=B9R5rR38+7XqiIyLeWWFMRDiEMmeppRUcow0M2UfyuA=; b=QCDXG84DxBKtRwhShmqU07avPDAXOtJZtn+912bWfzE/Iu33ZoPjcjHGQUsdilFJm/sYrsb3IU0JR77z3tFrU2L0zVdSymCqM6NNPXsp95XQNfm1S2GZPWuqROx95jST/Si5EJ7UeJhxZg/4NDDa2rFtNqQYA4tJVdIRbya9sXM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612754521982671.6303853190595; Sun, 7 Feb 2021 19:22:01 -0800 (PST) Received: from localhost ([::1]:57612 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8x7g-0000kS-O0 for importer@patchew.org; Sun, 07 Feb 2021 22:22:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58512) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wSg-0002w8-DW for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:38 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:36059) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wSe-0006Ci-Ax for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:38 -0500 Received: by mail-pf1-x434.google.com with SMTP id 18so6616603pfz.3 for ; Sun, 07 Feb 2021 18:39:35 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B9R5rR38+7XqiIyLeWWFMRDiEMmeppRUcow0M2UfyuA=; b=zsunbZTfGM6UeEdWmDaVFEknrrQ64uR0jXiB2qaPGuBkHogmhWGb3i1bkJb2g2jyws BgVRK4mDxYUIPtUC4bx7AbdB0e1PZu6U2MYzR64SlYhAdKRC8/l9yr+iOSjixgv/Mk66 R19+v9FkLa3JANhEZDWAiz/7nzm20DW2xesqtcXjghl+DsFDjjmzO6mYCo266F3Cy1qZ nSyYx6/rCcuYtC/ivZ3IGwbTn/FIMlygESTk+UwAurxhbylTqlfN/0k/XR9bB88dLlp/ sHW1K3hvyuhOiwN0wbma4g9/RaHZPedMh5U6eN6Z5buEPQ5uRTgLD3vRotraEUS/ZPAP mUww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B9R5rR38+7XqiIyLeWWFMRDiEMmeppRUcow0M2UfyuA=; b=m05GixFOa/WO5Ik4udiy5veSeb0FU/Z2/ek9EAca8lh+0rnFDtGZMknEjRPxok51/i zfsFmdOhEvPq8QXUlwm9MeAK/iabTUyelID+tjqTXbJpOT3eN55RbNPF3s4gBXFVyglB NOsvsifPStI6ELkuPE7Yr5V2o4/Qr3pCFbdgP24Fp7XxR7CsJdF+7sruZr7Fg2pbnDll URpQw7IWBX6+vCuqZhsZyJhYRQH/zRBHaxUid+79LhLtAVwF1ZPQu7WhsLIUtIexxuzr NGSrDiBC+cB4DtUbyulwQR9BG1WC584k/I5Br7USd0VCD5G+ojTERU879KqBMZ92sFYg LprQ== X-Gm-Message-State: AOAM532KAot5cTfxoSzE/Ai4RmY7ZZ9BuTOcrueRgRy3Hx7HZX0b3X4O oQzYkJxfLKi32Q6dl6HcObU6NGpLaXtZXA== X-Google-Smtp-Source: ABdhPJwIaNQpsFsfbwrAkqO84K3M1AjiNdPchVxpje2nbhwBpV90OudbeKADSYTyxmsmSpAYbU2Cbg== X-Received: by 2002:aa7:88c7:0:b029:1d1:4f1f:5fb6 with SMTP id k7-20020aa788c70000b02901d14f1f5fb6mr15463576pff.14.1612751975023; Sun, 07 Feb 2021 18:39:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 59/70] tcg/tci: Emit setcond before brcond Date: Sun, 7 Feb 2021 18:37:41 -0800 Message-Id: <20210208023752.270606-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The encoding planned for tci does not have enough room for brcond2, with 4 registers and a condition as input as well as the label. Resolve the condition into TCG_REG_TMP, and relax brcond to one register plus a label, considering the condition to always be reg !=3D 0. Signed-off-by: Richard Henderson --- tcg/tci.c | 68 ++++++++++------------------------------ tcg/tci/tcg-target.c.inc | 52 +++++++++++------------------- 2 files changed, 35 insertions(+), 85 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index d27db9f720..e7268b13e1 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -141,6 +141,16 @@ static void tci_args_nl(const uint8_t **tb_ptr, uint8_= t *n0, void **l1) check_size(start, tb_ptr); } =20 +static void tci_args_rl(const uint8_t **tb_ptr, TCGReg *r0, void **l1) +{ + const uint8_t *start =3D *tb_ptr; + + *r0 =3D tci_read_r(tb_ptr); + *l1 =3D (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); +} + static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { @@ -212,19 +222,6 @@ static void tci_args_rrs(const uint8_t **tb_ptr, check_size(start, tb_ptr); } =20 -static void tci_args_rrcl(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3) -{ - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *c2 =3D tci_read_b(tb_ptr); - *l3 =3D (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); -} - static void tci_args_rrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { @@ -293,21 +290,6 @@ static void tci_args_rrrr(const uint8_t **tb_ptr, check_size(start, tb_ptr); } =20 -static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, - TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) -{ - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *r3 =3D tci_read_r(tb_ptr); - *c4 =3D tci_read_b(tb_ptr); - *l5 =3D (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); -} - static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) { @@ -723,8 +705,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i32: - tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); - if (tci_compare32(regs[r0], regs[r1], condition)) { + tci_args_rl(&tb_ptr, &r0, &ptr); + if ((uint32_t)regs[r0]) { tb_ptr =3D ptr; } break; @@ -741,15 +723,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, T2 =3D tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; - case INDEX_op_brcond2_i32: - tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr); - T1 =3D tci_uint64(regs[r1], regs[r0]); - T2 =3D tci_uint64(regs[r3], regs[r2]); - if (tci_compare64(T1, T2, condition)) { - tb_ptr =3D ptr; - continue; - } - break; case INDEX_op_mulu2_i32: tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); @@ -877,8 +850,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i64: - tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); - if (tci_compare64(regs[r0], regs[r1], condition)) { + tci_args_rl(&tb_ptr, &r0, &ptr); + if (regs[r0]) { tb_ptr =3D ptr; } break; @@ -1188,9 +1161,9 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr); - info->fprintf_func(info->stream, "%-12s %s,%s,%s,%p", - op_name, str_r(r0), str_r(r1), str_c(c), ptr); + tci_args_rl(&tb_ptr, &r0, &ptr); + info->fprintf_func(info->stream, "%-12s %s,0,ne,%p", + op_name, str_r(r0), ptr); break; =20 case INDEX_op_setcond_i32: @@ -1315,13 +1288,6 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) str_r(r3), str_r(r4), str_c(c)); break; =20 - case INDEX_op_brcond2_i32: - tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &c, &ptr); - info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%p", - op_name, str_r(r0), str_r(r1), - str_r(r2), str_r(r3), str_c(c), ptr); - break; - case INDEX_op_mulu2_i32: tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index b29e75425d..e06d4e9380 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -349,6 +349,17 @@ static void tcg_out_op_rI(TCGContext *s, TCGOpcode op, } #endif =20 +static void tcg_out_op_rl(TCGContext *s, TCGOpcode op, TCGReg r0, TCGLabel= *l1) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tci_out_label(s, l1); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { uint8_t *old_code_ptr =3D s->code_ptr; @@ -400,20 +411,6 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 -static void tcg_out_op_rrcl(TCGContext *s, TCGOpcode op, - TCGReg r0, TCGReg r1, TCGCond c2, TCGLabel *l3) -{ - uint8_t *old_code_ptr =3D s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out8(s, c2); - tci_out_label(s, l3); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; -} - static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { @@ -487,23 +484,6 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 -static void tcg_out_op_rrrrcl(TCGContext *s, TCGOpcode op, - TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, - TCGCond c4, TCGLabel *l5) -{ - uint8_t *old_code_ptr =3D s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out8(s, c4); - tci_out_label(s, l5); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; -} - static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) @@ -704,7 +684,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, break; =20 CASE_32_64(brcond) - tcg_out_op_rrcl(s, opc, args[0], args[1], args[2], arg_label(args[= 3])); + tcg_out_op_rrrc(s, (opc =3D=3D INDEX_op_brcond_i32 + ? INDEX_op_setcond_i32 : INDEX_op_setcond_i64), + TCG_REG_TMP, args[0], args[1], args[2]); + tcg_out_op_rl(s, opc, TCG_REG_TMP, arg_label(args[3])); break; =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ @@ -730,8 +713,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, args[3], args[4], args[5]); break; case INDEX_op_brcond2_i32: - tcg_out_op_rrrrcl(s, opc, args[0], args[1], args[2], - args[3], args[4], arg_label(args[5])); + tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, TCG_REG_TMP, + args[0], args[1], args[2], args[3], args[4]); + tcg_out_op_rl(s, INDEX_op_brcond_i32, TCG_REG_TMP, arg_label(args[= 5])); break; case INDEX_op_mulu2_i32: tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612754668; cv=none; d=zohomail.com; s=zohoarc; b=HNHAHJow8xM7oJs5dDbFxvmGcl+MZGQ/iufje55uciL2a0w5Ssm4vCps7PmoWdwS/WnZUhhq7Z5IWEQWqlA+emJ0l+5nG90qJhhVhB44h0xnu8qhu5/JjJGqpwP7SKQF/W4q+cuy/SRjuPpU18ZUxFDuj5yzJSQWDXDl9soEDk4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612754668; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5KjNyz2z06X1nzffKUJIUfEvh2+8GuNK8mnSHukJjZc=; b=dZ23ekH1pv+rcoLK20zjZH+pu2V5BvJK1tk4wRT2cTUdKJb5iKACVlbSINyZ2rAz9dxsXuyjtrkuN73ebzMEPg/6Ydl61q0Y1o3p1/Zt0/LaDDBgFtcihfnSiIX+2nuVUWqNtxo61AaPpefxOPUZevzcwCmfLHucPLgIuEHqnTE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612754668489995.3935623672832; Sun, 7 Feb 2021 19:24:28 -0800 (PST) Received: from localhost ([::1]:37886 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8xA3-0004BM-CR for importer@patchew.org; Sun, 07 Feb 2021 22:24:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58518) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wSh-0002yQ-Hj for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:39 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:36478) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wSf-0006Cq-7B for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:39 -0500 Received: by mail-pj1-x102d.google.com with SMTP id gx20so7943328pjb.1 for ; Sun, 07 Feb 2021 18:39:36 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5KjNyz2z06X1nzffKUJIUfEvh2+8GuNK8mnSHukJjZc=; b=EyS5RtXdu53W1EcUD9CnTS41D013uMQwN/eqZzRcjoa+b31jlow16/QEK7HkX2PlxD Fbfn5ll/ivHaz4wJI/bp8f+UYhxsRcHJbELppnhF/p1AS3Bj8+Iq9k1969N2WM+WkpaW cJQIZF1+qnt8hvzzd68MPRiW2RfCBq1YOHHzD7Ku5I+pk3s6rKDUrrZ/+PVffjQNq56m 4JH2zIbNgRdXtxVlS8nEKiiY+zgjuMEwILwRplJ2HCq3KSsq7mdLuL8aefdbJpELlJPp 9z6zm7UaOSRQbko+5Tk18SM0Oh+vVhUNvx6UicWq/JrNBjz4TWzfJkNo+qDMEc2r6W65 BYKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5KjNyz2z06X1nzffKUJIUfEvh2+8GuNK8mnSHukJjZc=; b=Uz2l0/xTxuoAZQ4t7dUPojsgLNpMsGADcVKLwhyBLnaz1mznEHbwKLG/JlVvZR54Id qR2kD4mrzdbARkcxOkJoygUS8XjoCV3nrV0042mIfBlXJjETyIHMbg6ysrwaM7YQyz6R V6eyCTl0vB6dkvYkiu/GeGEPy3RwfvE3HSrkfIfCDaCebW+LrNwt/RqYhfWph84FOuba Dei5kYGbgXy02BNpQDpM8u4dfo4U+edll0N7co20s06Hy3FOHinsubK9is/+i2viAHqZ ynkq29DRZAZTWM4fb5UHMwqdM0/1DRcZ2CZxga9VALlsTlUKi+/R7GtDRBanWIdxYIIG bpdA== X-Gm-Message-State: AOAM530/30VoVLKPESCCEqYBvnov4kgcH6oRUL+r0Zkx3tauTbyAtxDT xb/Id6MZi7yObk2fz74c1boYPnwTa4qO6A== X-Google-Smtp-Source: ABdhPJz/dSks42GzfaWD9Ay7JzTjTXBvSEI6kYxUDHuj9hxAbl/RQZ17+BEAg9U475LDk/JDQVUaoQ== X-Received: by 2002:a17:90b:4b02:: with SMTP id lx2mr8150869pjb.178.1612751975961; Sun, 07 Feb 2021 18:39:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 60/70] tcg/tci: Remove tci_write_reg Date: Sun, 7 Feb 2021 18:37:42 -0800 Message-Id: <20210208023752.270606-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Inline it into its one caller, tci_write_reg64. Drop the asserts that are redundant with tcg_read_r. Signed-off-by: Richard Henderson --- tcg/tci.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index e7268b13e1..4f81cbb904 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -36,20 +36,11 @@ =20 __thread uintptr_t tci_tb_ptr; =20 -static void -tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) -{ - tci_assert(index < TCG_TARGET_NB_REGS); - tci_assert(index !=3D TCG_AREG0); - tci_assert(index !=3D TCG_REG_CALL_STACK); - regs[index] =3D value; -} - static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, uint32_t low_index, uint64_t value) { - tci_write_reg(regs, low_index, value); - tci_write_reg(regs, high_index, value >> 32); + regs[low_index] =3D value; + regs[high_index] =3D value >> 32; } =20 /* Create a 64 bit value from two 32 bit values. */ --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612754354; cv=none; d=zohomail.com; s=zohoarc; b=Sikhz4JKrqQ0099CjGCOFVGUFEG+7VuFcJo/IXcsfdVcv6GNs3DeL5oJTyQYnvwntftxexQrxd177vYDY4gxq7QzNhFKdB3VRRLeSlP9/nNlhYMhbG4R0FQUGL6cBm315206lLEdssK9haZMD7UfGKUwyDc0lkNuMreup8C6aJs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612754354; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kzUnbpFd4N7AqVaseztP0v4eZMlcZVSSr/zLlepL4IA=; b=FTCl1YdObivWnqk0NhOLdDoa6DQax9JwuccHkGL0ID5/txx6yYZrtxb+DYIC0GkZRAy3mpLeJ8Lvb9r6Op1J9iASrqPnqCWPnkJxujQYS702R6pD8dA8DB+c29Inaf7Ojmc00VzRIJy4gyCcWdDux2V9v/PzP4WGmgsOU5u5iiQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612754354616587.8367064736254; Sun, 7 Feb 2021 19:19:14 -0800 (PST) Received: from localhost ([::1]:47534 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8x4z-0004yk-Ag for importer@patchew.org; Sun, 07 Feb 2021 22:19:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58582) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wSl-00036P-ES for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:43 -0500 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:41424) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wSg-0006D3-RP for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:43 -0500 Received: by mail-pf1-x436.google.com with SMTP id q20so8753836pfu.8 for ; Sun, 07 Feb 2021 18:39:38 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kzUnbpFd4N7AqVaseztP0v4eZMlcZVSSr/zLlepL4IA=; b=hIM54Wcd2lti634cS/l/36BH1QgSoBB0ce6l7oBRstOLW9wtumMP6s/fbd8wTO4ug9 S2mhvbiXoTgfQq9aGo8endgcOlKjzf6Fn7xevMByV7pR9+Y5OHQxAgTga3UDMsHBaZYy HbNCbz7YmPY042H0qPKFbjt8nn+JvASOfuhvLp4s5mCproVk+dQUp2REoemqxkmNcKNM 5TTEPWJKCf06BWp4oaWx3Ja5QtbzvPbznsQl7q7Lrfnlq6uCl7G0AO7thOO6E2ZwqzXz pnMrzXQdA763R+77H9SQAnmBN0/NOpn6bf/DpJ/TJZFAuHR7j9/+N9kV7KbSqog1+uUv SUvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kzUnbpFd4N7AqVaseztP0v4eZMlcZVSSr/zLlepL4IA=; b=XZ/5QsUCyD250cbmWtQBReHSCMuGjX0X+XmBfXV7Wq098v1uADYyOUnt+yiLrpsRtH /Pl1uRLaCNNK1kKxnauOFxLID4VFoGMpjbwRSy5uh6/7wGJWB2ebvpzGucDnzhmUmTMM YrR7EAdbtrrhMoVJHPs1vvpWEK56KFFUQaEGdpjH2zmLVFnZ6b91BffNGqKMLDCitqPJ 7SSwZK9QxaOCC98xQVRgOHbhbNl27URAOiVSsjoVsEX/tbO3ziG0N+BA3691NlgDjc5A KeF9O/S/KicOhzJfkFuoZlU/rkRzkC5DDcK10a1vjfMSQiO3h/pgVxdjnkf4TQokh7o2 Jj0A== X-Gm-Message-State: AOAM532K4JSDre5O/sQE9GxSgdQciRdBJQgfCEvfS+AiaecGWXeLJwVb jY9nwYfP3ONv9cW6/mGt+CR1P8NH7A5Y4w== X-Google-Smtp-Source: ABdhPJyumenyDRTTJ6S+U4pLDXEz1BOZSj+a8rBFNBunq1Cnk/opXtuN8QJhGgDl3BoxhJELQ71Wsg== X-Received: by 2002:a05:6a00:80e:b029:1b6:39dd:8b2a with SMTP id m14-20020a056a00080eb02901b639dd8b2amr15769573pfk.23.1612751976984; Sun, 07 Feb 2021 18:39:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 61/70] tcg/tci: Change encoding to uint32_t units Date: Sun, 7 Feb 2021 18:37:43 -0800 Message-Id: <20210208023752.270606-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This removes all of the problems with unaligned accesses to the bytecode stream. With an 8-bit opcode at the bottom, we have 24 bits remaining, which are generally split into 6 4-bit slots. This fits well with the maximum length opcodes, e.g. INDEX_op_add2_i386, which have 6 register operands. We have, in previous patches, rearranged things such that there are no operations with a label, which have more than one other operand. Which leaves us with a 20-bit field in which to encode a label, giving us a maximum TB size of 512k -- easily large. Change the INDEX_op_tci_movi_{i32,i64} opcodes to tci_mov[il]. The former puts the immediate in the upper 20 bits of the insn, like we do for the label displacement. The later uses a label to reference an entry in the constant pool. Thus, in the worst case we still have a single memory reference for any constant, but now the constants are out-of-line of the bytecode and can be shared between different moves saving space. Change INDEX_op_call to use a label to reference a pair of pointers in the constant pool. This removes the only slightly dodgy link with the layout of struct TCGHelperInfo. The re-encode cannot be done in pieces. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 4 +- tcg/tci/tcg-target.h | 3 +- tcg/tci.c | 534 +++++++++++++++------------------------ tcg/tci/tcg-target.c.inc | 386 +++++++++++++--------------- tcg/tci/README | 20 +- 5 files changed, 380 insertions(+), 567 deletions(-) diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index bbb0884af8..5bbec858aa 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -277,8 +277,8 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) =20 #ifdef TCG_TARGET_INTERPRETER /* These opcodes are only for use between the tci generator and interprete= r. */ -DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) -DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) +DEF(tci_movi, 1, 0, 1, TCG_OPF_NOT_PRESENT) +DEF(tci_movl, 1, 0, 1, TCG_OPF_NOT_PRESENT) #endif =20 #undef TLADDR_ARGS diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 1558a6e44e..d953f2ead3 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -41,7 +41,7 @@ #define TCG_TARGET_H =20 #define TCG_TARGET_INTERPRETER 1 -#define TCG_TARGET_INSN_UNIT_SIZE 1 +#define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 =20 #if UINTPTR_MAX =3D=3D UINT32_MAX @@ -165,6 +165,7 @@ typedef enum { #define TCG_TARGET_STACK_ALIGN 8 =20 #define HAVE_TCG_QEMU_TB_EXEC +#define TCG_TARGET_NEED_POOL_LABELS =20 /* We could notice __i386__ or __s390x__ and reduce the barriers depending on the host. But if you want performance, you use the normal backend. diff --git a/tcg/tci.c b/tcg/tci.c index 4f81cbb904..c4f0a7e82d 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -49,49 +49,6 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low) return ((uint64_t)high << 32) + low; } =20 -/* Read constant byte from bytecode. */ -static uint8_t tci_read_b(const uint8_t **tb_ptr) -{ - return *(tb_ptr[0]++); -} - -/* Read register number from bytecode. */ -static TCGReg tci_read_r(const uint8_t **tb_ptr) -{ - uint8_t regno =3D tci_read_b(tb_ptr); - tci_assert(regno < TCG_TARGET_NB_REGS); - return regno; -} - -/* Read constant (native size) from bytecode. */ -static tcg_target_ulong tci_read_i(const uint8_t **tb_ptr) -{ - tcg_target_ulong value =3D *(const tcg_target_ulong *)(*tb_ptr); - *tb_ptr +=3D sizeof(value); - return value; -} - -/* Read unsigned constant (32 bit) from bytecode. */ -static uint32_t tci_read_i32(const uint8_t **tb_ptr) -{ - uint32_t value =3D *(const uint32_t *)(*tb_ptr); - *tb_ptr +=3D sizeof(value); - return value; -} - -/* Read signed constant (32 bit) from bytecode. */ -static int32_t tci_read_s32(const uint8_t **tb_ptr) -{ - int32_t value =3D *(const int32_t *)(*tb_ptr); - *tb_ptr +=3D sizeof(value); - return value; -} - -static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) -{ - return tci_read_i(tb_ptr); -} - /* * Load sets of arguments all at once. The naming convention is: * tci_args_ @@ -106,209 +63,128 @@ static tcg_target_ulong tci_read_label(const uint8_t= **tb_ptr) * s =3D signed ldst offset */ =20 -static void check_size(const uint8_t *start, const uint8_t **tb_ptr) +static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0) { - const uint8_t *old_code_ptr =3D start - 2; - uint8_t op_size =3D old_code_ptr[1]; - tci_assert(*tb_ptr =3D=3D old_code_ptr + op_size); + int diff =3D sextract32(insn, 12, 20); + *l0 =3D diff ? (void *)tb_ptr + diff : NULL; } =20 -static void tci_args_l(const uint8_t **tb_ptr, void **l0) +static void tci_args_nl(uint32_t insn, const void *tb_ptr, + uint8_t *n0, void **l1) { - const uint8_t *start =3D *tb_ptr; - - *l0 =3D (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); + *n0 =3D extract32(insn, 8, 4); + *l1 =3D sextract32(insn, 12, 20) + (void *)tb_ptr; } =20 -static void tci_args_nl(const uint8_t **tb_ptr, uint8_t *n0, void **l1) +static void tci_args_rl(uint32_t insn, const void *tb_ptr, + TCGReg *r0, void **l1) { - const uint8_t *start =3D *tb_ptr; - - *n0 =3D tci_read_b(tb_ptr); - *l1 =3D (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *l1 =3D sextract32(insn, 12, 20) + (void *)tb_ptr; } =20 -static void tci_args_rl(const uint8_t **tb_ptr, TCGReg *r0, void **l1) +static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *l1 =3D (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); } =20 -static void tci_args_rr(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1) +static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_target_ulong *i1) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *i1 =3D sextract32(insn, 12, 20); } =20 -static void tci_args_ri(const uint8_t **tb_ptr, - TCGReg *r0, tcg_target_ulong *i1) +static void tci_args_rrm(uint32_t insn, TCGReg *r0, + TCGReg *r1, TCGMemOpIdx *m2) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *i1 =3D tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *m2 =3D extract32(insn, 20, 12); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -static void tci_args_rI(const uint8_t **tb_ptr, - TCGReg *r0, tcg_target_ulong *i1) +static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *i1 =3D tci_read_i(tb_ptr); - - check_size(start, tb_ptr); -} -#endif - -static void tci_args_rrm(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2) -{ - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *m2 =3D tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); } =20 -static void tci_args_rrr(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, TCGReg *r2) +static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i= 2) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *i2 =3D sextract32(insn, 16, 16); } =20 -static void tci_args_rrs(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, int32_t *i2) -{ - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *i2 =3D tci_read_s32(tb_ptr); - - check_size(start, tb_ptr); -} - -static void tci_args_rrrc(const uint8_t **tb_ptr, +static void tci_args_rrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *c3 =3D tci_read_b(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *c3 =3D extract32(insn, 20, 4); } =20 -static void tci_args_rrrm(const uint8_t **tb_ptr, +static void tci_args_rrrm(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx = *m3) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *m3 =3D tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *m3 =3D extract32(insn, 20, 12); } =20 -static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, +static void tci_args_rrrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, uint8_t *i3, uint8_t *i4) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *i3 =3D tci_read_b(tb_ptr); - *i4 =3D tci_read_b(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *i3 =3D extract32(insn, 20, 6); + *i4 =3D extract32(insn, 26, 6); } =20 -static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, - TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4) +static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGReg *r4) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *r3 =3D tci_read_r(tb_ptr); - *m4 =3D tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *r3 =3D extract32(insn, 20, 4); + *r4 =3D extract32(insn, 24, 4); } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 -static void tci_args_rrrr(const uint8_t **tb_ptr, +static void tci_args_rrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *r3 =3D tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *r3 =3D extract32(insn, 20, 4); } =20 -static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, +static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *r3 =3D tci_read_r(tb_ptr); - *r4 =3D tci_read_r(tb_ptr); - *c5 =3D tci_read_b(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *r3 =3D extract32(insn, 20, 4); + *r4 =3D extract32(insn, 24, 4); + *c5 =3D extract32(insn, 28, 4); } =20 -static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, +static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *r3 =3D tci_read_r(tb_ptr); - *r4 =3D tci_read_r(tb_ptr); - *r5 =3D tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *r3 =3D extract32(insn, 20, 4); + *r4 =3D extract32(insn, 24, 4); + *r5 =3D extract32(insn, 28, 4); } #endif =20 @@ -464,7 +340,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCG= Cond condition) uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, const void *v_tb_ptr) { - const uint8_t *tb_ptr =3D v_tb_ptr; + const uint32_t *tb_ptr =3D v_tb_ptr; tcg_target_ulong regs[TCG_TARGET_NB_REGS]; uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) / sizeof(uint64_t)]; @@ -476,8 +352,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_assert(tb_ptr); =20 for (;;) { - TCGOpcode opc =3D tb_ptr[0]; - TCGReg r0, r1, r2, r3; + uint32_t insn; + TCGOpcode opc; + TCGReg r0, r1, r2, r3, r4; tcg_target_ulong t1; TCGCond condition; target_ulong taddr; @@ -485,23 +362,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r4, r5; + TCGReg r5; uint64_t T1, T2; #endif TCGMemOpIdx oi; int32_t ofs; void *ptr; =20 - /* Skip opcode and size entry. */ - tb_ptr +=3D 2; + insn =3D *tb_ptr++; + opc =3D extract32(insn, 0, 8); =20 switch (opc) { case INDEX_op_call: - /* - * We are passed a pointer to the TCGHelperInfo, which contains - * the function pointer followed by the ffi_cif pointer. - */ - tci_args_nl(&tb_ptr, &len, &ptr); + tci_args_nl(insn, tb_ptr, &len, &ptr); =20 /* Helper functions may need to access the "return address" */ tci_tb_ptr =3D (uintptr_t)tb_ptr; @@ -519,8 +392,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, } =20 /* - * Call the helper function. Any result winds up - * "left-aligned" in the stack[0] slot. + * We are passed a pointer into the constant pool, which + * contains a pair of the function pointer and the cif pointer. + * Any result winds up "left-aligned" in the stack[0] slot. */ { void **pptr =3D ptr; @@ -545,76 +419,80 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; =20 case INDEX_op_br: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); tb_ptr =3D ptr; continue; case INDEX_op_setcond_i32: - tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] =3D tci_compare32(regs[r1], regs[r2], condition); break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: - tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &condition); + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); T1 =3D tci_uint64(regs[r2], regs[r1]); T2 =3D tci_uint64(regs[r4], regs[r3]); regs[r0] =3D tci_compare64(T1, T2, condition); break; #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: - tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] =3D tci_compare64(regs[r1], regs[r2], condition); break; #endif CASE_32_64(mov) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D regs[r1]; break; - case INDEX_op_tci_movi_i32: - tci_args_ri(&tb_ptr, &r0, &t1); + case INDEX_op_tci_movi: + tci_args_ri(insn, &r0, &t1); regs[r0] =3D t1; break; + case INDEX_op_tci_movl: + tci_args_rl(insn, tb_ptr, &r0, &ptr); + regs[r0] =3D *(tcg_target_ulong *)ptr; + break; =20 /* Load/store operations (32 bit). */ =20 CASE_32_64(ld8u) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(uint8_t *)ptr; break; CASE_32_64(ld8s) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(int8_t *)ptr; break; CASE_32_64(ld16u) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(uint16_t *)ptr; break; CASE_32_64(ld16s) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(int16_t *)ptr; break; case INDEX_op_ld_i32: CASE_64(ld32u) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(uint32_t *)ptr; break; CASE_32_64(st8) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); *(uint8_t *)ptr =3D regs[r0]; break; CASE_32_64(st16) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); *(uint16_t *)ptr =3D regs[r0]; break; case INDEX_op_st_i32: CASE_64(st32) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); *(uint32_t *)ptr =3D regs[r0]; break; @@ -622,171 +500,166 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArch= State *env, /* Arithmetic operations (mixed 32/64 bit). */ =20 CASE_32_64(add) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] + regs[r2]; break; CASE_32_64(sub) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] - regs[r2]; break; CASE_32_64(mul) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] * regs[r2]; break; CASE_32_64(and) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] & regs[r2]; break; CASE_32_64(or) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] | regs[r2]; break; CASE_32_64(xor) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] ^ regs[r2]; break; =20 /* Arithmetic operations (32 bit). */ =20 case INDEX_op_div_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (int32_t)regs[r1] / (int32_t)regs[r2]; break; case INDEX_op_divu_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint32_t)regs[r1] / (uint32_t)regs[r2]; break; case INDEX_op_rem_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (int32_t)regs[r1] % (int32_t)regs[r2]; break; case INDEX_op_remu_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint32_t)regs[r1] % (uint32_t)regs[r2]; break; =20 /* Shift/rotate operations (32 bit). */ =20 case INDEX_op_shl_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint32_t)regs[r1] << (regs[r2] & 31); break; case INDEX_op_shr_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint32_t)regs[r1] >> (regs[r2] & 31); break; case INDEX_op_sar_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (int32_t)regs[r1] >> (regs[r2] & 31); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D rol32(regs[r1], regs[r2] & 31); break; case INDEX_op_rotr_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D ror32(regs[r1], regs[r2] & 31); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: - tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] =3D deposit32(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i32: - tci_args_rl(&tb_ptr, &r0, &ptr); + tci_args_rl(insn, tb_ptr, &r0, &ptr); if ((uint32_t)regs[r0]) { tb_ptr =3D ptr; } break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: - tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 =3D tci_uint64(regs[r3], regs[r2]); T2 =3D tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 + T2); break; case INDEX_op_sub2_i32: - tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 =3D tci_uint64(regs[r3], regs[r2]); T2 =3D tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; case INDEX_op_mulu2_i32: - tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D (int8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 CASE_32_64(ext16s) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D (int16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 CASE_32_64(ext8u) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D (uint8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 CASE_32_64(ext16u) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D (uint16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 CASE_32_64(bswap16) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D bswap16(regs[r1]); break; #endif #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 CASE_32_64(bswap32) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D bswap32(regs[r1]); break; #endif #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 CASE_32_64(not) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D ~regs[r1]; break; #endif #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 CASE_32_64(neg) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D -regs[r1]; break; #endif #if TCG_TARGET_REG_BITS =3D=3D 64 - case INDEX_op_tci_movi_i64: - tci_args_rI(&tb_ptr, &r0, &t1); - regs[r0] =3D t1; - break; - /* Load/store operations (64 bit). */ =20 case INDEX_op_ld32s_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(int32_t *)ptr; break; case INDEX_op_ld_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(uint64_t *)ptr; break; case INDEX_op_st_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); *(uint64_t *)ptr =3D regs[r0]; break; @@ -794,71 +667,71 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, /* Arithmetic operations (64 bit). */ =20 case INDEX_op_div_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (int64_t)regs[r1] / (int64_t)regs[r2]; break; case INDEX_op_divu_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint64_t)regs[r1] / (uint64_t)regs[r2]; break; case INDEX_op_rem_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (int64_t)regs[r1] % (int64_t)regs[r2]; break; case INDEX_op_remu_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint64_t)regs[r1] % (uint64_t)regs[r2]; break; =20 /* Shift/rotate operations (64 bit). */ =20 case INDEX_op_shl_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] << (regs[r2] & 63); break; case INDEX_op_shr_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] >> (regs[r2] & 63); break; case INDEX_op_sar_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (int64_t)regs[r1] >> (regs[r2] & 63); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D rol64(regs[r1], regs[r2] & 63); break; case INDEX_op_rotr_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D ror64(regs[r1], regs[r2] & 63); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: - tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] =3D deposit64(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i64: - tci_args_rl(&tb_ptr, &r0, &ptr); + tci_args_rl(insn, tb_ptr, &r0, &ptr); if (regs[r0]) { tb_ptr =3D ptr; } break; case INDEX_op_ext32s_i64: case INDEX_op_ext_i32_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D (int32_t)regs[r1]; break; case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D (uint32_t)regs[r1]; break; #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D bswap64(regs[r1]); break; #endif @@ -867,20 +740,20 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, /* QEMU specific operations. */ =20 case INDEX_op_exit_tb: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); return (uintptr_t)ptr; =20 case INDEX_op_goto_tb: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); tb_ptr =3D *(void **)ptr; break; =20 case INDEX_op_qemu_ld_i32: if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; } else { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr =3D tci_uint64(regs[r2], regs[r1]); } switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { @@ -916,14 +789,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_qemu_ld_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr =3D regs[r2]; } else { - tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); taddr =3D tci_uint64(regs[r3], regs[r2]); + oi =3D regs[r4]; } switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: @@ -974,10 +848,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_qemu_st_i32: if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; } else { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr =3D tci_uint64(regs[r2], regs[r1]); } tmp32 =3D regs[r0]; @@ -1004,16 +878,17 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchS= tate *env, =20 case INDEX_op_qemu_st_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; tmp64 =3D regs[r0]; } else { if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr =3D regs[r2]; } else { - tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); taddr =3D tci_uint64(regs[r3], regs[r2]); + oi =3D regs[r4]; } tmp64 =3D tci_uint64(regs[r1], regs[r0]); } @@ -1097,14 +972,14 @@ static const char *str_c(TCGCond c) /* Disassemble TCI bytecode. */ int print_insn_tci(bfd_vma addr, disassemble_info *info) { - uint8_t buf[256]; - int length, status; + const uint32_t *tb_ptr =3D (const void *)(uintptr_t)addr; const TCGOpDef *def; const char *op_name; + uint32_t insn; TCGOpcode op; - TCGReg r0, r1, r2, r3; + TCGReg r0, r1, r2, r3, r4; #if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r4, r5; + TCGReg r5; #endif tcg_target_ulong i1; int32_t s2; @@ -1112,71 +987,54 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) TCGMemOpIdx oi; uint8_t pos, len; void *ptr; - const uint8_t *tb_ptr; =20 - status =3D info->read_memory_func(addr, buf, 2, info); - if (status !=3D 0) { - info->memory_error_func(status, addr, info); - return -1; - } - op =3D buf[0]; - length =3D buf[1]; + /* TCI is always the host, so we don't need to load indirect. */ + insn =3D *tb_ptr++; =20 - if (length < 2) { - info->fprintf_func(info->stream, "invalid length %d", length); - return 1; - } - - status =3D info->read_memory_func(addr + 2, buf + 2, length - 2, info); - if (status !=3D 0) { - info->memory_error_func(status, addr + 2, info); - return -1; - } + info->fprintf_func(info->stream, "%08x ", insn); =20 + op =3D extract32(insn, 0, 8); def =3D &tcg_op_defs[op]; op_name =3D def->name; - tb_ptr =3D buf + 2; =20 switch (op) { case INDEX_op_br: case INDEX_op_exit_tb: case INDEX_op_goto_tb: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); break; =20 case INDEX_op_call: - tci_args_nl(&tb_ptr, &len, &ptr); + tci_args_nl(insn, tb_ptr, &len, &ptr); info->fprintf_func(info->stream, "%-12s %d,%p", op_name, len, ptr= ); break; =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - tci_args_rl(&tb_ptr, &r0, &ptr); + tci_args_rl(insn, tb_ptr, &r0, &ptr); info->fprintf_func(info->stream, "%-12s %s,0,ne,%p", op_name, str_r(r0), ptr); break; =20 case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &c); + tci_args_rrrc(insn, &r0, &r1, &r2, &c); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_c= (c)); break; =20 - case INDEX_op_tci_movi_i32: - tci_args_ri(&tb_ptr, &r0, &i1); + case INDEX_op_tci_movi: + tci_args_ri(insn, &r0, &i1); info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "", op_name, str_r(r0), i1); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 - case INDEX_op_tci_movi_i64: - tci_args_rI(&tb_ptr, &r0, &i1); - info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "", - op_name, str_r(r0), i1); + case INDEX_op_tci_movl: + tci_args_rl(insn, tb_ptr, &r0, &ptr); + info->fprintf_func(info->stream, "%-12s %s,%p", + op_name, str_r(r0), ptr); break; -#endif =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: @@ -1197,7 +1055,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) case INDEX_op_st32_i64: case INDEX_op_st_i32: case INDEX_op_st_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &s2); + tci_args_rrs(insn, &r0, &r1, &s2); info->fprintf_func(info->stream, "%-12s %s,%s,%d", op_name, str_r(r0), str_r(r1), s2); break; @@ -1224,7 +1082,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) case INDEX_op_not_i64: case INDEX_op_neg_i32: case INDEX_op_neg_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); info->fprintf_func(info->stream, "%-12s %s,%s", op_name, str_r(r0), str_r(r1)); break; @@ -1259,28 +1117,28 @@ int print_insn_tci(bfd_vma addr, disassemble_info *= info) case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); info->fprintf_func(info->stream, "%-12s %s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2)); break; =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%d,%d", op_name, str_r(r0), str_r(r1), str_r(r2), pos, = len); break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: - tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &c); + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3), str_r(r4), str_c(c)); break; =20 case INDEX_op_mulu2_i32: - tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3)); @@ -1288,7 +1146,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) =20 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3), str_r(r4), str_r(r5)); @@ -1306,30 +1164,38 @@ int print_insn_tci(bfd_vma addr, disassemble_info *= info) len +=3D DIV_ROUND_UP(TARGET_LONG_BITS, TCG_TARGET_REG_BITS); switch (len) { case 2: - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); info->fprintf_func(info->stream, "%-12s %s,%s,%x", op_name, str_r(r0), str_r(r1), oi); break; case 3: - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%x", op_name, str_r(r0), str_r(r1), str_r(r2), o= i); break; case 4: - tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); - info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%x", + tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s", op_name, str_r(r0), str_r(r1), - str_r(r2), str_r(r3), oi); + str_r(r2), str_r(r3), str_r(r4)); break; default: g_assert_not_reached(); } break; =20 + case 0: + /* tcg_out_nop_fill uses zeros */ + if (insn =3D=3D 0) { + info->fprintf_func(info->stream, "align"); + break; + } + /* fall through */ + default: info->fprintf_func(info->stream, "illegal opcode %d", op); break; } =20 - return length; + return sizeof(insn); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index e06d4e9380..0df8384be7 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -22,20 +22,7 @@ * THE SOFTWARE. */ =20 -/* TODO list: - * - See TODO comments in code. - */ - -/* Marker for missing code. */ -#define TODO() \ - do { \ - fprintf(stderr, "TODO %s:%u: %s()\n", \ - __FILE__, __LINE__, __func__); \ - tcg_abort(); \ - } while (0) - -/* Bitfield n...m (in 32 bit value). */ -#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) +#include "../tcg-pool.c.inc" =20 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { @@ -226,52 +213,16 @@ static const char *const tcg_target_reg_names[TCG_TAR= GET_NB_REGS] =3D { static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - /* tcg_out_reloc always uses the same type, addend. */ - tcg_debug_assert(type =3D=3D sizeof(tcg_target_long)); + intptr_t diff =3D value - (intptr_t)(code_ptr + 1); + tcg_debug_assert(addend =3D=3D 0); - tcg_debug_assert(value !=3D 0); - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_patch32(code_ptr, value); - } else { - tcg_patch64(code_ptr, value); - } - return true; -} - -/* Write value (native size). */ -static void tcg_out_i(TCGContext *s, tcg_target_ulong v) -{ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out32(s, v); - } else { - tcg_out64(s, v); - } -} - -/* Write opcode. */ -static void tcg_out_op_t(TCGContext *s, TCGOpcode op) -{ - tcg_out8(s, op); - tcg_out8(s, 0); -} - -/* Write register. */ -static void tcg_out_r(TCGContext *s, TCGArg t0) -{ - tcg_debug_assert(t0 < TCG_TARGET_NB_REGS); - tcg_out8(s, t0); -} - -/* Write label. */ -static void tci_out_label(TCGContext *s, TCGLabel *label) -{ - if (label->has_value) { - tcg_out_i(s, label->u.value); - tcg_debug_assert(label->u.value); - } else { - tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), label, 0); - s->code_ptr +=3D sizeof(tcg_target_ulong); + tcg_debug_assert(type =3D=3D 20); + + if (diff =3D=3D sextract32(diff, 0, type)) { + tcg_patch32(code_ptr, deposit32(*code_ptr, 32 - type, type, diff)); + return true; } + return false; } =20 static void stack_bounds_check(TCGReg base, target_long offset) @@ -285,251 +236,236 @@ static void stack_bounds_check(TCGReg base, target_= long offset) =20 static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tci_out_label(s, l0); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_reloc(s, s->code_ptr, 20, l0, 0); + insn =3D deposit32(insn, 0, 8, op); + tcg_out32(s, insn); } =20 static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; + intptr_t diff; =20 - tcg_out_op_t(s, op); - tcg_out_i(s, (uintptr_t)p0); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + /* Special case for exit_tb: map null -> 0. */ + if (p0 =3D=3D NULL) { + diff =3D 0; + } else { + diff =3D p0 - (void *)(s->code_ptr + 1); + tcg_debug_assert(diff !=3D 0); + if (diff !=3D sextract32(diff, 0, 20)) { + tcg_raise_tb_overflow(s); + } + } + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 12, 20, diff); + tcg_out32(s, insn); } =20 static void tcg_out_op_v(TCGContext *s, TCGOpcode op) { - uint8_t *old_code_ptr =3D s->code_ptr; - - tcg_out_op_t(s, op); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; -} - -static void tcg_out_op_np(TCGContext *s, TCGOpcode op, - uint8_t n0, const void *p1) -{ - uint8_t *old_code_ptr =3D s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out8(s, n0); - tcg_out_i(s, (uintptr_t)p1); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out32(s, (uint8_t)op); } =20 static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t = i1) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out32(s, i1); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_debug_assert(i1 =3D=3D sextract32(i1, 0, 20)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 20, i1); + tcg_out32(s, insn); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -static void tcg_out_op_rI(TCGContext *s, TCGOpcode op, - TCGReg r0, uint64_t i1) -{ - uint8_t *old_code_ptr =3D s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out64(s, i1); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; -} -#endif - static void tcg_out_op_rl(TCGContext *s, TCGOpcode op, TCGReg r0, TCGLabel= *l1) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tci_out_label(s, l1); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_reloc(s, s->code_ptr, 20, l1, 0); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + tcg_out32(s, insn); } =20 static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrm(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGArg m2) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out32(s, m2); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_debug_assert(m2 =3D=3D extract32(m2, 0, 12)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 20, 12, m2); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_debug_assert(i2 =3D=3D (int32_t)i2); - tcg_out32(s, i2); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_debug_assert(i2 =3D=3D sextract32(i2, 0, 16)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 16, i2); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out8(s, c3); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 4, c3); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrrm(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGArg m3) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out32(s, m3); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_debug_assert(m3 =3D=3D extract32(m3, 0, 12)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 12, m3); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out8(s, b3); - tcg_out8(s, b4); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_debug_assert(b3 =3D=3D extract32(b3, 0, 6)); + tcg_debug_assert(b4 =3D=3D extract32(b4, 0, 6)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 6, b3); + insn =3D deposit32(insn, 26, 6, b4); + tcg_out32(s, insn); } =20 -static void tcg_out_op_rrrrm(TCGContext *s, TCGOpcode op, TCGReg r0, - TCGReg r1, TCGReg r2, TCGReg r3, TCGArg m4) +static void tcg_out_op_rrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out32(s, m4); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 4, r3); + insn =3D deposit32(insn, 24, 4, r4); + tcg_out32(s, insn); } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 4, r3); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out_r(s, r4); - tcg_out8(s, c5); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 4, r3); + insn =3D deposit32(insn, 24, 4, r4); + insn =3D deposit32(insn, 28, 4, c5); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGReg r5) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out_r(s, r4); - tcg_out_r(s, r5); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 4, r3); + insn =3D deposit32(insn, 24, 4, r4); + insn =3D deposit32(insn, 28, 4, r5); + tcg_out32(s, insn); } #endif =20 +static void tcg_out_ldst(TCGContext *s, TCGOpcode op, TCGReg val, + TCGReg base, intptr_t offset) +{ + stack_bounds_check(base, offset); + if (offset !=3D sextract32(offset, 0, 16)) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); + tcg_out_op_rrr(s, (TCG_TARGET_REG_BITS =3D=3D 32 + ? INDEX_op_add_i32 : INDEX_op_add_i64), + TCG_REG_TMP, TCG_REG_TMP, base); + base =3D TCG_REG_TMP; + offset =3D 0; + } + tcg_out_op_rrs(s, op, val, base, offset); +} + static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, intptr_t offset) { - stack_bounds_check(base, offset); switch (type) { case TCG_TYPE_I32: - tcg_out_op_rrs(s, INDEX_op_ld_i32, val, base, offset); + tcg_out_ldst(s, INDEX_op_ld_i32, val, base, offset); break; #if TCG_TARGET_REG_BITS =3D=3D 64 case TCG_TYPE_I64: - tcg_out_op_rrs(s, INDEX_op_ld_i64, val, base, offset); + tcg_out_ldst(s, INDEX_op_ld_i64, val, base, offset); break; #endif default: @@ -559,22 +495,33 @@ static void tcg_out_movi(TCGContext *s, TCGType type, { switch (type) { case TCG_TYPE_I32: - tcg_out_op_ri(s, INDEX_op_tci_movi_i32, ret, arg); - break; #if TCG_TARGET_REG_BITS =3D=3D 64 + arg =3D (int32_t)arg; + /* fall through */ case TCG_TYPE_I64: - tcg_out_op_rI(s, INDEX_op_tci_movi_i64, ret, arg); - break; #endif + break; default: g_assert_not_reached(); } + + if (arg =3D=3D sextract32(arg, 0, 20)) { + tcg_out_op_ri(s, INDEX_op_tci_movi, ret, arg); + } else { + tcg_insn_unit insn =3D 0; + + new_pool_label(s, arg, 20, s->code_ptr, 0); + insn =3D deposit32(insn, 0, 8, INDEX_op_tci_movl); + insn =3D deposit32(insn, 8, 4, ret); + tcg_out32(s, insn); + } } =20 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { const TCGHelperInfo *info; uint8_t which; + tcg_insn_unit insn =3D 0; =20 info =3D g_hash_table_lookup(helper_table, (gpointer)arg); if (info->cif->rtype =3D=3D &ffi_type_void) { @@ -586,7 +533,11 @@ static void tcg_out_call(TCGContext *s, const tcg_insn= _unit *arg) which =3D 2; } =20 - tcg_out_op_np(s, INDEX_op_call, which, info); + new_pool_l2(s, 20, s->code_ptr, 0, + (uintptr_t)info->func, (uintptr_t)info->cif); + insn =3D deposit32(insn, 0, 8, INDEX_op_call); + insn =3D deposit32(insn, 8, 4, which); + tcg_out32(s, insn); } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -644,8 +595,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, case INDEX_op_st_i32: CASE_64(st32) CASE_64(st) - stack_bounds_check(args[1], args[2]); - tcg_out_op_rrs(s, opc, args[0], args[1], args[2]); + tcg_out_ldst(s, opc, args[0], args[1], args[2]); break; =20 CASE_32_64(add) @@ -738,8 +688,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); } else { - tcg_out_op_rrrrm(s, opc, args[0], args[1], - args[2], args[3], args[4]); + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, args[4]); + tcg_out_op_rrrrr(s, opc, args[0], args[1], + args[2], args[3], TCG_REG_TMP); } break; =20 @@ -787,6 +738,11 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, return arg_ct->ct & TCG_CT_CONST; } =20 +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + memset(p, 0, sizeof(*p) * count); +} + static void tcg_target_init(TCGContext *s) { #if defined(CONFIG_DEBUG_TCG_INTERPRETER) diff --git a/tcg/tci/README b/tcg/tci/README index 9bb7d7a5d3..f72a40a395 100644 --- a/tcg/tci/README +++ b/tcg/tci/README @@ -23,10 +23,12 @@ This is what TCI (Tiny Code Interpreter) does. Like each TCG host frontend, TCI implements the code generator in tcg-target.c.inc, tcg-target.h. Both files are in directory tcg/tci. =20 -The additional file tcg/tci.c adds the interpreter. +The additional file tcg/tci.c adds the interpreter and disassembler. =20 -The bytecode consists of opcodes (same numeric values as those used by -TCG), command length and arguments of variable size and number. +The bytecode consists of opcodes (with only a few exceptions, with +the same same numeric values and semantics as used by TCG), and up +to six arguments packed into a 32-bit integer. See comments in tci.c +for details on the encoding. =20 3) Usage =20 @@ -39,11 +41,6 @@ suggest using this option. Setting it automatically woul= d need additional code in configure which must be fixed when new native TCG implementations are added. =20 -System emulation should work on any 32 or 64 bit host. -User mode emulation might work. Maybe a new linker script (*.ld) -is needed. Byte order might be wrong (on big endian hosts) -and need fixes in configure. - For hosts with native TCG, the interpreter TCI can be enabled by =20 configure --enable-tcg-interpreter @@ -118,13 +115,6 @@ u1 =3D linux-user-test works in the interpreter. These opcodes raise a runtime exception, so it is possible to see where code must be added. =20 -* The pseudo code is not optimized and still ugly. For hosts with special - alignment requirements, it needs some fixes (maybe aligned bytecode - would also improve speed for hosts which support byte alignment). - -* A better disassembler for the pseudo code would be nice (a very primitive - disassembler is included in tcg-target.c.inc). - * It might be useful to have a runtime option which selects the native TCG or TCI, so QEMU would have to include two TCGs. Today, selecting TCI is a configure option, so you need two compilations of QEMU. --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612755546; cv=none; d=zohomail.com; s=zohoarc; b=MiWiaimkiYC4D0YayO92krMOevJzsvXXgb8jJh07bZFeVacficmCiAC7R1lRt87NjkM5+abnnMlE/7QOmwvAEpsDAtlJEQJc1COz6faaw6sUSgNZ4ACRVRkbIiGJtIdzPlPF4kXNLTcxqztHCdNMNbdYHK4ljJPPQw/PeIxNYs4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612755546; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZqOw+gxfHcL+GE2Ru72t2p+WgkIxr/f1vF2n8FMDX2k=; b=a+lmsxTXot0Rdu7lzo4n6MILdZduDjAbd61Aq6sofBLMnGIMGW+FxECQGKmyzXQPxXjMayQHgzMNhobL+LbPorbBYDt9433CvBvnZYFUaiN/tMyGyStBYKQyyJYCXf1mHFmV26KQULwSPF14wAtGqixgXnlmaYJ2N5AIJ0XNlm4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612755546421743.8524164995976; Sun, 7 Feb 2021 19:39:06 -0800 (PST) Received: from localhost ([::1]:56272 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8xOD-0006Yf-8N for importer@patchew.org; Sun, 07 Feb 2021 22:39:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58538) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wSj-00032b-FU for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:41 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:37874) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wSh-0006DE-JO for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:41 -0500 Received: by mail-pl1-x632.google.com with SMTP id e12so7027609pls.4 for ; Sun, 07 Feb 2021 18:39:39 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZqOw+gxfHcL+GE2Ru72t2p+WgkIxr/f1vF2n8FMDX2k=; b=fpaXP0n498QmpOk5TdKJk7Xf7bOydW6kjxtL/2AOifgcn/a4Gle8McvcGBIGNLJ0q/ DVhUoE86sJUKfFDxJWAmg7oZZ3auFv/L22rYW33aoiwVd7QfFTI2YKKzPxV1wT7h5oCH vh3+/tqx5sQ3SPQ8bWFHxmZ08FbHgVcMLSJsrKVDWyZ1Wyj106LAJoe3g8bzuOwVhZPJ cUWc4sl6zU9YSKCODNyrNqAtKd6MPaIjZEkw1OIrTVDx7yqXSWZsB5wAEN9SHF34XrZw fP07PVYuWx5KrX4PNYAKpnCI10jz+kG7argIl7T0jHSlwM6qGXwQnM8v3mOnAK0M7Nfu OKzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZqOw+gxfHcL+GE2Ru72t2p+WgkIxr/f1vF2n8FMDX2k=; b=j46prRWMx9Yq+9QnPC7ePqz4ccViPlpuIwgO2TEmdocmKT7zSpeRWqfBfpbKcVNxVh RlAI77qaCbWig8tSAMYTWl3obgJcJk3ek1TKhUAFv0Vijm2PRKFe/beH3SiQPu2kNYce mxYD6RwPsiXBv5boZLCvmlvCe2ybwJtIp/pytQkZyP9L+rV80a6K7/a/qLPnk/eurF2Y rJMQZBcFx5Bt0CVvQcPnqYxKU79ID9ZMGmgrBfxKsjacRCLF50W8xHDqNfhLDDAGDCQc xoHGoGvAQI2Pg3XLk/Ky01BEb0eN7ln6tN40UiQOxjdKLm19kUFSJ5FJY6Qhsl/9yBjW bl8g== X-Gm-Message-State: AOAM532R0L0kdNOgT0zdkv+EAlOqkmaXokLykSlyM34/qoj9n3Nc1oZR icO+I8Pw1v/SjKiTTONDuxdChbFX+qLavQ== X-Google-Smtp-Source: ABdhPJwjG6B0sKUthLcxA7yRBokmXzatzr/igqRWhLyBdbf5JmxgUX+RfCNCxuSmKsmGJL5yr/lF8A== X-Received: by 2002:a17:902:c3cc:b029:e2:d0cd:4f6e with SMTP id j12-20020a170902c3ccb02900e2d0cd4f6emr5362196plj.77.1612751978244; Sun, 07 Feb 2021 18:39:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 62/70] tcg/tci: Implement goto_ptr Date: Sun, 7 Feb 2021 18:37:44 -0800 Message-Id: <20210208023752.270606-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This operation is critical to staying within the interpretation loop longer, which avoids the overhead of setup and teardown for many TBs. The check in tcg_prologue_init is disabled because TCI does want to use NULL to indicate exit, as opposed to branching to a real epilogue. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-con-set.h | 1 + tcg/tci/tcg-target.h | 2 +- tcg/tcg.c | 2 ++ tcg/tci.c | 19 +++++++++++++++++++ tcg/tci/tcg-target.c.inc | 16 ++++++++++++++++ 5 files changed, 39 insertions(+), 1 deletion(-) diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h index 316730f32c..ae2dc3b844 100644 --- a/tcg/tci/tcg-target-con-set.h +++ b/tcg/tci/tcg-target-con-set.h @@ -9,6 +9,7 @@ * Each operand should be a sequence of constraint letters as defined by * tcg-target-con-str.h; the constraint combination is inclusive or. */ +C_O0_I1(r) C_O0_I2(r, r) C_O0_I3(r, r, r) C_O0_I4(r, r, r, r) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index d953f2ead3..17911d3297 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -86,7 +86,7 @@ #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 -#define TCG_TARGET_HAS_goto_ptr 0 +#define TCG_TARGET_HAS_goto_ptr 1 #define TCG_TARGET_HAS_direct_jump 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 diff --git a/tcg/tcg.c b/tcg/tcg.c index 92aec0d238..ce80adcfbe 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1314,10 +1314,12 @@ void tcg_prologue_init(TCGContext *s) } #endif =20 +#ifndef CONFIG_TCG_INTERPRETER /* Assert that goto_ptr is implemented completely. */ if (TCG_TARGET_HAS_goto_ptr) { tcg_debug_assert(tcg_code_gen_epilogue !=3D NULL); } +#endif } =20 void tcg_func_start(TCGContext *s) diff --git a/tcg/tci.c b/tcg/tci.c index c4f0a7e82d..a6e30d31a9 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -69,6 +69,11 @@ static void tci_args_l(uint32_t insn, const void *tb_ptr= , void **l0) *l0 =3D diff ? (void *)tb_ptr + diff : NULL; } =20 +static void tci_args_r(uint32_t insn, TCGReg *r0) +{ + *r0 =3D extract32(insn, 8, 4); +} + static void tci_args_nl(uint32_t insn, const void *tb_ptr, uint8_t *n0, void **l1) { @@ -748,6 +753,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tb_ptr =3D *(void **)ptr; break; =20 + case INDEX_op_goto_ptr: + tci_args_r(insn, &r0); + ptr =3D (void *)regs[r0]; + if (!ptr) { + return 0; + } + tb_ptr =3D ptr; + break; + case INDEX_op_qemu_ld_i32: if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { tci_args_rrm(insn, &r0, &r1, &oi); @@ -1005,6 +1019,11 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); break; =20 + case INDEX_op_goto_ptr: + tci_args_r(insn, &r0); + info->fprintf_func(info->stream, "%-12s %s", op_name, str_r(r0)); + break; + case INDEX_op_call: tci_args_nl(insn, tb_ptr, &len, &ptr); info->fprintf_func(info->stream, "%-12s %d,%p", op_name, len, ptr= ); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 0df8384be7..db29bc6e54 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -27,6 +27,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { switch (op) { + case INDEX_op_goto_ptr: + return C_O0_I1(r); + case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: @@ -263,6 +266,15 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, = void *p0) tcg_out32(s, insn); } =20 +static void tcg_out_op_r(TCGContext *s, TCGOpcode op, TCGReg r0) +{ + tcg_insn_unit insn =3D 0; + + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + tcg_out32(s, insn); +} + static void tcg_out_op_v(TCGContext *s, TCGOpcode op) { tcg_out32(s, (uint8_t)op); @@ -567,6 +579,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, set_jmp_reset_offset(s, args[0]); break; =20 + case INDEX_op_goto_ptr: + tcg_out_op_r(s, opc, args[0]); + break; + case INDEX_op_br: tcg_out_op_l(s, opc, arg_label(args[0])); break; --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612755704; cv=none; d=zohomail.com; s=zohoarc; b=CrbDFtbNG0tD1IwUqHtRb2E12HBQgAGvDJ7+3k7tTikebiL/uWJW+IjxQ24rAWZWJRmUMGhAlWnbo1R2XaDM9n6+E6+UGsm1ucu9My1gHDehZM1xsUsvLGhUtEFB5JW2cX8sFAZ6J0y5D7dBx9wZUm+EnFIh8tJrlG1mZePGzs4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612755704; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lLuTVZMheh+w94V9lSybCso+88KsI23VfpQyYgw6vik=; b=VcgStkm/ZhMvRidDCo0Bg/0Ij7zqBDZF7mA9UyaBl3dc4Xt4t+wQjCedacTj6TQpjjKYp75BJbto/pj/gVtpl8aX5Ed1QYcDvD8b1hMypmmU6OrQ25KmA639TOEU8xdPKpGsVNGRsxrs3VBH52kFxpBPQ0tUM9g7cwxNj2P4cfI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612755704653402.84080822059343; Sun, 7 Feb 2021 19:41:44 -0800 (PST) Received: from localhost ([::1]:36740 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8xQl-0001gQ-6c for importer@patchew.org; Sun, 07 Feb 2021 22:41:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58562) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wSk-00034u-Ii for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:42 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:55243) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wSi-0006E6-Oe for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:42 -0500 Received: by mail-pj1-x1031.google.com with SMTP id gb24so934678pjb.4 for ; Sun, 07 Feb 2021 18:39:40 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lLuTVZMheh+w94V9lSybCso+88KsI23VfpQyYgw6vik=; b=LKRfmQ6qvJR312Tp5KhXnnlnYoyvf4v91Fe8arlt6ok5omrVDkZTl0w8OAJnUeONv5 I5cXEI+4bWpL+W1kKHXJszPnl7XwLsLlGWmQOz5Xj4k2cZfYLpaM+oWTMiiQ4tGmD6sR nkvcIb9gHHknOqlw3XW05pr0vKGR1bPPDJjNsuy06XMmKSFqjRXsLQRAo4ewV8naFivg nKWVr8bvvNX/zs4h96sOU2rDnfV2hbCxJd7OcrlQhfxeSXOpWR+ZArmfjXUEUZLgyHS4 2OCYG7nFpU7m9HYONP/W+Vceynd8rrTFYzExiw8O7CCn+oIwNbQHyj9VQPbvBET/AHaA K7KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lLuTVZMheh+w94V9lSybCso+88KsI23VfpQyYgw6vik=; b=FhiKJRLP2cHYw6xXhdudYfK5fOPpUzVyspXpcxP5ZlBgpzLr1epVG3MqwIsr2kbezn LTPwGXmgxnd+95I5wEiUC4NH1Fres8ztZ89+v2yH2ox0nj9mbET7EYLHxq7qF0FS0Pme WhJNYlf4y74sQ+dMzchPC5QpMzz5eMXdYbBkZe7aXYPAX3V8KynHmRaz1RM35bCQbZSD AQ+FBH8isbdM1if+i5ZofEGW/O2Y5gz4lgjaXbUQ+5eT+LQkBPDiFK4DGlKeQb7dOE2a YtYAV7MrWU1XckUURtAGgWtbo5VbKsIqCFmnbYE2C+47kLWv8t1qLPWwPeNi/2KQVc1y Dwrw== X-Gm-Message-State: AOAM531pPrxx0tHMHtZAhnl+YwuVEvdtynX6by7cNnRu+LZW0Ku+onDj 6TFxUrGB/ls7MK1IX7W7Ocz4z3nZif/wUQ== X-Google-Smtp-Source: ABdhPJxlTru1X5czcaKutWxosbabcReZIleXknUHmERg17+J1rQixRnXHkLaagq7c89+zAcv//EMBw== X-Received: by 2002:a17:902:bb87:b029:e1:d1f:2736 with SMTP id m7-20020a170902bb87b02900e10d1f2736mr14231919pls.1.1612751979458; Sun, 07 Feb 2021 18:39:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 63/70] tcg/tci: Implement movcond Date: Sun, 7 Feb 2021 18:37:45 -0800 Message-Id: <20210208023752.270606-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" When this opcode is not available in the backend, tcg middle-end will expand this as a series of 5 opcodes. So implementing this saves bytecode space. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 4 ++-- tcg/tci.c | 16 +++++++++++++++- tcg/tci/tcg-target.c.inc | 10 +++++++--- 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 17911d3297..f53773a555 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -82,7 +82,7 @@ #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_orc_i32 0 #define TCG_TARGET_HAS_rot_i32 1 -#define TCG_TARGET_HAS_movcond_i32 0 +#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 @@ -119,7 +119,7 @@ #define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_orc_i64 0 #define TCG_TARGET_HAS_rot_i64 1 -#define TCG_TARGET_HAS_movcond_i64 0 +#define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_add2_i32 0 #define TCG_TARGET_HAS_sub2_i32 0 diff --git a/tcg/tci.c b/tcg/tci.c index a6e30d31a9..2a39f8f5a0 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -169,6 +169,7 @@ static void tci_args_rrrr(uint32_t insn, *r2 =3D extract32(insn, 16, 4); *r3 =3D extract32(insn, 20, 4); } +#endif =20 static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) @@ -181,6 +182,7 @@ static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, = TCGReg *r1, *c5 =3D extract32(insn, 28, 4); } =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { @@ -431,6 +433,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] =3D tci_compare32(regs[r1], regs[r2], condition); break; + case INDEX_op_movcond_i32: + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); + tmp32 =3D tci_compare32(regs[r1], regs[r2], condition); + regs[r0] =3D regs[tmp32 ? r3 : r4]; + break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); @@ -443,6 +450,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] =3D tci_compare64(regs[r1], regs[r2], condition); break; + case INDEX_op_movcond_i64: + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); + tmp32 =3D tci_compare64(regs[r1], regs[r2], condition); + regs[r0] =3D regs[tmp32 ? r3 : r4]; + break; #endif CASE_32_64(mov) tci_args_rr(insn, &r0, &r1); @@ -1148,7 +1160,8 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) op_name, str_r(r0), str_r(r1), str_r(r2), pos, = len); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", @@ -1156,6 +1169,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) str_r(r3), str_r(r4), str_c(c)); break; =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_mulu2_i32: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index db29bc6e54..a0c458a60a 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -133,9 +133,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpco= de op) return C_O0_I4(r, r, r, r); case INDEX_op_mulu2_i32: return C_O2_I2(r, r, r, r); +#endif + + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: return C_O1_I4(r, r, r, r, r); -#endif =20 case INDEX_op_qemu_ld_i32: return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS @@ -419,6 +422,7 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, insn =3D deposit32(insn, 20, 4, r3); tcg_out32(s, insn); } +#endif =20 static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, @@ -436,6 +440,7 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode = op, tcg_out32(s, insn); } =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGReg r5) @@ -591,12 +596,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, tcg_out_op_rrrc(s, opc, args[0], args[1], args[2], args[3]); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 + CASE_32_64(movcond) case INDEX_op_setcond2_i32: tcg_out_op_rrrrrc(s, opc, args[0], args[1], args[2], args[3], args[4], args[5]); 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rhMhsBiepdz6ZgRnVQ9WJVuiU6dgvoZgG9ax0hIWeII=; b=gf+qE9Phnjphx4PsF+uWOpAKIUaBQXBdb94rf2iuNFiGiWNsxc5bKJTCgng8c++4xz TNQ2Jox3CxqkdDbanm6uwfb5HxqzhsZPdKupaTt6kF59RqZ1bv9MXjYb9pmfCGypvVHB BKS7LUuTX1pyWjSCbxTk3AgunbxbKLeHyBka59APrb+LAJoTWhrLu0bB2zzt4p8TweSW 9613to/za00QAx0WRdNTC2bLoTveCEOzS39wFpa1NR4ZpwzH2Ap77bTV2ngrjIf+p40v ewZ5xUCclZNvUHVM/SNcaYkXLHu30PeXpOWUClKHLb01xbX8BCHJAomvrkWq9qUTyi4J v/1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rhMhsBiepdz6ZgRnVQ9WJVuiU6dgvoZgG9ax0hIWeII=; b=UfklTgcFR88tzxbGoyR1JdWiTP0S+9MzGiN3lui+/GUXBucBImWJGMGZpdWiqNi77T sUnP0a3QQWWiPjhlM1xDeSw6wqQ5T2Slha2WqGuDpbopXausrxli/MTzjZLVF9/2Tdo3 7oUhdCTiG48IJToEdFky4p8mntBfiPN8h0n2laTw1Mk4He/GcSpXOJeCt895LpsXgzGC MU8ClDEzsHH2UMckj77AyKfbOABQ2yHFFJEafta9YXJD+FpXOeB1LdTVVDjwq6L9bSYw ADPBRig3dTzfIH/evgov+okbofL0wELiU4SIE8pTav1CocLoHhLGY9gPR3APNR35Uc0M nd0g== X-Gm-Message-State: AOAM531FjLQ9p3QH3OJkP80ekd0H7d7ESMfkIsvhvYBpfo0hEpj6TUxO Z6IuSsCylvyLyD16cz34sZ7PbNKT2ElVXg== X-Google-Smtp-Source: ABdhPJzNfj88yFN5jxAIl8c7nknTLIGis6hUF3mpWZ/r9OkOOMQKiETRubaKnQkxNIiExzSzAvbVtw== X-Received: by 2002:a63:1458:: with SMTP id 24mr15452406pgu.441.1612751980458; Sun, 07 Feb 2021 18:39:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 64/70] tcg/tci: Implement andc, orc, eqv, nand, nor Date: Sun, 7 Feb 2021 18:37:46 -0800 Message-Id: <20210208023752.270606-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These were already present in tcg-target.c.inc, but not in the interpreter. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 20 ++++++++++---------- tcg/tci.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 10 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index f53773a555..5945272a43 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -67,20 +67,20 @@ #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 #define TCG_TARGET_HAS_ext16u_i32 1 -#define TCG_TARGET_HAS_andc_i32 0 +#define TCG_TARGET_HAS_andc_i32 1 #define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_extract_i32 0 #define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_extract2_i32 0 -#define TCG_TARGET_HAS_eqv_i32 0 -#define TCG_TARGET_HAS_nand_i32 0 -#define TCG_TARGET_HAS_nor_i32 0 +#define TCG_TARGET_HAS_eqv_i32 1 +#define TCG_TARGET_HAS_nand_i32 1 +#define TCG_TARGET_HAS_nor_i32 1 #define TCG_TARGET_HAS_clz_i32 0 #define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_ctpop_i32 0 #define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_not_i32 1 -#define TCG_TARGET_HAS_orc_i32 0 +#define TCG_TARGET_HAS_orc_i32 1 #define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_muls2_i32 0 @@ -108,16 +108,16 @@ #define TCG_TARGET_HAS_ext8u_i64 1 #define TCG_TARGET_HAS_ext16u_i64 1 #define TCG_TARGET_HAS_ext32u_i64 1 -#define TCG_TARGET_HAS_andc_i64 0 -#define TCG_TARGET_HAS_eqv_i64 0 -#define TCG_TARGET_HAS_nand_i64 0 -#define TCG_TARGET_HAS_nor_i64 0 +#define TCG_TARGET_HAS_andc_i64 1 +#define TCG_TARGET_HAS_eqv_i64 1 +#define TCG_TARGET_HAS_nand_i64 1 +#define TCG_TARGET_HAS_nor_i64 1 #define TCG_TARGET_HAS_clz_i64 0 #define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_ctpop_i64 0 #define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_not_i64 1 -#define TCG_TARGET_HAS_orc_i64 0 +#define TCG_TARGET_HAS_orc_i64 1 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_muls2_i64 0 diff --git a/tcg/tci.c b/tcg/tci.c index 2a39f8f5a0..9c17947e6b 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -540,6 +540,36 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] ^ regs[r2]; break; +#if TCG_TARGET_HAS_andc_i32 || TCG_TARGET_HAS_andc_i64 + CASE_32_64(andc) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] & ~regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_orc_i32 || TCG_TARGET_HAS_orc_i64 + CASE_32_64(orc) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] | ~regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64 + CASE_32_64(eqv) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D ~(regs[r1] ^ regs[r2]); + break; +#endif +#if TCG_TARGET_HAS_nand_i32 || TCG_TARGET_HAS_nand_i64 + CASE_32_64(nand) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D ~(regs[r1] & regs[r2]); + break; +#endif +#if TCG_TARGET_HAS_nor_i32 || TCG_TARGET_HAS_nor_i64 + CASE_32_64(nor) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D ~(regs[r1] | regs[r2]); + break; +#endif =20 /* Arithmetic operations (32 bit). */ =20 @@ -1130,6 +1160,16 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + case INDEX_op_eqv_i32: + case INDEX_op_eqv_i64: + case INDEX_op_nand_i32: + case INDEX_op_nand_i64: + case INDEX_op_nor_i32: + case INDEX_op_nor_i64: case INDEX_op_div_i32: case INDEX_op_div_i64: case INDEX_op_rem_i32: --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4GLVuYuzRltqq/bjvGdZN73wsp3XyCbMAEbRMKz6MNY=; b=IvX2U/cyYMf5UxmfLMLBMLrnCjYshs6y7lIRFTMklKfTk5pJ5Xm284tmz0/m3j1k0Y NKvym8GN8IJHwpwU3kzDLFjamEmr8cjzuLaYb3VHWpYscZ38D4MT/RSSP7OUGOi5lCOz G/1wBQa26AW2CGcwjsXsEpQm2x3bvbmjsNYyfqVol+cfGXBsev2z5XmtliQmbtkzyIL5 18L++nbEjbhw9Etr1LdVXyRIko5gc2BUTvrbiC5pZqWvpWeDfX9LA7NYKLvJbMHw3TJD D7MB6+yh4EUSS4NQFjqyLd7B2RJeRtSTS1qJeXb5cch1dXw2Jr2SR3Hv4bNKXqdqrbXX iFrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4GLVuYuzRltqq/bjvGdZN73wsp3XyCbMAEbRMKz6MNY=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 8 ++++---- tcg/tci.c | 42 ++++++++++++++++++++++++++++++++++++++++ tcg/tci/tcg-target.c.inc | 32 ++++++++++++++++++++++++++++++ 3 files changed, 78 insertions(+), 4 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 5945272a43..60b67b196b 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -69,8 +69,8 @@ #define TCG_TARGET_HAS_ext16u_i32 1 #define TCG_TARGET_HAS_andc_i32 1 #define TCG_TARGET_HAS_deposit_i32 1 -#define TCG_TARGET_HAS_extract_i32 0 -#define TCG_TARGET_HAS_sextract_i32 0 +#define TCG_TARGET_HAS_extract_i32 1 +#define TCG_TARGET_HAS_sextract_i32 1 #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_eqv_i32 1 #define TCG_TARGET_HAS_nand_i32 1 @@ -97,8 +97,8 @@ #define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_deposit_i64 1 -#define TCG_TARGET_HAS_extract_i64 0 -#define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_extract_i64 1 +#define TCG_TARGET_HAS_sextract_i64 1 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_rem_i64 1 diff --git a/tcg/tci.c b/tcg/tci.c index 9c17947e6b..831a3bb97e 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -122,6 +122,15 @@ static void tci_args_rrs(uint32_t insn, TCGReg *r0, TC= GReg *r1, int32_t *i2) *i2 =3D sextract32(insn, 16, 16); } =20 +static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, + uint8_t *i2, uint8_t *i3) +{ + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *i2 =3D extract32(insn, 16, 6); + *i3 =3D extract32(insn, 22, 6); +} + static void tci_args_rrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { @@ -619,6 +628,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] =3D deposit32(regs[r1], pos, len, regs[r2]); break; +#endif +#if TCG_TARGET_HAS_extract_i32 + case INDEX_op_extract_i32: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] =3D extract32(regs[r1], pos, len); + break; +#endif +#if TCG_TARGET_HAS_sextract_i32 + case INDEX_op_sextract_i32: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] =3D sextract32(regs[r1], pos, len); + break; #endif case INDEX_op_brcond_i32: tci_args_rl(insn, tb_ptr, &r0, &ptr); @@ -759,6 +780,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] =3D deposit64(regs[r1], pos, len, regs[r2]); break; +#endif +#if TCG_TARGET_HAS_extract_i64 + case INDEX_op_extract_i64: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] =3D extract64(regs[r1], pos, len); + break; +#endif +#if TCG_TARGET_HAS_sextract_i64 + case INDEX_op_sextract_i64: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] =3D sextract64(regs[r1], pos, len); + break; #endif case INDEX_op_brcond_i64: tci_args_rl(insn, tb_ptr, &r0, &ptr); @@ -1200,6 +1233,15 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) op_name, str_r(r0), str_r(r1), str_r(r2), pos, = len); break; =20 + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + case INDEX_op_sextract_i32: + case INDEX_op_sextract_i64: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + info->fprintf_func(info->stream, "%-12s %s,%s,%d,%d", + op_name, str_r(r0), str_r(r1), pos, len); + break; + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index a0c458a60a..cedd0328df 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -63,6 +63,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode= op) case INDEX_op_bswap32_i32: case INDEX_op_bswap32_i64: case INDEX_op_bswap64_i64: + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + case INDEX_op_sextract_i32: + case INDEX_op_sextract_i64: return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: @@ -352,6 +356,21 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, tcg_out32(s, insn); } =20 +static void tcg_out_op_rrbb(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, uint8_t b2, uint8_t b3) +{ + tcg_insn_unit insn =3D 0; + + tcg_debug_assert(b2 =3D=3D extract32(b2, 0, 6)); + tcg_debug_assert(b3 =3D=3D extract32(b3, 0, 6)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 6, b2); + insn =3D deposit32(insn, 22, 6, b3); + tcg_out32(s, insn); +} + static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { @@ -653,6 +672,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, } break; =20 + CASE_32_64(extract) /* Optional (TCG_TARGET_HAS_extract_*). */ + CASE_32_64(sextract) /* Optional (TCG_TARGET_HAS_sextract_*). */ + { + TCGArg pos =3D args[2], len =3D args[3]; + TCGArg max =3D tcg_op_defs[opc].flags & TCG_OPF_64BIT ? 64 : 3= 2; + + tcg_debug_assert(pos < max); + tcg_debug_assert(pos + len <=3D max); + + tcg_out_op_rrbb(s, opc, args[0], args[1], pos, len); + } + break; + CASE_32_64(brcond) tcg_out_op_rrrc(s, (opc =3D=3D INDEX_op_brcond_i32 ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 12 +++++------ tcg/tci.c | 44 ++++++++++++++++++++++++++++++++++++++++ tcg/tci/tcg-target.c.inc | 9 ++++++++ 3 files changed, 59 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 60b67b196b..59859bd8a6 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -75,9 +75,9 @@ #define TCG_TARGET_HAS_eqv_i32 1 #define TCG_TARGET_HAS_nand_i32 1 #define TCG_TARGET_HAS_nor_i32 1 -#define TCG_TARGET_HAS_clz_i32 0 -#define TCG_TARGET_HAS_ctz_i32 0 -#define TCG_TARGET_HAS_ctpop_i32 0 +#define TCG_TARGET_HAS_clz_i32 1 +#define TCG_TARGET_HAS_ctz_i32 1 +#define TCG_TARGET_HAS_ctpop_i32 1 #define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_orc_i32 1 @@ -112,9 +112,9 @@ #define TCG_TARGET_HAS_eqv_i64 1 #define TCG_TARGET_HAS_nand_i64 1 #define TCG_TARGET_HAS_nor_i64 1 -#define TCG_TARGET_HAS_clz_i64 0 -#define TCG_TARGET_HAS_ctz_i64 0 -#define TCG_TARGET_HAS_ctpop_i64 0 +#define TCG_TARGET_HAS_clz_i64 1 +#define TCG_TARGET_HAS_ctz_i64 1 +#define TCG_TARGET_HAS_ctpop_i64 1 #define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_orc_i64 1 diff --git a/tcg/tci.c b/tcg/tci.c index 831a3bb97e..35f2c4bfbb 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -598,6 +598,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint32_t)regs[r1] % (uint32_t)regs[r2]; break; +#if TCG_TARGET_HAS_clz_i32 + case INDEX_op_clz_i32: + tci_args_rrr(insn, &r0, &r1, &r2); + tmp32 =3D regs[r1]; + regs[r0] =3D tmp32 ? clz32(tmp32) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctz_i32 + case INDEX_op_ctz_i32: + tci_args_rrr(insn, &r0, &r1, &r2); + tmp32 =3D regs[r1]; + regs[r0] =3D tmp32 ? ctz32(tmp32) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctpop_i32 + case INDEX_op_ctpop_i32: + tci_args_rr(insn, &r0, &r1); + regs[r0] =3D ctpop32(regs[r1]); + break; +#endif =20 /* Shift/rotate operations (32 bit). */ =20 @@ -750,6 +770,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint64_t)regs[r1] % (uint64_t)regs[r2]; break; +#if TCG_TARGET_HAS_clz_i64 + case INDEX_op_clz_i64: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] ? clz64(regs[r1]) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctz_i64 + case INDEX_op_ctz_i64: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] ? ctz64(regs[r1]) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctpop_i64 + case INDEX_op_ctpop_i64: + tci_args_rr(insn, &r0, &r1); + regs[r0] =3D ctpop64(regs[r1]); + break; +#endif =20 /* Shift/rotate operations (64 bit). */ =20 @@ -1176,6 +1214,8 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) case INDEX_op_not_i64: case INDEX_op_neg_i32: case INDEX_op_neg_i64: + case INDEX_op_ctpop_i32: + case INDEX_op_ctpop_i64: tci_args_rr(insn, &r0, &r1); info->fprintf_func(info->stream, "%-12s %s,%s", op_name, str_r(r0), str_r(r1)); @@ -1221,6 +1261,10 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: + case INDEX_op_clz_i32: + case INDEX_op_clz_i64: + case INDEX_op_ctz_i32: + case INDEX_op_ctz_i64: tci_args_rrr(insn, &r0, &r1, &r2); info->fprintf_func(info->stream, "%-12s %s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2)); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index cedd0328df..664d715440 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -67,6 +67,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode = op) case INDEX_op_extract_i64: case INDEX_op_sextract_i32: case INDEX_op_sextract_i64: + case INDEX_op_ctpop_i32: + case INDEX_op_ctpop_i64: return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: @@ -122,6 +124,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpco= de op) case INDEX_op_setcond_i64: case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: + case INDEX_op_clz_i32: + case INDEX_op_clz_i64: + case INDEX_op_ctz_i32: + case INDEX_op_ctz_i64: return C_O1_I2(r, r, r); =20 case INDEX_op_brcond_i32: @@ -657,6 +663,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(clz) /* Optional (TCG_TARGET_HAS_clz_*). */ + CASE_32_64(ctz) /* Optional (TCG_TARGET_HAS_ctz_*). */ tcg_out_op_rrr(s, opc, args[0], args[1], args[2]); break; =20 @@ -705,6 +713,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ + CASE_32_64(ctpop) /* Optional (TCG_TARGET_HAS_ctpop_*). */ tcg_out_op_rr(s, opc, args[0], args[1]); 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=K7frB2t4HRQY2QCd4vmgctpTB+qUKaU+sWJuOgxV4RM=; b=AVIzDXYF05gFR0X4DPktnk5vfX59KZ/gAZhte9VnTc4KWH+4LhfE/mXN7CrlXsgKtB EqZdNFE+ksZA7u+Yn3m9KG6G4tsi1Y+HKyNudvXt3XlEVZED8qeIBekP7MmNtVLlCcrV UHGMQu4kEXxFUEhimwKGQpx8zwicIqaXz92wwlGtZHxOHMLCLuQpLkW3KrDhzJ8FAPXG U+rcjfwrPsR+ntwVffkg/MoaIc76+lUEa2ylTawp3T4kPC56E+am/3g6ay1fIDulD5Vw UQiYbt5BvGjXIZZ0ahpggxv9/iL8qUbhnNmfgi5He07ffXn9Xq7Yfa+94ZtILCmwY2Xx BCMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K7frB2t4HRQY2QCd4vmgctpTB+qUKaU+sWJuOgxV4RM=; b=ULG6g2vGRKrZxGn136Nsd0m2N1PJfPCZXN/KPmfN77oygPaCMMlfI1tq6vqOomupal QXA//DWlHr6uRM4I5M/PBkh3CSrBuyVK5yIHJL6IvMIxaTD/AnSVhT+gQE+i2B3W6CXJ Yq0/RUc5Y0Yso5xmPZ0rDXfZbKfAqIAghJDQ9ucUvfCZ/1/Xinsvjay/QcM94fjzUsym u3ox1OfUuCQjzxuw7nzh+KJ9b1PIg9Tx9W+VvK9z8EceJ5hJLkLAoWplLZ/Usgo89RUn uihZ1iPKHiDrYNUiLMzm1Hn5/qL7D2FnO1qKmKfmDTRr6NctViff51LJWUIT5FzGCooo WGdA== X-Gm-Message-State: AOAM530Lff+rO4Qdb3rBy7FF5QZeOAMvCttt5vJNjpPo6Ei9h4ASLe3B hiaklh0QbZFDQKFv3E6ZZjGiYI3g7qkJrA== X-Google-Smtp-Source: ABdhPJwCxEEnEwJRzND1WHP674UNMT1WYfAow+tFDBNB6XttEURoJ+j8SqjCCh17YOldijOwKDaaHw== X-Received: by 2002:a62:16cb:0:b029:1da:358c:4338 with SMTP id 194-20020a6216cb0000b02901da358c4338mr8477786pfw.36.1612751983720; Sun, 07 Feb 2021 18:39:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 67/70] tcg/tci: Implement mulu2, muls2 Date: Sun, 7 Feb 2021 18:37:49 -0800 Message-Id: <20210208023752.270606-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We already had mulu2_i32 for a 32-bit host; expand this to 64-bit hosts as well. The muls2_i32 and the 64-bit opcodes are new. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 8 ++++---- tcg/tci.c | 35 +++++++++++++++++++++++++++++------ tcg/tci/tcg-target.c.inc | 16 ++++++++++------ 3 files changed, 43 insertions(+), 16 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 59859bd8a6..71a44bbfb0 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -83,7 +83,7 @@ #define TCG_TARGET_HAS_orc_i32 1 #define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 -#define TCG_TARGET_HAS_muls2_i32 0 +#define TCG_TARGET_HAS_muls2_i32 1 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 @@ -120,13 +120,13 @@ #define TCG_TARGET_HAS_orc_i64 1 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 -#define TCG_TARGET_HAS_muls2_i64 0 +#define TCG_TARGET_HAS_muls2_i64 1 #define TCG_TARGET_HAS_add2_i32 0 #define TCG_TARGET_HAS_sub2_i32 0 -#define TCG_TARGET_HAS_mulu2_i32 0 +#define TCG_TARGET_HAS_mulu2_i32 1 #define TCG_TARGET_HAS_add2_i64 0 #define TCG_TARGET_HAS_sub2_i64 0 -#define TCG_TARGET_HAS_mulu2_i64 0 +#define TCG_TARGET_HAS_mulu2_i64 1 #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 #else diff --git a/tcg/tci.c b/tcg/tci.c index 35f2c4bfbb..5d83b2d957 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -39,7 +39,7 @@ __thread uintptr_t tci_tb_ptr; static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, uint32_t low_index, uint64_t value) { - regs[low_index] =3D value; + regs[low_index] =3D (uint32_t)value; regs[high_index] =3D value >> 32; } =20 @@ -169,7 +169,6 @@ static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, T= CGReg *r1, *r4 =3D extract32(insn, 24, 4); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) { @@ -178,7 +177,6 @@ static void tci_args_rrrr(uint32_t insn, *r2 =3D extract32(insn, 16, 4); *r3 =3D extract32(insn, 20, 4); } -#endif =20 static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) @@ -680,11 +678,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, T2 =3D tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; +#endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ +#if TCG_TARGET_HAS_mulu2_i32 case INDEX_op_mulu2_i32: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); - tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); + tmp64 =3D (uint64_t)(uint32_t)regs[r2] * (uint32_t)regs[r3]; + tci_write_reg64(regs, r1, r0, tmp64); break; -#endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ +#endif +#if TCG_TARGET_HAS_muls2_i32 + case INDEX_op_muls2_i32: + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); + tmp64 =3D (int64_t)(int32_t)regs[r2] * (int32_t)regs[r3]; + tci_write_reg64(regs, r1, r0, tmp64); + break; +#endif #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) tci_args_rr(insn, &r0, &r1); @@ -788,6 +796,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, regs[r0] =3D ctpop64(regs[r1]); break; #endif +#if TCG_TARGET_HAS_mulu2_i64 + case INDEX_op_mulu2_i64: + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); + mulu64(®s[r0], ®s[r1], regs[r2], regs[r3]); + break; +#endif +#if TCG_TARGET_HAS_muls2_i64 + case INDEX_op_muls2_i64: + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); + muls64(®s[r0], ®s[r1], regs[r2], regs[r3]); + break; +#endif =20 /* Shift/rotate operations (64 bit). */ =20 @@ -1295,14 +1315,17 @@ int print_insn_tci(bfd_vma addr, disassemble_info *= info) str_r(r3), str_r(r4), str_c(c)); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_mulu2_i32: + case INDEX_op_mulu2_i64: + case INDEX_op_muls2_i32: + case INDEX_op_muls2_i64: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3)); break; =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 664d715440..eb48633fba 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -141,10 +141,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) return C_O2_I4(r, r, r, r, r, r); case INDEX_op_brcond2_i32: return C_O0_I4(r, r, r, r); - case INDEX_op_mulu2_i32: - return C_O2_I2(r, r, r, r); #endif =20 + case INDEX_op_mulu2_i32: + case INDEX_op_mulu2_i64: + case INDEX_op_muls2_i32: + case INDEX_op_muls2_i64: + return C_O2_I2(r, r, r, r); + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: @@ -434,7 +438,6 @@ static void tcg_out_op_rrrrr(TCGContext *s, TCGOpcode o= p, TCGReg r0, tcg_out32(s, insn); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) { @@ -447,7 +450,6 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, insn =3D deposit32(insn, 20, 4, r3); tcg_out32(s, insn); } -#endif =20 static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, @@ -728,10 +730,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, args[0], args[1], args[2], args[3], args[4]); tcg_out_op_rl(s, INDEX_op_brcond_i32, TCG_REG_TMP, arg_label(args[= 5])); break; - case INDEX_op_mulu2_i32: +#endif + + CASE_32_64(mulu2) + CASE_32_64(muls2) tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); break; -#endif =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_st_i32: --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ykwqi1nfU63kykOjWC2hHHptQCv8OjjZ7CWKjmVZrJc=; b=yMRYjECCSY/WyYR8sHSDnhgLIj9Yl8zksb42z0VOXcXz/CJViX+Gx+9RQz/F+Q2QmW j3t2BUgoAAQWR+iMkPmq1wLDRlIef911u+2gOQbvogUQ/zaKKLjQWhDhqtCv9MPye8aV CKt5SRUudAFzqyG5ZzAsdNyvqm8XyMKGq9wARSxWFqk9Hl6bdwHrdkEc0oS8pBx0FWqJ +e9MvNvETqL1plrBUSgz1qS81R22mkRGX9tT93uhi81S9Ku3ytU0119/Y8nDPStkfJMo GplEUKfVXc0YbKmC9HJRFcWdCjo4mRLEQqAfRk6Z9hnFQiSWeWGosO+PPX/jDpPRBCJ1 XhoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ykwqi1nfU63kykOjWC2hHHptQCv8OjjZ7CWKjmVZrJc=; b=t05Siufw/S7fkbygtm/bx12C3PIhJReiv0N8TZr+Nt4tNXWxDciCTFJn9+rb6JAtzC Lu4q6PbyD6amgRQOn4iU9kk3rzNLSPIKY7Cj8e4CvZZLp+MEeqVoCT2sifDuykhTFB/g e7eQC/UhYDuIzYSYbkn8yrPGasgRpympHMYl9qi4Kq4brl4YT5nCQhTjlaxus9N/OP3H LnCIyxgj3HyRm0C0bzm8L8itlqPhp1FvjX7B10lufCjZWOQo1QAB7VnsSzYrH6fkBKHR 1lJqYvV9Omz3LH5z4PdmFYisWQZxiCPIKiSt2pGYluAOCNCSxlTGE+dY6uRbOn1lhDZB 22jw== X-Gm-Message-State: AOAM532c3Dv5QooAh15sdN5ktd2kf21V/rTF2oCF4FqWwNScGAxMXU7+ xaMkZVsE3WxEm7ReKxkXGhUl98W1apIXmA== X-Google-Smtp-Source: ABdhPJw6Aj9sPEyE10DqiFcVAjHUnX4+crJZv/8UZWRPhq8c3hW7l05kTJQohWnmTs2YLmb/msNrIw== X-Received: by 2002:a63:1865:: with SMTP id 37mr14980337pgy.206.1612751984750; Sun, 07 Feb 2021 18:39:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 68/70] tcg/tci: Implement add2, sub2 Date: Sun, 7 Feb 2021 18:37:50 -0800 Message-Id: <20210208023752.270606-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We already had the 32-bit versions for a 32-bit host; expand this to 64-bit hosts as well. The 64-bit opcodes are new. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 8 ++++---- tcg/tci.c | 40 ++++++++++++++++++++++++++-------------- tcg/tci/tcg-target.c.inc | 15 ++++++++------- 3 files changed, 38 insertions(+), 25 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 71a44bbfb0..515b3c7a56 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -121,11 +121,11 @@ #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_muls2_i64 1 -#define TCG_TARGET_HAS_add2_i32 0 -#define TCG_TARGET_HAS_sub2_i32 0 +#define TCG_TARGET_HAS_add2_i32 1 +#define TCG_TARGET_HAS_sub2_i32 1 #define TCG_TARGET_HAS_mulu2_i32 1 -#define TCG_TARGET_HAS_add2_i64 0 -#define TCG_TARGET_HAS_sub2_i64 0 +#define TCG_TARGET_HAS_add2_i64 1 +#define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_mulu2_i64 1 #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 diff --git a/tcg/tci.c b/tcg/tci.c index 5d83b2d957..ee16142f48 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -189,7 +189,6 @@ static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, = TCGReg *r1, *c5 =3D extract32(insn, 28, 4); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { @@ -200,7 +199,6 @@ static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, = TCGReg *r1, *r4 =3D extract32(insn, 24, 4); *r5 =3D extract32(insn, 28, 4); } -#endif =20 static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { @@ -368,17 +366,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, for (;;) { uint32_t insn; TCGOpcode opc; - TCGReg r0, r1, r2, r3, r4; + TCGReg r0, r1, r2, r3, r4, r5; tcg_target_ulong t1; TCGCond condition; target_ulong taddr; uint8_t pos, len; uint32_t tmp32; uint64_t tmp64; -#if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r5; uint64_t T1, T2; -#endif TCGMemOpIdx oi; int32_t ofs; void *ptr; @@ -665,20 +660,22 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tb_ptr =3D ptr; } break; -#if TCG_TARGET_REG_BITS =3D=3D 32 +#if TCG_TARGET_REG_BITS =3D=3D 32 || TCG_TARGET_HAS_add2_i32 case INDEX_op_add2_i32: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 =3D tci_uint64(regs[r3], regs[r2]); T2 =3D tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 + T2); break; +#endif +#if TCG_TARGET_REG_BITS =3D=3D 32 || TCG_TARGET_HAS_sub2_i32 case INDEX_op_sub2_i32: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 =3D tci_uint64(regs[r3], regs[r2]); T2 =3D tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; -#endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ +#endif #if TCG_TARGET_HAS_mulu2_i32 case INDEX_op_mulu2_i32: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); @@ -808,6 +805,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, muls64(®s[r0], ®s[r1], regs[r2], regs[r3]); break; #endif +#if TCG_TARGET_HAS_add2_i64 + case INDEX_op_add2_i64: + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); + T1 =3D regs[r2] + regs[r4]; + T2 =3D regs[r3] + regs[r5] + (T1 < regs[r2]); + regs[r0] =3D T1; + regs[r1] =3D T2; + break; +#endif +#if TCG_TARGET_HAS_add2_i64 + case INDEX_op_sub2_i64: + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); + T1 =3D regs[r2] - regs[r4]; + T2 =3D regs[r3] - regs[r5] - (regs[r2] < regs[r4]); + regs[r0] =3D T1; + regs[r1] =3D T2; + break; +#endif =20 /* Shift/rotate operations (64 bit). */ =20 @@ -1124,10 +1139,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) const char *op_name; uint32_t insn; TCGOpcode op; - TCGReg r0, r1, r2, r3, r4; -#if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r5; -#endif + TCGReg r0, r1, r2, r3, r4, r5; tcg_target_ulong i1; int32_t s2; TCGCond c; @@ -1325,15 +1337,15 @@ int print_insn_tci(bfd_vma addr, disassemble_info *= info) str_r(r2), str_r(r3)); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: + case INDEX_op_add2_i64: case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3), str_r(r4), str_r(r5)); break; -#endif =20 case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index eb48633fba..9b2e2c32a1 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -134,11 +134,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_brcond_i64: return C_O0_I2(r, r); =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 - /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */ case INDEX_op_add2_i32: + case INDEX_op_add2_i64: case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: return C_O2_I4(r, r, r, r, r, r); + +#if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_brcond2_i32: return C_O0_I4(r, r, r, r); #endif @@ -467,7 +469,6 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode = op, tcg_out32(s, insn); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGReg r5) @@ -483,7 +484,6 @@ static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode = op, insn =3D deposit32(insn, 28, 4, r5); tcg_out32(s, insn); } -#endif =20 static void tcg_out_ldst(TCGContext *s, TCGOpcode op, TCGReg val, TCGReg base, intptr_t offset) @@ -719,12 +719,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, tcg_out_op_rr(s, opc, args[0], args[1]); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 - case INDEX_op_add2_i32: - case INDEX_op_sub2_i32: + CASE_32_64(add2) + CASE_32_64(sub2) tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2], args[3], args[4], args[5]); break; + +#if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_brcond2_i32: tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, TCG_REG_TMP, args[0], args[1], args[2], args[3], args[4]); --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612754912; cv=none; d=zohomail.com; s=zohoarc; b=Heo8T1Loz8a57A/8ABC/p3OUo2GH/Tw/g4VgFyNocA/dcHlmLnnYapXWW11f2gduxcEpkT3A//GOKp7jplpKvWnujVaDVLTt4X8U6ak87JZXCEYehvo2KR5gPutr0TqRdnsZN5zKRvYL0dfrNv684w5WJingSKb7Z/whTg96BgM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612754912; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qzll/P0wtV+vx8SpfL7JfV6f6jbtOfqckGjdgSv5tbQ=; b=IYtaj0IZ51VaKgf9Ix0Y2SgJf7Nhs1p6fpOftYXObgG8Pi4drZ59t7Rv6ddkm9IvFG2viC53AnkXX7qcax0AP+sfPsYpBqy/GWM/6k66Uev2NHalPuA3e2ZsLozaggE/9f0PMO2VxoNLgcicO6aRlCDqfIffhVJkYAMJUjVbd8E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612754912142542.2472326748601; Sun, 7 Feb 2021 19:28:32 -0800 (PST) Received: from localhost ([::1]:53564 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8xDx-0002B2-TA for importer@patchew.org; Sun, 07 Feb 2021 22:28:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58664) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wSr-0003Hs-5L for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:49 -0500 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:44117) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wSp-0006GO-7U for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:48 -0500 Received: by mail-pf1-x429.google.com with SMTP id t29so8740928pfg.11 for ; Sun, 07 Feb 2021 18:39:46 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qzll/P0wtV+vx8SpfL7JfV6f6jbtOfqckGjdgSv5tbQ=; b=QCIVrdZt8v+LF+wkl5axc4RGmnZhZR7gaq65Ufj8qI+SRWi809WK/1ldmcTyN0HE7Z fb8sxrZxJWHCI5cjQnT+ltaQfhjbgIrRwc6HGmDtTbb2H+r76/V8sffD6D4QINCfhxzl JEdPBiD869ezHA4v0vwM7lOy1gMQvm0yQuvrYgFlP4bf39a6Ft68F4KeWYzo96VYU7LJ FkM/hFySFmHMo6nCszMWFuaE84oK/HM6NUZDPOOPBYGn3DV5UZmGBMU2u34i5f37bKDE Lx/wyiNE8KwrKmaf+4aGJlIjAWYQnk6jXvVUdvpF7g/7yY3tGCBMZYhlUAJbL7wQnSax WC7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qzll/P0wtV+vx8SpfL7JfV6f6jbtOfqckGjdgSv5tbQ=; b=AiEStRkTbiPG+OVjYKPjZ5gjekd/xjAvQ1SOr+C2fbOTOg+UM+j5Dp5qKHPQnC4ANj QELy3YLJohqae5Xp9+E1KSGvY+Mnyg1iSdHaQF/7la0zUZD0mxAusxJ8OCEV8XKx3tsI xpLAA8bcyN5ZaXiCgzlp11tkwo2TdU+dJyIwjiAAovohZaEw3bcbyqmxzzPWkXP/Oq/z xQrnZTccRYCIHvgkK+dlKoVoSrCXfXXIHt/oUaBq/cCcXMggxQouckDcXbLb5sXGyQyQ X8wfbEGfUOwzXDXnBmDQ5/lDEV+1WcquQczSL/k0b85aYoKbTnZ0Zx0s2Oo7cEzljBAn 5qxw== X-Gm-Message-State: AOAM5302I/XgWGIqZ3elDPPuno/N7F2hBDHEQz+/tvY6ZrVoshgbT0AX t9jWEPyF6xmQRyw3AQcmizqRZi0TNf1VqA== X-Google-Smtp-Source: ABdhPJyD0aHbyOm3uv+Bh3Zs0icSFidg/DGOAjwWKaGBAsnYozjMjA5cNX0VQ2oJDT/ah3IUsagd+A== X-Received: by 2002:a63:e10b:: with SMTP id z11mr14919554pgh.40.1612751985974; Sun, 07 Feb 2021 18:39:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 69/70] tests/tcg: Increase timeout for TCI Date: Sun, 7 Feb 2021 18:37:51 -0800 Message-Id: <20210208023752.270606-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The longest test at the moment seems to be a (slower) aarch64 host, for which test-mmap takes 64 seconds. Signed-off-by: Richard Henderson --- configure | 3 +++ tests/tcg/Makefile.target | 6 ++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/configure b/configure index a34f91171d..53d0a32bc7 100755 --- a/configure +++ b/configure @@ -5790,6 +5790,9 @@ fi if test "$optreset" =3D "yes" ; then echo "HAVE_OPTRESET=3Dy" >> $config_host_mak fi +if test "$tcg" =3D "enabled" -a "$tcg_interpreter" =3D "true" ; then + echo "CONFIG_TCG_INTERPRETER=3Dy" >> $config_host_mak +fi if test "$fdatasync" =3D "yes" ; then echo "CONFIG_FDATASYNC=3Dy" >> $config_host_mak fi diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target index 24d75a5801..fa5813192a 100644 --- a/tests/tcg/Makefile.target +++ b/tests/tcg/Makefile.target @@ -77,8 +77,10 @@ LDFLAGS=3D QEMU_OPTS=3D =20 =20 -# If TCG debugging is enabled things are a lot slower -ifeq ($(CONFIG_DEBUG_TCG),y) +# If TCG debugging, or TCI is enabled things are a lot slower +ifneq ($(CONFIG_TCG_INTERPRETER),) +TIMEOUT=3D90 +else ifneq ($(CONFIG_DEBUG_TCG),) TIMEOUT=3D60 else TIMEOUT=3D15 --=20 2.25.1 From nobody Mon Feb 9 20:06:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612755098; cv=none; d=zohomail.com; s=zohoarc; b=RniDdxUU2mHhQ5m8llQX2AcLvnyUy8lHytTrtS3+zOOIo82SikHtOZMp4SoC/CU2kbEG35rWhLKEQsa0GP/Kaia0VXMBeRtOJbpKhLLApD9QyNV5y4sWXSda/bbjSQel/tTQXYRvy2kWHIq8IOhB+4ZaDD1AIPDpoTJLi7qT1SI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612755098; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wEpSveRBqQxH9QCIh+2wXIVlcJM9/sJDV4z9gEqJssk=; b=N0ANY4+MUu6q99aEl8mTyEnWA0t93QYgfxPf8aW+e+4b67TI7Kr80Z7tE+gfX72WNrhRWGF6u5ODj0lm5as/8Vz0r5qwZKTrp8r7ges25hViH7CbXi3KOvG7tZPyUy8uzlGK5iedf2bVLkgHtIAOkdIzJavkEnYL7kBijr9QHE4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161275509893294.5517258187283; Sun, 7 Feb 2021 19:31:38 -0800 (PST) Received: from localhost ([::1]:33980 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8xGz-0005kV-HD for importer@patchew.org; Sun, 07 Feb 2021 22:31:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58672) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l8wSs-0003Jr-2i for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:50 -0500 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:38458) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l8wSq-0006Gn-A2 for qemu-devel@nongnu.org; Sun, 07 Feb 2021 21:39:49 -0500 Received: by mail-pf1-x429.google.com with SMTP id d26so7525204pfn.5 for ; Sun, 07 Feb 2021 18:39:47 -0800 (PST) Received: from localhost.localdomain (174-21-150-71.tukw.qwest.net. [174.21.150.71]) by smtp.gmail.com with ESMTPSA id 74sm650954pfw.53.2021.02.07.18.39.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:39:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wEpSveRBqQxH9QCIh+2wXIVlcJM9/sJDV4z9gEqJssk=; b=RgdofgZ2++BadXux44Uy10k/X2YD042pBdjkPDajA06TSut4D4DGD9IUAkDl4N4+R0 ciuVUbwr7P1EvYiEDucq6+dX5v8a2riM44BIKYWVqMu3GAMhIiz9sVamFUknkSOsiajA TC2CjQpxJyVRcRhfIEaO7eYcGK1C0g6xytMYPiWJUCIvm4kQGl6Fm4ruSOKZkecth1Vu 50fkpAahL5AbbB4iqSwHVm1Fv9psNSs8u5HFgNqxFuaUt/RHT+Xw0tajeSJWcQelw24g hX9C0J5xRarcne37EplNGNUyR9CH6yJCPDGFN22PZ0MkmUsmQJDdcyaKp5poi3Hq3YPO nENg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wEpSveRBqQxH9QCIh+2wXIVlcJM9/sJDV4z9gEqJssk=; b=t+DeEB3Ews5RmwSHBG5NEU3Mr7Uq+/gpkvwXOJSUmnF4PrNq9Eqw02Y43kVcI+MoEj NEkMPt+brkI1J0eH7Q6Sm8Qyuq21lsulhEfbWVzDX6hxUJZB6/MDqqTd6uXKjXCJZlc9 /ANdys2RhsssyE0szCS2qcr2Icc4Y5bH5BiSHKIKtaaAG3PAXAyq7oVWRcBHBB+NVV3A N8ek86ag7TY5WGwLGJYdJUqC0yIXWpSzXJ56EQNR45AQLGMqZEPHB4RADTmCh5Kmp17o TYuor5b2pT3gwiex6Zxo/jYXcNGHxG55HYbXrTnu2RmU6hZRgVlwi+LdZzZBkR14tAC8 N0ng== X-Gm-Message-State: AOAM533hOdS+n/U2qfWiw1EwoGybMiZG1yPiRXVURqMnjG70RK4DS5hu t4dBEsJ3D1063S90QUB7Dencl5bv25WHYQ== X-Google-Smtp-Source: ABdhPJxU2YtsSvb2fPsIP0C9XYiNpq7HyCyjYO+F37enGOend2US457A1mUR+V2f0cckcoHSwsqZoQ== X-Received: by 2002:a62:d446:0:b029:1d2:8347:9db9 with SMTP id u6-20020a62d4460000b02901d283479db9mr15846816pfl.22.1612751987062; Sun, 07 Feb 2021 18:39:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 70/70] gitlab: Enable cross-i386 builds of TCI Date: Sun, 7 Feb 2021 18:37:52 -0800 Message-Id: <20210208023752.270606-71-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We're currently only testing TCI with a 64-bit host -- also test with a 32-bit host. Enable a selection of softmmu and user-only targets, 32-bit LE, 64-bit LE, 32-bit BE, as there are ifdefs for each. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- .gitlab-ci.d/crossbuilds.yml | 17 ++++++++++++++--- .../docker/dockerfiles/fedora-i386-cross.docker | 1 + 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index 66547b6683..99300f786b 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -6,7 +6,8 @@ - mkdir build - cd build - PKG_CONFIG_PATH=3D$PKG_CONFIG_PATH - ../configure --enable-werror $QEMU_CONFIGURE_OPTS --disable-user + ../configure --enable-werror $QEMU_CONFIGURE_OPTS $ACCEL_CONFIGURE_O= PTS + --disable-user --target-list-exclude=3D"arm-softmmu cris-softmmu i386-softmmu microblaze-softmmu mips-softmmu mipsel-softmmu mips64-softmmu ppc-softmmu sh4-softmmu xtensa-softmmu" @@ -27,7 +28,7 @@ - PKG_CONFIG_PATH=3D$PKG_CONFIG_PATH ../configure --enable-werror $QEMU_CONFIGURE_OPTS --disable-tools --enable-${ACCEL:-kvm} $ACCEL_CONFIGURE_OPTS - - make -j$(expr $(nproc) + 1) all check-build + - make -j$(expr $(nproc) + 1) all check-build $MAKE_CHECK_ARGS =20 .cross_user_build_job: stage: build @@ -36,7 +37,8 @@ - mkdir build - cd build - PKG_CONFIG_PATH=3D$PKG_CONFIG_PATH - ../configure --enable-werror $QEMU_CONFIGURE_OPTS --disable-system + ../configure --enable-werror $QEMU_CONFIGURE_OPTS $ACCEL_CONFIGURE_O= PTS + --disable-system - make -j$(expr $(nproc) + 1) all check-build $MAKE_CHECK_ARGS =20 cross-armel-system: @@ -81,6 +83,15 @@ cross-i386-user: IMAGE: fedora-i386-cross MAKE_CHECK_ARGS: check =20 +cross-i386-tci: + extends: .cross_accel_build_job + timeout: 60m + variables: + IMAGE: fedora-i386-cross + ACCEL: tcg-interpreter + ACCEL_CONFIGURE_OPTS: --target-list=3Di386-softmmu,i386-linux-user,aar= ch64-softmmu,aarch64-linux-user,ppc-softmmu,ppc-linux-user + MAKE_CHECK_ARGS: check + cross-mips-system: extends: .cross_system_build_job variables: diff --git a/tests/docker/dockerfiles/fedora-i386-cross.docker b/tests/dock= er/dockerfiles/fedora-i386-cross.docker index a6e411291b..aa66314c65 100644 --- a/tests/docker/dockerfiles/fedora-i386-cross.docker +++ b/tests/docker/dockerfiles/fedora-i386-cross.docker @@ -5,6 +5,7 @@ ENV PACKAGES \ findutils \ gcc \ git \ + libffi-devel.i686 \ libtasn1-devel.i686 \ libzstd-devel.i686 \ make \ --=20 2.25.1