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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id i20sm16845931wmq.7.2021.02.07.15.23.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 15:23:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1gVWXaMf3oEyIVlaRSD52U7PW5E6+zv5BhWBd9cIe8U=; b=dieu8kT6DPBl7biaAhh2IbRiZhFKJaDFtk8m6kE+KmZajs5PsD1IaEptYuYVKkUY7s Zfp9qKFNP+WDAMPdffILTbNrvQq1heYfVgX1TPSaPi5ByDfYNKVVhcSfHp6gAk1Qe7Ai Bx5YjO9bpLdGH6RRCxeG6CA/hxdfRypv8ID45uC7g5gJuZaVTq7ygkRyAzoutHrUlj7Q m8656dYNQyRWAcJnb/0xf0cOvtVAvmBEbfu4Fd63Dh/+JmfX2vXd0yVHwMEdRqYfmYBc niDhY+KUHqvcoLVASRNe2zpwRw+0EEzg21aOGkiWWs/L843DuKj6mhFsAf0zdrgd55Lq xNjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=1gVWXaMf3oEyIVlaRSD52U7PW5E6+zv5BhWBd9cIe8U=; b=siZqwqShMBgnnEsN084sPfUzcW6MR3oNjQA0A60pTKkfhZpsCx+v8+850uDj1H2ps4 kGaAX4XKSK9q2rlto2fPlzCSFaKytuBwn+yCYFjYeLMEKGOEltEhT7xm49CxnwC3sRgC 1/4ApXmvp6v1BJIpAfQvpg7pNjNU+xAb58JAdekXD79L3NA4llAn9W6E7I/4aERUnFNG T6xiZdZQZUXUQF3cy7ZVxpSWCamUtDGLMBnw+94MxAZaWa9REzTUCNtrt3pz51+HDosi B6FC6jIDFtNVP7WedTa2ndWzN0EIDjwqtb4i7Ux8xJZo+Irx/qUDtDgNNbvftDnYc1Ro Hh3Q== X-Gm-Message-State: AOAM533Y1tHvHKgoFOhdeV2yG1+aSH68XbjM6csw5e95NtVdbgEQs5Xn N07eBnDM6G3gB4C69dqj8Js= X-Google-Smtp-Source: ABdhPJyVklY2iZR1qB2FvBdZpCQETYGMgFD+Uou4udI+xcdPBlAgXW06g+snhQC2056ftJigqmzpHw== X-Received: by 2002:a5d:5910:: with SMTP id v16mr17553674wrd.29.1612740225386; Sun, 07 Feb 2021 15:23:45 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato , Paolo Bonzini , Aurelien Jarno , Sagar Karandikar , Palmer Dabbelt , Laurent Vivier , qemu-arm@nongnu.org, Claudio Fontana , Peter Maydell , Richard Henderson , Alistair Francis , Jiaxun Yang , Aleksandar Rikalo , qemu-riscv@nongnu.org Subject: [PATCH v2 6/6] exec/cpu_ldst: Move tlb* declarations to "exec/exec-all.h" Date: Mon, 8 Feb 2021 00:23:10 +0100 Message-Id: <20210207232310.2505283-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210207232310.2505283-1-f4bug@amsat.org> References: <20210207232310.2505283-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Keep MMU functions in "exec/cpu_ldst.h", and move TLB functions to "exec/exec-all.h". As tlb_addr_write() is only called in accel/tcg/cputlb.c, make move it there as a static function. Doing so we removed the "tcg/tcg.h" dependency on "exec/cpu_ldst.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu_ldst.h | 28 ---------------------------- include/exec/exec-all.h | 16 ++++++++++++++++ accel/tcg/cputlb.c | 9 +++++++++ 3 files changed, 25 insertions(+), 28 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index ef54cb7e1f8..c1753a64dfd 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -291,34 +291,6 @@ static inline void cpu_stq_le_mmuidx_ra(CPUArchState *= env, abi_ptr addr, =20 #else =20 -/* Needed for TCG_OVERSIZED_GUEST */ -#include "tcg/tcg.h" - -static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry) -{ -#if TCG_OVERSIZED_GUEST - return entry->addr_write; -#else - return qatomic_read(&entry->addr_write); -#endif -} - -/* Find the TLB index corresponding to the mmu_idx + address pair. */ -static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx, - target_ulong addr) -{ - uintptr_t size_mask =3D env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY= _BITS; - - return (addr >> TARGET_PAGE_BITS) & size_mask; -} - -/* Find the TLB entry corresponding to the mmu_idx + address pair. */ -static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, - target_ulong addr) -{ - return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)]; -} - uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, int mmu_idx, uintptr_t ra); int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index c5e8e355b7f..8e54b537189 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -297,6 +297,22 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); =20 +/* Find the TLB index corresponding to the mmu_idx + address pair. */ +static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx, + target_ulong addr) +{ + uintptr_t size_mask =3D env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY= _BITS; + + return (addr >> TARGET_PAGE_BITS) & size_mask; +} + +/* Find the TLB entry corresponding to the mmu_idx + address pair. */ +static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, + target_ulong addr) +{ + return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)]; +} + /* * Find the iotlbentry for ptr. This *must* be present in the TLB * because we just found the mapping. diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a6247da34a0..084d19b52d7 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -429,6 +429,15 @@ void tlb_flush_all_cpus_synced(CPUState *src_cpu) tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, ALL_MMUIDX_BITS); } =20 +static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry) +{ +#if TCG_OVERSIZED_GUEST + return entry->addr_write; +#else + return qatomic_read(&entry->addr_write); +#endif +} + void tlb_assert_iotlb_entry_for_ptr_present(CPUArchState *env, int ptr_mmu= _idx, uint64_t ptr, MMUAccessType ptr_access, --=20 2.26.2