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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id g1sm24266272wrq.30.2021.02.07.15.23.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 15:23:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1+/tMS8+lcjG3CT8AZjxjSJSDoUQYqmsaNIWbdboyjk=; b=vOlG7yWldhqlrtKrJfzP0hjuA5oP71mJ6EJAmU6JbUk7Z4lDJnb5g7LiFU+pAPvthi ZdazYD9bB8KU1rXgjVvOu9rqQeKV1/BWD3/QsMMjWjiTtgZ6elHTz/pk2BwUg27OX9hz 3RaiXXvoyxFMG59IV2vevS+Tm60pdCJ+jcXw14Rm+UJE+UtVoFL3emfk+3GpGa1P7Z1S ME8NNd4KSdHsyJYScmCZzxM8hzmJE4/rcjOJPCgrUn/LWlGsURUIioX6/vVJoqiqbPG0 RKshuDXC9apbZJEG2lLTT2XpbAAqJ/j2xyji0EmYdQPFxR+1cZ0OsNkGI417IkqvMBvR ruWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=1+/tMS8+lcjG3CT8AZjxjSJSDoUQYqmsaNIWbdboyjk=; b=VgT+wSfihdU/YL7gngm9hGHd5kr/N4HGA6pHScM4NmT/0i6g/JNpzZzX5kJbBnSd2T N1rPsUwE9zKGDwJuJz6PzvgVy10m3KG9XLQOrjPH/SGEfI63Ci54AcMpaWuCgL7xFPgD uWzF+ERzkLr52O+FyTQaAtdeXALc4QSzza7EHCKHi2tzfqqyHe5GEoaFRacLyCeElyIs ry7KiThCKl/LdN3k0oWA3OZBEHEegkA9zNejXLmHAwgBsS9+Lmf3nsal5ZtakPpum7y9 afBDtwC1mgHJ24CMEoPMIw1oEUldx4Q2V96TBXebcakkUZCiUGenVBClXSImMFpRON+q vXbA== X-Gm-Message-State: AOAM531m5ubrNLyiVwzQ1mEgyTsIB0w+QDdSKqv7Fs+joiIMpA6W6c4N FE5e1PuLzYd2uOS/VA0fjqw= X-Google-Smtp-Source: ABdhPJwS3bInnfNiklbTXweoQsYPzIE0S7UPU9PuK4/kWIUr24hZAgrdKcbBbH0d5SE+snNrk7S1mQ== X-Received: by 2002:adf:f508:: with SMTP id q8mr17031679wro.291.1612740198745; Sun, 07 Feb 2021 15:23:18 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato , Paolo Bonzini , Aurelien Jarno , Sagar Karandikar , Palmer Dabbelt , Laurent Vivier , qemu-arm@nongnu.org, Claudio Fontana , Peter Maydell , Richard Henderson , Alistair Francis , Jiaxun Yang , Aleksandar Rikalo , qemu-riscv@nongnu.org Subject: [RFC PATCH v2 1/6] target: Replace tcg_debug_assert() by assert() Date: Mon, 8 Feb 2021 00:23:05 +0100 Message-Id: <20210207232310.2505283-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210207232310.2505283-1-f4bug@amsat.org> References: <20210207232310.2505283-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Since commit 262a69f4282 ("osdep.h: Prohibit disabling assert() in supported builds") we can not build QEMU with assert() disabled. tcg_debug_assert() does nothing until QEMU is configured with --enable-debug-tcg. Since there is no obvious logic whether to use tcg_debug_assert() or assert() for files under target/, simplify by using plain assert() everywhere. Keep tcg_debug_assert() for the tcg/ and accel/ directories. Patch created mechanically using: $ sed -i s/tcg_debug_assert/assert/ \ $(git grep -l tcg_debug_assert target/) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- If there is a logic, we should document it, and include "tcg/tcg.h" in these files. --- target/arm/translate.h | 4 +-- target/arm/mte_helper.c | 4 +-- target/arm/sve_helper.c | 8 +++--- target/arm/translate-a64.c | 12 ++++----- target/arm/translate-sve.c | 4 +-- target/arm/translate.c | 36 ++++++++++++------------- target/hppa/translate.c | 4 +-- target/rx/op_helper.c | 6 ++--- target/rx/translate.c | 14 +++++----- target/sh4/translate.c | 4 +-- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 11 files changed, 49 insertions(+), 49 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 423b0e08df0..e2ddf87629c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -220,7 +220,7 @@ static inline void set_pstate_bits(uint32_t bits) { TCGv_i32 p =3D tcg_temp_new_i32(); =20 - tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); + assert(!(bits & CACHED_PSTATE_BITS)); =20 tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); tcg_gen_ori_i32(p, p, bits); @@ -233,7 +233,7 @@ static inline void clear_pstate_bits(uint32_t bits) { TCGv_i32 p =3D tcg_temp_new_i32(); =20 - tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); + assert(!(bits & CACHED_PSTATE_BITS)); =20 tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); tcg_gen_andi_i32(p, p, ~bits); diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 153bd1e9df8..6cea9d1b506 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -166,8 +166,8 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, * not set in the cputlb lookup above. */ mr =3D memory_region_from_host(host, &ptr_ra); - tcg_debug_assert(mr !=3D NULL); - tcg_debug_assert(memory_region_is_ram(mr)); + assert(mr !=3D NULL); + assert(memory_region_is_ram(mr)); ptr_paddr =3D ptr_ra; do { ptr_paddr +=3D mr->addr; diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 844db08bd57..c8cdf7618eb 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4030,7 +4030,7 @@ static intptr_t find_next_active(uint64_t *vg, intptr= _t reg_off, reg_off +=3D ctz64(pg); =20 /* We should never see an out of range predicate bit set. */ - tcg_debug_assert(reg_off < reg_max); + assert(reg_off < reg_max); return reg_off; } =20 @@ -4186,7 +4186,7 @@ static bool sve_cont_ldst_elements(SVEContLdSt *info,= target_ulong addr, /* No active elements, no pages touched. */ return false; } - tcg_debug_assert(reg_off_last >=3D 0 && reg_off_last < reg_max); + assert(reg_off_last >=3D 0 && reg_off_last < reg_max); =20 info->reg_off_first[0] =3D reg_off_first; info->mem_off_first[0] =3D (reg_off_first >> esz) * msize; @@ -4235,7 +4235,7 @@ static bool sve_cont_ldst_elements(SVEContLdSt *info,= target_ulong addr, * this may affect the address reported in an exception. */ reg_off_split =3D find_next_active(vg, reg_off_split, reg_max, esz); - tcg_debug_assert(reg_off_split <=3D reg_off_last); + assert(reg_off_split <=3D reg_off_last); info->reg_off_first[1] =3D reg_off_split; info->mem_off_first[1] =3D (reg_off_split >> esz) * msize; info->reg_off_last[1] =3D reg_off_last; @@ -4794,7 +4794,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const = target_ulong addr, /* Probe the page(s). */ if (!sve_cont_ldst_pages(&info, fault, env, addr, MMU_DATA_LOAD, retad= dr)) { /* Fault on first element. */ - tcg_debug_assert(fault =3D=3D FAULT_NO); + assert(fault =3D=3D FAULT_NO); memset(vd, 0, reg_max); goto do_fault; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ffc060e5d70..f570506133c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -144,7 +144,7 @@ static void set_btype(DisasContext *s, int val) TCGv_i32 tcg_val; =20 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */ - tcg_debug_assert(val >=3D 1 && val <=3D 3); + assert(val >=3D 1 && val <=3D 3); =20 tcg_val =3D tcg_const_i32(val); tcg_gen_st_i32(tcg_val, cpu_env, offsetof(CPUARMState, btype)); @@ -10659,7 +10659,7 @@ static void handle_vec_simd_shri(DisasContext *s, b= ool is_q, bool is_u, unallocated_encoding(s); return; } - tcg_debug_assert(size <=3D 3); + assert(size <=3D 3); =20 if (!fp_access_check(s)) { return; @@ -12812,7 +12812,7 @@ static void disas_simd_two_reg_misc(DisasContext *s= , uint32_t insn) /* Coverity claims (size =3D=3D 3 && !is_q) has been eliminated * from all paths leading to here. */ - tcg_debug_assert(is_q); + assert(is_q); for (pass =3D 0; pass < 2; pass++) { TCGv_i64 tcg_op =3D tcg_temp_new_i64(); TCGv_i64 tcg_res =3D tcg_temp_new_i64(); @@ -14615,7 +14615,7 @@ static void disas_a64_insn(CPUARMState *env, DisasC= ontext *s) s->guarded_page =3D is_guarded_page(env, s); =20 /* First insn can have btype set to non-zero. */ - tcg_debug_assert(s->btype >=3D 0); + assert(s->btype >=3D 0); =20 /* * Note that the Branch Target Exception has fairly high @@ -14633,7 +14633,7 @@ static void disas_a64_insn(CPUARMState *env, DisasC= ontext *s) } } else { /* Not the first insn: btype must be 0. */ - tcg_debug_assert(s->btype =3D=3D 0); + assert(s->btype =3D=3D 0); } } =20 @@ -14733,7 +14733,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, =20 #ifdef CONFIG_USER_ONLY /* In sve_probe_page, we assume TBI is enabled. */ - tcg_debug_assert(dc->tbid & 1); + assert(dc->tbid & 1); #endif =20 /* Single step state. The code-generation logic here is: diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 27402af23c0..a1e327f863e 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3938,8 +3938,8 @@ static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCM= LA_zzxz *a) gen_helper_gvec_fcmlas_idx, }; =20 - tcg_debug_assert(a->esz =3D=3D 1 || a->esz =3D=3D 2); - tcg_debug_assert(a->rd =3D=3D a->ra); + assert(a->esz =3D=3D 1 || a->esz =3D=3D 2); + assert(a->rd =3D=3D a->ra); if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F= 16 : FPST_FPCR); diff --git a/target/arm/translate.c b/target/arm/translate.c index 1653cca1aaa..04ebfcc0d6d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2972,7 +2972,7 @@ void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_= ofs, uint32_t rn_ofs, static gen_helper_gvec_3_ptr * const fns[2] =3D { gen_helper_gvec_qrdmlah_s16, gen_helper_gvec_qrdmlah_s32 }; - tcg_debug_assert(vece >=3D 1 && vece <=3D 2); + assert(vece >=3D 1 && vece <=3D 2); gen_gvec_fn3_qc(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, fns[vece - 1]); } =20 @@ -2982,7 +2982,7 @@ void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_= ofs, uint32_t rn_ofs, static gen_helper_gvec_3_ptr * const fns[2] =3D { gen_helper_gvec_qrdmlsh_s16, gen_helper_gvec_qrdmlsh_s32 }; - tcg_debug_assert(vece >=3D 1 && vece <=3D 2); + assert(vece >=3D 1 && vece <=3D 2); gen_gvec_fn3_qc(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, fns[vece - 1]); } =20 @@ -3105,8 +3105,8 @@ void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, ui= nt32_t rm_ofs, }; =20 /* tszimm encoding produces immediates in the range [1..esize]. */ - tcg_debug_assert(shift > 0); - tcg_debug_assert(shift <=3D (8 << vece)); + assert(shift > 0); + assert(shift <=3D (8 << vece)); =20 /* * Shifts larger than the element size are architecturally valid. @@ -3181,8 +3181,8 @@ void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, ui= nt32_t rm_ofs, }; =20 /* tszimm encoding produces immediates in the range [1..esize]. */ - tcg_debug_assert(shift > 0); - tcg_debug_assert(shift <=3D (8 << vece)); + assert(shift > 0); + assert(shift <=3D (8 << vece)); =20 /* * Shifts larger than the element size are architecturally valid. @@ -3290,8 +3290,8 @@ void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, u= int32_t rm_ofs, }; =20 /* tszimm encoding produces immediates in the range [1..esize] */ - tcg_debug_assert(shift > 0); - tcg_debug_assert(shift <=3D (8 << vece)); + assert(shift > 0); + assert(shift <=3D (8 << vece)); =20 if (shift =3D=3D (8 << vece)) { /* @@ -3386,8 +3386,8 @@ void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, u= int32_t rm_ofs, }; =20 /* tszimm encoding produces immediates in the range [1..esize] */ - tcg_debug_assert(shift > 0); - tcg_debug_assert(shift <=3D (8 << vece)); + assert(shift > 0); + assert(shift <=3D (8 << vece)); =20 /* * Shifts larger than the element size are architecturally valid. @@ -3491,8 +3491,8 @@ void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, u= int32_t rm_ofs, }; =20 /* tszimm encoding produces immediates in the range [1..esize] */ - tcg_debug_assert(shift > 0); - tcg_debug_assert(shift <=3D (8 << vece)); + assert(shift > 0); + assert(shift <=3D (8 << vece)); =20 if (shift =3D=3D (8 << vece)) { /* @@ -3606,8 +3606,8 @@ void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, u= int32_t rm_ofs, }; =20 /* tszimm encoding produces immediates in the range [1..esize] */ - tcg_debug_assert(shift > 0); - tcg_debug_assert(shift <=3D (8 << vece)); + assert(shift > 0); + assert(shift <=3D (8 << vece)); =20 tcg_gen_gvec_2i(rd_ofs, rm_ofs, opr_sz, max_sz, shift, &ops[vece]); } @@ -3695,8 +3695,8 @@ void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uin= t32_t rm_ofs, }; =20 /* tszimm encoding produces immediates in the range [1..esize]. */ - tcg_debug_assert(shift > 0); - tcg_debug_assert(shift <=3D (8 << vece)); + assert(shift > 0); + assert(shift <=3D (8 << vece)); =20 /* Shift of esize leaves destination unchanged. */ if (shift < (8 << vece)) { @@ -3788,8 +3788,8 @@ void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uin= t32_t rm_ofs, }; =20 /* tszimm encoding produces immediates in the range [0..esize-1]. */ - tcg_debug_assert(shift >=3D 0); - tcg_debug_assert(shift < (8 << vece)); + assert(shift >=3D 0); + assert(shift < (8 << vece)); =20 if (shift =3D=3D 0) { tcg_gen_gvec_mov(vece, rd_ofs, rm_ofs, opr_sz, max_sz); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 64af1e0d5cc..ceb3bacc7dd 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1945,8 +1945,8 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg de= st, for the indirect branch consumes no special resources, we can (conditionally) skip B and continue execution. */ /* The use_nullify_skip test implies we have a known control path.= */ - tcg_debug_assert(ctx->iaoq_b !=3D -1); - tcg_debug_assert(ctx->iaoq_n !=3D -1); + assert(ctx->iaoq_b !=3D -1); + assert(ctx->iaoq_n !=3D -1); =20 /* We do have to handle the non-local temporary, DEST, before branching. Since IOAQ_F is not really live at this point, we diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c index 4d315b44492..03d285fbafe 100644 --- a/target/rx/op_helper.c +++ b/target/rx/op_helper.c @@ -234,7 +234,7 @@ static void (* const cpu_stfn[])(CPUArchState *env, =20 void helper_sstr(CPURXState *env, uint32_t sz) { - tcg_debug_assert(sz < 3); + assert(sz < 3); while (env->regs[3] !=3D 0) { cpu_stfn[sz](env, env->regs[1], env->regs[2], GETPC()); env->regs[1] +=3D 1 << sz; @@ -283,7 +283,7 @@ void helper_smovb(CPURXState *env) void helper_suntil(CPURXState *env, uint32_t sz) { uint32_t tmp; - tcg_debug_assert(sz < 3); + assert(sz < 3); if (env->regs[3] =3D=3D 0) { return ; } @@ -302,7 +302,7 @@ void helper_suntil(CPURXState *env, uint32_t sz) void helper_swhile(CPURXState *env, uint32_t sz) { uint32_t tmp; - tcg_debug_assert(sz < 3); + assert(sz < 3); if (env->regs[3] =3D=3D 0) { return ; } diff --git a/target/rx/translate.c b/target/rx/translate.c index 9ea941c6302..ff12af4f7f8 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -87,7 +87,7 @@ static uint32_t li(DisasContext *ctx, int sz) CPURXState *env =3D ctx->env; addr =3D ctx->base.pc_next; =20 - tcg_debug_assert(sz < 4); + assert(sz < 4); switch (sz) { case 1: ctx->base.pc_next +=3D 1; @@ -201,7 +201,7 @@ static inline TCGv rx_index_addr(DisasContext *ctx, TCG= v mem, { uint32_t dsp; =20 - tcg_debug_assert(ld < 3); + assert(ld < 3); switch (ld) { case 0: return cpu_regs[reg]; @@ -222,7 +222,7 @@ static inline TCGv rx_index_addr(DisasContext *ctx, TCG= v mem, static inline MemOp mi_to_mop(unsigned mi) { static const MemOp mop[5] =3D { MO_SB, MO_SW, MO_UL, MO_UW, MO_UB }; - tcg_debug_assert(mi < 5); + assert(mi < 5); return mop[mi]; } =20 @@ -258,7 +258,7 @@ static int is_privileged(DisasContext *ctx, int is_exce= ption) /* generate QEMU condition */ static void psw_cond(DisasCompare *dc, uint32_t cond) { - tcg_debug_assert(cond < 16); + assert(cond < 16); switch (cond) { case 0: /* z */ dc->cond =3D TCG_COND_EQ; @@ -1401,7 +1401,7 @@ static inline void shiftr_imm(uint32_t rd, uint32_t r= s, uint32_t imm, static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) =3D { tcg_gen_shri_i32, tcg_gen_sari_i32, }; - tcg_debug_assert(alith < 2); + assert(alith < 2); if (imm) { gen_sXri[alith](cpu_regs[rd], cpu_regs[rs], imm - 1); tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); @@ -1425,7 +1425,7 @@ static inline void shiftr_reg(uint32_t rd, uint32_t r= s, unsigned int alith) static void (* const gen_sXr[])(TCGv ret, TCGv arg1, TCGv arg2) =3D { tcg_gen_shr_i32, tcg_gen_sar_i32, }; - tcg_debug_assert(alith < 2); + assert(alith < 2); noshift =3D gen_new_label(); done =3D gen_new_label(); count =3D tcg_temp_new(); @@ -2282,7 +2282,7 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a) { TCGv vec; =20 - tcg_debug_assert(a->imm < 0x100); + assert(a->imm < 0x100); vec =3D tcg_const_i32(a->imm); tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); gen_helper_rxint(cpu_env, vec); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 93127906237..f12cc0830bf 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -339,7 +339,7 @@ static void gen_delayed_conditional_jump(DisasContext *= ctx) static inline void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { /* We have already signaled illegal instruction for odd Dr. */ - tcg_debug_assert((reg & 1) =3D=3D 0); + assert((reg & 1) =3D=3D 0); reg ^=3D ctx->fbank; tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]); } @@ -347,7 +347,7 @@ static inline void gen_load_fpr64(DisasContext *ctx, TC= Gv_i64 t, int reg) static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { /* We have already signaled illegal instruction for odd Dr. */ - tcg_debug_assert((reg & 1) =3D=3D 0); + assert((reg & 1) =3D=3D 0); reg ^=3D ctx->fbank; tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t); } diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 887c6b88831..f0e6e844f5f 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -992,7 +992,7 @@ static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t = dofs, uint32_t aofs, .vece =3D MO_64 }, }; =20 - tcg_debug_assert(vece <=3D MO_64); + assert(vece <=3D MO_64); tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &rsub_op[vece]); } =20 --=20 2.26.2 From nobody Tue Nov 18 19:49:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) client-ip=209.85.221.43; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id l1sm25605825wrp.40.2021.02.07.15.23.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 15:23:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H7DdpVZKuaTFU+QINWMbbbomeFKhPW3S4eDxwf+nJCo=; b=Cbe0/5QwUe4ZyDD3MCWKIRYwfN9+3L6rNnWC2TOjH7OXHTThDg2a1ZbJVNQ3Kzf3st En6PUVBxAp4PxuocUpThjh2BUbXwmj4TsUAq7zyP/wF/zcmEyBp7UsQy6xsrBppchqPb xaKn+OA362o9B5Pfn+32MFxsnEaxvQmoexp0yQS5CrniIOSwJ9UVILT4OQ0YV+l4a8zb UIDtHmQtVDPxPhHTOfcOKsjj00ADyCFI+YiUb6EKu47ho7vr5MjQQly8zmSOk2hxHeGo q0CgRJRIbHzG8ADxnWIbKDypHAzL8Wkz7WT/WiLYiSMgUGkKHqucN8bPsg5DIZX6MVT3 KL2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=H7DdpVZKuaTFU+QINWMbbbomeFKhPW3S4eDxwf+nJCo=; b=RIgCT7EXbu3/L9GLbdt6S3fUyC/0TFJNe02EajPA2t8rJeECuLwC1RPzkI6629jjMK U1HBOtGXSz3Di6bDYoArlH+o3s7UH4DAEcQM+/QKj8RLlHkrxOKl77KeCf3Vjx4azNF1 7gXPW9iM2iQGWEhfLPZmKmapHom/RbUe+tiEZ/ummMxz8ZonFQMIooR5HqHx2s+X2uXk k2e/gJkMp00tHDBNQnijzdlcyKbOv/RtDTfhcv9lkgY6gU7Z6ToyiDuw3guMTzKQlI1r wcnhKPtQ+Ofsk1/7pu5csZiZne9N3xOuEsfPD/h3AURPuNEnRGup5u7gfeqepHmR4P7t +vgA== X-Gm-Message-State: AOAM530VrD/y8Ds4BmRoHHdmwJd6MGH7B6HwfpFll3rQ7ofVfd/hOta7 Ot4JnIXQD0qpNeyoYNg7Qro= X-Google-Smtp-Source: ABdhPJyWiUk4XoFKg97EVROdcEEDZ3GQAVdpr0UYoBXaLXyG4LroE1FRPhHK/244ObpYQu6Z9zgkqw== X-Received: by 2002:a5d:5283:: with SMTP id c3mr16559778wrv.319.1612740203868; Sun, 07 Feb 2021 15:23:23 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato , Paolo Bonzini , Aurelien Jarno , Sagar Karandikar , Palmer Dabbelt , Laurent Vivier , qemu-arm@nongnu.org, Claudio Fontana , Peter Maydell , Richard Henderson , Alistair Francis , Jiaxun Yang , Aleksandar Rikalo , qemu-riscv@nongnu.org Subject: [PATCH v2 2/6] target/m68k: Include missing "tcg/tcg.h" header Date: Mon, 8 Feb 2021 00:23:06 +0100 Message-Id: <20210207232310.2505283-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210207232310.2505283-1-f4bug@amsat.org> References: <20210207232310.2505283-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Commit 14f944063af ("target-m68k: add cas/cas2 ops") introduced use of typedef/prototypes declared in "tcg/tcg.h" without including it. This was not a problem because "tcg/tcg.h" is pulled in by "exec/cpu_ldst.h". To be able to remove this header there, we first need to include it here in op_helper.c, else we get: [953/1018] Compiling C object libqemu-m68k-softmmu.fa.p/target_m68k_op_he= lper.c.o target/m68k/op_helper.c: In function =E2=80=98do_cas2l=E2=80=99: target/m68k/op_helper.c:774:5: error: unknown type name =E2=80=98TCGMemOp= Idx=E2=80=99 774 | TCGMemOpIdx oi; | ^~~~~~~~~~~ target/m68k/op_helper.c:787:18: error: implicit declaration of function = =E2=80=98make_memop_idx=E2=80=99 [-Werror=3Dimplicit-function-declaration] 787 | oi =3D make_memop_idx(MO_BEQ, mmu_idx); | ^~~~~~~~~~~~~~ target/m68k/op_helper.c:787:18: error: nested extern declaration of =E2= =80=98make_memop_idx=E2=80=99 [-Werror=3Dnested-externs] target/m68k/op_helper.c:788:17: error: implicit declaration of function = =E2=80=98helper_atomic_cmpxchgq_be_mmu=E2=80=99; did you mean =E2=80=98help= er_atomic_cmpxchgq_be=E2=80=99? [-Werror=3Dimplicit-function-declaration] 788 | l =3D helper_atomic_cmpxchgq_be_mmu(env, a1, c, u, oi= , ra); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | helper_atomic_cmpxchgq_be target/m68k/op_helper.c:788:17: error: nested extern declaration of =E2= =80=98helper_atomic_cmpxchgq_be_mmu=E2=80=99 [-Werror=3Dnested-externs] cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/m68k/op_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 202498deb51..36b68fd318f 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" +#include "tcg/tcg.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" --=20 2.26.2 From nobody Tue Nov 18 19:49:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1612740211; cv=none; d=zohomail.com; s=zohoarc; b=ALFnmmKprI3EUjCkaHu3ZMqLMthUxaf3B/Z5iXeTuiLFPbmhBA+2wnPQRezZ6CRFfGugvIDA/O1ERDipkK3xdZUnDWXuk+Y1IXNwhJz+j5D2Ghp9RUcPBL2aFBO8udnYAQQBPJV2JOld1s+uVaWlmEx/JQ1+xiNtrsmhmoMV5ZQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612740211; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NB0PxeiyUnyh7a2jT9hNZ8p231d4tVFomh4sbxGsRA8=; b=HT2e97ZLu+PF7zqPUw5U8S6EwG38xh3VGlVpVfHJ8VaRHCS8UdBORGA19N0igTldXmb+2DNk7DrwYG0J9sMK3JXG2jAu9j5dNR4MbK5Nb0imGRLwmqjsLOiOtN40p/B6gGTRrW9MdVxcM8GVj+SKO+cL2uQbWMvnTC97DoOblY0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by mx.zohomail.com with SMTPS id 1612740211044366.8486783458669; Sun, 7 Feb 2021 15:23:31 -0800 (PST) Received: by mail-wr1-f44.google.com with SMTP id v15so15128991wrx.4 for ; Sun, 07 Feb 2021 15:23:30 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id z15sm23614358wrt.8.2021.02.07.15.23.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 15:23:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NB0PxeiyUnyh7a2jT9hNZ8p231d4tVFomh4sbxGsRA8=; b=H6dm/1g2ElXpRCdyGyvOLm4dKRdC6BeKWByg/dXiUz0knV2bgWzJd3p7kpSMk48iUj n0YgH4Mi06hj9k34E/GnUesKNDs2zXLHIY2a403RiqM/29KiHeHOfIrt7Eru9EIavz8F 2vBeGt9jCLeMEBHZtC9XBCbJBitHKeb8N2hdWhxlTB3LdatBjksFWjR3jwVSgVbGyGTc +GUX9kmB+ZzY9XmyyCjpzeQYAtrvw/3diNFHUWKzGwOAlYQ0Pvx80vzkjfMiY0C5FY+2 sBWm1dY2uowJxUj2hcDyp1SbD1RLCBzO+u5ylJ5C8VsTboAptYR0Gq9PQYentVq26HUp vlkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=NB0PxeiyUnyh7a2jT9hNZ8p231d4tVFomh4sbxGsRA8=; b=hclzt/p2J5AkQF2VgAq4Hb1Jkb2lTZaJ9LFw73zoCJr9iucyeZZMb7l35j38ScPAwg j0lkfnPm1Rq3EzUg1PguEuZ9yniSBwyUSTTTMVkfQLLpbA+4POvRe2cN5lqTEBeyisSc IVoVbOJt71nSYj5ozUzl1NTBbryMjKFPhH03J3B2/yA1NfmWDPm+l49zU7KtDwTM8k3n eKCZonubkEDQOfiD8uVTCYgcBoSj9RbneiE5XXuN1UOK+0l/Rfu3VlhplXY23O9MNUEz OqEIc7jzNAHdGoNGitu9Dh2OkyR5Go6JYnbvSmoxsX90JzCggs4K09R46J+G8166fVzy ieJQ== X-Gm-Message-State: AOAM530k02YUP2laPTOemrDHgDB1ORtwiqcdDPI5cRBFmAaSAnyG6mqC eZBRrMQL/e/fKOIoxEC6sns= X-Google-Smtp-Source: ABdhPJyQhz82BwQ8fi6Ee/12u4Dqp9KXCyb8ZlEgT+XV6b8wbWh5emTcY+vdGvd0IVs3IxxcaNbqow== X-Received: by 2002:a5d:4292:: with SMTP id k18mr17223984wrq.218.1612740209256; Sun, 07 Feb 2021 15:23:29 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato , Paolo Bonzini , Aurelien Jarno , Sagar Karandikar , Palmer Dabbelt , Laurent Vivier , qemu-arm@nongnu.org, Claudio Fontana , Peter Maydell , Richard Henderson , Alistair Francis , Jiaxun Yang , Aleksandar Rikalo , qemu-riscv@nongnu.org Subject: [PATCH v2 3/6] target/mips: Include missing "tcg/tcg.h" header Date: Mon, 8 Feb 2021 00:23:07 +0100 Message-Id: <20210207232310.2505283-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210207232310.2505283-1-f4bug@amsat.org> References: <20210207232310.2505283-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Commit 83be6b54123 ("Fix MSA instructions LD. on big endian host") introduced use of typedef/prototypes declared in "tcg/tcg.h" without including it. This was not a problem because "tcg/tcg.h" is pulled in by "exec/cpu_ldst.h". To be able to remove this header there, we first need to include it here in op_helper.c, else we get: [222/337] Compiling C object libqemu-mips-softmmu.fa.p/target_mips_msa_he= lper.c.o target/mips/msa_helper.c: In function =E2=80=98helper_msa_ld_b=E2=80=99: target/mips/msa_helper.c:8214:9: error: unknown type name =E2=80=98TCGMem= OpIdx=E2=80=99 8214 | TCGMemOpIdx oi =3D make_memop_idx(MO_TE | DF | MO_UNALN, = \ | ^~~~~~~~~~~ target/mips/msa_helper.c:8224:5: note: in expansion of macro =E2=80=98MEM= OP_IDX=E2=80=99 8224 | MEMOP_IDX(DF_BYTE) | ^~~~~~~~~ target/mips/msa_helper.c:8214:26: error: implicit declaration of function= =E2=80=98make_memop_idx=E2=80=99 [-Werror=3Dimplicit-function-declaration] 8214 | TCGMemOpIdx oi =3D make_memop_idx(MO_TE | DF | MO_UNALN, = \ | ^~~~~~~~~~~~~~ target/mips/msa_helper.c:8227:18: error: implicit declaration of function= =E2=80=98helper_ret_ldub_mmu=E2=80=99 [-Werror=3Dimplicit-function-declara= tion] 8227 | pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE= ), oi, GETPC()); | ^~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/msa_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 1298a1917ce..4caefe29ad7 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internal.h" +#include "tcg/tcg.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exec/memop.h" --=20 2.26.2 From nobody Tue Nov 18 19:49:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) client-ip=209.85.128.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1612740216; cv=none; d=zohomail.com; s=zohoarc; b=REIhZx8lb+ZuWlAAjAPara6IeJM2gUJt+wIFXdVf34q5PFaCy+tIASliaGYhJm89iQdDooYa0mJQwIb86Fi5QFL6VP2r+3FmG0ND+7PMTjf+QGSib9zfFpLj/UQDTUh/zfUdQ7sBn4vo6FrPWJ5ycYPwY1reyEffc1HIbhcWmzo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612740216; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9gknr3qlLHrPVofS5zv6p1SYehluW78knvLtOubYhBs=; b=Y0IcykiBjIi1ck+6kyoojvV5rLXC5N51IB47mliJJE87kea+cc20nDJOx6CaDfzNtPuaoVPnMs2IPKYyLynvsKSIegXNWlTK/iaNak3QJjZNN4YzrWAJnoJiDlUpwoXEU+gjsBKQ1gEyXKRGNSshwGQyj1FBlMTPHz10aQkiUME= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) by mx.zohomail.com with SMTPS id 1612740216342941.1886930169368; Sun, 7 Feb 2021 15:23:36 -0800 (PST) Received: by mail-wm1-f42.google.com with SMTP id j11so11147841wmi.3 for ; Sun, 07 Feb 2021 15:23:35 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id e10sm24315162wro.65.2021.02.07.15.23.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 15:23:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9gknr3qlLHrPVofS5zv6p1SYehluW78knvLtOubYhBs=; b=K1AaafdYfn0sBrm+KdYQJAGu13yoJyk/44KneP29aXMPf/9RL7wbXwv7enDMeXR8tG /XuGjf+uAIKFmqwYv7PpvhzNyH4LmfOlux/5XFu6+tDrz1e7uvByNMY4StPMoRM6yC7+ 0evGxHJPAXFHJdP0jUM3wtH9MvFFUulsPJFi5AsAaUe3q2xEcYVtcqXbU/c/nS/sG3HY x5hGdI4HSEtrBnwHNAvHwVPQAa80SRIKMwLDxuaWfIk/of/Z25GE5ExlWUaf/jGIy89j TE2M2PqdEWRCWK8lqc5fmIWpB/Mcy9MKv1QtHsZlClyoziZspXHVZ5f9QUgCkYrvKJr7 r2Iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=9gknr3qlLHrPVofS5zv6p1SYehluW78knvLtOubYhBs=; b=UttPPEKCxdX4ETWxF+iDVW93tDeIMJ0TLRcoQmvQKUuKtExXA1xgtre9n0FUJSe30v cgzbd7gn5Y4ZhFy5C7gD36DOHzQukoNxMf+zmeJwRVg+xvQLFOGUR5WWNdTnku7nwfEt Nnr8LnLE6pxeg9Y4eLE6uePhNy4CNjQNX0m2xySs5uR+MylrChgbUAD+WqNlu78F+4QG 4p0nLAZcXjO2Di6eQ6BaU3t7CHPGj1thfgD1L2l5YUQScwWLVrT8YbkN9bq+tluLLdpv fyIUdX1xSqB0iClOckV0OsIIQkcW19djTMDNkFPDqq3OiqTX1RCJM2l3Iv/r/9wxbr4U W+zw== X-Gm-Message-State: AOAM530VFc1wsHg/j+qV2TVjxGCVTod96qvKC3OxGQ6W55Wguf1Nwz2X uvFrRCXpm5/jM0PmbE4EhxI= X-Google-Smtp-Source: ABdhPJxC60ACe0vE/X8upoWTKt/bY8N5fxgL8wrEih7fHr44FtHzW3qjMJzC63oI76VmJSIKv+s0fQ== X-Received: by 2002:a1c:6308:: with SMTP id x8mr12528249wmb.78.1612740214536; Sun, 07 Feb 2021 15:23:34 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato , Paolo Bonzini , Aurelien Jarno , Sagar Karandikar , Palmer Dabbelt , Laurent Vivier , qemu-arm@nongnu.org, Claudio Fontana , Peter Maydell , Richard Henderson , Alistair Francis , Jiaxun Yang , Aleksandar Rikalo , qemu-riscv@nongnu.org Subject: [PATCH v2 4/6] accel/tcg: Include missing "tcg/tcg.h" header Date: Mon, 8 Feb 2021 00:23:08 +0100 Message-Id: <20210207232310.2505283-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210207232310.2505283-1-f4bug@amsat.org> References: <20210207232310.2505283-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Commit 3468b59e18b ("tcg: enable multiple TCG contexts in softmmu") introduced use of typedef/prototypes declared in "tcg/tcg.h" without including it. This was not a problem because "tcg/tcg.h" is pulled in by "exec/cpu_ldst.h". To be able to remove this header there, we first need to include it here in op_helper.c, else we get: accel/tcg/tcg-accel-ops-mttcg.c: In function =E2=80=98mttcg_cpu_thread_fn= =E2=80=99: accel/tcg/tcg-accel-ops-mttcg.c:52:5: error: implicit declaration of func= tion =E2=80=98tcg_register_thread=E2=80=99; did you mean =E2=80=98rcu_regis= ter_thread=E2=80=99? [-Werror=3Dimplicit-function-declaration] 52 | tcg_register_thread(); | ^~~~~~~~~~~~~~~~~~~ | rcu_register_thread accel/tcg/tcg-accel-ops-mttcg.c:52:5: error: nested extern declaration of= =E2=80=98tcg_register_thread=E2=80=99 [-Werror=3Dnested-externs] cc1: all warnings being treated as errors accel/tcg/tcg-accel-ops-rr.c: In function =E2=80=98rr_cpu_thread_fn=E2=80= =99: accel/tcg/tcg-accel-ops-rr.c:153:5: error: implicit declaration of functi= on =E2=80=98tcg_register_thread=E2=80=99; did you mean =E2=80=98rcu_registe= r_thread=E2=80=99? [-Werror=3Dimplicit-function-declaration] 153 | tcg_register_thread(); | ^~~~~~~~~~~~~~~~~~~ | rcu_register_thread accel/tcg/tcg-accel-ops-rr.c:153:5: error: nested extern declaration of = =E2=80=98tcg_register_thread=E2=80=99 [-Werror=3Dnested-externs] cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e --- accel/tcg/tcg-accel-ops-mttcg.c | 1 + accel/tcg/tcg-accel-ops-rr.c | 1 + 2 files changed, 2 insertions(+) diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttc= g.c index 42973fb062b..ddbca6c5b8c 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -32,6 +32,7 @@ #include "exec/exec-all.h" #include "hw/boards.h" =20 +#include "tcg/tcg.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-mttcg.h" =20 diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index 4a66055e0d7..1bb1d0f8f1c 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -32,6 +32,7 @@ #include "exec/exec-all.h" #include "hw/boards.h" =20 +#include "tcg/tcg.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-rr.h" #include "tcg-accel-ops-icount.h" --=20 2.26.2 From nobody Tue Nov 18 19:49:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) client-ip=209.85.128.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1612740221; cv=none; d=zohomail.com; s=zohoarc; b=JmbdnKZc/+RQ7E1qQCJW6oN/Cf6cgtehgtintBUTSUpLJDLdoM4paXMtxX5/90JaC72dmP4wofC/akmh7tJmxw5jWwndCUswCJShSqYDdWVcZdgcjVWMAFXuWJv6OSmmfiUitmACiJIEx0e8CqyfYI4HMTyrVqfNOI1N9JARQTI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612740221; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=imFQGKJBgIE298lnVAuxYDCszjx31PWDfQloLbhmsMQ=; b=lvRmQ5mvOxfTwY8bPGvM6NyoEB63CsVw9pSqQZN/F7MW/D0AfMpkmqrMUTwIH18ryF8Ke2+pvSJ8fq+tkFsC11CUOgl7kOUdXdjrOcmaP4I5y4sxYgebhLZ9/rOobBRkoyZZo2vFiI5+A60gopIXFX2y6zzjV437Nvu4E3s/N5k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) by mx.zohomail.com with SMTPS id 1612740221798295.5209381364092; Sun, 7 Feb 2021 15:23:41 -0800 (PST) Received: by mail-wm1-f51.google.com with SMTP id 190so11169375wmz.0 for ; Sun, 07 Feb 2021 15:23:41 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id o9sm26708567wrw.81.2021.02.07.15.23.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 15:23:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=imFQGKJBgIE298lnVAuxYDCszjx31PWDfQloLbhmsMQ=; b=jRfVShxCvoHj4VIdXI31W8+mms47QKtM/dYAbewXt33U3qwjP+25jHorFrShriMLfR 6yrVo/Ew3pAD+/Z3diDybMuIj5u6epsQxB7C241FvlXXZeV0g0a6Hj04uj01Cj6sLOLp pEzCGhE3HMKQ7FOCHIw8EeVJMcwntoFal6fon3OayqoB3OhNVaTkK/hF3QzvrybV8Zt9 5h/4+2Z/AxVFHi4ewFBBtIKamyNOW2BL1dhamqZslKsBo9R/Xhzlxz4kHNUpNN0PjY9B glbOr1ZSs81mLNFLi89Ky1tPf1r6X6xqQveTQmGHf/+s5jBLSRpC9aaIXVp2Y55dr5qD /LPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=imFQGKJBgIE298lnVAuxYDCszjx31PWDfQloLbhmsMQ=; b=Y+2cQ6/f4SJhxgz1JOTU3vXqjho2XPy2IlxSIToCg0MuPFAyFUQd8yi+OIMHU3pEQN WHt4DpYOZzW44SQ3ETuUC8SlSOYMXl0CGtHA7CEGQV7P2VVnaH/odKtM5C62G4lXnQbb 85EAlBTx0TVGS0m4NRCRV/9Zftdzybbh4Mit4rdBcV8qy5qDlD8SZiEiektX7U5190QF U73TksboS5+d3vX5PqzKd619e4diCDlqe9r7OFkYJtWbEO7+ShZwf1t62njudWkOfIdC 37bg+U+uENXQPaQUWGqjwwDcxXyE27Ur/pbrsNl7zr791XdZo7vDtoO7ZfZ3YglBDvWx YeQg== X-Gm-Message-State: AOAM531bUJNztPTFrg7W3q0oJS0c3hDFvr+ZvLHR+xDbL/Mk4U7SYzXA CZ01LC17VHchkeUpIpBRTYY= X-Google-Smtp-Source: ABdhPJwDN8+BIrRLVWqNQox4XrA+rwoqz+xuYjuBQqhBTRYwtR5A+IjXfxnAZnvhz091w3y2sDUcvg== X-Received: by 2002:a05:600c:4105:: with SMTP id j5mr12536306wmi.0.1612740220035; Sun, 07 Feb 2021 15:23:40 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato , Paolo Bonzini , Aurelien Jarno , Sagar Karandikar , Palmer Dabbelt , Laurent Vivier , qemu-arm@nongnu.org, Claudio Fontana , Peter Maydell , Richard Henderson , Alistair Francis , Jiaxun Yang , Aleksandar Rikalo , qemu-riscv@nongnu.org Subject: [RFC PATCH v2 5/6] accel/tcg: Refactor debugging tlb_assert_iotlb_entry_for_ptr_present() Date: Mon, 8 Feb 2021 00:23:09 +0100 Message-Id: <20210207232310.2505283-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210207232310.2505283-1-f4bug@amsat.org> References: <20210207232310.2505283-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Refactor debug code as tlb_assert_iotlb_entry_for_ptr_present() helper. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e --- What this code does is out of my league, but refactoring it allow keeping tlb_addr_write() local to accel/tcg/cputlb.c in the next patch. --- include/exec/exec-all.h | 9 +++++++++ accel/tcg/cputlb.c | 14 ++++++++++++++ target/arm/mte_helper.c | 11 ++--------- target/arm/sve_helper.c | 10 ++-------- 4 files changed, 27 insertions(+), 17 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f933c74c446..c5e8e355b7f 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -296,6 +296,15 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulo= ng vaddr, void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); + +/* + * Find the iotlbentry for ptr. This *must* be present in the TLB + * because we just found the mapping. + */ +void tlb_assert_iotlb_entry_for_ptr_present(CPUArchState *env, int ptr_mmu= _idx, + uint64_t ptr, + MMUAccessType ptr_access, + uintptr_t index); #else static inline void tlb_init(CPUState *cpu) { diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 8a7b779270a..a6247da34a0 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -429,6 +429,20 @@ void tlb_flush_all_cpus_synced(CPUState *src_cpu) tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, ALL_MMUIDX_BITS); } =20 +void tlb_assert_iotlb_entry_for_ptr_present(CPUArchState *env, int ptr_mmu= _idx, + uint64_t ptr, + MMUAccessType ptr_access, + uintptr_t index) +{ +#ifdef CONFIG_DEBUG_TCG + CPUTLBEntry *entry =3D tlb_entry(env, ptr_mmu_idx, ptr); + target_ulong comparator =3D (ptr_access =3D=3D MMU_DATA_LOAD + ? entry->addr_read + : tlb_addr_write(entry)); + g_assert(tlb_hit(comparator, ptr)); +#endif +} + static bool tlb_hit_page_mask_anyprot(CPUTLBEntry *tlb_entry, target_ulong page, target_ulong mask) { diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 6cea9d1b506..f47d3b4570e 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -111,15 +111,8 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, i= nt ptr_mmu_idx, * matching tlb entry + iotlb entry. */ index =3D tlb_index(env, ptr_mmu_idx, ptr); -# ifdef CONFIG_DEBUG_TCG - { - CPUTLBEntry *entry =3D tlb_entry(env, ptr_mmu_idx, ptr); - target_ulong comparator =3D (ptr_access =3D=3D MMU_DATA_LOAD - ? entry->addr_read - : tlb_addr_write(entry)); - g_assert(tlb_hit(comparator, ptr)); - } -# endif + tlb_assert_iotlb_entry_for_ptr_present(env, ptr_mmu_idx, ptr, + ptr_access, index); iotlbentry =3D &env_tlb(env)->d[ptr_mmu_idx].iotlb[index]; =20 /* If the virtual page MemAttr !=3D Tagged, access unchecked. */ diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index c8cdf7618eb..a5708da0f2f 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4089,14 +4089,8 @@ static bool sve_probe_page(SVEHostPage *info, bool n= ofault, { uintptr_t index =3D tlb_index(env, mmu_idx, addr); =20 -# ifdef CONFIG_DEBUG_TCG - CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong comparator =3D (access_type =3D=3D MMU_DATA_LOAD - ? entry->addr_read - : tlb_addr_write(entry)); - g_assert(tlb_hit(comparator, addr)); -# endif - + tlb_assert_iotlb_entry_for_ptr_present(env, mmu_idx, addr, + access_type, index); CPUIOTLBEntry *iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[inde= x]; info->attrs =3D iotlbentry->attrs; } --=20 2.26.2 From nobody Tue Nov 18 19:49:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) client-ip=209.85.221.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1612740227; cv=none; d=zohomail.com; s=zohoarc; b=Ft3idBVAF5NJifO5ixRawXVQhRDnFUFSe3PFTSBeCTgsDfPtFQQFiB2jVEDUaRghcB2DwSx/5oHVzmmZGPZ8iWdSefu5gRj4+SKMBzrTneuawAPvF3a611Z+eG7POH4QyQ2rLbtoWP2QoHBNKnuwXsKqbTIc2dD3nOdwXKxfKaM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612740227; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1gVWXaMf3oEyIVlaRSD52U7PW5E6+zv5BhWBd9cIe8U=; b=CONghZqA40qmTvbG2wljHOMm2GcZE1u1Vl0d7X88xdn7CT8au8aJL+2VTuqHLM+8IfJLwcKzWtzxqMIG8Cm7YIYHD7mlXaKF3lMwWglbkrfX85AP2vsGFtnENoRT7FOrE1tmCDTSX3qbD8z2p9j8u36dxT+HWR9EzakuvWCabpg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) by mx.zohomail.com with SMTPS id 1612740227107512.0292606581694; Sun, 7 Feb 2021 15:23:47 -0800 (PST) Received: by mail-wr1-f54.google.com with SMTP id z6so15071857wrq.10 for ; Sun, 07 Feb 2021 15:23:46 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id i20sm16845931wmq.7.2021.02.07.15.23.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 15:23:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1gVWXaMf3oEyIVlaRSD52U7PW5E6+zv5BhWBd9cIe8U=; b=dieu8kT6DPBl7biaAhh2IbRiZhFKJaDFtk8m6kE+KmZajs5PsD1IaEptYuYVKkUY7s Zfp9qKFNP+WDAMPdffILTbNrvQq1heYfVgX1TPSaPi5ByDfYNKVVhcSfHp6gAk1Qe7Ai Bx5YjO9bpLdGH6RRCxeG6CA/hxdfRypv8ID45uC7g5gJuZaVTq7ygkRyAzoutHrUlj7Q m8656dYNQyRWAcJnb/0xf0cOvtVAvmBEbfu4Fd63Dh/+JmfX2vXd0yVHwMEdRqYfmYBc niDhY+KUHqvcoLVASRNe2zpwRw+0EEzg21aOGkiWWs/L843DuKj6mhFsAf0zdrgd55Lq xNjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=1gVWXaMf3oEyIVlaRSD52U7PW5E6+zv5BhWBd9cIe8U=; b=siZqwqShMBgnnEsN084sPfUzcW6MR3oNjQA0A60pTKkfhZpsCx+v8+850uDj1H2ps4 kGaAX4XKSK9q2rlto2fPlzCSFaKytuBwn+yCYFjYeLMEKGOEltEhT7xm49CxnwC3sRgC 1/4ApXmvp6v1BJIpAfQvpg7pNjNU+xAb58JAdekXD79L3NA4llAn9W6E7I/4aERUnFNG T6xiZdZQZUXUQF3cy7ZVxpSWCamUtDGLMBnw+94MxAZaWa9REzTUCNtrt3pz51+HDosi B6FC6jIDFtNVP7WedTa2ndWzN0EIDjwqtb4i7Ux8xJZo+Irx/qUDtDgNNbvftDnYc1Ro Hh3Q== X-Gm-Message-State: AOAM533Y1tHvHKgoFOhdeV2yG1+aSH68XbjM6csw5e95NtVdbgEQs5Xn N07eBnDM6G3gB4C69dqj8Js= X-Google-Smtp-Source: ABdhPJyVklY2iZR1qB2FvBdZpCQETYGMgFD+Uou4udI+xcdPBlAgXW06g+snhQC2056ftJigqmzpHw== X-Received: by 2002:a5d:5910:: with SMTP id v16mr17553674wrd.29.1612740225386; Sun, 07 Feb 2021 15:23:45 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato , Paolo Bonzini , Aurelien Jarno , Sagar Karandikar , Palmer Dabbelt , Laurent Vivier , qemu-arm@nongnu.org, Claudio Fontana , Peter Maydell , Richard Henderson , Alistair Francis , Jiaxun Yang , Aleksandar Rikalo , qemu-riscv@nongnu.org Subject: [PATCH v2 6/6] exec/cpu_ldst: Move tlb* declarations to "exec/exec-all.h" Date: Mon, 8 Feb 2021 00:23:10 +0100 Message-Id: <20210207232310.2505283-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210207232310.2505283-1-f4bug@amsat.org> References: <20210207232310.2505283-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Keep MMU functions in "exec/cpu_ldst.h", and move TLB functions to "exec/exec-all.h". As tlb_addr_write() is only called in accel/tcg/cputlb.c, make move it there as a static function. Doing so we removed the "tcg/tcg.h" dependency on "exec/cpu_ldst.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu_ldst.h | 28 ---------------------------- include/exec/exec-all.h | 16 ++++++++++++++++ accel/tcg/cputlb.c | 9 +++++++++ 3 files changed, 25 insertions(+), 28 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index ef54cb7e1f8..c1753a64dfd 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -291,34 +291,6 @@ static inline void cpu_stq_le_mmuidx_ra(CPUArchState *= env, abi_ptr addr, =20 #else =20 -/* Needed for TCG_OVERSIZED_GUEST */ -#include "tcg/tcg.h" - -static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry) -{ -#if TCG_OVERSIZED_GUEST - return entry->addr_write; -#else - return qatomic_read(&entry->addr_write); -#endif -} - -/* Find the TLB index corresponding to the mmu_idx + address pair. */ -static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx, - target_ulong addr) -{ - uintptr_t size_mask =3D env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY= _BITS; - - return (addr >> TARGET_PAGE_BITS) & size_mask; -} - -/* Find the TLB entry corresponding to the mmu_idx + address pair. */ -static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, - target_ulong addr) -{ - return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)]; -} - uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, int mmu_idx, uintptr_t ra); int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index c5e8e355b7f..8e54b537189 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -297,6 +297,22 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); =20 +/* Find the TLB index corresponding to the mmu_idx + address pair. */ +static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx, + target_ulong addr) +{ + uintptr_t size_mask =3D env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY= _BITS; + + return (addr >> TARGET_PAGE_BITS) & size_mask; +} + +/* Find the TLB entry corresponding to the mmu_idx + address pair. */ +static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, + target_ulong addr) +{ + return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)]; +} + /* * Find the iotlbentry for ptr. This *must* be present in the TLB * because we just found the mapping. diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a6247da34a0..084d19b52d7 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -429,6 +429,15 @@ void tlb_flush_all_cpus_synced(CPUState *src_cpu) tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, ALL_MMUIDX_BITS); } =20 +static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry) +{ +#if TCG_OVERSIZED_GUEST + return entry->addr_write; +#else + return qatomic_read(&entry->addr_write); +#endif +} + void tlb_assert_iotlb_entry_for_ptr_present(CPUArchState *env, int ptr_mmu= _idx, uint64_t ptr, MMUAccessType ptr_access, --=20 2.26.2