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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id 17sm5576104wmf.32.2021.02.07.14.58.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 14:58:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6n5uXZgPlc77dVVpesg0vBLpgeFYV6lVDwxVtKrTEDs=; b=YeIVFRo/yRcs5SJWzrCfTiCArWRYrocnMn4X6kziKbr6MhW++SX1PtCyEyGQZd+kGY tOlwZBr+7deQFsdQKadLsMBe4ASJUp+HSxxuDNVPaYBJueRZb/C/C7WxJG3D79ppRhCQ iUGrCEcXFdQ+iWmNmK92/f4EmX4IbTeA5ugKv/A9s9bxOkxNpN2xcGcziJfE+il5CvtD YMlJZhd3zUNQlcdDVcVSAQUb5uQeyzWmnoK7HFXi4aa86VSSoDlHL20qdudrv20O/NR/ MOWVDWVvrqiS26OgljeMyyq5Ghc+JvAtqQu6GVOFuNeDLUwGmos1txKeX3hoYIjq41hY YB8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=6n5uXZgPlc77dVVpesg0vBLpgeFYV6lVDwxVtKrTEDs=; b=SzVfUyJjEEjPqIvDao+IkuQy3cCznt8DQ1giE+X54WEQa9RJFb4kljaPxBBPHvuHoe orZEXdBNf9uCoe9waeo7/GiZSSRnSgbO6Zpz4BBmMNuwOdkcUU/hFWnyje/vsgneCJfy VZuQM31AEwcWCCJXQ6mTtvFUdT0QP+LewdlFr53qcUbs7WoZHQdUgneqiHojoAlxjSG/ kS6M30M4viJCg9O8IVrLJ1Kh59wuUnEGOoBd4fDftJ4qDWeTnWWi4nA5OPzDkFiYf4oA OqimCC77FFvxWKIMt7Eijly0EybveDo3wMUVhJBs6FTQJIIYygN7PN5u5qi5oJuqObZB rRnw== X-Gm-Message-State: AOAM531Ptx6nsqV6ifnbCdkqNBn+K0Qv1nUZf01g41s2FcVqpvkXOnx7 qL/ehqQvH+6BhYUIcvMXlXc= X-Google-Smtp-Source: ABdhPJyKaYBwlx4Ml54sqgoR2xi2FkiFtZqoUWQNFBtJf7BoZU6GfNpggY5XvhO7fwh2CTDqXSBgBg== X-Received: by 2002:adf:9148:: with SMTP id j66mr17301090wrj.28.1612738693175; Sun, 07 Feb 2021 14:58:13 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Bastian Koppelmann , Peter Maydell , Claudio Fontana , Paolo Bonzini , Yoshinori Sato , Aleksandar Rikalo , qemu-arm@nongnu.org, Aurelien Jarno , qemu-riscv@nongnu.org, Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Alistair Francis , Sagar Karandikar , Jiaxun Yang Subject: [PATCH 6/6] exec/cpu_ldst: Move tlb* declarations to "exec/exec-all.h" Date: Sun, 7 Feb 2021 23:57:38 +0100 Message-Id: <20210207225738.2482987-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210207225738.2482987-1-f4bug@amsat.org> References: <20210207225738.2482987-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Keep MMU functions in "exec/cpu_ldst.h", and move TLB functions to "exec/exec-all.h". As tlb_addr_write() is only called in accel/tcg/cputlb.c, make move it there as a static function. Doing so we removed the "tcg/tcg.h" dependency on "exec/cpu_ldst.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu_ldst.h | 52 ----------------------------------------- include/exec/exec-all.h | 38 ++++++++++++++++++++++++++++++ accel/tcg/cputlb.c | 9 +++++++ 3 files changed, 47 insertions(+), 52 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index ef54cb7e1f8..cb0a096497f 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -291,34 +291,6 @@ static inline void cpu_stq_le_mmuidx_ra(CPUArchState *= env, abi_ptr addr, =20 #else =20 -/* Needed for TCG_OVERSIZED_GUEST */ -#include "tcg/tcg.h" - -static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry) -{ -#if TCG_OVERSIZED_GUEST - return entry->addr_write; -#else - return qatomic_read(&entry->addr_write); -#endif -} - -/* Find the TLB index corresponding to the mmu_idx + address pair. */ -static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx, - target_ulong addr) -{ - uintptr_t size_mask =3D env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY= _BITS; - - return (addr >> TARGET_PAGE_BITS) & size_mask; -} - -/* Find the TLB entry corresponding to the mmu_idx + address pair. */ -static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, - target_ulong addr) -{ - return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)]; -} - uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, int mmu_idx, uintptr_t ra); int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, @@ -422,28 +394,4 @@ static inline int cpu_ldsw_code(CPUArchState *env, abi= _ptr addr) return (int16_t)cpu_lduw_code(env, addr); } =20 -/** - * tlb_vaddr_to_host: - * @env: CPUArchState - * @addr: guest virtual address to look up - * @access_type: 0 for read, 1 for write, 2 for execute - * @mmu_idx: MMU index to use for lookup - * - * Look up the specified guest virtual index in the TCG softmmu TLB. - * If we can translate a host virtual address suitable for direct RAM - * access, without causing a guest exception, then return it. - * Otherwise (TLB entry is for an I/O access, guest software - * TLB fill required, etc) return NULL. - */ -#ifdef CONFIG_USER_ONLY -static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, - MMUAccessType access_type, int mmu_i= dx) -{ - return g2h(addr); -} -#else -void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, - MMUAccessType access_type, int mmu_idx); -#endif - #endif /* CPU_LDST_H */ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index c5e8e355b7f..5024b9abd4a 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -297,6 +297,38 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); =20 +/** + * tlb_vaddr_to_host: + * @env: CPUArchState + * @addr: guest virtual address to look up + * @access_type: 0 for read, 1 for write, 2 for execute + * @mmu_idx: MMU index to use for lookup + * + * Look up the specified guest virtual index in the TCG softmmu TLB. + * If we can translate a host virtual address suitable for direct RAM + * access, without causing a guest exception, then return it. + * Otherwise (TLB entry is for an I/O access, guest software + * TLB fill required, etc) return NULL. + */ +void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, + MMUAccessType access_type, int mmu_idx); + +/* Find the TLB index corresponding to the mmu_idx + address pair. */ +static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx, + target_ulong addr) +{ + uintptr_t size_mask =3D env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY= _BITS; + + return (addr >> TARGET_PAGE_BITS) & size_mask; +} + +/* Find the TLB entry corresponding to the mmu_idx + address pair. */ +static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, + target_ulong addr) +{ + return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)]; +} + /* * Find the iotlbentry for ptr. This *must* be present in the TLB * because we just found the mapping. @@ -374,6 +406,12 @@ tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState= *cpu, target_ulong addr, uint16_t idxmap, unsigned bi= ts) { } + +static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, + MMUAccessType access_type, int mmu_i= dx) +{ + return g2h(addr); +} #endif /** * probe_access: diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a6247da34a0..084d19b52d7 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -429,6 +429,15 @@ void tlb_flush_all_cpus_synced(CPUState *src_cpu) tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, ALL_MMUIDX_BITS); } =20 +static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry) +{ +#if TCG_OVERSIZED_GUEST + return entry->addr_write; +#else + return qatomic_read(&entry->addr_write); +#endif +} + void tlb_assert_iotlb_entry_for_ptr_present(CPUArchState *env, int ptr_mmu= _idx, uint64_t ptr, MMUAccessType ptr_access, --=20 2.26.2