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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id h14sm18355487wmq.45.2021.02.07.14.57.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 14:57:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1+/tMS8+lcjG3CT8AZjxjSJSDoUQYqmsaNIWbdboyjk=; b=qAjNQw8ReHPB08ee9rNAf3mETr0TMoWDRFBYDdk/m1RggnZiop0DJ8bZ7Zx87eMAhV 7oOIf5Eel4tva5PbSLIIkWe03QFepVh+e46hJeiiAlS3EcuDG6zUTD3erm39TQB3wtL1 RSNBgGtYi8CwRXcH7ciJ0zViQNSNBrwnE4L+nSZgFUVTF3rVTnnXpkQrtLUbCVsjxcrp XQxiFRHYIDknIbSrzTWRnZpP6X5aTaSkovgn2MslarRXE1kOKPnUsj2M3HA+GAEGvhnQ B4t7cfZ9qU8aQMo0878Wg+eCT4eMRbWv18dea0Gr7ZxMTabCB8P4TywPTMH3X2SjyjiM 1Q9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=1+/tMS8+lcjG3CT8AZjxjSJSDoUQYqmsaNIWbdboyjk=; b=hoCHQmtOG74XT06LZcJWlPINdsKLrNFUTBmIcCKrVaoVMEn9267JeFMIKOfbiJSEmL dXzWfJ+/4jB6uX8KMPauhq+gGfjVMD8i04+W1iJxthtWa/AInoGIVCMBJ+QMLVSD6OmZ t3INfsX02vXSJ0AAP4R1sh6q267l9Hy1EnhHl+j40Vk04nYCzTVkhMFUCyouvPuEJHQ/ xFMGvj3PSQh3H4aZFDyJP4tPvp2vCtmUhlWix3TJ3cQeysJkfNFSC0wIej5Mm/7Hheg2 0U2EVMCVcEHxkikWdhpItiqyQgsD7Bn5tqnHerBi//1Aqyz4MuR6MoCfm0I/FRrveYRU TnMA== X-Gm-Message-State: AOAM531Ytdn4WBZ7FJlTqwTVBu6rgS1edslO4N9A5BoTZA2wUMA/c/nK oNpF2qn3oZQg9k3EmSJ36nc= X-Google-Smtp-Source: ABdhPJw5AHY7EwN/DBv3E4A9gTdNfx71QdGvsQdTAEvDUN7KIE6wb07RsQZb6U13rqbiFMuZfCo80w== X-Received: by 2002:a05:600c:4e8e:: with SMTP id f14mr12277659wmq.139.1612738666709; Sun, 07 Feb 2021 14:57:46 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Bastian Koppelmann , Peter Maydell , Claudio Fontana , Paolo Bonzini , Yoshinori Sato , Aleksandar Rikalo , qemu-arm@nongnu.org, Aurelien Jarno , qemu-riscv@nongnu.org, Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Alistair Francis , Sagar Karandikar , Jiaxun Yang Subject: [RFC PATCH 1/6] target: Replace tcg_debug_assert() by assert() Date: Sun, 7 Feb 2021 23:57:33 +0100 Message-Id: <20210207225738.2482987-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210207225738.2482987-1-f4bug@amsat.org> References: <20210207225738.2482987-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Since commit 262a69f4282 ("osdep.h: Prohibit disabling assert() in supported builds") we can not build QEMU with assert() disabled. tcg_debug_assert() does nothing until QEMU is configured with --enable-debug-tcg. Since there is no obvious logic whether to use tcg_debug_assert() or assert() for files under target/, simplify by using plain assert() everywhere. Keep tcg_debug_assert() for the tcg/ and accel/ directories. Patch created mechanically using: $ sed -i s/tcg_debug_assert/assert/ \ $(git grep -l tcg_debug_assert target/) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- If there is a logic, we should document it, and include "tcg/tcg.h" in these files. --- target/arm/translate.h | 4 +-- target/arm/mte_helper.c | 4 +-- target/arm/sve_helper.c | 8 +++--- target/arm/translate-a64.c | 12 ++++----- target/arm/translate-sve.c | 4 +-- target/arm/translate.c | 36 ++++++++++++------------- target/hppa/translate.c | 4 +-- target/rx/op_helper.c | 6 ++--- target/rx/translate.c | 14 +++++----- target/sh4/translate.c | 4 +-- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 11 files changed, 49 insertions(+), 49 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 423b0e08df0..e2ddf87629c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -220,7 +220,7 @@ static inline void set_pstate_bits(uint32_t bits) { TCGv_i32 p =3D tcg_temp_new_i32(); =20 - tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); + assert(!(bits & CACHED_PSTATE_BITS)); =20 tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); tcg_gen_ori_i32(p, p, bits); @@ -233,7 +233,7 @@ static inline void clear_pstate_bits(uint32_t bits) { TCGv_i32 p =3D tcg_temp_new_i32(); =20 - tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); + assert(!(bits & CACHED_PSTATE_BITS)); =20 tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); tcg_gen_andi_i32(p, p, ~bits); diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 153bd1e9df8..6cea9d1b506 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -166,8 +166,8 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, * not set in the cputlb lookup above. */ mr =3D memory_region_from_host(host, &ptr_ra); - tcg_debug_assert(mr !=3D NULL); - tcg_debug_assert(memory_region_is_ram(mr)); + assert(mr !=3D NULL); + assert(memory_region_is_ram(mr)); ptr_paddr =3D ptr_ra; do { ptr_paddr +=3D mr->addr; diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 844db08bd57..c8cdf7618eb 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4030,7 +4030,7 @@ static intptr_t find_next_active(uint64_t *vg, intptr= _t reg_off, reg_off +=3D ctz64(pg); =20 /* We should never see an out of range predicate bit set. */ - tcg_debug_assert(reg_off < reg_max); + assert(reg_off < reg_max); return reg_off; } =20 @@ -4186,7 +4186,7 @@ static bool sve_cont_ldst_elements(SVEContLdSt *info,= target_ulong addr, /* No active elements, no pages touched. */ return false; } - tcg_debug_assert(reg_off_last >=3D 0 && reg_off_last < reg_max); + assert(reg_off_last >=3D 0 && reg_off_last < reg_max); =20 info->reg_off_first[0] =3D reg_off_first; info->mem_off_first[0] =3D (reg_off_first >> esz) * msize; @@ -4235,7 +4235,7 @@ static bool sve_cont_ldst_elements(SVEContLdSt *info,= target_ulong addr, * this may affect the address reported in an exception. */ reg_off_split =3D find_next_active(vg, reg_off_split, reg_max, esz); - tcg_debug_assert(reg_off_split <=3D reg_off_last); + assert(reg_off_split <=3D reg_off_last); info->reg_off_first[1] =3D reg_off_split; info->mem_off_first[1] =3D (reg_off_split >> esz) * msize; info->reg_off_last[1] =3D reg_off_last; @@ -4794,7 +4794,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const = target_ulong addr, /* Probe the page(s). */ if (!sve_cont_ldst_pages(&info, fault, env, addr, MMU_DATA_LOAD, retad= dr)) { /* Fault on first element. */ - tcg_debug_assert(fault =3D=3D FAULT_NO); + assert(fault =3D=3D FAULT_NO); memset(vd, 0, reg_max); goto do_fault; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ffc060e5d70..f570506133c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -144,7 +144,7 @@ static void set_btype(DisasContext *s, int val) TCGv_i32 tcg_val; =20 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */ - tcg_debug_assert(val >=3D 1 && val <=3D 3); + assert(val >=3D 1 && val <=3D 3); =20 tcg_val =3D tcg_const_i32(val); tcg_gen_st_i32(tcg_val, cpu_env, offsetof(CPUARMState, btype)); @@ -10659,7 +10659,7 @@ static void handle_vec_simd_shri(DisasContext *s, b= ool is_q, bool is_u, unallocated_encoding(s); return; } - tcg_debug_assert(size <=3D 3); + assert(size <=3D 3); =20 if (!fp_access_check(s)) { return; @@ -12812,7 +12812,7 @@ static void disas_simd_two_reg_misc(DisasContext *s= , uint32_t insn) /* Coverity claims (size =3D=3D 3 && !is_q) has been eliminated * from all paths leading to here. */ - tcg_debug_assert(is_q); + assert(is_q); for (pass =3D 0; pass < 2; pass++) { TCGv_i64 tcg_op =3D tcg_temp_new_i64(); TCGv_i64 tcg_res =3D tcg_temp_new_i64(); @@ -14615,7 +14615,7 @@ static void disas_a64_insn(CPUARMState *env, DisasC= ontext *s) s->guarded_page =3D is_guarded_page(env, s); =20 /* First insn can have btype set to non-zero. */ - tcg_debug_assert(s->btype >=3D 0); + assert(s->btype >=3D 0); =20 /* * Note that the Branch Target Exception has fairly high @@ -14633,7 +14633,7 @@ static void disas_a64_insn(CPUARMState *env, DisasC= ontext *s) } } else { /* Not the first insn: btype must be 0. */ - tcg_debug_assert(s->btype =3D=3D 0); + assert(s->btype =3D=3D 0); } } =20 @@ -14733,7 +14733,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, =20 #ifdef CONFIG_USER_ONLY /* In sve_probe_page, we assume TBI is enabled. */ - tcg_debug_assert(dc->tbid & 1); + assert(dc->tbid & 1); #endif =20 /* Single step state. The code-generation logic here is: diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 27402af23c0..a1e327f863e 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3938,8 +3938,8 @@ static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCM= LA_zzxz *a) gen_helper_gvec_fcmlas_idx, }; =20 - tcg_debug_assert(a->esz =3D=3D 1 || a->esz =3D=3D 2); - tcg_debug_assert(a->rd =3D=3D a->ra); + assert(a->esz =3D=3D 1 || a->esz =3D=3D 2); + assert(a->rd =3D=3D a->ra); if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F= 16 : FPST_FPCR); diff --git a/target/arm/translate.c b/target/arm/translate.c index 1653cca1aaa..04ebfcc0d6d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2972,7 +2972,7 @@ void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_= ofs, uint32_t rn_ofs, static gen_helper_gvec_3_ptr * const fns[2] =3D { gen_helper_gvec_qrdmlah_s16, gen_helper_gvec_qrdmlah_s32 }; - tcg_debug_assert(vece >=3D 1 && vece <=3D 2); + assert(vece >=3D 1 && vece <=3D 2); gen_gvec_fn3_qc(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, fns[vece - 1]); } =20 @@ -2982,7 +2982,7 @@ void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_= ofs, uint32_t rn_ofs, static gen_helper_gvec_3_ptr * const fns[2] =3D { gen_helper_gvec_qrdmlsh_s16, gen_helper_gvec_qrdmlsh_s32 }; - tcg_debug_assert(vece >=3D 1 && vece <=3D 2); + assert(vece >=3D 1 && vece <=3D 2); gen_gvec_fn3_qc(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, fns[vece - 1]); } =20 @@ -3105,8 +3105,8 @@ void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, ui= nt32_t rm_ofs, }; =20 /* tszimm encoding produces immediates in the range [1..esize]. */ - tcg_debug_assert(shift > 0); - tcg_debug_assert(shift <=3D (8 << vece)); + assert(shift > 0); + assert(shift <=3D (8 << vece)); =20 /* * Shifts larger than the element size are architecturally valid. @@ -3181,8 +3181,8 @@ void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, ui= nt32_t rm_ofs, }; =20 /* tszimm encoding produces immediates in the range [1..esize]. */ - tcg_debug_assert(shift > 0); - tcg_debug_assert(shift <=3D (8 << vece)); + assert(shift > 0); + assert(shift <=3D (8 << vece)); =20 /* * Shifts larger than the element size are architecturally valid. @@ -3290,8 +3290,8 @@ void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, u= int32_t rm_ofs, }; =20 /* tszimm encoding produces immediates in the range [1..esize] */ - tcg_debug_assert(shift > 0); - tcg_debug_assert(shift <=3D (8 << vece)); + assert(shift > 0); + assert(shift <=3D (8 << vece)); =20 if (shift =3D=3D (8 << vece)) { /* @@ -3386,8 +3386,8 @@ void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, u= int32_t rm_ofs, }; =20 /* tszimm encoding produces immediates in the range [1..esize] */ - tcg_debug_assert(shift > 0); - tcg_debug_assert(shift <=3D (8 << vece)); + assert(shift > 0); + assert(shift <=3D (8 << vece)); =20 /* * Shifts larger than the element size are architecturally valid. @@ -3491,8 +3491,8 @@ void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, u= int32_t rm_ofs, }; =20 /* tszimm encoding produces immediates in the range [1..esize] */ - tcg_debug_assert(shift > 0); - tcg_debug_assert(shift <=3D (8 << vece)); + assert(shift > 0); + assert(shift <=3D (8 << vece)); =20 if (shift =3D=3D (8 << vece)) { /* @@ -3606,8 +3606,8 @@ void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, u= int32_t rm_ofs, }; =20 /* tszimm encoding produces immediates in the range [1..esize] */ - tcg_debug_assert(shift > 0); - tcg_debug_assert(shift <=3D (8 << vece)); + assert(shift > 0); + assert(shift <=3D (8 << vece)); =20 tcg_gen_gvec_2i(rd_ofs, rm_ofs, opr_sz, max_sz, shift, &ops[vece]); } @@ -3695,8 +3695,8 @@ void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uin= t32_t rm_ofs, }; =20 /* tszimm encoding produces immediates in the range [1..esize]. */ - tcg_debug_assert(shift > 0); - tcg_debug_assert(shift <=3D (8 << vece)); + assert(shift > 0); + assert(shift <=3D (8 << vece)); =20 /* Shift of esize leaves destination unchanged. */ if (shift < (8 << vece)) { @@ -3788,8 +3788,8 @@ void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uin= t32_t rm_ofs, }; =20 /* tszimm encoding produces immediates in the range [0..esize-1]. */ - tcg_debug_assert(shift >=3D 0); - tcg_debug_assert(shift < (8 << vece)); + assert(shift >=3D 0); + assert(shift < (8 << vece)); =20 if (shift =3D=3D 0) { tcg_gen_gvec_mov(vece, rd_ofs, rm_ofs, opr_sz, max_sz); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 64af1e0d5cc..ceb3bacc7dd 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1945,8 +1945,8 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg de= st, for the indirect branch consumes no special resources, we can (conditionally) skip B and continue execution. */ /* The use_nullify_skip test implies we have a known control path.= */ - tcg_debug_assert(ctx->iaoq_b !=3D -1); - tcg_debug_assert(ctx->iaoq_n !=3D -1); + assert(ctx->iaoq_b !=3D -1); + assert(ctx->iaoq_n !=3D -1); =20 /* We do have to handle the non-local temporary, DEST, before branching. Since IOAQ_F is not really live at this point, we diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c index 4d315b44492..03d285fbafe 100644 --- a/target/rx/op_helper.c +++ b/target/rx/op_helper.c @@ -234,7 +234,7 @@ static void (* const cpu_stfn[])(CPUArchState *env, =20 void helper_sstr(CPURXState *env, uint32_t sz) { - tcg_debug_assert(sz < 3); + assert(sz < 3); while (env->regs[3] !=3D 0) { cpu_stfn[sz](env, env->regs[1], env->regs[2], GETPC()); env->regs[1] +=3D 1 << sz; @@ -283,7 +283,7 @@ void helper_smovb(CPURXState *env) void helper_suntil(CPURXState *env, uint32_t sz) { uint32_t tmp; - tcg_debug_assert(sz < 3); + assert(sz < 3); if (env->regs[3] =3D=3D 0) { return ; } @@ -302,7 +302,7 @@ void helper_suntil(CPURXState *env, uint32_t sz) void helper_swhile(CPURXState *env, uint32_t sz) { uint32_t tmp; - tcg_debug_assert(sz < 3); + assert(sz < 3); if (env->regs[3] =3D=3D 0) { return ; } diff --git a/target/rx/translate.c b/target/rx/translate.c index 9ea941c6302..ff12af4f7f8 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -87,7 +87,7 @@ static uint32_t li(DisasContext *ctx, int sz) CPURXState *env =3D ctx->env; addr =3D ctx->base.pc_next; =20 - tcg_debug_assert(sz < 4); + assert(sz < 4); switch (sz) { case 1: ctx->base.pc_next +=3D 1; @@ -201,7 +201,7 @@ static inline TCGv rx_index_addr(DisasContext *ctx, TCG= v mem, { uint32_t dsp; =20 - tcg_debug_assert(ld < 3); + assert(ld < 3); switch (ld) { case 0: return cpu_regs[reg]; @@ -222,7 +222,7 @@ static inline TCGv rx_index_addr(DisasContext *ctx, TCG= v mem, static inline MemOp mi_to_mop(unsigned mi) { static const MemOp mop[5] =3D { MO_SB, MO_SW, MO_UL, MO_UW, MO_UB }; - tcg_debug_assert(mi < 5); + assert(mi < 5); return mop[mi]; } =20 @@ -258,7 +258,7 @@ static int is_privileged(DisasContext *ctx, int is_exce= ption) /* generate QEMU condition */ static void psw_cond(DisasCompare *dc, uint32_t cond) { - tcg_debug_assert(cond < 16); + assert(cond < 16); switch (cond) { case 0: /* z */ dc->cond =3D TCG_COND_EQ; @@ -1401,7 +1401,7 @@ static inline void shiftr_imm(uint32_t rd, uint32_t r= s, uint32_t imm, static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) =3D { tcg_gen_shri_i32, tcg_gen_sari_i32, }; - tcg_debug_assert(alith < 2); + assert(alith < 2); if (imm) { gen_sXri[alith](cpu_regs[rd], cpu_regs[rs], imm - 1); tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); @@ -1425,7 +1425,7 @@ static inline void shiftr_reg(uint32_t rd, uint32_t r= s, unsigned int alith) static void (* const gen_sXr[])(TCGv ret, TCGv arg1, TCGv arg2) =3D { tcg_gen_shr_i32, tcg_gen_sar_i32, }; - tcg_debug_assert(alith < 2); + assert(alith < 2); noshift =3D gen_new_label(); done =3D gen_new_label(); count =3D tcg_temp_new(); @@ -2282,7 +2282,7 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a) { TCGv vec; =20 - tcg_debug_assert(a->imm < 0x100); + assert(a->imm < 0x100); vec =3D tcg_const_i32(a->imm); tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); gen_helper_rxint(cpu_env, vec); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 93127906237..f12cc0830bf 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -339,7 +339,7 @@ static void gen_delayed_conditional_jump(DisasContext *= ctx) static inline void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { /* We have already signaled illegal instruction for odd Dr. */ - tcg_debug_assert((reg & 1) =3D=3D 0); + assert((reg & 1) =3D=3D 0); reg ^=3D ctx->fbank; tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]); } @@ -347,7 +347,7 @@ static inline void gen_load_fpr64(DisasContext *ctx, TC= Gv_i64 t, int reg) static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { /* We have already signaled illegal instruction for odd Dr. */ - tcg_debug_assert((reg & 1) =3D=3D 0); + assert((reg & 1) =3D=3D 0); reg ^=3D ctx->fbank; tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t); } diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 887c6b88831..f0e6e844f5f 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -992,7 +992,7 @@ static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t = dofs, uint32_t aofs, .vece =3D MO_64 }, }; =20 - tcg_debug_assert(vece <=3D MO_64); + assert(vece <=3D MO_64); tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &rsub_op[vece]); } =20 --=20 2.26.2 From nobody Tue Nov 18 19:45:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.53 as permitted sender) client-ip=209.85.128.53; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id r11sm18905340wmh.9.2021.02.07.14.57.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 14:57:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H7DdpVZKuaTFU+QINWMbbbomeFKhPW3S4eDxwf+nJCo=; b=DuwqKccHtBt4dz86RKdnXAtbY1C6a2HgS+5yvCWHJgZFtaXXGTwchErp5vAQyTjPq6 zpDQmq0x0jdwDD9c+O6S01GcEyxWMNZP55PSPzqFB9FWlSW1Ri8O7Wlshqg+s4xaTeAS hRqp7tWRf4EJVztY/4rSkH7FGLB2XnXK2wacllpoOaBiRbXuEtSXeJWDNGEiGOY1/qyn VMQgLGtoxwmohWvTGx0uBr6Zb9T2McbRsYj8f7FgJ3xX6HoXOVFsGmDjg7YQSTjzv3zE UmdR0rIismdm6Vbdy0zaFmpb2SYcPt95TFl5ioS4vJ5x0rUEcZ5JX2Ayhdik84KTEPjm rcvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=H7DdpVZKuaTFU+QINWMbbbomeFKhPW3S4eDxwf+nJCo=; b=YVaJaHVkNGGfGiC3pPt7lpIAaIFF6NQECeTokYBVd53q2d8bH5SyMWAKozPGWWRMai N1BXl/+wiBYPH+iw4q4HY5vcIPh3qdHhBDEPhHGehW8DFAkqeC56CqYM/vQyhgK7x0e4 FHGupZh/5k4GGM8jcei2KB0juiYAwhpfDFKf18MgTV0M/EdAo5calsOkCYvxkgCYHhf0 ydAcbbAR0NhNvFvUxI6is9XSNwy7FExeZjvwXwIuOBqjnY/jVt/A/y1puCE+Vid5cGwW rGFAvD8BQMV1qJeW3fMo4hAb/Dqk53kvf6Pe0yrfBaB01qPSXHfY4/haJTb1elQ5eEYN gNAQ== X-Gm-Message-State: AOAM530vQ4gMwK3Y6NUwjIJ1+6qgFJt3Hh5xKaN98F6SQJPTeqHhTvH/ g+p4xAgnIz9ZlrgfWADH1AY= X-Google-Smtp-Source: ABdhPJwwUp3pd9IOFWEbOPAGSNqjz7Z9MdmROAusVzFJqHVWJmI2Yzh/PuF0aoHSDrcg1CGoH1St0A== X-Received: by 2002:a1c:6802:: with SMTP id d2mr11968962wmc.32.1612738672031; Sun, 07 Feb 2021 14:57:52 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Bastian Koppelmann , Peter Maydell , Claudio Fontana , Paolo Bonzini , Yoshinori Sato , Aleksandar Rikalo , qemu-arm@nongnu.org, Aurelien Jarno , qemu-riscv@nongnu.org, Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Alistair Francis , Sagar Karandikar , Jiaxun Yang Subject: [PATCH 2/6] target/m68k: Include missing "tcg/tcg.h" header Date: Sun, 7 Feb 2021 23:57:34 +0100 Message-Id: <20210207225738.2482987-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210207225738.2482987-1-f4bug@amsat.org> References: <20210207225738.2482987-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Commit 14f944063af ("target-m68k: add cas/cas2 ops") introduced use of typedef/prototypes declared in "tcg/tcg.h" without including it. This was not a problem because "tcg/tcg.h" is pulled in by "exec/cpu_ldst.h". To be able to remove this header there, we first need to include it here in op_helper.c, else we get: [953/1018] Compiling C object libqemu-m68k-softmmu.fa.p/target_m68k_op_he= lper.c.o target/m68k/op_helper.c: In function =E2=80=98do_cas2l=E2=80=99: target/m68k/op_helper.c:774:5: error: unknown type name =E2=80=98TCGMemOp= Idx=E2=80=99 774 | TCGMemOpIdx oi; | ^~~~~~~~~~~ target/m68k/op_helper.c:787:18: error: implicit declaration of function = =E2=80=98make_memop_idx=E2=80=99 [-Werror=3Dimplicit-function-declaration] 787 | oi =3D make_memop_idx(MO_BEQ, mmu_idx); | ^~~~~~~~~~~~~~ target/m68k/op_helper.c:787:18: error: nested extern declaration of =E2= =80=98make_memop_idx=E2=80=99 [-Werror=3Dnested-externs] target/m68k/op_helper.c:788:17: error: implicit declaration of function = =E2=80=98helper_atomic_cmpxchgq_be_mmu=E2=80=99; did you mean =E2=80=98help= er_atomic_cmpxchgq_be=E2=80=99? [-Werror=3Dimplicit-function-declaration] 788 | l =3D helper_atomic_cmpxchgq_be_mmu(env, a1, c, u, oi= , ra); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | helper_atomic_cmpxchgq_be target/m68k/op_helper.c:788:17: error: nested extern declaration of =E2= =80=98helper_atomic_cmpxchgq_be_mmu=E2=80=99 [-Werror=3Dnested-externs] cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/m68k/op_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 202498deb51..36b68fd318f 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" +#include "tcg/tcg.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" --=20 2.26.2 From nobody Tue Nov 18 19:45:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1612738678; cv=none; d=zohomail.com; s=zohoarc; b=BQk1Au5s586df+QgF24gq9eoVwC6lfLfJYtPWo8AOmZsp59ocrcYUpYm45BfwOvnb7jmI6Q3+WVFa5RiaiebOPyxtdazWmunWFU5XfOyMaW5mVfb/FJW8iu8/gJ8EaH9rdE26olMX4JgFkkis6jo25zObiSfWp3fGjzKg870l/c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612738678; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NB0PxeiyUnyh7a2jT9hNZ8p231d4tVFomh4sbxGsRA8=; b=flW3kpBwhWFPEZAhxEbAETANAUUZFjHPP6zAcsaXWyn5KDrfiHyQLrYhZMkD+LP9X4qV077Jf7NIwQ/qFkWz+jKt7hGn3T9XcHjER2Cxu6lWRdgNuveijJ888lqP59C7B21pS0O4+F2ENO5p30sJOUvBI3XdBkkUX6O6YOWrsZk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by mx.zohomail.com with SMTPS id 1612738678896626.5688005291038; Sun, 7 Feb 2021 14:57:58 -0800 (PST) Received: by mail-wr1-f42.google.com with SMTP id u14so15122026wri.3 for ; Sun, 07 Feb 2021 14:57:58 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id x22sm11914204wmc.25.2021.02.07.14.57.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 14:57:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NB0PxeiyUnyh7a2jT9hNZ8p231d4tVFomh4sbxGsRA8=; b=slRltlSuqvMFAGDBp3viXRI6JthnwFNxMwx6RyJ4j3hm6GV/kR9+8aqbOR6+A3BzxM 0gtAC2rKPePsftfbo2XRRqavnfHOHTTxZenueD1DBEgcyFvQOWS+b1CAFlPgNuIcf2S6 Ub1CbWlMaUNAY2o2E745DxA/eCYW2hPoYn2eeziOfZuk1dKP+bavqtGruhPoSODD1Li7 HcHGRTZPvnMhyio06yyhs0bIZiJJTDHJ0OiqQ4Wqq+hYWmXbiFlQbr59xigi+VYUCHS8 J6++DG236usVcnz+B7fXf4m4ssOQcjrHqq5+b5KzQETJUVxdEL6UiXPvpSV2R6qrDNyC Hf9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=NB0PxeiyUnyh7a2jT9hNZ8p231d4tVFomh4sbxGsRA8=; b=fRl8VwZMH1Si578jMBSZJzqbqrnmgBF4THYiC29M/vLHZ9fNElJD2dWCSRYSPYguYx QYR7y2kZloKOY1RHU1kEx6eKYGToVRn8re220v1G+LiMr4JVFNfqa+06ORQ0EhUAx3PS 61NYN9rvRbo9NZm0XIeLVeiEqaJCCvlKfhMuZL3taDPWdJmqmAqEIMR8ix7lhMiYXjPn qEgYNoc0KH1FpL9pfMd1VNtjyyliUSFUsM69Q2crGeVj2pPX4C8e/sDeZhcBBtljkg84 B2UgaGb4MgPdD+AG0woquYU1nEi24Eys274qASk0YwoJ2yvm87c2/AcbilG6gXRRQWFz Z27w== X-Gm-Message-State: AOAM53025iQ8J5tJEh2+X+OpDbLYc2o3f9eWRizRGX44gAzm8UETb94s +7Kh6z2P389BplxdUoUgq/c= X-Google-Smtp-Source: ABdhPJwLDjFqLd5L/mM0ElOOSdXdRjOEnmrWm2sULZ8NwEYj/DXiJdrswdakwvI4ZhxHWX0b3IF7MA== X-Received: by 2002:a5d:4646:: with SMTP id j6mr17052829wrs.38.1612738677165; Sun, 07 Feb 2021 14:57:57 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Bastian Koppelmann , Peter Maydell , Claudio Fontana , Paolo Bonzini , Yoshinori Sato , Aleksandar Rikalo , qemu-arm@nongnu.org, Aurelien Jarno , qemu-riscv@nongnu.org, Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Alistair Francis , Sagar Karandikar , Jiaxun Yang Subject: [PATCH 3/6] target/mips: Include missing "tcg/tcg.h" header Date: Sun, 7 Feb 2021 23:57:35 +0100 Message-Id: <20210207225738.2482987-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210207225738.2482987-1-f4bug@amsat.org> References: <20210207225738.2482987-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Commit 83be6b54123 ("Fix MSA instructions LD. on big endian host") introduced use of typedef/prototypes declared in "tcg/tcg.h" without including it. This was not a problem because "tcg/tcg.h" is pulled in by "exec/cpu_ldst.h". To be able to remove this header there, we first need to include it here in op_helper.c, else we get: [222/337] Compiling C object libqemu-mips-softmmu.fa.p/target_mips_msa_he= lper.c.o target/mips/msa_helper.c: In function =E2=80=98helper_msa_ld_b=E2=80=99: target/mips/msa_helper.c:8214:9: error: unknown type name =E2=80=98TCGMem= OpIdx=E2=80=99 8214 | TCGMemOpIdx oi =3D make_memop_idx(MO_TE | DF | MO_UNALN, = \ | ^~~~~~~~~~~ target/mips/msa_helper.c:8224:5: note: in expansion of macro =E2=80=98MEM= OP_IDX=E2=80=99 8224 | MEMOP_IDX(DF_BYTE) | ^~~~~~~~~ target/mips/msa_helper.c:8214:26: error: implicit declaration of function= =E2=80=98make_memop_idx=E2=80=99 [-Werror=3Dimplicit-function-declaration] 8214 | TCGMemOpIdx oi =3D make_memop_idx(MO_TE | DF | MO_UNALN, = \ | ^~~~~~~~~~~~~~ target/mips/msa_helper.c:8227:18: error: implicit declaration of function= =E2=80=98helper_ret_ldub_mmu=E2=80=99 [-Werror=3Dimplicit-function-declara= tion] 8227 | pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE= ), oi, GETPC()); | ^~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/msa_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 1298a1917ce..4caefe29ad7 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internal.h" +#include "tcg/tcg.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exec/memop.h" --=20 2.26.2 From nobody Tue Nov 18 19:45:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) client-ip=209.85.221.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1612738684; cv=none; d=zohomail.com; s=zohoarc; b=PwfuliXfBTngyZBgImrJXWzWKxDhfXQ5n3gVvcD03LULjhts9vVxoGCI30VO5M/5dHcZRNAkurzhbaDyxJ+iKhSlrDVHvIFlsQXRQahYOtZWeZpIfwaEvkkhgNS41E3zWOM3dTaM9xZRBjnBxWjQZnBsEdVZEtziC47E1eDTwss= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612738684; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9gknr3qlLHrPVofS5zv6p1SYehluW78knvLtOubYhBs=; b=VvPpDpb1HiSeJj+LpSZYTxncstdsJDQDeocgKR2nZQVdhQpDeulf7ZqHgqGC8TP7R9MCX/1BlU5Pq+Pz2NEK5ZhR/5wfmIbzN1tZRtx3OS/EmdLC3bvjV/D668fieUco63v0BawUcYCXw+zLDdmfGZpfnha0R6i3ilE9TV83/R0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) by mx.zohomail.com with SMTPS id 1612738684280980.6756838997968; Sun, 7 Feb 2021 14:58:04 -0800 (PST) Received: by mail-wr1-f46.google.com with SMTP id q7so15023184wre.13 for ; Sun, 07 Feb 2021 14:58:03 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id z4sm24488281wrw.38.2021.02.07.14.58.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 14:58:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9gknr3qlLHrPVofS5zv6p1SYehluW78knvLtOubYhBs=; b=QPiUsnBXh6zQA8cvIUf9ti97QrSwqi3bDBEnuY07Vz4fILCRyGjOwtnK45kK464dio 5WPadZImBIr6aw0k5vyV2uxqYyLHPOjixZqCz0vPdEbSAlDrWHBk2FbdYxS7MSjbbTtY LbN4tD7GhzEeQKmyOx3+luv7KS33p5yTjoXR2f5V7BC/WPbyi2AlqOJj0mDZVbZxIMYo GzFaodM5Tae7XL4Q2MlxhUh6WLujp9P5Py0gpaRn2H/R+GJQYrRkc6iNooaSges3oLKW jpVdP4BbjkgLrJmJoB1qHno80cPvPoOSb3thRC3FrbOnwGT6+wNG4fll+jgztTGlEdTs 16Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=9gknr3qlLHrPVofS5zv6p1SYehluW78knvLtOubYhBs=; b=Q3nLbcsW1U9u/CSMVg0TJVE9ZnmTVTwQnxxqvp2UiwtwoobUe8ANB5DupuEAD+7X5+ kY/SzEY/5/gkFvE2wP6CsnQtfySYLvDwxyYvTpTUf2KKNtJfUrzOXavGXXrkgjYXzybf FgOPM8kWu64KYX6eXbgg+1sZ51A6tqpEgUI1eM3f3H6uqw5h23BVh90bmCHd2CWgvClh jJmrok6Ay0tUKkcFl2yU3l+a0YE1jvefKTnSmJteBe6N+Vke7aEcFIZ7wpSGj83WOXCW kLzyoa0remig2jOJ3mzMCUHpyAnspylCnYtEu0RNwZjYXHrcAdxFQz/pN+sbeWJkvuXg x2Vw== X-Gm-Message-State: AOAM53282WZCUkWypBbgO2WTu5win/N26EX9eZbh5SHz0rMJTGP3cYN/ V4EXknfh31f9Lxs8DfjZ2+k= X-Google-Smtp-Source: ABdhPJwmtUdPun0LfupoJgX97gEgxC4Lsu0OtQsJR7cY6J+fqgd3HrNrCOxT9sTkn64oSwfDnHymeg== X-Received: by 2002:a5d:6a02:: with SMTP id m2mr17045630wru.364.1612738682431; Sun, 07 Feb 2021 14:58:02 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Bastian Koppelmann , Peter Maydell , Claudio Fontana , Paolo Bonzini , Yoshinori Sato , Aleksandar Rikalo , qemu-arm@nongnu.org, Aurelien Jarno , qemu-riscv@nongnu.org, Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Alistair Francis , Sagar Karandikar , Jiaxun Yang Subject: [PATCH 4/6] accel/tcg: Include missing "tcg/tcg.h" header Date: Sun, 7 Feb 2021 23:57:36 +0100 Message-Id: <20210207225738.2482987-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210207225738.2482987-1-f4bug@amsat.org> References: <20210207225738.2482987-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Commit 3468b59e18b ("tcg: enable multiple TCG contexts in softmmu") introduced use of typedef/prototypes declared in "tcg/tcg.h" without including it. This was not a problem because "tcg/tcg.h" is pulled in by "exec/cpu_ldst.h". To be able to remove this header there, we first need to include it here in op_helper.c, else we get: accel/tcg/tcg-accel-ops-mttcg.c: In function =E2=80=98mttcg_cpu_thread_fn= =E2=80=99: accel/tcg/tcg-accel-ops-mttcg.c:52:5: error: implicit declaration of func= tion =E2=80=98tcg_register_thread=E2=80=99; did you mean =E2=80=98rcu_regis= ter_thread=E2=80=99? [-Werror=3Dimplicit-function-declaration] 52 | tcg_register_thread(); | ^~~~~~~~~~~~~~~~~~~ | rcu_register_thread accel/tcg/tcg-accel-ops-mttcg.c:52:5: error: nested extern declaration of= =E2=80=98tcg_register_thread=E2=80=99 [-Werror=3Dnested-externs] cc1: all warnings being treated as errors accel/tcg/tcg-accel-ops-rr.c: In function =E2=80=98rr_cpu_thread_fn=E2=80= =99: accel/tcg/tcg-accel-ops-rr.c:153:5: error: implicit declaration of functi= on =E2=80=98tcg_register_thread=E2=80=99; did you mean =E2=80=98rcu_registe= r_thread=E2=80=99? [-Werror=3Dimplicit-function-declaration] 153 | tcg_register_thread(); | ^~~~~~~~~~~~~~~~~~~ | rcu_register_thread accel/tcg/tcg-accel-ops-rr.c:153:5: error: nested extern declaration of = =E2=80=98tcg_register_thread=E2=80=99 [-Werror=3Dnested-externs] cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/tcg-accel-ops-mttcg.c | 1 + accel/tcg/tcg-accel-ops-rr.c | 1 + 2 files changed, 2 insertions(+) diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttc= g.c index 42973fb062b..ddbca6c5b8c 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -32,6 +32,7 @@ #include "exec/exec-all.h" #include "hw/boards.h" =20 +#include "tcg/tcg.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-mttcg.h" =20 diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index 4a66055e0d7..1bb1d0f8f1c 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -32,6 +32,7 @@ #include "exec/exec-all.h" #include "hw/boards.h" =20 +#include "tcg/tcg.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-rr.h" #include "tcg-accel-ops-icount.h" --=20 2.26.2 From nobody Tue Nov 18 19:45:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.45 as permitted sender) client-ip=209.85.128.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1612738689; cv=none; d=zohomail.com; s=zohoarc; b=Z5e8Kw5FZT5j9M4IwF2EDIk7il5t191XHYInuaC6htnecVjRP5jHYJ9mcTW1U7lwohOYKOH+DbZuNS4yhpmS6RiY4hlXzMraiscP94irLt1ZvHGY/x21davJMjDaj6DbbsW5iYbL9COhP5UfkeFRbnb8Zv3fJi5j0i/q14rbXY8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612738689; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=imFQGKJBgIE298lnVAuxYDCszjx31PWDfQloLbhmsMQ=; b=X9Ix3TF9349pIwcsx/U2AF/mVV1NDYDq8VJP89zNk2hDYI+3LoYUJO28XH1uHhIrQRx8a0W9kWux4GgNN2AdH9mdS2lUsaNUMb3g20DPKBKykjSe4akrbaZsvjiourxYlzcGrOQZUUipZ5Tgdn9rQUiwWqdkeJUtutLyZC1KDmI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by mx.zohomail.com with SMTPS id 1612738689671789.9267566525159; Sun, 7 Feb 2021 14:58:09 -0800 (PST) Received: by mail-wm1-f45.google.com with SMTP id 190so11144182wmz.0 for ; Sun, 07 Feb 2021 14:58:09 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id z6sm6300217wmi.39.2021.02.07.14.58.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 14:58:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=imFQGKJBgIE298lnVAuxYDCszjx31PWDfQloLbhmsMQ=; b=ccqfoVFWKhdwHfQk7EbK+L+WxFtzyD2lU54qDn3jgzJBdMirDaUQk7vEegZZYvh5pJ RprOm+NyNZeYKPsmdBydtNPkZQfQycmxtC1V+7juepQlohVEx/0KEdKVTYlLplACS3WE km9oxVD3WQZNG68qlnfzSJb1QsaEeDNZJT/PGaq8s75GNyq9pM/Er94AKuRLeXjp1tlj pVaEdHgsyHt1K1gIVFnXc4Wv0Taq+HupGxWlkDkCpR/q2mhxWcuN4uYpiPUKl8XZ2DKV 5zcV1t79HCt1Yg3Xcj3IkC3HFx082SYlE59JYxbdXDM0o82JuN1Ks2XWWqMhcM90icRI KPtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=imFQGKJBgIE298lnVAuxYDCszjx31PWDfQloLbhmsMQ=; b=sNALV5hmcbTbFMYTsnoaPlPyNH6x2+HPHFEeiqrmHTof6yNhmLqudXyzsEGu6/6Mdd Vt7IW2tivFLwPOfUggxq7EuXxXthq+imeRQHO3hhGU71ajLcla0ccbfn+bzbaH8eL2Qp PUaok9M65bVPol1d+bycsDc82/TRVM73VrDVS1bDHdCqXzxGAUs8xlrgeaHWr7aN82OV +p3QwEosqIeSO8VSdlcCWFEYyRjpqQgHHOePHCvzvXgsTvAve+wueuqZ6yQSrKVoBNDX 4ZtAYB3/FuYNk6au/OUfXv5M4bwl0UIfrLd1nptD0usQHFlvYPSeHD28NOO/P8rzCxXd zX3A== X-Gm-Message-State: AOAM5333bUrXZsF1z3mxEXk9ZNU8ljsC73UQr1Spi1c/KLVIdZQdusUK 0eq7n1PA10OSmOn4oh4ejDY= X-Google-Smtp-Source: ABdhPJw/1Snq5MMokBjwZDAYrhfP9rZn2CbyxktT5w7GVWiOTMd+hThpFCk39XUsnjoTLmsK7GY4pw== X-Received: by 2002:a7b:cb4f:: with SMTP id v15mr12379534wmj.162.1612738687873; Sun, 07 Feb 2021 14:58:07 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Bastian Koppelmann , Peter Maydell , Claudio Fontana , Paolo Bonzini , Yoshinori Sato , Aleksandar Rikalo , qemu-arm@nongnu.org, Aurelien Jarno , qemu-riscv@nongnu.org, Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Alistair Francis , Sagar Karandikar , Jiaxun Yang Subject: [RFC PATCH 5/6] accel/tcg: Refactor debugging tlb_assert_iotlb_entry_for_ptr_present() Date: Sun, 7 Feb 2021 23:57:37 +0100 Message-Id: <20210207225738.2482987-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210207225738.2482987-1-f4bug@amsat.org> References: <20210207225738.2482987-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Refactor debug code as tlb_assert_iotlb_entry_for_ptr_present() helper. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- What this code does is out of my league, but refactoring it allow keeping tlb_addr_write() local to accel/tcg/cputlb.c in the next patch. --- include/exec/exec-all.h | 9 +++++++++ accel/tcg/cputlb.c | 14 ++++++++++++++ target/arm/mte_helper.c | 11 ++--------- target/arm/sve_helper.c | 10 ++-------- 4 files changed, 27 insertions(+), 17 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f933c74c446..c5e8e355b7f 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -296,6 +296,15 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulo= ng vaddr, void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); + +/* + * Find the iotlbentry for ptr. This *must* be present in the TLB + * because we just found the mapping. + */ +void tlb_assert_iotlb_entry_for_ptr_present(CPUArchState *env, int ptr_mmu= _idx, + uint64_t ptr, + MMUAccessType ptr_access, + uintptr_t index); #else static inline void tlb_init(CPUState *cpu) { diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 8a7b779270a..a6247da34a0 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -429,6 +429,20 @@ void tlb_flush_all_cpus_synced(CPUState *src_cpu) tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, ALL_MMUIDX_BITS); } =20 +void tlb_assert_iotlb_entry_for_ptr_present(CPUArchState *env, int ptr_mmu= _idx, + uint64_t ptr, + MMUAccessType ptr_access, + uintptr_t index) +{ +#ifdef CONFIG_DEBUG_TCG + CPUTLBEntry *entry =3D tlb_entry(env, ptr_mmu_idx, ptr); + target_ulong comparator =3D (ptr_access =3D=3D MMU_DATA_LOAD + ? entry->addr_read + : tlb_addr_write(entry)); + g_assert(tlb_hit(comparator, ptr)); +#endif +} + static bool tlb_hit_page_mask_anyprot(CPUTLBEntry *tlb_entry, target_ulong page, target_ulong mask) { diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 6cea9d1b506..f47d3b4570e 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -111,15 +111,8 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, i= nt ptr_mmu_idx, * matching tlb entry + iotlb entry. */ index =3D tlb_index(env, ptr_mmu_idx, ptr); -# ifdef CONFIG_DEBUG_TCG - { - CPUTLBEntry *entry =3D tlb_entry(env, ptr_mmu_idx, ptr); - target_ulong comparator =3D (ptr_access =3D=3D MMU_DATA_LOAD - ? entry->addr_read - : tlb_addr_write(entry)); - g_assert(tlb_hit(comparator, ptr)); - } -# endif + tlb_assert_iotlb_entry_for_ptr_present(env, ptr_mmu_idx, ptr, + ptr_access, index); iotlbentry =3D &env_tlb(env)->d[ptr_mmu_idx].iotlb[index]; =20 /* If the virtual page MemAttr !=3D Tagged, access unchecked. */ diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index c8cdf7618eb..a5708da0f2f 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4089,14 +4089,8 @@ static bool sve_probe_page(SVEHostPage *info, bool n= ofault, { uintptr_t index =3D tlb_index(env, mmu_idx, addr); =20 -# ifdef CONFIG_DEBUG_TCG - CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong comparator =3D (access_type =3D=3D MMU_DATA_LOAD - ? entry->addr_read - : tlb_addr_write(entry)); - g_assert(tlb_hit(comparator, addr)); -# endif - + tlb_assert_iotlb_entry_for_ptr_present(env, mmu_idx, addr, + access_type, index); CPUIOTLBEntry *iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[inde= x]; info->attrs =3D iotlbentry->attrs; } --=20 2.26.2 From nobody Tue Nov 18 19:45:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1612738694; cv=none; d=zohomail.com; s=zohoarc; b=KHkhXb2I7d+KGU29QryfuHd2d+s0o1+fEs7lC29G1kY5llodAk0ebEahVnjQVZcLRzXZtRBm0cGujGFRYUfaWAmyi1VWHiDJoZqNoMaD9xgtTq4FcW094gGUEN5LE6X7YvGIYZCGhAYLUQJ7X7xmaEl4lQt4Ur2jcHkGQOHAwp8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612738694; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6n5uXZgPlc77dVVpesg0vBLpgeFYV6lVDwxVtKrTEDs=; b=hdrU9yKjQ5EetOAuYJho7eloo//kXG32yKWKaI/4ik9tN8eFkca7kmro9o6LAFhbn+C55eCbz65/5tLHVgJpUJ8zm0NtZB0sNYulmOeW/Kfwe/qqZ6o3kXbzdtrQWrl8aaOa/dYdbxYly8oq9UALOglvkmobdRKRUaIy1friUbg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by mx.zohomail.com with SMTPS id 1612738694888467.395997991376; Sun, 7 Feb 2021 14:58:14 -0800 (PST) Received: by mail-wr1-f49.google.com with SMTP id g10so15134506wrx.1 for ; Sun, 07 Feb 2021 14:58:14 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id 17sm5576104wmf.32.2021.02.07.14.58.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 14:58:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6n5uXZgPlc77dVVpesg0vBLpgeFYV6lVDwxVtKrTEDs=; b=YeIVFRo/yRcs5SJWzrCfTiCArWRYrocnMn4X6kziKbr6MhW++SX1PtCyEyGQZd+kGY tOlwZBr+7deQFsdQKadLsMBe4ASJUp+HSxxuDNVPaYBJueRZb/C/C7WxJG3D79ppRhCQ iUGrCEcXFdQ+iWmNmK92/f4EmX4IbTeA5ugKv/A9s9bxOkxNpN2xcGcziJfE+il5CvtD YMlJZhd3zUNQlcdDVcVSAQUb5uQeyzWmnoK7HFXi4aa86VSSoDlHL20qdudrv20O/NR/ MOWVDWVvrqiS26OgljeMyyq5Ghc+JvAtqQu6GVOFuNeDLUwGmos1txKeX3hoYIjq41hY YB8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=6n5uXZgPlc77dVVpesg0vBLpgeFYV6lVDwxVtKrTEDs=; b=SzVfUyJjEEjPqIvDao+IkuQy3cCznt8DQ1giE+X54WEQa9RJFb4kljaPxBBPHvuHoe orZEXdBNf9uCoe9waeo7/GiZSSRnSgbO6Zpz4BBmMNuwOdkcUU/hFWnyje/vsgneCJfy VZuQM31AEwcWCCJXQ6mTtvFUdT0QP+LewdlFr53qcUbs7WoZHQdUgneqiHojoAlxjSG/ kS6M30M4viJCg9O8IVrLJ1Kh59wuUnEGOoBd4fDftJ4qDWeTnWWi4nA5OPzDkFiYf4oA OqimCC77FFvxWKIMt7Eijly0EybveDo3wMUVhJBs6FTQJIIYygN7PN5u5qi5oJuqObZB rRnw== X-Gm-Message-State: AOAM531Ptx6nsqV6ifnbCdkqNBn+K0Qv1nUZf01g41s2FcVqpvkXOnx7 qL/ehqQvH+6BhYUIcvMXlXc= X-Google-Smtp-Source: ABdhPJyKaYBwlx4Ml54sqgoR2xi2FkiFtZqoUWQNFBtJf7BoZU6GfNpggY5XvhO7fwh2CTDqXSBgBg== X-Received: by 2002:adf:9148:: with SMTP id j66mr17301090wrj.28.1612738693175; Sun, 07 Feb 2021 14:58:13 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Bastian Koppelmann , Peter Maydell , Claudio Fontana , Paolo Bonzini , Yoshinori Sato , Aleksandar Rikalo , qemu-arm@nongnu.org, Aurelien Jarno , qemu-riscv@nongnu.org, Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Alistair Francis , Sagar Karandikar , Jiaxun Yang Subject: [PATCH 6/6] exec/cpu_ldst: Move tlb* declarations to "exec/exec-all.h" Date: Sun, 7 Feb 2021 23:57:38 +0100 Message-Id: <20210207225738.2482987-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210207225738.2482987-1-f4bug@amsat.org> References: <20210207225738.2482987-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Keep MMU functions in "exec/cpu_ldst.h", and move TLB functions to "exec/exec-all.h". As tlb_addr_write() is only called in accel/tcg/cputlb.c, make move it there as a static function. Doing so we removed the "tcg/tcg.h" dependency on "exec/cpu_ldst.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu_ldst.h | 52 ----------------------------------------- include/exec/exec-all.h | 38 ++++++++++++++++++++++++++++++ accel/tcg/cputlb.c | 9 +++++++ 3 files changed, 47 insertions(+), 52 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index ef54cb7e1f8..cb0a096497f 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -291,34 +291,6 @@ static inline void cpu_stq_le_mmuidx_ra(CPUArchState *= env, abi_ptr addr, =20 #else =20 -/* Needed for TCG_OVERSIZED_GUEST */ -#include "tcg/tcg.h" - -static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry) -{ -#if TCG_OVERSIZED_GUEST - return entry->addr_write; -#else - return qatomic_read(&entry->addr_write); -#endif -} - -/* Find the TLB index corresponding to the mmu_idx + address pair. */ -static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx, - target_ulong addr) -{ - uintptr_t size_mask =3D env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY= _BITS; - - return (addr >> TARGET_PAGE_BITS) & size_mask; -} - -/* Find the TLB entry corresponding to the mmu_idx + address pair. */ -static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, - target_ulong addr) -{ - return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)]; -} - uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, int mmu_idx, uintptr_t ra); int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, @@ -422,28 +394,4 @@ static inline int cpu_ldsw_code(CPUArchState *env, abi= _ptr addr) return (int16_t)cpu_lduw_code(env, addr); } =20 -/** - * tlb_vaddr_to_host: - * @env: CPUArchState - * @addr: guest virtual address to look up - * @access_type: 0 for read, 1 for write, 2 for execute - * @mmu_idx: MMU index to use for lookup - * - * Look up the specified guest virtual index in the TCG softmmu TLB. - * If we can translate a host virtual address suitable for direct RAM - * access, without causing a guest exception, then return it. - * Otherwise (TLB entry is for an I/O access, guest software - * TLB fill required, etc) return NULL. - */ -#ifdef CONFIG_USER_ONLY -static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, - MMUAccessType access_type, int mmu_i= dx) -{ - return g2h(addr); -} -#else -void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, - MMUAccessType access_type, int mmu_idx); -#endif - #endif /* CPU_LDST_H */ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index c5e8e355b7f..5024b9abd4a 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -297,6 +297,38 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); =20 +/** + * tlb_vaddr_to_host: + * @env: CPUArchState + * @addr: guest virtual address to look up + * @access_type: 0 for read, 1 for write, 2 for execute + * @mmu_idx: MMU index to use for lookup + * + * Look up the specified guest virtual index in the TCG softmmu TLB. + * If we can translate a host virtual address suitable for direct RAM + * access, without causing a guest exception, then return it. + * Otherwise (TLB entry is for an I/O access, guest software + * TLB fill required, etc) return NULL. + */ +void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, + MMUAccessType access_type, int mmu_idx); + +/* Find the TLB index corresponding to the mmu_idx + address pair. */ +static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx, + target_ulong addr) +{ + uintptr_t size_mask =3D env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY= _BITS; + + return (addr >> TARGET_PAGE_BITS) & size_mask; +} + +/* Find the TLB entry corresponding to the mmu_idx + address pair. */ +static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, + target_ulong addr) +{ + return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)]; +} + /* * Find the iotlbentry for ptr. This *must* be present in the TLB * because we just found the mapping. @@ -374,6 +406,12 @@ tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState= *cpu, target_ulong addr, uint16_t idxmap, unsigned bi= ts) { } + +static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, + MMUAccessType access_type, int mmu_i= dx) +{ + return g2h(addr); +} #endif /** * probe_access: diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a6247da34a0..084d19b52d7 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -429,6 +429,15 @@ void tlb_flush_all_cpus_synced(CPUState *src_cpu) tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, ALL_MMUIDX_BITS); } =20 +static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry) +{ +#if TCG_OVERSIZED_GUEST + return entry->addr_write; +#else + return qatomic_read(&entry->addr_write); +#endif +} + void tlb_assert_iotlb_entry_for_ptr_present(CPUArchState *env, int ptr_mmu= _idx, uint64_t ptr, MMUAccessType ptr_access, --=20 2.26.2