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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id c23sm12155149pgc.72.2021.02.05.14.58.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 14:58:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CDNDNmQVrH9FyBtOR/vi1j3G0RlDrYz84M7eOMXNK0Y=; b=gCzSHsehdILOE8mmsaXoi6yj6ZWep+nzraEGSf8qESevsMx1qaKSAHkU6CWg3o+hj4 khYnbWh3qGzFQynXaFGkaWp0MBVxUVGVpLo2K5eohf5HIZrGbG2YE8E6D+xn63Zc39q7 7Oh9z6zvhS+GL75SArTIAPWEZNHlp0WXWG6IXLfvjrViMBWf1+JzV9dy1eYiXfILFEqY I1yAWzIC4zCNfyq0liH+nu3kSG8cR5mAPbTYKgUTYRPzsLqjsuiylUnBwFxhMx9Rjzo3 qCPFJLos6JcxkVRA4SnvUMbmWtFTGPVT0IrbvyP2ZTGtZ2g9MOMaqIe6vNvxDHQhOygK ES8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CDNDNmQVrH9FyBtOR/vi1j3G0RlDrYz84M7eOMXNK0Y=; b=IHNR2LGQl5Jvv4irDRnynh+DUd1PKBLS4WdMYPl5LK+HUs2PtJ7edH9FgRJAolmr3a uQTEC0bcuhM3vUXfEKhfa0WMp32bS6QexxNqVfLJFRtZqCe6j2+kfkgSZb0dh6VhxVrk zjl+E4NBxdT1YdeR2Rx/OWJ5JfrThollcqtBnnIDPUb+QFyxJz7me4a1vBeqvQVxFUUn nVgWEg4iJhAOv45Lu8M5TBjcWw9+gkABDdOZfGnJBokpFOvsjKZ94YETMDH5HsLQxdt3 ECsysqPTaDDgxddXqC5Ni45XmsX4v+/cbIhEcxgnmvvkCVb8GBXHqRnsjGdkTEFOX/f6 w72Q== X-Gm-Message-State: AOAM532rpx1zzIKCRt/+LtUZmVX65+sXZVmAxJlEa3XfAn4Z0bonZ3V8 Z0jhY2f1jkxq1s417b7laNoJOwiq7Ts2BJ5L X-Google-Smtp-Source: ABdhPJwFQ84PMM3AoVQJbkOBdNHaXA8kl/uQ4fSUJlqHNH+LaVeoL6t0LhBa4YUxpTzAXG64UuhUVA== X-Received: by 2002:a63:dd17:: with SMTP id t23mr6627687pgg.320.1612565896418; Fri, 05 Feb 2021 14:58:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 43/46] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass Date: Fri, 5 Feb 2021 12:56:47 -1000 Message-Id: <20210205225650.1330794-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210205225650.1330794-1-richard.henderson@linaro.org> References: <20210205225650.1330794-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Claudio Fontana we cannot in principle make the TCG Operations field definitions conditional on CONFIG_TCG in code that is included by both common_ss and specific_ss modules. Therefore, what we can do safely to restrict the TCG fields to TCG-only builds, is to move all tcg cpu operations into a separate header file, which is only included by TCG, target-specific code. This leaves just a NULL pointer in the cpu.h for the non-TCG builds. This also tidies up the code in all targets a bit, having all TCG cpu operations neatly contained by a dedicated data struct. Signed-off-by: Claudio Fontana Message-Id: <20210204163931.7358-16-cfontana@suse.de> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 103 ++------------------------------ include/hw/core/tcg-cpu-ops.h | 97 ++++++++++++++++++++++++++++++ target/arm/internals.h | 6 ++ accel/tcg/cpu-exec.c | 27 +++++---- accel/tcg/cputlb.c | 35 +++++++++-- accel/tcg/user-exec.c | 9 +-- hw/mips/jazz.c | 7 ++- softmmu/physmem.c | 13 ++-- target/alpha/cpu.c | 21 +++++-- target/arm/cpu.c | 41 ++++++++----- target/arm/cpu64.c | 7 +-- target/arm/cpu_tcg.c | 28 +++++++-- target/avr/cpu.c | 19 ++++-- target/avr/helper.c | 5 +- target/cris/cpu.c | 43 ++++++++----- target/cris/helper.c | 5 +- target/hppa/cpu.c | 22 ++++--- target/i386/tcg/tcg-cpu.c | 26 ++++---- target/lm32/cpu.c | 19 ++++-- target/m68k/cpu.c | 19 ++++-- target/microblaze/cpu.c | 25 +++++--- target/mips/cpu.c | 36 +++++++---- target/moxie/cpu.c | 15 ++++- target/nios2/cpu.c | 18 ++++-- target/openrisc/cpu.c | 17 ++++-- target/riscv/cpu.c | 23 ++++--- target/rx/cpu.c | 20 +++++-- target/s390x/cpu.c | 33 ++++++---- target/sh4/cpu.c | 21 +++++-- target/sparc/cpu.c | 25 +++++--- target/tilegx/cpu.c | 17 ++++-- target/tricore/cpu.c | 12 +++- target/unicore32/cpu.c | 17 ++++-- target/xtensa/cpu.c | 23 ++++--- target/ppc/translate_init.c.inc | 33 ++++++---- MAINTAINERS | 1 + 36 files changed, 582 insertions(+), 306 deletions(-) create mode 100644 include/hw/core/tcg-cpu-ops.h diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index e76a49754d..4f6c6b18c9 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -76,78 +76,8 @@ typedef struct CPUWatchpoint CPUWatchpoint; =20 struct TranslationBlock; =20 -/** - * struct TcgCpuOperations: TCG operations specific to a CPU class - */ -typedef struct TcgCpuOperations { - /** - * @initialize: Initalize TCG state - * - * Called when the first CPU is realized. - */ - void (*initialize)(void); - /** - * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock - * - * This is called when we abandon execution of a TB before starting it, - * and must set all parts of the CPU state which the previous TB in the - * chain may not have updated. - * By default, when this is NULL, a call is made to @set_pc(tb->pc). - * - * If more state needs to be restored, the target must implement a - * function to restore all the state, and register it here. - */ - void (*synchronize_from_tb)(CPUState *cpu, - const struct TranslationBlock *tb); - /** @cpu_exec_enter: Callback for cpu_exec preparation */ - void (*cpu_exec_enter)(CPUState *cpu); - /** @cpu_exec_exit: Callback for cpu_exec cleanup */ - void (*cpu_exec_exit)(CPUState *cpu); - /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ - bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); - /** @do_interrupt: Callback for interrupt handling. */ - void (*do_interrupt)(CPUState *cpu); - /** - * @tlb_fill: Handle a softmmu tlb miss or user-only address fault - * - * For system mode, if the access is valid, call tlb_set_page - * and return true; if the access is invalid, and probe is - * true, return false; otherwise raise an exception and do - * not return. For user-only mode, always raise an exception - * and do not return. - */ - bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); - /** @debug_excp_handler: Callback for handling debug exceptions */ - void (*debug_excp_handler)(CPUState *cpu); - - /** - * @do_transaction_failed: Callback for handling failed memory transac= tions - * (ie bus faults or external aborts; not MMU faults) - */ - void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr ad= dr, - unsigned size, MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t retaddr); - /** - * @do_unaligned_access: Callback for unaligned access handling - */ - void (*do_unaligned_access)(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); - /** - * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by A= RM - */ - vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); - - /** - * @debug_check_watchpoint: return true if the architectural - * watchpoint whose address has matched should really fire, used by ARM - */ - bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); - -} TcgCpuOperations; +/* see tcg-cpu-ops.h */ +struct TCGCPUOps; =20 /** * CPUClass: @@ -258,7 +188,8 @@ struct CPUClass { int gdb_num_core_regs; bool gdb_stop_before_watchpoint; =20 - TcgCpuOperations tcg_ops; + /* when TCG is not available, this pointer is NULL */ + struct TCGCPUOps *tcg_ops; }; =20 /* @@ -889,32 +820,6 @@ CPUState *cpu_by_arch_id(int64_t id); =20 void cpu_interrupt(CPUState *cpu, int mask); =20 -static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - cc->tcg_ops.do_unaligned_access(cpu, addr, access_type, mmu_idx, retad= dr); -} - -static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, - uintptr_t retaddr) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - if (!cpu->ignore_memory_transaction_failures && - cc->tcg_ops.do_transaction_failed) { - cc->tcg_ops.do_transaction_failed(cpu, physaddr, addr, size, - access_type, mmu_idx, attrs, - response, retaddr); - } -} - /** * cpu_set_pc: * @cpu: The CPU to set the program counter for. diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h new file mode 100644 index 0000000000..ccc97d1894 --- /dev/null +++ b/include/hw/core/tcg-cpu-ops.h @@ -0,0 +1,97 @@ +/* + * TCG CPU-specific operations + * + * Copyright 2021 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef TCG_CPU_OPS_H +#define TCG_CPU_OPS_H + +#include "hw/core/cpu.h" + +struct TCGCPUOps { + /** + * @initialize: Initalize TCG state + * + * Called when the first CPU is realized. + */ + void (*initialize)(void); + /** + * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock + * + * This is called when we abandon execution of a TB before starting it, + * and must set all parts of the CPU state which the previous TB in the + * chain may not have updated. + * By default, when this is NULL, a call is made to @set_pc(tb->pc). + * + * If more state needs to be restored, the target must implement a + * function to restore all the state, and register it here. + */ + void (*synchronize_from_tb)(CPUState *cpu, + const struct TranslationBlock *tb); + /** @cpu_exec_enter: Callback for cpu_exec preparation */ + void (*cpu_exec_enter)(CPUState *cpu); + /** @cpu_exec_exit: Callback for cpu_exec cleanup */ + void (*cpu_exec_exit)(CPUState *cpu); + /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ + bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** + * @do_interrupt: Callback for interrupt handling. + * + * note that this is in general SOFTMMU only, but it actually isn't + * because of an x86 hack (accel/tcg/cpu-exec.c), so we cannot put it + * in the SOFTMMU section in general. + */ + void (*do_interrupt)(CPUState *cpu); + /** + * @tlb_fill: Handle a softmmu tlb miss or user-only address fault + * + * For system mode, if the access is valid, call tlb_set_page + * and return true; if the access is invalid, and probe is + * true, return false; otherwise raise an exception and do + * not return. For user-only mode, always raise an exception + * and do not return. + */ + bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + /** @debug_excp_handler: Callback for handling debug exceptions */ + void (*debug_excp_handler)(CPUState *cpu); + +#ifdef NEED_CPU_H +#ifdef CONFIG_SOFTMMU + /** + * @do_transaction_failed: Callback for handling failed memory transac= tions + * (ie bus faults or external aborts; not MMU faults) + */ + void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr ad= dr, + unsigned size, MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr); + /** + * @do_unaligned_access: Callback for unaligned access handling + */ + void (*do_unaligned_access)(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); + + /** + * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by A= RM + */ + vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); + + /** + * @debug_check_watchpoint: return true if the architectural + * watchpoint whose address has matched should really fire, used by ARM + */ + bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); + +#endif /* CONFIG_SOFTMMU */ +#endif /* NEED_CPU_H */ + +}; + +#endif /* TCG_CPU_OPS_H */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 853fa88fd6..448982dd2f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -171,6 +171,12 @@ static inline int r14_bank_number(int mode) void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); =20 +#ifdef CONFIG_TCG +void arm_cpu_synchronize_from_tb(CPUState *cs, + const struct TranslationBlock *tb); +#endif /* CONFIG_TCG */ + + enum arm_fprounding { FPROUNDING_TIEEVEN, FPROUNDING_POSINF, diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 633ee3ef9e..d9ef69121c 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -21,6 +21,7 @@ #include "qemu-common.h" #include "qemu/qemu-print.h" #include "cpu.h" +#include "hw/core/tcg-cpu-ops.h" #include "trace.h" #include "disas/disas.h" #include "exec/exec-all.h" @@ -213,8 +214,8 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *= tb_exit) TARGET_FMT_lx "] %s\n", last_tb->tc.ptr, last_tb->pc, lookup_symbol(last_tb->pc)); - if (cc->tcg_ops.synchronize_from_tb) { - cc->tcg_ops.synchronize_from_tb(cpu, last_tb); + if (cc->tcg_ops->synchronize_from_tb) { + cc->tcg_ops->synchronize_from_tb(cpu, last_tb); } else { assert(cc->set_pc); cc->set_pc(cpu, last_tb->pc); @@ -262,8 +263,8 @@ static void cpu_exec_enter(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->tcg_ops.cpu_exec_enter) { - cc->tcg_ops.cpu_exec_enter(cpu); + if (cc->tcg_ops->cpu_exec_enter) { + cc->tcg_ops->cpu_exec_enter(cpu); } } =20 @@ -271,8 +272,8 @@ static void cpu_exec_exit(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->tcg_ops.cpu_exec_exit) { - cc->tcg_ops.cpu_exec_exit(cpu); + if (cc->tcg_ops->cpu_exec_exit) { + cc->tcg_ops->cpu_exec_exit(cpu); } } =20 @@ -512,8 +513,8 @@ static inline void cpu_handle_debug_exception(CPUState = *cpu) } } =20 - if (cc->tcg_ops.debug_excp_handler) { - cc->tcg_ops.debug_excp_handler(cpu); + if (cc->tcg_ops->debug_excp_handler) { + cc->tcg_ops->debug_excp_handler(cpu); } } =20 @@ -547,7 +548,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) loop */ #if defined(TARGET_I386) CPUClass *cc =3D CPU_GET_CLASS(cpu); - cc->tcg_ops.do_interrupt(cpu); + cc->tcg_ops->do_interrupt(cpu); #endif *ret =3D cpu->exception_index; cpu->exception_index =3D -1; @@ -556,7 +557,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) if (replay_exception()) { CPUClass *cc =3D CPU_GET_CLASS(cpu); qemu_mutex_lock_iothread(); - cc->tcg_ops.do_interrupt(cpu); + cc->tcg_ops->do_interrupt(cpu); qemu_mutex_unlock_iothread(); cpu->exception_index =3D -1; =20 @@ -655,8 +656,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, True when it is, and we should restart on a new TB, and via longjmp via cpu_loop_exit. */ else { - if (cc->tcg_ops.cpu_exec_interrupt && - cc->tcg_ops.cpu_exec_interrupt(cpu, interrupt_request)) { + if (cc->tcg_ops->cpu_exec_interrupt && + cc->tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { if (need_replay_interrupt(interrupt_request)) { replay_interrupt(); } @@ -834,7 +835,7 @@ void tcg_exec_realizefn(CPUState *cpu, Error **errp) CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 if (!tcg_target_initialized) { - cc->tcg_ops.initialize(); + cc->tcg_ops->initialize(); tcg_target_initialized =3D true; } tlb_init(cpu); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b7717803b8..8a7b779270 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "cpu.h" +#include "hw/core/tcg-cpu-ops.h" #include "exec/exec-all.h" #include "exec/memory.h" #include "exec/address-spaces.h" @@ -1305,11 +1306,37 @@ static void tlb_fill(CPUState *cpu, target_ulong ad= dr, int size, * This is not a probe, so only valid return is success; failure * should result in exception + longjmp to the cpu loop. */ - ok =3D cc->tcg_ops.tlb_fill(cpu, addr, size, - access_type, mmu_idx, false, retaddr); + ok =3D cc->tcg_ops->tlb_fill(cpu, addr, size, + access_type, mmu_idx, false, retaddr); assert(ok); } =20 +static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, mmu_idx, reta= ddr); +} + +static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, + uintptr_t retaddr) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (!cpu->ignore_memory_transaction_failures && + cc->tcg_ops->do_transaction_failed) { + cc->tcg_ops->do_transaction_failed(cpu, physaddr, addr, size, + access_type, mmu_idx, attrs, + response, retaddr); + } +} + static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, target_ulong addr, uintptr_t retaddr, MMUAccessType access_type, MemOp op) @@ -1577,8 +1604,8 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, CPUState *cs =3D env_cpu(env); CPUClass *cc =3D CPU_GET_CLASS(cs); =20 - if (!cc->tcg_ops.tlb_fill(cs, addr, fault_size, access_type, - mmu_idx, nonfault, retaddr)) { + if (!cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_type, + mmu_idx, nonfault, retaddr)) { /* Non-faulting page table read failed. */ *phost =3D NULL; return TLB_INVALID_MASK; diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 9e6e188d19..0b6f56ca40 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" +#include "hw/core/tcg-cpu-ops.h" #include "disas/disas.h" #include "exec/exec-all.h" #include "tcg/tcg.h" @@ -187,8 +188,8 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, clear_helper_retaddr(); =20 cc =3D CPU_GET_CLASS(cpu); - cc->tcg_ops.tlb_fill(cpu, address, 0, access_type, - MMU_USER_IDX, false, pc); + cc->tcg_ops->tlb_fill(cpu, address, 0, access_type, + MMU_USER_IDX, false, pc); g_assert_not_reached(); } =20 @@ -218,8 +219,8 @@ static int probe_access_internal(CPUArchState *env, tar= get_ulong addr, } else { CPUState *cpu =3D env_cpu(env); CPUClass *cc =3D CPU_GET_CLASS(cpu); - cc->tcg_ops.tlb_fill(cpu, addr, fault_size, access_type, - MMU_USER_IDX, false, ra); + cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_type, + MMU_USER_IDX, false, ra); g_assert_not_reached(); } } diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index 46c71a0ac8..83c8086062 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -53,6 +53,9 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/help_option.h" +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" +#endif /* CONFIG_TCG */ =20 enum jazz_model_e { JAZZ_MAGNUM, @@ -209,8 +212,8 @@ static void mips_jazz_init(MachineState *machine, */ cc =3D CPU_GET_CLASS(cpu); #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) - real_do_transaction_failed =3D cc->tcg_ops.do_transaction_failed; - cc->tcg_ops.do_transaction_failed =3D mips_jazz_do_transaction_failed; + real_do_transaction_failed =3D cc->tcg_ops->do_transaction_failed; + cc->tcg_ops->do_transaction_failed =3D mips_jazz_do_transaction_failed; #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ =20 /* allocate RAM */ diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 9e64cf7adf..243c3097d3 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -24,6 +24,11 @@ #include "qemu/cutils.h" #include "qemu/cacheflush.h" #include "cpu.h" + +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" +#endif /* CONFIG_TCG */ + #include "exec/exec-all.h" #include "exec/target_page.h" #include "hw/qdev-core.h" @@ -894,9 +899,9 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, va= ddr len, return; } =20 - if (cc->tcg_ops.adjust_watchpoint_address) { + if (cc->tcg_ops->adjust_watchpoint_address) { /* this is currently used only by ARM BE32 */ - addr =3D cc->tcg_ops.adjust_watchpoint_address(cpu, addr, len); + addr =3D cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len); } QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if (watchpoint_address_matches(wp, addr, len) @@ -917,8 +922,8 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, va= ddr len, wp->hitaddr =3D MAX(addr, wp->vaddr); wp->hitattrs =3D attrs; if (!cpu->watchpoint_hit) { - if (wp->flags & BP_CPU && cc->tcg_ops.debug_check_watchpoi= nt && - !cc->tcg_ops.debug_check_watchpoint(cpu, wp)) { + if (wp->flags & BP_CPU && cc->tcg_ops->debug_check_watchpo= int && + !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) { wp->flags &=3D ~BP_WATCHPOINT_HIT; continue; } diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 0710298e5a..27192b62e2 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -206,6 +206,20 @@ static void alpha_cpu_initfn(Object *obj) #endif } =20 +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps alpha_tcg_ops =3D { + .initialize =3D alpha_translate_init, + .cpu_exec_interrupt =3D alpha_cpu_exec_interrupt, + .tlb_fill =3D alpha_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D alpha_cpu_do_interrupt, + .do_transaction_failed =3D alpha_cpu_do_transaction_failed, + .do_unaligned_access =3D alpha_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + static void alpha_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -217,22 +231,17 @@ static void alpha_cpu_class_init(ObjectClass *oc, voi= d *data) =20 cc->class_by_name =3D alpha_cpu_class_by_name; cc->has_work =3D alpha_cpu_has_work; - cc->tcg_ops.do_interrupt =3D alpha_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt =3D alpha_cpu_exec_interrupt; cc->dump_state =3D alpha_cpu_dump_state; cc->set_pc =3D alpha_cpu_set_pc; cc->gdb_read_register =3D alpha_cpu_gdb_read_register; cc->gdb_write_register =3D alpha_cpu_gdb_write_register; - cc->tcg_ops.tlb_fill =3D alpha_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->tcg_ops.do_transaction_failed =3D alpha_cpu_do_transaction_failed; - cc->tcg_ops.do_unaligned_access =3D alpha_cpu_do_unaligned_access; cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_alpha_cpu; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; - cc->tcg_ops.initialize =3D alpha_translate_init; =20 + cc->tcg_ops =3D &alpha_tcg_ops; cc->gdb_num_core_regs =3D 67; } =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c9a66d3103..8ddb2556f8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -26,6 +26,9 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include "cpu.h" +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" +#endif /* CONFIG_TCG */ #include "internals.h" #include "exec/exec-all.h" #include "hw/qdev-properties.h" @@ -55,8 +58,8 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) } =20 #ifdef CONFIG_TCG -static void arm_cpu_synchronize_from_tb(CPUState *cs, - const TranslationBlock *tb) +void arm_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -590,7 +593,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) found: cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; - cc->tcg_ops.do_interrupt(cs); + cc->tcg_ops->do_interrupt(cs); return true; } =20 @@ -2242,6 +2245,24 @@ static gchar *arm_gdb_arch_name(CPUState *cs) return g_strdup("arm"); } =20 +#ifdef CONFIG_TCG +static struct TCGCPUOps arm_tcg_ops =3D { + .initialize =3D arm_translate_init, + .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, + .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, + .tlb_fill =3D arm_cpu_tlb_fill, + .debug_excp_handler =3D arm_debug_excp_handler, + +#if !defined(CONFIG_USER_ONLY) + .do_interrupt =3D arm_cpu_do_interrupt, + .do_transaction_failed =3D arm_cpu_do_transaction_failed, + .do_unaligned_access =3D arm_cpu_do_unaligned_access, + .adjust_watchpoint_address =3D arm_adjust_watchpoint_address, + .debug_check_watchpoint =3D arm_debug_check_watchpoint, +#endif /* !CONFIG_USER_ONLY */ +}; +#endif /* CONFIG_TCG */ + static void arm_cpu_class_init(ObjectClass *oc, void *data) { ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); @@ -2274,19 +2295,9 @@ static void arm_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_get_dynamic_xml =3D arm_gdb_get_dynamic_xml; cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D arm_disas_set_info; + #ifdef CONFIG_TCG - cc->tcg_ops.initialize =3D arm_translate_init; - cc->tcg_ops.cpu_exec_interrupt =3D arm_cpu_exec_interrupt; - cc->tcg_ops.synchronize_from_tb =3D arm_cpu_synchronize_from_tb; - cc->tcg_ops.tlb_fill =3D arm_cpu_tlb_fill; - cc->tcg_ops.debug_excp_handler =3D arm_debug_excp_handler; -#if !defined(CONFIG_USER_ONLY) - cc->tcg_ops.do_interrupt =3D arm_cpu_do_interrupt; - cc->tcg_ops.do_transaction_failed =3D arm_cpu_do_transaction_failed; - cc->tcg_ops.do_unaligned_access =3D arm_cpu_do_unaligned_access; - cc->tcg_ops.adjust_watchpoint_address =3D arm_adjust_watchpoint_addres= s; - cc->tcg_ops.debug_check_watchpoint =3D arm_debug_check_watchpoint; -#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ + cc->tcg_ops =3D &arm_tcg_ops; #endif /* CONFIG_TCG */ } =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a9a1cdb871..10c5118176 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -21,6 +21,9 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "cpu.h" +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" +#endif /* CONFIG_TCG */ #include "qemu/module.h" #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" @@ -805,10 +808,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, vo= id *data) { CPUClass *cc =3D CPU_CLASS(oc); =20 -#ifdef CONFIG_TCG - cc->tcg_ops.cpu_exec_interrupt =3D arm_cpu_exec_interrupt; -#endif /* CONFIG_TCG */ - cc->gdb_read_register =3D aarch64_cpu_gdb_read_register; cc->gdb_write_register =3D aarch64_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 34; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index d9c160f1ac..c29b434c60 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -10,6 +10,9 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" +#endif /* CONFIG_TCG */ #include "internals.h" =20 /* CPU models. These are not needed for the AArch64 linux-user build. */ @@ -34,7 +37,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) if (interrupt_request & CPU_INTERRUPT_HARD && (armv7m_nvic_can_take_pending_exception(env->nvic))) { cs->exception_index =3D EXCP_IRQ; - cc->tcg_ops.do_interrupt(cs); + cc->tcg_ops->do_interrupt(cs); ret =3D true; } return ret; @@ -660,6 +663,24 @@ static void pxa270c5_initfn(Object *obj) cpu->reset_sctlr =3D 0x00000078; } =20 +#ifdef CONFIG_TCG +static struct TCGCPUOps arm_v7m_tcg_ops =3D { + .initialize =3D arm_translate_init, + .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, + .cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt, + .tlb_fill =3D arm_cpu_tlb_fill, + .debug_excp_handler =3D arm_debug_excp_handler, + +#if !defined(CONFIG_USER_ONLY) + .do_interrupt =3D arm_v7m_cpu_do_interrupt, + .do_transaction_failed =3D arm_cpu_do_transaction_failed, + .do_unaligned_access =3D arm_cpu_do_unaligned_access, + .adjust_watchpoint_address =3D arm_adjust_watchpoint_address, + .debug_check_watchpoint =3D arm_debug_check_watchpoint, +#endif /* !CONFIG_USER_ONLY */ +}; +#endif /* CONFIG_TCG */ + static void arm_v7m_class_init(ObjectClass *oc, void *data) { ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); @@ -667,10 +688,7 @@ static void arm_v7m_class_init(ObjectClass *oc, void *= data) =20 acc->info =3D data; #ifdef CONFIG_TCG - cc->tcg_ops.cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; -#ifndef CONFIG_USER_ONLY - cc->tcg_ops.do_interrupt =3D arm_v7m_cpu_do_interrupt; -#endif + cc->tcg_ops =3D &arm_v7m_tcg_ops; #endif /* CONFIG_TCG */ =20 cc->gdb_core_xml_file =3D "arm-m-profile.xml"; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 476e645b37..fa0f8e0e80 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -184,6 +184,19 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, = int flags) qemu_fprintf(f, "\n"); } =20 +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps avr_tcg_ops =3D { + .initialize =3D avr_cpu_tcg_init, + .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, + .cpu_exec_interrupt =3D avr_cpu_exec_interrupt, + .tlb_fill =3D avr_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D avr_cpu_do_interrupt, +#endif /* !CONFIG_USER_ONLY */ +}; + static void avr_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -198,21 +211,17 @@ static void avr_cpu_class_init(ObjectClass *oc, void = *data) cc->class_by_name =3D avr_cpu_class_by_name; =20 cc->has_work =3D avr_cpu_has_work; - cc->tcg_ops.do_interrupt =3D avr_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt =3D avr_cpu_exec_interrupt; cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; - cc->tcg_ops.tlb_fill =3D avr_cpu_tlb_fill; cc->vmsd =3D &vms_avr_cpu; cc->disas_set_info =3D avr_cpu_disas_set_info; - cc->tcg_ops.initialize =3D avr_cpu_tcg_init; - cc->tcg_ops.synchronize_from_tb =3D avr_cpu_synchronize_from_tb; cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 35; cc->gdb_core_xml_file =3D "avr-cpu.xml"; + cc->tcg_ops =3D &avr_tcg_ops; } =20 /* diff --git a/target/avr/helper.c b/target/avr/helper.c index 69d3b6181f..65880b9928 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -20,6 +20,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "hw/core/tcg-cpu-ops.h" #include "exec/exec-all.h" #include "exec/address-spaces.h" #include "exec/helper-proto.h" @@ -34,7 +35,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_r= equest) if (interrupt_request & CPU_INTERRUPT_RESET) { if (cpu_interrupts_enabled(env)) { cs->exception_index =3D EXCP_RESET; - cc->tcg_ops.do_interrupt(cs); + cc->tcg_ops->do_interrupt(cs); =20 cs->interrupt_request &=3D ~CPU_INTERRUPT_RESET; =20 @@ -45,7 +46,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_r= equest) if (cpu_interrupts_enabled(env) && env->intsrc !=3D 0) { int index =3D ctz32(env->intsrc); cs->exception_index =3D EXCP_INT(index); - cc->tcg_ops.do_interrupt(cs); + cc->tcg_ops->do_interrupt(cs); =20 env->intsrc &=3D env->intsrc - 1; /* clear the interrupt */ cs->interrupt_request &=3D ~CPU_INTERRUPT_HARD; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index b65743e8ca..ed983380fc 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -193,15 +193,36 @@ static void cris_cpu_initfn(Object *obj) #endif } =20 +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps crisv10_tcg_ops =3D { + .initialize =3D cris_initialize_crisv10_tcg, + .cpu_exec_interrupt =3D cris_cpu_exec_interrupt, + .tlb_fill =3D cris_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D crisv10_cpu_do_interrupt, +#endif /* !CONFIG_USER_ONLY */ +}; + +static struct TCGCPUOps crisv32_tcg_ops =3D { + .initialize =3D cris_initialize_tcg, + .cpu_exec_interrupt =3D cris_cpu_exec_interrupt, + .tlb_fill =3D cris_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D cris_cpu_do_interrupt, +#endif /* !CONFIG_USER_ONLY */ +}; + static void crisv8_cpu_class_init(ObjectClass *oc, void *data) { CPUClass *cc =3D CPU_CLASS(oc); CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 8; - cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; - cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; + cc->tcg_ops =3D &crisv10_tcg_ops; } =20 static void crisv9_cpu_class_init(ObjectClass *oc, void *data) @@ -210,9 +231,8 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void= *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 9; - cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; - cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; + cc->tcg_ops =3D &crisv10_tcg_ops; } =20 static void crisv10_cpu_class_init(ObjectClass *oc, void *data) @@ -221,9 +241,8 @@ static void crisv10_cpu_class_init(ObjectClass *oc, voi= d *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 10; - cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; - cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; + cc->tcg_ops =3D &crisv10_tcg_ops; } =20 static void crisv11_cpu_class_init(ObjectClass *oc, void *data) @@ -232,9 +251,8 @@ static void crisv11_cpu_class_init(ObjectClass *oc, voi= d *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 11; - cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; - cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; + cc->tcg_ops =3D &crisv10_tcg_ops; } =20 static void crisv17_cpu_class_init(ObjectClass *oc, void *data) @@ -243,16 +261,17 @@ static void crisv17_cpu_class_init(ObjectClass *oc, v= oid *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 17; - cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; - cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; + cc->tcg_ops =3D &crisv10_tcg_ops; } =20 static void crisv32_cpu_class_init(ObjectClass *oc, void *data) { + CPUClass *cc =3D CPU_CLASS(oc); CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 32; + cc->tcg_ops =3D &crisv32_tcg_ops; } =20 static void cris_cpu_class_init(ObjectClass *oc, void *data) @@ -268,13 +287,10 @@ static void cris_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D cris_cpu_class_by_name; cc->has_work =3D cris_cpu_has_work; - cc->tcg_ops.do_interrupt =3D cris_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt =3D cris_cpu_exec_interrupt; cc->dump_state =3D cris_cpu_dump_state; cc->set_pc =3D cris_cpu_set_pc; cc->gdb_read_register =3D cris_cpu_gdb_read_register; cc->gdb_write_register =3D cris_cpu_gdb_write_register; - cc->tcg_ops.tlb_fill =3D cris_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_cris_cpu; @@ -284,7 +300,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_stop_before_watchpoint =3D true; =20 cc->disas_set_info =3D cris_disas_set_info; - cc->tcg_ops.initialize =3D cris_initialize_tcg; } =20 #define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/cris/helper.c b/target/cris/helper.c index 1f4d6f7d45..7e3bb58fe1 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -20,6 +20,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "hw/core/tcg-cpu-ops.h" #include "mmu.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" @@ -299,7 +300,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) && (env->pregs[PR_CCS] & I_FLAG) && !env->locked_irq) { cs->exception_index =3D EXCP_IRQ; - cc->tcg_ops.do_interrupt(cs); + cc->tcg_ops->do_interrupt(cs); ret =3D true; } if (interrupt_request & CPU_INTERRUPT_NMI) { @@ -311,7 +312,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) } if ((env->pregs[PR_CCS] & m_flag_archval)) { cs->exception_index =3D EXCP_NMI; - cc->tcg_ops.do_interrupt(cs); + cc->tcg_ops->do_interrupt(cs); ret =3D true; } } diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index fd7f849a1c..d8fad52d1f 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -131,6 +131,20 @@ static ObjectClass *hppa_cpu_class_by_name(const char = *cpu_model) return object_class_by_name(TYPE_HPPA_CPU); } =20 +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps hppa_tcg_ops =3D { + .initialize =3D hppa_translate_init, + .synchronize_from_tb =3D hppa_cpu_synchronize_from_tb, + .cpu_exec_interrupt =3D hppa_cpu_exec_interrupt, + .tlb_fill =3D hppa_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D hppa_cpu_do_interrupt, + .do_unaligned_access =3D hppa_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + static void hppa_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -142,23 +156,17 @@ static void hppa_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D hppa_cpu_class_by_name; cc->has_work =3D hppa_cpu_has_work; - cc->tcg_ops.do_interrupt =3D hppa_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt =3D hppa_cpu_exec_interrupt; cc->dump_state =3D hppa_cpu_dump_state; cc->set_pc =3D hppa_cpu_set_pc; - cc->tcg_ops.synchronize_from_tb =3D hppa_cpu_synchronize_from_tb; cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; - cc->tcg_ops.tlb_fill =3D hppa_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; - cc->tcg_ops.do_unaligned_access =3D hppa_cpu_do_unaligned_access; dc->vmsd =3D &vmstate_hppa_cpu; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; - cc->tcg_ops.initialize =3D hppa_translate_init; - cc->gdb_num_core_regs =3D 128; + cc->tcg_ops =3D &hppa_tcg_ops; } =20 static const TypeInfo hppa_cpu_type_info =3D { diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 4a53cd89e2..1e125d2175 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -57,16 +57,22 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, cpu->env.eip =3D tb->pc - tb->cs_base; } =20 +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps x86_tcg_ops =3D { + .initialize =3D tcg_x86_init, + .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, + .cpu_exec_enter =3D x86_cpu_exec_enter, + .cpu_exec_exit =3D x86_cpu_exec_exit, + .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, + .do_interrupt =3D x86_cpu_do_interrupt, + .tlb_fill =3D x86_cpu_tlb_fill, +#ifndef CONFIG_USER_ONLY + .debug_excp_handler =3D breakpoint_handler, +#endif /* !CONFIG_USER_ONLY */ +}; + void tcg_cpu_common_class_init(CPUClass *cc) { - cc->tcg_ops.do_interrupt =3D x86_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt =3D x86_cpu_exec_interrupt; - cc->tcg_ops.synchronize_from_tb =3D x86_cpu_synchronize_from_tb; - cc->tcg_ops.cpu_exec_enter =3D x86_cpu_exec_enter; - cc->tcg_ops.cpu_exec_exit =3D x86_cpu_exec_exit; - cc->tcg_ops.initialize =3D tcg_x86_init; - cc->tcg_ops.tlb_fill =3D x86_cpu_tlb_fill; -#ifndef CONFIG_USER_ONLY - cc->tcg_ops.debug_excp_handler =3D breakpoint_handler; -#endif + cc->tcg_ops =3D &x86_tcg_ops; } diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index fb3761b749..c23d72874c 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -210,6 +210,19 @@ static ObjectClass *lm32_cpu_class_by_name(const char = *cpu_model) return oc; } =20 +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps lm32_tcg_ops =3D { + .initialize =3D lm32_translate_init, + .cpu_exec_interrupt =3D lm32_cpu_exec_interrupt, + .tlb_fill =3D lm32_cpu_tlb_fill, + .debug_excp_handler =3D lm32_debug_excp_handler, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D lm32_cpu_do_interrupt, +#endif /* !CONFIG_USER_ONLY */ +}; + static void lm32_cpu_class_init(ObjectClass *oc, void *data) { LM32CPUClass *lcc =3D LM32_CPU_CLASS(oc); @@ -222,22 +235,18 @@ static void lm32_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D lm32_cpu_class_by_name; cc->has_work =3D lm32_cpu_has_work; - cc->tcg_ops.do_interrupt =3D lm32_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt =3D lm32_cpu_exec_interrupt; cc->dump_state =3D lm32_cpu_dump_state; cc->set_pc =3D lm32_cpu_set_pc; cc->gdb_read_register =3D lm32_cpu_gdb_read_register; cc->gdb_write_register =3D lm32_cpu_gdb_write_register; - cc->tcg_ops.tlb_fill =3D lm32_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_lm32_cpu; #endif cc->gdb_num_core_regs =3D 32 + 7; cc->gdb_stop_before_watchpoint =3D true; - cc->tcg_ops.debug_excp_handler =3D lm32_debug_excp_handler; cc->disas_set_info =3D lm32_cpu_disas_set_info; - cc->tcg_ops.initialize =3D lm32_translate_init; + cc->tcg_ops =3D &lm32_tcg_ops; } =20 #define DEFINE_LM32_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index e68b933c84..c6fde8132b 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -453,6 +453,19 @@ static const VMStateDescription vmstate_m68k_cpu =3D { }; #endif =20 +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps m68k_tcg_ops =3D { + .initialize =3D m68k_tcg_init, + .cpu_exec_interrupt =3D m68k_cpu_exec_interrupt, + .tlb_fill =3D m68k_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D m68k_cpu_do_interrupt, + .do_transaction_failed =3D m68k_cpu_transaction_failed, +#endif /* !CONFIG_USER_ONLY */ +}; + static void m68k_cpu_class_init(ObjectClass *c, void *data) { M68kCPUClass *mcc =3D M68K_CPU_CLASS(c); @@ -465,22 +478,18 @@ static void m68k_cpu_class_init(ObjectClass *c, void = *data) =20 cc->class_by_name =3D m68k_cpu_class_by_name; cc->has_work =3D m68k_cpu_has_work; - cc->tcg_ops.do_interrupt =3D m68k_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt =3D m68k_cpu_exec_interrupt; cc->dump_state =3D m68k_cpu_dump_state; cc->set_pc =3D m68k_cpu_set_pc; cc->gdb_read_register =3D m68k_cpu_gdb_read_register; cc->gdb_write_register =3D m68k_cpu_gdb_write_register; - cc->tcg_ops.tlb_fill =3D m68k_cpu_tlb_fill; #if defined(CONFIG_SOFTMMU) - cc->tcg_ops.do_transaction_failed =3D m68k_cpu_transaction_failed; cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_m68k_cpu; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; - cc->tcg_ops.initialize =3D m68k_tcg_init; =20 cc->gdb_num_core_regs =3D 18; + cc->tcg_ops =3D &m68k_tcg_ops; } =20 static void m68k_cpu_class_init_cf_core(ObjectClass *c, void *data) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6678310f51..433ba20203 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -352,6 +352,21 @@ static ObjectClass *mb_cpu_class_by_name(const char *c= pu_model) return object_class_by_name(TYPE_MICROBLAZE_CPU); } =20 +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps mb_tcg_ops =3D { + .initialize =3D mb_tcg_init, + .synchronize_from_tb =3D mb_cpu_synchronize_from_tb, + .cpu_exec_interrupt =3D mb_cpu_exec_interrupt, + .tlb_fill =3D mb_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D mb_cpu_do_interrupt, + .do_transaction_failed =3D mb_cpu_transaction_failed, + .do_unaligned_access =3D mb_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + static void mb_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -364,17 +379,13 @@ static void mb_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->class_by_name =3D mb_cpu_class_by_name; cc->has_work =3D mb_cpu_has_work; - cc->tcg_ops.do_interrupt =3D mb_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt =3D mb_cpu_exec_interrupt; + cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; - cc->tcg_ops.synchronize_from_tb =3D mb_cpu_synchronize_from_tb; cc->gdb_read_register =3D mb_cpu_gdb_read_register; cc->gdb_write_register =3D mb_cpu_gdb_write_register; - cc->tcg_ops.tlb_fill =3D mb_cpu_tlb_fill; + #ifndef CONFIG_USER_ONLY - cc->tcg_ops.do_transaction_failed =3D mb_cpu_transaction_failed; - cc->tcg_ops.do_unaligned_access =3D mb_cpu_do_unaligned_access; cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; dc->vmsd =3D &vmstate_mb_cpu; #endif @@ -382,7 +393,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->gdb_num_core_regs =3D 32 + 27; =20 cc->disas_set_info =3D mb_disas_set_info; - cc->tcg_ops.initialize =3D mb_tcg_init; + cc->tcg_ops =3D &mb_tcg_ops; } =20 static const TypeInfo mb_cpu_type_info =3D { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 1e93e295cc..ad163ead62 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -663,6 +663,26 @@ static Property mips_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" +/* + * NB: cannot be const, as some elements are changed for specific + * mips hardware (see hw/mips/jazz.c). + */ +static struct TCGCPUOps mips_tcg_ops =3D { + .initialize =3D mips_tcg_init, + .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, + .cpu_exec_interrupt =3D mips_cpu_exec_interrupt, + .tlb_fill =3D mips_cpu_tlb_fill, + +#if !defined(CONFIG_USER_ONLY) + .do_interrupt =3D mips_cpu_do_interrupt, + .do_transaction_failed =3D mips_cpu_do_transaction_failed, + .do_unaligned_access =3D mips_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; +#endif /* CONFIG_TCG */ + static void mips_cpu_class_init(ObjectClass *c, void *data) { MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(c); @@ -685,21 +705,11 @@ static void mips_cpu_class_init(ObjectClass *c, void = *data) cc->vmsd =3D &vmstate_mips_cpu; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; -#ifdef CONFIG_TCG - cc->tcg_ops.initialize =3D mips_tcg_init; - cc->tcg_ops.do_interrupt =3D mips_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt =3D mips_cpu_exec_interrupt; - cc->tcg_ops.synchronize_from_tb =3D mips_cpu_synchronize_from_tb; - cc->tcg_ops.tlb_fill =3D mips_cpu_tlb_fill; -#ifndef CONFIG_USER_ONLY - cc->tcg_ops.do_transaction_failed =3D mips_cpu_do_transaction_failed; - cc->tcg_ops.do_unaligned_access =3D mips_cpu_do_unaligned_access; - -#endif /* CONFIG_USER_ONLY */ -#endif /* CONFIG_TCG */ - cc->gdb_num_core_regs =3D 73; cc->gdb_stop_before_watchpoint =3D true; +#ifdef CONFIG_TCG + cc->tcg_ops =3D &mips_tcg_ops; +#endif /* CONFIG_TCG */ } =20 static const TypeInfo mips_cpu_type_info =3D { diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 36bef4d357..83bec34d36 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -94,6 +94,17 @@ static ObjectClass *moxie_cpu_class_by_name(const char *= cpu_model) return oc; } =20 +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps moxie_tcg_ops =3D { + .initialize =3D moxie_translate_init, + .tlb_fill =3D moxie_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D moxie_cpu_do_interrupt, +#endif /* !CONFIG_USER_ONLY */ +}; + static void moxie_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -107,16 +118,14 @@ static void moxie_cpu_class_init(ObjectClass *oc, voi= d *data) cc->class_by_name =3D moxie_cpu_class_by_name; =20 cc->has_work =3D moxie_cpu_has_work; - cc->tcg_ops.do_interrupt =3D moxie_cpu_do_interrupt; cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; - cc->tcg_ops.tlb_fill =3D moxie_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_moxie_cpu; #endif cc->disas_set_info =3D moxie_cpu_disas_set_info; - cc->tcg_ops.initialize =3D moxie_translate_init; + cc->tcg_ops =3D &moxie_tcg_ops; } =20 static void moxielite_initfn(Object *obj) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index c43aa3d4c4..e9c9fc3a38 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -207,6 +207,18 @@ static Property nios2_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps nios2_tcg_ops =3D { + .initialize =3D nios2_tcg_init, + .cpu_exec_interrupt =3D nios2_cpu_exec_interrupt, + .tlb_fill =3D nios2_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D nios2_cpu_do_interrupt, + .do_unaligned_access =3D nios2_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; =20 static void nios2_cpu_class_init(ObjectClass *oc, void *data) { @@ -221,20 +233,16 @@ static void nios2_cpu_class_init(ObjectClass *oc, voi= d *data) =20 cc->class_by_name =3D nios2_cpu_class_by_name; cc->has_work =3D nios2_cpu_has_work; - cc->tcg_ops.do_interrupt =3D nios2_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt =3D nios2_cpu_exec_interrupt; cc->dump_state =3D nios2_cpu_dump_state; cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; - cc->tcg_ops.tlb_fill =3D nios2_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->tcg_ops.do_unaligned_access =3D nios2_cpu_do_unaligned_access; cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; #endif cc->gdb_read_register =3D nios2_cpu_gdb_read_register; cc->gdb_write_register =3D nios2_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 49; - cc->tcg_ops.initialize =3D nios2_tcg_init; + cc->tcg_ops =3D &nios2_tcg_ops; } =20 static const TypeInfo nios2_cpu_type_info =3D { diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 1a31f7564f..2c64842f46 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -174,6 +174,18 @@ static void openrisc_any_initfn(Object *obj) | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); } =20 +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps openrisc_tcg_ops =3D { + .initialize =3D openrisc_translate_init, + .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, + .tlb_fill =3D openrisc_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D openrisc_cpu_do_interrupt, +#endif /* !CONFIG_USER_ONLY */ +}; + static void openrisc_cpu_class_init(ObjectClass *oc, void *data) { OpenRISCCPUClass *occ =3D OPENRISC_CPU_CLASS(oc); @@ -186,20 +198,17 @@ static void openrisc_cpu_class_init(ObjectClass *oc, = void *data) =20 cc->class_by_name =3D openrisc_cpu_class_by_name; cc->has_work =3D openrisc_cpu_has_work; - cc->tcg_ops.do_interrupt =3D openrisc_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt; cc->dump_state =3D openrisc_cpu_dump_state; cc->set_pc =3D openrisc_cpu_set_pc; cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; - cc->tcg_ops.tlb_fill =3D openrisc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_openrisc_cpu; #endif cc->gdb_num_core_regs =3D 32 + 3; - cc->tcg_ops.initialize =3D openrisc_translate_init; cc->disas_set_info =3D openrisc_disas_set_info; + cc->tcg_ops =3D &openrisc_tcg_ops; } =20 /* Sort alphabetically by type name, except for "any". */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5e85fd58b6..16f1a34238 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -580,6 +580,21 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState = *cs, const char *xmlname) return NULL; } =20 +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps riscv_tcg_ops =3D { + .initialize =3D riscv_translate_init, + .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, + .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, + .tlb_fill =3D riscv_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D riscv_cpu_do_interrupt, + .do_transaction_failed =3D riscv_cpu_do_transaction_failed, + .do_unaligned_access =3D riscv_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); @@ -593,11 +608,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void = *data) =20 cc->class_by_name =3D riscv_cpu_class_by_name; cc->has_work =3D riscv_cpu_has_work; - cc->tcg_ops.do_interrupt =3D riscv_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt =3D riscv_cpu_exec_interrupt; cc->dump_state =3D riscv_cpu_dump_state; cc->set_pc =3D riscv_cpu_set_pc; - cc->tcg_ops.synchronize_from_tb =3D riscv_cpu_synchronize_from_tb; cc->gdb_read_register =3D riscv_cpu_gdb_read_register; cc->gdb_write_register =3D riscv_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 33; @@ -609,16 +621,13 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->tcg_ops.do_transaction_failed =3D riscv_cpu_do_transaction_failed; - cc->tcg_ops.do_unaligned_access =3D riscv_cpu_do_unaligned_access; cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; /* For now, mark unmigratable: */ cc->vmsd =3D &vmstate_riscv_cpu; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; - cc->tcg_ops.initialize =3D riscv_translate_init; - cc->tcg_ops.tlb_fill =3D riscv_cpu_tlb_fill; + cc->tcg_ops =3D &riscv_tcg_ops; =20 device_class_set_props(dc, riscv_cpu_properties); } diff --git a/target/rx/cpu.c b/target/rx/cpu.c index e79f009cbd..7ac6618b26 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -173,6 +173,19 @@ static void rx_cpu_init(Object *obj) qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); } =20 +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps rx_tcg_ops =3D { + .initialize =3D rx_translate_init, + .synchronize_from_tb =3D rx_cpu_synchronize_from_tb, + .cpu_exec_interrupt =3D rx_cpu_exec_interrupt, + .tlb_fill =3D rx_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D rx_cpu_do_interrupt, +#endif /* !CONFIG_USER_ONLY */ +}; + static void rx_cpu_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -186,20 +199,17 @@ static void rx_cpu_class_init(ObjectClass *klass, voi= d *data) =20 cc->class_by_name =3D rx_cpu_class_by_name; cc->has_work =3D rx_cpu_has_work; - cc->tcg_ops.do_interrupt =3D rx_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt =3D rx_cpu_exec_interrupt; cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; - cc->tcg_ops.synchronize_from_tb =3D rx_cpu_synchronize_from_tb; + cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; cc->disas_set_info =3D rx_cpu_disas_set_info; - cc->tcg_ops.initialize =3D rx_translate_init; - cc->tcg_ops.tlb_fill =3D rx_cpu_tlb_fill; =20 cc->gdb_num_core_regs =3D 26; cc->gdb_core_xml_file =3D "rx-core.xml"; + cc->tcg_ops =3D &rx_tcg_ops; } =20 static const TypeInfo rx_cpu_info =3D { diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index a723ede8d1..d35eb39a1b 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -477,6 +477,22 @@ static void s390_cpu_reset_full(DeviceState *dev) return s390_cpu_reset(s, S390_CPU_RESET_CLEAR); } =20 +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps s390_tcg_ops =3D { + .initialize =3D s390x_translate_init, + .tlb_fill =3D s390_cpu_tlb_fill, + +#if !defined(CONFIG_USER_ONLY) + .cpu_exec_interrupt =3D s390_cpu_exec_interrupt, + .do_interrupt =3D s390_cpu_do_interrupt, + .debug_excp_handler =3D s390x_cpu_debug_excp_handler, + .do_unaligned_access =3D s390x_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; +#endif /* CONFIG_TCG */ + static void s390_cpu_class_init(ObjectClass *oc, void *data) { S390CPUClass *scc =3D S390_CPU_CLASS(oc); @@ -495,9 +511,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) scc->reset =3D s390_cpu_reset; cc->class_by_name =3D s390_cpu_class_by_name, cc->has_work =3D s390_cpu_has_work; -#ifdef CONFIG_TCG - cc->tcg_ops.do_interrupt =3D s390_cpu_do_interrupt; -#endif cc->dump_state =3D s390_cpu_dump_state; cc->set_pc =3D s390_cpu_set_pc; cc->gdb_read_register =3D s390_cpu_gdb_read_register; @@ -507,23 +520,17 @@ static void s390_cpu_class_init(ObjectClass *oc, void= *data) cc->vmsd =3D &vmstate_s390_cpu; cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; -#ifdef CONFIG_TCG - cc->tcg_ops.cpu_exec_interrupt =3D s390_cpu_exec_interrupt; - cc->tcg_ops.debug_excp_handler =3D s390x_cpu_debug_excp_handler; - cc->tcg_ops.do_unaligned_access =3D s390x_cpu_do_unaligned_access; -#endif #endif cc->disas_set_info =3D s390_cpu_disas_set_info; -#ifdef CONFIG_TCG - cc->tcg_ops.initialize =3D s390x_translate_init; - cc->tcg_ops.tlb_fill =3D s390_cpu_tlb_fill; -#endif - cc->gdb_num_core_regs =3D S390_NUM_CORE_REGS; cc->gdb_core_xml_file =3D "s390x-core64.xml"; cc->gdb_arch_name =3D s390_gdb_arch_name; =20 s390_cpu_model_class_register_props(oc); + +#ifdef CONFIG_TCG + cc->tcg_ops =3D &s390_tcg_ops; +#endif /* CONFIG_TCG */ } =20 static const TypeInfo s390_cpu_type_info =3D { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 292152b562..a78d283bc8 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -206,6 +206,20 @@ static const VMStateDescription vmstate_sh_cpu =3D { .unmigratable =3D 1, }; =20 +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps superh_tcg_ops =3D { + .initialize =3D sh4_translate_init, + .synchronize_from_tb =3D superh_cpu_synchronize_from_tb, + .cpu_exec_interrupt =3D superh_cpu_exec_interrupt, + .tlb_fill =3D superh_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D superh_cpu_do_interrupt, + .do_unaligned_access =3D superh_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + static void superh_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -219,24 +233,19 @@ static void superh_cpu_class_init(ObjectClass *oc, vo= id *data) =20 cc->class_by_name =3D superh_cpu_class_by_name; cc->has_work =3D superh_cpu_has_work; - cc->tcg_ops.do_interrupt =3D superh_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt =3D superh_cpu_exec_interrupt; cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; - cc->tcg_ops.synchronize_from_tb =3D superh_cpu_synchronize_from_tb; cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; - cc->tcg_ops.tlb_fill =3D superh_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->tcg_ops.do_unaligned_access =3D superh_cpu_do_unaligned_access; cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; - cc->tcg_ops.initialize =3D sh4_translate_init; =20 cc->gdb_num_core_regs =3D 59; =20 dc->vmsd =3D &vmstate_sh_cpu; + cc->tcg_ops =3D &superh_tcg_ops; } =20 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \ diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 1b785f60df..aece2c7dc8 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -848,6 +848,23 @@ static Property sparc_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps sparc_tcg_ops =3D { + .initialize =3D sparc_tcg_init, + .synchronize_from_tb =3D sparc_cpu_synchronize_from_tb, + .cpu_exec_interrupt =3D sparc_cpu_exec_interrupt, + .tlb_fill =3D sparc_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D sparc_cpu_do_interrupt, + .do_transaction_failed =3D sparc_cpu_do_transaction_failed, + .do_unaligned_access =3D sparc_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; +#endif /* CONFIG_TCG */ + static void sparc_cpu_class_init(ObjectClass *oc, void *data) { SPARCCPUClass *scc =3D SPARC_CPU_CLASS(oc); @@ -863,31 +880,25 @@ static void sparc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->class_by_name =3D sparc_cpu_class_by_name; cc->parse_features =3D sparc_cpu_parse_features; cc->has_work =3D sparc_cpu_has_work; - cc->tcg_ops.do_interrupt =3D sparc_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt =3D sparc_cpu_exec_interrupt; cc->dump_state =3D sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) cc->memory_rw_debug =3D sparc_cpu_memory_rw_debug; #endif cc->set_pc =3D sparc_cpu_set_pc; - cc->tcg_ops.synchronize_from_tb =3D sparc_cpu_synchronize_from_tb; cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; - cc->tcg_ops.tlb_fill =3D sparc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->tcg_ops.do_transaction_failed =3D sparc_cpu_do_transaction_failed; - cc->tcg_ops.do_unaligned_access =3D sparc_cpu_do_unaligned_access; cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_sparc_cpu; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; - cc->tcg_ops.initialize =3D sparc_tcg_init; =20 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) cc->gdb_num_core_regs =3D 86; #else cc->gdb_num_core_regs =3D 72; #endif + cc->tcg_ops =3D &sparc_tcg_ops; } =20 static const TypeInfo sparc_cpu_type_info =3D { diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 7d4ead4ef1..d969c2f133 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -134,6 +134,18 @@ static bool tilegx_cpu_exec_interrupt(CPUState *cs, in= t interrupt_request) return false; } =20 +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps tilegx_tcg_ops =3D { + .initialize =3D tilegx_tcg_init, + .cpu_exec_interrupt =3D tilegx_cpu_exec_interrupt, + .tlb_fill =3D tilegx_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D tilegx_cpu_do_interrupt, +#endif /* !CONFIG_USER_ONLY */ +}; + static void tilegx_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -147,13 +159,10 @@ static void tilegx_cpu_class_init(ObjectClass *oc, vo= id *data) =20 cc->class_by_name =3D tilegx_cpu_class_by_name; cc->has_work =3D tilegx_cpu_has_work; - cc->tcg_ops.do_interrupt =3D tilegx_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt =3D tilegx_cpu_exec_interrupt; cc->dump_state =3D tilegx_cpu_dump_state; cc->set_pc =3D tilegx_cpu_set_pc; - cc->tcg_ops.tlb_fill =3D tilegx_cpu_tlb_fill; cc->gdb_num_core_regs =3D 0; - cc->tcg_ops.initialize =3D tilegx_tcg_init; + cc->tcg_ops =3D &tilegx_tcg_ops; } =20 static const TypeInfo tilegx_cpu_type_info =3D { diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 9b21b640e2..0b1e139bcb 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -142,6 +142,14 @@ static void tc27x_initfn(Object *obj) set_feature(&cpu->env, TRICORE_FEATURE_161); } =20 +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps tricore_tcg_ops =3D { + .initialize =3D tricore_tcg_init, + .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, + .tlb_fill =3D tricore_cpu_tlb_fill, +}; + static void tricore_cpu_class_init(ObjectClass *c, void *data) { TriCoreCPUClass *mcc =3D TRICORE_CPU_CLASS(c); @@ -162,10 +170,8 @@ static void tricore_cpu_class_init(ObjectClass *c, voi= d *data) =20 cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; - cc->tcg_ops.synchronize_from_tb =3D tricore_cpu_synchronize_from_tb; cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; - cc->tcg_ops.initialize =3D tricore_tcg_init; - cc->tcg_ops.tlb_fill =3D tricore_cpu_tlb_fill; + cc->tcg_ops =3D &tricore_tcg_ops; } =20 #define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index e27ffc571a..0258884f84 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -120,6 +120,18 @@ static const VMStateDescription vmstate_uc32_cpu =3D { .unmigratable =3D 1, }; =20 +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps uc32_tcg_ops =3D { + .initialize =3D uc32_translate_init, + .cpu_exec_interrupt =3D uc32_cpu_exec_interrupt, + .tlb_fill =3D uc32_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D uc32_cpu_do_interrupt, +#endif /* !CONFIG_USER_ONLY */ +}; + static void uc32_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -131,14 +143,11 @@ static void uc32_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D uc32_cpu_class_by_name; cc->has_work =3D uc32_cpu_has_work; - cc->tcg_ops.do_interrupt =3D uc32_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt =3D uc32_cpu_exec_interrupt; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; - cc->tcg_ops.tlb_fill =3D uc32_cpu_tlb_fill; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; - cc->tcg_ops.initialize =3D uc32_translate_init; dc->vmsd =3D &vmstate_uc32_cpu; + cc->tcg_ops =3D &uc32_tcg_ops; } =20 #define DEFINE_UNICORE32_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 4b6381569f..e2b2c7a71c 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -181,6 +181,21 @@ static const VMStateDescription vmstate_xtensa_cpu =3D= { .unmigratable =3D 1, }; =20 +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps xtensa_tcg_ops =3D { + .initialize =3D xtensa_translate_init, + .cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt, + .tlb_fill =3D xtensa_cpu_tlb_fill, + .debug_excp_handler =3D xtensa_breakpoint_handler, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D xtensa_cpu_do_interrupt, + .do_transaction_failed =3D xtensa_cpu_do_transaction_failed, + .do_unaligned_access =3D xtensa_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + static void xtensa_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -194,23 +209,17 @@ static void xtensa_cpu_class_init(ObjectClass *oc, vo= id *data) =20 cc->class_by_name =3D xtensa_cpu_class_by_name; cc->has_work =3D xtensa_cpu_has_work; - cc->tcg_ops.do_interrupt =3D xtensa_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt; cc->dump_state =3D xtensa_cpu_dump_state; cc->set_pc =3D xtensa_cpu_set_pc; cc->gdb_read_register =3D xtensa_cpu_gdb_read_register; cc->gdb_write_register =3D xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint =3D true; - cc->tcg_ops.tlb_fill =3D xtensa_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->tcg_ops.do_unaligned_access =3D xtensa_cpu_do_unaligned_access; cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; - cc->tcg_ops.do_transaction_failed =3D xtensa_cpu_do_transaction_failed; #endif - cc->tcg_ops.debug_excp_handler =3D xtensa_breakpoint_handler; cc->disas_set_info =3D xtensa_cpu_disas_set_info; - cc->tcg_ops.initialize =3D xtensa_translate_init; dc->vmsd =3D &vmstate_xtensa_cpu; + cc->tcg_ops =3D &xtensa_tcg_ops; } =20 static const TypeInfo xtensa_cpu_type_info =3D { diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 27ab243c6e..9867d0a6e4 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10827,6 +10827,23 @@ static Property ppc_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps ppc_tcg_ops =3D { + .initialize =3D ppc_translate_init, + .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, + .tlb_fill =3D ppc_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D ppc_cpu_do_interrupt, + .cpu_exec_enter =3D ppc_cpu_exec_enter, + .cpu_exec_exit =3D ppc_cpu_exec_exit, + .do_unaligned_access =3D ppc_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; +#endif /* CONFIG_TCG */ + static void ppc_cpu_class_init(ObjectClass *oc, void *data) { PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); @@ -10878,21 +10895,13 @@ static void ppc_cpu_class_init(ObjectClass *oc, v= oid *data) #ifndef CONFIG_USER_ONLY cc->virtio_is_big_endian =3D ppc_cpu_is_big_endian; #endif -#ifdef CONFIG_TCG - cc->tcg_ops.initialize =3D ppc_translate_init; - cc->tcg_ops.cpu_exec_interrupt =3D ppc_cpu_exec_interrupt; - cc->tcg_ops.do_interrupt =3D ppc_cpu_do_interrupt; - cc->tcg_ops.tlb_fill =3D ppc_cpu_tlb_fill; -#ifndef CONFIG_USER_ONLY - cc->tcg_ops.cpu_exec_enter =3D ppc_cpu_exec_enter; - cc->tcg_ops.cpu_exec_exit =3D ppc_cpu_exec_exit; - cc->tcg_ops.do_unaligned_access =3D ppc_cpu_do_unaligned_access; -#endif /* !CONFIG_USER_ONLY */ -#endif /* CONFIG_TCG */ - cc->disas_set_info =3D ppc_disas_set_info; =20 dc->fw_name =3D "PowerPC,UNKNOWN"; + +#ifdef CONFIG_TCG + cc->tcg_ops =3D &ppc_tcg_ops; +#endif /* CONFIG_TCG */ } =20 static const TypeInfo ppc_cpu_type_info =3D { diff --git a/MAINTAINERS b/MAINTAINERS index 00626941f1..c8559b34d7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -129,6 +129,7 @@ F: include/exec/helper*.h F: include/exec/tb-hash.h F: include/sysemu/cpus.h F: include/sysemu/tcg.h +F: include/hw/core/tcg-cpu-ops.h =20 FPU emulation M: Aurelien Jarno --=20 2.25.1