From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612547701; cv=none; d=zohomail.com; s=zohoarc; b=OB3n4n9o6ekdsV0x6RPBwmAKDlAaxQQmfqGuOZcUgBK0fPMhV4q7r0Sk15+RIIUZ/jreqOaMdWTxHmg8GVfJXowZRCrQV72qan480W64jS4ZdFLGw0xE4uu+fQtBXl+8viok9vS/qRI+cb2eft8gqvYOcnfnwwW8DHiivTOCpVs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612547701; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=g+EZctwruwxJ+bIOTViWFK3zdYVscML+NxpdSxKPVAo=; b=DKAqtxpInebbS9fDZT33AfLJHFtRo3nMZadklz28kmisfSz67CIi7oic2bbimkls4StXaVy5/LlJahn4m63BnKi+s1sQyoebROdgPhbO0Dbb4/frqRdcK9EotEU45tLPdK9q2fNSQEfXhApmVa2wNIwqWnlPVwAgFaT/fuRvqjo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612547701488921.6393820158274; Fri, 5 Feb 2021 09:55:01 -0800 (PST) Received: from localhost ([::1]:36604 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l85Js-0000Qm-B0 for importer@patchew.org; Fri, 05 Feb 2021 12:55:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45924) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l84TG-0006bq-KU for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:00:40 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:54108) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l84T3-0003zK-Cn for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:00:36 -0500 Received: by mail-wm1-x336.google.com with SMTP id j11so6564364wmi.3 for ; Fri, 05 Feb 2021 09:00:23 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=g+EZctwruwxJ+bIOTViWFK3zdYVscML+NxpdSxKPVAo=; b=Qvp1pu4u+vQKimrApKXyxwfCm/A3lbHEMeMumikqS/kes2ckAZiLYMYis9DgDtPnuV sAUxp9ba40f0HUl5kqgedpLD8Rcr6YJrrYrjaEJ9OM+ftu/DC1K5s60/PRBUcDqhSSdp LbYmxV6TN06Z8J1GW8cbf0PbcXxeAyEcVIEorL6BoJuP4/kNUptADtLhN50z1q2b6wgx vw1SkZgeLe7aDBipIDUU4YMPqvno26U+mlzSVFZLt/TN+Xla4yu8N/+amQdqeUQl209c LvrUrfN7S2rSUH7/JjLFyn/kHDGguVo+gKT7Rl2ze2VEa/270LAWSuJYESCaf9Qn9oxD vp8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g+EZctwruwxJ+bIOTViWFK3zdYVscML+NxpdSxKPVAo=; b=LmozJUo3qHDnHA+cXP/CjVneo8xyPVsI1b6R1eh9qsHqH1JmGmDigxqatu+dPlDFYw q6Pz3QL29RcHje43bpdkFIbOo9eKAMkF2fWwrDjnlC1wkmo2TqvY2Dk4otwbQM86I3qy niQMK7NZfCj/gyhlaUG2gWcDzza5fqwtbFVFVDXzTKi3XW362Xwu1np2vx0f3uEUDzG9 M/brke7EFzUIqfNTMLwKhFo63jAoAcuEXDCc4HjgYttoe5mN32Tm2vVK/jCRzNgI4oyc QmUtRsTay9I79gRKXRQB0T8hr/zuYNxERigRVeANgHMFPXfnGOdXug+3LLwbMnCKGlD2 fCcw== X-Gm-Message-State: AOAM531gnDl+NzOoM9zQ6xqb9pnbNE15/wnOpdirqKhI/NWcHdg80qFk FoYMHo7aFqjUVjjRjKd45TbzjA== X-Google-Smtp-Source: ABdhPJyJI+24ZSsT72N9vbEpG1HnwbDWVFUEVkUK1ECZDF0tZyMXEj6Spu+2w00GiAlUK0SjUMuEKQ== X-Received: by 2002:a1c:2905:: with SMTP id p5mr4288589wmp.156.1612544422513; Fri, 05 Feb 2021 09:00:22 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 01/24] hw/arm/mps2-tz: Make SYSCLK frequency board-specific Date: Fri, 5 Feb 2021 16:59:56 +0000 Message-Id: <20210205170019.25319-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The AN524 has a different SYSCLK frequency from the AN505 and AN521; make the SYSCLK frequency a field in the MPS2TZMachineClass rather than a compile-time constant so we can support the AN524. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 90caa914934..82ce6262817 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -76,6 +76,7 @@ struct MPS2TZMachineClass { MachineClass parent; MPS2TZFPGAType fpga_type; uint32_t scc_id; + uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ const char *armsse_type; }; =20 @@ -111,8 +112,6 @@ struct MPS2TZMachineState { =20 OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) =20 -/* Main SYSCLK frequency in Hz */ -#define SYSCLK_FRQ 20000000 /* Slow 32Khz S32KCLK frequency in Hz */ #define S32KCLK_FRQ (32 * 1000) =20 @@ -186,6 +185,7 @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState = *mms, static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size) { + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart =3D opaque; int i =3D uart - &mms->uart[0]; int rxirqno =3D i * 2; @@ -196,7 +196,7 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms,= void *opaque, =20 object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART); qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); - qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); + qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->sysclk_frq); sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); s =3D SYS_BUS_DEVICE(uart); sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); @@ -403,7 +403,7 @@ static void mps2tz_common_init(MachineState *machine) =20 /* These clocks don't need migration because they are fixed-frequency = */ mms->sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); - clock_set_hz(mms->sysclk, SYSCLK_FRQ); + clock_set_hz(mms->sysclk, mmc->sysclk_frq); mms->s32kclk =3D clock_new(OBJECT(machine), "S32KCLK"); clock_set_hz(mms->s32kclk, S32KCLK_FRQ); =20 @@ -670,6 +670,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, vo= id *data) mmc->fpga_type =3D FPGA_AN505; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id =3D 0x41045050; + mmc->sysclk_frq =3D 20 * 1000 * 1000; /* 20MHz */ mmc->armsse_type =3D TYPE_IOTKIT; } =20 @@ -685,6 +686,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, vo= id *data) mmc->fpga_type =3D FPGA_AN521; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id =3D 0x41045210; + mmc->sysclk_frq =3D 20 * 1000 * 1000; /* 20MHz */ mmc->armsse_type =3D TYPE_SSE200; } =20 --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612547898; cv=none; d=zohomail.com; s=zohoarc; b=DDLPzF7EU9yZnEw20ueunL8I7VuGNjWCJ2m3vrJVrM8yQ9P0yE2ZKiPvswVy6SKPaSjq3M63Bhdd9+E6L45fPtwfVKAG4MUTQWm9DGXWmEXwcePg/jnNlnuF3TMp3iFYh7g/xPjp/ocHpnRMeyAp053nikB9dlgd3Hp/1tdgzwg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612547898; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6e/ocFlNpbvzWzShp69RWnr5b+cScjq0s1B9GZ0rX5w=; b=CQ3Zc64s9hdBVx/Of9ljlRYwysFCtyV3o014roWBjcXcsSLI/pErTJWKhGBM38Xr46hX1xn1lXgPpXvxZjO83iqh4rgtQKOFy5gAn3S0OXCvqL4vGiniKA+RgEpEJLSPL7kqem4OcjqzSigX5v/GwT+7iXSjbQNMQUA2i3CiaWI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612547898897880.8777514470328; Fri, 5 Feb 2021 09:58:18 -0800 (PST) Received: from localhost ([::1]:46496 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l85N3-0004cS-NW for importer@patchew.org; Fri, 05 Feb 2021 12:58:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46020) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l84TO-0006eU-S0 for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:00:48 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:38578) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l84T3-000400-GM for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:00:46 -0500 Received: by mail-wm1-x330.google.com with SMTP id y187so6447735wmd.3 for ; Fri, 05 Feb 2021 09:00:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6e/ocFlNpbvzWzShp69RWnr5b+cScjq0s1B9GZ0rX5w=; b=VU1fOfjB2vqX/Qnx5iw3D6D2LKQ5cXEMGUOcCXoeSDIPHiT8skK9dQ+bcMEdO7KO5o mC9qvqGOsXgevNc5lM4IM8r3Ef7vlEABp1I55DxtpSQCkI/t9A5gzCuBvUDkRJ2GuxsJ 6akzD/X3yWBAUf3FzNvPc5WuJpGhy7SaFS6gSfa/7bBN2as44MgjiZKx0RjVEXWEp4tQ 1nfZ8cdhpTg1ZZXLJ/q99IZ+ir3NpZ1/x4VkVkH04nsJk1RjSdLmpCH2MpkkWgxJqQvp /TLb5A+U15K9ZgKhVfdtxs7GT914ofbI32qNOUKdQ6Xu3agB4xt1DL1Z+m9OexoN6wra Twvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6e/ocFlNpbvzWzShp69RWnr5b+cScjq0s1B9GZ0rX5w=; b=deSb9FcMmWwAveO051RF8tzWXYAd0HEL93pgT+eTitdjEvExQY+U5cenVP5xkAzU23 ZMRJoohSzf3VJJro3DfsRztxuCjPWnTQhzv+/AbmQjarwaERXQEyMCbV2y1/xw2Phjxm py5v4XlTrECHhSdUAmP8VFsfzXns2vfWkNxsGi9UwhRY9iWUHMJ2jpgW2gew5c7g0/kG 1uEq+I6KIYBv5r6mfcr/d2/LghL1bynLAekbR2trThTfaMavIwz/0dVuw3mkh3YDED/T JkqpYJkYvEvKE87MzjKRT3dlG54Wm1kl9y3TkzxmYehBwukAkEm11qnMZgBBEao7jn5p lg/w== X-Gm-Message-State: AOAM532nbXMdGxHjlQiCxnoRLSSI6buNA0nHCct6WPEzj0A3BnVS58jz xcueykyzz/v+s1UoavaNI7wkrw== X-Google-Smtp-Source: ABdhPJzWKPvIEAKCmVNCEUVyCzbULaEZg7w+QFOYy+JZneu3IYKAOLki6bAyCyBbkIkOrKnM+I3Rsg== X-Received: by 2002:a05:600c:4e8e:: with SMTP id f14mr4348607wmq.139.1612544423375; Fri, 05 Feb 2021 09:00:23 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/24] hw/misc/mps2-scc: Support configurable number of OSCCLK values Date: Fri, 5 Feb 2021 16:59:57 +0000 Message-Id: <20210205170019.25319-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Currently the MPS2 SCC device implements a fixed number of OSCCLK values (3). The variant of this device in the MPS3 AN524 board has 6 OSCCLK values. Switch to using a PROP_ARRAY, which allows board code to specify how large the OSCCLK array should be as well as its values. With a variable-length property array, the SCC no longer specifies default values for the OSCCLKs, so we must set them explicitly in the board code. This defaults are actually incorrect for the an521 and an505; we will correct this bug in a following patch. This is a migration compatibility break for all the mps boards. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- It would be possible to avoid the compat break, but we've already broken compat for the mps boards this release cycle (eg in commit eeae0b2bf4e69de2) when we added Clock support to the armsse code, so there's no point in trying to keep compat for this change. --- include/hw/misc/mps2-scc.h | 7 +++---- hw/arm/mps2-tz.c | 5 +++++ hw/arm/mps2.c | 5 +++++ hw/misc/mps2-scc.c | 24 +++++++++++++----------- 4 files changed, 26 insertions(+), 15 deletions(-) diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h index f65d8732031..514da49f69e 100644 --- a/include/hw/misc/mps2-scc.h +++ b/include/hw/misc/mps2-scc.h @@ -19,8 +19,6 @@ #define TYPE_MPS2_SCC "mps2-scc" OBJECT_DECLARE_SIMPLE_TYPE(MPS2SCC, MPS2_SCC) =20 -#define NUM_OSCCLK 3 - struct MPS2SCC { /*< private >*/ SysBusDevice parent_obj; @@ -39,8 +37,9 @@ struct MPS2SCC { uint32_t dll; uint32_t aid; uint32_t id; - uint32_t oscclk[NUM_OSCCLK]; - uint32_t oscclk_reset[NUM_OSCCLK]; + uint32_t num_oscclk; + uint32_t *oscclk; + uint32_t *oscclk_reset; }; =20 #endif diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 82ce6262817..7c066c11ed4 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -219,6 +219,11 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms,= void *opaque, qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); + /* This will need to be per-FPGA image eventually */ + qdev_prop_set_uint32(sccdev, "len-oscclk", 3); + qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000); + qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000); + qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); } diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 39add416db5..81413b7133e 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -373,6 +373,11 @@ static void mps2_common_init(MachineState *machine) qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); + /* All these FPGA images have the same OSCCLK configuration */ + qdev_prop_set_uint32(sccdev, "len-oscclk", 3); + qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000); + qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000); + qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000); object_initialize_child(OBJECT(mms), "fpgaio", diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index ce1dfe93562..52a4e183b71 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -57,7 +57,7 @@ static bool scc_cfg_write(MPS2SCC *s, unsigned function, { trace_mps2_scc_cfg_write(function, device, value); =20 - if (function !=3D 1 || device >=3D NUM_OSCCLK) { + if (function !=3D 1 || device >=3D s->num_oscclk) { qemu_log_mask(LOG_GUEST_ERROR, "MPS2 SCC config write: bad function %d device %d\n", function, device); @@ -75,7 +75,7 @@ static bool scc_cfg_write(MPS2SCC *s, unsigned function, static bool scc_cfg_read(MPS2SCC *s, unsigned function, unsigned device, uint32_t *value) { - if (function !=3D 1 || device >=3D NUM_OSCCLK) { + if (function !=3D 1 || device >=3D s->num_oscclk) { qemu_log_mask(LOG_GUEST_ERROR, "MPS2 SCC config read: bad function %d device %d\n", function, device); @@ -227,7 +227,7 @@ static void mps2_scc_reset(DeviceState *dev) s->cfgctrl =3D 0x100000; s->cfgstat =3D 0; s->dll =3D 0xffff0001; - for (i =3D 0; i < NUM_OSCCLK; i++) { + for (i =3D 0; i < s->num_oscclk; i++) { s->oscclk[i] =3D s->oscclk_reset[i]; } for (i =3D 0; i < ARRAY_SIZE(s->led); i++) { @@ -254,12 +254,14 @@ static void mps2_scc_realize(DeviceState *dev, Error = **errp) LED_COLOR_GREEN, name); g_free(name); } + + s->oscclk =3D g_new0(uint32_t, s->num_oscclk); } =20 static const VMStateDescription mps2_scc_vmstate =3D { .name =3D "mps2-scc", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_UINT32(cfg0, MPS2SCC), VMSTATE_UINT32(cfg1, MPS2SCC), @@ -268,7 +270,8 @@ static const VMStateDescription mps2_scc_vmstate =3D { VMSTATE_UINT32(cfgctrl, MPS2SCC), VMSTATE_UINT32(cfgstat, MPS2SCC), VMSTATE_UINT32(dll, MPS2SCC), - VMSTATE_UINT32_ARRAY(oscclk, MPS2SCC, NUM_OSCCLK), + VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk, + 0, vmstate_info_uint32, uint32_t), VMSTATE_END_OF_LIST() } }; @@ -280,14 +283,13 @@ static Property mps2_scc_properties[] =3D { DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0), DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0), DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0), - /* These are the initial settings for the source clocks on the board. + /* + * These are the initial settings for the source clocks on the board. * In hardware they can be configured via a config file read by the * motherboard configuration controller to suit the FPGA image. - * These default values are used by most of the standard FPGA images. */ - DEFINE_PROP_UINT32("oscclk0", MPS2SCC, oscclk_reset[0], 50000000), - DEFINE_PROP_UINT32("oscclk1", MPS2SCC, oscclk_reset[1], 24576000), - DEFINE_PROP_UINT32("oscclk2", MPS2SCC, oscclk_reset[2], 25000000), + DEFINE_PROP_ARRAY("oscclk", MPS2SCC, num_oscclk, oscclk_reset, + qdev_prop_uint32, uint32_t), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Xp3VtAOG1GswVbARvzGyUBGRaDF2ix07eBPCXFhqLuk=; b=zzMjQ8kG+iiRuUcKWhuNiYn/oiaJh2lpMWqNQdJ5NtXsp0k3Ka3xqWvULtSgGTF1ae 4ZgVphvW0q5Te64U5tmn0qNKGbVVPZ7WdeDWkCOjWX7m4AF6Tm585p7GxHc7CPIh1At+ 32bnD2skwB+RTPMIxKeioerKusBGAErIR1uUEImSQoYibiQrMu/1+kUPKarAOs26KDot W3VWzph5tagVSRzWSU2CxEkq4CfEPUN3K0Jt/KW/7ADgaRx/0x2FufLVz3EP1i1cQdAd To5TOK2y/vMn6G/FlRz83URtlbO//+81meUB7bWVowXPQ43CJiwWSYSYDwrtyxHYnKI3 WNEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Xp3VtAOG1GswVbARvzGyUBGRaDF2ix07eBPCXFhqLuk=; b=ctVAs8mXYiBCV/pN+7Dkm4EnVidns5Oy5yzwYKgTGNRgV0Fn0Lrg0mvij+p8c+vb0e 7Dq5h6ZnTN1zQ5zgmdsh44dmC788KmKdvezvJrxjUuhkPvcieokiHNoEBwSs92pfR9iw pioZvERAz3YM11cm2CJjQUEdQ0XfDHAGcOXx2QeCkdrtJqmrA7OtbhmnAqQb0Xvj1jtl fGHYzso0bt7V9rloqzRzL53kyPLrzRjeKOe04OrTDgiWiVT9omZeqmKsedNHOjLSRXBR fD1yixlWwH9FIYvELC7++83KHY27G+uOjJLx1ze1CnNRD/HlPuhitkJzhF0hkok2NP60 2zzw== X-Gm-Message-State: AOAM532AYBgyPvYXwSSvooXVbSlxOLs+SwvVlE5SuLIjhK406JYlIKYH JkXwPf2ozKlnWSDtXmEmofOqG2YIdwq5Lw== X-Google-Smtp-Source: ABdhPJwVz27R8ZPA1ynLB7RMN9BmkV+QXBCU4Gx/MPsVa0WXFpQj/tXAlmRbbC1MinOkFAGBFTjOWA== X-Received: by 2002:a1c:d7:: with SMTP id 206mr4414038wma.68.1612544424256; Fri, 05 Feb 2021 09:00:24 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 03/24] hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511 Date: Fri, 5 Feb 2021 16:59:58 +0000 Message-Id: <20210205170019.25319-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We were previously using the default OSCCLK settings, which are correct for the older MPS2 boards (mps2-an385, mps2-an386, mps2-an500, mps2-an511), but wrong for the mps2-an505 and mps2-511 implemented in mps2-tz.c. Now we're setting the values explicitly we can fix them to be correct. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 7c066c11ed4..976f5f5c682 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -221,8 +221,8 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, = void *opaque, qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); /* This will need to be per-FPGA image eventually */ qdev_prop_set_uint32(sccdev, "len-oscclk", 3); - qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000); - qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000); + qdev_prop_set_uint32(sccdev, "oscclk[0]", 40000000); + qdev_prop_set_uint32(sccdev, "oscclk[1]", 24580000); qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612548196; cv=none; d=zohomail.com; s=zohoarc; b=dfedZzwajC1S1TBri1FfEBmSBDb8EoUz1r4vY/GPiRNzzfr+CRUZU2ucSvqyTIMjtjKHeaMEfDZcbLl/I2SRsgbHTdaDq9ZxEs6CwLjslrsP/2wfodt5/ob3jYWzqGVu59bCSad9mJ3LPBZg8Nhy57EnJriVsEqobT/+IHb93pI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612548196; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FHr6FuqE0B2b9d2HJA4DI+zb7En8n9XfTjpsu+vmnps=; b=f8Psj7QIQzeo0sOQdY7d6lNqoSzkba/svXllFH0SjYuWA8R3IxyOfMPR0umcMupb8OTiQj2JeTOKK9qqjTneBfTk1U6E/zHQUQ8wtfTon9Io7MatAteiDdR7oo2vi8JzovZg+ha/nIzK2je0MLMAg4CpJxDDiA39zccWJw2OQKo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612548196346623.7430413755719; Fri, 5 Feb 2021 10:03:16 -0800 (PST) Received: from localhost ([::1]:56560 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l85Rp-0000cJ-QE for importer@patchew.org; Fri, 05 Feb 2021 13:03:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46152) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l84TZ-0006kM-Uz for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:00:58 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:34278) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l84T8-00041a-Nh for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:00:57 -0500 Received: by mail-wm1-x32b.google.com with SMTP id o10so8223197wmc.1 for ; Fri, 05 Feb 2021 09:00:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FHr6FuqE0B2b9d2HJA4DI+zb7En8n9XfTjpsu+vmnps=; b=VwtlGJvqc9vzrrtxKLU+wWrLnXTjlDfg0aroLhg4kM1G3UF0A8Z4NgDMZ9mYx/1fBg RCj8pWT1J6SogJaBttzVilfetr05xULGMdAfbCenKz8G92aSaQmaPViZhO2ZxtpT+tUp l9YcYGvE7uKWs27P4csHIGkWs3vCdfXY52/ZNd17YGHY69p/gb4ASNOHtmanPAMACbb+ ytBqkBAbse4qGtcxToac1I0l4SbIqjw9gomjNWbwVWkObH34A6L1piRGLYeoZGr43P/w TScjOuZ75Xnetq9YJxCBX/n3OX9qXHfTNH8jswv7EsBN1zte7D0bVWcGz3uXFe67ahbs kkrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FHr6FuqE0B2b9d2HJA4DI+zb7En8n9XfTjpsu+vmnps=; b=o0pyHJXj90k53I1OxCd3X28gSzKD/z+BRnfWbjMqhhzcM9Z/Td5s55S1sGhZk7ziJy H+QAd8WfZkZxq1o/wTA+/bEHjsJ2BYezQhrlAEKN6Md8DxesIqA0gXoO8D/vI61kdtCT Oj82hK0lz00LQUpg9PZNu3TSw6/MzA/qUUe6ZymXXtpu2CYGkbdHH6pefGuPtCyTCWk7 nBS3RDmVK2Q0F65wtg88CUDCR9oq9DAW2njTiWLRkV/RLtm2eC4cvcT2JPPSTcrs3qnp erYusCGNPFu5aJS5Rr5lMTMwRYVJTXsm9fyqyoUyA0wAQDrv8oFFz7qRA2/tQmF70VzF 7eag== X-Gm-Message-State: AOAM532cO9cprDRSmVMXQCVTUMpSUfRkXjsqQQtoydo6Rr/jdfPoEodT hBZHHiKdkzsb7L9TFCMVqM1oyIAmJkAocw== X-Google-Smtp-Source: ABdhPJzO8461YBBzNNJZgcfXlkxRXibCIejMuMAm0szLwSMhmwceM2Pv3abohSEFdFb9voabClranw== X-Received: by 2002:a05:600c:3504:: with SMTP id h4mr4444267wmq.168.1612544425124; Fri, 05 Feb 2021 09:00:25 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/24] hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board Date: Fri, 5 Feb 2021 16:59:59 +0000 Message-Id: <20210205170019.25319-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The AN505 and AN511 happen to share the same OSCCLK values, but the AN524 will have a different set (and more of them), so split the settings out to be per-board. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 976f5f5c682..9add1453cc2 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -77,6 +77,8 @@ struct MPS2TZMachineClass { MPS2TZFPGAType fpga_type; uint32_t scc_id; uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ + uint32_t len_oscclk; + const uint32_t *oscclk; const char *armsse_type; }; =20 @@ -115,6 +117,12 @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineC= lass, MPS2TZ_MACHINE) /* Slow 32Khz S32KCLK frequency in Hz */ #define S32KCLK_FRQ (32 * 1000) =20 +static const uint32_t an505_oscclk[] =3D { + 40000000, + 24580000, + 25000000, +}; + /* Create an alias of an entire original MemoryRegion @orig * located at @base in the memory map. */ @@ -213,17 +221,18 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms= , void *opaque, MPS2SCC *scc =3D opaque; DeviceState *sccdev; MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); + int i; =20 object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); sccdev =3D DEVICE(scc); qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); - /* This will need to be per-FPGA image eventually */ - qdev_prop_set_uint32(sccdev, "len-oscclk", 3); - qdev_prop_set_uint32(sccdev, "oscclk[0]", 40000000); - qdev_prop_set_uint32(sccdev, "oscclk[1]", 24580000); - qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); + qdev_prop_set_uint32(sccdev, "len-oscclk", mmc->len_oscclk); + for (i =3D 0; i < mmc->len_oscclk; i++) { + g_autofree char *propname =3D g_strdup_printf("oscclk[%d]", i); + qdev_prop_set_uint32(sccdev, propname, mmc->oscclk[i]); + } sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); } @@ -676,6 +685,8 @@ static void mps2tz_an505_class_init(ObjectClass *oc, vo= id *data) mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id =3D 0x41045050; mmc->sysclk_frq =3D 20 * 1000 * 1000; /* 20MHz */ + mmc->oscclk =3D an505_oscclk; + mmc->len_oscclk =3D ARRAY_SIZE(an505_oscclk); mmc->armsse_type =3D TYPE_IOTKIT; } =20 @@ -692,6 +703,8 @@ static void mps2tz_an521_class_init(ObjectClass *oc, vo= id *data) mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id =3D 0x41045210; mmc->sysclk_frq =3D 20 * 1000 * 1000; /* 20MHz */ + mmc->oscclk =3D an505_oscclk; /* AN521 is the same as AN505 here */ + mmc->len_oscclk =3D ARRAY_SIZE(an505_oscclk); mmc->armsse_type =3D TYPE_SSE200; } =20 --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612547753; cv=none; d=zohomail.com; s=zohoarc; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vPha70CdlIz8Ft1BgdKuRx55ClhohOzaXUUXYhoxm5M=; b=g/8Lv/PCmVVItNdnAT1VaNzH6B+1ScitB/EWkMXo76JuspwX8JbLRsHlLlLee0nDvW EWrJJV7170rDPEvm6/JvvOJBv0R5dHiecIISaq3C2j3KWh17zKwfN3NdhUeJ3+45Khl/ 0PUmeCACBhuD54Axrp3YkMofMjoHhcl7FGs8tpxROV9vCM1rNuBr7uW/nhAA03wxZ+pr ETdjw0M7A1WllSLuIK+X+MyFkaOGuWko4akScpG6ZOlP3wwxQoi6DKEdIAamjTCsqFs6 mPskzGVRO6jR/oCWmQ0Pd9st2x1d40Id4RF4M0Pr+4s2BKDDdmu/OjRI5hZVMUHrl1Ax t0LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vPha70CdlIz8Ft1BgdKuRx55ClhohOzaXUUXYhoxm5M=; b=dTO623Z/WI78uXIFs3uJlAUbp+RxFzE8qbwhIGRGX2wAe+jukPdMiOUjUnftodjGJr L2Dh5JSIptzR7gNwFgfOC70mww7VjNWxCTkj6kwAWb7Mdw4oW0tGWVnGg4GXbrCos8S4 CHNa9Gdr7WRnr+yFGBCYOmvlf0Jw6UuOk21K4+L3Vzcntl6sPh5U4r5fZPm1UYqta+En HbNpVMBSUSgSjoPyTLHW6er5lKqbCGq/NrAgqZj2PV0cKzvgj1XWLv8SvxVO30Kpbzfm In1QsLFzk8JXZATuj1QhJiPHEig6t3NEkhV3Mgj3nMvyy8tLjKqJ96AMrGvJSBY2fcpK oniw== X-Gm-Message-State: AOAM531GkXtgErGRv/R/rCWX37HRc9XQGPRkN6tj1PlhjUZ/6mPXAA// 3nx3pEK09Y+LgktV3beq3mWvzEPWCfD+bQ== X-Google-Smtp-Source: ABdhPJwq74pQs3PSxuyoQe+TpvHr/b5JJ6jNvIXFdf6Gyhejr/WqQWr6I7iQVUAL0A0s2EfKV8xeBg== X-Received: by 2002:a5d:6712:: with SMTP id o18mr5862736wru.375.1612544425859; Fri, 05 Feb 2021 09:00:25 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 05/24] hw/misc/mps2-fpgaio: Make number of LEDs configurable by board Date: Fri, 5 Feb 2021 17:00:00 +0000 Message-Id: <20210205170019.25319-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The MPS2 board has 2 LEDs, but the MPS3 board has 10 LEDs. The FPGAIO device is similar on both sets of boards, but the LED0 register has correspondingly more bits that have an effect. Add a device property for number of LEDs. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/mps2-fpgaio.h | 5 ++++- hw/misc/mps2-fpgaio.c | 31 +++++++++++++++++++++++-------- 2 files changed, 27 insertions(+), 9 deletions(-) diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h index a010fdb2b6d..bfe73134e78 100644 --- a/include/hw/misc/mps2-fpgaio.h +++ b/include/hw/misc/mps2-fpgaio.h @@ -28,13 +28,16 @@ #define TYPE_MPS2_FPGAIO "mps2-fpgaio" OBJECT_DECLARE_SIMPLE_TYPE(MPS2FPGAIO, MPS2_FPGAIO) =20 +#define MPS2FPGAIO_MAX_LEDS 32 + struct MPS2FPGAIO { /*< private >*/ SysBusDevice parent_obj; =20 /*< public >*/ MemoryRegion iomem; - LEDState *led[2]; + LEDState *led[MPS2FPGAIO_MAX_LEDS]; + uint32_t num_leds; =20 uint32_t led0; uint32_t prescale; diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c index 6af0e8f837a..b28a1be22cc 100644 --- a/hw/misc/mps2-fpgaio.c +++ b/hw/misc/mps2-fpgaio.c @@ -177,9 +177,14 @@ static void mps2_fpgaio_write(void *opaque, hwaddr off= set, uint64_t value, =20 switch (offset) { case A_LED0: - s->led0 =3D value & 0x3; - led_set_state(s->led[0], value & 0x01); - led_set_state(s->led[1], value & 0x02); + if (s->num_leds !=3D 0) { + int i; + + s->led0 =3D value & MAKE_64BIT_MASK(0, s->num_leds); + for (i =3D 0; i < s->num_leds; i++) { + led_set_state(s->led[i], value & (1 << i)); + } + } break; case A_PRESCALE: resync_counter(s); @@ -238,7 +243,7 @@ static void mps2_fpgaio_reset(DeviceState *dev) s->pscntr =3D 0; s->pscntr_sync_ticks =3D now; =20 - for (size_t i =3D 0; i < ARRAY_SIZE(s->led); i++) { + for (size_t i =3D 0; i < s->num_leds; i++) { device_cold_reset(DEVICE(s->led[i])); } } @@ -256,11 +261,19 @@ static void mps2_fpgaio_init(Object *obj) static void mps2_fpgaio_realize(DeviceState *dev, Error **errp) { MPS2FPGAIO *s =3D MPS2_FPGAIO(dev); + int i; =20 - s->led[0] =3D led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH, - LED_COLOR_GREEN, "USERLED0"); - s->led[1] =3D led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH, - LED_COLOR_GREEN, "USERLED1"); + if (s->num_leds > MPS2FPGAIO_MAX_LEDS) { + error_setg(errp, "num-leds cannot be greater than %d", + MPS2FPGAIO_MAX_LEDS); + return; + } + + for (i =3D 0; i < s->num_leds; i++) { + g_autofree char *ledname =3D g_strdup_printf("USERLED%d", i); + s->led[i] =3D led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_= HIGH, + LED_COLOR_GREEN, ledname); + } } =20 static bool mps2_fpgaio_counters_needed(void *opaque) @@ -303,6 +316,8 @@ static const VMStateDescription mps2_fpgaio_vmstate =3D= { static Property mps2_fpgaio_properties[] =3D { /* Frequency of the prescale counter */ DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000), + /* Number of LEDs controlled by LED0 register */ + DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO, num_leds, 2), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/oJeRnXgSDJEHEJaO9pMCaTGB+0Qu174IkpqLDjGWdU=; b=xiGUezDfHv/GkXr/7aj9xhQDpJePHBEJ2RVtDtSlql8BEoHkWSJco2n2iDcTLnFQJw D8Poap30475CmjufapHWwxh+PbZ0AMDwfp5CusUj8aP9PW/Rc7EDzdSzDbUmA8qat7a8 pJJxTPGl/imoyfeVbhVMi/XJ0Gagw5g2djlU7/De9aJ7TOAtG274ajG4ATXDxa79vOJm /6A2gUtDQ15IYSxraZ4Fy9Kv3RBwuT6t+BiSBb72ugPQQFefnXNvK1oC68/Dw3tj2UKj XqDtfycn0Abs1epZJu0DghI3jyKqnzUqIWAZZn+F6kVAlPyuysx8m7Pd7rf6UEwOAQd0 R8xA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/oJeRnXgSDJEHEJaO9pMCaTGB+0Qu174IkpqLDjGWdU=; b=WZqfGNXNs4JRx+Jaeub5wroRF9XisjCT8o72UCLjwEv6Mpp7JZhzFev6aznYrviNwU lM13fK0PN8GThN1hImxy3VAha3RDsYbcaD0tZGDhMq6/qvXZGq+4Y+twgH8UvT2WUCzu ogGNH0L/WJK2V1dmXO5KXvGsobIllcF7cWIze7yGMyZ3ft6vVLnq0YrdE6cVS64xqrvf iI18spMiBfWzZUIA9NMfI9cXvHQLMFYV0mwEAlyFg/9mRcE+1H16XR9uLf2kdb2tC1tM CPg5Hsw57C5eSUEgcjDROQk99A0iBsSs7rqfBiLzlClL4zMiacbKKnT70ZeoWrA0RT/o V02w== X-Gm-Message-State: AOAM531r34p7Rad72QDb1HiqFInwCdlY2J9tJUEMpTn426jJ4Fi8r+4I SN1tVE3ef3/iv9VAM7C9ab224Q== X-Google-Smtp-Source: ABdhPJwmKLRTjNiQy8X1axUpaeddKNdzJXWIUh1QBqOKhv9DDpUmJExESI+/M8xLJDknR9EoF64H8A== X-Received: by 2002:a05:600c:4f8f:: with SMTP id n15mr4404462wmq.31.1612544426722; Fri, 05 Feb 2021 09:00:26 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 06/24] hw/misc/mps2-fpgaio: Support SWITCH register Date: Fri, 5 Feb 2021 17:00:01 +0000 Message-Id: <20210205170019.25319-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" MPS3 boards have an extra SWITCH register in the FPGAIO block which reports the value of some switches. Implement this, governed by a property the board code can use to specify whether whether it exists. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/mps2-fpgaio.h | 1 + hw/misc/mps2-fpgaio.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h index bfe73134e78..83c6e18a4ee 100644 --- a/include/hw/misc/mps2-fpgaio.h +++ b/include/hw/misc/mps2-fpgaio.h @@ -38,6 +38,7 @@ struct MPS2FPGAIO { MemoryRegion iomem; LEDState *led[MPS2FPGAIO_MAX_LEDS]; uint32_t num_leds; + bool have_switches; =20 uint32_t led0; uint32_t prescale; diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c index b28a1be22cc..b54657a4f07 100644 --- a/hw/misc/mps2-fpgaio.c +++ b/hw/misc/mps2-fpgaio.c @@ -35,6 +35,7 @@ REG32(CLK100HZ, 0x14) REG32(COUNTER, 0x18) REG32(PRESCALE, 0x1c) REG32(PSCNTR, 0x20) +REG32(SWITCH, 0x28) REG32(MISC, 0x4c) =20 static uint32_t counter_from_tickoff(int64_t now, int64_t tick_offset, int= frq) @@ -156,7 +157,15 @@ static uint64_t mps2_fpgaio_read(void *opaque, hwaddr = offset, unsigned size) resync_counter(s); r =3D s->pscntr; break; + case A_SWITCH: + if (!s->have_switches) { + goto bad_offset; + } + /* User-togglable board switches. We don't model that, so report 0= . */ + r =3D 0; + break; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "MPS2 FPGAIO read: bad offset %x\n", (int) offset); r =3D 0; @@ -318,6 +327,7 @@ static Property mps2_fpgaio_properties[] =3D { DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000), /* Number of LEDs controlled by LED0 register */ DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO, num_leds, 2), + DEFINE_PROP_BOOL("have-switches", MPS2FPGAIO, have_switches, false), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612546911; cv=none; d=zohomail.com; s=zohoarc; b=DYEEyIkkTYwt3l7cZNlajhizEEH/KyDIQEhizaiPO3YRr0sQqj/nM8vy6uvmZedas7+6SWrAIt/f+8/2CZXNP8XM09DI6I3dlo25FELTOuyE4inD/zwk/jeCzQn8yGlPrjL1WWjc/Zxaxd7Vgns1vUICIZB4c4PrmnLNvPJFXNg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612546911; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RMlSEt6PiH0qMk4plcisXlg9m+5b90Bk6CfkYCOT5n0=; b=GcN1hgnjoM/bkosignaloCk5YL+8tR67M1MhF4vlOEHLTWsreggjUjYUOK95N7PaWsJcDHpOG/ZNJFRHVLjB6SlixdDvOnqC4puTWoqWaoI3Mqrmhe3vleEkKJ4PggQQqkoYeGfyCimo04bo2XfOjlNrxGCGEPCcmmEXZPzCKkI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612546911921489.3416735141228; Fri, 5 Feb 2021 09:41:51 -0800 (PST) Received: from localhost ([::1]:37172 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8578-0005Zy-TN for importer@patchew.org; Fri, 05 Feb 2021 12:41:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46174) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l84Td-0006m0-G1 for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:02 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:35379) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l84T8-000439-OP for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:01 -0500 Received: by mail-wr1-x433.google.com with SMTP id l12so8485577wry.2 for ; Fri, 05 Feb 2021 09:00:28 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=RMlSEt6PiH0qMk4plcisXlg9m+5b90Bk6CfkYCOT5n0=; b=vbfFqhNMDID3Tq4WnXtj/B2iEi46MaVQecWXaH7uv2XJgxqARyIf5WxSSqr0B7ztvN 5RrNU0VUzhQoONZoL1y/nlsbqoa6wk2WPggrN3M54QuThfzix8HxJK+0WkVRFIOqqVWS rgqT0ajJASPdK38jXZyCgGB0NIdycmNQ0IFV6vz8SKl13Uq2wtC4W/dq9aJGUpkCJTWd JaNmGSX30keRBld/wiL5BRKlCndatLB7U/BVtT6ac7EALdMrvf5rsP7cZ+YTi78JhbGD w3v3tjo1r84jOn0IWYNhzffncSoqfFrJAJIorGwUCk/bREBPwClANSjaxYnPf8yv9lTF OgJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RMlSEt6PiH0qMk4plcisXlg9m+5b90Bk6CfkYCOT5n0=; b=KxWJE1z0oO3bpXzqeqqBEpmptzUuNl3RjYPKbtpLUmcm84PUOI6rQNoLL240CTPGFu N4WLwgd32e+MDtyjTepOC37pOd669pjxF+QpJWpvuGc8RYii6rqtVHk8h0qbRvKNFIkE w0oSLxyO8jRc9yv82HUXLjNfo+EuuSS/W0OsvMOnutMJC4ceRwmwo3ineJCsz+1Vx9aD O36STaQEuXx9ymCblbPBqvzasQ44f/ffPt17jfIf8/oMQC2OVdLDVg8u2LNic7aGKgGU 7wfwH3NpvMef8uf+DwGW3TAxqn57JoJVtH8UthzTQeptNgV03SdsiiN7XojGofV/C8jt QATQ== X-Gm-Message-State: AOAM530ElhbHOhk5qY9e09rj2k4ci4gdcxK9+BKLhrT1wLxDXTeEMWbp JgWEA493apQLdVwfNl286N4v876Xm4j4DA== X-Google-Smtp-Source: ABdhPJyTBeVt0JOPV+n4JwGZLwSJArPUngUMEK/PxchKlLXawU2q7EpDp8NEJ/VqfZBRZFWs95PiXg== X-Received: by 2002:a5d:50d2:: with SMTP id f18mr6334526wrt.338.1612544427436; Fri, 05 Feb 2021 09:00:27 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 07/24] hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board Date: Fri, 5 Feb 2021 17:00:02 +0000 Message-Id: <20210205170019.25319-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Set the FPGAIO num-leds and have-switches properties explicitly per-board, rather than relying on the defaults. The AN505 and AN521 both have the same settings as the default values, but the AN524 will be different. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 9add1453cc2..94618ae54d2 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -79,6 +79,8 @@ struct MPS2TZMachineClass { uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ uint32_t len_oscclk; const uint32_t *oscclk; + uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ + bool fpgaio_switches; /* Does FPGAIO have SWITCH register? */ const char *armsse_type; }; =20 @@ -241,8 +243,11 @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *m= ms, void *opaque, const char *name, hwaddr size) { MPS2FPGAIO *fpgaio =3D opaque; + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); =20 object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAI= O); + qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); + qdev_prop_set_bit(DEVICE(fpgaio), "have-switches", mmc->fpgaio_switche= s); sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); } @@ -687,6 +692,8 @@ static void mps2tz_an505_class_init(ObjectClass *oc, vo= id *data) mmc->sysclk_frq =3D 20 * 1000 * 1000; /* 20MHz */ mmc->oscclk =3D an505_oscclk; mmc->len_oscclk =3D ARRAY_SIZE(an505_oscclk); + mmc->fpgaio_num_leds =3D 2; + mmc->fpgaio_switches =3D false; mmc->armsse_type =3D TYPE_IOTKIT; } =20 @@ -705,6 +712,8 @@ static void mps2tz_an521_class_init(ObjectClass *oc, vo= id *data) mmc->sysclk_frq =3D 20 * 1000 * 1000; /* 20MHz */ mmc->oscclk =3D an505_oscclk; /* AN521 is the same as AN505 here */ mmc->len_oscclk =3D ARRAY_SIZE(an505_oscclk); + mmc->fpgaio_num_leds =3D 2; + mmc->fpgaio_switches =3D false; mmc->armsse_type =3D TYPE_SSE200; } =20 --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612546674; cv=none; d=zohomail.com; s=zohoarc; b=XDQuVhhQd48ZpfKnbMHn5Eyr8/RgdOn6LmIpUfcy2AQ3WDUeyKfXQXDmLX0XyilO+G3r12OUz2hP/B8raFt5l+p4syaAgxttbjJ2DkQDkVTi+tgDKXb3Osr+fRu0ijrqCceZtEJvGNNR5KhcGoMVrVASljkyQqVwVxIIkSng6r0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612546674; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=va0A81ClB5F8EaAWROYYvDbctjGQ9fM8K2ZTOurTkG4=; b=iOxk1kl0ZWzM1naBcNYIjw2uDu4VdKH4qApSJfWmPLtOJA3ZnHXC0ogBIYdj1qIvxkjjx/iz2hsqhOMGEv4PMoxebNB2AxqvAVE1K24I1t/Q+fWLXkhujJEkGIbyQ7Gkncj+R3tTWreev6re2K2sUnbb1WaNF1l8tz7l5bIJmAY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612546674430723.9711504297661; Fri, 5 Feb 2021 09:37:54 -0800 (PST) Received: from localhost ([::1]:57120 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l853D-0001JQ-7M for importer@patchew.org; Fri, 05 Feb 2021 12:37:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46160) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l84Tb-0006lN-Nd for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:01 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:40921) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l84T8-00043L-NT for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:00:59 -0500 Received: by mail-wm1-x330.google.com with SMTP id c127so6433852wmf.5 for ; Fri, 05 Feb 2021 09:00:29 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=va0A81ClB5F8EaAWROYYvDbctjGQ9fM8K2ZTOurTkG4=; b=TTcdLbMweCBfuBARQyE3SgXm8z7P6eT37kQBiei0xUACTJXkaefHx3E5pE8m9lc71t 2T8BQNDcp2OpDguWB2iaeHOxH30YxoEXkk9idN6qxtysEJAJek3ybHj1edxmj6B43Aub wdmjEKQPc5n5ukAII2R7JmS/vTa7KxzZIW1osvEx3hhX5REPjdr6JBrMI+0XYTo5zYlc 8fvOtA8YjG8KSVjwok5BVqdDN0UwwciHxved2zwOnoTVkYytqNGp1Z55Y+q8u9nsEFGD jHMrWMi/yBdpV12koric9YsSL4UI6QmTSqai9hj4HDJaNJYQwq0wgxAHBjAFY4N90eoy N6wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=va0A81ClB5F8EaAWROYYvDbctjGQ9fM8K2ZTOurTkG4=; b=K9caKbvW1hpMwBU75sCk1CxvpqyHK+6qPFpdwrcr+fq34mnHJK29EuSx/2+7BvrgEv dMIyhGH5EB1GH5vMK9ugXVjAvKlpKdiCN7Q6VPzq8cF4UuhZKY34kyoY1KEnUDxQtlD2 Itgm0bYBzZsDzWFCuO6W2FNjpphO5w2WpV9EmfYJJArlGW+l+ofpzfuvV+hszC4TzR3j o+/8WrrtpCOsAU7VV1AQZsrdzwb1bqEN2m+9tRSfZiM335yH/WQnw8jEyPkyZYNosie4 L5F/hPFSURD7r3BB1QRvs2zSweUVnqf7sByJC7v8imRO1sJtJavbjToay0z5cTkouw1s bSHg== X-Gm-Message-State: AOAM533a79IYqrRrjw0oSB/CtqL9kiJVJpYQt9cUENZ8o+1RmT6keeqe lBalr2zT0nPza3pm6/qSeFC2vw7kKpveIw== X-Google-Smtp-Source: ABdhPJyeSSj3NxNlRdlExOhyNhCqA8XV5jAZediKVZaMg8c27NDiLGY5kyXAhMma353O9GknmyYP4A== X-Received: by 2002:a1c:a9d7:: with SMTP id s206mr4469059wme.42.1612544428262; Fri, 05 Feb 2021 09:00:28 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/24] hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type Date: Fri, 5 Feb 2021 17:00:03 +0000 Message-Id: <20210205170019.25319-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In the mps2-tz board code, we handle devices whose interrupt lines must be wired to all CPUs by creating IRQ splitter devices for the AN521, because it has 2 CPUs, but wiring the device IRQ directly to the SSE/IoTKit input for the AN505, which has only 1 CPU. We can avoid making an explicit check on the board type constant by instead creating and using the IRQ splitters for any board with more than 1 CPU. This avoids having to add extra cases to the conditionals every time we add new boards. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- This removes the only current user of mmc->fpga_type, but we're going to want it again later in the series. --- hw/arm/mps2-tz.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 94618ae54d2..4d8e42fa6b6 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -139,17 +139,14 @@ static void make_ram_alias(MemoryRegion *mr, const ch= ar *name, static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) { /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ - MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); + MachineClass *mc =3D MACHINE_GET_CLASS(mms); =20 assert(irqno < MPS2TZ_NUMIRQ); =20 - switch (mmc->fpga_type) { - case FPGA_AN505: - return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irq= no); - case FPGA_AN521: + if (mc->max_cpus > 1) { return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); - default: - g_assert_not_reached(); + } else { + return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irq= no); } } =20 @@ -437,10 +434,12 @@ static void mps2tz_common_init(MachineState *machine) sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); =20 /* - * The AN521 needs us to create splitters to feed the IRQ inputs - * for each CPU in the SSE-200 from each device in the board. + * If this board has more than one CPU, then we need to create splitte= rs + * to feed the IRQ inputs for each CPU in the SSE from each device in = the + * board. If there is only one CPU, we can just wire the device IRQ + * directly to the SSE's IRQ input. */ - if (mmc->fpga_type =3D=3D FPGA_AN521) { + if (mc->max_cpus > 1) { for (i =3D 0; i < MPS2TZ_NUMIRQ; i++) { char *name =3D g_strdup_printf("mps2-irq-splitter%d", i); SplitIRQ *splitter =3D &mms->cpu_irq_splitter[i]; --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612548423; cv=none; d=zohomail.com; s=zohoarc; b=c/D9GIDpHVF0MOhKvKBpFXmBw8iMFqvFMmr8wRr9QQkMx/LG/4Eyg6YacsftJ7mFzYm1OvvCsyKQixEuomRv2eqMKxSIpgt0qT6Ip8umlEwoC8v+HrH4Q1Q5eo2fPJkjx+atnxxXatsXaJ2QsiR3hYbSwgIO8bvAwkvEHgpXY5U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612548423; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WtrfuXabVXGeTIyTEVS5d0lsWCXmLnI61ZuEmNjOGlM=; b=EPhL7/Xun+QD0gEDY9skBOY8YXYTfOhjSRmpfU14YNlDN7b1+oI2HE0jARyXPFA9sH1ZR+QRX/dsEsGmfRCeRHknNBH/VmhgKRSS3dlICwuhyVU6VRQXM2Av6hB28uX0wNwVHco1JggUhFjVvS8knPGrCybtSTkAkVcjsB0qHC4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161254842320154.69106404409081; Fri, 5 Feb 2021 10:07:03 -0800 (PST) Received: from localhost ([::1]:36804 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l85VW-0004PJ-08 for importer@patchew.org; Fri, 05 Feb 2021 13:07:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46150) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l84Ta-0006kL-Uz for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:00:59 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:35371) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l84T8-00043W-N7 for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:00:56 -0500 Received: by mail-wr1-x42a.google.com with SMTP id l12so8485702wry.2 for ; Fri, 05 Feb 2021 09:00:29 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=WtrfuXabVXGeTIyTEVS5d0lsWCXmLnI61ZuEmNjOGlM=; b=DDtqw24MGTthrvTCDmCVUhvyNywQQ3ySB1PCZmmdqA69MvBPLN8u+GuH550lICpKTM /2Ur1N+ajMBksskb/5L85bcM0JId2ij6HExRnzFXFAyyQI2m4hCMGJRJYVuHNmeGNN3F zsX+EspckPaQQftqV2kqKbLrT2u4/JSCWPyWOCG2JpOAeev7VVgyIhQijjSeZ8LSEiGc kxeOdU7UilnarRePQ0M2zVlXuT94V52X55+xXMh/LN8HIy3xIt3qZQOKZt0hmJSY+B+O /xkdf0icRQFKPVF/Tcg1aOOP2u49grsQlKA5VCDHhwYy2NB+eIvTXmtc/urONqgoq7fR ZUvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WtrfuXabVXGeTIyTEVS5d0lsWCXmLnI61ZuEmNjOGlM=; b=dRJ+l6XpRgVZ4SGm3xqscbkeyawISNoJSWJ3FxgknsAFO/xjg5Ff6wufSXhHrrrcMS v3LIa7arEbiXbP7hcEPl02/UDS/fnvMd0V1C609WcTQtmVEWzE+Ruw2+3EdOQsrnNENF AVALFX74p6jdtytOa9FAdI5AZBMQ6T0I5bx2UKjFvqJT+4FEirmiFyEBMWdpyZp9yAFG dI+8spb2Zz583vd+qCOdyx7eqdrS7R2N0EoDhtjjBTcbmEZgq0vK3Kh/3j15LqjHPcmX KeICJHFC0kRcZCbb1dSHHEIj8cN0YDtwkz/oD+Lu3gJjFrCZbMm+56TQQXVMaecSzCGc Ekeg== X-Gm-Message-State: AOAM533KGPl1sg8eDBpx25G28gkyFmsIFPEGZFr9ilEk9E8NzR9ee5tC Zopxw+5Ta3kF12hqbpiBh4aUanivt2Dbkg== X-Google-Smtp-Source: ABdhPJybn6y2gQSULSVsv1OrsCCTXzBd/a+tOJs0XPHiYTRigflHHmdt+wnotStNMNz9YAIn6gMVcg== X-Received: by 2002:adf:f182:: with SMTP id h2mr5997610wro.355.1612544429075; Fri, 05 Feb 2021 09:00:29 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 09/24] hw/arm/mps2-tz: Make number of IRQs board-specific Date: Fri, 5 Feb 2021 17:00:04 +0000 Message-Id: <20210205170019.25319-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The AN524 has more interrupt lines than the AN505 and AN521; make numirq board-specific rather than a compile-time constant. Since the difference is small (92 on the current boards and 95 on the new one) we don't dynamically allocate the cpu_irq_splitter[] array but leave it as a fixed length array whose size is the maximum needed for any of the boards. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 4d8e42fa6b6..0f021676854 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -65,7 +65,7 @@ #include "hw/qdev-clock.h" #include "qom/object.h" =20 -#define MPS2TZ_NUMIRQ 92 +#define MPS2TZ_NUMIRQ_MAX 92 =20 typedef enum MPS2TZFPGAType { FPGA_AN505, @@ -81,6 +81,7 @@ struct MPS2TZMachineClass { const uint32_t *oscclk; uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ bool fpgaio_switches; /* Does FPGAIO have SWITCH register? */ + int numirq; /* Number of external interrupts */ const char *armsse_type; }; =20 @@ -105,7 +106,7 @@ struct MPS2TZMachineState { SplitIRQ sec_resp_splitter; qemu_or_irq uart_irq_orgate; DeviceState *lan9118; - SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ]; + SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; Clock *sysclk; Clock *s32kclk; }; @@ -140,8 +141,9 @@ static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms,= int irqno) { /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ MachineClass *mc =3D MACHINE_GET_CLASS(mms); + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); =20 - assert(irqno < MPS2TZ_NUMIRQ); + assert(irqno < mmc->numirq); =20 if (mc->max_cpus > 1) { return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); @@ -428,7 +430,7 @@ static void mps2tz_common_init(MachineState *machine) iotkitdev =3D DEVICE(&mms->iotkit); object_property_set_link(OBJECT(&mms->iotkit), "memory", OBJECT(system_memory), &error_abort); - qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); + qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); @@ -439,8 +441,9 @@ static void mps2tz_common_init(MachineState *machine) * board. If there is only one CPU, we can just wire the device IRQ * directly to the SSE's IRQ input. */ + assert(mmc->numirq <=3D MPS2TZ_NUMIRQ_MAX); if (mc->max_cpus > 1) { - for (i =3D 0; i < MPS2TZ_NUMIRQ; i++) { + for (i =3D 0; i < mmc->numirq; i++) { char *name =3D g_strdup_printf("mps2-irq-splitter%d", i); SplitIRQ *splitter =3D &mms->cpu_irq_splitter[i]; =20 @@ -693,6 +696,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, vo= id *data) mmc->len_oscclk =3D ARRAY_SIZE(an505_oscclk); mmc->fpgaio_num_leds =3D 2; mmc->fpgaio_switches =3D false; + mmc->numirq =3D 92; mmc->armsse_type =3D TYPE_IOTKIT; } =20 @@ -713,6 +717,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, vo= id *data) mmc->len_oscclk =3D ARRAY_SIZE(an505_oscclk); mmc->fpgaio_num_leds =3D 2; mmc->fpgaio_switches =3D false; + mmc->numirq =3D 92; mmc->armsse_type =3D TYPE_SSE200; } =20 --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612546087; cv=none; d=zohomail.com; s=zohoarc; b=YbEASckWyUJMBXxHaVHniXzlA5dBjj8wdLPqL/XVzMAfXpnjLKtW4gCxwwumtskphpAjriwYy/fZeOzY4snLCTK1Jyoq3LJTZ2WFf9DYX+PtAfCMuvxwrbU7MeDXX/2hsATZSZQ9FEvWFP6dBr8qFG8oPgOwGkMcOGJj/dL7CRw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612546087; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DWcDLedvIdrpO/Dyf18yelSJMFxD3oqKzuBHwfEwOy0=; b=PCrqgOEuDk9889d6bvfyc3HAyIFaz7izHe1ZlnYAAet5EcEmjZpZ3WazViMeHCXoT1KD7uP+5A2AjwR0S/OQJQT6ZzsKbU5iYOhqczGO14ZlnmiVvw8FCyXXCWfQvdr5XoMeTkXIl4a3tlr+oPMI54nekMUJU1ZDZ/sb0S716nY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612546087700471.664908452703; Fri, 5 Feb 2021 09:28:07 -0800 (PST) Received: from localhost ([::1]:38378 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l84tq-0001Cr-Mh for importer@patchew.org; Fri, 05 Feb 2021 12:28:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46274) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l84Th-0006p0-1V for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:05 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:33530) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l84TE-00043o-Iv for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:04 -0500 Received: by mail-wr1-x436.google.com with SMTP id 7so8520011wrz.0 for ; Fri, 05 Feb 2021 09:00:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DWcDLedvIdrpO/Dyf18yelSJMFxD3oqKzuBHwfEwOy0=; b=MwNWdA25f9XlFRHdpLJ9pQamQZfeQ/cSUkb7ANAmUhD5+fk+Swk58K7BKCJ7m4XqHY MqN62Yb+vwWH2GFu312RmGzs1gCwONPRnvo07adVfWO4TnS8pZlyl3VaTYVWCjjvBV1p 3vAg5iHPyThQ2RPBNn+3K5bJ2zmQkhL0qvEBencWoRFG0hVv/nQPHgK3+rQoDBHDzAU4 x4U6LmvLaZZWiazz61ZKQTaHtZ/nNREAoQQspuRXU7JbwMDs//hbQK7CZ550A0KLh/cv jyxQLnpa2IOnawM7dFeRyvboznI5kf/ke0MXSW1mAW0/KvNisolTCef0HF01smdvBWiF c6wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DWcDLedvIdrpO/Dyf18yelSJMFxD3oqKzuBHwfEwOy0=; b=YjxO7m6urU7p8dIjvvwbgjDt9VQ1xmmxaXaCP2VlIK7KkUPZKER8DOCOo4WOBVUHvL TI7vaPZfCwSgE4h0d95mviRQxhpe6AvpiatdMjGiuYb8Kym6yMg9kLTk3uzMvdGTgNz+ auIBwGtkEX9cDOSxtkOPeLJyucWYC/kykDxBUp4Rndar7WxOif5SUWKplmDJ/1hi+4UG otlK5gZGLmhT3/5zPjalmZQBcuJYgM7a1nxRPzrAwJCNk9WVSEL/H+F24TTfQS/z3iQq iOZW3wcsrVEx7OtE2vlioJvkbvnBDEH0Rh7wYVaJu2+E1uIgHBMW0JBa9wg53o4bXz8x 5ElA== X-Gm-Message-State: AOAM533F7QWS/1lJpHeF/+brKZNJyPaqlUl6vs9jyKUVBBwIoSSWw8zd 4sqf4FXLJRnUV4AZ6M9ukh6xcw== X-Google-Smtp-Source: ABdhPJzyweqLqcJW5hoZ7aD1Azm5eyKTDDCUYyispkuJIaKcLh86M7wy7itTr7oL8wgjk0/7YcsNkQ== X-Received: by 2002:adf:eed0:: with SMTP id a16mr5908493wrp.107.1612544430039; Fri, 05 Feb 2021 09:00:30 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 10/24] hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524 Date: Fri, 5 Feb 2021 17:00:05 +0000 Message-Id: <20210205170019.25319-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The AN524 version of the SCC interface has different behaviour for some of the CFG registers; implement it. Each board in this family can have minor differences in the meaning of the CFG registers, so rather than trying to specify all the possible semantics via individual device properties, we make the behaviour conditional on the part-number field of the SCC_ID register which the board code already passes us. For the AN524, the differences are: * CFG3 is reserved rather than being board switches * CFG5 is a new register ("ACLK Frequency in Hz") * CFG6 is a new register ("Clock divider for BRAM") We implement both of the new registers as reads-as-written. Signed-off-by: Peter Maydell --- include/hw/misc/mps2-scc.h | 3 ++ hw/misc/mps2-scc.c | 71 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 72 insertions(+), 2 deletions(-) diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h index 514da49f69e..49d070616aa 100644 --- a/include/hw/misc/mps2-scc.h +++ b/include/hw/misc/mps2-scc.h @@ -29,7 +29,10 @@ struct MPS2SCC { =20 uint32_t cfg0; uint32_t cfg1; + uint32_t cfg2; uint32_t cfg4; + uint32_t cfg5; + uint32_t cfg6; uint32_t cfgdata_rtn; uint32_t cfgdata_out; uint32_t cfgctrl; diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index 52a4e183b71..562ace06a58 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -31,8 +31,11 @@ =20 REG32(CFG0, 0) REG32(CFG1, 4) +REG32(CFG2, 8) REG32(CFG3, 0xc) REG32(CFG4, 0x10) +REG32(CFG5, 0x14) +REG32(CFG6, 0x18) REG32(CFGDATA_RTN, 0xa0) REG32(CFGDATA_OUT, 0xa4) REG32(CFGCTRL, 0xa8) @@ -49,6 +52,12 @@ REG32(DLL, 0x100) REG32(AID, 0xFF8) REG32(ID, 0xFFC) =20 +static int scc_partno(MPS2SCC *s) +{ + /* Return the partno field of the SCC_ID (0x524, 0x511, etc) */ + return extract32(s->id, 4, 8); +} + /* Handle a write via the SYS_CFG channel to the specified function/device. * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit). */ @@ -100,7 +109,18 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr off= set, unsigned size) case A_CFG1: r =3D s->cfg1; break; + case A_CFG2: + if (scc_partno(s) !=3D 0x524) { + /* CFG2 reserved on other boards */ + goto bad_offset; + } + r =3D s->cfg2; + break; case A_CFG3: + if (scc_partno(s) =3D=3D 0x524) { + /* CFG3 reserved on AN524 */ + goto bad_offset; + } /* These are user-settable DIP switches on the board. We don't * model that, so just return zeroes. */ @@ -109,6 +129,20 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr off= set, unsigned size) case A_CFG4: r =3D s->cfg4; break; + case A_CFG5: + if (scc_partno(s) !=3D 0x524) { + /* CFG5 reserved on other boards */ + goto bad_offset; + } + r =3D s->cfg5; + break; + case A_CFG6: + if (scc_partno(s) !=3D 0x524) { + /* CFG6 reserved on other boards */ + goto bad_offset; + } + r =3D s->cfg6; + break; case A_CFGDATA_RTN: r =3D s->cfgdata_rtn; break; @@ -131,6 +165,7 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offs= et, unsigned size) r =3D s->id; break; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "MPS2 SCC read: bad offset %x\n", (int) offset); r =3D 0; @@ -159,6 +194,30 @@ static void mps2_scc_write(void *opaque, hwaddr offset= , uint64_t value, led_set_state(s->led[i], extract32(value, i, 1)); } break; + case A_CFG2: + if (scc_partno(s) !=3D 0x524) { + /* CFG2 reserved on other boards */ + goto bad_offset; + } + /* AN524: QSPI Select signal */ + s->cfg2 =3D value; + break; + case A_CFG5: + if (scc_partno(s) !=3D 0x524) { + /* CFG5 reserved on other boards */ + goto bad_offset; + } + /* AN524: ACLK frequency in Hz */ + s->cfg5 =3D value; + break; + case A_CFG6: + if (scc_partno(s) !=3D 0x524) { + /* CFG6 reserved on other boards */ + goto bad_offset; + } + /* AN524: Clock divider for BRAM */ + s->cfg6 =3D value; + break; case A_CFGDATA_OUT: s->cfgdata_out =3D value; break; @@ -202,6 +261,7 @@ static void mps2_scc_write(void *opaque, hwaddr offset,= uint64_t value, s->dll =3D deposit32(s->dll, 24, 8, extract32(value, 24, 8)); break; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "MPS2 SCC write: bad offset 0x%x\n", (int) offset); break; @@ -222,6 +282,9 @@ static void mps2_scc_reset(DeviceState *dev) trace_mps2_scc_reset(); s->cfg0 =3D 0; s->cfg1 =3D 0; + s->cfg2 =3D 0; + s->cfg5 =3D 0; + s->cfg6 =3D 0; s->cfgdata_rtn =3D 0; s->cfgdata_out =3D 0; s->cfgctrl =3D 0x100000; @@ -260,11 +323,15 @@ static void mps2_scc_realize(DeviceState *dev, Error = **errp) =20 static const VMStateDescription mps2_scc_vmstate =3D { .name =3D "mps2-scc", - .version_id =3D 2, - .minimum_version_id =3D 2, + .version_id =3D 3, + .minimum_version_id =3D 3, .fields =3D (VMStateField[]) { VMSTATE_UINT32(cfg0, MPS2SCC), VMSTATE_UINT32(cfg1, MPS2SCC), + VMSTATE_UINT32(cfg2, MPS2SCC), + /* cfg3, cfg4 are read-only so need not be migrated */ + VMSTATE_UINT32(cfg5, MPS2SCC), + VMSTATE_UINT32(cfg6, MPS2SCC), VMSTATE_UINT32(cfgdata_rtn, MPS2SCC), VMSTATE_UINT32(cfgdata_out, MPS2SCC), VMSTATE_UINT32(cfgctrl, MPS2SCC), --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=z2Vyh+lBTQMBhsM4yGTc2A7bMPBGx/fyuKp+EIKhHX0=; b=eJHfa3q+jWJ5y5NK0pUi3jsKKRsfq4GBkqvwHJDraKeU1GgSeoKXlPdutpu0gPXnD9 HCQPe/nOiD8f2aG8Ean57IQEe1wpku3pdUOuY01e/CqUG3iq0XYivuU0135RKSn+cA0R qnKCAmQ+/ucwHIMsI4C7aj0DGAdteZaCiz07W76/a1604S71rXw1oLUNPP7NRATnoRMd /t0iRI5VT8F/0tBGqmTtTxi4hJArjuf+40ftr4TnE5u7Yv3rrU7/qJaZ8dF0L0x63p6K fysz/OE3qQXkJ8nVl1WzppYqbHA6m3bmyOZ/QqqzympfXhwro48KlDvkZYxb61+OsJ6s ruSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z2Vyh+lBTQMBhsM4yGTc2A7bMPBGx/fyuKp+EIKhHX0=; b=BkEU5a7HPczWwfyHN0pIM0TH7LXxKLr+ZK5evVs5ISGx8/Bx864+YuGPmLZOglI4/s sh9jvIonw/qO8Yl1OX9QbOp2EUgJKsaoA6CvPh2rclgVi+ZIwNKg4bve20CaYSG6byom mRzUCDnR7G9Qk+jBBH+F0BHfotbvW1D6Shf4AZSsE/le4l3emi/PjowQuyriwdQPWmRI L5KoTTx4blxsLTo69lLpS0qjZT6/zDYyhLoHlyR/vdY8EYyqjp5lWXWljTAwYIpj8OuM 2P3g35F+CybUNPCX5sSSloZbsBCFOQHbzgr96jpNFIOHcp7i6pqC7WTvMbvUBS9u/V+i amHw== X-Gm-Message-State: AOAM530MisL0ZKPRuMXLVZdnoFcSekd6zrQomqqhh1SZ5K/ZBpBs7D4n +cMvNdV7YCK1Yy9xzJ6zzpHJzA== X-Google-Smtp-Source: ABdhPJxg4955ettY9yKZGr1oxK+uy0EH8PSGQAd7fyM0Tw/FlcPyIPcQlZDPoX3lxfsY9Z7iSSPqKg== X-Received: by 2002:a05:6000:1045:: with SMTP id c5mr6274932wrx.250.1612544430834; Fri, 05 Feb 2021 09:00:30 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 11/24] hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI Date: Fri, 5 Feb 2021 17:00:06 +0000 Message-Id: <20210205170019.25319-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" On the MPS2 boards, the first 32 interrupt lines are entirely internal to the SSE; interrupt lines for devices outside the SSE start at 32. In the application notes that document each FPGA image, the interrupt wiring is documented from the point of view of the CPU, so '0' is the first of the SSE's interrupts and the devices in the FPGA image itself are '32' and up: so the UART 0 Receive interrupt is 32, the SPI #0 interrupt is 51, and so on. Within our implementation, because the external interrupts must be connected to the EXP_IRQ[0...n] lines of the SSE object, we made the get_sse_irq_in() function take an irqno whose values start at 0 for the first FPGA device interrupt. In this numbering scheme the UART 0 Receive interrupt is 0, the SPI #0 interrupt is 19, and so on. The result of these two different numbering schemes has been that half of the devices were wired up to the wrong IRQs: the UART IRQs are wired up correctly, but the DMA and SPI devices were passing start-at-32 values to get_sse_irq_in() and so being mis-connected. Fix the bug by making get_sse_irq_in() take values specified with the same scheme that the hardware manuals use, to avoid confusion. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 0f021676854..844092f4fd5 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -139,11 +139,21 @@ static void make_ram_alias(MemoryRegion *mr, const ch= ar *name, =20 static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) { - /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ + /* + * Return a qemu_irq which will signal IRQ n to all CPUs in the + * SSE. The irqno should be as the CPU sees it, so the first + * external-to-the-SSE interrupt is 32. + */ MachineClass *mc =3D MACHINE_GET_CLASS(mms); MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); =20 - assert(irqno < mmc->numirq); + assert(irqno >=3D 32 && irqno < (mmc->numirq + 32)); + + /* + * Convert from "CPU irq number" (as listed in the FPGA image + * documentation) to the SSE external-interrupt number. + */ + irqno -=3D 32; =20 if (mc->max_cpus > 1) { return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); @@ -197,9 +207,9 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms,= void *opaque, MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart =3D opaque; int i =3D uart - &mms->uart[0]; - int rxirqno =3D i * 2; - int txirqno =3D i * 2 + 1; - int combirqno =3D i + 10; + int rxirqno =3D i * 2 + 32; + int txirqno =3D i * 2 + 33; + int combirqno =3D i + 42; SysBusDevice *s; DeviceState *orgate_dev =3D DEVICE(&mms->uart_irq_orgate); =20 @@ -266,7 +276,7 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *m= ms, void *opaque, =20 s =3D SYS_BUS_DEVICE(mms->lan9118); sysbus_realize_and_unref(s, &error_fatal); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 48)); return sysbus_mmio_get_region(s, 0); } =20 @@ -507,7 +517,7 @@ static void mps2tz_common_init(MachineState *machine) &error_fatal); qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, - get_sse_irq_in(mms, 15)); + get_sse_irq_in(mms, 47)); =20 /* Most of the devices in the FPGA are behind Peripheral Protection * Controllers. The required order for initializing things is: --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612546320; cv=none; d=zohomail.com; s=zohoarc; b=Qzr0Rf1ApkR0L7uJqPx7J0/5KtVvw8BYU8Jueac2NmM9De8I835VrTljrPTYygmuAkbeambzW0EE0S4fpM3GbCc7SavS7XeHWxNoAAK04Bh99CgXH9kxFr0aOsBRm/IsQNEJPB2i4+9S7AjdV5V8rlXgNgZKcR4DsioWGJ6ePFY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612546320; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/pIYyrQAv+HRu+fw0UlomO31PGq1UabPbDOzFOgakDc=; b=dPRKxzRPelmuunsWM5JrJuxeoZyinraPmqPSnqEpJMnfK3LhiKgwOmYlyAbS0KACbxAHo9MK0W7UtpeudzunDLI/su+9Yck3M7HzBytN8jS2c07xS2P08m7/iOzxRIK4ofjdPhiqZL7qcuOls+CzE/Eh8Z2F2A0bp7hvqDTalEo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612546320208291.6065336404172; Fri, 5 Feb 2021 09:32:00 -0800 (PST) Received: from localhost ([::1]:47442 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l84xb-00058f-1t for importer@patchew.org; Fri, 05 Feb 2021 12:31:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46316) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l84Tj-0006qu-Ba for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:09 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:33521) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l84TE-00044D-It for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:06 -0500 Received: by mail-wr1-x42c.google.com with SMTP id 7so8520133wrz.0 for ; Fri, 05 Feb 2021 09:00:32 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/pIYyrQAv+HRu+fw0UlomO31PGq1UabPbDOzFOgakDc=; b=MK10JLpRkXTWAjzzzvBWqfaxpRjnCCYTehD/8tH3A07sMe1KidehC5uK8GEfH2Bk6a m39fBD7bnuEF7gwtSxnn1gPTiOdGIN1m6U5ILwUBnFq9ivq6EEF1j3T+RvZxR5LWiocz 9o7biyuN3Mh/ygRm/Yf23v46onUq/w+sTaUJSq6z7dKKQ3yEkvKmdAGoIBKqeEsPvPFi ipuUAbDvO2lgXESbZDjwdi6bDZ8yLTEWSTRaDFNYoqMiMSqrkZWzbnY/g4k4u6qXJqbT 12m+/GVHU+lQuZhYlOHoDuO1zNqs9ag+3ZduSCPgUCjIkkd8f6R5RUkbjGe1Hlh7NXaR EZ6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/pIYyrQAv+HRu+fw0UlomO31PGq1UabPbDOzFOgakDc=; b=dM1S8fcTm5iJqe0YskIp3cEob+yrcmC9izXDUpDT6pEyzYjf+gsgTsbw0qe29bh3Xk k3wjgyw1SUduCIL9Vx96k5c1147r6XrGEDylDG8/Ovf/hWjNLyuOu9N8N/+ScsYCK/B4 edJ8s1G8ptoEjNBlWi3MsYOJpYpkydc13ihpajlUpEOavEI+S8JZ1N+o9xNA8UTjB+aD vaygcaG17aGwqD2n2tZz9xeNdDnNebqYAezkAfTM3EQ7AyCriR/D4Ngaou5Q3Eu4LbcA KF00qKO/tNLaoBzC8zKDjJXcln/JaPVWv+LISfKjGyFBuzov1sMmHjyT6NF9bCS4asqQ IG8w== X-Gm-Message-State: AOAM532zum2/uQZ8fLTCE6YEOg+ZOg5RBMoP2q6qZL6FnbmQiMVey5eP FkN1n+ixG0nTv2U7KX/JChZ4JbRXhD8Ogg== X-Google-Smtp-Source: ABdhPJy/FQSK3OPmqkCt/YfR6nS4J5SzAAMK3+r6fKMO9BRm6XJQWU+6puErHdI+VqX6XurQEHOngA== X-Received: by 2002:adf:e5c6:: with SMTP id a6mr6115023wrn.400.1612544431612; Fri, 05 Feb 2021 09:00:31 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 12/24] hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts Date: Fri, 5 Feb 2021 17:00:07 +0000 Message-Id: <20210205170019.25319-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The mps2-tz code uses PPCPortInfo data structures to define what devices are present and how they are wired up. Currently we use these to specify device types and addresses, but hard-code the interrupt line wiring in each make_* helper function. This works for the two boards we have at the moment, but the AN524 has some devices with different interrupt assignments. This commit adds the framework to allow PPCPortInfo structures to specify interrupt numbers. We add an array of interrupt numbers to the PPCPortInfo struct, and pass it through to the make_* helpers. The following commit will change the make_* helpers over to using the framework. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 36 ++++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 844092f4fd5..0c75b2230ed 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -170,7 +170,8 @@ static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms,= int irqno) * needs to be plugged into the downstream end of the PPC port. */ typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size); + const char *name, hwaddr size, + const int *irqs); =20 typedef struct PPCPortInfo { const char *name; @@ -178,6 +179,7 @@ typedef struct PPCPortInfo { void *opaque; hwaddr addr; hwaddr size; + int irqs[3]; /* currently no device needs more IRQ lines than this */ } PPCPortInfo; =20 typedef struct PPCInfo { @@ -186,8 +188,9 @@ typedef struct PPCInfo { } PPCInfo; =20 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, - void *opaque, - const char *name, hwaddr size) + void *opaque, + const char *name, hwaddr size, + const int *irqs) { /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, * and return a pointer to its MemoryRegion. @@ -202,7 +205,8 @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState = *mms, } =20 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart =3D opaque; @@ -227,7 +231,8 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms,= void *opaque, } =20 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { MPS2SCC *scc =3D opaque; DeviceState *sccdev; @@ -249,7 +254,8 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, = void *opaque, } =20 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { MPS2FPGAIO *fpgaio =3D opaque; MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); @@ -262,7 +268,8 @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mm= s, void *opaque, } =20 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { SysBusDevice *s; NICInfo *nd =3D &nd_table[0]; @@ -281,7 +288,8 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *m= ms, void *opaque, } =20 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { TZMPC *mpc =3D opaque; int i =3D mpc - &mms->ssram_mpc[0]; @@ -318,7 +326,8 @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, = void *opaque, } =20 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { PL080State *dma =3D opaque; int i =3D dma - &mms->dma[0]; @@ -373,7 +382,8 @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, = void *opaque, } =20 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { /* * The AN505 has five PL022 SPI controllers. @@ -395,7 +405,8 @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms, = void *opaque, } =20 static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { ArmSbconI2CState *i2c =3D opaque; SysBusDevice *s; @@ -604,7 +615,8 @@ static void mps2tz_common_init(MachineState *machine) continue; } =20 - mr =3D pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->si= ze); + mr =3D pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->si= ze, + pinfo->irqs); portname =3D g_strdup_printf("port[%d]", port); object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), &error_fatal); --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612546677; cv=none; d=zohomail.com; s=zohoarc; b=dqn0Ky1wtOwN+0BVxPT/T9UAXhi3VyM1dy21LIRZKK3Qxaxadc1SuPS4D6NxZmxPTVXLcC/g7i9utOMI7QA135HRyk/MRlKihIa1cCHR/3aFuRkMbq3cmRd6tz5FmgzPaXBvhtBSLExDoJHBQHGq8+E1Zb48C/+E2wCBCefKf7A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612546677; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bR3iCRZSQtsiL/0YanNf64ks34qWLJ5kgt2Osppz8EY=; b=s1UguYTa03aWaHgLSvHXJdyKdN4ZML9BystZ+BkSLCscJL4XZPhXxmfAVwRbW2+iio Z2ffNjAz++Bk23K8g9sQzy5TZJV5GlsKoAI3kchYYSky0BU6+EFn4VDAGpAvwaIbYt+j x1WZVzeZtTU/R3vVYNLVGX7G2ZzjL4Q9Yfp98LqLInKTEc0d/3PHB+kGHq4TARYXIrU/ 89ChX6SrDVf7Yfmc89Z2hKkg0ZO2dBMn9oeAsYtnJGGfYgWlRzRBKkOZVV0fc9wQ9SdK BgTUCchVOBnpj0mzWjFrVb+NxE6KOUoXPiT7Luq/ubh16hJvNPXdgnfk154PzgmG1FuP nr8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bR3iCRZSQtsiL/0YanNf64ks34qWLJ5kgt2Osppz8EY=; b=Xg+dkJM3y6K/key7U+JCY4iRTcsK4M2/ua8O5ft1V9Ww2/uGvBlieNic2flfBJnVoZ nVNlknleX4QUbGpNmcuPzHJrzRVbC47wKNiQGnJT/FXsTjcR0PTSiMvxlA7BgceurCYH vvGPmq4YE1oOL9O8V4oQmQcoZR4fdugcu1JHeO3ARdp+AadDUWQkXpgVHW+6l8a1s2qv JzGsBZ7pEb6pFYh25eVufDpjiyAByxJWB+A6FG9H/DC1VcNAQbQez5dz8r9+Pzc02ewa 4PAKg3w0wqFYUgyxe4+0I6BzwaESlPkf6dJRxSnDZb8BbWtH5sLIIb5wuJyKYPuY8Ak0 OnGg== X-Gm-Message-State: AOAM530pkQH/EDEi7Famm+/w+EgOBEC0xKBx/njzUGyCUWBYY215+KFF sOLaT96xvhQPFF4fS1S6/mQiB1MoUpA6Vw== X-Google-Smtp-Source: ABdhPJwHtJlMh2wTaoDLRkGyYHEn4DLkeLbo3k7jLtMQaLg6OgLs6TkzUFlfkBxHo/Bw49Qwb6Zjpg== X-Received: by 2002:a5d:6a8f:: with SMTP id s15mr6098511wru.252.1612544432527; Fri, 05 Feb 2021 09:00:32 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 13/24] hw/arm/mps2-tz: Move device IRQ info to data structures Date: Fri, 5 Feb 2021 17:00:08 +0000 Message-Id: <20210205170019.25319-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Move the specification of the IRQ information for the uart, ethernet, dma and spi devices to the data structures. (The other devices handled by the PPCPortInfo structures don't have any interrupt lines we need to wire up.) Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 52 +++++++++++++++++++++++------------------------- 1 file changed, 25 insertions(+), 27 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 0c75b2230ed..07694413005 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -208,12 +208,10 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mm= s, void *opaque, const char *name, hwaddr size, const int *irqs) { + /* The irq[] array is tx, rx, combined, in that order */ MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart =3D opaque; int i =3D uart - &mms->uart[0]; - int rxirqno =3D i * 2 + 32; - int txirqno =3D i * 2 + 33; - int combirqno =3D i + 42; SysBusDevice *s; DeviceState *orgate_dev =3D DEVICE(&mms->uart_irq_orgate); =20 @@ -222,11 +220,11 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mm= s, void *opaque, qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->sysclk_frq); sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); s =3D SYS_BUS_DEVICE(uart); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); - sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); - sysbus_connect_irq(s, 4, get_sse_irq_in(mms, combirqno)); + sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2])); return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); } =20 @@ -283,7 +281,7 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *m= ms, void *opaque, =20 s =3D SYS_BUS_DEVICE(mms->lan9118); sysbus_realize_and_unref(s, &error_fatal); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 48)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); return sysbus_mmio_get_region(s, 0); } =20 @@ -329,6 +327,7 @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, = void *opaque, const char *name, hwaddr size, const int *irqs) { + /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */ PL080State *dma =3D opaque; int i =3D dma - &mms->dma[0]; SysBusDevice *s; @@ -373,9 +372,9 @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, = void *opaque, =20 s =3D SYS_BUS_DEVICE(dma); /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 58 + i * 3)); - sysbus_connect_irq(s, 1, get_sse_irq_in(mms, 56 + i * 3)); - sysbus_connect_irq(s, 2, get_sse_irq_in(mms, 57 + i * 3)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); + sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqs[2])); =20 g_free(mscname); return sysbus_mmio_get_region(s, 0); @@ -394,13 +393,12 @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms= , void *opaque, * lines are set via the "MISC" register in the MPS2 FPGAIO device. */ PL022State *spi =3D opaque; - int i =3D spi - &mms->spi[0]; SysBusDevice *s; =20 object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022); sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal); s =3D SYS_BUS_DEVICE(spi); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); return sysbus_mmio_get_region(s, 0); } =20 @@ -551,16 +549,16 @@ static void mps2tz_common_init(MachineState *machine) }, { .name =3D "apb_ppcexp1", .ports =3D { - { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000 }, - { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000 }, - { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000 }, - { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000 }, - { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000 }, - { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, - { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, - { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, - { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, - { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, + { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000, { 51= } }, + { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000, { 52= } }, + { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000, { 53= } }, + { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000, { 54= } }, + { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000, { 55= } }, + { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000, {= 32, 33, 42 } }, + { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000, {= 34, 35, 43 } }, + { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, {= 36, 37, 44 } }, + { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, {= 38, 39, 45 } }, + { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, {= 40, 41, 46 } }, { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 }, { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 }, { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 }, @@ -582,15 +580,15 @@ static void mps2tz_common_init(MachineState *machine) { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x10= 00 }, { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x10= 00 }, { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x10= 00 }, - { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 }, + { "eth", make_eth_dev, NULL, 0x42000000, 0x100000, { 48 } = }, }, }, { .name =3D "ahb_ppcexp1", .ports =3D { - { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000 }, - { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000 }, - { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000 }, - { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000 }, + { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000, { 58= , 56, 57 } }, + { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000, { 61= , 59, 60 } }, + { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000, { 64= , 62, 63 } }, + { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000, { 67= , 65, 66 } }, }, }, }; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Pkc1ViGT7MqLH1WJfEkEx25IDm75/A8GGd4uuqI01Qc=; b=o7QQMVG1wzL8HDe6bM09YFdykZH+bsdJmIUbou0erH8kkvtY4khkPS/+LvmAr0H1/7 GdmBK5IK54Ay7swHinKNAaJK39bCL2ohY9bwbca3vBHKJ255sjZJSDx3/tR07/ONacyl e2yIai33vxDMXJ6h6lfM9+/z09ys0pFJRHQxcluSFo8PzeZuShj8+FFhxj8MpKi8XTmw RBB3VdJ2uIM7eMF/2aDDdm5KbCyWrOAB2jRVfDB7a8BLxPeJhVSh2VNozL7Th8L3hEyL cP+t1QmFMZ933Ip8vrqnW9Fpv3lYpV8B0ZaIUTNc09hiTj4UTP24Fw7CsfbvIzBcgoQH WjAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Pkc1ViGT7MqLH1WJfEkEx25IDm75/A8GGd4uuqI01Qc=; b=QX7GgFnf+XIdpxz2x/OgsFk2XNhDeE7afotZkVKc8cTg5MI1plqvR/cHD6ntubN7jT SmfZryPCbN0xRpN9QGU795S9cy2gqifkRo87ODlToPWTY+GT4pVFTAW+ogk6+jwk3fAv LMyP3zfci5dT7dQELnfwR0l2dvIM9hePQ3K+iGmN18ICO7YfYnRtAfBtQUe6g7/qDvyr cIGye67AOvlwQH891+nKxuKm3zJg+Xd+AwLItaATfwRNGwIc1Re7IQJdrSWFmHtZw77m u2Od2YktC//UpkT5RYjFuvdRzPLWGqeEvFNsPgyFYwIdAwxIhn8PLIpw5T5jZjiHiEaB PsZg== X-Gm-Message-State: AOAM531H62fdFGeSh0pEaOH401QD9Igg3VACLQ4+tJYTt9U5JV08C+xN 4eox05Yo9eKBrO0+ryhBM2Dsyg== X-Google-Smtp-Source: ABdhPJxGACVZ+rk54LEjmLHN42RIa+ExSZ3Jw3pj/oy9NPJyimmdHmLrTEHve1ASyooH/uEHpY9OjQ== X-Received: by 2002:adf:e411:: with SMTP id g17mr6177695wrm.296.1612544433205; Fri, 05 Feb 2021 09:00:33 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 14/24] hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs Date: Fri, 5 Feb 2021 17:00:09 +0000 Message-Id: <20210205170019.25319-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We create an OR gate to wire together the overflow IRQs for all the UARTs on the board; this has to have twice the number of inputs as there are UARTs, since each UART feeds it a TX overflow and an RX overflow interrupt line. Replace the hardcoded '10' with a calculation based on the size of the uart[] array in the MPS2TZMachineState. (We rely on OR gate inputs that are never wired up or asserted being treated as always-zero.) Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 07694413005..87993516816 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -516,13 +516,18 @@ static void mps2tz_common_init(MachineState *machine) */ memory_region_add_subregion(system_memory, 0x80000000, machine->ram); =20 - /* The overflow IRQs for all UARTs are ORed together. + /* + * The overflow IRQs for all UARTs are ORed together. * Tx, Rx and "combined" IRQs are sent to the NVIC separately. - * Create the OR gate for this. + * Create the OR gate for this: it has one input for the TX overflow + * and one for the RX overflow for each UART we might have. + * (If the board has fewer than the maximum possible number of UARTs + * those inputs are never wired up and are treated as always-zero.) */ object_initialize_child(OBJECT(mms), "uart-irq-orgate", &mms->uart_irq_orgate, TYPE_OR_IRQ); - object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", 10, + object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", + 2 * ARRAY_SIZE(mms->uart), &error_fatal); qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612547578; cv=none; d=zohomail.com; s=zohoarc; b=bew8UJqp2b10TQRsg+meVMoHJ6/IesTQCSH4IWmRVygDtb1SNm/bFrh7mZIXqXDTa5NjsSn/wnwt6qrSEcZih2+gKplBuzndUGXtnTAGAVLpzOmX2uRGByg4hZ0YzRu9ANfmur3NX14iu8IN8rcx0TyGRVivMLY4B8zz+U+aotY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612547578; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VpEyWn0wqUXodQwTIXDgKgRTk0zKQyW4b0d+sVm3VCI=; b=jpvSYse+dSnLVeNPgPwrXks4Q2hRA7f3xV/9hmad6HHnkwhuzD/arakl1XgdOUuWa7ZVBDOhVwwJHyYd6Ad8eah0sI2wpMMZdvAjYPmpQ0ByKL9ZE2q7MddH56QwLjyj1dCOXv6+sKBdodG5oSn1Kce0g6kNJMxdHx94vgefQ1A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161254757872477.26720062781305; Fri, 5 Feb 2021 09:52:58 -0800 (PST) Received: from localhost ([::1]:59938 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l85Ht-0006su-BV for importer@patchew.org; Fri, 05 Feb 2021 12:52:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46590) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l84Tz-0007AH-Ry for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:23 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:46081) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l84TZ-00047s-Kn for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:23 -0500 Received: by mail-wr1-x42a.google.com with SMTP id q7so8392874wre.13 for ; Fri, 05 Feb 2021 09:00:50 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=VpEyWn0wqUXodQwTIXDgKgRTk0zKQyW4b0d+sVm3VCI=; b=BIWjCI6jjc9x3sWh6SqmHD9A8PEP7h0E2sRv2/o8FaPShO94KenudQn1oWedpfXuiM uS+57m9l++0oKZy2vc1bETlm2d5JJLSQKD5lbWzqVgKcWys/Y20kaayvFudBhYejesMi m1RBVzWcRINj6B0LDwpU0XNFMoVW/e0j4uUpb4VMb+jDwMEorzudgdZKA9uDjitWRTzm NaTLEEriRVT0Zep+K3aPv9hdiD+rV6U+XJVAExN0sdng3LyM/nIX/FLs7QTY70C4PmwS NIIWYfPGKHvKMvIxFD2conrnpQi+5pRwJgWXyu+J4cRxHG+i2zLjUpv9MG1yL1LHqKLv lHug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VpEyWn0wqUXodQwTIXDgKgRTk0zKQyW4b0d+sVm3VCI=; b=o3ymgmDUrWMG0Q1qQ+/LZbL6ZGqIXM4WBMIX9tVvpOxnoIRp6wIKj7EWUfX39Hw8g+ YnE7XCNQ1zqI81tLfxMWUzCSxeFfKNhA183jdFiOpMyjavI3rATjqa2nHTFCLkrj04N5 /9MNhm2x5Oo1mhF/7pNwTfVo2iBEgeXykNCRJo5O9vkB378AbIMY1hBLuVnIKn3EksL/ Rr07/yYPXjvnSlkYJfm81gDmHAnGV8sraUZ+TDsuhCNAE3Lj3QBliWo1xT8KUK6FQ20p gHJs5it4Q//hdqJ7hmrC9dxPuFiMusEaEQaGPJ20LT49EIRfsLRF0O3pGITDF0+Kr/2c Fw2Q== X-Gm-Message-State: AOAM533KvlddLMCuvDII7UM2vsBoiOupSdpXQAWHIRzMnWmNmGoVIFlu yKYvzuRXAjkjW5tbZAUk6j5u+w== X-Google-Smtp-Source: ABdhPJydTQuNg01KxrLG39GEjwVVBm5joB+EmSl+mlWuV/H0Amvtf8D8CZ8+E2vvxdmwLjjqZAHktg== X-Received: by 2002:a5d:6712:: with SMTP id o18mr5863434wru.375.1612544433926; Fri, 05 Feb 2021 09:00:33 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 15/24] hw/arm/mps2-tz: Allow boards to have different PPCInfo data Date: Fri, 5 Feb 2021 17:00:10 +0000 Message-Id: <20210205170019.25319-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The AN505 and AN521 have the same device layout, but the AN524 is somewhat different. Allow for more than one PPCInfo array, which can be selected based on the board type. Signed-off-by: Peter Maydell --- We can't just put the arrays at file-scope and set up pointers to them in the MPS2TZMachineClass struct, because the array members include entries like "&mms->uart[0]" which is only valid inside the mps2tz_common_init() function. --- hw/arm/mps2-tz.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 87993516816..721ac444920 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -423,6 +423,8 @@ static void mps2tz_common_init(MachineState *machine) MemoryRegion *system_memory =3D get_system_memory(); DeviceState *iotkitdev; DeviceState *dev_splitter; + const PPCInfo *ppcs; + int num_ppcs; int i; =20 if (strcmp(machine->cpu_type, mc->default_cpu_type) !=3D 0) { @@ -544,7 +546,7 @@ static void mps2tz_common_init(MachineState *machine) * + wire up the PPC's control lines to the IoTKit object */ =20 - const PPCInfo ppcs[] =3D { { + const PPCInfo an505_ppcs[] =3D { { .name =3D "apb_ppcexp0", .ports =3D { { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1= 000 }, @@ -598,7 +600,17 @@ static void mps2tz_common_init(MachineState *machine) }, }; =20 - for (i =3D 0; i < ARRAY_SIZE(ppcs); i++) { + switch (mmc->fpga_type) { + case FPGA_AN505: + case FPGA_AN521: + ppcs =3D an505_ppcs; + num_ppcs =3D ARRAY_SIZE(an505_ppcs); + break; + default: + g_assert_not_reached(); + } + + for (i =3D 0; i < num_ppcs; i++) { const PPCInfo *ppcinfo =3D &ppcs[i]; TZPPC *ppc =3D &mms->ppc[i]; DeviceState *ppcdev; --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612548600; cv=none; d=zohomail.com; s=zohoarc; b=iphyGQbqPYEcxJBIJJ9QKgbXngb3qE2izVP/u9587SvSMqE6EQR89rrtq0+CjAUZCdcG1wIQd99jWuCJbLf+5IxS5wGwG6RY2+o9Jp0exrubGcwgf0pscSpsA+6/y3TZBRStTyvT1T/tSIieeqpDGaNmRzC0SZt4+7a4rEs1XDU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612548600; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xP6Xb4op7arwmIlS9Ob8QiEZZSJzfIan0T/eBfhQnhQ=; b=lDNAsSY4+bW0gYKZslEtCec4iG74VIrduApacygJZc3OfVnidDaNFtAmPTDiI2Td9bHd5pNn7Eedn2lmZh8DQlaoTGXexWJlmLs50qWyQQ90pi42oOwjDPUPvGgDONRprW/gOiCJ1Cu8AOm4m4pMLnhhb8Bq21WhdX/bdTn0oYY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612548600889493.3243870656314; Fri, 5 Feb 2021 10:10:00 -0800 (PST) Received: from localhost ([::1]:43752 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l85YN-00016I-Jn for importer@patchew.org; Fri, 05 Feb 2021 13:09:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46656) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l84U2-0007FJ-Af for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:26 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:36785) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l84TZ-00048B-Km for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:26 -0500 Received: by mail-wm1-x333.google.com with SMTP id i9so6452248wmq.1 for ; Fri, 05 Feb 2021 09:00:51 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xP6Xb4op7arwmIlS9Ob8QiEZZSJzfIan0T/eBfhQnhQ=; b=LhrF5eceqZZUKhRR/oSEPR4mezCVB4OkoI2BT/rn26LdzJdflqcLVDll6OP2fnuW6D SdfQLeoBQqsyd2eyNShyrmFnvrnEO9lJg6Q6ibzqYL+uUmUIYG7YP1Ii0uvSdvLJKJmI o9BpHFloXmIGx9yIDui+Z/kVODffvJBA9I5gY8FwR3xLrd5UGK6mpS4YDzZrcoqWIjrB 0d061P8FI9EbduSVV8Atj/e0lE4g1IB8bgqWQjDSDrmTpNqZ2SmrJ7CEtUxK8J4LLebm SNGlstchEZUqpTWqOOREvYgI/cIQMu25k6pxzENzr2vk8YTNEPMMHPJbc3/yJFhhFAen EoCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xP6Xb4op7arwmIlS9Ob8QiEZZSJzfIan0T/eBfhQnhQ=; b=DDyWAUxlax0X6mdHRmh+CX4nOislZsKIzpS7QsJPpLVhsuRDJWilG7yMNM4UbAAiTU LGEp8W229OfMDKzqKLFtyeQsSgjrJmEiEOnPt7124LC2chIi4w3IMM9z0yGsflijR4CD 3sgRKdyLltW8KHoIsQFYm13h+Wn8B022yeRdyJ/es7R5FaC4uiVkw6Dq/T9N5Npg0t0S tqPlPNfAbtoWIFjpYrVP3geZaj5kzTKg5phzdGl0eZjJGsD4GZKLseGoI8rwH6qLbbik ExhwDwDBkFivLn5b7yn8lJ+Txo2rDC6uMToP35DnhnQ5pXE2QnAXhcR+qet03wSFXy27 Kv0w== X-Gm-Message-State: AOAM530QT9M9REXfHexQf5hfKL/DAL2i/d4fJ7ndO2s23GZH/MFPrDNt xpmoPsNOh3o6x8ql94/MXDU3PZHiV6JcQg== X-Google-Smtp-Source: ABdhPJwTHjtDxcDxcN7HYndZwjUp8VRSsflM17Rrxc7faFCBBxnE79BBEiPYmKopI2C49xcjTpoT3g== X-Received: by 2002:a1c:9c01:: with SMTP id f1mr4226913wme.159.1612544434740; Fri, 05 Feb 2021 09:00:34 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 16/24] hw/arm/mps2-tz: Make RAM arrangement board-specific Date: Fri, 5 Feb 2021 17:00:11 +0000 Message-Id: <20210205170019.25319-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The AN505 and AN521 have the same layout of RAM; the AN524 does not. Replace the current hard-coding of where the RAM is and which parts of it are behind which MPCs with a data-driven approach. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 175 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 138 insertions(+), 37 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 721ac444920..1e8dde768c2 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -66,12 +66,35 @@ #include "qom/object.h" =20 #define MPS2TZ_NUMIRQ_MAX 92 +#define MPS2TZ_RAM_MAX 4 =20 typedef enum MPS2TZFPGAType { FPGA_AN505, FPGA_AN521, } MPS2TZFPGAType; =20 +/* + * Define the layout of RAM in a board, including which parts are + * behind which MPCs. + * mrindex specifies the index into mms->ram[] to use for the backing RAM; + * -1 means "use the system RAM". + */ +typedef struct RAMInfo { + const char *name; + uint32_t base; + uint32_t size; + int mpc; /* MPC number, -1 for "not behind an MPC" */ + int mrindex; + int flags; +} RAMInfo; + +/* + * Flag values: + * IS_ALIAS: this RAM area is an alias to the upstream end of the + * MPC specified by its .mpc value + */ +#define IS_ALIAS 1 + struct MPS2TZMachineClass { MachineClass parent; MPS2TZFPGAType fpga_type; @@ -82,6 +105,7 @@ struct MPS2TZMachineClass { uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ bool fpgaio_switches; /* Does FPGAIO have SWITCH register? */ int numirq; /* Number of external interrupts */ + const RAMInfo *raminfo; const char *armsse_type; }; =20 @@ -89,12 +113,11 @@ struct MPS2TZMachineState { MachineState parent; =20 ARMSSE iotkit; - MemoryRegion ssram[3]; - MemoryRegion ssram1_m; + MemoryRegion ram[MPS2TZ_RAM_MAX]; MPS2SCC scc; MPS2FPGAIO fpgaio; TZPPC ppc[5]; - TZMPC ssram_mpc[3]; + TZMPC mpc[3]; PL022State spi[5]; ArmSbconI2CState i2c[4]; UnimplementedDeviceState i2s_audio; @@ -126,6 +149,77 @@ static const uint32_t an505_oscclk[] =3D { 25000000, }; =20 +static const RAMInfo an505_raminfo[] =3D { { + .name =3D "ssram-0", + .base =3D 0x00000000, + .size =3D 0x00400000, + .mpc =3D 0, + .mrindex =3D 0, + }, { + .name =3D "ssram-1", + .base =3D 0x28000000, + .size =3D 0x00200000, + .mpc =3D 1, + .mrindex =3D 1, + }, { + .name =3D "ssram-2", + .base =3D 0x28200000, + .size =3D 0x00200000, + .mpc =3D 2, + .mrindex =3D 2, + }, { + .name =3D "ssram-0-alias", + .base =3D 0x00400000, + .size =3D 0x00400000, + .mpc =3D 0, + .mrindex =3D 3, + .flags =3D IS_ALIAS, + }, { + /* Use the largest bit of contiguous RAM as our "system memory" */ + .name =3D "mps.ram", + .base =3D 0x80000000, + .size =3D 16 * MiB, + .mpc =3D -1, + .mrindex =3D -1, + }, { + .name =3D NULL, + }, +}; + +static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mp= c) +{ + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); + const RAMInfo *p; + + for (p =3D mmc->raminfo; p->name; p++) { + if (p->mpc =3D=3D mpc && !(p->flags & IS_ALIAS)) { + return p; + } + } + /* if raminfo array doesn't have an entry for each MPC this is a bug */ + g_assert_not_reached(); +} + +static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, + const RAMInfo *raminfo) +{ + /* Return an initialized MemoryRegion for the RAMInfo. */ + MemoryRegion *ram; + + if (raminfo->mrindex < 0) { + /* Means this RAMInfo is for QEMU's "system memory" */ + MachineState *machine =3D MACHINE(mms); + return machine->ram; + } + + assert(raminfo->mrindex < MPS2TZ_RAM_MAX); + ram =3D &mms->ram[raminfo->mrindex]; + + memory_region_init_ram(ram, NULL, raminfo->name, + raminfo->size, &error_fatal); + return ram; +} + /* Create an alias of an entire original MemoryRegion @orig * located at @base in the memory map. */ @@ -290,35 +384,23 @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms= , void *opaque, const int *irqs) { TZMPC *mpc =3D opaque; - int i =3D mpc - &mms->ssram_mpc[0]; - MemoryRegion *ssram =3D &mms->ssram[i]; + int i =3D mpc - &mms->mpc[0]; MemoryRegion *upstream; - char *mpcname =3D g_strdup_printf("%s-mpc", name); - static uint32_t ramsize[] =3D { 0x00400000, 0x00200000, 0x00200000 }; - static uint32_t rambase[] =3D { 0x00000000, 0x28000000, 0x28200000 }; + const RAMInfo *raminfo =3D find_raminfo_for_mpc(mms, i); + MemoryRegion *ram =3D mr_for_raminfo(mms, raminfo); =20 - memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal); - - object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC); - object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ssram), + object_initialize_child(OBJECT(mms), name, mpc, TYPE_TZ_MPC); + object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ram), &error_fatal); sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); /* Map the upstream end of the MPC into system memory */ upstream =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); - memory_region_add_subregion(get_system_memory(), rambase[i], upstream); + memory_region_add_subregion(get_system_memory(), raminfo->base, upstre= am); /* and connect its interrupt to the IoTKit */ qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, qdev_get_gpio_in_named(DEVICE(&mms->iotkit= ), "mpcexp_status", i)= ); =20 - /* The first SSRAM is a special case as it has an alias; accesses to - * the alias region at 0x00400000 must also go to the MPC upstream. - */ - if (i =3D=3D 0) { - make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x0040000= 0); - } - - g_free(mpcname); /* Return the register interface MR for our caller to map behind the P= PC */ return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); } @@ -415,6 +497,28 @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms,= void *opaque, return sysbus_mmio_get_region(s, 0); } =20 +static void create_non_mpc_ram(MPS2TZMachineState *mms) +{ + /* + * Handle the RAMs which are either not behind MPCs or which are + * aliases to another MPC. + */ + const RAMInfo *p; + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); + + for (p =3D mmc->raminfo; p->name; p++) { + if (p->flags & IS_ALIAS) { + SysBusDevice *mpc_sbd =3D SYS_BUS_DEVICE(&mms->mpc[p->mpc]); + MemoryRegion *upstream =3D sysbus_mmio_get_region(mpc_sbd, 1); + make_ram_alias(&mms->ram[p->mrindex], p->name, upstream, p->ba= se); + } else if (p->mpc =3D=3D -1) { + /* RAM not behind an MPC */ + MemoryRegion *mr =3D mr_for_raminfo(mms, p); + memory_region_add_subregion(get_system_memory(), p->base, mr); + } + } +} + static void mps2tz_common_init(MachineState *machine) { MPS2TZMachineState *mms =3D MPS2TZ_MACHINE(machine); @@ -499,24 +603,17 @@ static void mps2tz_common_init(MachineState *machine) qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, qdev_get_gpio_in(dev_splitter, 0)); =20 - /* The IoTKit sets up much of the memory layout, including + /* + * The IoTKit sets up much of the memory layout, including * the aliases between secure and non-secure regions in the - * address space. The FPGA itself contains: - * - * 0x00000000..0x003fffff SSRAM1 - * 0x00400000..0x007fffff alias of SSRAM1 - * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 - * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices - * 0x80000000..0x80ffffff 16MB PSRAM - */ - - /* The FPGA images have an odd combination of different RAMs, + * address space, and also most of the devices in the system. + * The FPGA itself contains various RAMs and some additional devices. + * The FPGA images have an odd combination of different RAMs, * because in hardware they are different implementations and * connected to different buses, giving varying performance/size * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily - * call the 16MB our "system memory", as it's the largest lump. + * call the largest lump our "system memory". */ - memory_region_add_subregion(system_memory, 0x80000000, machine->ram); =20 /* * The overflow IRQs for all UARTs are ORed together. @@ -549,9 +646,9 @@ static void mps2tz_common_init(MachineState *machine) const PPCInfo an505_ppcs[] =3D { { .name =3D "apb_ppcexp0", .ports =3D { - { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1= 000 }, - { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1= 000 }, - { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1= 000 }, + { "ssram-0-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x100= 0 }, + { "ssram-1-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x100= 0 }, + { "ssram-2-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x100= 0 }, }, }, { .name =3D "apb_ppcexp1", @@ -684,6 +781,8 @@ static void mps2tz_common_init(MachineState *machine) =20 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); =20 + create_non_mpc_ram(mms); + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400= 000); } =20 @@ -734,6 +833,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, vo= id *data) mmc->fpgaio_num_leds =3D 2; mmc->fpgaio_switches =3D false; mmc->numirq =3D 92; + mmc->raminfo =3D an505_raminfo; mmc->armsse_type =3D TYPE_IOTKIT; } =20 @@ -755,6 +855,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, vo= id *data) mmc->fpgaio_num_leds =3D 2; mmc->fpgaio_switches =3D false; mmc->numirq =3D 92; + mmc->raminfo =3D an505_raminfo; /* AN521 is the same as AN505 here */ mmc->armsse_type =3D TYPE_SSE200; } =20 --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612547402; cv=none; d=zohomail.com; s=zohoarc; b=CN41PgN/SPqNhoty3BHxa0mC6kK43+wkUkqO4i9/SuXkQqjsTqa623iofNdetqPpDCnmLwHPE27hE3AE6oBsV9+taGNRlDYT52ngvLyIfawWlf72OAd8vubZDoRwiNe5et5Mkc13wSVv1/dRSpB15KmWxK9j8pWaRM/me+NiT7o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612547402; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jMMA1bcWT9Cf0LVPoBI3bN3FRfuppErnoBYF5x3xFs8=; b=G4NFVM8Jrg3xLYKw46b1gqxkn/v3V0SyJ4ccMc51R3cbrlEvcyKSLxonELTpY4ibpPUeQcw0ggVDwTN/nRdlvhTZ1ztPLuT/KeI47PG4iHb7yN+Gg8lLokCNGZQcZE4tZYHkUXrWt90SH35NL5GTenwLiGRjqR5QS2jtfI+f780= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612547402710950.4648487309037; Fri, 5 Feb 2021 09:50:02 -0800 (PST) Received: from localhost ([::1]:51342 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l85F3-0003I5-6w for importer@patchew.org; Fri, 05 Feb 2021 12:50:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46588) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l84Tz-0007AB-Lc for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:23 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:43544) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l84TW-00048D-It for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:23 -0500 Received: by mail-wr1-x42f.google.com with SMTP id z6so8407581wrq.10 for ; Fri, 05 Feb 2021 09:00:51 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jMMA1bcWT9Cf0LVPoBI3bN3FRfuppErnoBYF5x3xFs8=; b=BSJcvNylWfV2OAx7I8JLY6GWD/PmR3i4voRQfrQKWyM/3t9MFuKLq4uzudSCTBIuET 4Wa3g+TTtnbNYd3qOcAeU/AtSAAzYUU84dzVZuA2rxwkSZ9MJN+F83Rv8UapQhQoB7dL gBMZCirI7DMXm2QLCqvect23rgLEHDCOhZTiwsUyfmM6quzUUZYuyk1qF5mOwLB04oip JID+RVC99OqtNXwHF/Hu8Szl/IjtRp/FJgo4qJtO21BIiuYwOwJVsICU/Ht2LmPenfMG csCpH2eaaLcriYi3J1DS/vZkrlpg7D+4Y51B9v4M69kiuv5KxqQRdtyGA8XA2vTD/GZ1 2TEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jMMA1bcWT9Cf0LVPoBI3bN3FRfuppErnoBYF5x3xFs8=; b=DPWv5Af/pTPec8q6xzF+C27ccSiqidraJQjR/F6crC2RkgPlstN46/KPdwfVo1Ml9B 1o3+fd6ilpF33hKbDIXmOMKOI6S4YLp2IzVnzMYfBaxqquKM6iks4dAFogU9+yEIm7j3 g6jffh8Q0TmIrAmhbMlas4xDfz6MMzIcSeJ/INoCjdxqdO2E4eCZmVNOHMUv1y2/8f1K OXYINzJk9eogC3nuWQooRNeBjVuO6wcmMI6xTUb2YyLSRi1lCx6iaI6oe3uyLyFddAUO hvmAl4iP4pW/QPkQ2CBvIQSy4REgqGzX6JoCttOnoYwLIO1uQBU+LKvSIj1dA168iaPY IdYg== X-Gm-Message-State: AOAM531v+uBJhOq6hT3dNGw73Yfxf4Y/vq4B/WalFcnimNIRvQwshlsW 0fKrONGCgUETDgyRdeJbq/weGRfVBnYoGQ== X-Google-Smtp-Source: ABdhPJwDNEip7+TYbg6JbDRaHAz/Ef5YXQtGRmHoXJIoigMPugWKOReugGuqQcUEkLZCE0D2n90ZPA== X-Received: by 2002:a5d:6311:: with SMTP id i17mr5988743wru.195.1612544435474; Fri, 05 Feb 2021 09:00:35 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 17/24] hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data Date: Fri, 5 Feb 2021 17:00:12 +0000 Message-Id: <20210205170019.25319-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Instead of hardcoding the MachineClass default_ram_size and default_ram_id fields, set them on class creation by finding the entry in the RAMInfo array which is marked as being the QEMU system RAM. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 1e8dde768c2..b46b32746e0 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -811,8 +811,26 @@ static void mps2tz_class_init(ObjectClass *oc, void *d= ata) =20 mc->init =3D mps2tz_common_init; iic->check =3D mps2_tz_idau_check; - mc->default_ram_size =3D 16 * MiB; - mc->default_ram_id =3D "mps.ram"; +} + +static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc) +{ + /* + * Set mc->default_ram_size and default_ram_id from the + * information in mmc->raminfo. + */ + MachineClass *mc =3D MACHINE_CLASS(mmc); + const RAMInfo *p; + + for (p =3D mmc->raminfo; p->name; p++) { + if (p->mrindex < 0) { + /* Found the entry for "system memory" */ + mc->default_ram_size =3D p->size; + mc->default_ram_id =3D p->name; + return; + } + } + g_assert_not_reached(); } =20 static void mps2tz_an505_class_init(ObjectClass *oc, void *data) @@ -835,6 +853,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, vo= id *data) mmc->numirq =3D 92; mmc->raminfo =3D an505_raminfo; mmc->armsse_type =3D TYPE_IOTKIT; + mps2tz_set_default_ram_info(mmc); } =20 static void mps2tz_an521_class_init(ObjectClass *oc, void *data) @@ -857,6 +876,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, vo= id *data) mmc->numirq =3D 92; mmc->raminfo =3D an505_raminfo; /* AN521 is the same as AN505 here */ mmc->armsse_type =3D TYPE_SSE200; + mps2tz_set_default_ram_info(mmc); } =20 static const TypeInfo mps2tz_info =3D { --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612548298; cv=none; d=zohomail.com; s=zohoarc; b=cprnW/YbU5014tzbYPLsPInY8cLwgfzzlV/MW56iCQSPYcpzjrDFnfp+lhZxVuBesQPavzKl9k7H6VxnT6PrId6/ghIaNMY1n4YLkSw/DWIKwzUplpfoKW/Lba5CJjp9pJirlJg7qNcgRty6Vt6xYt/DzRyqIV1rNbWkqPphw7A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612548298; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=M0p8lPGYTACYbzRLtR7fBRTYLnsV3hqqOQcj+ku4dlo=; b=G8EK5U+jP4BtB0VwQQLOQIJIy/MW0GIUKm4MJiciXiGYGVPjtBfMgFSFiKEZclh/+ykJc7I9jX7zPH/t+upeEk9IKMo0jSfYse8OmQH8Vux+G7LrXRyBYWgcu0p4ZMZdHTXOyB7fXedbTlDvlNwnhVqE9RZn9p5Jk9iCftvEC34= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612548298441605.935563415726; Fri, 5 Feb 2021 10:04:58 -0800 (PST) Received: from localhost ([::1]:59974 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l85TT-00025A-Vk for importer@patchew.org; Fri, 05 Feb 2021 13:04:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46596) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l84U0-0007Ae-2O for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:24 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:46089) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l84TZ-00048Q-LA for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:23 -0500 Received: by mail-wr1-x432.google.com with SMTP id q7so8393054wre.13 for ; Fri, 05 Feb 2021 09:00:52 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=M0p8lPGYTACYbzRLtR7fBRTYLnsV3hqqOQcj+ku4dlo=; b=pY+t6REUnChKux8CNuu2SL+CRK0Itagle1XrT50PNB3claeRbxT/M/N0hz29P7yYRo 6tVFbzK1ACPm3Dn1bVIrHn5TumAuXXjS/hQwBDhhuE8xvW31PxriJ49Mph48IE6JYOLg ju6rb7l9QhV4LIF9xKnFvGT0gceyOgNZvz4Fu59ZmgUjIE7O5OmvDKY6siKHAKbvDmyS fPDLO2ycNPVyUmUl46EaJjeG5YK0iMKRl08afnOiZhQ/CdsxaX7xNZjRdGue0DgBEmrT pGRorGH3TUEyUzSJp07nL/qjepY4UD4A3HqcEP6zdRGvqOJ58zQAef87/6ych5e5tPIt Vhhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M0p8lPGYTACYbzRLtR7fBRTYLnsV3hqqOQcj+ku4dlo=; b=R4M2UU8WuBnky3IIBApwNXWx9NCGuutRXp7BCLyKBY1EVB/nRLlShbOfOXQFzM4Buj hR4jtzqm+1x0aVcm+ejZe2CzrpaxMPudoM/cvoWGY9mQqrf7PAV+DEv2FYwCEE5RtyGc xKeg7M//N3TTBdbSzrimOZDqeJRmcWxW6tCYqYJbUT3jKbBh385LCi93S9jIBbG/H1g5 mwMeTdPsIjUQ8k8kI4cfpTekVJuVQ595B5zh2pVXiwrE+hJAJZiQpgXUzLsVyofA7Yd5 enl8ismGD3GNOiN9iOvYxHNjjUeraUW3F6sRh9XHAbMUYac2+p+ApJUAxQ91zy912rEm qhAg== X-Gm-Message-State: AOAM5326I7jiiMY7a0eK4EaNT8FqbY+8naTZgLxhcNUj0KCRGx6y3cD5 aGQrbq5GEZOE9OVeLbSWhbww+A== X-Google-Smtp-Source: ABdhPJyH4cp5e66yqoKU8hyQ78w00L4f68V6CL98B690UarIZm9R8DTyq9PYxoYhPwhmJdizjfCE1A== X-Received: by 2002:a5d:50d2:: with SMTP id f18mr6335347wrt.338.1612544436251; Fri, 05 Feb 2021 09:00:36 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 18/24] hw/arm/mps2-tz: Support ROMs as well as RAMs Date: Fri, 5 Feb 2021 17:00:13 +0000 Message-Id: <20210205170019.25319-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The AN505 and AN521 don't have any read-only memory, but the AN524 does; add a flag to ROMInfo to mark a region as ROM. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index b46b32746e0..ce5e804c734 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -92,8 +92,10 @@ typedef struct RAMInfo { * Flag values: * IS_ALIAS: this RAM area is an alias to the upstream end of the * MPC specified by its .mpc value + * IS_ROM: this RAM area is read-only */ #define IS_ALIAS 1 +#define IS_ROM 2 =20 struct MPS2TZMachineClass { MachineClass parent; @@ -209,6 +211,7 @@ static MemoryRegion *mr_for_raminfo(MPS2TZMachineState = *mms, if (raminfo->mrindex < 0) { /* Means this RAMInfo is for QEMU's "system memory" */ MachineState *machine =3D MACHINE(mms); + assert(!(raminfo->flags & IS_ROM)); return machine->ram; } =20 @@ -217,6 +220,9 @@ static MemoryRegion *mr_for_raminfo(MPS2TZMachineState = *mms, =20 memory_region_init_ram(ram, NULL, raminfo->name, raminfo->size, &error_fatal); + if (raminfo->flags & IS_ROM) { + memory_region_set_readonly(ram, true); + } return ram; } =20 --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612547496; cv=none; d=zohomail.com; s=zohoarc; b=msS2Uozu9XfjqJ0RscNGaQ8bKsZvHnXADHNZEsCv5azoQJsNm0kfMm9eqkn3Ie9vPGt7yI7QnTKTR9qZrJKbhBmTgmdqsq1RGeKFEhZSB4V5D7KXD5B13A/cfPyeG9DdM9ZRzKFlircz2el6eGa12dUxGrV56I5Dxl6WlwYDwQI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612547496; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jBPg420nC8pQh3qALQMd4OOROzhv7e66E6mvu1AgKfg=; b=Rbp1JKHAcXHlZ/Ta0rL68ZapVb9ubAc5xHuRIQcdMQ8SMXYkEEE++UVkZKzQVrpbb9bvPVXYeUY2uP+qmznIMBKet2eflcIYcWrq8xYUR0vpvMk+OA9PDbFsAAuZLBZWYeAaZfMkE1enq/uIxm+tWtdbda5NCwtvuugvQZJaI+I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612547496798866.3660319960147; Fri, 5 Feb 2021 09:51:36 -0800 (PST) Received: from localhost ([::1]:56094 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l85GZ-0005Fy-E6 for importer@patchew.org; Fri, 05 Feb 2021 12:51:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46370) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l84Tl-0006t0-K6 for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:09 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:45620) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l84TO-00045G-Io for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:09 -0500 Received: by mail-wr1-x42e.google.com with SMTP id m13so8408654wro.12 for ; Fri, 05 Feb 2021 09:00:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jBPg420nC8pQh3qALQMd4OOROzhv7e66E6mvu1AgKfg=; b=aMO9rVa9eBZJ7k5HnfJuACbVQZpsAuYiABnsXFmGortX5AI9bs82hCReJ0hhSOAdRx srhrMiEcByg14dQdRlXIzSx1j40I0sYlNuhski9P+/3rfOraUEY3R7UWhyRxhhYs1usT Fm3j1cDH9WueZwN0FSNHp6mfQNTV1SWogaWyg0QQaIBInMo0osQrI3SPqoVcKhsYYUd3 JFiwVicvLvDSdzVczd/zWEfXCKJ547wUDgcFFL9yzNXU53IFh7FiX1a/vxfnaY1EaVfm ZWMl7tQK/b/6cmPBqJw0URU+d7FfFNQ0Ujy4llfPx5OLRH/L8QDHiWzh8hd3C9DZqctp +XGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jBPg420nC8pQh3qALQMd4OOROzhv7e66E6mvu1AgKfg=; b=Fo7ZnpyGmJe6nSrYs5FfYNgTgTkWevfTBpm6OvE3h3nrzs0zssjxfm0YN0yaXW9ITY bHk4m3VIjylUpEYxLNB7VeST1jBrKN4U5n7zQkTla3SU8d0mxHab/IBxZ0mFr/q0xPvO GijEI5Re47QO+PwBhudJxmbmKfln+GhEkVCT56lF0BIJMedmWFYCPyfX6Cbt1z340yuq KjZNMk3was8pZe60FRfT1qsTU+Nm1qqfWGpOJxeQjqI2Y2yL7bJ9CFYK+3sAM93UM100 vQPKkyMwIacocy/f1MGHYy8XzWMmDBBwv3LErLml7NzmUdMuCSDulQEGYcZ+hZ6FjGDl ms9w== X-Gm-Message-State: AOAM531JLioNWUzGgMKuElbEE0jgXpVTpG6LCxl2jGXQrbJLEONESnQo FxQL8I8bKGkod2BlOebvc+Usu419kkp+Uw== X-Google-Smtp-Source: ABdhPJy4IPIoOQkF8FHSSyctkzQH0xJ3BZf5j/SDCXLJPwSnfwg3OTv9M1bPEQn+JkpF0LiPLafj0Q== X-Received: by 2002:a5d:6842:: with SMTP id o2mr6221786wrw.310.1612544437055; Fri, 05 Feb 2021 09:00:37 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 19/24] hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo Date: Fri, 5 Feb 2021 17:00:14 +0000 Message-Id: <20210205170019.25319-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The armv7m_load_kernel() function takes a mem_size argument which it expects to be the size of the memory region at guest address 0. (It uses this argument only as a limit on how large a raw image file it can load at address zero). Instead of hardcoding this value, find the RAMInfo corresponding to the 0 address and extract its size. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index ce5e804c734..17173057af2 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -525,6 +525,20 @@ static void create_non_mpc_ram(MPS2TZMachineState *mms) } } =20 +static uint32_t boot_ram_size(MPS2TZMachineState *mms) +{ + /* Return the size of the RAM block at guest address zero */ + const RAMInfo *p; + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); + + for (p =3D mmc->raminfo; p->name; p++) { + if (p->base =3D=3D 0) { + return p->size; + } + } + g_assert_not_reached(); +} + static void mps2tz_common_init(MachineState *machine) { MPS2TZMachineState *mms =3D MPS2TZ_MACHINE(machine); @@ -789,7 +803,8 @@ static void mps2tz_common_init(MachineState *machine) =20 create_non_mpc_ram(mms); =20 - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400= 000); + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + boot_ram_size(mms)); } =20 static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612547924; cv=none; d=zohomail.com; s=zohoarc; b=AyTJO9pgON3vvja/bzmHpbEjF8Wkv2AmEEi6oRBPj2J/RBpdK5SwyCDIDsFwcFyfeHyzqa/mMJC1HFyWPRKsuLc9GbVRPcvvCQbyMvcxeqGxnNuVrT4u06fKiLPBCZQs+osKDTpARTDfIidlWB7XFHb37pQQeChaVErRniGxhME= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612547924; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DE4kV9oRwWVFbHVvXhpOiSYu9RVGMP8mh3PWmkMh9ek=; b=AgPYjXYKwgA9HvCq1TIZyfZarg6EbfMMykgI+bnfHi1JF8LvzhPUlSF8SIUhKYtOkKotSb4/xVmAY76tay4v6cNwaeCJO4X9+5YWXzGLUECRXF/C6HkBALYagcGl1tZyMQ62Ta0IfAbU/uBJ7N0XsG8tYhxpLabM+VyMV99XhTU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612547924416225.29230080802688; Fri, 5 Feb 2021 09:58:44 -0800 (PST) Received: from localhost ([::1]:47572 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l85NT-00053t-7X for importer@patchew.org; Fri, 05 Feb 2021 12:58:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46380) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l84Tm-0006uQ-HW for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:10 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:54645) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l84TO-00045e-J3 for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:10 -0500 Received: by mail-wm1-x336.google.com with SMTP id w4so6564316wmi.4 for ; Fri, 05 Feb 2021 09:00:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DE4kV9oRwWVFbHVvXhpOiSYu9RVGMP8mh3PWmkMh9ek=; b=JpPNUj0TIQRuZpObBhbPzMqADwGBame4F1BNqpps+iaa5aq4iH+rwfzij9YEbkFGs7 zKuF5Mo2D7WIOBRLPwUD16LPEf+DhLUudRw8MEf5jkCjpPyASrQBVJjyJ1hZo6QZ7MTj 1/jcM91euC6zNZz/JzvepW9+z5q1TCTW6mw8WcD96OWEaD6UzWlliBOIVJViBEjwNuFt tFLT/B2yPMT+AW+dgWdhnEb4Ce5ujrwRzPdzI1wYJlTOB7dVFS6Dxy+PrW9NUVkSnzdQ zALrHuegKTCtrGUA66Qmgcjh2EvDrhXuxgUG45QqVjXIEhXhsxzsHVwW/LIvBOvMuwAv V0tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DE4kV9oRwWVFbHVvXhpOiSYu9RVGMP8mh3PWmkMh9ek=; b=GxkW40ctAsDPN2Os3XiwkH6sealAlIQ26r/lLHgIMIPdNXtSr7tBwqJcgIaqiZs+xy TqLCCmNu39OL0Gsq8TPLpOVT3SPHgfk6BWq0nIQctRTsCnxXA8lRD1GZHOad/o9BDDfH JCk90NR0obdFdeNM8+VdE6zITAFDm8StboWRUnLtuGXLzYYLN8WG4biK7zBXqADTl0sd qPAQJhzZ8nXZtWgFijzwEfE9/RHieTCPfZKYUxOKgYMn0XZgYGoX7dQGFhMZil2dxM9K Ixm3qBf6KbksOJWSsiQJkKUgrP5SzUTjrsVxtwPjGOFPYL3sIjKWKEkAd7IsNHtwTmSV TZ2A== X-Gm-Message-State: AOAM5323ci9+cSmNeCz5cL3EGMz6/kK850qGc2x6C1tyYjZBIDUBAKfl yt/0uwxlooGbG1nDJRGCi6KKaQ== X-Google-Smtp-Source: ABdhPJyEAJpjpMefnekWTU+ufp3lSai4Ni1p4awo+plYuzKsTKsl2ob04VuE5uHeRUWmaQKvad0REA== X-Received: by 2002:a1c:2ed4:: with SMTP id u203mr4419279wmu.45.1612544437894; Fri, 05 Feb 2021 09:00:37 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 20/24] hw/arm/mps2-tz: Add new mps3-an524 board Date: Fri, 5 Feb 2021 17:00:15 +0000 Message-Id: <20210205170019.25319-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Add support for the mps3-an524 board; this is an SSE-200 based FPGA image, like the existing mps2-an521. It has a usefully larger amount of RAM, and a PL031 RTC, as well as some more minor differences. In real hardware this image runs on a newer generation of the FPGA board, the MPS3 rather than the older MPS2. Architecturally the two boards are similar, so we implement the MPS3 boards in the mps2-tz.c file as variations of the existing MPS2 boards. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 136 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 132 insertions(+), 4 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 17173057af2..aa57c4b2596 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -27,11 +27,13 @@ * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html * Application Note AN521: * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html + * Application Note AN524: + * https://developer.arm.com/documentation/dai0524/latest/ * * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Gu= ide * (ARM ECM0601256) for the details of some of the device layout: * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm0601= 256/index.html - * Similarly, the AN521 uses the SSE-200, and the SSE-200 TRM defines + * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM def= ines * most of the device layout: * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/cor= elink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_= 00_en.pdf * @@ -65,12 +67,13 @@ #include "hw/qdev-clock.h" #include "qom/object.h" =20 -#define MPS2TZ_NUMIRQ_MAX 92 +#define MPS2TZ_NUMIRQ_MAX 95 #define MPS2TZ_RAM_MAX 4 =20 typedef enum MPS2TZFPGAType { FPGA_AN505, FPGA_AN521, + FPGA_AN524, } MPS2TZFPGAType; =20 /* @@ -121,13 +124,15 @@ struct MPS2TZMachineState { TZPPC ppc[5]; TZMPC mpc[3]; PL022State spi[5]; - ArmSbconI2CState i2c[4]; + ArmSbconI2CState i2c[5]; UnimplementedDeviceState i2s_audio; UnimplementedDeviceState gpio[4]; UnimplementedDeviceState gfx; + UnimplementedDeviceState cldc; + UnimplementedDeviceState rtc; PL080State dma[4]; TZMSC msc[4]; - CMSDKAPBUART uart[5]; + CMSDKAPBUART uart[6]; SplitIRQ sec_resp_splitter; qemu_or_irq uart_irq_orgate; DeviceState *lan9118; @@ -139,6 +144,7 @@ struct MPS2TZMachineState { #define TYPE_MPS2TZ_MACHINE "mps2tz" #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") +#define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524") =20 OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) =20 @@ -151,6 +157,15 @@ static const uint32_t an505_oscclk[] =3D { 25000000, }; =20 +static const uint32_t an524_oscclk[] =3D { + 24000000, + 32000000, + 50000000, + 50000000, + 24576000, + 23750000, +}; + static const RAMInfo an505_raminfo[] =3D { { .name =3D "ssram-0", .base =3D 0x00000000, @@ -188,6 +203,37 @@ static const RAMInfo an505_raminfo[] =3D { { }, }; =20 +static const RAMInfo an524_raminfo[] =3D { { + .name =3D "bram", + .base =3D 0x00000000, + .size =3D 512 * KiB, + .mpc =3D 0, + .mrindex =3D 0, + }, { + .name =3D "sram", + .base =3D 0x20000000, + .size =3D 32 * 4 * KiB, + .mpc =3D 1, + .mrindex =3D 1, + }, { + /* We don't model QSPI flash yet; for now expose it as simple ROM = */ + .name =3D "QSPI", + .base =3D 0x28000000, + .size =3D 8 * MiB, + .mpc =3D 1, + .mrindex =3D 2, + .flags =3D IS_ROM, + }, { + .name =3D "DDR", + .base =3D 0x60000000, + .size =3D 2 * GiB, + .mpc =3D 2, + .mrindex =3D -1, + }, { + .name =3D NULL, + }, +}; + static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mp= c) { MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); @@ -717,12 +763,66 @@ static void mps2tz_common_init(MachineState *machine) }, }; =20 + const PPCInfo an524_ppcs[] =3D { { + .name =3D "apb_ppcexp0", + .ports =3D { + { "bram-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, + { "qspi-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, + { "ddr-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, + }, + }, { + .name =3D "apb_ppcexp1", + .ports =3D { + { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000 }, + { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000 }, + { "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52= } }, + { "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53= } }, + { "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54= } }, + { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000 }, + { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000 }, + { /* port 7 reserved */ }, + { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000 }, + }, + }, { + .name =3D "apb_ppcexp2", + .ports =3D { + { "scc", make_scc, &mms->scc, 0x41300000, 0x1000 }, + { "i2s-audio", make_unimp_dev, &mms->i2s_audio, + 0x41301000, 0x1000 }, + { "fpgaio", make_fpgaio, &mms->fpgaio, 0x41302000, 0x1000 = }, + { "uart0", make_uart, &mms->uart[0], 0x41303000, 0x1000, {= 32, 33, 42 } }, + { "uart1", make_uart, &mms->uart[1], 0x41304000, 0x1000, {= 34, 35, 43 } }, + { "uart2", make_uart, &mms->uart[2], 0x41305000, 0x1000, {= 36, 37, 44 } }, + { "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, {= 38, 39, 45 } }, + { "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, {= 40, 41, 46 } }, + { "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, {= 124, 125, 126 } }, + + { /* port 9 reserved */ }, + { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, + { "rtc", make_unimp_dev, &mms->rtc, 0x4130b000, 0x1000 }, + }, + }, { + .name =3D "ahb_ppcexp0", + .ports =3D { + { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x10= 00 }, + { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x10= 00 }, + { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x10= 00 }, + { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x10= 00 }, + { "eth", make_eth_dev, NULL, 0x41400000, 0x100000, { 48 } = }, + }, + }, + }; + switch (mmc->fpga_type) { case FPGA_AN505: case FPGA_AN521: ppcs =3D an505_ppcs; num_ppcs =3D ARRAY_SIZE(an505_ppcs); break; + case FPGA_AN524: + ppcs =3D an524_ppcs; + num_ppcs =3D ARRAY_SIZE(an524_ppcs); + break; default: g_assert_not_reached(); } @@ -900,6 +1000,27 @@ static void mps2tz_an521_class_init(ObjectClass *oc, = void *data) mps2tz_set_default_ram_info(mmc); } =20 +static void mps3tz_an524_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_CLASS(oc); + + mc->desc =3D "ARM MPS3 with AN524 FPGA image for dual Cortex-M33"; + mc->default_cpus =3D 2; + mc->min_cpus =3D mc->default_cpus; + mc->max_cpus =3D mc->default_cpus; + mmc->fpga_type =3D FPGA_AN524; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); + mmc->scc_id =3D 0x41045240; + mmc->sysclk_frq =3D 32 * 1000 * 1000; /* 32MHz */ + mmc->oscclk =3D an524_oscclk; + mmc->len_oscclk =3D ARRAY_SIZE(an524_oscclk); + mmc->numirq =3D 95; + mmc->raminfo =3D an524_raminfo; + mmc->armsse_type =3D TYPE_SSE200; + mps2tz_set_default_ram_info(mmc); +} + static const TypeInfo mps2tz_info =3D { .name =3D TYPE_MPS2TZ_MACHINE, .parent =3D TYPE_MACHINE, @@ -925,11 +1046,18 @@ static const TypeInfo mps2tz_an521_info =3D { .class_init =3D mps2tz_an521_class_init, }; =20 +static const TypeInfo mps3tz_an524_info =3D { + .name =3D TYPE_MPS3TZ_AN524_MACHINE, + .parent =3D TYPE_MPS2TZ_MACHINE, + .class_init =3D mps3tz_an524_class_init, +}; + static void mps2tz_machine_init(void) { type_register_static(&mps2tz_info); type_register_static(&mps2tz_an505_info); type_register_static(&mps2tz_an521_info); + type_register_static(&mps3tz_an524_info); } =20 type_init(mps2tz_machine_init); --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=gSDR8Mqc+foRqFOzXhqtEOdNoxWnrjbPBnz7VqeXzgo=; b=uqJjaZGFuapQ3fys4wH5iO9bLP77I9ssMg4zHAePNfgpji1dX6CPZRUGuh1p9iaG3Z UlSFVCfmdqQwksOjAQFZvFHLddaWFXr3N12IYoztFyDblOn7Ai6rZRmQ+E98VR3avi7M kbBRRk9N276Ha2dugGVkY2gBE/c3PLusA046wSVAHpYAMDmwTeWqyiKnEAEjyH37Y8IB 94SIHE8k1XGKo2ZHizJAIuSpCeD0dH7qTSq4spxyswVLMRovAE5tRpPldOT+4L3odBNE CUo9+kP9Oa0wKxvP67IdlYkYFf0A2tnHyrh3Ym3eC7asRa9buodTqNjxuH1SpdOCqiy3 ye6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gSDR8Mqc+foRqFOzXhqtEOdNoxWnrjbPBnz7VqeXzgo=; b=XkDRKYKS/OlefqJdxAG1oCk6pimXDOhLP0VN0L9hE/paxp7qSRJNuPCejUnPZGdCdn TndvRCiKSRIXSb5oDBk6E5o1XJ1CLhYZo80rvKu6sxmqaxpVwnVceDRzqs591HMIPHOo YUw759mnOFwd7U+r3OFcVP+MOlZR05ZP/mhaPwhrlcwCOaISN4/Oh9c50ZuWL4B23xgu rEjK8BfzKpV2L+tUU7Dtwe++Uwl2WemdoSzNpLUazrCdliLzqCyUjgagZ+UKuNoG22MG da4hYZVWPBztZQ5Db+9Vbn4y4Ni6/7tvjYlyy8hRDqHMOks75T8kCas8PzzDhq2O6P4K sTqg== X-Gm-Message-State: AOAM533fyjeAVgT2ahS2FO39/nhgeme6vZaut/hAgaWaoQFI08aRu+l9 mHsDdeS0vcgUB9QcjsN04JTS/g== X-Google-Smtp-Source: ABdhPJwQXtKbCOp6Rt6ML6Ze8vT9lWvmKy/uJszZ5H80LeFv73Tsa8jKgPQZOJUPg1GjLGu3p1CVEw== X-Received: by 2002:adf:f182:: with SMTP id h2mr5998497wro.355.1612544438794; Fri, 05 Feb 2021 09:00:38 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 21/24] hw/arm/mps2-tz: Stub out USB controller for mps3-an524 Date: Fri, 5 Feb 2021 17:00:16 +0000 Message-Id: <20210205170019.25319-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The AN524 has a USB controller (an ISP1763); we don't have a model of it but we should provide a stub "unimplemented-device" for it. This is slightly complicated because the USB controller shares a PPC port with the ethernet controller. Implement a make_* function which provides creates a container MemoryRegion with both the ethernet controller and an unimplemented-device stub for the USB controller. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index aa57c4b2596..db1afa4bd22 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -119,6 +119,8 @@ struct MPS2TZMachineState { =20 ARMSSE iotkit; MemoryRegion ram[MPS2TZ_RAM_MAX]; + MemoryRegion eth_usb_container; + MPS2SCC scc; MPS2FPGAIO fpgaio; TZPPC ppc[5]; @@ -130,6 +132,7 @@ struct MPS2TZMachineState { UnimplementedDeviceState gfx; UnimplementedDeviceState cldc; UnimplementedDeviceState rtc; + UnimplementedDeviceState usb; PL080State dma[4]; TZMSC msc[4]; CMSDKAPBUART uart[6]; @@ -431,6 +434,49 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *= mms, void *opaque, return sysbus_mmio_get_region(s, 0); } =20 +static MemoryRegion *make_eth_usb(MPS2TZMachineState *mms, void *opaque, + const char *name, hwaddr size, + const int *irqs) +{ + /* + * The AN524 makes the ethernet and USB share a PPC port. + * irqs[] is the ethernet IRQ. + */ + SysBusDevice *s; + NICInfo *nd =3D &nd_table[0]; + + memory_region_init(&mms->eth_usb_container, OBJECT(mms), + "mps2-tz-eth-usb-container", 0x200000); + + /* + * In hardware this is a LAN9220; the LAN9118 is software compatible + * except that it doesn't support the checksum-offload feature. + */ + qemu_check_nic_model(nd, "lan9118"); + mms->lan9118 =3D qdev_new(TYPE_LAN9118); + qdev_set_nic_properties(mms->lan9118, nd); + + s =3D SYS_BUS_DEVICE(mms->lan9118); + sysbus_realize_and_unref(s, &error_fatal); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); + + memory_region_add_subregion(&mms->eth_usb_container, + 0, sysbus_mmio_get_region(s, 0)); + + /* The USB OTG controller is an ISP1763; we don't have a model of it. = */ + object_initialize_child(OBJECT(mms), "usb-otg", + &mms->usb, TYPE_UNIMPLEMENTED_DEVICE); + qdev_prop_set_string(DEVICE(&mms->usb), "name", "usb-otg"); + qdev_prop_set_uint64(DEVICE(&mms->usb), "size", 0x100000); + s =3D SYS_BUS_DEVICE(&mms->usb); + sysbus_realize(s, &error_fatal); + + memory_region_add_subregion(&mms->eth_usb_container, + 0x100000, sysbus_mmio_get_region(s, 0)); + + return &mms->eth_usb_container; +} + static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, const int *irqs) @@ -808,7 +854,7 @@ static void mps2tz_common_init(MachineState *machine) { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x10= 00 }, { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x10= 00 }, { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x10= 00 }, - { "eth", make_eth_dev, NULL, 0x41400000, 0x100000, { 48 } = }, + { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 4= 8 } }, }, }, }; --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=fbSQXUXJEDGMaGC9KOnv4xEcH7gCV3geuE6p5sgHfh8=; b=Hte+PatvB/wD6GEvkwc2+vBLqw6TWp5P6EGpVjHY6DYpftiUEYd0/TXuSJQqbe/smp fTwC12Hb6g84oP52inUgUXsuH8iVW/pXtLL3wD9D/3OHS4Q++PCN7rmuuxURTQhMGKvB omEv/5PVMGLYfnlOkdEtdQaFTdvfVIHzNWoMHlqJCv44zysIBrap5SbArmG0sLRpuaa2 YxENM/axDVe+q64TGSmU0e/qoyGPiEdJkvMNdKHqVSXVDVVUYEoGYu3AlPg6O69UpV/a YFpusFTYkXTQOT//ERABnLC+O1Za485byjNDPX5F9mn8Yi+SrMkKd/2ZessTcJsihNUW RENg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fbSQXUXJEDGMaGC9KOnv4xEcH7gCV3geuE6p5sgHfh8=; b=O83OFBWqeGEUU5oeRknF6ydg/IO4gWvswureK/2TrCpB+lUKH0nfIHop49gsAbwctR U4/60KyupUGRo+OgHJNa8kykZh4SUwebfFXBltlmOIaPOFKY8UmKTF8C0yvPRb9EjwVw nJImpBITv2WtNfzH90jhp5pVNy7cPpsTL0cHI4kmpGZjzDZjYjCTpAMLYdXoYlKA/TJV RI68JemrhaGabzPQhapGn8SmzksWvlFsHHxmMRtlN/i/MIgDCTAzlOjZj+DUo9zhUi2F wVUqJ+M2KWXaEbW9ShejlyGCsxzrU9XGiiHgGrpXXn3qAUPEza0q4c5YoclFZl7omk2q 5h5w== X-Gm-Message-State: AOAM531/IoJT8P/V8HQ8npXN4gflDw0WTgcQ5YCPJv79Puc1TzOnG2N9 gKcHb2e8iqiu5vCK+HOvg7KqRw== X-Google-Smtp-Source: ABdhPJz+OXQX1Mq8/xcv3ZWn6/CIXW4Zo8KcjqH8sEoLPtDkyhOcVEuBSvih3ddxK48paaTFJVTKag== X-Received: by 2002:a5d:458a:: with SMTP id p10mr6085659wrq.168.1612544439505; Fri, 05 Feb 2021 09:00:39 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 22/24] hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524 Date: Fri, 5 Feb 2021 17:00:17 +0000 Message-Id: <20210205170019.25319-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The AN524 has a PL031 RTC, which we have a model of; provide it rather than an unimplemented-device stub. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps2-tz.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index db1afa4bd22..27feb36616e 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -59,6 +59,7 @@ #include "hw/misc/tz-msc.h" #include "hw/arm/armsse.h" #include "hw/dma/pl080.h" +#include "hw/rtc/pl031.h" #include "hw/ssi/pl022.h" #include "hw/i2c/arm_sbcon_i2c.h" #include "hw/net/lan9118.h" @@ -131,8 +132,8 @@ struct MPS2TZMachineState { UnimplementedDeviceState gpio[4]; UnimplementedDeviceState gfx; UnimplementedDeviceState cldc; - UnimplementedDeviceState rtc; UnimplementedDeviceState usb; + PL031State rtc; PL080State dma[4]; TZMSC msc[4]; CMSDKAPBUART uart[6]; @@ -595,6 +596,23 @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms,= void *opaque, return sysbus_mmio_get_region(s, 0); } =20 +static MemoryRegion *make_rtc(MPS2TZMachineState *mms, void *opaque, + const char *name, hwaddr size, + const int *irqs) +{ + PL031State *pl031 =3D opaque; + SysBusDevice *s; + + object_initialize_child(OBJECT(mms), name, pl031, TYPE_PL031); + s =3D SYS_BUS_DEVICE(pl031); + sysbus_realize(s, &error_fatal); + /* + * The board docs don't give an IRQ number for the PL031, so + * presumably it is not connected. + */ + return sysbus_mmio_get_region(s, 0); +} + static void create_non_mpc_ram(MPS2TZMachineState *mms) { /* @@ -845,7 +863,7 @@ static void mps2tz_common_init(MachineState *machine) =20 { /* port 9 reserved */ }, { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, - { "rtc", make_unimp_dev, &mms->rtc, 0x4130b000, 0x1000 }, + { "rtc", make_rtc, &mms->rtc, 0x4130b000, 0x1000 }, }, }, { .name =3D "ahb_ppcexp0", --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612549350; cv=none; d=zohomail.com; s=zohoarc; b=lN1l0BDDBOQ2G2PN5G9jJ7v+CJkwzDGgMkqPaRnvOq4t4NcF1VXHUUeBq7EqE8VsY4SWgR3HtlN/kT4JY/O0GB9KCLN4cs2JvIhSZlWOR4T8tdn+WHxlkmeXgPsblZeMJ03kpotXVMVJn99Wf4E6gpBmj0NnMnoT2f3AYgZEct0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612549350; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=saCU3fNa93sGe02vfYgHjxSHpcdvDyRLS+pyj+1uZRs=; b=nIX1eRAfee+quOrxhs48hA3X5YvXJh5UITQw5Jnj9RtRIBxyqYub5x+FcO7wkbdnpOdUIpoJQECvcfvKjKMcyd+4sAqaorgLHMaPpx0QteqffxO8m1pG54V8369J/uQG73fnPV8h9tI3FbQ2kBroUzag1gUAsFLZ0PiGhn8rhUQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16125493504262.085783787075002; Fri, 5 Feb 2021 10:22:30 -0800 (PST) Received: from localhost ([::1]:43650 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l85kT-0004kg-7V for importer@patchew.org; Fri, 05 Feb 2021 13:22:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46466) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l84Ts-00071d-Qn for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:16 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:33532) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l84TS-00047W-Rx for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:16 -0500 Received: by mail-wr1-x436.google.com with SMTP id 7so8520725wrz.0 for ; Fri, 05 Feb 2021 09:00:48 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=saCU3fNa93sGe02vfYgHjxSHpcdvDyRLS+pyj+1uZRs=; b=Vqi0kulHOqCCVtlemY34va18uaiYFHQQR5y+nmjaIJT5o7eW4bn/r7gMBzWWgofvYV hW1+i67RTEeQAqhivgNzte/6UqMhoJSh5MeEC1Ta0znzvTyNUSd8QGW8jP8DVjvaOVIu gTHKOPGZ5/vE1Ds2nYOR3ahc+1eSnLH1yKjuEOMSlVXKHgxQt9UFvtAn//8fVYSNEBlf b8/4nbRoR6EOJRmFDG5NW9cmoKtNDIq/S6GhfY9qzLaBroLdv3Juz9kNQYs8DLdpMs0R e5AZX0SUakA7IrRp/B4OYg6+XlA6SOTjoe3lQp7D5xuDed9pAf+8lDpl6DmTeVtTkYMJ GSMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=saCU3fNa93sGe02vfYgHjxSHpcdvDyRLS+pyj+1uZRs=; b=SXI36a6vL99fT5jf49xIzcxzSGAOvZ0BSsbX+MJpj0fdiXd976P7oV07Qyj01CZnL/ lTRFdGuo2mekaJsb6DCtb0Q7RnGgCGV6mvgWejf1gEKRW/IeJL9l44JieplT8TNkEYao DkDnPJB1v0UVBvb/bbxRpXbdPmBfoMQpIoFC/Oxx/tGugU68EE7yCKHEY3055lIOSIAv MDzlJecXNhRyVkSp3xIoi8u32t4qSldrdJ1wxCTIJ1afoP0bwPkp+H8MdNquQp1hSlcD Dk3rfRLPn0CSNzkmLoJq8lBjq+qXLhHhz64mFR4B6hzeqwLgeCD1xSzMm5YLtG+Twn9k mYMw== X-Gm-Message-State: AOAM531lv2blUDK3nJP5kZADEQKIWhGwaUJml2xLbvWx2+nteY8nVLp3 B3GyPCfDjQwivtxom9uGocbu3w== X-Google-Smtp-Source: ABdhPJw/Q8zqSHNh1pF+QaNV1mDx9nGVciuno+RpjDrHeW8j9Br7yxhlwNEnoQiWNziB8e9icI1Xzw== X-Received: by 2002:adf:decf:: with SMTP id i15mr6010264wrn.405.1612544440245; Fri, 05 Feb 2021 09:00:40 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 23/24] docs/system/arm/mps2.rst: Document the new mps3-an524 board Date: Fri, 5 Feb 2021 17:00:18 +0000 Message-Id: <20210205170019.25319-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Add brief documentation of the new mps3-an524 board. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- docs/system/arm/mps2.rst | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index 8c5b5f1fe07..601ccea15cb 100644 --- a/docs/system/arm/mps2.rst +++ b/docs/system/arm/mps2.rst @@ -1,12 +1,15 @@ -Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an= 505``, ``mps2-an511``, ``mps2-an521``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, = ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 These board models all use Arm M-profile CPUs. =20 -The Arm MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger -FPGA but is otherwise the same as the 2). Since the CPU itself -and most of the devices are in the FPGA, the details of the board -as seen by the guest depend significantly on the FPGA image. +The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a +bigger FPGA but is otherwise the same as the 2; the 3 has a bigger +FPGA again, can handle 4GB of RAM and has a USB controller and QSPI flash). + +Since the CPU itself and most of the devices are in the FPGA, the +details of the board as seen by the guest depend significantly on the +FPGA image. =20 QEMU models the following FPGA images: =20 @@ -22,12 +25,21 @@ QEMU models the following FPGA images: Cortex-M3 'DesignStart' as documented in Arm Application Note AN511 ``mps2-an521`` Dual Cortex-M33 as documented in Arm Application Note AN521 +``mps3-an524`` + Dual Cortex-M33 on an MPS3, as documented in Arm Application Note AN524 =20 Differences between QEMU and real hardware: =20 - AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as if zbt_boot_ctrl is always zero) +- AN524 remapping of low memory to either BRAM or to QSPI flash is + unimplemented (QEMU always maps this to BRAM, ignoring the + SCC CFG_REG0 memory-remap bit) - QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest visible difference is that the LAN9118 doesn't support checksum offloading +- QEMU does not model the QSPI flash in MPS3 boards as real QSPI + flash, but only as simple ROM, so attempting to rewrite the flash + from the guest will fail +- QEMU does not model the USB controller in MPS3 boards --=20 2.20.1 From nobody Sat Apr 27 06:15:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612546972; cv=none; d=zohomail.com; s=zohoarc; b=Ehnx+YWIz43cNCNFANf8f/nWEN0WQrGT6SBickk2MQML6Wv2lvHP7JF+lJlBd1AsG/+gaiF0tlEjTK8v+9WX89pvR4oLX4pnFB9fFNmLhiln0dhhLWN2S2TB5/ul2ItE8P9va4tmkV0dpVDnH3ZDS9C6p+BfD4UVcJQqptEefSE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612546972; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Lp/PXJ/Lg+jhfej9/mPuXMN8i+zU7pqYIRVDjsjSQS8=; b=fmGMxjewO73jm2VkbOzWT4EVhbm532OClwSIc+dA4Fw6jbAvY8TQ/cbuQWfJhUuREj90mS1zvcQXoseAykA72kmFjLVf4qkAoeYzrG9VgOqovmTPJEDzvvxRwBoU2JJ9PDHme1VoukeAWafkAoYcESm9q2H8H4XeCXU4dhwMzBY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612546972865793.2760939149321; Fri, 5 Feb 2021 09:42:52 -0800 (PST) Received: from localhost ([::1]:39058 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l8587-0006N6-47 for importer@patchew.org; Fri, 05 Feb 2021 12:42:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46396) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l84Tn-0006wk-Qc for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:11 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:38215) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l84TO-00045L-JD for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:01:11 -0500 Received: by mail-wr1-x429.google.com with SMTP id b3so8451270wrj.5 for ; Fri, 05 Feb 2021 09:00:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Lp/PXJ/Lg+jhfej9/mPuXMN8i+zU7pqYIRVDjsjSQS8=; b=yW1fULBK2cOdQTC7E/RkebMVAZvJry9y1rMYHeYfcGPOZgajhWqHA7pbFakRKXdsGh Ni/tZog01acku1CI7ADzAdlZX2xrL6m15HVD7t3f2z/bwTvwnCcn16UnB75tWk22hjfE Thb7Bij1e97u/jUv3+eN4Ex85DpD9le0P5Sth8Y8ET8cyQqgy17VKd+BbtDq+hQjwXPn 4t4e1frVviAiTeXtPM7A6eJaE6dPNyhrDhFKy9QC9UmAJ0g8VCRl85GxS2i62Ek0WCsX UwrdNSd/13pJ3rNVc5F3LmUmB5q/qBilitE3HmodEfigdbMznQnK3AkEfC2bKwavNhcf HH2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Lp/PXJ/Lg+jhfej9/mPuXMN8i+zU7pqYIRVDjsjSQS8=; b=K0ILzi2KlokA1DPpmkS4Q1M32i0cq8HUcGYaSOcgVCdcDDdKRwa4MgnjTNr0vXNYrP 5UWtIrJNq2tBcKc9oV67atmo5vJqFdsgMPH2JrGcGqPp3bGCYswpXBqrH+ZwBeH1UpB3 ADpb2i8DrYiWEMUxlASa15gEpqrCu5Og9I07fLeh4gb+sU1vZgykx39UbDq5+6novOmk llgrYU3YlY6+y7XYSTTU+boMEzEpMvy1MgExDaU9z00AI30pBdpz62zYmM+6d6weUJXV S7U9sFqZw8o3DSYWlyNutoJ1skdij5Lpmusnk5MjfcTYiPvbna7/Vax8C02bU1RBmRAY YZ2A== X-Gm-Message-State: AOAM530cwGcRJtzvwo3V1HBadgMODfr2Ps9cDrizQe+CiIwEJMgh/y3l f1OHHgKhGgpQrsxJeMxXFFinFQ== X-Google-Smtp-Source: ABdhPJzmo+jZXJpo06gk1+gfg9kSSOxUnpNEObe2Kl0bSJh3VY42bDJKXWnhFL0Nde3fPbGEMxlYQw== X-Received: by 2002:adf:80e7:: with SMTP id 94mr5129031wrl.5.1612544441264; Fri, 05 Feb 2021 09:00:41 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 24/24] hw/arm/mps2: Update old infocenter.arm.com URLs Date: Fri, 5 Feb 2021 17:00:19 +0000 Message-Id: <20210205170019.25319-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Update old infocenter.arm.com URLs to the equivalent developer.arm.com ones (the old URLs should redirect, but we might as well avoid the redirection notice, and the new URLs are pleasantly shorter). This commit covers the links to the MPS2 board TRM, the various Application Notes, the IoTKit and SSE-200 documents. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- There are some other infocenter URLs in the codebase; we should probably update those too, but they don't really fit in with this patchset, so I'll do them separately later. --- include/hw/arm/armsse.h | 4 ++-- include/hw/misc/armsse-cpuid.h | 2 +- include/hw/misc/armsse-mhu.h | 2 +- include/hw/misc/iotkit-secctl.h | 2 +- include/hw/misc/iotkit-sysctl.h | 2 +- include/hw/misc/iotkit-sysinfo.h | 2 +- include/hw/misc/mps2-fpgaio.h | 2 +- hw/arm/mps2-tz.c | 11 +++++------ hw/misc/armsse-cpuid.c | 2 +- hw/misc/armsse-mhu.c | 2 +- hw/misc/iotkit-sysctl.c | 2 +- hw/misc/iotkit-sysinfo.c | 2 +- hw/misc/mps2-fpgaio.c | 2 +- hw/misc/mps2-scc.c | 2 +- 14 files changed, 19 insertions(+), 20 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 676cd4f36b0..09284ca75cf 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -14,9 +14,9 @@ * hardware, which include the IoT Kit and the SSE-050, SSE-100 and * SSE-200. Currently we model: * - the Arm IoT Kit which is documented in - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm060125= 6/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * - the SSE-200 which is documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/core= link_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_0= 0_en.pdf + * https://developer.arm.com/documentation/101104/latest/ * * The IoTKit contains: * a Cortex-M33 diff --git a/include/hw/misc/armsse-cpuid.h b/include/hw/misc/armsse-cpuid.h index a61355e5161..9c0926322cb 100644 --- a/include/hw/misc/armsse-cpuid.h +++ b/include/hw/misc/armsse-cpuid.h @@ -12,7 +12,7 @@ /* * This is a model of the "CPU_IDENTITY" register block which is part of t= he * Arm SSE-200 and documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/core= link_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_0= 0_en.pdf + * https://developer.arm.com/documentation/101104/latest/ * * QEMU interface: * + QOM property "CPUID": the value to use for the CPUID register diff --git a/include/hw/misc/armsse-mhu.h b/include/hw/misc/armsse-mhu.h index 2671b5b978b..41925ded89b 100644 --- a/include/hw/misc/armsse-mhu.h +++ b/include/hw/misc/armsse-mhu.h @@ -12,7 +12,7 @@ /* * This is a model of the Message Handling Unit (MHU) which is part of the * Arm SSE-200 and documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/core= link_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_0= 0_en.pdf + * https://developer.arm.com/documentation/101104/latest/ * * QEMU interface: * + sysbus MMIO region 0: the system information register bank diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secct= l.h index 54c212b515c..227d44abe49 100644 --- a/include/hw/misc/iotkit-secctl.h +++ b/include/hw/misc/iotkit-secctl.h @@ -11,7 +11,7 @@ =20 /* This is a model of the security controller which is part of the * Arm IoT Kit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm060125= 6/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * * QEMU interface: * + sysbus MMIO region 0 is the "secure privilege control block" registe= rs diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysct= l.h index 2b5636b218c..2bc391138db 100644 --- a/include/hw/misc/iotkit-sysctl.h +++ b/include/hw/misc/iotkit-sysctl.h @@ -12,7 +12,7 @@ /* * This is a model of the "system control element" which is part of the * Arm IoTKit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm060125= 6/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * Specifically, it implements the "system information block" and * "system control register" blocks. * diff --git a/include/hw/misc/iotkit-sysinfo.h b/include/hw/misc/iotkit-sysi= nfo.h index 7e620e2eafe..055771d2098 100644 --- a/include/hw/misc/iotkit-sysinfo.h +++ b/include/hw/misc/iotkit-sysinfo.h @@ -12,7 +12,7 @@ /* * This is a model of the "system information block" which is part of the * Arm IoTKit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm060125= 6/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * QEMU interface: * + QOM property "SYS_VERSION": value to use for SYS_VERSION register * + QOM property "SYS_CONFIG": value to use for SYS_CONFIG register diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h index 83c6e18a4ee..7f622bae536 100644 --- a/include/hw/misc/mps2-fpgaio.h +++ b/include/hw/misc/mps2-fpgaio.h @@ -12,7 +12,7 @@ /* This is a model of the FPGAIO register block in the AN505 * FPGA image for the MPS2 dev board; it is documented in the * application note: - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html + * https://developer.arm.com/documentation/dai0505/latest/ * * QEMU interface: * + sysbus MMIO region 0: the register bank diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 27feb36616e..944f44f4a31 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -22,21 +22,20 @@ * https://developer.arm.com/products/system-design/development-boards/fpg= a-prototyping-boards/mps2 * * Board TRM: - * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/vers= atile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_techni= cal_reference_100112_0200_06_en.pdf + * https://developer.arm.com/documentation/100112/latest/ * Application Note AN505: - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html + * https://developer.arm.com/documentation/dai0505/latest/ * Application Note AN521: - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html + * https://developer.arm.com/documentation/dai0521/latest/ * Application Note AN524: * https://developer.arm.com/documentation/dai0524/latest/ * * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Gu= ide * (ARM ECM0601256) for the details of some of the device layout: - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm0601= 256/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM def= ines * most of the device layout: - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/cor= elink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_= 00_en.pdf - * + * https://developer.arm.com/documentation/101104/latest/ */ =20 #include "qemu/osdep.h" diff --git a/hw/misc/armsse-cpuid.c b/hw/misc/armsse-cpuid.c index d58138dc28c..e785a090519 100644 --- a/hw/misc/armsse-cpuid.c +++ b/hw/misc/armsse-cpuid.c @@ -12,7 +12,7 @@ /* * This is a model of the "CPU_IDENTITY" register block which is part of t= he * Arm SSE-200 and documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/core= link_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_0= 0_en.pdf + * https://developer.arm.com/documentation/101104/latest/ * * It consists of one read-only CPUID register (set by QOM property), plus= the * usual ID registers. diff --git a/hw/misc/armsse-mhu.c b/hw/misc/armsse-mhu.c index a45d97fada8..0be7f0fc874 100644 --- a/hw/misc/armsse-mhu.c +++ b/hw/misc/armsse-mhu.c @@ -12,7 +12,7 @@ /* * This is a model of the Message Handling Unit (MHU) which is part of the * Arm SSE-200 and documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/core= link_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_0= 0_en.pdf + * https://developer.arm.com/documentation/101104/latest/ */ =20 #include "qemu/osdep.h" diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index 964b48c74d9..222511c4b04 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -12,7 +12,7 @@ /* * This is a model of the "system control element" which is part of the * Arm IoTKit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm060125= 6/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * Specifically, it implements the "system control register" blocks. */ =20 diff --git a/hw/misc/iotkit-sysinfo.c b/hw/misc/iotkit-sysinfo.c index b2dcfc4376c..52e70053df7 100644 --- a/hw/misc/iotkit-sysinfo.c +++ b/hw/misc/iotkit-sysinfo.c @@ -12,7 +12,7 @@ /* * This is a model of the "system information block" which is part of the * Arm IoTKit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm060125= 6/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * It consists of 2 read-only version/config registers, plus the * usual ID registers. */ diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c index b54657a4f07..64a383e063b 100644 --- a/hw/misc/mps2-fpgaio.c +++ b/hw/misc/mps2-fpgaio.c @@ -12,7 +12,7 @@ /* This is a model of the "FPGA system control and I/O" block found * in the AN505 FPGA image for the MPS2 devboard. * It is documented in AN505: - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html + * https://developer.arm.com/documentation/dai0505/latest/ */ =20 #include "qemu/osdep.h" diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index 562ace06a58..140a4b9ceba 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -13,7 +13,7 @@ * found in the FPGA images of MPS2 development boards. * * Documentation of it can be found in the MPS2 TRM: - * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.100112_01= 00_03_en/index.html + * https://developer.arm.com/documentation/100112/latest/ * and also in the Application Notes documenting individual FPGA images. */ =20 --=20 2.20.1