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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DTK4SJ5LYtJuHvuHu8AwQw2u8TQxf0ZzT7dsGBYnc0Y=; b=kePOshLbYGH7DlnSrh6q2+BxLTkAzaVnUfnvBxbMu11rWZNnm2hVdev2GyPL4CiJV/ +Np8864tiZXPvGE3hTxK1qG8snvXhZltjWZ+Bzqnl2lVI7nCY0c3Xt6PqQsu44f8kGYB YEDg0mxtYrbiycHRm4lP/jE9IxzySecnxxwAkiSZAheF/IEcGDIj1idzMhh3hoilpIjm dfI+FKdSUacZcrRCwY5vgkQbJ7uFitV/zWlodcFPBYZ03tkHay6UYWppOEJJoqxstEuJ ClYCpFhY9ElVfKCQk1V+YEtZxBZeGjtrff+7oaldWVmatNXOoFrX+cnV4JW/ZA/XI624 EnFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DTK4SJ5LYtJuHvuHu8AwQw2u8TQxf0ZzT7dsGBYnc0Y=; b=EWuepmu8Dvv+Sg358OiQZQN4Ma5jpR0+KHlxMhwm70uANDJWjL6+TWll5RtveH+Ulu /3pg9GVBu8dba9dZOT/w2kjc/GTCwLCZC3DTCV0D00qvI3wADAt2PzvW3vOyclFgn7+W sv3d2q5e7XZANubWlad7tC9BFIkZPMfyBfxWs0ROgh9aVZHw7pKjFeOVhs39b9KkpjWq 5o4Tpo13rKAdDz9cG4ey+amvWUtUiayfRuovnfjt0tLm7CHVMvlETrut9ItIKmKWVf0u fmGbp+2ggS0GN3Pac3lukDZHyCOt3LBpNnRR1HP8RNGZMMfzbsDO2mL5nZn+rMhwrdkM 6mlA== X-Gm-Message-State: AOAM531rmWuPun1JFBTdbb2bq2SR8qsVvwoQrU64umaSPs6SfnrHrf48 87RxSmMthHnJoIneZPaJlszpO/uEj2hbNLxI X-Google-Smtp-Source: ABdhPJxiWk6mRMbUfz+0DBKOIJhVNaktFtQFqUA1m5uxBaJzd5OQmcFsSyn4PhmLu+P2DigJ6lwJAg== X-Received: by 2002:a17:90a:4096:: with SMTP id l22mr4322871pjg.34.1612403179342; Wed, 03 Feb 2021 17:46:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 37/93] tcg/tci: Merge basic arithmetic operations Date: Wed, 3 Feb 2021 15:44:13 -1000 Message-Id: <20210204014509.882821-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This includes add, sub, mul, and, or, xor. Signed-off-by: Richard Henderson --- tcg/tci.c | 83 +++++++++++++++++-------------------------------------- 1 file changed, 25 insertions(+), 58 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 0246e663a3..894e87e1b0 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -468,26 +468,47 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, *(uint32_t *)(t1 + t2) =3D t0; break; =20 - /* Arithmetic operations (32 bit). */ + /* Arithmetic operations (mixed 32/64 bit). */ =20 - case INDEX_op_add_i32: + CASE_32_64(add) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; - case INDEX_op_sub_i32: + CASE_32_64(sub) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; - case INDEX_op_mul_i32: + CASE_32_64(mul) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; + CASE_32_64(and) + t0 =3D *tb_ptr++; + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, t1 & t2); + break; + CASE_32_64(or) + t0 =3D *tb_ptr++; + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, t1 | t2); + break; + CASE_32_64(xor) + t0 =3D *tb_ptr++; + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, t1 ^ t2); + break; + + /* Arithmetic operations (32 bit). */ + case INDEX_op_div_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); @@ -512,24 +533,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); break; - case INDEX_op_and_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); - break; - case INDEX_op_or_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); - break; - case INDEX_op_xor_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); - break; =20 /* Shift/rotate operations (32 bit). */ =20 @@ -712,24 +715,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, =20 /* Arithmetic operations (64 bit). */ =20 - case INDEX_op_add_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 + t2); - break; - case INDEX_op_sub_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 - t2); - break; - case INDEX_op_mul_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 * t2); - break; case INDEX_op_div_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); @@ -754,24 +739,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; - case INDEX_op_and_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); - break; - case INDEX_op_or_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); - break; - case INDEX_op_xor_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); - break; =20 /* Shift/rotate operations (64 bit). */ =20 --=20 2.25.1