From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612403490; cv=none; d=zohomail.com; s=zohoarc; b=lHQ7sssRSCR//+KmbD/mIcN83PTHAjOI8ovBWk5QUrnbXHHmDmth2Oft5tWthce+hxam9CKpOjFxY0QiyuZ14WxNxH0jHEvDv+iE7DDZ8LR2LPNxPBjHb/Wl9OPwpr5idFy2aH23X+pVspgIizw8/NgdHa8gp48RyAGgmG6qd7E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612403490; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=06H8W/q0v8WI5yMb4Dgc4NhHzAw8roTrWJkM0Lw1UXA=; b=Hg7dpLvhoid6k1EFDnjL1DRDckPKCKPP258EjcMH2vyvV+ESKCukwlZIGEnNzOK1sPAoMAGhge/gTZ6NXyFSojNMwukSOsjwr1VG5Sug0/YU83Sm96zGI36gj8SlUkjY+0ANwWdLXtOYsNRY6XNUDJ3OUx94s7INjaShOtsJzrU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612403490266144.8814420221736; Wed, 3 Feb 2021 17:51:30 -0800 (PST) Received: from localhost ([::1]:42794 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7Tns-0001xo-PY for importer@patchew.org; Wed, 03 Feb 2021 20:51:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44108) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Thv-0004Uz-Mq for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:19 -0500 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:35017) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tht-0003WL-B7 for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:19 -0500 Received: by mail-pg1-x52f.google.com with SMTP id t25so1048727pga.2 for ; Wed, 03 Feb 2021 17:45:16 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=06H8W/q0v8WI5yMb4Dgc4NhHzAw8roTrWJkM0Lw1UXA=; b=DuqrYvMwhBsc+qfGK1FRo0OYd+ObwZJjKbK91T39gCwuU3LrSqkOrErS6AAw+3ogQ6 HoP1IYIAMqYv5yLwGI4i2ICtFICfW4Yn6b9HJKauwAOmh+ImpeoP/yWcmGDB8KD/Vukh RAHahpVMWLMGXPu5RRoAji87XBIvYRoG1hRU5YZohGnZdzL7sdPibIKBbyfEDhJFufLc /9waZnEeTskxdNC89DYgkQkNv4bHNW1KksxoG9MEyCTVYYsXeixEZE1Q91DMVWsRRpOQ ytJj5HWx2iydLXfoebTvT4p4e8ufAMr3OUYCOIqIdJiRh+Ac65sJEnmdayAYtpsl9qaK 9FcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=06H8W/q0v8WI5yMb4Dgc4NhHzAw8roTrWJkM0Lw1UXA=; b=YA74PkgLDnOauqAENe5lUoG9rrmVhJ7KS2laoFVz5cYyBYv/R6kLQm2JXnuuftQM9o Gh5W9pQNU5ikT4DaSRXaocZY1HgP04wkY/rvFBzeG/PrnYBdhFb4vKF8RUayg2BphV32 rlvD9UY+NyiTwuKOzCgl69PFf7OMnr8pCf6DKtPTzeth9CjTS1Q3qREGufp052sX/NJg +4E3tohXdIdaz6jpOBT0D+k8yQYHo/+6RXTfesj7zm3bFBTPz2prTlg8mENWetpI9Saw HvCAHIoKW0FMYUSxsJANe7Dkg1VsFMGrzyPGavAeZO4hjpY6mQ+QYEdxpOVOFz7IkAev 0HCg== X-Gm-Message-State: AOAM532/EnrQPac/WpUyAVPZ6BPgNamVt3BjGI4zbj1C80cXbJYkKHSp UN1TMkuNVsCxXH9lQhA4+iqBmTl1hoMFSZVR X-Google-Smtp-Source: ABdhPJzLN6FM2njZLsbVLKAuUAgkNXInu3QxWRRxovKjKH6Es3fTt7HJe4ldbi6CYaDEay+pftptVA== X-Received: by 2002:a62:f243:0:b029:1c2:8424:2495 with SMTP id y3-20020a62f2430000b02901c284242495mr5827298pfl.32.1612403115921; Wed, 03 Feb 2021 17:45:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 01/93] gdbstub: Fix handle_query_xfer_auxv Date: Wed, 3 Feb 2021 15:43:37 -1000 Message-Id: <20210204014509.882821-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The main problem was that we were treating a guest address as a host address with a mere cast. Use the correct interface for accessing guest memory. Do not allow offset =3D=3D auxv_len, which would result in an empty packet. Fixes: 51c623b0de1 ("gdbstub: add support to Xfer:auxv:read: packet") Signed-off-by: Richard Henderson --- gdbstub.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index c7ca7e9f88..759bb00bcf 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -2245,7 +2245,6 @@ static void handle_query_xfer_auxv(GdbCmdContext *gdb= _ctx, void *user_ctx) { TaskState *ts; unsigned long offset, len, saved_auxv, auxv_len; - const char *mem; =20 if (gdb_ctx->num_params < 2) { put_packet("E22"); @@ -2257,8 +2256,8 @@ static void handle_query_xfer_auxv(GdbCmdContext *gdb= _ctx, void *user_ctx) ts =3D gdbserver_state.c_cpu->opaque; saved_auxv =3D ts->info->saved_auxv; auxv_len =3D ts->info->auxv_len; - mem =3D (const char *)(saved_auxv + offset); - if (offset > auxv_len) { + + if (offset >=3D auxv_len) { put_packet("E00"); return; } @@ -2269,12 +2268,20 @@ static void handle_query_xfer_auxv(GdbCmdContext *g= db_ctx, void *user_ctx) =20 if (len < auxv_len - offset) { g_string_assign(gdbserver_state.str_buf, "m"); - memtox(gdbserver_state.str_buf, mem, len); } else { g_string_assign(gdbserver_state.str_buf, "l"); - memtox(gdbserver_state.str_buf, mem, auxv_len - offset); + len =3D auxv_len - offset; } =20 + g_byte_array_set_size(gdbserver_state.mem_buf, len); + if (target_memory_rw_debug(gdbserver_state.g_cpu, saved_auxv + offset, + gdbserver_state.mem_buf->data, len, false))= { + put_packet("E14"); + return; + } + + memtox(gdbserver_state.str_buf, + (const char *)gdbserver_state.mem_buf->data, len); put_packet_binary(gdbserver_state.str_buf->str, gdbserver_state.str_buf->len, true); } --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612403327; cv=none; d=zohomail.com; s=zohoarc; b=GN/eHtKvzYb2YZSFvGa7OLuw4+zNrzxhAm7fBP2FHcj4bZXB+lRmqCAQYUXt74kPnCyTtyZMW791P3q8mzqHjVAqI955WrTeqJPGyM6cjawC8ltIYjv0y2UxPu0afrVI1370uYxwKQSbYK7FrLrVn0EIvrjmcH4cvJ+B+DByiXw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612403327; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rTk7Zu1K9am+nHTK4Qgzw1qdbWz4Og49PpMunTWLZww=; b=bqDZLH7g2NkIcLMTrfcp9Q1ARmunqAVKFeVqjGGyLyIkWRAre2I1Q5HC3HrJsiBfCQp9+AXjlHpo5lTFUWry34tsiLHIMk26x1aJ+Q4bOqBycl34A+/Tt4yhPGm3UeW6dtzG02SA4rDq9R9S49iqrF3DnDxxeAmxVw6XCzA0w5g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612403327889431.85435814164384; Wed, 3 Feb 2021 17:48:47 -0800 (PST) Received: from localhost ([::1]:34248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7TlG-0006mk-P8 for importer@patchew.org; Wed, 03 Feb 2021 20:48:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44116) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Thw-0004VD-PY for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:20 -0500 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:39190) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Thv-0003WU-6H for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:20 -0500 Received: by mail-pj1-x102e.google.com with SMTP id d2so818468pjs.4 for ; Wed, 03 Feb 2021 17:45:18 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rTk7Zu1K9am+nHTK4Qgzw1qdbWz4Og49PpMunTWLZww=; b=L+vMsTdHO+F+rWu2A8IcnDBW63zUfluuYsThUOtUy1nn1H/N21XLlrqEk6Hfdcn2K0 UH5iIBiHBNkXe4Uhd5JUuRKx5GDWIA5qUFSnRNGmxXsVHQOOghVYMsHDiZC0XacpWjWB PbB8y9/38/Bwl5DNpYyPHgk8xsgMULnpG5PwvU0ilUNOyZm5HYG6OQL2jB0aNpXmkrqV +SdeQ2zPytUBoyArIB2y2tWaL8Y1cwmdk3FMhQ9+TegaUQH5GHh6u4DMb3+iXr+EhQvt sWwM6mcsAb/rlCS1pDCDWcqkPQ1wPVk2NNIc74619CXvZ0FjZzl1dKZPhCa+LsOKVz96 UuDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rTk7Zu1K9am+nHTK4Qgzw1qdbWz4Og49PpMunTWLZww=; b=iAFJVYFkrRqKLukr5jU7lWt3k+qkz9slZ4Wx41NV3ZWv8cRfIH/0Vbmnu07lZSMHZg WwvSFSjnW/hpKDltGkqB5umtcWh2wVzHtAmSIDoFtHcsiiqoTC1sMKyh5oEgXBXD+Nct gOOnaMeZQnwVKmqvBDbRwNMZ+IhoDZcFqF5O511hy5P7eIjmFkVplN39olzLS4UdxTe7 jikNeRBGMg3YCmtttvhvZt1SrITpEmNf3cPRq1XHnEx0IiZTT0BAQqHowPHlJbgdxc6a tXqAwyc1OHj7UoqwYR9zlhH3BpvKN/On6eY6ARBdV04xJ4KmNTZiSfVurO2l+WDH6E5T 8Ejg== X-Gm-Message-State: AOAM532w3zY5uWWJIRFb6olxh8xF0hUbT/vedWT3EfldRUD20dEe8ci6 N4qlmRwFrYILgZx+hynRhg68QIglfT1fhw39 X-Google-Smtp-Source: ABdhPJwWneJQAsKF2/LryP/2pTcpuRQg1iOmdJPzPb3LkbuvZedSj0AvWKPgScQ5ebqD9OZamJTi5Q== X-Received: by 2002:a17:90b:1996:: with SMTP id mv22mr5867676pjb.121.1612403117725; Wed, 03 Feb 2021 17:45:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 02/93] tcg: Split out tcg_raise_tb_overflow Date: Wed, 3 Feb 2021 15:43:38 -1000 Message-Id: <20210204014509.882821-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Allow other places in tcg to restart with a smaller tb. Signed-off-by: Richard Henderson --- tcg/tcg.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 63a12b197b..bbe3dcee03 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -346,6 +346,12 @@ static void set_jmp_reset_offset(TCGContext *s, int wh= ich) s->tb_jmp_reset_offset[which] =3D tcg_current_code_size(s); } =20 +/* Signal overflow, starting over with fewer guest insns. */ +static void QEMU_NORETURN tcg_raise_tb_overflow(TCGContext *s) +{ + siglongjmp(s->jmp_trans, -2); +} + #define C_PFX1(P, A) P##A #define C_PFX2(P, A, B) P##A##_##B #define C_PFX3(P, A, B, C) P##A##_##B##_##C @@ -1310,8 +1316,7 @@ static TCGTemp *tcg_temp_alloc(TCGContext *s) int n =3D s->nb_temps++; =20 if (n >=3D TCG_MAX_TEMPS) { - /* Signal overflow, starting over with fewer guest insns. */ - siglongjmp(s->jmp_trans, -2); + tcg_raise_tb_overflow(s); } return memset(&s->temps[n], 0, sizeof(TCGTemp)); } --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612403654; cv=none; d=zohomail.com; s=zohoarc; b=HCrWnOe+F8ENYvNydp99VXmooEgojP6dUmwO/1iHrfrgH/NTJCDowIEoJxI34HsiUGaUrDb/klDNCsZ87O9cdZR09WLw/wFji302cAqhEJdcWiAD5ZFj9kyS8PACR2rw59HCBkGAfFFkirkCk2u0d6BZOBMCV3EnYsrd6/M5RJg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612403654; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=C3tpiU3zelsjFSQQuB1ZzEawshUyJREYmvhF2hEYIiM=; b=V1xQx+lx8UExH5JCcOYQM8waq47lBqr+waLjlgoT9cEvX1cbEOId2K7bgld6tL+L00VquZ5KL16RtsBsIscojoRct7gfUKL8unwQaqtUX/HhAPiQoHr8N8/mPToLI4sdPXQohF5fssM7g1XdHeJQ6rHfFC2y25hyZiOkmCGlgvg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612403654403478.4780989094828; Wed, 3 Feb 2021 17:54:14 -0800 (PST) Received: from localhost ([::1]:51378 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7TqX-0005ZS-6w for importer@patchew.org; Wed, 03 Feb 2021 20:54:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44130) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Thz-0004XO-11 for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:23 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:33127) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Thx-0003XU-At for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:22 -0500 Received: by mail-pl1-x62b.google.com with SMTP id d13so905261plg.0 for ; Wed, 03 Feb 2021 17:45:20 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=C3tpiU3zelsjFSQQuB1ZzEawshUyJREYmvhF2hEYIiM=; b=Lsga50J3Bb6Bfy1Df6O/QA443/VfrkhBkUx5unmEi8UJ2M5fyC2q25127EGJLvz3IL gQzeuPmCIkLadfLPEOpq8dyZXAcP6+FmAu0LXjl1Il0wFy3WQ4x99T7YPs+BCUiqLeRM /45K8Zq9T+V5VNjNwTWfWbYnNmqbZoHzfobqrgWl2OIi6tR+f4IbYTgHfdcyHQYlfQZ5 XygnzwpQuYMJmjkRGRbpJ4IX2G4VX2+aKuM35Jwf80Pw5VExqWOdLxFTqznBvbzewxSw rsu9ZkqIQGOJhycftrchSEx8m8Y3Qx2K60+g1K9negiar9b/cImflr4zEQfuITjVAPcm t5mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=C3tpiU3zelsjFSQQuB1ZzEawshUyJREYmvhF2hEYIiM=; b=s9sanZXPNiCoAKkax5MB+OCYHrSsOtKD+TgQ+CGvlXYYtYa8HUFjFHMhdBx3JkEqS6 776Zam6U9ci62wqGxjmU52Fn3lEoQ8TURKhkgIKS5thDh744og17YJyU+xZAPv29yDOs A7hyFgpQBnCHUaVPJsa1as5LTwIGzL/jRE2Y2cOu3pxvZ4obfL3fueJE9uCuZV1IBK3O FGfw6ef6pHvQUMkcWZ11n3EtzceJzKhN+FCRS8yHR8onHZTk4rOhto+u2tSr82ZtOLSR KSGKl5To39kpR2W/v5OHvJXIeijcNVkwsVtLFAixwavhlIT95KOpzWN2uNiZQTz67//G ZZTA== X-Gm-Message-State: AOAM532vwfClNlo8xCJiiaa6mqvDJsQTmw8iX2gD1Y9IAzcrJKdBRHsd 5FE3OxXy59P8+UcMSOIP32F4TyPvmE+XgZ9W X-Google-Smtp-Source: ABdhPJwQbJIqh1PYswrsCWsEoq28AYrkeNJb6LTC00TOFwxtpzRbAVBhPwRZcwrV5RuTGM1DbN9vZw== X-Received: by 2002:a17:902:e211:b029:e2:843c:426e with SMTP id u17-20020a170902e211b02900e2843c426emr5543556plb.16.1612403120092; Wed, 03 Feb 2021 17:45:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 03/93] configure: Fix --enable-tcg-interpreter Date: Wed, 3 Feb 2021 15:43:39 -1000 Message-Id: <20210204014509.882821-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The configure option was backward, and we failed to pass the value on to meson. Fixes: 23a77b2d18b ("build-system: clean up TCG/TCI configury") Tested-by: Stefan Weil Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel P. Berrang=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- configure | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/configure b/configure index e85d6baf8f..a34f91171d 100755 --- a/configure +++ b/configure @@ -1110,9 +1110,9 @@ for opt do ;; --enable-whpx) whpx=3D"enabled" ;; - --disable-tcg-interpreter) tcg_interpreter=3D"true" + --disable-tcg-interpreter) tcg_interpreter=3D"false" ;; - --enable-tcg-interpreter) tcg_interpreter=3D"false" + --enable-tcg-interpreter) tcg_interpreter=3D"true" ;; --disable-cap-ng) cap_ng=3D"disabled" ;; @@ -6417,6 +6417,7 @@ NINJA=3D$ninja $meson setup \ -Dvhost_user_blk_server=3D$vhost_user_blk_server \ -Dfuse=3D$fuse -Dfuse_lseek=3D$fuse_lseek -Dguest_agent_msi=3D$gue= st_agent_msi \ $(if test "$default_features" =3D no; then echo "-Dauto_features= =3Ddisabled"; fi) \ + -Dtcg_interpreter=3D$tcg_interpreter \ $cross_arg \ "$PWD" "$source_path" =20 --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612403329; cv=none; d=zohomail.com; s=zohoarc; b=MXHRy1z/tlv9kMvAVxJ69KhT0zN4V4omvWlwGxH8bdVx4o6xvzSmQLurrbC2nlxHFliqEFzFmjX9yxOPovb/CRcoqiffcZy9cAQys2WsjFr83VhIl78IrQ3HRn0BsBMriiPcEKrzdPuYY3Z0uCA+ge2LsvPaIt/hgm94r5Iz69g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612403329; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xzKpOz1dnkvT+2F/uu8BRDtdRIBrUsrfNHwaFpPfXw4=; b=AqbUO/Tn2TGnKjmzYvBdLKoSdALk3CdgFO8hKJxr9aKaryzEM2VMxcAHdMnvWBXorz9fj4j+VgJJRGtnL8qCO+A0m3Lh1ToeG+ByrhTF06NBKTI4TXjnUK3JwyVnALIaWjcOo6eIi6tX6gF/jpQZvF69lWt8I5dowfbWe8GrUT0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612403329275247.7110852045397; Wed, 3 Feb 2021 17:48:49 -0800 (PST) Received: from localhost ([::1]:34510 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7TlI-0006tE-24 for importer@patchew.org; Wed, 03 Feb 2021 20:48:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44144) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Ti1-0004YA-AC for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:25 -0500 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:42751) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Thz-0003YX-Ie for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:24 -0500 Received: by mail-pf1-x436.google.com with SMTP id w18so1063748pfu.9 for ; Wed, 03 Feb 2021 17:45:23 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xzKpOz1dnkvT+2F/uu8BRDtdRIBrUsrfNHwaFpPfXw4=; b=IhdIKzElpOv0lQMryl8M6dS4hOA9665UbHINzDX6dQgUWFLXpvS5GD+tAehApDxpQO CU5f5DpxEYOrUr+TePx40CTXMKbyN4Kkpk1O0toxJ8g7ivMjCb7GHUHjdkb6tJ4KZ3Te leb9UmzXh6XkwrJD3cTrKHYGCBxqTr4oyt5UwZGQw7ZFa3e8GH/gOk5C8B+hhjm0Y17A ijVWPoeZQYRYwY7zp/j9gVoLm5lfDLIQMZ3FicrGKW2LUub35SYTvQ96I1ikh0ddKq38 C8wdnppL2Nat+o2d44N0kLjbREAQ+MqNqUqBX39iEuTcsTDlPfqzDbynnzZyvvjLu6ag SHzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xzKpOz1dnkvT+2F/uu8BRDtdRIBrUsrfNHwaFpPfXw4=; b=EuEJAi2TaO6qxUUU45yVzIsernznU02KRw+o1PIdqvkWkyOtYWykduHwllQ2nVm/IV Wq+/k/V2lemab072q9kDD3usj7O2qRgBIqduH1eq6dsnQ9ebDtWimrcA6D04VXwN4FCe g//evMsRQDZOn6tUCYgyYWev8k0EpQJZfJufTUaubA2OGIe79OwKKuP7B3ufrj0WU3kn cgExEpDS9SU9i+yhx7wE4lBs0WGjoY++H/CQId3d5mLF+KZS4SLrkNmYKjt1hzyerR2H 2X7nnB4CaGgRjsnbUTZvyGvtBPSBJrM+fli+K3Yge/JvmAJZqx8RnrVx6jg356q63x7U ffvA== X-Gm-Message-State: AOAM5318ijGpNbuJpDm4OdFtHcp8TjKVWI+QgKuYLc2y3wA6Vi7pntuU P7Tufk5wwczq53Q1TXuU7mJRGTkbtBRldHnH X-Google-Smtp-Source: ABdhPJxwvaweb/4fJbJP45XD5TCp0I6Hipsui8x1MPQrj5l5/O9RJ0/xrIoTpLJ8berwbqiiOLzWqg== X-Received: by 2002:a05:6a00:1385:b029:1be:ac19:3a9d with SMTP id t5-20020a056a001385b02901beac193a9dmr5727605pfg.65.1612403122266; Wed, 03 Feb 2021 17:45:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 04/93] tcg: Manage splitwx in tc_ptr_to_region_tree by hand Date: Wed, 3 Feb 2021 15:43:40 -1000 Message-Id: <20210204014509.882821-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The use in tcg_tb_lookup is given a random pc that comes from the pc of a signal handler. Do not assert that the pointer is already within the code gen buffer at all, much less the writable mirror of it. Fixes: db0c51a3803 Signed-off-by: Richard Henderson --- For TCI, this indicates a bug in handle_cpu_signal, in that we are taking PC from the host signal frame. Which is, nearly, unrelated to TCI at all. The TCI "pc" is tci_tb_ptr (fixed in the next patch to at least be thread-local). We update this only on calls, since we don't expect SEGV during the interpretation loop. Which works ok for softmmu, in which we pass down pc by hand to the helpers, but is not ok for user-only, where we simply perform the raw memory operation. I don't know how to fix this, exactly. Probably by storing to tci_tb_ptr before each qemu_ld/qemu_st operation, with barriers. Then Doing the Right Thing in handle_cpu_signal. And perhaps by clearing tci_tb_ptr whenever we're not expecting a SEGV on behalf of the guest (and thus anything left is a qemu host bug). --- v2: Retain full struct initialization --- tcg/tcg.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index bbe3dcee03..2991112829 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -513,11 +513,21 @@ static void tcg_region_trees_init(void) } } =20 -static struct tcg_region_tree *tc_ptr_to_region_tree(const void *cp) +static struct tcg_region_tree *tc_ptr_to_region_tree(const void *p) { - void *p =3D tcg_splitwx_to_rw(cp); size_t region_idx; =20 + /* + * Like tcg_splitwx_to_rw, with no assert. The pc may come from + * a signal handler over which the caller has no control. + */ + if (!in_code_gen_buffer(p)) { + p -=3D tcg_splitwx_diff; + if (!in_code_gen_buffer(p)) { + return NULL; + } + } + if (p < region.start_aligned) { region_idx =3D 0; } else { @@ -536,6 +546,7 @@ void tcg_tb_insert(TranslationBlock *tb) { struct tcg_region_tree *rt =3D tc_ptr_to_region_tree(tb->tc.ptr); =20 + g_assert(rt !=3D NULL); qemu_mutex_lock(&rt->lock); g_tree_insert(rt->tree, &tb->tc, tb); qemu_mutex_unlock(&rt->lock); @@ -545,6 +556,7 @@ void tcg_tb_remove(TranslationBlock *tb) { struct tcg_region_tree *rt =3D tc_ptr_to_region_tree(tb->tc.ptr); =20 + g_assert(rt !=3D NULL); qemu_mutex_lock(&rt->lock); g_tree_remove(rt->tree, &tb->tc); qemu_mutex_unlock(&rt->lock); @@ -561,6 +573,10 @@ TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr) TranslationBlock *tb; struct tb_tc s =3D { .ptr =3D (void *)tc_ptr }; =20 + if (rt =3D=3D NULL) { + return NULL; + } + qemu_mutex_lock(&rt->lock); tb =3D g_tree_lookup(rt->tree, &s); qemu_mutex_unlock(&rt->lock); --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612403329; cv=none; d=zohomail.com; s=zohoarc; b=b5YNaWZuCOiZq4sYqxT6Tf5k6vnuV1QGqw+kqTMCX93fW3miTEF8kD26gekevDZ9UqNOIubUCdheMDZRDfmMjk/G43oVIhZV+cf1PE9DFCjZ+JQBpYw+9gQfQm7G+kdMTMJPEwpBOFimmnzJ+1n4sFgQ6ssWnYOTIWClKsPP3O0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612403329; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=V9K6psPZgkSjeT0TMBnqZlPYxPfyJCvKViKqKJxu0LY=; b=eBIRG5SG0theWTwgxjb7gsGDwhOPgt3YWJWrN+XGfJf3hqDxssNYg/Tz7+JbL10RFjAfRI9HYxIKpita8KD2/bWnHoK6xKF3Pj3hGgL34vecJvudjTKqndPz0c8IfeOl49PMz0uDzX1oukbiX3tw6VHIJ546RtA3MCp7+qyU7Qo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612403329580341.3174705659609; Wed, 3 Feb 2021 17:48:49 -0800 (PST) Received: from localhost ([::1]:34466 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7TlI-0006s5-9b for importer@patchew.org; Wed, 03 Feb 2021 20:48:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44184) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Ti6-0004cS-BS for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:35 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:35656) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Ti1-0003Ym-EO for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:30 -0500 Received: by mail-pj1-x102c.google.com with SMTP id e9so829693pjj.0 for ; Wed, 03 Feb 2021 17:45:24 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V9K6psPZgkSjeT0TMBnqZlPYxPfyJCvKViKqKJxu0LY=; b=uuIVQvvvSb6f8yb+XbcoE1ez4bzg77o2R+bPOvOsPZFrd8xitgjQ/eaWytDgX6R/55 2uTY/fPh/rdTdr8ajzUGWCcb90Ad5nRk5s7usl3RFG8DAZGJgWBdYWBArEEwAWdAdMOw 0X+7ThiJbQEe7SzMAtL0G4a/c+NuSRQtJ8oLWz3JHMyM9T+DmULo+ppdh10O6W5uVB9s 5hPrQHEM+VTjrLnmsMaVVUbjd7WP6ED9J+Rr3BhXvt0nLP37/GqYzU6WThepyrkKp/+f Iqxzh7ZhGC11M8yRns9LwzdA3S9py/T7dZPezyRmQu5SMdYFRifzEzmVSct51eT+xLSH CmvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V9K6psPZgkSjeT0TMBnqZlPYxPfyJCvKViKqKJxu0LY=; b=rEX6kfkyrC6D9H9N+4MRB5QBZ+OJiFS1NUHAX/3U8rgEAwKWh62UvHwWZGi9lIrTqJ kXnpRYwsuBCA15hUm41iU8SeuXy1YhtNr/vi2pwzn8hPB0ixNdVKTX+k7GUmQSW5bWcC gTdaAy7cNJBR/pomV6SLTDdSL0UoSmvatLvw5Lr83XPWuXOuHtFNL3P0KpMiRBc3JG+b LCaYOPmeN6hv1aXEO3CjUM7Slg0xsnSki5Iht/t3jFaRPKpB1+H1KvTx4Ymr7/IKIKjK dqqmyO8/ObqCaA18F1O6s/HFJFEiYiRzhdn74/PoMGbM8xPi64fi3neR1PhCVaDekUEB FN5Q== X-Gm-Message-State: AOAM531lFp5D8LvYHRcLGHwJ+GayVlhkfF0Ss/gjXRFJLUNq6Ip+ZSLa Mq4N72aUF3maLhJH/35Fn3efSWddmC7FtH3K X-Google-Smtp-Source: ABdhPJx2Hu6C4L74Qt6XqPcFtxwhL/jyo+lC5vtzZeTiBieEbO6pA4eQUCNgpNhKhQLlbUm4kFrs0Q== X-Received: by 2002:a17:903:1c3:b029:de:6b19:e72e with SMTP id e3-20020a17090301c3b02900de6b19e72emr5785243plh.63.1612403124015; Wed, 03 Feb 2021 17:45:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 05/93] tcg/tci: Make tci_tb_ptr thread-local Date: Wed, 3 Feb 2021 15:43:41 -1000 Message-Id: <20210204014509.882821-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Each thread must have its own pc, even under TCI. Remove the GETPC ifdef, because GETPC is always available for helpers, and thus is always required. Move the assignment under INDEX_op_call, because the value is only visible when we make a call to a helper function. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/exec/exec-all.h | 2 +- tcg/tcg-common.c | 4 ---- tcg/tci.c | 7 +++---- 3 files changed, 4 insertions(+), 9 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 125000bcf7..f933c74c44 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -544,7 +544,7 @@ void tb_set_jmp_target(TranslationBlock *tb, int n, uin= tptr_t addr); =20 /* GETPC is the true target of the return instruction that we'll execute. = */ #if defined(CONFIG_TCG_INTERPRETER) -extern uintptr_t tci_tb_ptr; +extern __thread uintptr_t tci_tb_ptr; # define GETPC() tci_tb_ptr #else # define GETPC() \ diff --git a/tcg/tcg-common.c b/tcg/tcg-common.c index 7e1992e79e..aa0c4f60c9 100644 --- a/tcg/tcg-common.c +++ b/tcg/tcg-common.c @@ -25,10 +25,6 @@ #include "qemu/osdep.h" #include "tcg/tcg.h" =20 -#if defined(CONFIG_TCG_INTERPRETER) -uintptr_t tci_tb_ptr; -#endif - TCGOpDef tcg_op_defs[] =3D { #define DEF(s, oargs, iargs, cargs, flags) \ { #s, oargs, iargs, cargs, iargs + oargs + cargs, flags }, diff --git a/tcg/tci.c b/tcg/tci.c index 3fc82d3c79..b3f9531a73 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,6 +57,8 @@ typedef uint64_t (*helper_function)(tcg_target_ulong, tcg= _target_ulong, tcg_target_ulong, tcg_target_ulong); #endif =20 +__thread uintptr_t tci_tb_ptr; + static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg = index) { tci_assert(index < TCG_TARGET_NB_REGS); @@ -526,16 +528,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #endif TCGMemOpIdx oi; =20 -#if defined(GETPC) - tci_tb_ptr =3D (uintptr_t)tb_ptr; -#endif - /* Skip opcode and size entry. */ tb_ptr +=3D 2; =20 switch (opc) { case INDEX_op_call: t0 =3D tci_read_ri(regs, &tb_ptr); + tci_tb_ptr =3D (uintptr_t)tb_ptr; #if TCG_TARGET_REG_BITS =3D=3D 32 tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), tci_read_reg(regs, TCG_REG_R1), --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612403490; cv=none; d=zohomail.com; s=zohoarc; b=Bi+CsYATkOXat8cvKLxGS0WICe8jXcErbvdDVmgBWtsaZlJU4LC7mSFHGJdq9fSboqaJVEwcoCYrOm/jgIUt4laITaTqNZlcHKPtZuyPoYyc2b+ZFK6el+rdRE1IbrzMO6LdGnWvgbUt6iPNe5ToeFVmsCTHBFHSxiD+rn9ldSg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612403490; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=onZUWhtxKDVzYiKYm4mcVALF5M4RSZvicSg1zN9qm0A=; b=UVSkB/TvIw3QJHs2rkHi64nYHn8HgQhrKtmIpl+Rk9jtv1o8uU9JjaQYlxoluaJDZMcwLd2Fo8dYC+N3TdfJSTF88Sqyfp7f5uQ0zBhO52BVeI89QIhaUums7KMUZCF1zt1oISbz7aSLPGrjQ7qZzVOXFKknv/VXYB2cDKxWpA0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161240349033969.37429647768693; Wed, 3 Feb 2021 17:51:30 -0800 (PST) Received: from localhost ([::1]:42820 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7Tnt-0001yS-8Z for importer@patchew.org; Wed, 03 Feb 2021 20:51:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44222) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7TiA-0004cl-15 for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:37 -0500 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:41211) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Ti4-0003Zs-7a for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:33 -0500 Received: by mail-pf1-x433.google.com with SMTP id q20so1061354pfu.8 for ; Wed, 03 Feb 2021 17:45:27 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=onZUWhtxKDVzYiKYm4mcVALF5M4RSZvicSg1zN9qm0A=; b=hBRwnBjJOGd90+PlG3cx3eV94tCTthP6l6BAbCd6MkTYms3dLPFhe3ZeeWzwboJXdM C06ztdWAeeXl5rVM0JZaxUrq/eg70N6hwcDQJ5JrUlDGqnuedca/rSIgvhwTQ9Rch2jU xDvyH651hvdCulacf7xtk3nqYqNd01xvhsQiNk9Dc8fK3bITPg5EwmE+vP4ywN+f45Ew ok9t8Clf6dOysDCZK4eb6RtSsbaJ18W8XN+5QxRn21ekaAVSOQwJFh/tBYvWTGZLAi/U ji7Ny6C53NbgJI/p7q03SEcbt79m2BKyLOXA5sNt6XOHJZZUbpU8//8A7u9D3Jkyr9Rd vSPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=onZUWhtxKDVzYiKYm4mcVALF5M4RSZvicSg1zN9qm0A=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Stefan Weil That TCG opcode is used by debian-buster (arm64) running ffmpeg: qemu-aarch64 /usr/bin/ffmpeg -i theora.mkv theora.webm Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reported-by: Alex Benn=C3=A9e Signed-off-by: Stefan Weil Message-Id: <20210128024814.2056958-1-sw@weilnetz.de> Signed-off-by: Richard Henderson --- tcg/tci.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tcg/tci.c b/tcg/tci.c index b3f9531a73..2ba97da189 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -615,7 +615,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, TODO(); break; case INDEX_op_ld16s_i32: - TODO(); + t0 =3D *tb_ptr++; + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_s32(&tb_ptr); + tci_write_reg(regs, t0, *(int16_t *)(t1 + t2)); break; case INDEX_op_ld_i32: t0 =3D *tb_ptr++; --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612403654; cv=none; d=zohomail.com; s=zohoarc; b=bo2lpBvSwdTHPY6LX0lGhhspJWUUGJE4udvtRyGbh9xN2heRc+gOzHWHY5uLm04VgKm63mS3fsy3yqNk6TxpolyBlWssPPdVREjPXVBmc1lYxuLfyxsCWsI0043y23QHSp0pknK0raB/9U0N7/ilQrCjPaNDNG91ROm27vWf90U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612403654; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Stefan Weil That TCG opcode is used by debian-buster (arm64) running ffmpeg: qemu-aarch64 /usr/bin/ffmpeg -i theora.mkv theora.webm Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reported-by: Alex Benn=C3=A9e Signed-off-by: Stefan Weil Message-Id: <20210128020425.2055454-1-sw@weilnetz.de> Signed-off-by: Richard Henderson --- tcg/tci.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tcg/tci.c b/tcg/tci.c index 2ba97da189..c3a8511dfe 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -883,7 +883,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2)); break; case INDEX_op_ld8s_i64: - TODO(); + t0 =3D *tb_ptr++; + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_s32(&tb_ptr); + tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); break; case INDEX_op_ld16u_i64: t0 =3D *tb_ptr++; --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612403884; cv=none; d=zohomail.com; s=zohoarc; b=bYVnmddu++vcjbAIBFhNbtonVoiE+e3ePiVVgJHYYEwvxpuixLwIrlFicHVXm7RqRSOK1PDg1c/v8jM4Nx6bY8YYKfY+X5EhgMbvRTb3baKtCkkhQ1uI4Uxo8Pkp0sSFY+t1QtP4adoKRszWVKviA/uT9n+fAf+bFTKdH5miAyY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612403884; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Tquh43lruzGWRcmOiBMYX1Wiqh+FHEpp7zn+YOCAYms=; b=Q7YCG5gBBR5dAENACZmZOp7ONIuHDlbayAnxtx6eFqMp9PaKBu+A9BpZuWWD4tm5Xk 6Oesllt3amJOwSlKjvXYL8mGBv/rKLqW/M12ovQxJ8dVtmwPCBqVzbDBet95y3t1i0mT wgW9QDIfAYPZI9pODbb/WPo1B5A3m900957ncFYf7a5+M7/tR6MCv7pmyMswuGzpI2V3 NwO4HLimCcKZ5ofNGmol34hNiv/nHtKxNvesjWylOm2zyIjQda/imjtDnNEWkyXcoMC0 e658QHjiPlBBrTLQiwaRe704aNr/7n9VJ+oqEcXARSalP3TaqU/6xzpa+t2mJx931NZO T73A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Tquh43lruzGWRcmOiBMYX1Wiqh+FHEpp7zn+YOCAYms=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index c3a8511dfe..e8023b5384 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -117,14 +117,6 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tc= g_target_ulong value) regs[index] =3D value; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -static void -tci_write_reg32s(tcg_target_ulong *regs, TCGReg index, int32_t value) -{ - tci_write_reg(regs, index, value); -} -#endif - static void tci_write_reg8(tcg_target_ulong *regs, TCGReg index, uint8_t v= alue) { tci_write_reg(regs, index, value); @@ -907,7 +899,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg32s(regs, t0, *(int32_t *)(t1 + t2)); + tci_write_reg(regs, t0, *(int32_t *)(t1 + t2)); break; case INDEX_op_ld_i64: t0 =3D *tb_ptr++; --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612403838; cv=none; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index e8023b5384..740244cc54 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -117,11 +117,6 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tc= g_target_ulong value) regs[index] =3D value; } =20 -static void tci_write_reg8(tcg_target_ulong *regs, TCGReg index, uint8_t v= alue) -{ - tci_write_reg(regs, index, value); -} - #if TCG_TARGET_REG_BITS =3D=3D 64 static void tci_write_reg16(tcg_target_ulong *regs, TCGReg index, uint16_t value) @@ -598,7 +593,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2)); + tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2)); break; case INDEX_op_ld8s_i32: TODO(); @@ -872,7 +867,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2)); + tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2)); break; case INDEX_op_ld8s_i64: t0 =3D *tb_ptr++; --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nVyouWDBw9IpYjnxIdxk6Lk2rEB7Cry5s6L8ndOAdHg=; b=NdoYMnjHmyQvM+j4L13WrO6BPZBj853ioYhDZGgZwFbt2clZ1HfMQQJ34JLljDJdJP 0CVJq83vxIS1kxftApmKxnkpxgobCc6FO1DKygYaELvcNrIy3cKyX42st+AgZGAmHnub JsYmBDshCn29rBwvRklehCBP5kSYJMmWaAXOq/1gc6Lxm+t/IB0eX64X0hEkmNL0Y9MJ wv531LFWGgZtBAr2fpvCxCLr7/8rvMbtcjj2n3fahcrPd8GvuaUUdM3rg3UMFN1GqSSf E8WYapmRc6qduRWQ/ux+f13XeYZXYqBMqdGctMQNn9B+XCcylzP1h+ECOopPzVc101NI C9OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nVyouWDBw9IpYjnxIdxk6Lk2rEB7Cry5s6L8ndOAdHg=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 740244cc54..005d2946c4 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -117,14 +117,6 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tc= g_target_ulong value) regs[index] =3D value; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -static void -tci_write_reg16(tcg_target_ulong *regs, TCGReg index, uint16_t value) -{ - tci_write_reg(regs, index, value); -} -#endif - static void tci_write_reg32(tcg_target_ulong *regs, TCGReg index, uint32_t value) { @@ -879,7 +871,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg16(regs, t0, *(uint16_t *)(t1 + t2)); + tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2)); break; case INDEX_op_ld16s_i64: TODO(); --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612403656; cv=none; d=zohomail.com; s=zohoarc; b=HP7ombRBQnfCaoxxACuY8FGNlU5t6DlxhIbK+y7+ED3fQbVDUw4ZgZjV5p59WiIs/Pk7ASDEdkbXVvqEkFWHla5l01rg4iCjLvRyOBLa9Hy+MnMUkJj1hlJASkiPWGk+UEQZ91C+aImFCspXatauJBwEHtI7Au8toK4TmCimv+Q= ARC-Message-Signature: i=1; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WvF+amzq1Ily9oj+9g5vZaVj1S2ujChoxYC/fno/cGA=; b=VefMLW0RzdlXgxXLhstmgppJN7lToGqgdjD63svg2OleeE7WJWwYht90Yqm36wPqbC FkI/GGW8DPAtGW/r3bfeN2XupMmB9aQr/p6zv9KtD9uPp/2fd20//IwsOnJZ3dgi7oMx HFkiYaumOLRpBvZAt9YaXnTYsH9dlSE9a3oO+GldDKtxlV3lAQyUEA0ktdFhH3V9KOmM 4KxPYK/A5MAJ/DQNerYzkw0m36S6HJ5B06TZ0kYfb6/egRXywBaayUpfIav0vIkdufYX 7l1r93N8AIvkf3fnMIVadNUzCLeE9XSjZVcpLsIjTsdx7OzWc8Iff+Ci/VP24bZXuUw0 ubrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WvF+amzq1Ily9oj+9g5vZaVj1S2ujChoxYC/fno/cGA=; b=BdJpI/jqx6aJWKT0KCublf1mc8EBpCsFi8FebmDuKbR8ogTzLtVSoGbEvbOdynEksu x1yijUljtp40CqJh406PF9oMmJw5/PGV1gCOKH3fS4T0LBxczxuUjRCvztc6mJKf9i2t VlTUld6Tipt99GPhTAqbgax2RdnTYLUg761QUFDxAs16ko68bDmuDXw5kZ9JoE4+RR+e 34SKbVbjFpMNb8HonM1jedrbCIIII6NQV7EM0y4tq+am62w0M1tAX/FqKzkepLuFpzqL PUQ/ef/6kmmNYnU+b5yc1N854O0DoZZ61my4Tg5n/XihXY5ghMgAzfKbIxXX7Ze7++hn Ysgw== X-Gm-Message-State: AOAM533AWbp6ocIOJb7v1InrYQva3BdBfM6Tq/nKP550TtmwgRvQyIdd vR5hnVTvFyCR6beP92WowSJDtb8my/dzgv/B X-Google-Smtp-Source: ABdhPJzav12R3/Nwq8D26Zyt92jfIyhDjVn0O16zjiySQiFt2A0VJmZ3cq2asZhpAcCuNfx9JtA9Zg== X-Received: by 2002:a17:902:ce8b:b029:e2:9905:db5a with SMTP id f11-20020a170902ce8bb02900e29905db5amr2598380plg.77.1612403135156; Wed, 03 Feb 2021 17:45:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 11/93] tcg/tci: Inline tci_write_reg32 into all callers Date: Wed, 3 Feb 2021 15:43:47 -1000 Message-Id: <20210204014509.882821-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) For a 64-bit TCI, the upper bits of a 32-bit operation are undefined (much like a native ppc64 32-bit operation). It simplifies everything if we don't force-extend the result. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci.c | 66 +++++++++++++++++++++++++------------------------------ 1 file changed, 30 insertions(+), 36 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 005d2946c4..39ad00663f 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -117,12 +117,6 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tc= g_target_ulong value) regs[index] =3D value; } =20 -static void -tci_write_reg32(tcg_target_ulong *regs, TCGReg index, uint32_t value) -{ - tci_write_reg(regs, index, value); -} - #if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, uint32_t low_index, uint64_t value) @@ -549,7 +543,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t1 =3D tci_read_r32(regs, &tb_ptr); t2 =3D tci_read_ri32(regs, &tb_ptr); condition =3D *tb_ptr++; - tci_write_reg32(regs, t0, tci_compare32(t1, t2, condition)); + tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: @@ -557,7 +551,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tmp64 =3D tci_read_r64(regs, &tb_ptr); v64 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; - tci_write_reg32(regs, t0, tci_compare64(tmp64, v64, condition)= ); + tci_write_reg(regs, t0, tci_compare64(tmp64, v64, condition)); break; #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: @@ -571,12 +565,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, case INDEX_op_mov_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg32(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_i32(&tb_ptr); - tci_write_reg32(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; =20 /* Load/store operations (32 bit). */ @@ -603,7 +597,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg32(regs, t0, *(uint32_t *)(t1 + t2)); + tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); break; case INDEX_op_st8_i32: t0 =3D tci_read_r8(regs, &tb_ptr); @@ -631,44 +625,44 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, t0 =3D *tb_ptr++; t1 =3D tci_read_ri32(regs, &tb_ptr); t2 =3D tci_read_ri32(regs, &tb_ptr); - tci_write_reg32(regs, t0, t1 + t2); + tci_write_reg(regs, t0, t1 + t2); break; case INDEX_op_sub_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_ri32(regs, &tb_ptr); t2 =3D tci_read_ri32(regs, &tb_ptr); - tci_write_reg32(regs, t0, t1 - t2); + tci_write_reg(regs, t0, t1 - t2); break; case INDEX_op_mul_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_ri32(regs, &tb_ptr); t2 =3D tci_read_ri32(regs, &tb_ptr); - tci_write_reg32(regs, t0, t1 * t2); + tci_write_reg(regs, t0, t1 * t2); break; #if TCG_TARGET_HAS_div_i32 case INDEX_op_div_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_ri32(regs, &tb_ptr); t2 =3D tci_read_ri32(regs, &tb_ptr); - tci_write_reg32(regs, t0, (int32_t)t1 / (int32_t)t2); + tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); break; case INDEX_op_divu_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_ri32(regs, &tb_ptr); t2 =3D tci_read_ri32(regs, &tb_ptr); - tci_write_reg32(regs, t0, t1 / t2); + tci_write_reg(regs, t0, t1 / t2); break; case INDEX_op_rem_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_ri32(regs, &tb_ptr); t2 =3D tci_read_ri32(regs, &tb_ptr); - tci_write_reg32(regs, t0, (int32_t)t1 % (int32_t)t2); + tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); break; case INDEX_op_remu_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_ri32(regs, &tb_ptr); t2 =3D tci_read_ri32(regs, &tb_ptr); - tci_write_reg32(regs, t0, t1 % t2); + tci_write_reg(regs, t0, t1 % t2); break; #elif TCG_TARGET_HAS_div2_i32 case INDEX_op_div2_i32: @@ -680,19 +674,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, t0 =3D *tb_ptr++; t1 =3D tci_read_ri32(regs, &tb_ptr); t2 =3D tci_read_ri32(regs, &tb_ptr); - tci_write_reg32(regs, t0, t1 & t2); + tci_write_reg(regs, t0, t1 & t2); break; case INDEX_op_or_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_ri32(regs, &tb_ptr); t2 =3D tci_read_ri32(regs, &tb_ptr); - tci_write_reg32(regs, t0, t1 | t2); + tci_write_reg(regs, t0, t1 | t2); break; case INDEX_op_xor_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_ri32(regs, &tb_ptr); t2 =3D tci_read_ri32(regs, &tb_ptr); - tci_write_reg32(regs, t0, t1 ^ t2); + tci_write_reg(regs, t0, t1 ^ t2); break; =20 /* Shift/rotate operations (32 bit). */ @@ -701,32 +695,32 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, t0 =3D *tb_ptr++; t1 =3D tci_read_ri32(regs, &tb_ptr); t2 =3D tci_read_ri32(regs, &tb_ptr); - tci_write_reg32(regs, t0, t1 << (t2 & 31)); + tci_write_reg(regs, t0, t1 << (t2 & 31)); break; case INDEX_op_shr_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_ri32(regs, &tb_ptr); t2 =3D tci_read_ri32(regs, &tb_ptr); - tci_write_reg32(regs, t0, t1 >> (t2 & 31)); + tci_write_reg(regs, t0, t1 >> (t2 & 31)); break; case INDEX_op_sar_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_ri32(regs, &tb_ptr); t2 =3D tci_read_ri32(regs, &tb_ptr); - tci_write_reg32(regs, t0, ((int32_t)t1 >> (t2 & 31))); + tci_write_reg(regs, t0, ((int32_t)t1 >> (t2 & 31))); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_ri32(regs, &tb_ptr); t2 =3D tci_read_ri32(regs, &tb_ptr); - tci_write_reg32(regs, t0, rol32(t1, t2 & 31)); + tci_write_reg(regs, t0, rol32(t1, t2 & 31)); break; case INDEX_op_rotr_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_ri32(regs, &tb_ptr); t2 =3D tci_read_ri32(regs, &tb_ptr); - tci_write_reg32(regs, t0, ror32(t1, t2 & 31)); + tci_write_reg(regs, t0, ror32(t1, t2 & 31)); break; #endif #if TCG_TARGET_HAS_deposit_i32 @@ -737,7 +731,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp32 =3D (((1 << tmp8) - 1) << tmp16); - tci_write_reg32(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp= 32)); + tci_write_reg(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32= )); break; #endif case INDEX_op_brcond_i32: @@ -789,56 +783,56 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, case INDEX_op_ext8s_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_r8s(regs, &tb_ptr); - tci_write_reg32(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 case INDEX_op_ext16s_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_r16s(regs, &tb_ptr); - tci_write_reg32(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext8u_i32 case INDEX_op_ext8u_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_r8(regs, &tb_ptr); - tci_write_reg32(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16u_i32 case INDEX_op_ext16u_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_r16(regs, &tb_ptr); - tci_write_reg32(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_bswap16_i32 case INDEX_op_bswap16_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_r16(regs, &tb_ptr); - tci_write_reg32(regs, t0, bswap16(t1)); + tci_write_reg(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i32 case INDEX_op_bswap32_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg32(regs, t0, bswap32(t1)); + tci_write_reg(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_not_i32 case INDEX_op_not_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg32(regs, t0, ~t1); + tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i32 case INDEX_op_neg_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg32(regs, t0, -t1); + tci_write_reg(regs, t0, -t1); break; #endif #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -880,7 +874,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg32(regs, t0, *(uint32_t *)(t1 + t2)); + tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); break; case INDEX_op_ld32s_i64: t0 =3D *tb_ptr++; --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3gzoTh/DnzHssC7cCFW1QEczWz5vWhlHn8h/Weu1Sj0=; b=WXWBfUmPVVByWsLl+iNeHXF0Cdpw08A7JRafkgQdq14yBdkrvSwiLHdQ5SrhKMEKfp JN/XlFJcqzynKJr49xnZpQAjkxPdUFJxzWa8qekz8J/ML+9AZOw1I0dCmCwpeqcSIlWL QVZSU4HVkmQ1OVcJjEnEGqmbJMyhY/0quWV4wDGCaQHeuz63IQnINF+SkCI9LmpQwmMj F72TAn+N4+lK020etKDkH73RU5Ia9E1WPc+3YJ+x7XzZmZV57dChUbgfD09GqR2xu8ts 7AsuehLgc2+Pntr/tWdtZe3mEzjx6xhkhevzrx8JIAAcnvMth2UXfCCX25GUjROj+144 TLSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3gzoTh/DnzHssC7cCFW1QEczWz5vWhlHn8h/Weu1Sj0=; b=J6pJTriFX0K/GaWMg4eLmU4fd5+rYa6d220ipTaGRi0Q+veOdX4ApYHCtaPyh07+st tpXDjGSss+jJQgE/9DrE1fHXk7YM6z9W4amZmQ6cWTZxOj/YLALXlxDNzWWwzXtzTaXf 8+nsnAIJZXs8dBOJi/gP81kdZVcW9/S6w+CBafZ/jV8MWbHwtmXSIfZJnBJvvHwXZxPc N4TqnuHjH5/aZcaT4y1sb+T3wTUrFVzNf+GWxnPUHY0Ssr1JQuhXaYRjtljhkoMPiRta 6vP4lAxkVN8xzCkqgwbQ7j4x8uWhxv8PfCe+XJzkK8vlO+2HXLC5kDrAQksPZVG6/ljA 8W5Q== X-Gm-Message-State: AOAM530+pxo6+SEMq4P9W/n0gRZZtLWCSFPWco01s2uXMcHqq5vhgnnY 5FPoAsIIieIon9Vu8cONHbAPx3QsBGSB5qA5 X-Google-Smtp-Source: ABdhPJzDtkYYMZI3pk5KgHnsouu03cOC/WAUwjuM+jr5Lci7Q9eEPdq8ChNQwrMcju61BQGZVrYCWQ== X-Received: by 2002:a62:190d:0:b029:1bd:e11c:4eff with SMTP id 13-20020a62190d0000b02901bde11c4effmr5932336pfz.22.1612403137321; Wed, 03 Feb 2021 17:45:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 12/93] tcg/tci: Inline tci_write_reg64 into 64-bit callers Date: Wed, 3 Feb 2021 15:43:48 -1000 Message-Id: <20210204014509.882821-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Note that we had two functions of the same name: a 32-bit version which took two register numbers and a 64-bit version which was a no-op wrapper for tcg_write_reg. After this, we are left with only the 32-bit version. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci.c | 60 +++++++++++++++++++++++++------------------------------ 1 file changed, 27 insertions(+), 33 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 39ad00663f..0f56702b93 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -124,12 +124,6 @@ static void tci_write_reg64(tcg_target_ulong *regs, ui= nt32_t high_index, tci_write_reg(regs, low_index, value); tci_write_reg(regs, high_index, value >> 32); } -#elif TCG_TARGET_REG_BITS =3D=3D 64 -static void -tci_write_reg64(tcg_target_ulong *regs, TCGReg index, uint64_t value) -{ - tci_write_reg(regs, index, value); -} #endif =20 #if TCG_TARGET_REG_BITS =3D=3D 32 @@ -559,7 +553,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t1 =3D tci_read_r64(regs, &tb_ptr); t2 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; - tci_write_reg64(regs, t0, tci_compare64(t1, t2, condition)); + tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; #endif case INDEX_op_mov_i32: @@ -839,12 +833,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, case INDEX_op_mov_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r64(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_i64(&tb_ptr); - tci_write_reg64(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; =20 /* Load/store operations (64 bit). */ @@ -886,7 +880,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg64(regs, t0, *(uint64_t *)(t1 + t2)); + tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st8_i64: t0 =3D tci_read_r8(regs, &tb_ptr); @@ -920,19 +914,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, t0 =3D *tb_ptr++; t1 =3D tci_read_ri64(regs, &tb_ptr); t2 =3D tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1 + t2); + tci_write_reg(regs, t0, t1 + t2); break; case INDEX_op_sub_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_ri64(regs, &tb_ptr); t2 =3D tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1 - t2); + tci_write_reg(regs, t0, t1 - t2); break; case INDEX_op_mul_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_ri64(regs, &tb_ptr); t2 =3D tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1 * t2); + tci_write_reg(regs, t0, t1 * t2); break; #if TCG_TARGET_HAS_div_i64 case INDEX_op_div_i64: @@ -951,19 +945,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, t0 =3D *tb_ptr++; t1 =3D tci_read_ri64(regs, &tb_ptr); t2 =3D tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1 & t2); + tci_write_reg(regs, t0, t1 & t2); break; case INDEX_op_or_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_ri64(regs, &tb_ptr); t2 =3D tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1 | t2); + tci_write_reg(regs, t0, t1 | t2); break; case INDEX_op_xor_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_ri64(regs, &tb_ptr); t2 =3D tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1 ^ t2); + tci_write_reg(regs, t0, t1 ^ t2); break; =20 /* Shift/rotate operations (64 bit). */ @@ -972,32 +966,32 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, t0 =3D *tb_ptr++; t1 =3D tci_read_ri64(regs, &tb_ptr); t2 =3D tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1 << (t2 & 63)); + tci_write_reg(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_ri64(regs, &tb_ptr); t2 =3D tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1 >> (t2 & 63)); + tci_write_reg(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_ri64(regs, &tb_ptr); t2 =3D tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, ((int64_t)t1 >> (t2 & 63))); + tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_ri64(regs, &tb_ptr); t2 =3D tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, rol64(t1, t2 & 63)); + tci_write_reg(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_ri64(regs, &tb_ptr); t2 =3D tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, ror64(t1, t2 & 63)); + tci_write_reg(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 @@ -1008,7 +1002,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp64 =3D (((1ULL << tmp8) - 1) << tmp16); - tci_write_reg64(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp= 64)); + tci_write_reg(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64= )); break; #endif case INDEX_op_brcond_i64: @@ -1026,28 +1020,28 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArch= State *env, case INDEX_op_ext8u_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r8(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext8s_i64 case INDEX_op_ext8s_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r8s(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16s_i64 case INDEX_op_ext16s_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r16s(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16u_i64 case INDEX_op_ext16u_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r16(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext32s_i64 @@ -1056,7 +1050,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, case INDEX_op_ext_i32_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r32s(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; #if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: @@ -1064,41 +1058,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArch= State *env, case INDEX_op_extu_i32_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; #if TCG_TARGET_HAS_bswap16_i64 case INDEX_op_bswap16_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r16(regs, &tb_ptr); - tci_write_reg64(regs, t0, bswap16(t1)); + tci_write_reg(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i64 case INDEX_op_bswap32_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg64(regs, t0, bswap32(t1)); + tci_write_reg(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r64(regs, &tb_ptr); - tci_write_reg64(regs, t0, bswap64(t1)); + tci_write_reg(regs, t0, bswap64(t1)); break; #endif #if TCG_TARGET_HAS_not_i64 case INDEX_op_not_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r64(regs, &tb_ptr); - tci_write_reg64(regs, t0, ~t1); + tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i64 case INDEX_op_neg_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r64(regs, &tb_ptr); - tci_write_reg64(regs, t0, -t1); + tci_write_reg(regs, t0, -t1); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 0f56702b93..7e108bcbb3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -455,6 +455,18 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TC= GCond condition) # define qemu_st_beq(X) stq_be_p(g2h(taddr), X) #endif =20 +#if TCG_TARGET_REG_BITS =3D=3D 64 +# define CASE_32_64(x) \ + case glue(glue(INDEX_op_, x), _i64): \ + case glue(glue(INDEX_op_, x), _i32): +# define CASE_64(x) \ + case glue(glue(INDEX_op_, x), _i64): +#else +# define CASE_32_64(x) \ + case glue(glue(INDEX_op_, x), _i32): +# define CASE_64(x) +#endif + /* Interpret pseudo code in tb. */ /* * Disable CFI checks. @@ -569,7 +581,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, =20 /* Load/store operations (32 bit). */ =20 - case INDEX_op_ld8u_i32: + CASE_32_64(ld8u) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); @@ -843,12 +855,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, =20 /* Load/store operations (64 bit). */ =20 - case INDEX_op_ld8u_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2)); - break; case INDEX_op_ld8s_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404099; cv=none; d=zohomail.com; s=zohoarc; b=O/tVVfdG6ofVgbCkX44uO9Id/WCCT/J+75yTZu9l+TIo+hphhEOb6rkm5mSyDYUL5d6QYG9LBcVD50L+Q2myCqBne9wedIbFwrg4fLw0U8XRkCQljSfq9piXyQ5lVT1VkP1sRQsaMuuFCm9jg5AQs438Wje2HKs2QwxESxhvgWo= ARC-Message-Signature: i=1; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ivQ6CdRm/OXUCJL48bE6dU1klkzWgC1aTXX7CV1kiyA=; b=UfBjul+bPBIcX1icEoskim/EySeIf6QRnYqdF0wZkPkYOsYrd/H5PrhNdAeDC9QwBH +/cDEenkgymVPJPn1S31zK/tMJBMALlkMCnEfQPEyMips5daxoNNOKR+lDgU5wNJCXyE TnJkWexxAB2xALsASLcDM87TbhGEqsqQXndP9OpEu8JM1RHlV2Ln9BzXZdGoMpzuR12R 0G5s7P3SIXFjLn8V35gpsOnEypZ5Zvcsl08Ltt/JZuIUB8IoV3yyz1UolqIMbWQl/FPe WK9y5UYMrx1L+xk6dAF0A8tRYuVr0OlrzObEVt4uYx2/AZ6DGIQhmHvzt0Pe50UVWsff xeOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ivQ6CdRm/OXUCJL48bE6dU1klkzWgC1aTXX7CV1kiyA=; b=bdrKMm2mMjN3+dPh+Opup97yh4qS0dssEZ3lk+LLHBQF14K/HeLaVCDEHTy0+NXOGI agTCRL1fKigltLk+E7Z1DW+w9DdFopUDlY1ffBCVkMytl3KgPw7UO8l7YRo2jYE/VlTn oPXG3hwGnHbzBYd/3/S3Ojq39HiFbbSNkxgTtgcsz+GNDQf2uh6zvj0qWqJBBJOtv1uR 4OttojLYPshAomlCx7ncLSk2RRmYzHZ/IE71Pc9VqPHpesoq+SnCYn2AJcQypw25NIl7 PZ58zvlS2lUQuk9yWmpknIO/nJCePaOvzxI861w3dvObTsGPEr/W7nWCTPWdDUF0mebk hZ2g== X-Gm-Message-State: AOAM5317nAOXMtH5QdrT3LZC5twYs/Cs336fOPQzKsFTo2mvyLV+BlJ0 sr4HpUSN/CpS+qyDni0hZrrP9SCC6uzqMAZe X-Google-Smtp-Source: ABdhPJzB3I9Ft8MWUPdwyh1aPSLhDl5EDPikr0kF/lU+UFtfowQeWfjcd/brGoeJFiG6S/96gQfMJQ== X-Received: by 2002:a17:902:724c:b029:e1:4aae:c72 with SMTP id c12-20020a170902724cb02900e14aae0c72mr5743828pll.81.1612403140657; Wed, 03 Feb 2021 17:45:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 14/93] tcg/tci: Merge INDEX_op_ld8s_{i32,i64} Date: Wed, 3 Feb 2021 15:43:50 -1000 Message-Id: <20210204014509.882821-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Eliminating a TODO for ld8s_i32. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 7e108bcbb3..c31be1a1f4 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -587,8 +587,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2)); break; - case INDEX_op_ld8s_i32: - TODO(); + CASE_32_64(ld8s) + t0 =3D *tb_ptr++; + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_s32(&tb_ptr); + tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); break; case INDEX_op_ld16u_i32: TODO(); @@ -855,12 +858,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, =20 /* Load/store operations (64 bit). */ =20 - case INDEX_op_ld8s_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); - break; case INDEX_op_ld16u_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612403658; cv=none; d=zohomail.com; s=zohoarc; b=ViQMQduJCphx2F72JV2Kz7rjha0JYjUaRK+aMLFuG729/mAGtysrt/+oRFJ43pNbgX2fHIdwIGe6N7BjHFn80o7pZ+IVwiO6iEwqOZK/UBGozKEYkdN4elJHsDk/bjKIDB5LvIf4ewpSphzbSwSQ1cNcARo83aqexFaNrp8Z+r8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612403658; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SP+dSNoCSW/u6ABPE/2oquCEK8adb2mItiXQWA/oP48=; b=UY6IDB6ohkcspoCXCXxZrbyNsW0vJsiVZ3Q5bHI55kl+cvkuH41J9yHGXfdElnyWSavRDC3GVTEJGwzbcCa8X92t7N6a+N3KHsGqcs6KqXvh1IAxtjztcGDUHIShEzLgZvl+G4Xi3q3Lronq7XMdHXnDNRAObHKmau+4xpfipbc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612403658449539.7408653084104; Wed, 3 Feb 2021 17:54:18 -0800 (PST) Received: from localhost ([::1]:51854 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7Tqb-0005l8-DU for importer@patchew.org; Wed, 03 Feb 2021 20:54:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44344) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7TiN-0004k4-7K for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:47 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:45516) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7TiL-0003jB-BL for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:46 -0500 Received: by mail-pl1-x633.google.com with SMTP id b8so869457plh.12 for ; Wed, 03 Feb 2021 17:45:43 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SP+dSNoCSW/u6ABPE/2oquCEK8adb2mItiXQWA/oP48=; b=rIVz8A2Q3OkvbEYRbfC5vbM4owPmPE7eX6sTZfu5/YAExfsSh5qfcqNWcyNi2VFU6h dyvjOUTYsNO9LMnkwbTygoww44tpkqXnQZC4l3sLGrk8giD2C9tzG/eKZNGV9SlnD/rB bvjsd1mbmoetK2dK+KO6HGEgGHA5/pmJvPVGQVAo9cW5P8wBg28gHu+YP8OFNcmW4ipq 3kHJfrNT/iVZlLv5Q9X2ByKOWU016YhGRmjIGWwlw+HL/FfFDOdoskKZ8kgbsbr4kqRL Ke0TtIjA65dPHOK/Y9KH42YVSn0f+qqboqGweU2KOJcCY+OY52b3hzlhTGpTx7MRjZLB HCPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SP+dSNoCSW/u6ABPE/2oquCEK8adb2mItiXQWA/oP48=; b=qCuf2priFhq18tiNleo2r4YV2LRl2yJrOSnmp8IHYbZSjuSq0LUlYoxTxx6fvNTvJC dYcm5UkIXmTfkqm+deWsZLB2ug82J7O35VYo2+9wJoZaNGKkj/XKP/DNydG81P5RECh5 rnfJwA8Sk+2xYlQJ4cTjGlEzhXgUTKFJmX5Flj2t5nNVPSKTutC9Vr9hub3aYbIr6Aeh Bwkzll6aMfAJ0rccqzbZP4Q8c1InOGw246ORpM+366CjAMxcwUTtyoOQYXBsxXeFacm6 +B3zJK81IvLIsnZ3iMny6NYsr+2rCPk4KMuAGDKCbRScTzjZGHjYSPrsROClNxKeHsPW pM0g== X-Gm-Message-State: AOAM530PnrU/gzqe9lEAMBqfv5thmA8lEoCaG8wIMsF97NqvR5lR9QBR bMJH4YE9kAojiK3hdbB5aflJ70zRT4PZUfRM X-Google-Smtp-Source: ABdhPJwW2qiSZLUtqIiaMuQN3AACNiT8TiEA/z23UAEoJl29PN5+LTKU2wKDxie++TlXSYl8Mc/0mA== X-Received: by 2002:a17:90a:4dc5:: with SMTP id r5mr5846098pjl.114.1612403142387; Wed, 03 Feb 2021 17:45:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 15/93] tcg/tci: Merge INDEX_op_ld16u_{i32,i64} Date: Wed, 3 Feb 2021 15:43:51 -1000 Message-Id: <20210204014509.882821-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Eliminating a TODO for ld16u_i32. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index c31be1a1f4..b64d611ec9 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -593,8 +593,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); break; - case INDEX_op_ld16u_i32: - TODO(); + CASE_32_64(ld16u) + t0 =3D *tb_ptr++; + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_s32(&tb_ptr); + tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2)); break; case INDEX_op_ld16s_i32: t0 =3D *tb_ptr++; @@ -858,12 +861,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, =20 /* Load/store operations (64 bit). */ =20 - case INDEX_op_ld16u_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2)); - break; case INDEX_op_ld16s_i64: TODO(); break; --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404046; cv=none; d=zohomail.com; s=zohoarc; b=cc486zY27Zyt4tcWfdsQosNk2HluDyBctERrwL5ufMKtdER4aPTfF3yx9TnZpc8u2gzVcNE7nkT1II0UoRS/5x8hOCU+SX6KzWI1WzEc9Wot82rK5fac1acHXiOkWgdJwId/SMjLEQT7ksUMp9EObjkON9X97FQiHy8iaVxEj+w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612404046; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ILdwR5pcSGw7723xZ1U2bA9/JhsnvGlthCTDNdPrhhQ=; b=b44dXRKQpbqw1VXFkiR0jcs7wuC8rcBR01qF7DJpzZ5iU+LfOKoy/SBL8NB/oxZUZQ79ll2MbLeHROCkyPmbxai3jbb8syPpp4lNkcbsNpcuCRhaMRL71hriUHeXdB4RNT+cLbJpZYnMwStWh+XRezflUYUNKCJrnKPgUYRrA3Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612404046969710.5162288839438; Wed, 3 Feb 2021 18:00:46 -0800 (PST) Received: from localhost ([::1]:40690 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7Twr-0004Qk-Oe for importer@patchew.org; Wed, 03 Feb 2021 21:00:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44352) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7TiN-0004l2-Me for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:49 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:42495) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7TiL-0003k8-Ct for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:47 -0500 Received: by mail-pl1-x633.google.com with SMTP id s15so878014plr.9 for ; Wed, 03 Feb 2021 17:45:44 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ILdwR5pcSGw7723xZ1U2bA9/JhsnvGlthCTDNdPrhhQ=; b=oozajDP2aARzt/Jp5h4z5+b4IwyfwMOpvRz0yvq61ZmHFhVhMydHUYUghXwINtwm6k 8Fc+zwIie81G7+2UoiXV8EX0oex++Z0ZsL2yB1CxOjHKNa3ePrYYzVdLHgQ1ShoOKaaP DyQXELBkLSIl9jXj36mVDiDxAwMI9epeiEUzROcEabSWX+bee2zyAIzBEee9oyWvlDnC z+1Dj4/FzC56DXDnksW4WebP6tGQgxxh9atPT8r3XPJkWU2BocOd3/A58wMdsApmvcPR 17rwR6a36fUAMLKp0YL2ioBOAx7fiSwYE3C2n6MAPFJjesTpoa9bwiFNVioTKDBbzXlD n2jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ILdwR5pcSGw7723xZ1U2bA9/JhsnvGlthCTDNdPrhhQ=; b=n6Ibav+Jnxn5/zFkU1yLFT1T1jzIW8xJzxwJE7gV8jSXqOReP/kKfCHqT5Q9G7Upv7 wg7mt1bvagSzq1F0Oyr1CpEMA27k/t+ch9hjNMxrWi6PrSQHR67hHEXmojPmk6zOkHWC DyvbalFR/A+Os1OM1uD3fvBSz5p+HdIjuA2LQ9rsnK0MsoHt1QaBkT2omX0OpGWIgAKx sx8AVdCX9fVZ/5HF7i2xqiD/ktv0Fnc0zN+ZYt161PPrk8xAEb4fyxULj7eEjphMttK8 VLtB8YXIMbXga4ThC7Q/nDSlaoOKLyoBiyOXNnydKreI8c6/8TEVxMdA/cZ85LtYp5q/ VKGg== X-Gm-Message-State: AOAM533sMRVCCh+tgrPuhW3kKT31MUmMmgZPI9LdMpSgZA8PfC4mMRGY iD9kiSyIPwlOo0eAYMgdL0J+kin0m0AfBDtO X-Google-Smtp-Source: ABdhPJz32IvJS924JiN2Oc4GzLGkCZ2GT1RRPX6SgjwHaK2ZvPUwRNl6XDOdNXqaEXlXIYCSlx5pQg== X-Received: by 2002:a17:90b:23c2:: with SMTP id md2mr5842366pjb.222.1612403143889; Wed, 03 Feb 2021 17:45:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 16/93] tcg/tci: Merge INDEX_op_ld16s_{i32,i64} Date: Wed, 3 Feb 2021 15:43:52 -1000 Message-Id: <20210204014509.882821-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Eliminating a TODO for ld16s_i64. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index b64d611ec9..259a8538bf 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -599,7 +599,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2)); break; - case INDEX_op_ld16s_i32: + CASE_32_64(ld16s) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); @@ -861,9 +861,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, =20 /* Load/store operations (64 bit). */ =20 - case INDEX_op_ld16s_i64: - TODO(); - break; case INDEX_op_ld32u_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404181; cv=none; d=zohomail.com; s=zohoarc; b=ZlBnQ3MSTuKdm7g/USfkhU21M5DEmfM14nTWHWrIYjEPAMMbtXZUMMaisfZRVqbZRin0jPZvNZZzO/hQT+fWuW83aWd5Ckd3zf+s5AqlMBPS0+qRJVlQDSWNlK8leVhKXcmx47prQ1f5MaEOfE/w/U/CfZnOvpWT2tH5Zbg7rak= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612404181; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iY5vh2fyihhpXHBTL1OAa7t0Sts/YD95jy25p+z4l7A=; b=YiNM1CzPhhFeba1CRphy+0RO7OOPYGEfi5EC7zccZn4el42KR5DQe6DykbyqBSDwxdBUZe0neHrHOi1mjEcXo5N07+rRvZnR76pbNM8CRBWenHDNg+SzrGXHtpFjZFphOClhv3eHf1V2gm3B+18KzX+IUhDhGn8L/4LaBqP/8VQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612404181141285.3122642434937; Wed, 3 Feb 2021 18:03:01 -0800 (PST) Received: from localhost ([::1]:49330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7Tz2-00086y-0V for importer@patchew.org; Wed, 03 Feb 2021 21:03:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44372) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7TiO-0004li-H1 for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:49 -0500 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:41599) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7TiM-0003ly-TR for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:48 -0500 Received: by mail-pg1-x536.google.com with SMTP id i7so1022761pgc.8 for ; Wed, 03 Feb 2021 17:45:46 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 259a8538bf..55863f76a7 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -606,6 +606,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_write_reg(regs, t0, *(int16_t *)(t1 + t2)); break; case INDEX_op_ld_i32: + CASE_64(ld32u) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); @@ -861,12 +862,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, =20 /* Load/store operations (64 bit). */ =20 - case INDEX_op_ld32u_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); - break; case INDEX_op_ld32s_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404297; cv=none; d=zohomail.com; s=zohoarc; b=Z3tS0qMM4exMuQ4x7AAvih+QUYeOIzphw0qQzwVeTFUV0q1elonjNqhModbJChY4e++d4NT9EIJmyjBDG8pSfhUF57cRr5Gha0LbzlB53WQWJpiPXdb/Dj/8m2U6LdWD/Ok1e0mFdoIqTSZkSgxj4GTOxKGuENbmuwWbmGQLznU= ARC-Message-Signature: i=1; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=06+ir6ny4Ln0oN97wv1SB2Wg0mLnpqdVB1qEhcqxE0Q=; b=CIJ6L2za/Ld2FKI+1PRjFlC2hbXMicLJz9qeHkuxjjF0Uts1UCo0YiKkR5GuGRzO0h eeM6A4goor7ZF8P/Eg/uEoN8VlhPHQOHEGZOdBDB1gjnqatgB8IvGZJY9cg36QS2/TTq qqKjFIk7+PSFfHBOKmwt0jY3F9/8sRKUG29U2pzB3/Ln38j1Z8Nl4UuglMM4gSfJah65 oiVF+9fIZNqZDZfcb1yWJbPjIwxSg2Mfg8b9S6wd8yXSOXkLXkanLvqUrkyLxe+5nc0Q /gru/GEEWOFIGKV7FnmiY7us7Z+PuvEwxA6uVht0Y99h+tddW9gJLSsDcKqsYUZhWjEl cZPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=06+ir6ny4Ln0oN97wv1SB2Wg0mLnpqdVB1qEhcqxE0Q=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 55863f76a7..6819c97792 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -612,7 +612,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); break; - case INDEX_op_st8_i32: + CASE_32_64(st8) t0 =3D tci_read_r8(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); @@ -874,12 +874,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; - case INDEX_op_st8_i64: - t0 =3D tci_read_r8(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - *(uint8_t *)(t1 + t2) =3D t0; - break; case INDEX_op_st16_i64: t0 =3D tci_read_r16(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=acbBM9pC8e1A/bvx5nB4UsPCm3LAoSp/wHIVXG+hEzA=; b=wMuzlzxb/KNISWtkhg14HHUfc1qQUIFCO+/mSl8xNUmhLq3lOJpKl+da5olT93LABi XC2mvbSjzwo+rfdcg5Lj/FSj2m8ruoEbDsXjPCl6C+bGtuSIiijXHeEbwycVv/Ng30y/ QJKpB+GvOfMZe009/QZPMMJhH4ISnfZiRySnQpLYq+4Wk8SJYJnLanvzJmMkEzGnO4nG RroqCR1oTHx3FL3zq8CTV4Wom/pqGP7y/Rj3FSkWYNtUdWqjm3Jo6qaKTjog626lV1c7 bGH51l+11VQCRAZLFJfPIHYNipjFfooxiBWYjyjBXWCofgdD+N8c/WdQa+bq18eIOUeL bgtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=acbBM9pC8e1A/bvx5nB4UsPCm3LAoSp/wHIVXG+hEzA=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 6819c97792..fe935e71a3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -618,7 +618,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t2 =3D tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) =3D t0; break; - case INDEX_op_st16_i32: + CASE_32_64(st16) t0 =3D tci_read_r16(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); @@ -874,12 +874,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; - case INDEX_op_st16_i64: - t0 =3D tci_read_r16(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - *(uint16_t *)(t1 + t2) =3D t0; - break; case INDEX_op_st32_i64: t0 =3D tci_read_r32(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404682; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aEJQJ28aTfFYwWXCrc4/tQ7PstJpDur23rDVFAChQBo=; b=RixZ2tfG4LIRL+V3EXWjLFxaErEiHAkX62uedpc/7udtA6rqMVPDJP36G6hDNwBK6G tfsst1+7V2O8zecmXnWirr8AtTxdNQmcgNExM0tb//8vX62CsdS2ZrJQUf1e41PsfabG pz65jsZYndxld7EQIqJ4RzZs1LS7M36oR5d+nJipqV+6hL2I1SqU5EGGFni3gUQid11V GRmrIsodM00q7mAZD5vkoj3wOQfJRrS4YfUk1r9lKGiSfdmlH+H0LEs6QW6eMYJTZb4l OSdDUaaHceEW4HQE1DmZMytffHm1GRqdyYY7iLZBvSJecGaF1feeccJ2UslQ7Kc02BWT mtlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aEJQJ28aTfFYwWXCrc4/tQ7PstJpDur23rDVFAChQBo=; b=WNEv5FI/6ibUsqLrh5ojbCLOmy9LOQiFQ6YxRqikfHAsUJXA4bhlP911NuejO0h30N 8Ux+j4sPdnPL3PSe4I77gzeBe1vqLcZMuXovrjZY3bpDEMdzhhtVuZWiXHYv6n1gxSG7 UND0pCNORovIFNFjWCLophLWNHd5kouNUPgMTldBuZld7DodN2ErUB9yhOb4sE54iEb8 gKRaQnfDGqdXJylCNooI0BkeNEtLC+t4RpHzvBkI3KmLztBZjvT6TADTUHzXXkuNOArj FPT5VuTEXasufPm1VpR9JJufBLCI9Kkzr7oY7QzJN9fkgtBt1vjtwI2ULPgohUyBpvWW uZtw== X-Gm-Message-State: AOAM530mH4pNPjHWxQHLi+94jvGXzbJDuh5rsA+EyMjgX10px0bbLNHZ ytUSawj1eW+otSJD4Ll7zky22ssxkSet0m+S X-Google-Smtp-Source: ABdhPJwflp2+Jr+UrevoEzwyTX6jknaYbF3jvW8+AmcjvCgS3w0ONZlFC7DqTaI2BMRMP73q49TWsQ== X-Received: by 2002:a65:4983:: with SMTP id r3mr6716986pgs.288.1612403150550; Wed, 03 Feb 2021 17:45:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 20/93] tcg/tci: Move stack bounds check to compile-time Date: Wed, 3 Feb 2021 15:43:56 -1000 Message-Id: <20210204014509.882821-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The existing check was incomplete: (1) Only applied to two of the 7 stores, and not to the loads at all. (2) Only checked the upper, but not the lower bound of the stack. Doing this at compile time means that we don't need to do it at runtime as well. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci.c | 2 -- tcg/tci/tcg-target.c.inc | 13 +++++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index fe935e71a3..ee2cd7dfa2 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -628,7 +628,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t0 =3D tci_read_r32(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_assert(t1 !=3D sp_value || (int32_t)t2 < 0); *(uint32_t *)(t1 + t2) =3D t0; break; =20 @@ -884,7 +883,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t0 =3D tci_read_r64(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_assert(t1 !=3D sp_value || (int32_t)t2 < 0); *(uint64_t *)(t1 + t2) =3D t0; break; =20 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f0f6b13112..82efb9af60 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -375,10 +375,20 @@ static void tci_out_label(TCGContext *s, TCGLabel *la= bel) } } =20 +static void stack_bounds_check(TCGReg base, target_long offset) +{ + if (base =3D=3D TCG_REG_CALL_STACK) { + tcg_debug_assert(offset < 0); + tcg_debug_assert(offset >=3D -(CPU_TEMP_BUF_NLONGS * sizeof(long))= ); + } +} + static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg= 1, intptr_t arg2) { uint8_t *old_code_ptr =3D s->code_ptr; + + stack_bounds_check(arg1, arg2); if (type =3D=3D TCG_TYPE_I32) { tcg_out_op_t(s, INDEX_op_ld_i32); tcg_out_r(s, ret); @@ -514,6 +524,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: + stack_bounds_check(args[1], args[2]); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_debug_assert(args[2] =3D=3D (int32_t)args[2]); @@ -716,6 +727,8 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCG= Reg arg, TCGReg arg1, intptr_t arg2) { uint8_t *old_code_ptr =3D s->code_ptr; + + stack_bounds_check(arg1, arg2); if (type =3D=3D TCG_TYPE_I32) { tcg_out_op_t(s, INDEX_op_st_i32); tcg_out_r(s, arg); --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404215; cv=none; d=zohomail.com; s=zohoarc; b=BD0bZxWkM1hzAscw801TjkGecLT+R3uPycjuKwbuXwEn5NRBzBkjOBxFyYIkIidmEZdV+e0a4qPUDPdR4FNi1rjkf2KEtXhsOxmQl1EM7PFkkL2Zx/hX0HJVN5b/qAT7WYYq7fBoIm/jahVuPH3aA3LJTpo1sGiYiQvosDtiGeA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612404215; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pMV4BySeK8KuIUlVV1lxW3l1A4MrToushLk684ASlQM=; b=dVwlutw80FxsPbJX9yqA1/0KG1J9RfxvtCSvzo97vmzR6VCoMPAzUIW3oAfLCWdE9mqKGZvQ5dJQmP3WRJc2OZ6VKler/kdq/iGA6NPZsH6Kj9bzTrJSmddp3crejcIarR7j9dknzgPrxlIofH3AvQNapCJ65Hh/c5LkZB2DgDg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161240421535448.445427008273896; Wed, 3 Feb 2021 18:03:35 -0800 (PST) Received: from localhost ([::1]:51698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7Tza-0000f9-90 for importer@patchew.org; Wed, 03 Feb 2021 21:03:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44428) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7TiW-0004zh-CI for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:57 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:35655) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7TiT-0003pO-HC for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:56 -0500 Received: by mail-pj1-x1029.google.com with SMTP id e9so830340pjj.0 for ; Wed, 03 Feb 2021 17:45:53 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index ee2cd7dfa2..eb70672efb 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -625,6 +625,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, *(uint16_t *)(t1 + t2) =3D t0; break; case INDEX_op_st_i32: + CASE_64(st32) t0 =3D tci_read_r32(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); @@ -873,12 +874,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; - case INDEX_op_st32_i64: - t0 =3D tci_read_r32(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - *(uint32_t *)(t1 + t2) =3D t0; - break; case INDEX_op_st_i64: t0 =3D tci_read_r64(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404886; cv=none; d=zohomail.com; s=zohoarc; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PJmFss8croBP2fe7sUR8rqNmFHSeMIecdaY2so4F4z0=; b=p21AHYlEF2ucBz1JosZKGCJ6+4A/Xf83NilSNFh2f0bXJj/DfNQzzJLTYRTW0j1WX9 riI9pbCXpS4geJoBhP+4PAzBxE7EZTrnp8TXkCR7VodDbatXOnEeJZid2b89QezcNYnf 7B3VV3H0L1apGQEyQIAmFWRywXs41TFdUKCG9ULJU4TCTaR16iUz3h1NNZtrWDH5KNAT AWG0tFdNYVYtkbsrgd8xwhZ3iPlj3Inz4A3aJuUVaIVDQdje/+N5tpDTn5CZ9AVSwXsN psbfxoSaHNoVG+KpQCBtr0C1bvyaUDEX2kvkKpiRY22Y+IrnisQbdv7GrLQosFNjaG+f TvxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PJmFss8croBP2fe7sUR8rqNmFHSeMIecdaY2so4F4z0=; b=NFC4yzaP1uHR07487mTaG8fEGkdhX4mtDrtEgQ3wDvtl5vrn8FApO/WhUPAAMjwAd/ 1Aand+dg3e8zXHjADqYa8oEQl0BscyDQtX1Y1EPpTgTr6ez1IDhHLRxTUweH6Th4tmBQ H6Qy7O7I87WfIcsFkzcpcVRFIxV2eqmj22zTvUqFzKivJAFBtpuOySn3C3ves8Th0ncx 6CUB5n5di5ZaGoL/byK4jfz5iHMQIzwYmgFVHJfIRAZbFEqraXM0jgnE18J3HyONKQgQ 20OcicDwfBniCgAARxoHj+WkbFCh2PlQxDPzqMWCafvb/KhQAlnPwGMLlYBcJPcbjnDV dSOQ== X-Gm-Message-State: AOAM531QItVBOuL96Qz8M9hlemjp2vEY+ZdrmnkTrG13Gh8a23tzwVhI ylbrEC0wgl4alXOQ1Yzenu83ckFcxyZbYar5 X-Google-Smtp-Source: ABdhPJwhV7LQbhENYFyXtxdyilAnzVbT7qtWM8A3aVCRW59Yvfh5j9Yl9b8FnefwLBVXnlOEVI/LIA== X-Received: by 2002:a17:902:9a4a:b029:dc:435c:70ad with SMTP id x10-20020a1709029a4ab02900dc435c70admr5676762plv.77.1612403154013; Wed, 03 Feb 2021 17:45:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 22/93] tcg/tci: Use g_assert_not_reached Date: Wed, 3 Feb 2021 15:43:58 -1000 Message-Id: <20210204014509.882821-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Three TODO instances are never happen cases. Other uses of tcg_abort are also indicating unreachable cases. Tested-by: Alex Benn=C3=A9e Reviewed-by: Stefan Weil Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index eb70672efb..36d594672f 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -362,7 +362,7 @@ static bool tci_compare32(uint32_t u0, uint32_t u1, TCG= Cond condition) result =3D (u0 > u1); break; default: - TODO(); + g_assert_not_reached(); } return result; } @@ -404,7 +404,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCG= Cond condition) result =3D (u0 > u1); break; default: - TODO(); + g_assert_not_reached(); } return result; } @@ -1114,7 +1114,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tmp32 =3D qemu_ld_beul; break; default: - tcg_abort(); + g_assert_not_reached(); } tci_write_reg(regs, t0, tmp32); break; @@ -1163,7 +1163,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tmp64 =3D qemu_ld_beq; break; default: - tcg_abort(); + g_assert_not_reached(); } tci_write_reg(regs, t0, tmp64); if (TCG_TARGET_REG_BITS =3D=3D 32) { @@ -1191,7 +1191,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, qemu_st_bel(t0); break; default: - tcg_abort(); + g_assert_not_reached(); } break; case INDEX_op_qemu_st_i64: @@ -1221,7 +1221,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, qemu_st_beq(tmp64); break; default: - tcg_abort(); + g_assert_not_reached(); } break; case INDEX_op_mb: @@ -1229,8 +1229,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, smp_mb(); break; default: - TODO(); - break; + g_assert_not_reached(); } tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); } --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404041; cv=none; d=zohomail.com; s=zohoarc; b=OMi3TwqG/YY52lebPNbdOaaBq/zv57gzu42Pln0ubB8Y6LuKWUpPn1vQTFzLr1usH+Zpjn5mA0rTxE4/d7s+w5M5MmNLG/PWUVGobNak/HSaw9vzFExgwEPMPwCQ1ErlnXe+5JlsQHprgYEAsJxd6FhtnngqFJFxjsq5c/gtT1o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612404041; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rzqE8qXvCMMaAx4wVWdxYTRZ0dwbqGtPGHyjXMn8W48=; b=nUjrBVPsEoHLKp9wQYsjUuX4IaOfqYRb6SbmlexPxDd7U88k3AdC1lMGGxNey7FCCo97GnjV5BWjNVkAS1BJXDbxcuET0hEilEZozkTkrfOUB3Kcc0bxYHy5B9XeTkXeM3YlmXHXIaQxMLx4ySr40cgIX8UDM7sTmn+rMMM+IbU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612404041774333.79366052317687; Wed, 3 Feb 2021 18:00:41 -0800 (PST) Received: from localhost ([::1]:40256 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7Twm-0004GA-4F for importer@patchew.org; Wed, 03 Feb 2021 21:00:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44464) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7TiZ-00051I-VN for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:59 -0500 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:38322) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7TiX-0003qU-0v for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:45:59 -0500 Received: by mail-pf1-x42b.google.com with SMTP id y205so1074765pfc.5 for ; Wed, 03 Feb 2021 17:45:56 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rzqE8qXvCMMaAx4wVWdxYTRZ0dwbqGtPGHyjXMn8W48=; b=lZJQyPOO1KRBaGJWUaxPtMbyv5ZnjpvVgchjfLMlgsJdrzobET4BPO1b0pwD6C8RzD ZMBrPcGfdgpK992RRyi57neonIkdb3J9WhzhqKSntZj7Wtoa40oN+hytYuNl06o/4ifj M0FWJjuAMMWU72G9kog9LrIZqM/a65o5uAP1Da9/8Xg+sgk+EB6NCaREiOzuUG7eYKkc popXNDg4UKZ5pUPs9vmn4eewx60rYi2xtt7BGd9dZCDrwC6z6kt2Kb/hN1D2U2VJEmi4 c1pzjE/VnFRfaEDnAByTlkcy5J7JEQiVprpvV6S62g3/O85zmHGlanAKxvAAcyNh9s4f YFOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rzqE8qXvCMMaAx4wVWdxYTRZ0dwbqGtPGHyjXMn8W48=; b=mxezS9+9UHSPheQSjivWonwHShUayNIct6enY3M34lqQ0LQ9Vfwb9vNDaiYqUtRISi HUu4YHflwiYWaZkRE/w+EWONEbYZAW8Zkq8+sUQb/v3nu/pCkO9wXIZwmzsL//imTjz2 ZB5IdI6HUuJW64d0W7WgA+r8oAEmNLBeS/pKbioUNOOS5OtSAaQyfncvIAxrNSj6VYlN VslpTSPi4YeP7j70Jns85vY8StzjHymiPbm/A/LFLAIoxBiFAN66iVpcdQU2Rx0kAmvg dApLHNJQjdmW6lUoWL6fkE2i19WbZQLvJw/XBFJF+N40q3x50h6DHxTolhCDXSGW06S5 Y7rQ== X-Gm-Message-State: AOAM5330jc+Dp1okB9QtS5D9kGJvmZQTODg8tktnxmFTVX2AKCV5g/Ea hpcJyeNJQIs9XCA+FHHJzn0GAFjesvafMUIa X-Google-Smtp-Source: ABdhPJweLhPK8Av3gDK9TDMCUE0yrNUHjH24yAdIXtSUbg+jWxIoff/f9z10SkCVlHFvpnw+AoEjrQ== X-Received: by 2002:a63:4507:: with SMTP id s7mr6512529pga.390.1612403155898; Wed, 03 Feb 2021 17:45:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 23/93] tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_* Date: Wed, 3 Feb 2021 15:43:59 -1000 Message-Id: <20210204014509.882821-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) We do not simultaneously support div and div2 -- it's one or the other. TCI is already using div, so remove div2. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci.c | 12 ------------ tcg/tci/tcg-target.c.inc | 8 -------- 2 files changed, 20 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 36d594672f..25329345cf 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -652,7 +652,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t2 =3D tci_read_ri32(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; -#if TCG_TARGET_HAS_div_i32 case INDEX_op_div_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_ri32(regs, &tb_ptr); @@ -677,12 +676,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, t2 =3D tci_read_ri32(regs, &tb_ptr); tci_write_reg(regs, t0, t1 % t2); break; -#elif TCG_TARGET_HAS_div2_i32 - case INDEX_op_div2_i32: - case INDEX_op_divu2_i32: - TODO(); - break; -#endif case INDEX_op_and_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_ri32(regs, &tb_ptr); @@ -908,11 +901,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, case INDEX_op_remu_i64: TODO(); break; -#elif TCG_TARGET_HAS_div2_i64 - case INDEX_op_div2_i64: - case INDEX_op_divu2_i64: - TODO(); - break; #endif case INDEX_op_and_i64: t0 =3D *tb_ptr++; diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 82efb9af60..6dc5bac2f3 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -596,10 +596,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ TODO(); break; - case INDEX_op_div2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */ - case INDEX_op_divu2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */ - TODO(); - break; case INDEX_op_brcond_i64: tcg_out_r(s, args[0]); tcg_out_ri64(s, const_args[1], args[1]); @@ -639,10 +635,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, tcg_out_ri32(s, const_args[1], args[1]); tcg_out_ri32(s, const_args[2], args[2]); break; - case INDEX_op_div2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */ - case INDEX_op_divu2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */ - TODO(); - break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612403892; cv=none; d=zohomail.com; s=zohoarc; b=VTvj5aW/oyI+IbZOq7A373QBZpof1tU7+IDVxtx8ra3q/uVayCApqHtvT6dnoLoTAGzSHIWcvrC+m54vrlWvgsU2OQ6Cfu1H6ns9GFJ2S6VJGm+HOLGHpc0ZU/Lmb693u09p2MHIxTZD06C0wHKEC1CN5wdZloPHdkPzTXpKAuc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612403892; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nPG7Xcmlwk2vyC0De6Qy+WTUFdq1vGPN65ZNzO4h0N8=; b=dO0tnPEXQDgAcdQf7briCefW02VDBbHmM856uWgyLZfy8COheaWPHri+T82ll3lDEdh5rvbTdX9hH2U8rxMrbFWiU7/FF6AfPtgOmI/VNW9HXk5zuR7Wglsh2mCxy1IFNm3JpgdFWghwKp9lOUhB9kKGBkfyXYKAmtJNQWvyxRw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612403892853819.535833854207; Wed, 3 Feb 2021 17:58:12 -0800 (PST) Received: from localhost ([::1]:35140 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7TuN-0002AM-QU for importer@patchew.org; Wed, 03 Feb 2021 20:58:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44568) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Tij-00059z-Ka for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:11 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:35044) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7TiZ-0003qb-LL for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:07 -0500 Received: by mail-pf1-x434.google.com with SMTP id w14so1083861pfi.2 for ; Wed, 03 Feb 2021 17:45:58 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nPG7Xcmlwk2vyC0De6Qy+WTUFdq1vGPN65ZNzO4h0N8=; b=e22JbnducbnrgrRCACzwQIkeItCT0UJ7+xsgYFcc+vBheGLKBNa4rEok3A0svO/XZS m9Ud3MqcDsGKdcOZog+LE1YLkjojxk9tJkvsz030bLgDfdH7klFgDen4URedo6WSTVhv 3Hl/Qy0o7XMJcJAvtInwJh54Hc8TgYvff5TIOtfxPWKgEixA9zHn6oWidXgnVtjmNB3o +eHe40D/XE6dmFU2CcTYFCL0+JqS0ErglNc0+kIYsdhPe767HrTDnzDzGkMT3YI41RUy ytdnSnQJ4R+H0T0ZZFbGG7G83BmJ2T868SuNgGnUdP9+SIDgZDW2nuzVxOhlqw0f2jKj P/SQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nPG7Xcmlwk2vyC0De6Qy+WTUFdq1vGPN65ZNzO4h0N8=; b=BW1Wb3QDF8RyEhYWSPiG2ZLykFbJK/9dKuY+m7qfkRwZCgzW3XCvmRzcOVeFvQKswA H/TDV0t7kKZEHbNundBBwVui2Cv5a1LlFWkSrQYUar+VCKip3hrk76SwRtm2Sd9rucSt zaDAcsyokzCgmlcKROHoAIV4a8qgJ5PE320XYbA7OQygFpq1IpfpPAVnrFrbnh5B8pb1 XKoWESLsrTEffcFGOdABvCUaNkCbKQj32srpkZi7VrWKoZYwzTvcn7GPLa3gnws0vlR7 Kwb4fEyk4SmGgl/srAUg+rpb73elk8YRYREzBPO2zcnIVrYJAhyPMBdv+G/v4tGiM4Ww 6dfw== X-Gm-Message-State: AOAM5323cS5dNI0pn9EGPtWlrqavk+z8en6MXrJ9sTcIjAvq2vvc8ZCw akLhD9NqTgf7IAhxCo0yxDrp+sSgFwVSl3Fk X-Google-Smtp-Source: ABdhPJxzqHnsR/3vchMOCpLXxivjhPWu/rmVAJAZ1DXdg/inCLQwqHig7aobFtSs+NWLQgmKqxT9Dw== X-Received: by 2002:a63:d855:: with SMTP id k21mr6414313pgj.399.1612403157494; Wed, 03 Feb 2021 17:45:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 24/93] tcg/tci: Implement 64-bit division Date: Wed, 3 Feb 2021 15:44:00 -1000 Message-Id: <20210204014509.882821-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Trivially implemented like other arithmetic. Tested via check-tcg and the ppc64 target. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 4 ++-- tcg/tci.c | 28 ++++++++++++++++++++++------ tcg/tci/tcg-target.c.inc | 10 ++++------ 3 files changed, 28 insertions(+), 14 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index bb784e018e..7fc349a3de 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -100,8 +100,8 @@ #define TCG_TARGET_HAS_extract_i64 0 #define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_extract2_i64 0 -#define TCG_TARGET_HAS_div_i64 0 -#define TCG_TARGET_HAS_rem_i64 0 +#define TCG_TARGET_HAS_div_i64 1 +#define TCG_TARGET_HAS_rem_i64 1 #define TCG_TARGET_HAS_ext8s_i64 1 #define TCG_TARGET_HAS_ext16s_i64 1 #define TCG_TARGET_HAS_ext32s_i64 1 diff --git a/tcg/tci.c b/tcg/tci.c index 25329345cf..5c84a1c979 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -894,14 +894,30 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, t2 =3D tci_read_ri64(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; -#if TCG_TARGET_HAS_div_i64 case INDEX_op_div_i64: - case INDEX_op_divu_i64: - case INDEX_op_rem_i64: - case INDEX_op_remu_i64: - TODO(); + t0 =3D *tb_ptr++; + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); + break; + case INDEX_op_divu_i64: + t0 =3D *tb_ptr++; + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); + break; + case INDEX_op_rem_i64: + t0 =3D *tb_ptr++; + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); + break; + case INDEX_op_remu_i64: + t0 =3D *tb_ptr++; + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; -#endif case INDEX_op_and_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_ri64(regs, &tb_ptr); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 6dc5bac2f3..3327ce3072 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -577,6 +577,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, case INDEX_op_sar_i64: case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ + case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ + case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ + case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ + case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ tcg_out_r(s, args[0]); tcg_out_ri64(s, const_args[1], args[1]); tcg_out_ri64(s, const_args[2], args[2]); @@ -590,12 +594,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, tcg_debug_assert(args[4] <=3D UINT8_MAX); tcg_out8(s, args[4]); break; - case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - TODO(); - break; case INDEX_op_brcond_i64: tcg_out_r(s, args[0]); tcg_out_ri64(s, const_args[1], args[1]); --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404174; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5oMkWTFAvkbENXCd9UcZlqUmvtysI4E37yjhcZ4CH7A=; b=xle5V4a4kqCv2nbTnmDL1F5pLKB1kQsToVwsq+57vmouygcUOMz0DRYxoFk66YLJMS 2I/OyMbguKM637Ll58JPW5VNV14Ked7Ei4Xu0PTH5jvByAMLTCu/7TmnL8LCR847qPL0 yXy2P9F7Fb5cy/vRaj5/jv+vfD8HJQwtqXd4HvYQkNHHLHhCOTllppVRwPRtXr6ecysa g5g3ZsDMJUkNGYYulquvsOsl/6fdXwTYXLJSvRS2QcNp5AC2xjOg1JnN+LzH+RDBa1l8 unmxyCA2k/tTBeC2x3xGUvfgm3pm8lQKo5vcyBlDDMuhacfWF0PmKVDmbywz5ZvFEGCL Q4/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5oMkWTFAvkbENXCd9UcZlqUmvtysI4E37yjhcZ4CH7A=; b=dHa6J6aZTntZ5y3FLXeIIoVS3tPuKg1GJ2kDTT1z33OQBtnJskHM0yzt6IoePipntT SEhbsaKssAHT9pfG8wCQhY+UBPYHmWXiPk2NdNSwgcTWpTa58jD9FVbH5uQ6GXNBIKcu ffFKqFH2ZLgZ8dh6dIoY7IAfPm6zqAGQ5Bf5BgSZDliSXlmFEyFQnoDmPQT4mwyIQ4ol +qXt6icTDi1HddqyJE4c/0vQQnRNrlIkl95JRXCsx1CzLkoHNQu0kKuTfjYZiEulgyQn 7Y0JpTX23i9TtFVxDWhSY072A+qcdQv//7o4LaGKzZR1RNECE0yOK8m5H8NCL6DrJiAY szmQ== X-Gm-Message-State: AOAM532GgPNz9+PCNpBVoFaI4yjQ/Ciy5VEdWXtAUbu5UbR3jgaCw6S2 i/VuzzmfPparTbx4B2WWnttrCyypgqrHcJrz X-Google-Smtp-Source: ABdhPJz+1EL3F98lhINj4w6c+bTlaxu6pEFAG3MRq6P/8dbk+kQsdX9jF9kscRrG+99QRWovvsZ31Q== X-Received: by 2002:a63:c1d:: with SMTP id b29mr6618739pgl.9.1612403159413; Wed, 03 Feb 2021 17:45:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 25/93] tcg/tci: Remove TODO as unused Date: Wed, 3 Feb 2021 15:44:01 -1000 Message-Id: <20210204014509.882821-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 5c84a1c979..e0d815e4b2 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -33,14 +33,6 @@ #include "tcg/tcg-op.h" #include "qemu/compiler.h" =20 -/* Marker for missing code. */ -#define TODO() \ - do { \ - fprintf(stderr, "TODO %s:%u: %s()\n", \ - __FILE__, __LINE__, __func__); \ - tcg_abort(); \ - } while (0) - #if MAX_OPC_PARAM_IARGS !=3D 6 # error Fix needed, number of supported input arguments changed! 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=16lbvRerppaZSdDTN+VtWDIyr6a+gIglS3gZgOzl7iY=; b=R4NvyATnmW0tH/hLoTG1oouQSwlPgDOlAYfc57Mub4FXMUqG45m86M3eHaTp395kWu lOoRLPs7CXXYFA0V1XqcdxadaQDwpMjc9gwsf8jryta3GFK+M8BWfJYbv1Dv5WDjH4RU 8qG8t8ee71QcJ0wEJdADqCwMOCwUTHHvBXFAK3w2fmpC2UPV+CjcOtTYK4lC3BTpcn/n olC77t8Cx9+xgK0iFTqsb4ysqtqKA/b9K1EDQMZ0GksDt5Xa6QooYHEh+VBMtQ+JFyRR uQeaVpvFD+J0Ulul4PCxko9/uCagWb1N4emJbx8h58PNhfLicgglduBL9iMGjaOPsCb/ qiWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=16lbvRerppaZSdDTN+VtWDIyr6a+gIglS3gZgOzl7iY=; b=KyeJQZVTaNORYsjinR88eFoKZhDeLDUWTeGZJ8ILxhX36o+a5oSCFUF6DlJy8Dytm0 0UkVHgv/wKbW2XSd/Xsttl+f7Zqr50GDWrjiQh0cB0jG900n+EbCp0aDF76SMuW2aJjt thwbQqaCgKAn+DbH4Wu/oHgyQJnlggd/o2Qw9QJiRxU4DYXiyOLSKEzQcADNCZerstRh qXQkEBUxyct5SfuVsAgtpoNCMfkSEembI/kJaZNmm5hWIo+Z7EeH08OYhyWBL4n5SgOP WHcN0N6X4VC3KA0bjo25BKNQL3HV/XupoHoR+lGvfRoNnr6hmbDXVi1qsBGD4eRMJGJw pXeA== X-Gm-Message-State: AOAM532+nBaX5JSsdr2IzwNTY2NPhCj9Bn8/uF5uggx9P7G0sQIWH18q CiUC3jBFPIODvpOQG0SqqzIEXNwOJPmCVaV6 X-Google-Smtp-Source: ABdhPJxhbnO11OO0tSpM6mH8d7upOhKNh5Y9nBvA0k/CELab2jRq5a7AGD+M2EZFFINqHoRZB2/Y4Q== X-Received: by 2002:a62:80d3:0:b029:1c0:c5de:ff68 with SMTP id j202-20020a6280d30000b02901c0c5deff68mr5690901pfd.79.1612403161213; Wed, 03 Feb 2021 17:46:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 26/93] tcg/tci: Restrict TCG_TARGET_NB_REGS to 16 Date: Wed, 3 Feb 2021 15:44:02 -1000 Message-Id: <20210204014509.882821-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" As noted in several comments, 8 regs is not enough for 32-bit to perform calls, as currently implemented. Shortly, we will rearrange the encoding which will make 32 regs impossible. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tci/tcg-target.h | 32 +++++--------------------------- tcg/tci/tcg-target.c.inc | 26 -------------------------- 2 files changed, 5 insertions(+), 53 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 7fc349a3de..8f7ed676fc 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -133,11 +133,8 @@ #define TCG_TARGET_HAS_mulu2_i32 1 #endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ =20 -/* Number of registers available. - For 32 bit hosts, we need more than 8 registers (call arguments). */ -/* #define TCG_TARGET_NB_REGS 8 */ +/* Number of registers available. */ #define TCG_TARGET_NB_REGS 16 -/* #define TCG_TARGET_NB_REGS 32 */ =20 /* List of registers which are used by TCG. */ typedef enum { @@ -149,7 +146,6 @@ typedef enum { TCG_REG_R5, TCG_REG_R6, TCG_REG_R7, -#if TCG_TARGET_NB_REGS >=3D 16 TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, @@ -158,33 +154,15 @@ typedef enum { TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, -#if TCG_TARGET_NB_REGS >=3D 32 - TCG_REG_R16, - TCG_REG_R17, - TCG_REG_R18, - TCG_REG_R19, - TCG_REG_R20, - TCG_REG_R21, - TCG_REG_R22, - TCG_REG_R23, - TCG_REG_R24, - TCG_REG_R25, - TCG_REG_R26, - TCG_REG_R27, - TCG_REG_R28, - TCG_REG_R29, - TCG_REG_R30, - TCG_REG_R31, -#endif -#endif + + TCG_AREG0 =3D TCG_REG_R14, + TCG_REG_CALL_STACK =3D TCG_REG_R15, + /* Special value UINT8_MAX is used by TCI to encode constant values. */ TCG_CONST =3D UINT8_MAX } TCGReg; =20 -#define TCG_AREG0 (TCG_TARGET_NB_REGS - 2) - /* Used for function call generation. */ -#define TCG_REG_CALL_STACK (TCG_TARGET_NB_REGS - 1) #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_STACK_ALIGN 16 =20 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 3327ce3072..7e3bed811e 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -187,7 +187,6 @@ static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_R5, TCG_REG_R6, TCG_REG_R7, -#if TCG_TARGET_NB_REGS >=3D 16 TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, @@ -196,7 +195,6 @@ static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, -#endif }; =20 #if MAX_OPC_PARAM_IARGS !=3D 6 @@ -216,15 +214,11 @@ static const int tcg_target_call_iarg_regs[] =3D { #if TCG_TARGET_REG_BITS =3D=3D 32 /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */ TCG_REG_R7, -#if TCG_TARGET_NB_REGS >=3D 16 TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11, TCG_REG_R12, -#else -# error Too few input registers available -#endif #endif }; =20 @@ -245,7 +239,6 @@ static const char *const tcg_target_reg_names[TCG_TARGE= T_NB_REGS] =3D { "r05", "r06", "r07", -#if TCG_TARGET_NB_REGS >=3D 16 "r08", "r09", "r10", @@ -254,25 +247,6 @@ static const char *const tcg_target_reg_names[TCG_TARG= ET_NB_REGS] =3D { "r13", "r14", "r15", -#if TCG_TARGET_NB_REGS >=3D 32 - "r16", - "r17", - "r18", - "r19", - "r20", - "r21", - "r22", - "r23", - "r24", - "r25", - "r26", - "r27", - "r28", - "r29", - "r30", - "r31" -#endif -#endif }; #endif =20 --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612405118; cv=none; d=zohomail.com; s=zohoarc; b=ZEjLdaZXUXmfNNq+3SH/ODNmBEFXMRYR3RUqmGhZU8/qVu1kxewJnTecF1c2ukg23CirrSHeKQ19HwWjtd19SVBnRy2Ihy+Nf3dDtdncck9Y9cJbLFuFp42+rxGeMYseKFtojcVBHxvX5P+SpiOHKcp6CAh2zEl3DEMZMk6gmMA= ARC-Message-Signature: i=1; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jQllLPStMSpXHN7NTbXqzAr+6+LQfKhn+prBrsPItko=; b=T7gx58sfcOcVq3/jelk2LUWq3qrkCIfnRtVKOXZMyibprPGKIvN5uVRVt9A3vdnonF i+SKczPklN2tuolzwPWwgzGJ49sbRoK2W515hMKauRkGOrp60A6CHZLKPJvoPExdIh9T NyYzVRoMEt27boiANqqY8pbGv822rGEQLv2t61YvwF+78YqqdaUs96hiEQfxnueVzl9E Bb3Fonaw34qt086HoGjfp7Q+ZTMmb/49rxnjwH27HSzAI2dWTqUiHe12OhOGIJI/ZubE io+5N/I7TKJUhzE68/bhdVuJ4QqYghVLr22x8mJCNK6YgrDcG1XDV4nsVIcusTRsMvxt QBuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jQllLPStMSpXHN7NTbXqzAr+6+LQfKhn+prBrsPItko=; b=PWMw3eC26PsN7mBhiNoryUjkf17OC9EKFQt4Oif5Qh8NLivUWiHYJNrDjatE0Mc4Xx uWhTO+sKyJ+bCKqvIZ0Hpq9rPCrgqfRlMpTmU7yVxtoshR7Ca22VwJ/L5896Beuyl0C0 yJ0nr5TzNq43wRCmmE0pWPNAaHK+0YuIXORD8E9NfDKr5IQsaTwe+QuTJ5t153i4HU2c MoCcoS+X+kro1JD3qwWXxApHBUVt8XXfM7rNnGr7e4tuR+qShoQMsGpeaULZmtyvbmug bV6EDPOVkxjiEjWCnoTU6PO5OooT4fGkqUv0L+donrSPL4sdUt4G+XFdO11nhI7zRQhx NkjA== X-Gm-Message-State: AOAM531z560PejwkgqYkLxaAntpvoaIGO4MAG5CLmb5obTThpH8kwhZb ehaJXqHdNFwURtrYBWpSKkrwKo1oNRfTDXBA X-Google-Smtp-Source: ABdhPJxvsOPG3Wcb1hDAwJ53+UtsTLidPudyox5M5M7fbjGf/cA9bHpQ0oKWAgCXmZ1w5K32mwuFfw== X-Received: by 2002:a17:90a:ce89:: with SMTP id g9mr5786744pju.42.1612403162730; Wed, 03 Feb 2021 17:46:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 27/93] tcg/tci: Fix TCG_REG_R4 misusage Date: Wed, 3 Feb 2021 15:44:03 -1000 Message-Id: <20210204014509.882821-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This was removed from tcg_target_reg_alloc_order and tcg_target_call_iarg_regs on the assumption that it was the stack. This was incorrectly copied from i386. For tci, the stack is R15. By adding R4 back to tcg_target_call_iarg_regs, adjust the other entries so that 6 (or 12) entries are still present in the array, and adjust the numbers in the interpreter. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tci.c | 8 ++++---- tcg/tci/tcg-target.c.inc | 7 +------ 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index e0d815e4b2..935eb87330 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -511,14 +511,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tci_read_reg(regs, TCG_REG_R1), tci_read_reg(regs, TCG_REG_R2), tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R4), tci_read_reg(regs, TCG_REG_R5), tci_read_reg(regs, TCG_REG_R6), tci_read_reg(regs, TCG_REG_R7), tci_read_reg(regs, TCG_REG_R8), tci_read_reg(regs, TCG_REG_R9), tci_read_reg(regs, TCG_REG_R10), - tci_read_reg(regs, TCG_REG_R11), - tci_read_reg(regs, TCG_REG_R12)); + tci_read_reg(regs, TCG_REG_R11)); tci_write_reg(regs, TCG_REG_R0, tmp64); tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); #else @@ -526,8 +526,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_read_reg(regs, TCG_REG_R1), tci_read_reg(regs, TCG_REG_R2), tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R5), - tci_read_reg(regs, TCG_REG_R6)); + tci_read_reg(regs, TCG_REG_R4), + tci_read_reg(regs, TCG_REG_R5)); tci_write_reg(regs, TCG_REG_R0, tmp64); #endif break; diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 7e3bed811e..aba7f75ad1 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -181,9 +181,7 @@ static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, -#if 0 /* used for TCG_REG_CALL_STACK */ TCG_REG_R4, -#endif TCG_REG_R5, TCG_REG_R6, TCG_REG_R7, @@ -206,19 +204,16 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, -#if 0 /* used for TCG_REG_CALL_STACK */ TCG_REG_R4, -#endif TCG_REG_R5, - TCG_REG_R6, #if TCG_TARGET_REG_BITS =3D=3D 32 /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */ + TCG_REG_R6, TCG_REG_R7, TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11, - TCG_REG_R12, #endif }; =20 --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404391; cv=none; d=zohomail.com; s=zohoarc; b=RI+usP/T56vNr95YNJiC/tRCZD7Jk69MmGw/tvAPqbFQY/ZSOZcc2Bt5QKBeHG2fCvD53WwoPerxmERGPYBWzxqU4MBeRXebt08ha2+6q5UQPRH/3v5WsODMtjB46+mj+abf6Kh+FwCXMl6BiLPxg1O+AGlEJZqBIeF87govJqU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612404391; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LkYGLsnE5odHBLHKRYujD0SaJ6+i8O1fF0r+gNXotZQ=; b=aer8iH+ZyMJz4/wdY5VhiIQOipuvMemPH0/oKb2N/QLuOOw2dvcin0xJvCOgQCxlzgs7TTQyPPzf+VlDdgfckYSdv7GVBf4oc5ckn5TZfDm4yCY8jXSH72HQ9cPgqY2X5UgeOFAcSDyzSWUGdAaUBQmAE/2ospnD4EHhFG6hj5M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612404391962347.5159783577393; Wed, 3 Feb 2021 18:06:31 -0800 (PST) Received: from localhost ([::1]:60232 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7U2Q-0004At-TX for importer@patchew.org; Wed, 03 Feb 2021 21:06:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44664) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Tiq-0005C3-2o for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:19 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:46282) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tif-0003tu-DK for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:15 -0500 Received: by mail-pl1-x634.google.com with SMTP id u11so864851plg.13 for ; Wed, 03 Feb 2021 17:46:04 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LkYGLsnE5odHBLHKRYujD0SaJ6+i8O1fF0r+gNXotZQ=; b=eZsQKtecqisRl1xpSbVWYv80cWI/zD78JCH1ptNNjh2+TC8Fc+Ja6NzYWeK+ZRnzaZ Q/PzfWCgMdQlmJcDKwyxIIxpDRPtaud1B4Vu/bxujwbdXvTVa1cc/LKHHVTKxF/JGyqu 6as0fNPk94jAdE/BMUok5nzGN6KV7QvEdyvEtKnMOA5T/8wRf3MNMGt1dOvQ9xLmLhxI a4LbpVvw5xTTCZ5ogHPpZqbovD1MyTvvqoPjSzs9irbvfbbucN9QRGpC9A3ihvunaxIH gGmNQz9U5wJqgwSPOP2sGnddPIE68hzk984hqcv2d/74Ry8k5QUa1ORUvWG6IFdI1/zt OxQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LkYGLsnE5odHBLHKRYujD0SaJ6+i8O1fF0r+gNXotZQ=; b=o0YSqnxc9SfLU+TeTNNHbncqhqFg5QCRuaSN0SRqvcAomsd/DoVG2+MiZlYfF/9dT2 A7JLGrJ6HJPeuM2g9L8CYc/2pIOPaTCwjyACQ+OnbkGn5fvmFEEDK+AWPB+8vDxDki0U DM/PUJO++C5ntlJIG78nJwRKNtbF6HOGqa2diDj/l59YrRjjil9hmdKQE3krlu0kD6lA 7Fx80LFUPkbeztUqfduP2uv1fvWC4nI9CyBCDa3KiXWq9PmDmRSZlhFA3JFOpzXEXnpg RtpeTYLz1OUxPr7fcjTnhUwKcC5s1Bm3P3LphYeL9Vv8+yY94iQoHM4Ke1dDoBDryCnZ Jl1Q== X-Gm-Message-State: AOAM533n1Nd3WIn2b2CsNix4vy2Nrl4wcjXu5tYgHbZMCH9eBILjC8T2 WxM8ufa9jR9bwnaAMwVpMak6AZzjLMSgiugd X-Google-Smtp-Source: ABdhPJw0Z7Csiq2aFoyILS746Jo7sJbpXwdRYkFY5XG/9dwjWf2+sagxsx1QhqsADxrUwVlh3dqrAw== X-Received: by 2002:a17:90a:43a7:: with SMTP id r36mr6029354pjg.189.1612403164202; Wed, 03 Feb 2021 17:46:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 28/93] tcg/tci: Use bool in tcg_out_ri* Date: Wed, 3 Feb 2021 15:44:04 -1000 Message-Id: <20210204014509.882821-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This is the intended behavior. Remove the assert on the specific value passed, which can now never be anything besides false/true (0/1). Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tci/tcg-target.c.inc | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index aba7f75ad1..1b66368c94 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -295,10 +295,9 @@ static void tcg_out_r(TCGContext *s, TCGArg t0) } =20 /* Write register or constant (native size). */ -static void tcg_out_ri(TCGContext *s, int const_arg, TCGArg arg) +static void tcg_out_ri(TCGContext *s, bool const_arg, TCGArg arg) { if (const_arg) { - tcg_debug_assert(const_arg =3D=3D 1); tcg_out8(s, TCG_CONST); tcg_out_i(s, arg); } else { @@ -307,10 +306,9 @@ static void tcg_out_ri(TCGContext *s, int const_arg, T= CGArg arg) } =20 /* Write register or constant (32 bit). */ -static void tcg_out_ri32(TCGContext *s, int const_arg, TCGArg arg) +static void tcg_out_ri32(TCGContext *s, bool const_arg, TCGArg arg) { if (const_arg) { - tcg_debug_assert(const_arg =3D=3D 1); tcg_out8(s, TCG_CONST); tcg_out32(s, arg); } else { @@ -320,10 +318,9 @@ static void tcg_out_ri32(TCGContext *s, int const_arg,= TCGArg arg) =20 #if TCG_TARGET_REG_BITS =3D=3D 64 /* Write register or constant (64 bit). */ -static void tcg_out_ri64(TCGContext *s, int const_arg, TCGArg arg) +static void tcg_out_ri64(TCGContext *s, bool const_arg, TCGArg arg) { if (const_arg) { - tcg_debug_assert(const_arg =3D=3D 1); tcg_out8(s, TCG_CONST); tcg_out64(s, arg); } else { --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404789; cv=none; d=zohomail.com; s=zohoarc; b=hVEdU4wuvHpynEppyMpESkvHA4tyIJ5TMF73QU/y82yvS/3t/JnV+YblT511GlUBltFA+DEPB3W/tgeAKbzK3XQSrGmhdpyq7kAREdYYje6JjCo4IZsJM3gceF9xRowF4LCSU0aM0LuEWUOmzi7A3yI0G1r+ttyAxfgbbL5NKNk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612404789; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yS0gR/bmpwa/O4hUImsRvwlOE8hTboZh4LibIY9+LNE=; b=LTx0ib8b0izmB9GkXgR59Xd71FmwieE6LMIqc/jkKZ2DkbBaJLMb0phsb6YEJ1A5DzbgP7QWD0gKYt716gZYorh8gueDVCNk/PnDdmoaWAECq3YJMtMQcTYuh6mneP/5DM/C25pGw+26yupdE9yY3bxO5HoTUcWI7VFLqFglNxI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612404789985190.09193922729298; Wed, 3 Feb 2021 18:13:09 -0800 (PST) Received: from localhost ([::1]:49314 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7U8q-0003EM-Nt for importer@patchew.org; Wed, 03 Feb 2021 21:13:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44742) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Tiz-0005Hk-Ds for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:25 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:42488) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tih-0003u3-Iq for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:23 -0500 Received: by mail-pl1-x62a.google.com with SMTP id s15so878413plr.9 for ; Wed, 03 Feb 2021 17:46:06 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yS0gR/bmpwa/O4hUImsRvwlOE8hTboZh4LibIY9+LNE=; b=twoeh6Ref1+fBXfIf4gfW2QqhB3T69Yc+QE+/gmUf47fVkKCKDd4Zbc3/NgqpfHCwg UTLhgFjCDEUVFbzJENYdje+lf98DIqmU0RQZOx8l7BFqyp8q2JJjhe60mb010L5ZjA/e cCzQRiU/IeC1vqrc2KX1Ar+8XQW4rubH9MPKgU+mrgqzYOx6HyNf/6y/gr8nLVDQ9TcP Gu8v2RJ2HaXKtd+ih0GhzyKVjkx4ftJvXuOSyZWD/aEvmZSV4bh/ou+Vjr0hYHv3CIga svssWftPyfUSzwmj8kc8TjsyBRo/DUfmXwxI49dfePn//BKHnOpTlT6J5v+pO25eVDF7 pv5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yS0gR/bmpwa/O4hUImsRvwlOE8hTboZh4LibIY9+LNE=; b=P1rk95JT2h0zRT34sPH5EF0+2lIlpEHwv7Sw2L1kkP/N2xuMcpyVdB3lOpQsTpA2F2 qI20QNbtcz4QZUZSw9/vzwrA0HHZzSDTMemTZ3zUGFEg1BvdGmzLFuaJ5LAI/H4qPWsP Vibbk2ZzqEuVcIBom/kkI2Wxcz37oCSYtGIVXc3qLP2biSZT6GBg+LTCuiwmht/kgBQn 9n9ozaMmlRZ8iyd/kqKwvWswcENIm/ar4Yi+hHtJLIGpeHZqwqLYr+nz11KtikI03yRE Bw2IpdPrTZpwp7RJZEQlAwg4TMY6gp25yVxWWoZBCqmFCfwOiEYTiPG9QhbPjdmT7esq 9o+A== X-Gm-Message-State: AOAM530Z7uf94eU+OIlH3HmGparrIapQ30kId6chCK6YP8OyqgpRhXkZ 6Cl3fWgs85YdxmF01SpgxXO78DcxYOp1MsRl X-Google-Smtp-Source: ABdhPJwYCXu+qgB+wcHxvGXu0kTYideTX8YEAKapvE3Ts4JTwu3Sg7dVjT5oASA1HuQkpUcp3G8fRw== X-Received: by 2002:a17:902:9a49:b029:df:fab8:384 with SMTP id x9-20020a1709029a49b02900dffab80384mr5826517plv.37.1612403165705; Wed, 03 Feb 2021 17:46:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 29/93] tcg/tci: Remove TCG_CONST Date: Wed, 3 Feb 2021 15:44:05 -1000 Message-Id: <20210204014509.882821-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Only allow registers or constants, but not both, in any given position. Removing this difference in input will allow more code to be shared between 32-bit and 64-bit. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tci/tcg-target-con-set.h | 6 +- tcg/tci/tcg-target.h | 3 - tcg/tci.c | 189 +++++++++++++---------------------- tcg/tci/tcg-target.c.inc | 82 ++++----------- 4 files changed, 89 insertions(+), 191 deletions(-) diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h index 38e82f7535..f51b7bcb13 100644 --- a/tcg/tci/tcg-target-con-set.h +++ b/tcg/tci/tcg-target-con-set.h @@ -10,16 +10,12 @@ * tcg-target-con-str.h; the constraint combination is inclusive or. */ C_O0_I2(r, r) -C_O0_I2(r, ri) C_O0_I3(r, r, r) -C_O0_I4(r, r, ri, ri) C_O0_I4(r, r, r, r) C_O1_I1(r, r) C_O1_I2(r, 0, r) -C_O1_I2(r, ri, ri) C_O1_I2(r, r, r) -C_O1_I2(r, r, ri) -C_O1_I4(r, r, r, ri, ri) +C_O1_I4(r, r, r, r, r) C_O2_I1(r, r, r) C_O2_I2(r, r, r, r) C_O2_I4(r, r, r, r, r, r) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 8f7ed676fc..9c0021a26f 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -157,9 +157,6 @@ typedef enum { =20 TCG_AREG0 =3D TCG_REG_R14, TCG_REG_CALL_STACK =3D TCG_REG_R15, - - /* Special value UINT8_MAX is used by TCI to encode constant values. */ - TCG_CONST =3D UINT8_MAX } TCGReg; =20 /* Used for function call generation. */ diff --git a/tcg/tci.c b/tcg/tci.c index 935eb87330..fb3c97aaf1 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -255,61 +255,6 @@ tci_read_ulong(const tcg_target_ulong *regs, const uin= t8_t **tb_ptr) return taddr; } =20 -/* Read indexed register or constant (native size) from bytecode. */ -static tcg_target_ulong -tci_read_ri(const tcg_target_ulong *regs, const uint8_t **tb_ptr) -{ - tcg_target_ulong value; - TCGReg r =3D **tb_ptr; - *tb_ptr +=3D 1; - if (r =3D=3D TCG_CONST) { - value =3D tci_read_i(tb_ptr); - } else { - value =3D tci_read_reg(regs, r); - } - return value; -} - -/* Read indexed register or constant (32 bit) from bytecode. */ -static uint32_t tci_read_ri32(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - uint32_t value; - TCGReg r =3D **tb_ptr; - *tb_ptr +=3D 1; - if (r =3D=3D TCG_CONST) { - value =3D tci_read_i32(tb_ptr); - } else { - value =3D tci_read_reg32(regs, r); - } - return value; -} - -#if TCG_TARGET_REG_BITS =3D=3D 32 -/* Read two indexed registers or constants (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_ri64(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - uint32_t low =3D tci_read_ri32(regs, tb_ptr); - return tci_uint64(tci_read_ri32(regs, tb_ptr), low); -} -#elif TCG_TARGET_REG_BITS =3D=3D 64 -/* Read indexed register or constant (64 bit) from bytecode. */ -static uint64_t tci_read_ri64(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - uint64_t value; - TCGReg r =3D **tb_ptr; - *tb_ptr +=3D 1; - if (r =3D=3D TCG_CONST) { - value =3D tci_read_i64(tb_ptr); - } else { - value =3D tci_read_reg64(regs, r); - } - return value; -} -#endif - static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) { tcg_target_ulong label =3D tci_read_i(tb_ptr); @@ -504,7 +449,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, =20 switch (opc) { case INDEX_op_call: - t0 =3D tci_read_ri(regs, &tb_ptr); + t0 =3D tci_read_i(&tb_ptr); tci_tb_ptr =3D (uintptr_t)tb_ptr; #if TCG_TARGET_REG_BITS =3D=3D 32 tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), @@ -539,7 +484,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_setcond_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); condition =3D *tb_ptr++; tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); break; @@ -547,7 +492,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_setcond2_i32: t0 =3D *tb_ptr++; tmp64 =3D tci_read_r64(regs, &tb_ptr); - v64 =3D tci_read_ri64(regs, &tb_ptr); + v64 =3D tci_read_r64(regs, &tb_ptr); condition =3D *tb_ptr++; tci_write_reg(regs, t0, tci_compare64(tmp64, v64, condition)); break; @@ -555,7 +500,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_setcond_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); condition =3D *tb_ptr++; tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; @@ -628,62 +573,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_add_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(regs, &tb_ptr); - t2 =3D tci_read_ri32(regs, &tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; case INDEX_op_sub_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(regs, &tb_ptr); - t2 =3D tci_read_ri32(regs, &tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; case INDEX_op_mul_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(regs, &tb_ptr); - t2 =3D tci_read_ri32(regs, &tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; case INDEX_op_div_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(regs, &tb_ptr); - t2 =3D tci_read_ri32(regs, &tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); break; case INDEX_op_divu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(regs, &tb_ptr); - t2 =3D tci_read_ri32(regs, &tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tci_write_reg(regs, t0, t1 / t2); break; case INDEX_op_rem_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(regs, &tb_ptr); - t2 =3D tci_read_ri32(regs, &tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); break; case INDEX_op_remu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(regs, &tb_ptr); - t2 =3D tci_read_ri32(regs, &tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tci_write_reg(regs, t0, t1 % t2); break; case INDEX_op_and_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(regs, &tb_ptr); - t2 =3D tci_read_ri32(regs, &tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tci_write_reg(regs, t0, t1 & t2); break; case INDEX_op_or_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(regs, &tb_ptr); - t2 =3D tci_read_ri32(regs, &tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tci_write_reg(regs, t0, t1 | t2); break; case INDEX_op_xor_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(regs, &tb_ptr); - t2 =3D tci_read_ri32(regs, &tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tci_write_reg(regs, t0, t1 ^ t2); break; =20 @@ -691,33 +636,33 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_shl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(regs, &tb_ptr); - t2 =3D tci_read_ri32(regs, &tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tci_write_reg(regs, t0, t1 << (t2 & 31)); break; case INDEX_op_shr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(regs, &tb_ptr); - t2 =3D tci_read_ri32(regs, &tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tci_write_reg(regs, t0, t1 >> (t2 & 31)); break; case INDEX_op_sar_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(regs, &tb_ptr); - t2 =3D tci_read_ri32(regs, &tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tci_write_reg(regs, t0, ((int32_t)t1 >> (t2 & 31))); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(regs, &tb_ptr); - t2 =3D tci_read_ri32(regs, &tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tci_write_reg(regs, t0, rol32(t1, t2 & 31)); break; case INDEX_op_rotr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(regs, &tb_ptr); - t2 =3D tci_read_ri32(regs, &tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tci_write_reg(regs, t0, ror32(t1, t2 & 31)); break; #endif @@ -734,7 +679,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif case INDEX_op_brcond_i32: t0 =3D tci_read_r32(regs, &tb_ptr); - t1 =3D tci_read_ri32(regs, &tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare32(t0, t1, condition)) { @@ -760,7 +705,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; case INDEX_op_brcond2_i32: tmp64 =3D tci_read_r64(regs, &tb_ptr); - v64 =3D tci_read_ri64(regs, &tb_ptr); + v64 =3D tci_read_r64(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(tmp64, v64, condition)) { @@ -870,62 +815,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_add_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(regs, &tb_ptr); - t2 =3D tci_read_ri64(regs, &tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; case INDEX_op_sub_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(regs, &tb_ptr); - t2 =3D tci_read_ri64(regs, &tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; case INDEX_op_mul_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(regs, &tb_ptr); - t2 =3D tci_read_ri64(regs, &tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; case INDEX_op_div_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(regs, &tb_ptr); - t2 =3D tci_read_ri64(regs, &tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); break; case INDEX_op_divu_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(regs, &tb_ptr); - t2 =3D tci_read_ri64(regs, &tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); break; case INDEX_op_rem_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(regs, &tb_ptr); - t2 =3D tci_read_ri64(regs, &tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); break; case INDEX_op_remu_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(regs, &tb_ptr); - t2 =3D tci_read_ri64(regs, &tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; case INDEX_op_and_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(regs, &tb_ptr); - t2 =3D tci_read_ri64(regs, &tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tci_write_reg(regs, t0, t1 & t2); break; case INDEX_op_or_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(regs, &tb_ptr); - t2 =3D tci_read_ri64(regs, &tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tci_write_reg(regs, t0, t1 | t2); break; case INDEX_op_xor_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(regs, &tb_ptr); - t2 =3D tci_read_ri64(regs, &tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tci_write_reg(regs, t0, t1 ^ t2); break; =20 @@ -933,33 +878,33 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_shl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(regs, &tb_ptr); - t2 =3D tci_read_ri64(regs, &tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tci_write_reg(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(regs, &tb_ptr); - t2 =3D tci_read_ri64(regs, &tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tci_write_reg(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(regs, &tb_ptr); - t2 =3D tci_read_ri64(regs, &tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(regs, &tb_ptr); - t2 =3D tci_read_ri64(regs, &tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tci_write_reg(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(regs, &tb_ptr); - t2 =3D tci_read_ri64(regs, &tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tci_write_reg(regs, t0, ror64(t1, t2 & 63)); break; #endif @@ -976,7 +921,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif case INDEX_op_brcond_i64: t0 =3D tci_read_r64(regs, &tb_ptr); - t1 =3D tci_read_ri64(regs, &tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 1b66368c94..feac4659cc 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -92,8 +92,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode = op) case INDEX_op_rem_i64: case INDEX_op_remu_i32: case INDEX_op_remu_i64: - return C_O1_I2(r, r, r); - case INDEX_op_add_i32: case INDEX_op_add_i64: case INDEX_op_sub_i32: @@ -126,8 +124,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcod= e op) case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: - /* TODO: Does R, RI, RI result in faster code than R, R, RI? */ - return C_O1_I2(r, ri, ri); + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + return C_O1_I2(r, r, r); =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: @@ -135,11 +134,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpco= de op) =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return C_O0_I2(r, ri); - - case INDEX_op_setcond_i32: - case INDEX_op_setcond_i64: - return C_O1_I2(r, r, ri); + return C_O0_I2(r, r); =20 #if TCG_TARGET_REG_BITS =3D=3D 32 /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */ @@ -147,11 +142,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_sub2_i32: return C_O2_I4(r, r, r, r, r, r); case INDEX_op_brcond2_i32: - return C_O0_I4(r, r, ri, ri); + return C_O0_I4(r, r, r, r); case INDEX_op_mulu2_i32: return C_O2_I2(r, r, r, r); case INDEX_op_setcond2_i32: - return C_O1_I4(r, r, r, ri, ri); + return C_O1_I4(r, r, r, r, r); #endif =20 case INDEX_op_qemu_ld_i32: @@ -294,41 +289,6 @@ static void tcg_out_r(TCGContext *s, TCGArg t0) tcg_out8(s, t0); } =20 -/* Write register or constant (native size). */ -static void tcg_out_ri(TCGContext *s, bool const_arg, TCGArg arg) -{ - if (const_arg) { - tcg_out8(s, TCG_CONST); - tcg_out_i(s, arg); - } else { - tcg_out_r(s, arg); - } -} - -/* Write register or constant (32 bit). */ -static void tcg_out_ri32(TCGContext *s, bool const_arg, TCGArg arg) -{ - if (const_arg) { - tcg_out8(s, TCG_CONST); - tcg_out32(s, arg); - } else { - tcg_out_r(s, arg); - } -} - -#if TCG_TARGET_REG_BITS =3D=3D 64 -/* Write register or constant (64 bit). */ -static void tcg_out_ri64(TCGContext *s, bool const_arg, TCGArg arg) -{ - if (const_arg) { - tcg_out8(s, TCG_CONST); - tcg_out64(s, arg); - } else { - tcg_out_r(s, arg); - } -} -#endif - /* Write label. */ static void tci_out_label(TCGContext *s, TCGLabel *label) { @@ -416,7 +376,7 @@ static inline void tcg_out_call(TCGContext *s, const tc= g_insn_unit *arg) { uint8_t *old_code_ptr =3D s->code_ptr; tcg_out_op_t(s, INDEX_op_call); - tcg_out_ri(s, 1, (uintptr_t)arg); + tcg_out_i(s, (uintptr_t)arg); old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 @@ -450,7 +410,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, case INDEX_op_setcond_i32: tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); - tcg_out_ri32(s, const_args[2], args[2]); + tcg_out_r(s, args[2]); tcg_out8(s, args[3]); /* condition */ break; #if TCG_TARGET_REG_BITS =3D=3D 32 @@ -459,15 +419,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); - tcg_out_ri32(s, const_args[3], args[3]); - tcg_out_ri32(s, const_args[4], args[4]); + tcg_out_r(s, args[3]); + tcg_out_r(s, args[4]); tcg_out8(s, args[5]); /* condition */ break; #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); - tcg_out_ri64(s, const_args[2], args[2]); + tcg_out_r(s, args[2]); tcg_out8(s, args[3]); /* condition */ break; #endif @@ -513,8 +473,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ tcg_out_r(s, args[0]); - tcg_out_ri32(s, const_args[1], args[1]); - tcg_out_ri32(s, const_args[2], args[2]); + tcg_out_r(s, args[1]); + tcg_out_r(s, args[2]); break; case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). = */ tcg_out_r(s, args[0]); @@ -548,8 +508,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ tcg_out_r(s, args[0]); - tcg_out_ri64(s, const_args[1], args[1]); - tcg_out_ri64(s, const_args[2], args[2]); + tcg_out_r(s, args[1]); + tcg_out_r(s, args[2]); break; case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). = */ tcg_out_r(s, args[0]); @@ -562,7 +522,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, break; case INDEX_op_brcond_i64: tcg_out_r(s, args[0]); - tcg_out_ri64(s, const_args[1], args[1]); + tcg_out_r(s, args[1]); tcg_out8(s, args[2]); /* condition */ tci_out_label(s, arg_label(args[3])); break; @@ -596,8 +556,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ tcg_out_r(s, args[0]); - tcg_out_ri32(s, const_args[1], args[1]); - tcg_out_ri32(s, const_args[2], args[2]); + tcg_out_r(s, args[1]); + tcg_out_r(s, args[2]); break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: @@ -612,8 +572,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, case INDEX_op_brcond2_i32: tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); - tcg_out_ri32(s, const_args[2], args[2]); - tcg_out_ri32(s, const_args[3], args[3]); + tcg_out_r(s, args[2]); + tcg_out_r(s, args[3]); tcg_out8(s, args[4]); /* condition */ tci_out_label(s, arg_label(args[5])); break; @@ -626,7 +586,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, #endif case INDEX_op_brcond_i32: tcg_out_r(s, args[0]); - tcg_out_ri32(s, const_args[1], args[1]); + tcg_out_r(s, args[1]); tcg_out8(s, args[2]); /* condition */ tci_out_label(s, arg_label(args[3])); break; --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404111; cv=none; d=zohomail.com; s=zohoarc; b=Abzf1B9PRKalQpvsc5/1Dz4/2UPf3De+iZwhPMMWNLNl+fJd6ULdi79q1GC/M7JNOcMM3U76TOUg5jBjtWgk9CKSi2vgN8iiR0ApM09+yl1kMokHtqnL9W5xfMPsjmJqfNm8hVWlRa1IQdctoEojjHCEaKxjwIQ0CGykv4ozsaQ= ARC-Message-Signature: i=1; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VvjDH0d9yENa4ecfbUN1MGRyNECdD1MomwyxKEWSk7s=; b=kqnV9YjOYJgmVdcO4T69+y/u0xlnuLELHgVW2m+tzQ+FTKfuq6vHdNmxg1OyaY9EdY K317YvML7dpSXswW4TLV7qbxiqmq/wMWaohudkegdSNrBMaguJerU7j29cM75AyDEzGj HhX9VbkJF/V9PjHhnubty3zHtkWDAv/UDjmrUn36EntFo+sLeZG5t5G1P2W2Q4EAy4NG PPF6iZlhB6o7uni8+GjMN2fhaPk4LQOflA0iWYojd8EC3N+VlWfoDQmSigieOCH6P0bu p+OamfxsnNguUSHC73BzW3K5Yfe6eyWH/AYQfh+3WfqParhE+0htIbCyKcTVUh5+QMM6 9+Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VvjDH0d9yENa4ecfbUN1MGRyNECdD1MomwyxKEWSk7s=; b=F87HR8V+4flZOpft63E4n6OxVJX4zoYxFHKxG+EPd1Q/yKp9W0bB3somHM4zJRsrio KYopM0IuN+cakNYkMsCP0GG0R+Ity0C1IbizEoJZbV6G2HjN4wXAoUBRtucLekW41PiH PrshFHS0IB+Smvqqq2WvHkaBXSlKeP+dV6AVkdLOMQSjrPkqMPClcOWgR3bIlWcb0w0c MKcG8Dh7pB4BlfXdEmzTmrh3jHbRngpHGUr+GNGnuxTn1CfWGl58/XwVhCOCPHd+WvYq xz2BTcTbtbVA/JyKU7svJo1qURzr9qnDrHyNAUVzG2kELSIRHXKrmz2Dkn4znsNfBvMZ deag== X-Gm-Message-State: AOAM5317/DRB8fe0Mg5UT9f/vPHC2OFRsyrCUTekJw3EgJZD8iK/pXna 0JV+FRco67Jml2VLHQtEW9LoFVMK/GIIifj4 X-Google-Smtp-Source: ABdhPJzXf0rp6plUD7pGbcLClXnzVrgf5Ve7DQZRoQEmgQ/dN/yZl0kKW0Vfkb3zHC96yGWBPFO4GQ== X-Received: by 2002:a17:903:3049:b029:e2:8af3:76ec with SMTP id u9-20020a1709033049b02900e28af376ecmr4797749pla.51.1612403167272; Wed, 03 Feb 2021 17:46:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 30/93] tcg/tci: Merge identical cases in generation Date: Wed, 3 Feb 2021 15:44:06 -1000 Message-Id: <20210204014509.882821-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 204 ++++++++++++++------------------------- 1 file changed, 73 insertions(+), 131 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index feac4659cc..c79f9c32d8 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -380,6 +380,18 @@ static inline void tcg_out_call(TCGContext *s, const t= cg_insn_unit *arg) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +#if TCG_TARGET_REG_BITS =3D=3D 64 +# define CASE_32_64(x) \ + case glue(glue(INDEX_op_, x), _i64): \ + case glue(glue(INDEX_op_, x), _i32): +# define CASE_64(x) \ + case glue(glue(INDEX_op_, x), _i64): +#else +# define CASE_32_64(x) \ + case glue(glue(INDEX_op_, x), _i32): +# define CASE_64(x) +#endif + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { @@ -391,6 +403,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, case INDEX_op_exit_tb: tcg_out64(s, args[0]); break; + case INDEX_op_goto_tb: if (s->tb_jmp_insn_offset) { /* Direct jump method. */ @@ -404,15 +417,18 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, } set_jmp_reset_offset(s, args[0]); break; + case INDEX_op_br: tci_out_label(s, arg_label(args[0])); break; - case INDEX_op_setcond_i32: + + CASE_32_64(setcond) tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out8(s, args[3]); /* condition */ break; + #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */ @@ -423,60 +439,54 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, tcg_out_r(s, args[4]); tcg_out8(s, args[5]); /* condition */ break; -#elif TCG_TARGET_REG_BITS =3D=3D 64 - case INDEX_op_setcond_i64: - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out8(s, args[3]); /* condition */ - break; #endif - case INDEX_op_ld8u_i32: - case INDEX_op_ld8s_i32: - case INDEX_op_ld16u_i32: - case INDEX_op_ld16s_i32: + + CASE_32_64(ld8u) + CASE_32_64(ld8s) + CASE_32_64(ld16u) + CASE_32_64(ld16s) case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: + CASE_64(ld32u) + CASE_64(ld32s) + CASE_64(ld) + CASE_32_64(st8) + CASE_32_64(st16) case INDEX_op_st_i32: - case INDEX_op_ld8u_i64: - case INDEX_op_ld8s_i64: - case INDEX_op_ld16u_i64: - case INDEX_op_ld16s_i64: - case INDEX_op_ld32u_i64: - case INDEX_op_ld32s_i64: - case INDEX_op_ld_i64: - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: + CASE_64(st32) + CASE_64(st) stack_bounds_check(args[1], args[2]); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_debug_assert(args[2] =3D=3D (int32_t)args[2]); tcg_out32(s, args[2]); break; - case INDEX_op_add_i32: - case INDEX_op_sub_i32: - case INDEX_op_mul_i32: - case INDEX_op_and_i32: - case INDEX_op_andc_i32: /* Optional (TCG_TARGET_HAS_andc_i32). */ - case INDEX_op_eqv_i32: /* Optional (TCG_TARGET_HAS_eqv_i32). */ - case INDEX_op_nand_i32: /* Optional (TCG_TARGET_HAS_nand_i32). */ - case INDEX_op_nor_i32: /* Optional (TCG_TARGET_HAS_nor_i32). */ - case INDEX_op_or_i32: - case INDEX_op_orc_i32: /* Optional (TCG_TARGET_HAS_orc_i32). */ - case INDEX_op_xor_i32: - case INDEX_op_shl_i32: - case INDEX_op_shr_i32: - case INDEX_op_sar_i32: - case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ - case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ + + CASE_32_64(add) + CASE_32_64(sub) + CASE_32_64(mul) + CASE_32_64(and) + CASE_32_64(or) + CASE_32_64(xor) + CASE_32_64(andc) /* Optional (TCG_TARGET_HAS_andc_*). */ + CASE_32_64(orc) /* Optional (TCG_TARGET_HAS_orc_*). */ + CASE_32_64(eqv) /* Optional (TCG_TARGET_HAS_eqv_*). */ + CASE_32_64(nand) /* Optional (TCG_TARGET_HAS_nand_*). */ + CASE_32_64(nor) /* Optional (TCG_TARGET_HAS_nor_*). */ + CASE_32_64(shl) + CASE_32_64(shr) + CASE_32_64(sar) + CASE_32_64(rotl) /* Optional (TCG_TARGET_HAS_rot_*). */ + CASE_32_64(rotr) /* Optional (TCG_TARGET_HAS_rot_*). */ + CASE_32_64(div) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); break; - case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). = */ + + CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); @@ -486,79 +496,30 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, tcg_out8(s, args[4]); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 - case INDEX_op_add_i64: - case INDEX_op_sub_i64: - case INDEX_op_mul_i64: - case INDEX_op_and_i64: - case INDEX_op_andc_i64: /* Optional (TCG_TARGET_HAS_andc_i64). */ - case INDEX_op_eqv_i64: /* Optional (TCG_TARGET_HAS_eqv_i64). */ - case INDEX_op_nand_i64: /* Optional (TCG_TARGET_HAS_nand_i64). */ - case INDEX_op_nor_i64: /* Optional (TCG_TARGET_HAS_nor_i64). */ - case INDEX_op_or_i64: - case INDEX_op_orc_i64: /* Optional (TCG_TARGET_HAS_orc_i64). */ - case INDEX_op_xor_i64: - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ - case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ - case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - break; - case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). = */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_debug_assert(args[3] <=3D UINT8_MAX); - tcg_out8(s, args[3]); - tcg_debug_assert(args[4] <=3D UINT8_MAX); - tcg_out8(s, args[4]); - break; - case INDEX_op_brcond_i64: + CASE_32_64(brcond) tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out8(s, args[2]); /* condition */ tci_out_label(s, arg_label(args[3])); break; - case INDEX_op_bswap16_i64: /* Optional (TCG_TARGET_HAS_bswap16_i64). = */ - case INDEX_op_bswap32_i64: /* Optional (TCG_TARGET_HAS_bswap32_i64). = */ - case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). = */ - case INDEX_op_not_i64: /* Optional (TCG_TARGET_HAS_not_i64). */ - case INDEX_op_neg_i64: /* Optional (TCG_TARGET_HAS_neg_i64). */ - case INDEX_op_ext8s_i64: /* Optional (TCG_TARGET_HAS_ext8s_i64). */ - case INDEX_op_ext8u_i64: /* Optional (TCG_TARGET_HAS_ext8u_i64). */ - case INDEX_op_ext16s_i64: /* Optional (TCG_TARGET_HAS_ext16s_i64). */ - case INDEX_op_ext16u_i64: /* Optional (TCG_TARGET_HAS_ext16u_i64). */ - case INDEX_op_ext32s_i64: /* Optional (TCG_TARGET_HAS_ext32s_i64). */ - case INDEX_op_ext32u_i64: /* Optional (TCG_TARGET_HAS_ext32u_i64). */ - case INDEX_op_ext_i32_i64: - case INDEX_op_extu_i32_i64: -#endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ - case INDEX_op_neg_i32: /* Optional (TCG_TARGET_HAS_neg_i32). */ - case INDEX_op_not_i32: /* Optional (TCG_TARGET_HAS_not_i32). */ - case INDEX_op_ext8s_i32: /* Optional (TCG_TARGET_HAS_ext8s_i32). */ - case INDEX_op_ext16s_i32: /* Optional (TCG_TARGET_HAS_ext16s_i32). */ - case INDEX_op_ext8u_i32: /* Optional (TCG_TARGET_HAS_ext8u_i32). */ - case INDEX_op_ext16u_i32: /* Optional (TCG_TARGET_HAS_ext16u_i32). */ - case INDEX_op_bswap16_i32: /* Optional (TCG_TARGET_HAS_bswap16_i32). = */ - case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). = */ + + CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ + CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */ + CASE_32_64(ext8s) /* Optional (TCG_TARGET_HAS_ext8s_*). */ + CASE_32_64(ext8u) /* Optional (TCG_TARGET_HAS_ext8u_*). */ + CASE_32_64(ext16s) /* Optional (TCG_TARGET_HAS_ext16s_*). */ + CASE_32_64(ext16u) /* Optional (TCG_TARGET_HAS_ext16u_*). */ + CASE_64(ext32s) /* Optional (TCG_TARGET_HAS_ext32s_i64). */ + CASE_64(ext32u) /* Optional (TCG_TARGET_HAS_ext32u_i64). */ + CASE_64(ext_i32) + CASE_64(extu_i32) + CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ + CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ + CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); break; - case INDEX_op_div_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - case INDEX_op_divu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - break; + #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: @@ -584,31 +545,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, tcg_out_r(s, args[3]); break; #endif - case INDEX_op_brcond_i32: - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out8(s, args[2]); /* condition */ - tci_out_label(s, arg_label(args[3])); - break; + case INDEX_op_qemu_ld_i32: - tcg_out_r(s, *args++); - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out_i(s, *args++); - break; - case INDEX_op_qemu_ld_i64: - tcg_out_r(s, *args++); - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_r(s, *args++); - } - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out_i(s, *args++); - break; case INDEX_op_qemu_st_i32: tcg_out_r(s, *args++); tcg_out_r(s, *args++); @@ -617,6 +555,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, } tcg_out_i(s, *args++); break; + + case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: tcg_out_r(s, *args++); if (TCG_TARGET_REG_BITS =3D=3D 32) { @@ -628,8 +568,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, } tcg_out_i(s, *args++); break; + case INDEX_op_mb: break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YWPrxfItN4c65pZ/52Q4dTydvUr4VWbYL6z0GHLhLqg=; b=UpeJHkCgV3/5jo1hf1cY8gdP8Ua+rSj+fkpc9e5QNzx1wwBMjQQ7UNCi0T0EM4Gjh3 o1UnlpZq8bOI7967lE3iRadQ+KXQnDS/MPgEX253JL1Digf7BdryWm3Uy13Tch4u4oac RTXaFiMJLx6Mp/EBdr1VxBqDHeISmG3kYjRBxPQol1kZd8Pr91ZkXuri6k/nNPNLhHBs 2xdlj8qmnens6tZvG1whtvx/UcdJNYX8hy0H7Ej72VsLOWVbr6fxyOdqEVUx38VevdFe yIkRlXNTlnE37M40cRIsvQpVCHQeeVLnl1zYqV4k//AYJ8u9J6UusXDEGfusxYwai8un XG1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YWPrxfItN4c65pZ/52Q4dTydvUr4VWbYL6z0GHLhLqg=; b=Lp67mZaWp/fTHSdV8CFHYb53ejwAnZy/c1saJ1m5PUFaiDPDQD1wfnd55qyQSJ2SPT Au8eZIJYzvgW6HPYzIljuGUqiWMXp8nWJGaRbDU06dVZ1sORAwlSKrpdVjAWu88XcNT8 MHDE5jUnBTlAf4r1p25Nc6nqY4IVw3+VesiAJTZfT5Ii6ZvpSGLezQdcy9+FrKpdcK9G 219KEdGKbph9gic6oOmn0PK5OCbRwKt7S9pluzTdozVsETB3i6F+8rh68pI73g95uG6O tdwomimwQWm0wOOcXfsWeUPZO6t56qfwn6NsdLnPYcomWYdo4BsF+sv37iMhH6ey2EJG gdxA== X-Gm-Message-State: AOAM532MF5EpaTUYuO2bVg10BKyMTv66kLbGTuduj1X26ZuFRpASwZuW NyqnrnbhhimxczsOJQMg5KbO4GB9Iz4cBn8b X-Google-Smtp-Source: ABdhPJz1LqNue1aOI1vw1IqArOKAMRBn0eSAm8ofDTmvf9SAdFhSeHYtt3TFOmUAr2BaoQiIBjhdPA== X-Received: by 2002:a62:7ac4:0:b029:1bc:309a:46d3 with SMTP id v187-20020a627ac40000b02901bc309a46d3mr5717481pfc.18.1612403168784; Wed, 03 Feb 2021 17:46:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 31/93] tcg/tci: Remove tci_read_r8 Date: Wed, 3 Feb 2021 15:44:07 -1000 Message-Id: <20210204014509.882821-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use explicit casts for ext8u opcodes, and allow truncation to happen with the store for st8 opcodes. Signed-off-by: Richard Henderson --- tcg/tci.c | 23 +++++------------------ 1 file changed, 5 insertions(+), 18 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index fb3c97aaf1..c44a4aec7b 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -78,11 +78,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *r= egs, TCGReg index) } #endif =20 -static uint8_t tci_read_reg8(const tcg_target_ulong *regs, TCGReg index) -{ - return (uint8_t)tci_read_reg(regs, index); -} - static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index) { return (uint16_t)tci_read_reg(regs, index); @@ -169,14 +164,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t= **tb_ptr) return value; } =20 -/* Read indexed register (8 bit) from bytecode. */ -static uint8_t tci_read_r8(const tcg_target_ulong *regs, const uint8_t **t= b_ptr) -{ - uint8_t value =3D tci_read_reg8(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} - #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 /* Read indexed register (8 bit signed) from bytecode. */ static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **t= b_ptr) @@ -550,7 +537,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); break; CASE_32_64(st8) - t0 =3D tci_read_r8(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) =3D t0; @@ -739,8 +726,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext8u_i32 case INDEX_op_ext8u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16u_i32 @@ -933,8 +920,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext8u_i64 case INDEX_op_ext8u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint8_t)t1); break; #endif #if TCG_TARGET_HAS_ext8s_i64 --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404549; cv=none; d=zohomail.com; s=zohoarc; b=CE15MCUe4j4lz7ENQQOcwvAX7OcMHQ228aC6pAjo7HwH/YzgiCQDzshGM4Xoo1S5S+SIAyOG/Gim1ibNGG0o01SaMuBEQ+p09odm5rxFsrzxaVpa22V1M0h9N5zErYKURylebYke0tmqTHmF3cI21GkNXt37ibEKu1XbrFSBSYA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612404549; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=r7Bqt7XeLpJxFziax4YcAvS468lSm4SfB1qZvFnNDEY=; b=VVYPwVR1S20xrgbHfiK6diSK6cKHHE+sPyM3OMuhw6d+YPWr+J8c+Cn1HbSrdRjlPczEl2YFc6gOan7Jy4wJ12UUmlGmQyv6TP0HYX+Tf3CI6uiNt4yF+U6wsz5UilY3CA3hH6q/d+IuFPR23hiee2cjQGlmkFcd4/6e/LZCuM4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161240454987538.782503295372635; Wed, 3 Feb 2021 18:09:09 -0800 (PST) Received: from localhost ([::1]:40640 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7U4x-0007rC-2D for importer@patchew.org; Wed, 03 Feb 2021 21:09:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44716) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Tiw-0005F0-Fi for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:24 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:55429) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tin-0003vB-0S for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:22 -0500 Received: by mail-pj1-x1029.google.com with SMTP id s24so767912pjp.5 for ; Wed, 03 Feb 2021 17:46:11 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=r7Bqt7XeLpJxFziax4YcAvS468lSm4SfB1qZvFnNDEY=; b=rEFA1nE061rSgny28wXa4XZZSe36PAPAl1om1bEleHfoX2Xqyzig/BnjvLI8i1KZ0b gre2WSHy+HJdGcV4c596nLFSTjgi2UA+eEFUumQwlQiycuhRsDYBEYUhoe3FUOBDYoOh 8T+BQlkJmaULIE0J4JikgXQiflEwvOGCUKgvfuNeJZDX1/peCxwyS9kAM7luK3tl5Wiu otl2NUH02t3Cy/n+YfqcXjVUfb1xOWgfaMX39bUQUDELaEa6L7Eh1ABX4GMbrPwUPqgj K284ywuXluhGN5rsQsozpOsllJpLmUZwvqQtF/5iTq/y4sm1odCYoqu4rlKZDflCTfEe DvHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r7Bqt7XeLpJxFziax4YcAvS468lSm4SfB1qZvFnNDEY=; b=mB5dxXsqsgT5j5tHWcakERDHRPwA0vqVgYDYnQU7l5ZBFYKkW4XKNgzQ7/Vep93E9b OBXM/gfY1BSEzLR9LlN18wyHb7yJlf4ZfBqGvKs8d+ipW453sKAfBeh5x25veaW/mLJ8 lDYu1PO3cfC+/lOKRYn1eaDhxPiEcujEgIWc4NhVXt8JqTVmTgoKOGWgjKS48nXxViYk wFEpyM3SLFBTq67wiSS/xRLDih7u5hdqT9HIG+0LDArY0i1239IiYtAkVr4a6JEjHUZ/ csWBMzR1xb1/qdYpvA2swH+dEYbHfPOa7JM1KiK+hJPtTq+z8iY184zw3Iu5o6S9bo/C igmg== X-Gm-Message-State: AOAM532jFsbcaundseiCJVb2cSyjK0b+Uk32RwXM/K/EBh/xhxFBL8KU DOewg/yHusaYKuw4MwRWW5NbN970YeqL6c77 X-Google-Smtp-Source: ABdhPJy31zrhNUUktb0os9EJ+FIwccQ58zBe4HnQ3nUaoSAArNUVpbZga2eQ9lm3GiEzKpC7V1eUKA== X-Received: by 2002:a17:902:e211:b029:e2:843c:426e with SMTP id u17-20020a170902e211b02900e2843c426emr5546451plb.16.1612403170356; Wed, 03 Feb 2021 17:46:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 32/93] tcg/tci: Remove tci_read_r8s Date: Wed, 3 Feb 2021 15:44:08 -1000 Message-Id: <20210204014509.882821-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use explicit casts for ext8s opcodes. Signed-off-by: Richard Henderson --- tcg/tci.c | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index c44a4aec7b..25db479e62 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ul= ong *regs, TCGReg index) return regs[index]; } =20 -#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -static int8_t tci_read_reg8s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int8_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) { @@ -164,16 +157,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t= **tb_ptr) return value; } =20 -#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -/* Read indexed register (8 bit signed) from bytecode. */ -static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **t= b_ptr) -{ - int8_t value =3D tci_read_reg8s(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} -#endif - /* Read indexed register (16 bit) from bytecode. */ static uint16_t tci_read_r16(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -712,8 +695,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext8s_i32 case INDEX_op_ext8s_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 @@ -927,8 +910,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext8s_i64 case INDEX_op_ext8s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i64 --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404672; cv=none; d=zohomail.com; s=zohoarc; b=QOXH25fVEfE7/eLcsupC3moVNpo5tWaRPL1Cvpt0N1WyypljSrokJ7Y57pkFp3n5sO7kxtlhYRP2ELs4OOSsISMD9cXFh8oHwynnzXLyTWPgB3JNAegTio6JEEmfd6JxsxJy6gNWmiOcHbPHnCvdQh5GUDg5KSFWhmfb1KRzHww= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612404672; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WwtU4XN3I/7BQWEoh7IwoY3+ESrnoHkEE2Q1sU/eyYI=; b=ZXLPcYeR0FU8GCQC0O+Dx7/cw5VdaZO1v4lo6FRCT7xJ1CY1sR79kRxxNoG8ZBbOPRGOfvqFgGQH7jTQpeaaI0MzTrrD2Z692cS2VCbkZKr6yGfta8mhv1EpGv3O0sMvSxSq0dRtzH93oJ6nWowi3SOVMnWzoKuM8hX2YavJPxo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612404672895330.42728415274144; Wed, 3 Feb 2021 18:11:12 -0800 (PST) Received: from localhost ([::1]:46178 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7U6x-0001nB-Eb for importer@patchew.org; Wed, 03 Feb 2021 21:11:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44776) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Tj1-0005IY-RV for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:31 -0500 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:38328) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tin-0003vJ-5i for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:26 -0500 Received: by mail-pf1-x430.google.com with SMTP id y205so1075141pfc.5 for ; Wed, 03 Feb 2021 17:46:12 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WwtU4XN3I/7BQWEoh7IwoY3+ESrnoHkEE2Q1sU/eyYI=; b=jUaSU7TB1TnycY8zIj9HVapyoDHalm5npBGBVq6N50IDErN5Fcx9aKMXf5lrqKijDk m9VSBXhanqEQsClO7iwc47IlJgkuPKhhn3tAdFixoSAAMNOYysnvq0WmmwnY478HCMtG IwGHQwxGEtvrxvUfIUXSLO4HMTkn0hWF4DbbbslEDOD1UxWFlhLCXp4Fu83kmCbkzedB /C7GjvqqQxFa6KSHkwzDjArlIwKKZ2wrOsmr7alA/5pRZU5dART/ZNENQSzAHb9r3u6g /6XcaHMraHqdDW11ZXmFUrvK/tvTBrOXBM7akbsKhJKgyeyJ1eQaEXi1bzV9pC9ccWj4 Ye8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WwtU4XN3I/7BQWEoh7IwoY3+ESrnoHkEE2Q1sU/eyYI=; b=Xx/O2WA/wEgpBayIoZ8Q8whUDmJ0aZ9XmXC8434Ia4FdZ9GIxTeag2RM/RieavimH8 VY8jOhYf2QsqqPjoApCeeSigPag392KtX+NTdN0XRWNAmQxVrUlMAuFCurBTwkZj0qQy shv9r4fYPP9q7oTvft9QqD5sECafXpcZyfMuD/+QzOdGPjrc6QbCJRrQ2XEJwHf9Iovj t/MshE+KvIwt+wRpQtvu1CSXKCuLU8EIsPfND5bx0oedu7oMx4JxOiuQJQpXlwaH1qFX /pDrDx+J9ghVBlle1uMc6b7VL+L7jS47LjeR6yxirpWEoS2Ip2JWPhkFcoWOO49Vccht rCeg== X-Gm-Message-State: AOAM531JwC64HHzFIqoTZrLm45R3B/nd8TVgWCNOk8pUVF94pRpHrBYc 6+Xck8nhUPYyBeqDyLTv6XocaWNYPB1xi5iZ X-Google-Smtp-Source: ABdhPJw0p2vAZuan/NAlCuAKFpbp0Pp6zmeR0N9b3QLg2me1SPam2V2z9go742k2t9bQ9Pc4ERKaFA== X-Received: by 2002:a63:43c6:: with SMTP id q189mr6565356pga.245.1612403171906; Wed, 03 Feb 2021 17:46:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 33/93] tcg/tci: Remove tci_read_r16 Date: Wed, 3 Feb 2021 15:44:09 -1000 Message-Id: <20210204014509.882821-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use explicit casts for ext16u opcodes, and allow truncation to happen with the store for st8 opcodes, and with the call for bswap16 opcodes. Signed-off-by: Richard Henderson --- tcg/tci.c | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 25db479e62..547be0c2f0 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -71,11 +71,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *r= egs, TCGReg index) } #endif =20 -static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index) -{ - return (uint16_t)tci_read_reg(regs, index); -} - static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index) { return (uint32_t)tci_read_reg(regs, index); @@ -157,15 +152,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t= **tb_ptr) return value; } =20 -/* Read indexed register (16 bit) from bytecode. */ -static uint16_t tci_read_r16(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - uint16_t value =3D tci_read_reg16(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} - #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 /* Read indexed register (16 bit signed) from bytecode. */ static int16_t tci_read_r16s(const tcg_target_ulong *regs, @@ -526,7 +512,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, *(uint8_t *)(t1 + t2) =3D t0; break; CASE_32_64(st16) - t0 =3D tci_read_r16(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) =3D t0; @@ -716,14 +702,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #if TCG_TARGET_HAS_ext16u_i32 case INDEX_op_ext16u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint16_t)t1); break; #endif #if TCG_TARGET_HAS_bswap16_i32 case INDEX_op_bswap16_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif @@ -924,8 +910,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext16u_i64 case INDEX_op_ext16u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint16_t)t1); break; #endif #if TCG_TARGET_HAS_ext32s_i64 @@ -947,7 +933,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_bswap16_i64 case INDEX_op_bswap16_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404400; cv=none; d=zohomail.com; s=zohoarc; b=LWVWALVcdUGMA1F1uoPtPU2fvhmS7TAjrvDi02Zhzp26yy3+BlWY/4BBhSp3fTeJjA08hEFyeThtH6Z/1fMImLn75OeTlCHk/G1PTMnB5najJGfsqRr8Q2scbHRM0YdWndvUJ8AcvtQZcCI7DtApPGHMio5EvCXKxkwA6f1UVaE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612404400; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=afvqbbQ97M3vRazhloBXxdPonlEgZwJG3R71ZxT6Uq4=; b=YFu9j9zEeZPhWrO2LPlCpLkV1BwFXY+e42oRr0Mk5ObqSqKBI963rFyMcQ89gBQTpDro0eMhWSg0+cqtbW4relN4xzEF+M76re9pL+cwKnje2HKXKLcCY0GVN8uq1n67Sp+8nl1hLcnq5ixFcfJU/yALARzH28tZqLiJ9546RJg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612404400381689.248807633942; Wed, 3 Feb 2021 18:06:40 -0800 (PST) Received: from localhost ([::1]:32774 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7U2Z-0004VR-4C for importer@patchew.org; Wed, 03 Feb 2021 21:06:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44788) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Tj3-0005Ix-Rt for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:31 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:44897) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tio-0003vT-Vj for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:29 -0500 Received: by mail-pl1-x634.google.com with SMTP id j11so872286plt.11 for ; Wed, 03 Feb 2021 17:46:14 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=afvqbbQ97M3vRazhloBXxdPonlEgZwJG3R71ZxT6Uq4=; b=pLHgDKqYpMLN+RZsSBV72LtUuXEBRwSc2nmPs01ufYffbHacNCgtMob2g0yg7lg179 gsqsCY/rvCW3xHf2VsBhy5EO63oOJAiGsxw1RchlrPeGQwCKX7kJqzzysf2IH6uaM54Z 6NWbHuaDaYR4s44almgeBobBPJ9rwT33DJVf4MsIbfnNkqZ5RIFaUbwQYxU2q5nnvAOu 0yJD1rejHa5a/m29PaqO7RK3BJnNYqpArHrCXmbLnKZUZ8LskVBXEsgE8/QZIWyoOsSs dFldw72hZ0+CiSYjnM6iz7gTusyplacmlNtUn66HRQvhJzcW3Dmbse7tsiqDduF/ydcr MiPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=afvqbbQ97M3vRazhloBXxdPonlEgZwJG3R71ZxT6Uq4=; b=cyTpbsRKlPfAMuzUg3ZVjl5+ZoSJrVmEf0mWHoKH+gbzm3I5u0nLxxsmp4N/g789YQ cWFs+tztPLXrO62tbJgGWDcpm60pUuvoS4v7pA19cMa9bWqGfrSReJbPCTi4zRbRBnrG qzvIsEVUZDqLRUDiT3mGecbU/MRbURWJSRtLKzJRdxQTpL7ECRX4xl1bj80PX6Q8UYwe yofW6FNrkQ1oa9GtdjCxM4W2EfwvMZApKEzT3KQRBVsHT4f5A9bOtBQ0rBIiqmYvPhM6 GjgTNTybWvEo1xx8yc5dkHZM+foEH+qns5IbLI7U3UBATHG76mE3DMxwgatU5Tj0cOTZ YuKQ== X-Gm-Message-State: AOAM530GMjq13GNWAMl+bnaDoQeDCWlnAW+Dn3UHruAkqVYYJHwHsRfZ 9ma1DBDRNyaQXT1V0LnKqPHc5TpNjP563734 X-Google-Smtp-Source: ABdhPJwLo9eMRHasob6qK34xxrizMAANpp4mbs0cPbm0gMDY4nZue92Ah5EPzHvyU4MdA69DXfDGuQ== X-Received: by 2002:a17:902:c284:b029:e1:8863:b3d6 with SMTP id i4-20020a170902c284b02900e18863b3d6mr5690198pld.64.1612403173732; Wed, 03 Feb 2021 17:46:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 34/93] tcg/tci: Remove tci_read_r16s Date: Wed, 3 Feb 2021 15:44:10 -1000 Message-Id: <20210204014509.882821-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use explicit casts for ext16s opcodes. Signed-off-by: Richard Henderson --- tcg/tci.c | 148 +++++++++++++++++++++--------------------------------- 1 file changed, 58 insertions(+), 90 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 547be0c2f0..72ec63e18e 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ul= ong *regs, TCGReg index) return regs[index]; } =20 -#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int16_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_REG_BITS =3D=3D 64 static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) { @@ -71,11 +64,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *r= egs, TCGReg index) } #endif =20 -static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index) -{ - return (uint32_t)tci_read_reg(regs, index); -} - #if TCG_TARGET_REG_BITS =3D=3D 64 static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) { @@ -152,33 +140,13 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_= t **tb_ptr) return value; } =20 -#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -/* Read indexed register (16 bit signed) from bytecode. */ -static int16_t tci_read_r16s(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - int16_t value =3D tci_read_reg16s(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} -#endif - -/* Read indexed register (32 bit) from bytecode. */ -static uint32_t tci_read_r32(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - uint32_t value =3D tci_read_reg32(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} - #if TCG_TARGET_REG_BITS =3D=3D 32 /* Read two indexed registers (2 * 32 bit) from bytecode. */ static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - uint32_t low =3D tci_read_r32(regs, tb_ptr); - return tci_uint64(tci_read_r32(regs, tb_ptr), low); + uint32_t low =3D tci_read_r(regs, tb_ptr); + return tci_uint64(tci_read_r(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 /* Read indexed register (32 bit signed) from bytecode. */ @@ -439,8 +407,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, continue; case INDEX_op_setcond_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); condition =3D *tb_ptr++; tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); break; @@ -463,7 +431,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif case INDEX_op_mov_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i32: @@ -519,7 +487,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; case INDEX_op_st_i32: CASE_64(st32) - t0 =3D tci_read_r32(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint32_t *)(t1 + t2) =3D t0; @@ -529,62 +497,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_add_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; case INDEX_op_sub_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; case INDEX_op_mul_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; case INDEX_op_div_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); break; case INDEX_op_divu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 / t2); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2); break; case INDEX_op_rem_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); break; case INDEX_op_remu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 % t2); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); break; case INDEX_op_and_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 & t2); break; case INDEX_op_or_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 | t2); break; case INDEX_op_xor_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 ^ t2); break; =20 @@ -592,41 +560,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_shl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 << (t2 & 31)); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31)); break; case INDEX_op_shr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 >> (t2 & 31)); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31)); break; case INDEX_op_sar_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, ((int32_t)t1 >> (t2 & 31))); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31)); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, rol32(t1, t2 & 31)); break; case INDEX_op_rotr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ror32(t1, t2 & 31)); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - t2 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp32 =3D (((1 << tmp8) - 1) << tmp16); @@ -634,8 +602,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i32: - t0 =3D tci_read_r32(regs, &tb_ptr); - t1 =3D tci_read_r32(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare32(t0, t1, condition)) { @@ -673,9 +641,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_mulu2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - t2 =3D tci_read_r32(regs, &tb_ptr); - tmp64 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, t2 * tmp64); + t2 =3D tci_read_r(regs, &tb_ptr); + tmp64 =3D (uint32_t)tci_read_r(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 @@ -688,8 +656,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext16s_i32 case INDEX_op_ext16s_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int16_t)t1); break; #endif #if TCG_TARGET_HAS_ext8u_i32 @@ -716,21 +684,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #if TCG_TARGET_HAS_bswap32_i32 case INDEX_op_bswap32_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_not_i32 case INDEX_op_not_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i32 case INDEX_op_neg_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif @@ -903,8 +871,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_ext16s_i64 case INDEX_op_ext16s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int16_t)t1); break; #endif #if TCG_TARGET_HAS_ext16u_i64 @@ -927,8 +895,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif case INDEX_op_extu_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1); break; #if TCG_TARGET_HAS_bswap16_i64 case INDEX_op_bswap16_i64: @@ -940,7 +908,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_HAS_bswap32_i64 case INDEX_op_bswap32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); break; #endif --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ybRVe+0cbcMgdImiuixof8hM4eoxKsh03sT+tgpyyEY=; b=GHN3icFQ6n/hCBrkLU111p16ZGoNy4IkqtDhhAhxbQ4VUvo0h7i1xVaTA8/P1JFqgk TObgtqagdhV6fvK5mm7HVMAkm8y5Hc5d0vzIRSqYama9vfdgYT5ncAwJ9M2ynPj9gOrw PFGrdlQlJipd8fjw9et4Hzu/pUsB8ja+2HzuFms7OMco2NUJ15Eh6SfQLrr22Ofrd11d z/vpESOUsbdCGob9a8g/ndbJjlG9yj43m0kOG/CzRmLxGEaHDek6o27Bj6bmj3CSR62c /WP/KFnDIhO1Mbfm5QvBU0WW5vdowqu8jCr49cRn44AsZPAO88DId3tgAFxgvuWIJdj9 Ga/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ybRVe+0cbcMgdImiuixof8hM4eoxKsh03sT+tgpyyEY=; b=SZu24ANiQaNtaRDcZbu02FSuT2Z7MO7X5vDvVG7DiE115UUPTFIz43kBaOMtRr2j5/ zV3JwY2fFJGhWBR99PsvECSyePFuojFSOUbTZp1D1IGvKUYd1W264WD2Bih2l3qojSW6 MQGI2ks8PItbAmQd8PnN/eLEps5YP1RXYCiRn/O1DUIOuD+rehDhxgBl66mB2XK1zVnQ 7LyyaRt6s3wmMDj9IeE0CZI6mSRFQIkORBXbBPjk7uzowbhAFDeH8bo+rNvkmoORiwso s2P3/Jc4xfODY8G51Pqo/g9gADU7rSBEoj9csV4/5J5T5hGUi2p0Txl4Trn91kMdA9iw bHBQ== X-Gm-Message-State: AOAM530zx9ocM5GeWL0KG1j7hgwi6syCAOR3f2qh8Q2R41YIBG397hFg Uhgo+dYqlwWxoJaoaXYNbYp0+8opETyrXQh0 X-Google-Smtp-Source: ABdhPJz1i04Y1KVn1EKFb576LT8Z6I8pISzzXGFfWUtOEzSTH1YRMwExES7JsxFvselz1L5I6m+9mQ== X-Received: by 2002:a17:90b:8d7:: with SMTP id ds23mr5790883pjb.116.1612403175863; Wed, 03 Feb 2021 17:46:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 35/93] tcg/tci: Remove tci_read_r32s Date: Wed, 3 Feb 2021 15:44:11 -1000 Message-Id: <20210204014509.882821-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use explicit casts for ext32s opcodes. Signed-off-by: Richard Henderson --- tcg/tci.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 72ec63e18e..9c8395397a 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ul= ong *regs, TCGReg index) return regs[index]; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int32_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_REG_BITS =3D=3D 64 static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) { @@ -149,15 +142,6 @@ static uint64_t tci_read_r64(const tcg_target_ulong *r= egs, return tci_uint64(tci_read_r(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 -/* Read indexed register (32 bit signed) from bytecode. */ -static int32_t tci_read_r32s(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - int32_t value =3D tci_read_reg32s(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} - /* Read indexed register (64 bit) from bytecode. */ static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -887,8 +871,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif case INDEX_op_ext_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int32_t)t1); break; #if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612405351; cv=none; d=zohomail.com; s=zohoarc; b=Vi+gJYheMLYBfOFjYBxDZMfAfpIi4DBZEitZ/0UioTNzEAmxkhZS+uY/nDgZyqdJk9k6itMyCax2/M+8vHBh+3gmrpviHAN4BKxl3T/ja1VZ3M99zgLZ3yRd6bq3QlbyDSNog42A0CtUbXpX0ZUSn1LSdGcpp0rgCm9sZcJud00= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612405351; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rPMFB2Q7bqmshseEZXdi4DH7vz7QmPfw5K/IzP922xY=; b=Ie/6ZTOjMS+9PpFycw6L5PsTQtJJwzqoPlIbWhmWh6JHYuSaPWUDo/9eB3ybSvgj/Drmbevl4O8ZDZgeo2fkXyNRltXWkkFMogynVToXmsma2adOnnKbBWBanianPV1cW6jx9KfXNF3cYocnTynjLgnSf5IYi/1+guLmyg6l1x8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612405351644433.81855928244283; Wed, 3 Feb 2021 18:22:31 -0800 (PST) Received: from localhost ([::1]:43694 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7UHu-0004gA-Cc for importer@patchew.org; Wed, 03 Feb 2021 21:22:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Tj7-0005LA-KK for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:34 -0500 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:40255) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tis-0003vo-U0 for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:33 -0500 Received: by mail-pj1-x102f.google.com with SMTP id z9so817703pjl.5 for ; Wed, 03 Feb 2021 17:46:18 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rPMFB2Q7bqmshseEZXdi4DH7vz7QmPfw5K/IzP922xY=; b=fnsTU3vlxjWSLIbztOkICaZPN3fThTs6i6j+MDQlHxNb8A/vSpRTqQWoNN+TGuN96q nYVCv6ofxi6o4Ce4tyJ5s4fMJxM3l+3ks4utECwcrlrgNmXSp/PXNwvKpcI8LCcM0+UT jplLWDZDtQQr7POlxL7r1CMRufZMBcpIfX/7Uf3q4N7qL2s0i3tIy+WAy5y3Gn41kryV BMtRhGNFdbow9nqcu0vWi4JIJ8VSZKsmnAwSiYgtzjXAqOIuhGRlnGU8bYIeQzp62sAd n5cNghADkCMEFZ9Mahdc74DNdKjTHJVIqBzlUshKF3r8roHOTK3A54I1VLl6Ah0m7/A0 rzkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rPMFB2Q7bqmshseEZXdi4DH7vz7QmPfw5K/IzP922xY=; b=j7P2tc+ev4+Wc5mgVGRD4w5er74FkNwYzuZaYe8Yy6NJXbDN/FLD7XQQaQPIFN4+td rPP4XMSOspKZ9WPzcTu3jMMjWAAyshGhx+U1QVmd09cCwbKVEuC5Xcu0qqrrKCLOAgpq iUiMAkdLqX5bm2M4OaYyTM1RmcCPf7Z+DFIhDiRBbyUBJzPGp6OSc7Q16/hSCKA2+I6t RU7MCyVgiy0GEg3GfEFnrjCBKEpbQWzbY1CkkyOQdUKxScdiTYZClh9Fp7+t1WnHCkUL YJLHEjUXsQSMEC8MqtwizCW3Qo0I9D19G5wW4VwaOixC7HXVzwVPR827LtVDVfPDeDFy /ddA== X-Gm-Message-State: AOAM533ZBWVHC50XJiVleiP4XUEdTOAXc0pzXHspvKQKHgT9wUEDsu/G tL//ayLRm4T50iZhTshIpbsEvfHvbxlz0/Po X-Google-Smtp-Source: ABdhPJzFyInoelaPqEi6eKesf/DbTJvzPcOqQIi+GS9ICjplhDelm4W3mgADRKjFlxo1WtCVV07CQA== X-Received: by 2002:a17:90a:1503:: with SMTP id l3mr5776066pja.41.1612403177531; Wed, 03 Feb 2021 17:46:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 36/93] tcg/tci: Reduce use of tci_read_r64 Date: Wed, 3 Feb 2021 15:44:12 -1000 Message-Id: <20210204014509.882821-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In all cases restricted to 64-bit hosts, tcg_read_r is identical. We retain the 64-bit symbol for the single case of INDEX_op_qemu_st_i64. Signed-off-by: Richard Henderson --- tcg/tci.c | 93 +++++++++++++++++++++++++------------------------------ 1 file changed, 42 insertions(+), 51 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 9c8395397a..0246e663a3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ul= ong *regs, TCGReg index) return regs[index]; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) -{ - return tci_read_reg(regs, index); -} -#endif - static void tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) { @@ -146,9 +139,7 @@ static uint64_t tci_read_r64(const tcg_target_ulong *re= gs, static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - uint64_t value =3D tci_read_reg64(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; + return tci_read_r(regs, tb_ptr); } #endif =20 @@ -407,8 +398,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); condition =3D *tb_ptr++; tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; @@ -689,7 +680,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_mov_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i64: @@ -713,7 +704,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st_i64: - t0 =3D tci_read_r64(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint64_t *)(t1 + t2) =3D t0; @@ -723,62 +714,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_add_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; case INDEX_op_sub_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; case INDEX_op_mul_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; case INDEX_op_div_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); break; case INDEX_op_divu_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); break; case INDEX_op_rem_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); break; case INDEX_op_remu_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; case INDEX_op_and_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 & t2); break; case INDEX_op_or_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 | t2); break; case INDEX_op_xor_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 ^ t2); break; =20 @@ -786,41 +777,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_shl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp64 =3D (((1ULL << tmp8) - 1) << tmp16); @@ -828,8 +819,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i64: - t0 =3D tci_read_r64(regs, &tb_ptr); - t1 =3D tci_read_r64(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { @@ -899,21 +890,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap64(t1)); break; #endif #if TCG_TARGET_HAS_not_i64 case INDEX_op_not_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i64 case INDEX_op_neg_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DTK4SJ5LYtJuHvuHu8AwQw2u8TQxf0ZzT7dsGBYnc0Y=; b=kePOshLbYGH7DlnSrh6q2+BxLTkAzaVnUfnvBxbMu11rWZNnm2hVdev2GyPL4CiJV/ +Np8864tiZXPvGE3hTxK1qG8snvXhZltjWZ+Bzqnl2lVI7nCY0c3Xt6PqQsu44f8kGYB YEDg0mxtYrbiycHRm4lP/jE9IxzySecnxxwAkiSZAheF/IEcGDIj1idzMhh3hoilpIjm dfI+FKdSUacZcrRCwY5vgkQbJ7uFitV/zWlodcFPBYZ03tkHay6UYWppOEJJoqxstEuJ ClYCpFhY9ElVfKCQk1V+YEtZxBZeGjtrff+7oaldWVmatNXOoFrX+cnV4JW/ZA/XI624 EnFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DTK4SJ5LYtJuHvuHu8AwQw2u8TQxf0ZzT7dsGBYnc0Y=; b=EWuepmu8Dvv+Sg358OiQZQN4Ma5jpR0+KHlxMhwm70uANDJWjL6+TWll5RtveH+Ulu /3pg9GVBu8dba9dZOT/w2kjc/GTCwLCZC3DTCV0D00qvI3wADAt2PzvW3vOyclFgn7+W sv3d2q5e7XZANubWlad7tC9BFIkZPMfyBfxWs0ROgh9aVZHw7pKjFeOVhs39b9KkpjWq 5o4Tpo13rKAdDz9cG4ey+amvWUtUiayfRuovnfjt0tLm7CHVMvlETrut9ItIKmKWVf0u fmGbp+2ggS0GN3Pac3lukDZHyCOt3LBpNnRR1HP8RNGZMMfzbsDO2mL5nZn+rMhwrdkM 6mlA== X-Gm-Message-State: AOAM531rmWuPun1JFBTdbb2bq2SR8qsVvwoQrU64umaSPs6SfnrHrf48 87RxSmMthHnJoIneZPaJlszpO/uEj2hbNLxI X-Google-Smtp-Source: ABdhPJxiWk6mRMbUfz+0DBKOIJhVNaktFtQFqUA1m5uxBaJzd5OQmcFsSyn4PhmLu+P2DigJ6lwJAg== X-Received: by 2002:a17:90a:4096:: with SMTP id l22mr4322871pjg.34.1612403179342; Wed, 03 Feb 2021 17:46:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 37/93] tcg/tci: Merge basic arithmetic operations Date: Wed, 3 Feb 2021 15:44:13 -1000 Message-Id: <20210204014509.882821-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This includes add, sub, mul, and, or, xor. Signed-off-by: Richard Henderson --- tcg/tci.c | 83 +++++++++++++++++-------------------------------------- 1 file changed, 25 insertions(+), 58 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 0246e663a3..894e87e1b0 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -468,26 +468,47 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, *(uint32_t *)(t1 + t2) =3D t0; break; =20 - /* Arithmetic operations (32 bit). */ + /* Arithmetic operations (mixed 32/64 bit). */ =20 - case INDEX_op_add_i32: + CASE_32_64(add) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; - case INDEX_op_sub_i32: + CASE_32_64(sub) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; - case INDEX_op_mul_i32: + CASE_32_64(mul) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; + CASE_32_64(and) + t0 =3D *tb_ptr++; + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, t1 & t2); + break; + CASE_32_64(or) + t0 =3D *tb_ptr++; + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, t1 | t2); + break; + CASE_32_64(xor) + t0 =3D *tb_ptr++; + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, t1 ^ t2); + break; + + /* Arithmetic operations (32 bit). */ + case INDEX_op_div_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); @@ -512,24 +533,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); break; - case INDEX_op_and_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); - break; - case INDEX_op_or_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); - break; - case INDEX_op_xor_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); - break; =20 /* Shift/rotate operations (32 bit). */ =20 @@ -712,24 +715,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, =20 /* Arithmetic operations (64 bit). */ =20 - case INDEX_op_add_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 + t2); - break; - case INDEX_op_sub_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 - t2); - break; - case INDEX_op_mul_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 * t2); - break; case INDEX_op_div_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); @@ -754,24 +739,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; - case INDEX_op_and_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); - break; - case INDEX_op_or_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); - break; - case INDEX_op_xor_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); - break; =20 /* Shift/rotate operations (64 bit). */ =20 --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404796; cv=none; d=zohomail.com; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b0OZ8HZNEJw4TVjXNMfY9ukiBorqmrftQz6h6YJ1/P4=; b=JJNu6sHIoxvJg2SQXw3I2nYZ/AS0Nqi/b727N1o+HDijO2xALKqZ5ocBx3E0bMJdHh xq3eYZcKr3Cz6ZKFudiLPWEhS+3tkn6g28RNUSuTiuJCgMxn7lvpiGuIIBQeIqM+VP/n FhWoUi9/sEyhGirknOLFWPBZE7GmWJ8BjiXSApQ+gcuQVNMRKKcy2sDSQHk04Tn3Phnx VKiFPsDM3sv+B27HLjdI98FoHVit1dctxGXwwjcj+aNGIxcld6/613cqKSDUTvGP9T9F Dv4XlhXDo0qSfRAeV7VpZtimytg37V3pNYeQrPZma54Ukcl605bbxiOK4zJ6GaRH5zjS 39Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b0OZ8HZNEJw4TVjXNMfY9ukiBorqmrftQz6h6YJ1/P4=; b=NoZeSeTeUAe9ntedKeoaow+W0mTFq5r7Ra1nrgHuAzCicEddGAoJhwZIy2XPMPrtlY 5V+00lT7PgbJvI3vyukEfj7eOeVnGTMBYEJF7XFu45k3g1mg389a4SpUyG2mKikUqJVm IZrfnuxsRknrmIxun/4lGg55G7AxNAK5054GMa7YE3toJ6+jILBn7skKRCcxpeO38irq F97y6VxB3aSBLbSFPNAEs94JR115OgfQLGJdiiRsRSmL/lIrRB+yM6kWZT3fqmig1tCi n9Oej3iLs+yQ5cRUAY99PdkUMcllznbdVcDCnL3se3g2ApGAIMoUnR4vVeGxoCaWuxa4 DZ3w== X-Gm-Message-State: AOAM530iyz41hVvPzw81TcJdxrkA0OHR5r71r4PRdOOcb13j+NiG+XhA VSstcheAXLl0G36iVWX3IP9Wb3VUonEWPeuX X-Google-Smtp-Source: ABdhPJyINdloymCbiCC88YjC7KTPp3iAgaoI5pYg83MLCmtnvkGOc2MN09YzOxo8dl+/CEz1YdiRjw== X-Received: by 2002:a65:648e:: with SMTP id e14mr6492744pgv.453.1612403180967; Wed, 03 Feb 2021 17:46:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 38/93] tcg/tci: Merge extension operations Date: Wed, 3 Feb 2021 15:44:14 -1000 Message-Id: <20210204014509.882821-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This includes ext8s, ext8u, ext16s, ext16u. Signed-off-by: Richard Henderson --- tcg/tci.c | 44 ++++++++------------------------------------ 1 file changed, 8 insertions(+), 36 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 894e87e1b0..cdfd9b7af8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -624,29 +624,29 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ -#if TCG_TARGET_HAS_ext8s_i32 - case INDEX_op_ext8s_i32: +#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 + CASE_32_64(ext8s) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int8_t)t1); break; #endif -#if TCG_TARGET_HAS_ext16s_i32 - case INDEX_op_ext16s_i32: +#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 + CASE_32_64(ext16s) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int16_t)t1); break; #endif -#if TCG_TARGET_HAS_ext8u_i32 - case INDEX_op_ext8u_i32: +#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 + CASE_32_64(ext8u) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint8_t)t1); break; #endif -#if TCG_TARGET_HAS_ext16u_i32 - case INDEX_op_ext16u_i32: +#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 + CASE_32_64(ext16u) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint16_t)t1); @@ -796,34 +796,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, continue; } break; -#if TCG_TARGET_HAS_ext8u_i64 - case INDEX_op_ext8u_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint8_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext8s_i64 - case INDEX_op_ext8s_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (int8_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext16s_i64 - case INDEX_op_ext16s_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (int16_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext16u_i64 - case INDEX_op_ext16u_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint16_t)t1); - break; -#endif #if TCG_TARGET_HAS_ext32s_i64 case INDEX_op_ext32s_i64: #endif --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404878; cv=none; d=zohomail.com; s=zohoarc; b=nyYYy2Pom+OKI22bbKM04kUobZIclxPIj2RimEAgZRbD7S0Uq/gCH2xRbb7Dw/0ygCdunawkqKiocxeNNv72Fh91kf+xNASXKQBvd1AErew63MFRXuZ9Bb6tsbLEe2YFnFwODxDZiBWxD0yAixycGsp/yTySVpkZKYGJXHA/IaU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612404878; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MfW3tSMzNg4i1sVQnx6Ri1BGJD02W5/7jILfn3srnPM=; b=e7lHJ+AJJEzbOGeHk35o7JpnlthNII3v5heQhvSkgmTptTenF4qGN5t/KnadavmqLXTNfCmMUS3wgE8O62rqzDVb0WTPTIZ23/wrzThsSXaIUxd41M1B+D6z4M18/Gea8WSxI+haM6qZficqmPsOrBzUnX0rpqkZvpfCuY8zjDY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612404878342339.58009617388154; Wed, 3 Feb 2021 18:14:38 -0800 (PST) Received: from localhost ([::1]:54726 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7UAH-0005Yk-BF for importer@patchew.org; Wed, 03 Feb 2021 21:14:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44866) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7TjE-0005Nb-Bg for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:40 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:34566) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tiz-0003x8-60 for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:34 -0500 Received: by mail-pl1-x631.google.com with SMTP id u15so904465plf.1 for ; Wed, 03 Feb 2021 17:46:24 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MfW3tSMzNg4i1sVQnx6Ri1BGJD02W5/7jILfn3srnPM=; b=B1I0nlhuH5exjTJ7ZCYHW25afTk+3ZZegud7dSIjUSBIWWWr+O/N0GN6yGzo02hTEN /brIxOsF1/IxtZ9fPS0Smk/8yACBXWKeIDzWyKon7dKugPy6CpkN6VxPEUQOu6iV7+k0 eaopuszqhdBmRY8MNpYyY3innNkRjQY34w5x8IBcHVmCCUCVFu27IImc7KbS+aiLV+Oj 16XAv0lMqrgkXmjvkMOz2U1k5nZZjf+2t8t6hEdNV4fDJo2dA8kGXZhOfyahYYyJm9VH 2gO8e2gtrb5wscZmA0e8bharEZpnhIdkuS1s/wjq6RsFZxrjS+6DnatefCXaKXJzfKVa WChQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MfW3tSMzNg4i1sVQnx6Ri1BGJD02W5/7jILfn3srnPM=; b=hClOV/Z9rONKMom5neOtRKE3C+CvsRiUFrWtoU15BzaXo2EMVzKE1RvOEMZg4sZVNf BpfGg3vJaZ6bSV0Td1cCSuwC1mRuCDC5KsE+mSyAje3W8H9I8+2252F7RP0LzB5dqggW whHeGw+QhCtAeEcPhGai9GGhKBD4js/dnNahYBXen/UPGDd2yihMxwpff4PykTutUjHL Ix6oH8Dm4bZcvmq04CHTG/5NUSnDOhFlvf9ReX/xoOfnUVHAQ1vw4+hWVpbZoZogDYUJ vmb8ULxmJAvmUTlVVmnwAZnS3RfGJjjhsro6SZtL9TDia7rPu8Fc4+dJ8fgEXDpYIlfi NQ9w== X-Gm-Message-State: AOAM530jPv8hhX6S3k7VFOvQbt3CPF9YM6sWsYE5EWNWOl89iw+h4zvX F/C2O0co0xbNHJ6O+b4AyqFUti3jufz/drnW X-Google-Smtp-Source: ABdhPJyB7O/YlauJ1N3A6nPGumlf+RQSMsKLd//EKw8vrWFif++Fe0HjxmGTgrhEjh04QKWco+qifg== X-Received: by 2002:a17:90b:1996:: with SMTP id mv22mr5871769pjb.121.1612403184024; Wed, 03 Feb 2021 17:46:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 39/93] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64 Date: Wed, 3 Feb 2021 15:44:15 -1000 Message-Id: <20210204014509.882821-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These operations are always available under different names: INDEX_op_ext_i32_i64 and INDEX_op_extu_i32_i64, so we remove no code with the ifdef. Signed-off-by: Richard Henderson --- tcg/tci.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index cdfd9b7af8..1819652c5a 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -796,17 +796,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, continue; } break; -#if TCG_TARGET_HAS_ext32s_i64 case INDEX_op_ext32s_i64: -#endif case INDEX_op_ext_i32_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1); break; -#if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: -#endif case INDEX_op_extu_i32_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404979; cv=none; d=zohomail.com; s=zohoarc; b=RZ6pccPHN6Ofv3M4vrJSTbq5boBqd+g64TbAbOTI0jMR/U0NoMRM5ngs4N5Q4qALTF/xdqYmqOvooOCfGw9UMV5hz+4gaB1xbka8I7MiBHObn/AoFBATL+k1iaOmW8PVycmx6gfd7URdCHqKnvFRT9iMO3TAzvxRpFN9IDu57wo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612404979; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KcXtBKnullZQYp/0sBEeRm33/576gXQq0HPnlvclX78=; b=hM8rFdhaiilCyhzw30JA5noA7snb1YFqXI7l3sStuPoa9jYab56x+dA/HU4+YZVTKfXF94J3s7tWHY9j6iU0Ej6IzN36YROK4PkHazJTHlBKJPowDF42QP2zWsA7wPsmp4lrVBlnnumDZUgDy4GwzFACRKhBbx7IekB9HQo3aSM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612404979571709.4233027864545; Wed, 3 Feb 2021 18:16:19 -0800 (PST) Received: from localhost ([::1]:58460 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7UBu-000786-I9 for importer@patchew.org; Wed, 03 Feb 2021 21:16:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7TjH-0005Pi-2v for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:44 -0500 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:46780) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tj1-0003xI-J1 for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:40 -0500 Received: by mail-pf1-x430.google.com with SMTP id f63so1047502pfa.13 for ; Wed, 03 Feb 2021 17:46:26 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KcXtBKnullZQYp/0sBEeRm33/576gXQq0HPnlvclX78=; b=Z6iAJ/16muHmobNDvO6b/Z6Mv/iocvZZlRJMSCA1sgU5FO4RvtR2hegIDCYEewbFu8 aWnqNeX+WJFbLMCs4794znfXOtFBE0LgmOLv+YMpsblT3zFrC5Gw7sYVyx6DGSFuCljf I/7JJG8inEH2SeEbHwKHRR/4pGdquNgdV+Xa0Ggn64akzRnt7gMyFgH7hBXrDaM6sQgm +qfwmi7UqqmKjH/ofV91+FLiMAYMvSMH62cr9eJSCQwkC1ZUwEyQMgRlX0w15TI9NkkS mgSr2Zg5/6XuDsjQBQgtbTv08ElqIF2jlsZZsBAsHSKRxFf/doWVZCH2WI10PJOz8eHt pCbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KcXtBKnullZQYp/0sBEeRm33/576gXQq0HPnlvclX78=; b=jb5VjqulXcxrGjHw2s/4P/R1Hr/St+o/7NP/ffW5eqT/2AOuDjpFBYB/N4hjEKThtb zbV5PXe030cIahrj8RtqXjvmpEAdKdC0clrYhmOfWSGjsLqw1R9u3VWvawJjS+5bBHVH 84A9iYRQhNdx/zXwMn73fNxF+BQxf88ax8BxRjUF/IMb53xs/HO7OSLVhVVRDBG1jNUw 69xs0/sTj4TBiD3KcW7MolFGclHGkZ/dF4ZWJ4zq5S3P8rGmrE2B3P+La/6xScjS0oUV 6j/TP1LABuyUnZjLbZjg3FF+i0djvyCQ/MmM28hCUAGsUae+TalGD24xLBTUrESn3wQj kRAg== X-Gm-Message-State: AOAM532NBp5rA6Sm05pk/M4Ondg5gTH/kPAWZk6GQA/uirvOqNZtbpUQ 8vIhRJ/u4qIjEXXu+naZHAdKBRnNsskIP32v X-Google-Smtp-Source: ABdhPJzMfvtH9kJnMH7R0FHeyWfXBcgH20soRASzSlAl6ByVyRIupz9uFogG0ErJkcbDp84LUQj2oA== X-Received: by 2002:a62:115:0:b029:1b4:c593:acd4 with SMTP id 21-20020a6201150000b02901b4c593acd4mr5771094pfb.2.1612403185497; Wed, 03 Feb 2021 17:46:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 40/93] tcg/tci: Merge bswap operations Date: Wed, 3 Feb 2021 15:44:16 -1000 Message-Id: <20210204014509.882821-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This includes bswap16 and bswap32. Signed-off-by: Richard Henderson --- tcg/tci.c | 22 ++++------------------ 1 file changed, 4 insertions(+), 18 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 1819652c5a..c979215332 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -652,15 +652,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tci_write_reg(regs, t0, (uint16_t)t1); break; #endif -#if TCG_TARGET_HAS_bswap16_i32 - case INDEX_op_bswap16_i32: +#if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 + CASE_32_64(bswap16) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif -#if TCG_TARGET_HAS_bswap32_i32 - case INDEX_op_bswap32_i32: +#if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 + CASE_32_64(bswap32) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); @@ -808,20 +808,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1); break; -#if TCG_TARGET_HAS_bswap16_i64 - case INDEX_op_bswap16_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap16(t1)); - break; -#endif -#if TCG_TARGET_HAS_bswap32_i64 - case INDEX_op_bswap32_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap32(t1)); - break; -#endif #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 =3D *tb_ptr++; --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612404952; cv=none; d=zohomail.com; s=zohoarc; b=lWcSShT/U9MkiDEhYInvbUxlqMtpBA+H+xYVkoeTcsTRy/NdtpcBFZBks8DXh4soEFUhQdZv0DfFTQMESJ1CJysL9CsPZWKab2ClA93hlAcSjsKWufB93BQ0ETtwQ83oYOOd0KN1jBu/UhHPf+kOhO1lSun9KE5o65fp4Cz1cjI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612404952; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=v8YBF7O/DOHSCTIsDFGzgG9s+eMvXezLyegZpBv+3f8=; b=fMaurwB0nsIngXc4ntiBlmgiUjbXU1LguZk0LO2DEtORegoys2xqOcgPrQB+GZVQTQm292rHOYinyPEuh2huOvrZqAxZV/gPgPw2/oeX1ZIdKuAw5kmIJ8Wv7X4D4bHTDBmdGu34uKNCcqpXTkYL4PX27ZMSY5GIhGUn0+p77IQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612404952184334.591563698301; Wed, 3 Feb 2021 18:15:52 -0800 (PST) Received: from localhost ([::1]:57994 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7UBT-0006we-4X for importer@patchew.org; Wed, 03 Feb 2021 21:15:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44884) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7TjH-0005Pg-2r for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:44 -0500 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:33838) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tj3-0003xR-7i for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:39 -0500 Received: by mail-pf1-x42e.google.com with SMTP id m6so1088396pfk.1 for ; Wed, 03 Feb 2021 17:46:27 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 29 +++++------------------------ 1 file changed, 5 insertions(+), 24 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index c979215332..225cb698e8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -404,7 +404,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; #endif - case INDEX_op_mov_i32: + CASE_32_64(mov) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1); @@ -666,26 +666,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tci_write_reg(regs, t0, bswap32(t1)); break; #endif -#if TCG_TARGET_HAS_not_i32 - case INDEX_op_not_i32: +#if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 + CASE_32_64(not) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif -#if TCG_TARGET_HAS_neg_i32 - case INDEX_op_neg_i32: +#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 + CASE_32_64(neg) t0 =3D *tb_ptr++; t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif #if TCG_TARGET_REG_BITS =3D=3D 64 - case INDEX_op_mov_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); - break; case INDEX_op_tci_movi_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_i64(&tb_ptr); @@ -815,20 +810,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_write_reg(regs, t0, bswap64(t1)); break; #endif -#if TCG_TARGET_HAS_not_i64 - case INDEX_op_not_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, ~t1); - break; -#endif -#if TCG_TARGET_HAS_neg_i64 - case INDEX_op_neg_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, -t1); - break; -#endif #endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ =20 /* QEMU specific operations. */ --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612405240; cv=none; d=zohomail.com; s=zohoarc; b=kcsC0OnVBPmmsuSmqRKtOKO7Y3e+uZnoNo8LqSWQ9W9zTDj+e0Y7SVc4J1zmkJh7XGQMMeGyvGYn57jyPjjmuVkm6eg1V15Vk7EAk7zWNJzT51ykh52nOEOlH8QVitvLpNaypIG2Aa8docItSWUz5lywHQc07tsVACW5NRF3bQw= ARC-Message-Signature: i=1; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rgDo7IsNPQk1k4dENPTgVxVYE0qud9+qjI7vIiyJakQ=; b=OLvWh2M51FN1fTJEHnUBq7c+kG30NmudEX8JHsvUnnr++9Yui650lD7t3RMJPyvGfz F0bN9TTE7mJfsBrF4b9Zb6MnK7XACr8wAajVY/zZL+l/97U4T061AcoL3GPW/lR3O6iE O+cDWOpAMbRaCR7vn1NaDfhCpaVX0+5KmRSdo4czyueR76kVcAGLAHFA/C6vrNVt4Up0 sostElpQBQOzlvlhq5XicT4u7+kBXk3Sjnx7XWF72ss49aAM0a1LIvhaPB5J1U+1bwR/ TURNz7LiLbsq69iBgJut7PoCbbTg2OgP69JFXDCjT9Qn+Iw9BY2tjiW9ntxuHW4YXbvS 2Itw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rgDo7IsNPQk1k4dENPTgVxVYE0qud9+qjI7vIiyJakQ=; b=fExXYGOitYGBffqp0t9WFG9mnbGomzAQOovoP7kMAtdEPUYxSA1FzkRmwROVhoivs5 OylJgV8/bhl7Ny4bXD5pGxoy1I9xDRTeES8TGIyst5CzELJo2hERQSckBZq/4bsU3QKj aXKVkL3jIlEw4Nn8nuPUVtX+14ZooLFSERW7+jRKS/+DKKfb1YDJWM7ptdwk2MQvD46h 8Cif32ukRKO/PWe06Rfm34S0xBgUQJT7LyycWPzC29MwUnPxcwmTXukE5KYylkKGkJyh 7uUu3kMHEXOirg2Ehaz7px6Bi1dqNCAnkF8h7uOzGAGiiW4KMrOpCZjeffoqY5LBoDwe aoEg== X-Gm-Message-State: AOAM532HxOliOCwvLYU7gH9zjR1OWdQRXGEOO13dMIWcK0mSd9ji9a4e 4MRGIa4NQOLSUMt+ahyK/Tk+G87F0rWx2sfQ X-Google-Smtp-Source: ABdhPJwFs22gNkedzifg4KYFBoAnBaN4R1uKZIAEelhpt9e3tPP3kCVJhfrsl4Ts0pYWmXYssl3dWw== X-Received: by 2002:a17:90a:9310:: with SMTP id p16mr5913662pjo.211.1612403188818; Wed, 03 Feb 2021 17:46:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 42/93] tcg/tci: Rename tci_read_r to tci_read_rval Date: Wed, 3 Feb 2021 15:44:18 -1000 Message-Id: <20210204014509.882821-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In the next patches, we want to use tci_read_r to return the raw register number. So rename the existing function, which returns the register value, to tci_read_rval. Signed-off-by: Richard Henderson --- tcg/tci.c | 192 +++++++++++++++++++++++++++--------------------------- 1 file changed, 96 insertions(+), 96 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 225cb698e8..20aaaca959 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -119,7 +119,7 @@ static uint64_t tci_read_i64(const uint8_t **tb_ptr) =20 /* Read indexed register (native size) from bytecode. */ static tcg_target_ulong -tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) +tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { tcg_target_ulong value =3D tci_read_reg(regs, **tb_ptr); *tb_ptr +=3D 1; @@ -131,15 +131,15 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_= t **tb_ptr) static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - uint32_t low =3D tci_read_r(regs, tb_ptr); - return tci_uint64(tci_read_r(regs, tb_ptr), low); + uint32_t low =3D tci_read_rval(regs, tb_ptr); + return tci_uint64(tci_read_rval(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 /* Read indexed register (64 bit) from bytecode. */ static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - return tci_read_r(regs, tb_ptr); + return tci_read_rval(regs, tb_ptr); } #endif =20 @@ -147,9 +147,9 @@ static uint64_t tci_read_r64(const tcg_target_ulong *re= gs, static target_ulong tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - target_ulong taddr =3D tci_read_r(regs, tb_ptr); + target_ulong taddr =3D tci_read_rval(regs, tb_ptr); #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - taddr +=3D (uint64_t)tci_read_r(regs, tb_ptr) << 32; + taddr +=3D (uint64_t)tci_read_rval(regs, tb_ptr) << 32; #endif return taddr; } @@ -382,8 +382,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, continue; case INDEX_op_setcond_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); condition =3D *tb_ptr++; tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); break; @@ -398,15 +398,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); condition =3D *tb_ptr++; tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; #endif CASE_32_64(mov) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i32: @@ -419,51 +419,51 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 CASE_32_64(ld8u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2)); break; CASE_32_64(ld8s) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); break; CASE_32_64(ld16u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2)); break; CASE_32_64(ld16s) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(int16_t *)(t1 + t2)); break; case INDEX_op_ld_i32: CASE_64(ld32u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); break; CASE_32_64(st8) - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) =3D t0; break; CASE_32_64(st16) - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) =3D t0; break; case INDEX_op_st_i32: CASE_64(st32) - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint32_t *)(t1 + t2) =3D t0; break; @@ -472,38 +472,38 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 CASE_32_64(add) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; CASE_32_64(sub) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; CASE_32_64(mul) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; CASE_32_64(and) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 & t2); break; CASE_32_64(or) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 | t2); break; CASE_32_64(xor) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 ^ t2); break; =20 @@ -511,26 +511,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_div_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); break; case INDEX_op_divu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2); break; case INDEX_op_rem_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); break; case INDEX_op_remu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); break; =20 @@ -538,41 +538,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_shl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31)); break; case INDEX_op_shr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31)); break; case INDEX_op_sar_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31)); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, rol32(t1, t2 & 31)); break; case INDEX_op_rotr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ror32(t1, t2 & 31)); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp32 =3D (((1 << tmp8) - 1) << tmp16); @@ -580,8 +580,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i32: - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare32(t0, t1, condition)) { @@ -619,64 +619,64 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, case INDEX_op_mulu2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - t2 =3D tci_read_r(regs, &tb_ptr); - tmp64 =3D (uint32_t)tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); + tmp64 =3D (uint32_t)tci_read_rval(regs, &tb_ptr); tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 CASE_32_64(ext16s) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int16_t)t1); break; #endif #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 CASE_32_64(ext8u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 CASE_32_64(ext16u) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint16_t)t1); break; #endif #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 CASE_32_64(bswap16) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 CASE_32_64(bswap32) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 CASE_32_64(not) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 CASE_32_64(neg) t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif @@ -691,19 +691,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_ld32s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(int32_t *)(t1 + t2)); break; case INDEX_op_ld_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st_i64: - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint64_t *)(t1 + t2) =3D t0; break; @@ -712,26 +712,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_div_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); break; case INDEX_op_divu_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); break; case INDEX_op_rem_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); break; case INDEX_op_remu_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; =20 @@ -739,41 +739,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_shl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); - t2 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); + t2 =3D tci_read_rval(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp64 =3D (((1ULL << tmp8) - 1) << tmp16); @@ -781,8 +781,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i64: - t0 =3D tci_read_r(regs, &tb_ptr); - t1 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { @@ -794,19 +794,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, case INDEX_op_ext32s_i64: case INDEX_op_ext_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1); break; case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1); break; #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, bswap64(t1)); break; #endif @@ -913,7 +913,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, } break; case INDEX_op_qemu_st_i32: - t0 =3D tci_read_r(regs, &tb_ptr); + t0 =3D tci_read_rval(regs, &tb_ptr); taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6L5nwfntHiBbAqZT7vmSHngxEhaJDXVbwdQCQHJ8TTo=; b=q0mviuklDICOKKUiCYmLMcXKKmSBCAwIEeFO56iRToxdzWm9BIKNlfJCnEhbRucMd6 QzoT94NJRyy5eZJn3xg1yTibmKv6K2ir2yzkSmXQ30XPmCAAgUBY6MUts198crEcb+/g Yx98nFwuVW21ugXjvR1ZSF6JRQNeUZk6iOomqDyDtQ3ByFNvMOXTI4HF+QIddd3XenrR 5A+hp8F0InVU45Mn7dKYlTuFfcQJoFwkOGtn7bILGNDEB9mRnnSjc/R7fydrV7hOjcqd TRB7YtfdRhsDIJMiQTpD9skBkB2VsqRDHYtNlBrWOhvdLQ//MQ444+rqRLf5bJQb3rZY 3PJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6L5nwfntHiBbAqZT7vmSHngxEhaJDXVbwdQCQHJ8TTo=; b=GDuy8ZCLiA+Lu0KI+aecrOgB31D+nva3zduKxDdF8TQeZ4ITB6jglAU+DUlf432cym SUwR+90IP/LZZw2k6HbPMvXHa24Yz5wStOEGQgBqIG67hr0ZjaPVZUSC1q9iLIFWc3AX NHOy9somldLJexyiazXoE0WqtEc9wivITwkUrx2cvM/vKMx+lLFC8ymkxgGoPxZhTfql OTYFJ0ls8whf4r+GBglyP2JaCp0bVcoB3Vc9KSvsZ9/Vhwhzt6oXH6yVj2x0HvxVNFSA MIjFIlpvl/YYbL5qnh6Ib45jF55GcZ8LHGR4G/5fHFGm4IpRTmHtG0LJbK/w7Dgg2hGl w76Q== X-Gm-Message-State: AOAM530JKve0ASND/o1yAu7O5VppZfQsufuaBX+v9DhaLeLgVz6dWkp2 6irjSXMqIBAPDQQ6f4EAQn2Vk4PXecTKkt0A X-Google-Smtp-Source: ABdhPJy7r5TMQQvKZoylSIANAHg+wSXAj6U+1BgUkuZP4UZWzoUaVldDaiGZzA2x0kMP3jMotYrY/g== X-Received: by 2002:a17:902:d64e:b029:df:e5b1:b7f7 with SMTP id y14-20020a170902d64eb02900dfe5b1b7f7mr5660811plh.10.1612403190499; Wed, 03 Feb 2021 17:46:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 43/93] tcg/tci: Split out tci_args_rrs Date: Wed, 3 Feb 2021 15:44:19 -1000 Message-Id: <20210204014509.882821-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Begin splitting out functions that do pure argument decode, without actually loading values from the register set. This means that decoding need not concern itself between input and output registers. We can assert that the register number is in range during decode, so that it is safe to simply dereference from regs[] later. Signed-off-by: Richard Henderson --- tcg/tci.c | 111 ++++++++++++++++++++++++++++++++---------------------- 1 file changed, 67 insertions(+), 44 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 20aaaca959..be298ae39d 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -83,6 +83,20 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low) } #endif =20 +/* Read constant byte from bytecode. */ +static uint8_t tci_read_b(const uint8_t **tb_ptr) +{ + return *(tb_ptr[0]++); +} + +/* Read register number from bytecode. */ +static TCGReg tci_read_r(const uint8_t **tb_ptr) +{ + uint8_t regno =3D tci_read_b(tb_ptr); + tci_assert(regno < TCG_TARGET_NB_REGS); + return regno; +} + /* Read constant (native size) from bytecode. */ static tcg_target_ulong tci_read_i(const uint8_t **tb_ptr) { @@ -161,6 +175,23 @@ static tcg_target_ulong tci_read_label(const uint8_t *= *tb_ptr) return label; } =20 +/* + * Load sets of arguments all at once. The naming convention is: + * tci_args_ + * where arguments is a sequence of + * + * r =3D register + * s =3D signed ldst offset + */ + +static void tci_args_rrs(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, int32_t *i2) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *i2 =3D tci_read_s32(tb_ptr); +} + static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { bool result =3D false; @@ -328,6 +359,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint8_t op_size =3D tb_ptr[1]; const uint8_t *old_code_ptr =3D tb_ptr; #endif + TCGReg r0, r1; tcg_target_ulong t0; tcg_target_ulong t1; tcg_target_ulong t2; @@ -342,6 +374,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint64_t v64; #endif TCGMemOpIdx oi; + int32_t ofs; + void *ptr; =20 /* Skip opcode and size entry. */ tb_ptr +=3D 2; @@ -418,54 +452,46 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, /* Load/store operations (32 bit). */ =20 CASE_32_64(ld8u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint8_t *)ptr; break; CASE_32_64(ld8s) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(int8_t *)ptr; break; CASE_32_64(ld16u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint16_t *)ptr; break; CASE_32_64(ld16s) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(int16_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(int16_t *)ptr; break; case INDEX_op_ld_i32: CASE_64(ld32u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint32_t *)ptr; break; CASE_32_64(st8) - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - *(uint8_t *)(t1 + t2) =3D t0; + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + *(uint8_t *)ptr =3D regs[r0]; break; CASE_32_64(st16) - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - *(uint16_t *)(t1 + t2) =3D t0; + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + *(uint16_t *)ptr =3D regs[r0]; break; case INDEX_op_st_i32: CASE_64(st32) - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - *(uint32_t *)(t1 + t2) =3D t0; + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + *(uint32_t *)ptr =3D regs[r0]; break; =20 /* Arithmetic operations (mixed 32/64 bit). */ @@ -690,22 +716,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, /* Load/store operations (64 bit). */ =20 case INDEX_op_ld32s_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(int32_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(int32_t *)ptr; break; case INDEX_op_ld_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint64_t *)ptr; break; case INDEX_op_st_i64: - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_s32(&tb_ptr); - *(uint64_t *)(t1 + t2) =3D t0; + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + *(uint64_t *)ptr =3D regs[r0]; break; =20 /* Arithmetic operations (64 bit). */ --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612405438; cv=none; d=zohomail.com; s=zohoarc; b=RQdwDXG8yx5m8L+IHXGVPfRGVJj3Hz/i4ClWx8DKR4H9gq1GqFuQu1s/Pksgql+li5AVSlrs/Xf5zzRaUFfC6tzdZLGEYeTokvhWlO0PQ9qlKkVBCMkbChxhRBWpI1Byj5ITAAQBqbNh3FEf9c6Oikjgb1h8fQxZJRQ8lune5o0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612405438; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SycMd2jWeSgxswrzk2jq/EmJnAdi6ZgvEeestJkdRLA=; b=LcynX8psXkzYNk3VoqoKQOagTyVjc12L4P6IvTI6/+BN3EwSwjgvHlydoGWzwE2KZ0 q4i5Z2FI5IiIsaIH0TUciUybrAAoPrCHSifCyxbMvzgwFN7qr4hHypUNVUHyDOILMXvX UYtre4vvp3Y3BO7VMFPu7IuZ0pno85Fz5nXLHM+E+NUh0iJYvKgvqNih5+mc2iOyPhSx EAfBJSddK0YCkx426ch7EJcAbONJZQhxAmLH1MrivIg3z4lErwNMXmjh+biZOuQHH5/o d/DT2FlzMf2xn55tgd7Mwvfv+WgzL6RdX/coIXfcVyPpqaskmMJpunOHAa1O1kg/Mcck si/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SycMd2jWeSgxswrzk2jq/EmJnAdi6ZgvEeestJkdRLA=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 67 +++++++++++++++++++++++++------------------------------ 1 file changed, 31 insertions(+), 36 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index be298ae39d..0bc5294e8b 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -184,6 +184,13 @@ static tcg_target_ulong tci_read_label(const uint8_t *= *tb_ptr) * s =3D signed ldst offset */ =20 +static void tci_args_rr(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); +} + static void tci_args_rrs(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, int32_t *i2) { @@ -439,9 +446,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif CASE_32_64(mov) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D regs[r1]; break; case INDEX_op_tci_movi_i32: t0 =3D *tb_ptr++; @@ -652,58 +658,50 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int8_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (int8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 CASE_32_64(ext16s) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int16_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (int16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 CASE_32_64(ext8u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint8_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (uint8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 CASE_32_64(ext16u) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint16_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (uint16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 CASE_32_64(bswap16) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap16(t1)); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D bswap16(regs[r1]); break; #endif #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 CASE_32_64(bswap32) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap32(t1)); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D bswap32(regs[r1]); break; #endif #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 CASE_32_64(not) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, ~t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D ~regs[r1]; break; #endif #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 CASE_32_64(neg) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, -t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D -regs[r1]; break; #endif #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -816,21 +814,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; case INDEX_op_ext32s_i64: case INDEX_op_ext_i32_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (int32_t)regs[r1]; break; case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D (uint32_t)regs[r1]; break; #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap64(t1)); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] =3D bswap64(regs[r1]); break; #endif #endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612405573; cv=none; d=zohomail.com; s=zohoarc; b=I33S8hQXcvDKtlUh97B09plbDF8vxyoJfbMSwTKlXuBeHjNLEtQ29O3h25hSyDdkno8Ma1HhCQGp0vnj0bBhpbiKtrEaNNVam6i8yLIjylRxjsngsxRcsdjYM2CJ8VyL4OrH/2mKqqKlEgEd/536WNtt2HhNclCGxfUkvTfFHT8= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 154 ++++++++++++++++++++---------------------------------- 1 file changed, 57 insertions(+), 97 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 0bc5294e8b..1736234bfd 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -191,6 +191,14 @@ static void tci_args_rr(const uint8_t **tb_ptr, *r1 =3D tci_read_r(tb_ptr); } =20 +static void tci_args_rrr(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); +} + static void tci_args_rrs(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, int32_t *i2) { @@ -366,7 +374,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint8_t op_size =3D tb_ptr[1]; const uint8_t *old_code_ptr =3D tb_ptr; #endif - TCGReg r0, r1; + TCGReg r0, r1, r2; tcg_target_ulong t0; tcg_target_ulong t1; tcg_target_ulong t2; @@ -503,101 +511,71 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchS= tate *env, /* Arithmetic operations (mixed 32/64 bit). */ =20 CASE_32_64(add) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 + t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] + regs[r2]; break; CASE_32_64(sub) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 - t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] - regs[r2]; break; CASE_32_64(mul) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 * t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] * regs[r2]; break; CASE_32_64(and) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] & regs[r2]; break; CASE_32_64(or) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] | regs[r2]; break; CASE_32_64(xor) - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] ^ regs[r2]; break; =20 /* Arithmetic operations (32 bit). */ =20 case INDEX_op_div_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int32_t)regs[r1] / (int32_t)regs[r2]; break; case INDEX_op_divu_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint32_t)regs[r1] / (uint32_t)regs[r2]; break; case INDEX_op_rem_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int32_t)regs[r1] % (int32_t)regs[r2]; break; case INDEX_op_remu_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint32_t)regs[r1] % (uint32_t)regs[r2]; break; =20 /* Shift/rotate operations (32 bit). */ =20 case INDEX_op_shl_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint32_t)regs[r1] << (regs[r2] & 31); break; case INDEX_op_shr_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint32_t)regs[r1] >> (regs[r2] & 31); break; case INDEX_op_sar_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int32_t)regs[r1] >> (regs[r2] & 31); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, rol32(t1, t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D rol32(regs[r1], regs[r2] & 31); break; case INDEX_op_rotr_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, ror32(t1, t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D ror32(regs[r1], regs[r2] & 31); break; #endif #if TCG_TARGET_HAS_deposit_i32 @@ -732,62 +710,44 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, /* Arithmetic operations (64 bit). */ =20 case INDEX_op_div_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int64_t)regs[r1] / (int64_t)regs[r2]; break; case INDEX_op_divu_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint64_t)regs[r1] / (uint64_t)regs[r2]; break; case INDEX_op_rem_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int64_t)regs[r1] % (int64_t)regs[r2]; break; case INDEX_op_remu_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (uint64_t)regs[r1] % (uint64_t)regs[r2]; break; =20 /* Shift/rotate operations (64 bit). */ =20 case INDEX_op_shl_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 << (t2 & 63)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] << (regs[r2] & 63); break; case INDEX_op_shr_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 >> (t2 & 63)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D regs[r1] >> (regs[r2] & 63); break; case INDEX_op_sar_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D (int64_t)regs[r1] >> (regs[r2] & 63); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, rol64(t1, t2 & 63)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D rol64(regs[r1], regs[r2] & 63); break; case INDEX_op_rotr_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, ror64(t1, t2 & 63)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] =3D ror64(regs[r1], regs[r2] & 63); break; #endif #if TCG_TARGET_HAS_deposit_i64 --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612405936; cv=none; d=zohomail.com; s=zohoarc; b=Dr/zv/3jFnnl3H/GGsO0F7p434LQiWglLsLfZzvL9SuQqTWUR2HA/OH0RxvEaTfUAy6NZF5At0rTe12GGikbrIVkL3SByDjrB18PUr+7nva3FFl6US7Po9j1TMpHNA5CTfy5kQNtsS+7Dev8M0GY1d2Cuuxb5XbZisoay+IYOH8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612405936; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 1736234bfd..86625061f1 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -207,6 +207,15 @@ static void tci_args_rrs(const uint8_t **tb_ptr, *i2 =3D tci_read_s32(tb_ptr); } =20 +static void tci_args_rrrc(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *c3 =3D tci_read_b(tb_ptr); +} + static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { bool result =3D false; @@ -430,11 +439,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tb_ptr =3D (uint8_t *)label; continue; case INDEX_op_setcond_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - condition =3D *tb_ptr++; - tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); + tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + regs[r0] =3D tci_compare32(regs[r1], regs[r2], condition); break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: @@ -446,11 +452,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, break; #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - condition =3D *tb_ptr++; - tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); + tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + regs[r0] =3D tci_compare64(regs[r1], regs[r2], condition); break; #endif CASE_32_64(mov) --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612405510; cv=none; d=zohomail.com; s=zohoarc; b=KnbyGP2hS88SulfCtKJOdZqfB9oINI/rAft9HQ3nlRHSpbLPOaaizdCzlgJ641nZrBY+abDdTF+aSP9MinpfBRvJa+oAYC2jdkXbcupdDHH/81P8u3zdWPi5AJEWCw8Ct6cRFrMySM5c+0MVZiVr2YXuUi1jW8uvZ3s6YML6jUM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612405510; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 86625061f1..8bc9dd27b0 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -184,6 +184,11 @@ static tcg_target_ulong tci_read_label(const uint8_t *= *tb_ptr) * s =3D signed ldst offset */ =20 +static void tci_args_l(const uint8_t **tb_ptr, void **l0) +{ + *l0 =3D (void *)tci_read_label(tb_ptr); +} + static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { @@ -434,9 +439,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif break; case INDEX_op_br: - label =3D tci_read_label(&tb_ptr); + tci_args_l(&tb_ptr, &ptr); tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr =3D (uint8_t *)label; + tb_ptr =3D ptr; continue; case INDEX_op_setcond_i32: tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612405331; cv=none; d=zohomail.com; s=zohoarc; b=afFX/TRbNqLpJXV22O73OYSGX0q1iG2/fMYJ3qLT64AIK8S7djB6NONt8N0fZxAi9Rauw10mqDp7kxHb+v3Zpsso8AkQFwc7iilHpijgkfGT9bYb01mMHOD0Fvw3O9hcTT+d6swhvS6iZ6Lt7m4gZlmI6+AI2nH/ce/5Awy2Kq8= ARC-Message-Signature: i=1; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EjI7Jfr8LIthM/+Hr8pg5fY2MZ87PA6SSlhcAVNxWvA=; b=G4HqM0/mqxJNMm3fqDKPNJKEWL26cvA+6DWhVEsAnvZ7U1V5D0UDAsYgTW6j3pfQKJ AFdxcii/wAJPtx57GcTmqlsHWWhPnUnZbJ9xDz1MX1C63Br/tOg2GCsuYvV+d8k1PUvx dIRfEx1BHhQpTDTmRlXLhW/U+7gaWWJoUJH7iPAoTHNM065qKuH9iLV67zwQQo1iQulX LnOE4fmxpBwEHV0BacxOdVCpzx2txURrIyZt5lml3CWYGl4nI/y1w+Scxa+TG3oGwmgs 1oGs1Oe3/yS5p0o+mal6tDvCG36cLpJKMRNwOVvqIZ2mNb7G8mCOHan/4nW3icPtvvxX i4sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EjI7Jfr8LIthM/+Hr8pg5fY2MZ87PA6SSlhcAVNxWvA=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 8bc9dd27b0..692b95b5c2 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -221,6 +221,19 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, *c3 =3D tci_read_b(tb_ptr); } =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 +static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); + *r4 =3D tci_read_r(tb_ptr); + *c5 =3D tci_read_b(tb_ptr); +} +#endif + static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { bool result =3D false; @@ -400,7 +413,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 - uint64_t v64; + TCGReg r3, r4; + uint64_t v64, T1, T2; #endif TCGMemOpIdx oi; int32_t ofs; @@ -449,11 +463,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: - t0 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(regs, &tb_ptr); - v64 =3D tci_read_r64(regs, &tb_ptr); - condition =3D *tb_ptr++; - tci_write_reg(regs, t0, tci_compare64(tmp64, v64, condition)); + tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &condition); + T1 =3D tci_uint64(regs[r2], regs[r1]); + T2 =3D tci_uint64(regs[r4], regs[r3]); + regs[r0] =3D tci_compare64(T1, T2, condition); break; #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612405673; cv=none; d=zohomail.com; s=zohoarc; b=R3J5BGUrxfsf7dRsOg1obrBaG06UTiuvJmGJa8xVBeUfWzf5k0ftV/G0k/hUmV6lJ75zHDyz5/2Lm8RFvQutMqEibNdv71h318P2+lvOreqUqs/kAb0Q+y8c6y0UMjyM82zy05pVOz0Wvy+zrH764s4UWi+lAQHIasEyGOaev6A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612405673; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 52 ++++++++++++++++++++++++++++++++-------------------- 1 file changed, 32 insertions(+), 20 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 692b95b5c2..1e2f78a9f9 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -212,6 +212,15 @@ static void tci_args_rrs(const uint8_t **tb_ptr, *i2 =3D tci_read_s32(tb_ptr); } =20 +static void tci_args_rrcl(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *c2 =3D tci_read_b(tb_ptr); + *l3 =3D (void *)tci_read_label(tb_ptr); +} + static void tci_args_rrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { @@ -222,6 +231,17 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 +static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); + *c4 =3D tci_read_b(tb_ptr); + *l5 =3D (void *)tci_read_label(tb_ptr); +} + static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) { @@ -405,7 +425,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tcg_target_ulong t0; tcg_target_ulong t1; tcg_target_ulong t2; - tcg_target_ulong label; TCGCond condition; target_ulong taddr; uint8_t tmp8; @@ -414,7 +433,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 TCGReg r3, r4; - uint64_t v64, T1, T2; + uint64_t T1, T2; #endif TCGMemOpIdx oi; int32_t ofs; @@ -611,13 +630,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; #endif case INDEX_op_brcond_i32: - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - condition =3D *tb_ptr++; - label =3D tci_read_label(&tb_ptr); - if (tci_compare32(t0, t1, condition)) { + tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); + if (tci_compare32(regs[r0], regs[r1], condition)) { tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr =3D (uint8_t *)label; + tb_ptr =3D ptr; continue; } break; @@ -637,13 +653,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tci_write_reg64(regs, t1, t0, tmp64); break; case INDEX_op_brcond2_i32: - tmp64 =3D tci_read_r64(regs, &tb_ptr); - v64 =3D tci_read_r64(regs, &tb_ptr); - condition =3D *tb_ptr++; - label =3D tci_read_label(&tb_ptr); - if (tci_compare64(tmp64, v64, condition)) { + tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr); + T1 =3D tci_uint64(regs[r1], regs[r0]); + T2 =3D tci_uint64(regs[r3], regs[r2]); + if (tci_compare64(T1, T2, condition)) { tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr =3D (uint8_t *)label; + tb_ptr =3D ptr; continue; } break; @@ -783,13 +798,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; #endif case INDEX_op_brcond_i64: - t0 =3D tci_read_rval(regs, &tb_ptr); - t1 =3D tci_read_rval(regs, &tb_ptr); - condition =3D *tb_ptr++; - label =3D tci_read_label(&tb_ptr); - if (tci_compare64(t0, t1, condition)) { + tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); + if (tci_compare64(regs[r0], regs[r1], condition)) { tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr =3D (uint8_t *)label; + tb_ptr =3D ptr; continue; } break; --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612405506; cv=none; d=zohomail.com; s=zohoarc; b=OfcZqoeiF5QLsg/1VzdudmsxOjTV3rYU0OUsf6wLHNSIQ8LnGioVkqYfNViByAX6OxkWQlJaIxmmdqDF0CLeksgX9XgULnNx8v26l42GpImtQp+jEZsAUVKgjQ/+56pYBRSabtiRidVXN5NC7zJhWmUUNcUYvxO7oknK2Uq7rd4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612405506; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eSQe6U/PGZwTawoh3F37z3+OGlTxy4qNiRyYKdayrlc=; b=n6HxQ7HTwPNL/EYFkUv50P9tDramywG6JzXiurMy+3MlZ6W4lvQhJ6aMFNGSlQSa+ik9mdMMWF8L7lB+vH68mQ6xYGIf8bAcpDn2LkRluoCI85Wa4uctDPVUyUDxlHL26yJTs11fUc6vjWE/cXQCk164ceZi48j9lFou/3bYvY4= ARC-Authentication-Results: i=1; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eSQe6U/PGZwTawoh3F37z3+OGlTxy4qNiRyYKdayrlc=; b=YRgSjIFtqOYC9COao5LQz+NRV/bQHYsFyGVsElMFCX8WRlHoqeENVpeMgRB7HtrpGX 2H5VjZH9sDJRjvSsi5+Dk3LGXh++v70hitglIRtug4mvFitnCl02Xtj4ElxUECrOY/mw /y6aMX8Y1D8Ugzf42r+Ks43WsCqfBMcuz10fz5awsFci+f2TQhbTud2KU7jyk5yNjstt zLEHSH88ivBspTNanRfpuYyqPMBtNIEFXJXtucjEEtt/hNlZiltGXkzKtG9aaZLUIo/x 5FOsirPGkCDCnLYAWv7mkFFndDhpePO0HvybUMQsDtDcks4Aui+rdHo0TJ36Jz0I7qjI bC0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eSQe6U/PGZwTawoh3F37z3+OGlTxy4qNiRyYKdayrlc=; b=fleDV2OAKepqD6PDGAtAEl4yGo77U8y2hZe0/baCLT0oeaG0Lx9kOTHHzK7MALg8pl EUxWD1nPoj4ArgjfDlh0fIsLGFPxal5Z1Injyhz9qRSiWFMHoVsU1N4Z9rQxP5WsmI4l canuyvaw1S287s3/fYHgCxf9I+o1+WG409qdfIKGE8S25JDXqelHHLf13chRMeQ3e8+p HcZe2ALYgXOEfq312w8Ne7dF/X3qbhlSPTzCN8gUuGbgMTGh4bt3PARdPvCA2TCcpHyU FMr9EOEf7zMe7/6UZjEbt5csrfkReYtgohpG0yrsVMgiBAW2A9AzKVL8uqGBvhod44w+ aQMA== X-Gm-Message-State: AOAM532RM+BW7e+aypyGBIGk1TICmWrvMtV3k0XJzuygW0j5kfpv3cXv 68z5/ul9ft1mygdNgtRFzUlV1ujJrBN5LTA0 X-Google-Smtp-Source: ABdhPJxkopD0x0Nb3yObSHAEeRD0gDnmH5WDH1MEYS8433WJ7OqAWOIinfO8oNJSI6E/Au5WeLuf5A== X-Received: by 2002:a17:90a:ce89:: with SMTP id g9mr5789092pju.42.1612403201943; Wed, 03 Feb 2021 17:46:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 50/93] tcg/tci: Split out tci_args_ri and tci_args_rI Date: Wed, 3 Feb 2021 15:44:26 -1000 Message-Id: <20210204014509.882821-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 1e2f78a9f9..5cc05fa554 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -121,16 +121,6 @@ static int32_t tci_read_s32(const uint8_t **tb_ptr) return value; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -/* Read constant (64 bit) from bytecode. */ -static uint64_t tci_read_i64(const uint8_t **tb_ptr) -{ - uint64_t value =3D *(const uint64_t *)(*tb_ptr); - *tb_ptr +=3D sizeof(value); - return value; -} -#endif - /* Read indexed register (native size) from bytecode. */ static tcg_target_ulong tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -180,6 +170,8 @@ static tcg_target_ulong tci_read_label(const uint8_t **= tb_ptr) * tci_args_ * where arguments is a sequence of * + * i =3D immediate (uint32_t) + * I =3D immediate (tcg_target_ulong) * r =3D register * s =3D signed ldst offset */ @@ -196,6 +188,22 @@ static void tci_args_rr(const uint8_t **tb_ptr, *r1 =3D tci_read_r(tb_ptr); } =20 +static void tci_args_ri(const uint8_t **tb_ptr, + TCGReg *r0, tcg_target_ulong *i1) +{ + *r0 =3D tci_read_r(tb_ptr); + *i1 =3D tci_read_i32(tb_ptr); +} + +#if TCG_TARGET_REG_BITS =3D=3D 64 +static void tci_args_rI(const uint8_t **tb_ptr, + TCGReg *r0, tcg_target_ulong *i1) +{ + *r0 =3D tci_read_r(tb_ptr); + *i1 =3D tci_read_i(tb_ptr); +} +#endif + static void tci_args_rrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2) { @@ -498,9 +506,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, regs[r0] =3D regs[r1]; break; case INDEX_op_tci_movi_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_i32(&tb_ptr); - tci_write_reg(regs, t0, t1); + tci_args_ri(&tb_ptr, &r0, &t1); + regs[r0] =3D t1; break; =20 /* Load/store operations (32 bit). */ @@ -720,9 +727,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #endif #if TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_tci_movi_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_i64(&tb_ptr); - tci_write_reg(regs, t0, t1); + tci_args_rI(&tb_ptr, &r0, &t1); + regs[r0] =3D t1; break; =20 /* Load/store operations (64 bit). */ --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Date: Wed, 3 Feb 2021 15:44:27 -1000 Message-Id: <20210204014509.882821-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 5cc05fa554..92b13829c3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -452,30 +452,30 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 switch (opc) { case INDEX_op_call: - t0 =3D tci_read_i(&tb_ptr); + tci_args_l(&tb_ptr, &ptr); tci_tb_ptr =3D (uintptr_t)tb_ptr; #if TCG_TARGET_REG_BITS =3D=3D 32 - tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5), - tci_read_reg(regs, TCG_REG_R6), - tci_read_reg(regs, TCG_REG_R7), - tci_read_reg(regs, TCG_REG_R8), - tci_read_reg(regs, TCG_REG_R9), - tci_read_reg(regs, TCG_REG_R10), - tci_read_reg(regs, TCG_REG_R11)); + tmp64 =3D ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0= ), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R4), + tci_read_reg(regs, TCG_REG_R5), + tci_read_reg(regs, TCG_REG_R6), + tci_read_reg(regs, TCG_REG_R7), + tci_read_reg(regs, TCG_REG_R8), + tci_read_reg(regs, TCG_REG_R9), + tci_read_reg(regs, TCG_REG_R10), + tci_read_reg(regs, TCG_REG_R11)= ); tci_write_reg(regs, TCG_REG_R0, tmp64); tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); #else - tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5)); + tmp64 =3D ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0= ), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R4), + tci_read_reg(regs, TCG_REG_R5)); tci_write_reg(regs, TCG_REG_R0, tmp64); #endif break; --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612405782; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SiXlz8iU8i8mL6XFtS7HcVMO8xC61iquHDNUAoO7sPU=; b=hiG+dztcIn9Nhpj83I3qjdwExxUgw9sdDINPStrgmg15gZtHqnfLIHnIm/QDm8Frir 6DpY82HCGtCXTomQ0lcn8hsjI6ut+cTgSqkByBHsUwi/TbYI22dK/HjcG8dOYnTmVjgU B0Unm/IYlhvTc+16DRGds0ZSfTUtUWXzlK4QLiPSy1mDdn+hf41oGX9ivtRftO1e+cjx Pp+iL7nhcnAXs7EPm/SEWSs3B9MJzk6o0Xl4BN5C1LsKZOem1pqgDAZIkwpgicB9RNcK nAzkPME/LMJDB3z6uXFSoSadXw+ZIvRrpx62tsF1jPYPCJPbdXwg9pApoRoCgbfiaZ9d 46Ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SiXlz8iU8i8mL6XFtS7HcVMO8xC61iquHDNUAoO7sPU=; b=UAEaKjtYIRLAy8lIzJOQ/K5BahiNoF5FLTmS5exY0TNds8e9jn+VJu8KmPkSDX6hDI 3ZPmAY5dZKnYiE5Xr0nXT/ZkUZOR1HuUQM45W8n/WydDs2PvG5llgmLZUpcKak9PIWac u/+l8M6eJMmQ0LqdL49t5nNR/guUAcS6v5VQNYTfzYY7oBbYTANsVFLt3tUSbBNEEajl 5KFqI+FCMQA63RfRypxawezSClNTTMXVeWwc4T+tAfmHZp1/9ZhUUetpfszGby5rPilY IeFiPTwGlgRYLl9MM+80LeK1cvV71S6XDv9rvl98UDDA0Xj/5hJy/XV09eEQdxWIdO64 7X1w== X-Gm-Message-State: AOAM530pLaSVkqtRpjFHIE8HYCyfJMgNJiGhu44dwHM5yM7ErdQUzZfN D2bksxfMscs18b6ueyoR9QjHEilKZ04EUIIX X-Google-Smtp-Source: ABdhPJyKk11Q1moMYshAhNH0rSfS+ZEkeMI78a5OnFzNwj50uaOx7Uy+JAiO/jRtogLk+pvwXlfAPg== X-Received: by 2002:a65:44c5:: with SMTP id g5mr6641718pgs.295.1612403205478; Wed, 03 Feb 2021 17:46:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 52/93] tcg/tci: Reuse tci_args_l for exit_tb Date: Wed, 3 Feb 2021 15:44:28 -1000 Message-Id: <20210204014509.882821-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Do not emit a uint64_t, but a tcg_target_ulong, aka uintptr_t. This reduces the size of the constant on 32-bit hosts. The assert for label !=3D NULL has to be removed because that is a valid value for exit_tb. Signed-off-by: Richard Henderson --- tcg/tci.c | 13 ++++--------- tcg/tci/tcg-target.c.inc | 2 +- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 92b13829c3..57b6defe09 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -160,9 +160,7 @@ tci_read_ulong(const tcg_target_ulong *regs, const uint= 8_t **tb_ptr) =20 static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) { - tcg_target_ulong label =3D tci_read_i(tb_ptr); - tci_assert(label !=3D 0); - return label; + return tci_read_i(tb_ptr); } =20 /* @@ -417,7 +415,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tcg_target_ulong regs[TCG_TARGET_NB_REGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS]; uintptr_t sp_value =3D (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); - uintptr_t ret =3D 0; =20 regs[TCG_AREG0] =3D (tcg_target_ulong)env; regs[TCG_REG_CALL_STACK] =3D sp_value; @@ -832,9 +829,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, /* QEMU specific operations. */ =20 case INDEX_op_exit_tb: - ret =3D *(uint64_t *)tb_ptr; - goto exit; - break; + tci_args_l(&tb_ptr, &ptr); + return (uintptr_t)ptr; + case INDEX_op_goto_tb: /* Jump address is aligned */ tb_ptr =3D QEMU_ALIGN_PTR_UP(tb_ptr, 4); @@ -992,6 +989,4 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, } tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); } -exit: - return ret; } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c79f9c32d8..ff8040510f 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -401,7 +401,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, =20 switch (opc) { case INDEX_op_exit_tb: - tcg_out64(s, args[0]); + tcg_out_i(s, args[0]); break; =20 case INDEX_op_goto_tb: --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612406000; cv=none; d=zohomail.com; s=zohoarc; b=aFT8Tu/9SMUyvQL9UMLK9KICM9e8kQXxkCOaYKd2tjmllIp2CgD07kQj+TJ4j4TnjpHNRQUGeC73thavtma9gXbYU3+mKtIT1G/YPeQDYrsv0AuQG2cPJMYhTBSHIf1gdera+bV1aBMgZYi+kqAagh0ZHBX58B4S21012boiLdg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612406000; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1LT2MbDB8DSsnJ6nk4ZYA0KuSI+0ipd9FJnZcTxjPRQ=; b=dK3v+54hi8Wh1wavLgTc0neaMNo6EJuNJIgZ9JK3dG38upWDzFKlJzmPOxw5qWohJmH8t0QtdSi5tiWbRYL9qhmuYCmXEiuqEUi0eZlomNvBf0cGzkLC5NxGrvoFqo13Fju0VWfF96BNpwqygYQ7o+29czRB4KzOI3KQmeMWbeE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612406000134118.90878322359754; Wed, 3 Feb 2021 18:33:20 -0800 (PST) Received: from localhost ([::1]:44444 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7USM-0000Cw-Oi for importer@patchew.org; Wed, 03 Feb 2021 21:33:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7TjO-0005YZ-OV for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:50 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:46286) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7TjM-00041z-4L for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:50 -0500 Received: by mail-pl1-x636.google.com with SMTP id u11so865709plg.13 for ; Wed, 03 Feb 2021 17:46:47 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1LT2MbDB8DSsnJ6nk4ZYA0KuSI+0ipd9FJnZcTxjPRQ=; b=HbGV/3iKFDtFAmLUS7tlS7c69oaaLBT8pIaNn1nBNJL0beoC+AVcadAEgHwKl3pfjt wE3I8W0A9FscBLk8Zx61TVnOHXTI70gE4aWcax7OfWZzzJjgGlVmELkCGTV89NWQ5VYR NyCc8M0o6Wmqxctr/JyNaI3h7RJuch3CJT31bc0IkLsEcRGdSU7Gvq4yH6g238FV2Ajs 6mm+nOIjFo0GLqmGkThq92xFnkgzf1m+o5SmxbMPfq0XN4YOyj7r03SuDg55Ltz74sZA vQOT29h3lOsxGGJvdUG24zplL18P6oWycd1t9sKyLqwR8VmpgEvcZhc+mKDJ2Yin/uZr 4Gfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1LT2MbDB8DSsnJ6nk4ZYA0KuSI+0ipd9FJnZcTxjPRQ=; b=hKw42rs64W0Zs1XY5RX3TTATTVJ0ngw1xXsrhEQJN+AHos1Z888dkzGdS/95D9QQx2 g7bFVISF9UMF1mlmWR3YUXByBlEBFaLVbB0EtFsZ6nR0qN8yL9kj2kJmludZXQCa1OSi ipxW1RAarvZlMKlIPgxdQZDnffD3x+SUTFHVAU4hORDcPGh7++skGvRZlnPfRUW0u6Qr mrIqOf2LAfSkbakq1ZQhMehMdNEbVwDltDatz1hA2bOGlrlViwvY6K7yE63gLP+TA8YA oY6aPRcg1KRZaiN/pVggwjjnUSzV3P+ZEHDm8jM4SO3smArhjixPcES3SER7V3UCnglt 048A== X-Gm-Message-State: AOAM530FjkCwuAjK9aZdGverxOFzFpGJW5+0+Nqnq7fueGXgNO3KXwk3 rzgjmRiDFuBvWKkXcU9ZNi5yHZHi14c+NAb7 X-Google-Smtp-Source: ABdhPJzD1WtOAXwYHO9Kdvs3/jtaoZFkx6o3EBAcTAcX4NplyJ2+mTMEb8GkCFmKn1mXuGAyRvZycQ== X-Received: by 2002:a17:902:c942:b029:de:abac:f9c4 with SMTP id i2-20020a170902c942b02900deabacf9c4mr5582718pla.30.1612403206915; Wed, 03 Feb 2021 17:46:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 53/93] tcg/tci: Reuse tci_args_l for goto_tb Date: Wed, 3 Feb 2021 15:44:29 -1000 Message-Id: <20210204014509.882821-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert to indirect jumps, as it's less complicated. Then we just have a pointer to the tb address at which the chain is stored, from which we read. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 11 +++-------- tcg/tci.c | 8 +++----- tcg/tci/tcg-target.c.inc | 13 +++---------- 3 files changed, 9 insertions(+), 23 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 9c0021a26f..9285c930a2 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -87,7 +87,7 @@ #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 0 -#define TCG_TARGET_HAS_direct_jump 1 +#define TCG_TARGET_HAS_direct_jump 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -174,12 +174,7 @@ void tci_disas(uint8_t opc); =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 -static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jm= p_rx, - uintptr_t jmp_rw, uintptr_t ad= dr) -{ - /* patch the branch destination */ - qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4)); - /* no need to flush icache explicitly */ -} +/* not defined -- call should be eliminated at compile time */ +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 #endif /* TCG_TARGET_H */ diff --git a/tcg/tci.c b/tcg/tci.c index 57b6defe09..0301ee63a7 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -833,13 +833,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, return (uintptr_t)ptr; =20 case INDEX_op_goto_tb: - /* Jump address is aligned */ - tb_ptr =3D QEMU_ALIGN_PTR_UP(tb_ptr, 4); - t0 =3D qatomic_read((int32_t *)tb_ptr); - tb_ptr +=3D sizeof(int32_t); + tci_args_l(&tb_ptr, &ptr); tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); - tb_ptr +=3D (int32_t)t0; + tb_ptr =3D *(void **)ptr; continue; + case INDEX_op_qemu_ld_i32: t0 =3D *tb_ptr++; taddr =3D tci_read_ulong(regs, &tb_ptr); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index ff8040510f..2c64b4f617 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -405,16 +405,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, break; =20 case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset) { - /* Direct jump method. */ - /* Align for atomic patching and thread safety */ - s->code_ptr =3D QEMU_ALIGN_PTR_UP(s->code_ptr, 4); - s->tb_jmp_insn_offset[args[0]] =3D tcg_current_code_size(s); - tcg_out32(s, 0); - } else { - /* Indirect jump method. */ - TODO(); - } + tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); + /* indirect jump method. */ + tcg_out_i(s, (uintptr_t)(s->tb_jmp_target_addr + args[0])); set_jmp_reset_offset(s, args[0]); break; =20 --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612405899; cv=none; d=zohomail.com; s=zohoarc; b=F2mAGC/CIPw/sW1lkwL/w2Prljz2LFx6fNX7g5FBEBGyDTqqqNRmapYHWjU+wVE0JzeZlqlUCCU8DAxt+iQWYB4tHqvRTDNRsbDXCtKNhoFxFf/+vtIvdWnE3AUmyiJQcd9hQOc453z77L1U1Uc+FGAUNAZSsXmZs8VUKKkD8zw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612405899; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CAFEcBhH5Bm/1S+hn6Be2S25m9MyX50Fw2Tvsr0CL7s=; b=WPrDIdq7VyYVjy2qMqb76SilcdKAGVeg/7lgq5zoS45urJ1wHVjsrhVkG9iZ5Wh3YZyTJrixmrBqEZ19d3m0vK9TLliFPgxfnoY2p5/uMLX534nsUx5F43vXfNglMp9YsNHsX9Mnbzvr6l02H9fLt9949J6wAHDvm3vDqPLXjXM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612405899419902.8483498506638; Wed, 3 Feb 2021 18:31:39 -0800 (PST) Received: from localhost ([::1]:40200 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7UQj-0006on-9l for importer@patchew.org; Wed, 03 Feb 2021 21:31:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45048) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7TjP-0005aA-H7 for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:52 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:43882) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7TjN-00042D-P7 for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:51 -0500 Received: by mail-pl1-x632.google.com with SMTP id 8so873960plc.10 for ; Wed, 03 Feb 2021 17:46:49 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 0301ee63a7..84d77855ee 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -258,6 +258,17 @@ static void tci_args_rrrrrc(const uint8_t **tb_ptr, TC= GReg *r0, TCGReg *r1, *r4 =3D tci_read_r(tb_ptr); *c5 =3D tci_read_b(tb_ptr); } + +static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); + *r4 =3D tci_read_r(tb_ptr); + *r5 =3D tci_read_r(tb_ptr); +} #endif =20 static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) @@ -437,7 +448,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r3, r4; + TCGReg r3, r4, r5; uint64_t T1, T2; #endif TCGMemOpIdx oi; @@ -643,18 +654,16 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: - t0 =3D *tb_ptr++; - t1 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(regs, &tb_ptr); - tmp64 +=3D tci_read_r64(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, tmp64); + tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + T1 =3D tci_uint64(regs[r3], regs[r2]); + T2 =3D tci_uint64(regs[r5], regs[r4]); + tci_write_reg64(regs, r1, r0, T1 + T2); break; case INDEX_op_sub2_i32: - t0 =3D *tb_ptr++; - t1 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(regs, &tb_ptr); - tmp64 -=3D tci_read_r64(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, tmp64); + tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + T1 =3D tci_uint64(regs[r3], regs[r2]); + T2 =3D tci_uint64(regs[r5], regs[r4]); + tci_write_reg64(regs, r1, r0, T1 - T2); break; case INDEX_op_brcond2_i32: tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr); --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612406062; cv=none; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 84d77855ee..cb24295cd9 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -237,6 +237,15 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 +static void tci_args_rrrr(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); +} + static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) { @@ -676,11 +685,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, } break; case INDEX_op_mulu2_i32: - t0 =3D *tb_ptr++; - t1 =3D *tb_ptr++; - t2 =3D tci_read_rval(regs, &tb_ptr); - tmp64 =3D (uint32_t)tci_read_rval(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); + tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wOvkZ0sAbeq0kMMHx/GBq6hm2tymswKeRwzIJ0G9jzI=; b=D+WNkqjAdin8oWFhpTBepHLSSnPH+QAFj3X8tEoS4dFbup/c5O9E3kygGkX40u/Msu cK34j2gbriB3VJ9Q7hiQ/4MOjDIgoihXcIVoitFHhW82Ll/AGvP4ID/Mt9y7/glhrnIA 6JRa9fPas5iUqbutKWJrhM9MjRUP7a1y/1WbUaLqo7O1gRSae7MuuQ9L7azGoE6+JnOL CDcUtALWUH/ujZM7yPz9eO9vK/JBbQWrgTsDI70gJs7+ACFCfrlck5Wu/xv2FwJjdcjR qnLR29aye2h1+1cRHp9aITiEppGDCLxaKuhQZplU+vl/Ja6mdKhVbRndnj5AwTTEjHek ZlqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wOvkZ0sAbeq0kMMHx/GBq6hm2tymswKeRwzIJ0G9jzI=; b=CNOlB4z7fVKyBauTpnYdhiSFdbng16C61pe4y5ESWHpJ3O8vNq1TCQ1IsaSBcIONpK bPc3mSU9u1pMUkO2oNGc54oBA2haDiZszivnNvgBHfQCuPnWg56i4bsRDm2MgHPfp6X0 vCA5pJ25dicIq1nFR39X6TSOMcgqBpmPMNHwCVwLyDJss6Rdcs9/Y2asR2oqRIaoSoBH aIP5hcSBZ7c38fGij4zD0Wga5Kt1O7622IlxZyNOZwoingEQ39fHA0MXV5tusNay0J8J Pn7ivZWIqNVdFvNfR0rlND7+5bONSySJe7VZJIF43YVFCK3YE4Xui7g3KbuG9hfZgij/ aGvQ== X-Gm-Message-State: AOAM531sqvuF9FE9N6jMbrZXO1h9hPH5AvB/t8q27D3e5CyCQwkUGTN1 nTPwBPRABAEBmMp4OuTkwPEWkRrbDZUqmJIO X-Google-Smtp-Source: ABdhPJwuQoVwJIx4Rp69YMcRonNu81A48PcCVmFSnaEUkg66gN2UuLoeAacz+fTbQHjx6GStEJmHSA== X-Received: by 2002:a63:d855:: with SMTP id k21mr6417323pgj.399.1612403211710; Wed, 03 Feb 2021 17:46:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 56/93] tcg/tci: Clean up deposit operations Date: Wed, 3 Feb 2021 15:44:32 -1000 Message-Id: <20210204014509.882821-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use the correct set of asserts during code generation. We do not require the first input to overlap the output; the existing interpreter already supported that. Split out tci_args_rrrbb in the translator. Use the deposit32/64 functions rather than inline expansion. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-con-set.h | 1 - tcg/tci.c | 33 ++++++++++++++++----------------- tcg/tci/tcg-target.c.inc | 24 ++++++++++++++---------- 3 files changed, 30 insertions(+), 28 deletions(-) diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h index f51b7bcb13..316730f32c 100644 --- a/tcg/tci/tcg-target-con-set.h +++ b/tcg/tci/tcg-target-con-set.h @@ -13,7 +13,6 @@ C_O0_I2(r, r) C_O0_I3(r, r, r) C_O0_I4(r, r, r, r) C_O1_I1(r, r) -C_O1_I2(r, 0, r) C_O1_I2(r, r, r) C_O1_I4(r, r, r, r, r) C_O2_I1(r, r, r) diff --git a/tcg/tci.c b/tcg/tci.c index cb24295cd9..e10ccfc344 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -168,6 +168,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **= tb_ptr) * tci_args_ * where arguments is a sequence of * + * b =3D immediate (bit position) * i =3D immediate (uint32_t) * I =3D immediate (tcg_target_ulong) * r =3D register @@ -236,6 +237,16 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, *c3 =3D tci_read_b(tb_ptr); } =20 +static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, uint8_t *i3, uint8_t *i4) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *i3 =3D tci_read_b(tb_ptr); + *i4 =3D tci_read_b(tb_ptr); +} + #if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) @@ -449,11 +460,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, TCGReg r0, r1, r2; tcg_target_ulong t0; tcg_target_ulong t1; - tcg_target_ulong t2; TCGCond condition; target_ulong taddr; - uint8_t tmp8; - uint16_t tmp16; + uint8_t pos, len; uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 @@ -644,13 +653,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tmp16 =3D *tb_ptr++; - tmp8 =3D *tb_ptr++; - tmp32 =3D (((1 << tmp8) - 1) << tmp16); - tci_write_reg(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32= )); + tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + regs[r0] =3D deposit32(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i32: @@ -806,13 +810,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: - t0 =3D *tb_ptr++; - t1 =3D tci_read_rval(regs, &tb_ptr); - t2 =3D tci_read_rval(regs, &tb_ptr); - tmp16 =3D *tb_ptr++; - tmp8 =3D *tb_ptr++; - tmp64 =3D (((1ULL << tmp8) - 1) << tmp16); - tci_write_reg(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64= )); + tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + regs[r0] =3D deposit64(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i64: diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 2c64b4f617..640407b4a8 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -126,11 +126,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpco= de op) case INDEX_op_rotr_i64: case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - return C_O1_I2(r, r, r); - case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return C_O1_I2(r, 0, r); + return C_O1_I2(r, r, r); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: @@ -480,13 +478,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, break; =20 CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_debug_assert(args[3] <=3D UINT8_MAX); - tcg_out8(s, args[3]); - tcg_debug_assert(args[4] <=3D UINT8_MAX); - tcg_out8(s, args[4]); + { + TCGArg pos =3D args[3], len =3D args[4]; + TCGArg max =3D opc =3D=3D INDEX_op_deposit_i32 ? 32 : 64; + + tcg_debug_assert(pos < max); + tcg_debug_assert(pos + len <=3D max); + + tcg_out_r(s, args[0]); + tcg_out_r(s, args[1]); + tcg_out_r(s, args[2]); + tcg_out8(s, pos); + tcg_out8(s, len); + } break; =20 CASE_32_64(brcond) --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612405283; cv=none; d=zohomail.com; s=zohoarc; b=l7ftBa/oYNtrsMh3qErqmvOHdjD/BWKaEMMzSrBKyqxDMdUuEtmI0W3hZzxd7fp8PpR0rpZeRUylLcilfmbSlU0EMZ+44BaSf4+I6a0Rlobyg1E+OI23h8hVLJwqFwkpsZfPLU9skcHjToe0f1K/ALz6m59ouWtChyPAlxEzO0k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612405283; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fkXespGLacfat/Oc2ATzIf/ZqfIgEJ0vqqLFj00td/k=; b=WtIUTP/v2VrGLB6Wla2fDOU0NFqH0nSfYI5xIWwiYkVHmijaDI3S8ZBTFDiAGE7HZWpGaBOWNZuyZSVF/G2bgNkKRkqi+qtJJjbggqqYFpwjrs1LSvhsDV2+o4kGx1+Wg9rh6cw39JBgm3iu/kokxwlO/gSp8YgA6WNC9EXLpfk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612405283253698.8247151969483; Wed, 3 Feb 2021 18:21:23 -0800 (PST) Received: from localhost ([::1]:41170 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7UGn-0003YT-UA for importer@patchew.org; Wed, 03 Feb 2021 21:21:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45104) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7TjV-0005lV-1D for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:57 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:43360) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7TjS-00044d-K1 for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:56 -0500 Received: by mail-pf1-x431.google.com with SMTP id q131so1057881pfq.10 for ; Wed, 03 Feb 2021 17:46:54 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fkXespGLacfat/Oc2ATzIf/ZqfIgEJ0vqqLFj00td/k=; b=r6PYrn0ObFOVP9x9l/TTdhUh+ugROYzSwwYIrTiIG9RgyWimodhIkxi9o13hyFfyYj 4iNAsz1Vrdfn2SUPwBKHh8sVG8v41ioLWTAuo3NgNRdM4DVZseJoFzgDeqxBl7s/ddCp ypTmoSCg2yvUdhoHrLe8QKUPC0neeYzcwXM1+no7t8KlHr77+ZY+mbHGPkRZT0zQpwkM qoQfrsXX6xqfmmcYpQLvX31KgFj3mPtJlL19UtvElvD8lalpLfLtb4pD1uwGuYI9Sv5z yua84T0A2l+3dM30WG9EFx0dZj3xTLsnqsbEbVzud9WPJOGCHgErXcAVWxCZuWloh/5u N1eA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fkXespGLacfat/Oc2ATzIf/ZqfIgEJ0vqqLFj00td/k=; b=X2F5mGOMRkDMQUPyExoiADoFmQGcvT0rcV/2vODYHzsg3NhitWWHf6ePb8Da0aa8cp 7yiIsEY+Cr+PbkBs7nIEJaoCSrZgabO28BKzNCyQeN5GQtmAi06pJQ+1j+8XKFeumMLH Ktd6lbPc5GVKbLq1x2HI3NIqhOhbbwMN9Dfm3uTfu0fUH1mGXgtR1vwg9Wa3U2aiGRUi aNTWHZCAiBuMH/w/Dj3xUo0nUyurO+DVpjpl4QZMfCM+ZshB2j38ZIUYJEoKZE0Td+WO eP5TKaveYXnDE6nRyyEBe/cYj8ZgHI2/bpGAycDBDmCaXTgUxfzFlJco+LAcXH/RyVlT InJQ== X-Gm-Message-State: AOAM532750lEhz3qD5aQm1CQQmkXaoxxhzTNYbLklvJjLfsGm5qxkZ4O sG1f4oIMMl0I90pVIKyUaHMGVf7hhWOrMKLe X-Google-Smtp-Source: ABdhPJyEkHpuZH9Q7Q59HQSfoPbryO9oV3cu5iyl7iL06MiQ9M75w//P73zgO6S8bv88XlUxwP0RsQ== X-Received: by 2002:a63:c1d:: with SMTP id b29mr6621757pgl.9.1612403213294; Wed, 03 Feb 2021 17:46:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 57/93] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits Date: Wed, 3 Feb 2021 15:44:33 -1000 Message-Id: <20210204014509.882821-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We are currently using the "natural" size routine, which uses 64-bits on a 64-bit host. The TCGMemOpIdx operand has 11 bits, so we can safely reduce to 32-bits. Signed-off-by: Richard Henderson --- tcg/tci.c | 8 ++++---- tcg/tci/tcg-target.c.inc | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index e10ccfc344..ddc138359b 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -855,7 +855,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_qemu_ld_i32: t0 =3D *tb_ptr++; taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i(&tb_ptr); + oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp32 =3D qemu_ld_ub; @@ -892,7 +892,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, t1 =3D *tb_ptr++; } taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i(&tb_ptr); + oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp64 =3D qemu_ld_ub; @@ -941,7 +941,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_qemu_st_i32: t0 =3D tci_read_rval(regs, &tb_ptr); taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i(&tb_ptr); + oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: qemu_st_b(t0); @@ -965,7 +965,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_qemu_st_i64: tmp64 =3D tci_read_r64(regs, &tb_ptr); taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i(&tb_ptr); + oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: qemu_st_b(tmp64); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 640407b4a8..6c187a25cc 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -550,7 +550,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { tcg_out_r(s, *args++); } - tcg_out_i(s, *args++); + tcg_out32(s, *args++); break; =20 case INDEX_op_qemu_ld_i64: @@ -563,7 +563,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { tcg_out_r(s, *args++); } - tcg_out_i(s, *args++); + tcg_out32(s, *args++); break; =20 case INDEX_op_mb: --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612406137; cv=none; d=zohomail.com; s=zohoarc; b=AMrmhRkYmxo2YYmZm/NHrre5SSXuJBEtEzzfbFrERaPjZ9wyoPorMqmyUPxjMxlG+yWEpFv91imfMESVsZVpjMaXze52Ekwt6Sw0l5kKfmkjASVAcIX454jmQiFbg/Y1da9JQ4/2W/WKgB97Ug+2ePCHG7z0S3g3efFHpAghdcA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612406137; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Q08wWJmkpMRbD1uCLvdIthjIJ7wpxGIx6PIRtX9sdqE=; b=gktbsVHUBWTJ7c/j2XTOAc/tWcjb50HZV3S5R48OWhv5xHCGxMcfQlATkeG6Hypa4X+W144/2vWMf1abRt7scQpyjhdjiJph+S4BeDA4wlbFOl1BicU3PgqtdTIvWPEypcySozgjsxGVj2ZNSG3dOhzLSmzVJvyc7YZ213pAGt4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612406137499663.6519730794373; Wed, 3 Feb 2021 18:35:37 -0800 (PST) Received: from localhost ([::1]:53330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7UUa-0003qF-By for importer@patchew.org; Wed, 03 Feb 2021 21:35:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7TjW-0005pQ-HU for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:58 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:55432) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7TjU-00044r-A2 for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:58 -0500 Received: by mail-pj1-x1029.google.com with SMTP id s24so768877pjp.5 for ; Wed, 03 Feb 2021 17:46:55 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 147 ++++++++++++++++++++++++++++++------------------------ 1 file changed, 81 insertions(+), 66 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index ddc138359b..a1846825ea 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -66,22 +66,18 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg= _target_ulong value) regs[index] =3D value; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, uint32_t low_index, uint64_t value) { tci_write_reg(regs, low_index, value); tci_write_reg(regs, high_index, value >> 32); } -#endif =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 /* Create a 64 bit value from two 32 bit values. */ static uint64_t tci_uint64(uint32_t high, uint32_t low) { return ((uint64_t)high << 32) + low; } -#endif =20 /* Read constant byte from bytecode. */ static uint8_t tci_read_b(const uint8_t **tb_ptr) @@ -121,43 +117,6 @@ static int32_t tci_read_s32(const uint8_t **tb_ptr) return value; } =20 -/* Read indexed register (native size) from bytecode. */ -static tcg_target_ulong -tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr) -{ - tcg_target_ulong value =3D tci_read_reg(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; -} - -#if TCG_TARGET_REG_BITS =3D=3D 32 -/* Read two indexed registers (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_r64(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - uint32_t low =3D tci_read_rval(regs, tb_ptr); - return tci_uint64(tci_read_rval(regs, tb_ptr), low); -} -#elif TCG_TARGET_REG_BITS =3D=3D 64 -/* Read indexed register (64 bit) from bytecode. */ -static uint64_t tci_read_r64(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - return tci_read_rval(regs, tb_ptr); -} -#endif - -/* Read indexed register(s) with target address from bytecode. */ -static target_ulong -tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr) -{ - target_ulong taddr =3D tci_read_rval(regs, tb_ptr); -#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - taddr +=3D (uint64_t)tci_read_rval(regs, tb_ptr) << 32; -#endif - return taddr; -} - static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) { return tci_read_i(tb_ptr); @@ -171,6 +130,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **= tb_ptr) * b =3D immediate (bit position) * i =3D immediate (uint32_t) * I =3D immediate (tcg_target_ulong) + * m =3D immediate (TCGMemOpIdx) * r =3D register * s =3D signed ldst offset */ @@ -203,6 +163,14 @@ static void tci_args_rI(const uint8_t **tb_ptr, } #endif =20 +static void tci_args_rrm(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *m2 =3D tci_read_i32(tb_ptr); +} + static void tci_args_rrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2) { @@ -237,6 +205,15 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, *c3 =3D tci_read_b(tb_ptr); } =20 +static void tci_args_rrrm(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx = *m3) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *m3 =3D tci_read_i32(tb_ptr); +} + static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, uint8_t *i3, uint8_t *i4) { @@ -247,6 +224,16 @@ static void tci_args_rrrbb(const uint8_t **tb_ptr, TCG= Reg *r0, TCGReg *r1, *i4 =3D tci_read_b(tb_ptr); } =20 +static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4) +{ + *r0 =3D tci_read_r(tb_ptr); + *r1 =3D tci_read_r(tb_ptr); + *r2 =3D tci_read_r(tb_ptr); + *r3 =3D tci_read_r(tb_ptr); + *m4 =3D tci_read_i32(tb_ptr); +} + #if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) @@ -457,8 +444,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint8_t op_size =3D tb_ptr[1]; const uint8_t *old_code_ptr =3D tb_ptr; #endif - TCGReg r0, r1, r2; - tcg_target_ulong t0; + TCGReg r0, r1, r2, r3; tcg_target_ulong t1; TCGCond condition; target_ulong taddr; @@ -466,7 +452,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r3, r4, r5; + TCGReg r4, r5; uint64_t T1, T2; #endif TCGMemOpIdx oi; @@ -853,9 +839,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, continue; =20 case INDEX_op_qemu_ld_i32: - t0 =3D *tb_ptr++; - taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i32(&tb_ptr); + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr =3D regs[r1]; + } else { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr =3D tci_uint64(regs[r2], regs[r1]); + } switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp32 =3D qemu_ld_ub; @@ -884,15 +874,20 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, default: g_assert_not_reached(); } - tci_write_reg(regs, t0, tmp32); + regs[r0] =3D tmp32; break; + case INDEX_op_qemu_ld_i64: - t0 =3D *tb_ptr++; - if (TCG_TARGET_REG_BITS =3D=3D 32) { - t1 =3D *tb_ptr++; + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr =3D regs[r1]; + } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr =3D regs[r2]; + } else { + tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + taddr =3D tci_uint64(regs[r3], regs[r2]); } - taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp64 =3D qemu_ld_ub; @@ -933,39 +928,58 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, default: g_assert_not_reached(); } - tci_write_reg(regs, t0, tmp64); if (TCG_TARGET_REG_BITS =3D=3D 32) { - tci_write_reg(regs, t1, tmp64 >> 32); + tci_write_reg64(regs, r1, r0, tmp64); + } else { + regs[r0] =3D tmp64; } break; + case INDEX_op_qemu_st_i32: - t0 =3D tci_read_rval(regs, &tb_ptr); - taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i32(&tb_ptr); + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr =3D regs[r1]; + } else { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr =3D tci_uint64(regs[r2], regs[r1]); + } + tmp32 =3D regs[r0]; switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: - qemu_st_b(t0); + qemu_st_b(tmp32); break; case MO_LEUW: - qemu_st_lew(t0); + qemu_st_lew(tmp32); break; case MO_LEUL: - qemu_st_lel(t0); + qemu_st_lel(tmp32); break; case MO_BEUW: - qemu_st_bew(t0); + qemu_st_bew(tmp32); break; case MO_BEUL: - qemu_st_bel(t0); + qemu_st_bel(tmp32); break; default: g_assert_not_reached(); } break; + case INDEX_op_qemu_st_i64: - tmp64 =3D tci_read_r64(regs, &tb_ptr); - taddr =3D tci_read_ulong(regs, &tb_ptr); - oi =3D tci_read_i32(&tb_ptr); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr =3D regs[r1]; + tmp64 =3D regs[r0]; + } else { + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr =3D regs[r2]; + } else { + tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + taddr =3D tci_uint64(regs[r3], regs[r2]); + } + tmp64 =3D tci_uint64(regs[r1], regs[r0]); + } switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: qemu_st_b(tmp64); @@ -992,6 +1006,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, g_assert_not_reached(); } break; + case INDEX_op_mb: /* Ensure ordering for all kinds */ smp_mb(); --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hRHyPEsiO/sbh2eomZAl+YTq7kTrdOg7LphtzyHDt9Q=; b=yzc4UVefamkKi+ZzdmNdqpcq9Psk5AuBGV8oyF07TIyPmTBuvP0E9uft+IAI5BZ/Ni ZST3rOYH4qikDDiRmyNvny4Er8BDDapl6qHoSyGtAgwtBmqS164YJ8hJV1YGXZnShceN 5l6naum+iOLLA8KERYnYQ1/N4RiStVZCbNPgUV0GV/NCoN87tQVHhmT8qPzVNWdTZHGY DHX4m3LeJJVz1V4c5AQHNL7MX+IWCmbQ8QexlhFufO4qnjYnAbXDmf3jwKaoorURNHZA LPUrxsD+gewVuQf1294oSYb3T33MELH4Glzerc8Wg+dTNJXv+xw9Qr0naWqqv5uAnA6n H8jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hRHyPEsiO/sbh2eomZAl+YTq7kTrdOg7LphtzyHDt9Q=; b=Qk7zehllhru8acLUZdVj08BxEMooUZr4k3JIqnRm9BT4l4tcWpuMRwwaOlJ723Rw78 OfFOfR8M/ri0o46Ga4R1oCOJz7losOuxqGRx32ihBLryKWVsnuxBLsx6YlQnD1O5bsXR IEg86a6UOihq0PhUjPbGqWTaseqEtlL1dMluDJtTgH2zCVSJxEom7z8REUmHMYxlDVZs 3Bdx36rLWtg1XQtHvxCvo5AutxV7M7bDo7oDfpQs+391oIyF/g68DZUA6V/ttPIseZvy 1+2ZdMmsFzYU5OwqFW4UoirZRqjKkEmZg4ONhDHLIefCt+brI0j8yhJbJs867EIeu/ri enLA== X-Gm-Message-State: AOAM531d7skKxWpBiB99z1K+7XBJ6QZkYwWndWc9+IB3r6StIaFe5yzq xGh4VReqfXb+NaeVaCoYImmF1JdVb/pkb4Tg X-Google-Smtp-Source: ABdhPJxWwxUNln4P6Zyqx3HMvW9kmEsjj1MaheX7lbDbYHf0MlA7vuDA/Lrwz+s4bcV9hZyCBhDBcA== X-Received: by 2002:a62:3503:0:b029:1aa:6f15:b9fe with SMTP id c3-20020a6235030000b02901aa6f15b9femr5740085pfa.65.1612403216691; Wed, 03 Feb 2021 17:46:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 59/93] tcg/tci: Hoist op_size checking into tci_args_* Date: Wed, 3 Feb 2021 15:44:35 -1000 Message-Id: <20210204014509.882821-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This performs the size check while reading the arguments, which means that we don't have to arrange for it to be done after the operation. Which tidies all of the branches. Signed-off-by: Richard Henderson --- tcg/tci.c | 87 ++++++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 73 insertions(+), 14 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index a1846825ea..3dc89ed829 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -24,7 +24,7 @@ #if defined(CONFIG_DEBUG_TCG) # define tci_assert(cond) assert(cond) #else -# define tci_assert(cond) ((void)0) +# define tci_assert(cond) ((void)(cond)) #endif =20 #include "qemu-common.h" @@ -135,146 +135,217 @@ static tcg_target_ulong tci_read_label(const uint8_= t **tb_ptr) * s =3D signed ldst offset */ =20 +static void check_size(const uint8_t *start, const uint8_t **tb_ptr) +{ + const uint8_t *old_code_ptr =3D start - 2; + uint8_t op_size =3D old_code_ptr[1]; + tci_assert(*tb_ptr =3D=3D old_code_ptr + op_size); +} + static void tci_args_l(const uint8_t **tb_ptr, void **l0) { + const uint8_t *start =3D *tb_ptr; + *l0 =3D (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_ri(const uint8_t **tb_ptr, TCGReg *r0, tcg_target_ulong *i1) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *i1 =3D tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 static void tci_args_rI(const uint8_t **tb_ptr, TCGReg *r0, tcg_target_ulong *i1) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *i1 =3D tci_read_i(tb_ptr); + + check_size(start, tb_ptr); } #endif =20 static void tci_args_rrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *m2 =3D tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrs(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, int32_t *i2) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *i2 =3D tci_read_s32(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *c2 =3D tci_read_b(tb_ptr); *l3 =3D (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *c3 =3D tci_read_b(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx = *m3) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *m3 =3D tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, uint8_t *i3, uint8_t *i4) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *i3 =3D tci_read_b(tb_ptr); *i4 =3D tci_read_b(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); *m4 =3D tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); *c4 =3D tci_read_b(tb_ptr); *l5 =3D (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); *r4 =3D tci_read_r(tb_ptr); *c5 =3D tci_read_b(tb_ptr); + + check_size(start, tb_ptr); } =20 static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { + const uint8_t *start =3D *tb_ptr; + *r0 =3D tci_read_r(tb_ptr); *r1 =3D tci_read_r(tb_ptr); *r2 =3D tci_read_r(tb_ptr); *r3 =3D tci_read_r(tb_ptr); *r4 =3D tci_read_r(tb_ptr); *r5 =3D tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } #endif =20 @@ -440,10 +511,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, =20 for (;;) { TCGOpcode opc =3D tb_ptr[0]; -#if defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG) - uint8_t op_size =3D tb_ptr[1]; - const uint8_t *old_code_ptr =3D tb_ptr; -#endif TCGReg r0, r1, r2, r3; tcg_target_ulong t1; TCGCond condition; @@ -493,7 +560,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; case INDEX_op_br: tci_args_l(&tb_ptr, &ptr); - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D ptr; continue; case INDEX_op_setcond_i32: @@ -646,9 +712,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_brcond_i32: tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); if (tci_compare32(regs[r0], regs[r1], condition)) { - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D ptr; - continue; } break; #if TCG_TARGET_REG_BITS =3D=3D 32 @@ -669,7 +733,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, T1 =3D tci_uint64(regs[r1], regs[r0]); T2 =3D tci_uint64(regs[r3], regs[r2]); if (tci_compare64(T1, T2, condition)) { - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D ptr; continue; } @@ -803,9 +866,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, case INDEX_op_brcond_i64: tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); if (tci_compare64(regs[r0], regs[r1], condition)) { - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D ptr; - continue; } break; case INDEX_op_ext32s_i64: @@ -834,9 +895,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, =20 case INDEX_op_goto_tb: tci_args_l(&tb_ptr, &ptr); - tci_assert(tb_ptr =3D=3D old_code_ptr + op_size); tb_ptr =3D *(void **)ptr; - continue; + break; =20 case INDEX_op_qemu_ld_i32: if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { @@ -1014,6 +1074,5 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, default: g_assert_not_reached(); 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7AU7AuzkprD1DzoX758oP/Mpq/Dm/wXzaoKexxvkWBk=; b=er7akT1nwqQmv9gBfhPzwA2Qz2X1af1C8ChA5dliWRYIEb3EgF+tE7QwpDr2MVV+xa atdQ01XyDp6MtdOvorUfVt1WStdfs71x2SrNabmdyl9UN75aJOKFPMVm9r/3162lfPCB 8IvS/ciutaD0bJIoXyKo8CW2tA+egMUv7vNDxp2snaxYPwprn2w1ETvt7kAbnALbcSb7 Y9tuOcOG951gi18ZSRdtd8JKqcbU3fag6TepWk4mTNEA6GXLud26C8WFdCRoDul7JTPW lgItfaGAfjtQHLtXw4vJBcSAgyq5dQIyCgZXpkMYFd85HM/vZRg/QMZ5MjYOtxRYajB0 8MSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7AU7AuzkprD1DzoX758oP/Mpq/Dm/wXzaoKexxvkWBk=; b=owCqR0YHJ/yl2RcR4PdPHzNDvd4FpIMjGg0uE8ZckOEH72jsehDEFBljUdPXlJZ/cy 5SV0/T24w7Ot3Hf8kPjyE4nMFCSqHjJJbab43nK9FvcSfcnt+w26fMcHRi2yPUCS1g5X eLYpc6pfSQ6s9KxmcUzAir5pcLrOeTIb9GDpBXOkooPwNpV6C5PTikNodxOWtJDfoYVq Y6OGDX6Am34MTB2xtQB96nQRwkDfXmL4jDJlVBSHhT9EZL002g3sG1ex4FJZPbHkLPDz 63TX4JuxYRvQyz3mXuZ5VMn0+x46xN0lGfbisjnIfRr0+WFvLDgbp9PutYsUu7uETjpF fG0g== X-Gm-Message-State: AOAM532kZ2ceoDxR/4BGPZa+ysDwRJhaxqQQbtP4wdrMLSVwmx1caDIk xtSn97G2oVnvDi0aH97HcF9WmV998gBW8l0I X-Google-Smtp-Source: ABdhPJyV0ydIVe37K6KNXBznSkLnVL2uNtmr8wZnAzKMw2GijOAuW0dbgey18xk9w+QfG7F+64+zFw== X-Received: by 2002:a17:902:9b95:b029:df:d859:42bb with SMTP id y21-20020a1709029b95b02900dfd85942bbmr5952535plp.2.1612403218185; Wed, 03 Feb 2021 17:46:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 60/93] tcg/tci: Remove tci_disas Date: Wed, 3 Feb 2021 15:44:36 -1000 Message-Id: <20210204014509.882821-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This function is unused. It's not even the disassembler, which is print_insn_tci, located in disas/tci.c. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 2 -- tcg/tci/tcg-target.c.inc | 10 ---------- 2 files changed, 12 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 9285c930a2..52af6d8bc5 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -163,8 +163,6 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_STACK_ALIGN 16 =20 -void tci_disas(uint8_t opc); - #define HAVE_TCG_QEMU_TB_EXEC =20 /* We could notice __i386__ or __s390x__ and reduce the barriers depending diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 6c187a25cc..7fb3b04eaf 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -253,16 +253,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, return true; } =20 -#if defined(CONFIG_DEBUG_TCG_INTERPRETER) -/* Show current bytecode. Used by tcg interpreter. */ -void tci_disas(uint8_t opc) -{ - const TCGOpDef *def =3D &tcg_op_defs[opc]; - fprintf(stderr, "TCG %s %u, %u, %u\n", - def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs); -} -#endif - /* Write value (native size). */ static void tcg_out_i(TCGContext *s, tcg_target_ulong v) { --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612406362; cv=none; d=zohomail.com; s=zohoarc; b=nUvq1FNkZT7lViR+Z0Gt2gblSefZ9ffNTgMyvfeZxKONE8iyk02DNzcN6p3l7/ugGtojXwTus97fgqUnq5KM1yuil368gL6cggJJ6ZmLxc8g4Mf1Oof0gG6A0NPza5XZh1lkT4tOg/T1ez6PyY3khJvzFxrlQJOOgBJ2lbU9k+s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612406362; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iToOwgtlkbg5FQ3YOPz2xSqBMcKCFQNo9DwZ3Jeszk0=; b=gyqm5vcWPy13LoQ4ujl3kqeGrdOcA4MZPn7W8Y9H8x5/XcdDvhxbvsHzIzXumo+f280ToKu77oc59E5gRLr13CnyKDzcG201nAx5gfN6E1mzwCauYjVK2oOSIS46wnKXaWhETn5NPdVVPPX+P9FVTaAVuT4sMbBpvEOSGRci1fs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612406362597731.4323257549502; Wed, 3 Feb 2021 18:39:22 -0800 (PST) Received: from localhost ([::1]:33084 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7UYD-0007M7-9j for importer@patchew.org; Wed, 03 Feb 2021 21:39:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45160) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Tjb-00062a-Gu for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:47:03 -0500 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:33431) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7TjZ-000467-0f for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:47:03 -0500 Received: by mail-pj1-x102a.google.com with SMTP id lw17so4251806pjb.0 for ; Wed, 03 Feb 2021 17:47:00 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iToOwgtlkbg5FQ3YOPz2xSqBMcKCFQNo9DwZ3Jeszk0=; b=qg/NBCg03rxs2KhJpO61ZGIfk5GMtJYF976nK9Y/5NjYPk4K8QzQTdiL3PxgxtugtN udn6k54wNIi61G6qcW5vB51gT6LLZeZ8c2IQWdWOr/9wnM1nSXlz8/JrHtx6+q/E0ywM W+dm5KOCCHvj1Ic1Iq0DspiOyFS4RVsLu4/hYaL5Tt+b7cKbJEIGNxJQC7DO31GMwy6A QjFqVvk2+ZpB8G8yXEmJJnqdCdiVGKMTSVHKepvfEwfXATtA9+yryFCx9CD7xG5dxdKe 3DK6P/a7djnHom18FwWDrLlrcNKyqZVnvK9tqODYv6l2rBtqkPDwD8o8Iw73l+RprNCe wfUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iToOwgtlkbg5FQ3YOPz2xSqBMcKCFQNo9DwZ3Jeszk0=; b=EOvK4xVrtUTmQ4IGG/A0Q83oagovgO/L95eoniRQg1Cr4G1WhHKevncOG0/aFBlQ6e EjWvuhk7euwltr1oYmSOM9jk+1Chlfuo7k0/ycVLvQwhfZRzyU8fSemFhN+/HIMis+Tf ijNC8nljE+PWPZl9ROYY525JkS41PL4xVnN//lb+c2nTqA37jIO14uzTYe5Cv/71z8iC WF7b+Hq1izZdWUbQltY4Ds14szhlsAiUEL6a9UiQOSkL24WF+s0MXX1SleX+sOqpbYb5 ZUtKr4LBotSDItmPsBQ1pAx354772QR8Cg+vTRXZRE1zOUjJnQnYdIjtMU/1lhVAVg6E NBPw== X-Gm-Message-State: AOAM531wzEOtJuOx1c7eDfjPplOq0FTJE60MUpDmaIAAMCxPITKG1DBD E5dhO+n14GAwD32/AJ5O1401dYTaQMZFc4aw X-Google-Smtp-Source: ABdhPJwV5l5wxQwFCxJcmLdvKB825x+vBj3x55vlcE9STmwgbK/aREs3qIH8YHzq2a0iy0M35qWJYg== X-Received: by 2002:a17:902:ac8b:b029:e0:e42:dc26 with SMTP id h11-20020a170902ac8bb02900e00e42dc26mr5755987plr.44.1612403219553; Wed, 03 Feb 2021 17:46:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 61/93] tcg/tci: Implement the disassembler properly Date: Wed, 3 Feb 2021 15:44:37 -1000 Message-Id: <20210204014509.882821-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Actually print arguments as opposed to simply the opcodes and, uselessly, the argument counts. Reuse all of the helpers developed as part of the interpreter. Signed-off-by: Richard Henderson --- meson.build | 2 +- include/tcg/tcg-opc.h | 2 - disas/tci.c | 61 --------- tcg/tci.c | 283 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 284 insertions(+), 64 deletions(-) delete mode 100644 disas/tci.c diff --git a/meson.build b/meson.build index 2d8b433ff0..475d8a94ea 100644 --- a/meson.build +++ b/meson.build @@ -1901,7 +1901,7 @@ specific_ss.add(when: 'CONFIG_TCG', if_true: files( 'tcg/tcg-op.c', 'tcg/tcg.c', )) -specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('disas/tci.= c', 'tcg/tci.c')) +specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('tcg/tci.c'= )) =20 subdir('backends') subdir('disas') diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 900984c005..bbb0884af8 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -278,10 +278,8 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) #ifdef TCG_TARGET_INTERPRETER /* These opcodes are only for use between the tci generator and interprete= r. */ DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) -#if TCG_TARGET_REG_BITS =3D=3D 64 DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) #endif -#endif =20 #undef TLADDR_ARGS #undef DATA64_ARGS diff --git a/disas/tci.c b/disas/tci.c deleted file mode 100644 index f1d6c6b469..0000000000 --- a/disas/tci.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Tiny Code Interpreter for QEMU - disassembler - * - * Copyright (c) 2011 Stefan Weil - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "qemu/osdep.h" -#include "qemu-common.h" -#include "disas/dis-asm.h" -#include "tcg/tcg.h" - -/* Disassemble TCI bytecode. */ -int print_insn_tci(bfd_vma addr, disassemble_info *info) -{ - int length; - uint8_t byte; - int status; - TCGOpcode op; - - status =3D info->read_memory_func(addr, &byte, 1, info); - if (status !=3D 0) { - info->memory_error_func(status, addr, info); - return -1; - } - op =3D byte; - - addr++; - status =3D info->read_memory_func(addr, &byte, 1, info); - if (status !=3D 0) { - info->memory_error_func(status, addr, info); - return -1; - } - length =3D byte; - - if (op >=3D tcg_op_defs_max) { - info->fprintf_func(info->stream, "illegal opcode %d", op); - } else { - const TCGOpDef *def =3D &tcg_op_defs[op]; - int nb_oargs =3D def->nb_oargs; - int nb_iargs =3D def->nb_iargs; - int nb_cargs =3D def->nb_cargs; - /* TODO: Improve disassembler output. */ - info->fprintf_func(info->stream, "%s\to=3D%d i=3D%d c=3D%d", - def->name, nb_oargs, nb_iargs, nb_cargs); - } - - return length; -} diff --git a/tcg/tci.c b/tcg/tci.c index 3dc89ed829..6843e837ae 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -1076,3 +1076,286 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArch= State *env, } } } + +/* + * Disassembler that matches the interpreter + */ + +static const char *str_r(TCGReg r) +{ + static const char regs[TCG_TARGET_NB_REGS][4] =3D { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "env", "sp" + }; + + QEMU_BUILD_BUG_ON(TCG_AREG0 !=3D TCG_REG_R14); + QEMU_BUILD_BUG_ON(TCG_REG_CALL_STACK !=3D TCG_REG_R15); + + assert((unsigned)r < TCG_TARGET_NB_REGS); + return regs[r]; +} + +static const char *str_c(TCGCond c) +{ + static const char cond[16][8] =3D { + [TCG_COND_NEVER] =3D "never", + [TCG_COND_ALWAYS] =3D "always", + [TCG_COND_EQ] =3D "eq", + [TCG_COND_NE] =3D "ne", + [TCG_COND_LT] =3D "lt", + [TCG_COND_GE] =3D "ge", + [TCG_COND_LE] =3D "le", + [TCG_COND_GT] =3D "gt", + [TCG_COND_LTU] =3D "ltu", + [TCG_COND_GEU] =3D "geu", + [TCG_COND_LEU] =3D "leu", + [TCG_COND_GTU] =3D "gtu", + }; + + assert((unsigned)c < ARRAY_SIZE(cond)); + assert(cond[c][0] !=3D 0); + return cond[c]; +} + +/* Disassemble TCI bytecode. */ +int print_insn_tci(bfd_vma addr, disassemble_info *info) +{ + uint8_t buf[256]; + int length, status; + const TCGOpDef *def; + const char *op_name; + TCGOpcode op; + TCGReg r0, r1, r2, r3; +#if TCG_TARGET_REG_BITS =3D=3D 32 + TCGReg r4, r5; +#endif + tcg_target_ulong i1; + int32_t s2; + TCGCond c; + TCGMemOpIdx oi; + uint8_t pos, len; + void *ptr; + const uint8_t *tb_ptr; + + status =3D info->read_memory_func(addr, buf, 2, info); + if (status !=3D 0) { + info->memory_error_func(status, addr, info); + return -1; + } + op =3D buf[0]; + length =3D buf[1]; + + if (length < 2) { + info->fprintf_func(info->stream, "invalid length %d", length); + return 1; + } + + status =3D info->read_memory_func(addr + 2, buf + 2, length - 2, info); + if (status !=3D 0) { + info->memory_error_func(status, addr + 2, info); + return -1; + } + + def =3D &tcg_op_defs[op]; + op_name =3D def->name; + tb_ptr =3D buf + 2; + + switch (op) { + case INDEX_op_br: + case INDEX_op_call: + case INDEX_op_exit_tb: + case INDEX_op_goto_tb: + tci_args_l(&tb_ptr, &ptr); + info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); + break; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%p", + op_name, str_r(r0), str_r(r1), str_c(c), ptr); + break; + + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &c); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", + op_name, str_r(r0), str_r(r1), str_r(r2), str_c= (c)); + break; + + case INDEX_op_tci_movi_i32: + tci_args_ri(&tb_ptr, &r0, &i1); + info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "", + op_name, str_r(r0), i1); + break; + +#if TCG_TARGET_REG_BITS =3D=3D 64 + case INDEX_op_tci_movi_i64: + tci_args_rI(&tb_ptr, &r0, &i1); + info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "", + op_name, str_r(r0), i1); + break; +#endif + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i32: + case INDEX_op_ld_i64: + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i32: + case INDEX_op_st_i64: + tci_args_rrs(&tb_ptr, &r0, &r1, &s2); + info->fprintf_func(info->stream, "%-12s %s,%s,%d", + op_name, str_r(r0), str_r(r1), s2); + break; + + case INDEX_op_mov_i32: + case INDEX_op_mov_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + case INDEX_op_not_i32: + case INDEX_op_not_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + tci_args_rr(&tb_ptr, &r0, &r1); + info->fprintf_func(info->stream, "%-12s %s,%s", + op_name, str_r(r0), str_r(r1)); + break; + + case INDEX_op_add_i32: + case INDEX_op_add_i64: + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + case INDEX_op_and_i32: + case INDEX_op_and_i64: + case INDEX_op_or_i32: + case INDEX_op_or_i64: + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + case INDEX_op_div_i32: + case INDEX_op_div_i64: + case INDEX_op_rem_i32: + case INDEX_op_rem_i64: + case INDEX_op_divu_i32: + case INDEX_op_divu_i64: + case INDEX_op_remu_i32: + case INDEX_op_remu_i64: + case INDEX_op_shl_i32: + case INDEX_op_shl_i64: + case INDEX_op_shr_i32: + case INDEX_op_shr_i64: + case INDEX_op_sar_i32: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + info->fprintf_func(info->stream, "%-12s %s,%s,%s", + op_name, str_r(r0), str_r(r1), str_r(r2)); + break; + + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%d,%d", + op_name, str_r(r0), str_r(r1), str_r(r2), pos, = len); + break; + +#if TCG_TARGET_REG_BITS =3D=3D 32 + case INDEX_op_setcond2_i32: + tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &c); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", + op_name, str_r(r0), str_r(r1), str_r(r2), + str_r(r3), str_r(r4), str_c(c)); + break; + + case INDEX_op_brcond2_i32: + tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &c, &ptr); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%p", + op_name, str_r(r0), str_r(r1), + str_r(r2), str_r(r3), str_c(c), ptr); + break; + + case INDEX_op_mulu2_i32: + tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", + op_name, str_r(r0), str_r(r1), + str_r(r2), str_r(r3)); + break; + + case INDEX_op_add2_i32: + case INDEX_op_sub2_i32: + tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", + op_name, str_r(r0), str_r(r1), str_r(r2), + str_r(r3), str_r(r4), str_r(r5)); + break; +#endif + + case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_st_i64: + len =3D DIV_ROUND_UP(64, TCG_TARGET_REG_BITS); + goto do_qemu_ldst; + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_st_i32: + len =3D 1; + do_qemu_ldst: + len +=3D DIV_ROUND_UP(TARGET_LONG_BITS, TCG_TARGET_REG_BITS); + switch (len) { + case 2: + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + info->fprintf_func(info->stream, "%-12s %s,%s,%x", + op_name, str_r(r0), str_r(r1), oi); + break; + case 3: + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%x", + op_name, str_r(r0), str_r(r1), str_r(r2), o= i); + break; + case 4: + tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%x", + op_name, str_r(r0), str_r(r1), + str_r(r2), str_r(r3), oi); + break; + default: + g_assert_not_reached(); + } + break; + + default: + info->fprintf_func(info->stream, "illegal opcode %d", op); + break; + } + + return length; +} --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:47:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=grvYIe5/Gge3fEjJZ+Bf2tCoajmCwbWXSaPGURmUcZ8=; b=q7iaJi3gYygMtaRXPTvu6GtaXPRfBgl+/el9DE2WQKzTmRVCfrnTvJO3gqEL2fcYt+ Uq/2EDWAPkhVEAW1TO3PuFit54Vo0r6Zvt4zHKZXrw/h1ifd1xIwXSoskarGpTId1cul iPOlCKJGzLCuFbBh91NKOt3fZ9o1CiNAGvfmn3GEjAp63nwnWKlswS4mBY4FwUWN5Hit QKp/NMr4fApV3TiD1Sn+FVD/jHA1pYJuPk8NmPLZnLluTobKwqUh8XD8ofDJokJXxkMv eiazsUMOa7kq8ofTVic/zyxUyGwTTAXjiQh4SX8zM1muipEAghrXczvy99rbLwul1MA/ hgBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=grvYIe5/Gge3fEjJZ+Bf2tCoajmCwbWXSaPGURmUcZ8=; b=JmpBzFrCVzUNmMXrNYQXMKtAAB7t34c9j50RbEVYUJ398PLyFiZnAeywkYLca5R/vo sXOyqZprDwiX6C/A0vB/92grwJnwGxn+GP5lFlNehSoC68/1HB+iz8BlgoLV0Nf/DWA2 40KTIykNWyLOpk9O9G4tJBRrba0knMGoU8zeZV+ktUxFUPbpzTj6v31ssMOYRGOqf1Iz gFFw1kKsSQLtLUVMXnXbIxFIul+2xj/NDn/cfNhGyw0OSuY7KzTTmiIq3zWNRNPRRxTp q8NO1zIxumUf9JW3gWFw8FzF42ncNXzNgleJ1E/RoHtcmUc3qybqVvuyj0U5IWBwqZXb HOaQ== X-Gm-Message-State: AOAM531aq+HgA2iXvEeZ0i7lA/WtI+148ElhcmM+kudP7mZ54W3nbMwk gEor8OBVvDWt4GO7BNL14I5sp08HW9j3S7Rl X-Google-Smtp-Source: ABdhPJwRoV6evq/q7ybkFDo1rXH7E8mRNdyg4Deaankfvg1tEZVj1syaJ5dOJjRIi0KArYv+VeOc1Q== X-Received: by 2002:a17:903:1c3:b029:de:6b19:e72e with SMTP id e3-20020a17090301c3b02900de6b19e72emr5791099plh.63.1612403221043; Wed, 03 Feb 2021 17:47:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 62/93] tcg: Build ffi data structures for helpers Date: Wed, 3 Feb 2021 15:44:38 -1000 Message-Id: <20210204014509.882821-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We will shortly use libffi for tci, as that is the only portable way of calling arbitrary functions. Signed-off-by: Richard Henderson --- meson.build | 9 +- include/exec/helper-ffi.h | 115 +++++++++++++++++++++++++ include/exec/helper-tcg.h | 24 ++++-- target/hppa/helper.h | 2 + target/i386/ops_sse_header.h | 6 ++ target/m68k/helper.h | 1 + target/ppc/helper.h | 3 + tcg/tcg.c | 20 +++++ tests/docker/dockerfiles/fedora.docker | 1 + 9 files changed, 172 insertions(+), 9 deletions(-) create mode 100644 include/exec/helper-ffi.h diff --git a/meson.build b/meson.build index 475d8a94ea..fc08f15a00 100644 --- a/meson.build +++ b/meson.build @@ -1901,7 +1901,14 @@ specific_ss.add(when: 'CONFIG_TCG', if_true: files( 'tcg/tcg-op.c', 'tcg/tcg.c', )) -specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('tcg/tci.c'= )) + +if get_option('tcg_interpreter') + libffi =3D dependency('libffi', version: '>=3D3.0', + static: enable_static, method: 'pkg-config', + required: true) + specific_ss.add(libffi) + specific_ss.add(files('tcg/tci.c')) +endif =20 subdir('backends') subdir('disas') diff --git a/include/exec/helper-ffi.h b/include/exec/helper-ffi.h new file mode 100644 index 0000000000..3af1065af3 --- /dev/null +++ b/include/exec/helper-ffi.h @@ -0,0 +1,115 @@ +/* + * Helper file for declaring TCG helper functions. + * This one defines data structures private to tcg.c. + */ + +#ifndef HELPER_FFI_H +#define HELPER_FFI_H 1 + +#include "exec/helper-head.h" + +#define dh_ffitype_i32 &ffi_type_uint32 +#define dh_ffitype_s32 &ffi_type_sint32 +#define dh_ffitype_int &ffi_type_sint +#define dh_ffitype_i64 &ffi_type_uint64 +#define dh_ffitype_s64 &ffi_type_sint64 +#define dh_ffitype_f16 &ffi_type_uint32 +#define dh_ffitype_f32 &ffi_type_uint32 +#define dh_ffitype_f64 &ffi_type_uint64 +#ifdef TARGET_LONG_BITS +# if TARGET_LONG_BITS =3D=3D 32 +# define dh_ffitype_tl &ffi_type_uint32 +# else +# define dh_ffitype_tl &ffi_type_uint64 +# endif +#endif +#define dh_ffitype_ptr &ffi_type_pointer +#define dh_ffitype_cptr &ffi_type_pointer +#define dh_ffitype_void &ffi_type_void +#define dh_ffitype_noreturn &ffi_type_void +#define dh_ffitype_env &ffi_type_pointer +#define dh_ffitype(t) glue(dh_ffitype_, t) + +#define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 0, \ + }; + +#define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \ + static ffi_type *glue(cif_args_,NAME)[1] =3D { dh_ffitype(t1) }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 1, = \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \ + static ffi_type *glue(cif_args_,NAME)[2] =3D { \ + dh_ffitype(t1), dh_ffitype(t2) \ + }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 2, \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \ + static ffi_type *glue(cif_args_,NAME)[3] =3D { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3) \ + }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 3, \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \ + static ffi_type *glue(cif_args_,NAME)[4] =3D { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), dh_ffitype(t4) \ + }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 4, = \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \ + static ffi_type *glue(cif_args_,NAME)[5] =3D { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), \ + dh_ffitype(t4), dh_ffitype(t5) \ + }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 5, = \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \ + static ffi_type *glue(cif_args_,NAME)[6] =3D { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), \ + dh_ffitype(t4), dh_ffitype(t5), dh_ffitype(t6) \ + }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 6, = \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \ + static ffi_type *glue(cif_args_,NAME)[7] =3D { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), \ + dh_ffitype(t4), dh_ffitype(t5), dh_ffitype(t6), dh_ffitype(t7) \ + }; \ + static ffi_cif glue(cif_,NAME) =3D { \ + .rtype =3D dh_ffitype(ret), .nargs =3D 7, = \ + .arg_types =3D glue(cif_args_,NAME), \ + }; + +#include "helper.h" +#include "trace/generated-helpers.h" +#include "tcg-runtime.h" + +#undef DEF_HELPER_FLAGS_0 +#undef DEF_HELPER_FLAGS_1 +#undef DEF_HELPER_FLAGS_2 +#undef DEF_HELPER_FLAGS_3 +#undef DEF_HELPER_FLAGS_4 +#undef DEF_HELPER_FLAGS_5 +#undef DEF_HELPER_FLAGS_6 +#undef DEF_HELPER_FLAGS_7 + +#endif /* HELPER_FFI_H */ diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h index 27870509a2..a71b848576 100644 --- a/include/exec/helper-tcg.h +++ b/include/exec/helper-tcg.h @@ -10,50 +10,57 @@ to get all the macros expanded first. */ #define str(s) #s =20 +#ifdef CONFIG_TCG_INTERPRETER +# define DO_CIF(NAME) .cif =3D &cif_##NAME, +#else +# define DO_CIF(NAME) +#endif + #define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) }, =20 #define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) }, =20 #define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) }, =20 #define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) }, =20 #define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) }, =20 #define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | dh_sizemask(t5, 5) }, =20 #define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) }, =20 #define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), .flags =3D FLAGS, \ + { .func =3D HELPER(NAME), DO_CIF(NAME) .name =3D str(NAME), \ + .flags =3D FLAGS | dh_callflag(ret), \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) | dh_sizemask(t7, 7) }, @@ -64,6 +71,7 @@ #include "plugin-helpers.h" =20 #undef str +#undef DO_CIF #undef DEF_HELPER_FLAGS_0 #undef DEF_HELPER_FLAGS_1 #undef DEF_HELPER_FLAGS_2 diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 2d483aab58..35c612f09d 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -1,9 +1,11 @@ #if TARGET_REGISTER_BITS =3D=3D 64 # define dh_alias_tr i64 # define dh_is_64bit_tr 1 +# define dh_ffitype_tr dh_ffitype_i64 #else # define dh_alias_tr i32 # define dh_is_64bit_tr 0 +# define dh_ffitype_tr dh_ffitype_i32 #endif #define dh_ctype_tr target_ureg #define dh_is_signed_tr 0 diff --git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h index 6c0c849347..cae50f77eb 100644 --- a/target/i386/ops_sse_header.h +++ b/target/i386/ops_sse_header.h @@ -27,13 +27,19 @@ #define dh_alias_Reg ptr #define dh_alias_ZMMReg ptr #define dh_alias_MMXReg ptr + #define dh_ctype_Reg Reg * #define dh_ctype_ZMMReg ZMMReg * #define dh_ctype_MMXReg MMXReg * + #define dh_is_signed_Reg dh_is_signed_ptr #define dh_is_signed_ZMMReg dh_is_signed_ptr #define dh_is_signed_MMXReg dh_is_signed_ptr =20 +#define dh_ffitype_Reg dh_ffitype_ptr +#define dh_ffitype_ZMMReg dh_ffitype_ptr +#define dh_ffitype_MMXReg dh_ffitype_ptr + DEF_HELPER_3(glue(psrlw, SUFFIX), void, env, Reg, Reg) DEF_HELPER_3(glue(psraw, SUFFIX), void, env, Reg, Reg) DEF_HELPER_3(glue(psllw, SUFFIX), void, env, Reg, Reg) diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 77808497a9..672c99d5de 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -18,6 +18,7 @@ DEF_HELPER_4(cas2l_parallel, void, env, i32, i32, i32) #define dh_alias_fp ptr #define dh_ctype_fp FPReg * #define dh_is_signed_fp dh_is_signed_ptr +#define dh_ffitype_fp dh_ffitype_ptr =20 DEF_HELPER_3(exts32, void, env, fp, s32) DEF_HELPER_3(extf32, void, env, fp, f32) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 6a4dccf70c..bbd4700064 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -108,10 +108,12 @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i= 64) #define dh_alias_avr ptr #define dh_ctype_avr ppc_avr_t * #define dh_is_signed_avr dh_is_signed_ptr +#define dh_ffitype_avr dh_ffitype_ptr =20 #define dh_alias_vsr ptr #define dh_ctype_vsr ppc_vsr_t * #define dh_is_signed_vsr dh_is_signed_ptr +#define dh_ffitype_vsr dh_ffitype_ptr =20 DEF_HELPER_3(vavgub, void, avr, avr, avr) DEF_HELPER_3(vavguh, void, avr, avr, avr) @@ -696,6 +698,7 @@ DEF_HELPER_3(store_601_batu, void, env, i32, tl) #define dh_alias_fprp ptr #define dh_ctype_fprp ppc_fprp_t * #define dh_is_signed_fprp dh_is_signed_ptr +#define dh_ffitype_fprp dh_ffitype_ptr =20 DEF_HELPER_4(dadd, void, env, fprp, fprp, fprp) DEF_HELPER_4(daddq, void, env, fprp, fprp, fprp) diff --git a/tcg/tcg.c b/tcg/tcg.c index 2991112829..6382112215 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -66,6 +66,10 @@ #include "exec/log.h" #include "sysemu/sysemu.h" =20 +#ifdef CONFIG_TCG_INTERPRETER +#include +#endif + /* Forward declarations for functions declared in tcg-target.c.inc and used here. */ static void tcg_target_init(TCGContext *s); @@ -1082,6 +1086,9 @@ void tcg_pool_reset(TCGContext *s) =20 typedef struct TCGHelperInfo { void *func; +#ifdef CONFIG_TCG_INTERPRETER + ffi_cif *cif; +#endif const char *name; unsigned flags; unsigned sizemask; @@ -1089,6 +1096,10 @@ typedef struct TCGHelperInfo { =20 #include "exec/helper-proto.h" =20 +#ifdef CONFIG_TCG_INTERPRETER +#include "exec/helper-ffi.h" +#endif + static const TCGHelperInfo all_helpers[] =3D { #include "exec/helper-tcg.h" }; @@ -1136,6 +1147,15 @@ void tcg_context_init(TCGContext *s) (gpointer)&all_helpers[i]); } =20 +#ifdef CONFIG_TCG_INTERPRETER + for (i =3D 0; i < ARRAY_SIZE(all_helpers); ++i) { + ffi_cif *cif =3D all_helpers[i].cif; + ffi_status ok =3D ffi_prep_cif(cif, FFI_DEFAULT_ABI, cif->nargs, + cif->rtype, cif->arg_types); + tcg_debug_assert(ok =3D=3D FFI_OK); + } +#endif + tcg_target_init(s); process_op_defs(s); =20 diff --git a/tests/docker/dockerfiles/fedora.docker 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.47.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:47:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vBr7vhN4PGwbH1KaQVzNdMhftTOwE1A/EapiaKgFiUE=; b=CO9J7dL7EWXW/OBV9snxEJgzSf/GIUx2LVvCTNBerfGYfq7AKev9x8K1/6J2U25fBo 7EvCGMBEl+BY+5RjjH2tie4ct03kphd74zCxe2O9nb3pZGSRMpoBiw0tetfIaJzVH2Gb pmJMRhGOTMrUbKjBabGjwojOjRGpNsTCxGrSfb5u/YN5BhQA1yuf75uWX9HpN4IM58gk mniAHjszYrvxKMFxR1Kg4tMaQAAHqY+VXIVmx8aC9vSx3trAMW57kWS4aRJZ+lu6s5bH YHAHC05gtZR7KF96YLyGsu64mdxtqwKOOFqITGpMPwruqRtFPzxM0qiuhysZLai4dIrA ancg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vBr7vhN4PGwbH1KaQVzNdMhftTOwE1A/EapiaKgFiUE=; b=tyXDHK3uqNDrNFhM4Z9PD5IBFlUsEkKQxDS3M9FGdpJActmeExuvPwNfLbd0fxuOh1 XKpBdD7me5PI+qMSuOVGkrE4Qa+2Ajdn7CNyoN+Doqnvy1HmK7HQyo45iPs/6RGcrryJ PvYHmHsRWPWP2FZhzu6CsapVsWLUxj7AEzZ6yxW3lrO3Pw67uI/9zkAvnQxQNCtx+lBu EVBCUb9rZ01p7fFLmJRFQxbzEkPA1QZKN4/FK8gKYtWZ1RPS+fiBBOUVAY1G2oJo11X4 aWcyqyiGppBX5ryAGG9GgKlHqE6mA/tnHBWdum8PH4P7ugVSoZ0Q7XOVJZfqiUbbMpvk Yjmg== X-Gm-Message-State: AOAM532bBq/gAVp9HbWiEt+e1kAPfzhojx5uIPYagoWr1oajiAmHyDTO zwQO4h3c2aiNT9svj2oRMSrGhHEjAdGrJ2lh X-Google-Smtp-Source: ABdhPJyZT1stBXcdfiogQkhz8tMwDgk+vUOOs7WC2hIP8UPuWM4Ml0LHXgxQkAjkBys4M0pJ7a3Fgw== X-Received: by 2002:a17:902:be0e:b029:e0:5b2:659e with SMTP id r14-20020a170902be0eb02900e005b2659emr5693999pls.74.1612403222675; Wed, 03 Feb 2021 17:47:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 63/93] tcg/tci: Use ffi for calls Date: Wed, 3 Feb 2021 15:44:39 -1000 Message-Id: <20210204014509.882821-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This requires adjusting where arguments are stored. Place them on the stack at left-aligned positions. Adjust the stack frame to be at entirely positive offsets. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 + tcg/tci/tcg-target.h | 2 +- tcg/tcg.c | 72 ++++++++++++--------- tcg/tci.c | 131 ++++++++++++++++++++++----------------- tcg/tci/tcg-target.c.inc | 50 +++++++-------- 5 files changed, 143 insertions(+), 113 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 0f0695e90d..e5573a9877 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -53,6 +53,7 @@ #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) =20 #define CPU_TEMP_BUF_NLONGS 128 +#define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) =20 /* Default target word size to pointer size. */ #ifndef TCG_TARGET_REG_BITS diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 52af6d8bc5..4df10e2e83 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -161,7 +161,7 @@ typedef enum { =20 /* Used for function call generation. */ #define TCG_TARGET_CALL_STACK_OFFSET 0 -#define TCG_TARGET_STACK_ALIGN 16 +#define TCG_TARGET_STACK_ALIGN 8 =20 #define HAVE_TCG_QEMU_TB_EXEC =20 diff --git a/tcg/tcg.c b/tcg/tcg.c index 6382112215..92aec0d238 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -208,6 +208,18 @@ static size_t tree_size; static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT]; static TCGRegSet tcg_target_call_clobber_regs; =20 +typedef struct TCGHelperInfo { + void *func; +#ifdef CONFIG_TCG_INTERPRETER + ffi_cif *cif; +#endif + const char *name; + unsigned flags; + unsigned sizemask; +} TCGHelperInfo; + +static GHashTable *helper_table; + #if TCG_TARGET_INSN_UNIT_SIZE =3D=3D 1 static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t= v) { @@ -1084,16 +1096,6 @@ void tcg_pool_reset(TCGContext *s) s->pool_current =3D NULL; } =20 -typedef struct TCGHelperInfo { - void *func; -#ifdef CONFIG_TCG_INTERPRETER - ffi_cif *cif; -#endif - const char *name; - unsigned flags; - unsigned sizemask; -} TCGHelperInfo; - #include "exec/helper-proto.h" =20 #ifdef CONFIG_TCG_INTERPRETER @@ -1103,7 +1105,6 @@ typedef struct TCGHelperInfo { static const TCGHelperInfo all_helpers[] =3D { #include "exec/helper-tcg.h" }; -static GHashTable *helper_table; =20 static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)= ]; static void process_op_defs(TCGContext *s); @@ -2081,25 +2082,38 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int na= rgs, TCGTemp **args) =20 real_args =3D 0; for (i =3D 0; i < nargs; i++) { - int is_64bit =3D sizemask & (1 << (i+1)*2); - if (TCG_TARGET_REG_BITS < 64 && is_64bit) { -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - /* some targets want aligned 64 bit args */ - if (real_args & 1) { - op->args[pi++] =3D TCG_CALL_DUMMY_ARG; - real_args++; - } + bool is_64bit =3D sizemask & (1 << (i+1)*2); + bool want_align =3D false; + +#if defined(CONFIG_TCG_INTERPRETER) + /* + * Align all arguments, so that they land in predictable places + * for passing off to ffi_call. + */ + want_align =3D true; +#elif defined(TCG_TARGET_CALL_ALIGN_ARGS) + /* Some targets want aligned 64 bit args */ + want_align =3D is_64bit; #endif - /* If stack grows up, then we will be placing successive - arguments at lower addresses, which means we need to - reverse the order compared to how we would normally - treat either big or little-endian. For those arguments - that will wind up in registers, this still works for - HPPA (the only current STACK_GROWSUP target) since the - argument registers are *also* allocated in decreasing - order. If another such target is added, this logic may - have to get more complicated to differentiate between - stack arguments and register arguments. */ + + if (TCG_TARGET_REG_BITS < 64 && want_align && (real_args & 1)) { + op->args[pi++] =3D TCG_CALL_DUMMY_ARG; + real_args++; + } + + if (TCG_TARGET_REG_BITS < 64 && is_64bit) { + /* + * If stack grows up, then we will be placing successive + * arguments at lower addresses, which means we need to + * reverse the order compared to how we would normally + * treat either big or little-endian. For those arguments + * that will wind up in registers, this still works for + * HPPA (the only current STACK_GROWSUP target) since the + * argument registers are *also* allocated in decreasing + * order. If another such target is added, this logic may + * have to get more complicated to differentiate between + * stack arguments and register arguments. + */ #if defined(HOST_WORDS_BIGENDIAN) !=3D defined(TCG_TARGET_STACK_GROWSUP) op->args[pi++] =3D temp_arg(args[i] + 1); op->args[pi++] =3D temp_arg(args[i]); diff --git a/tcg/tci.c b/tcg/tci.c index 6843e837ae..d27db9f720 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -18,6 +18,13 @@ */ =20 #include "qemu/osdep.h" +#include "qemu-common.h" +#include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */ +#include "exec/cpu_ldst.h" +#include "tcg/tcg-op.h" +#include "qemu/compiler.h" +#include + =20 /* Enable TCI assertions only when debugging TCG (and without NDEBUG defin= ed). * Without assertions, the interpreter runs much faster. */ @@ -27,36 +34,8 @@ # define tci_assert(cond) ((void)(cond)) #endif =20 -#include "qemu-common.h" -#include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */ -#include "exec/cpu_ldst.h" -#include "tcg/tcg-op.h" -#include "qemu/compiler.h" - -#if MAX_OPC_PARAM_IARGS !=3D 6 -# error Fix needed, number of supported input arguments changed! -#endif -#if TCG_TARGET_REG_BITS =3D=3D 32 -typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong); -#else -typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong); -#endif - __thread uintptr_t tci_tb_ptr; =20 -static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg = index) -{ - tci_assert(index < TCG_TARGET_NB_REGS); - return regs[index]; -} - static void tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) { @@ -131,6 +110,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **= tb_ptr) * i =3D immediate (uint32_t) * I =3D immediate (tcg_target_ulong) * m =3D immediate (TCGMemOpIdx) + * n =3D immediate (call return length) * r =3D register * s =3D signed ldst offset */ @@ -151,6 +131,16 @@ static void tci_args_l(const uint8_t **tb_ptr, void **= l0) check_size(start, tb_ptr); } =20 +static void tci_args_nl(const uint8_t **tb_ptr, uint8_t *n0, void **l1) +{ + const uint8_t *start =3D *tb_ptr; + + *n0 =3D tci_read_b(tb_ptr); + *l1 =3D (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); +} + static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { @@ -491,6 +481,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCG= Cond condition) # define CASE_64(x) #endif =20 + /* Interpret pseudo code in tb. */ /* * Disable CFI checks. @@ -502,11 +493,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, { const uint8_t *tb_ptr =3D v_tb_ptr; tcg_target_ulong regs[TCG_TARGET_NB_REGS]; - long tcg_temps[CPU_TEMP_BUF_NLONGS]; - uintptr_t sp_value =3D (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); + uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) + / sizeof(uint64_t)]; + void *call_slots[TCG_STATIC_CALL_ARGS_SIZE / sizeof(uint64_t)]; =20 regs[TCG_AREG0] =3D (tcg_target_ulong)env; - regs[TCG_REG_CALL_STACK] =3D sp_value; + regs[TCG_REG_CALL_STACK] =3D (uintptr_t)stack; + call_slots[0] =3D NULL; tci_assert(tb_ptr); =20 for (;;) { @@ -531,33 +524,53 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 switch (opc) { case INDEX_op_call: - tci_args_l(&tb_ptr, &ptr); + /* + * We are passed a pointer to the TCGHelperInfo, which contains + * the function pointer followed by the ffi_cif pointer. + */ + tci_args_nl(&tb_ptr, &len, &ptr); + + /* Helper functions may need to access the "return address" */ tci_tb_ptr =3D (uintptr_t)tb_ptr; -#if TCG_TARGET_REG_BITS =3D=3D 32 - tmp64 =3D ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0= ), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5), - tci_read_reg(regs, TCG_REG_R6), - tci_read_reg(regs, TCG_REG_R7), - tci_read_reg(regs, TCG_REG_R8), - tci_read_reg(regs, TCG_REG_R9), - tci_read_reg(regs, TCG_REG_R10), - tci_read_reg(regs, TCG_REG_R11)= ); - tci_write_reg(regs, TCG_REG_R0, tmp64); - tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); -#else - tmp64 =3D ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0= ), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5)); - tci_write_reg(regs, TCG_REG_R0, tmp64); -#endif + + /* + * Set up the ffi_avalue array once, delayed until now + * because many TB's do not make any calls. In tcg_gen_callN, + * we arranged for every real argument to be "left-aligned" + * in each 64-bit slot. + */ + if (call_slots[0] =3D=3D NULL) { + for (int i =3D 0; i < ARRAY_SIZE(call_slots); ++i) { + call_slots[i] =3D &stack[i]; + } + } + + /* + * Call the helper function. Any result winds up + * "left-aligned" in the stack[0] slot. + */ + { + void **pptr =3D ptr; + ffi_call(pptr[1], pptr[0], stack, call_slots); + } + switch (len) { + case 0: /* void */ + break; + case 1: /* uint32_t */ + regs[TCG_REG_R0] =3D *(uint32_t *)stack; + break; + case 2: /* uint64_t */ + if (TCG_TARGET_REG_BITS =3D=3D 32) { + tci_write_reg64(regs, TCG_REG_R1, TCG_REG_R0, stack[0]= ); + } else { + regs[TCG_REG_R0] =3D stack[0]; + } + break; + default: + g_assert_not_reached(); + } break; + case INDEX_op_br: tci_args_l(&tb_ptr, &ptr); tb_ptr =3D ptr; @@ -1162,13 +1175,17 @@ int print_insn_tci(bfd_vma addr, disassemble_info *= info) =20 switch (op) { case INDEX_op_br: - case INDEX_op_call: case INDEX_op_exit_tb: case INDEX_op_goto_tb: tci_args_l(&tb_ptr, &ptr); info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); break; =20 + case INDEX_op_call: + tci_args_nl(&tb_ptr, &len, &ptr); + info->fprintf_func(info->stream, "%-12s %d,%p", op_name, len, ptr= ); + break; + case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 7fb3b04eaf..8d75482546 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -192,23 +192,8 @@ static const int tcg_target_reg_alloc_order[] =3D { # error Fix needed, number of supported input arguments changed! #endif =20 -static const int tcg_target_call_iarg_regs[] =3D { - TCG_REG_R0, - TCG_REG_R1, - TCG_REG_R2, - TCG_REG_R3, - TCG_REG_R4, - TCG_REG_R5, -#if TCG_TARGET_REG_BITS =3D=3D 32 - /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */ - TCG_REG_R6, - TCG_REG_R7, - TCG_REG_R8, - TCG_REG_R9, - TCG_REG_R10, - TCG_REG_R11, -#endif -}; +/* No call arguments via registers. All will be stored on the "stack". */ +static const int tcg_target_call_iarg_regs[] =3D { }; =20 static const int tcg_target_call_oarg_regs[] =3D { TCG_REG_R0, @@ -292,8 +277,9 @@ static void tci_out_label(TCGContext *s, TCGLabel *labe= l) static void stack_bounds_check(TCGReg base, target_long offset) { if (base =3D=3D TCG_REG_CALL_STACK) { - tcg_debug_assert(offset < 0); - tcg_debug_assert(offset >=3D -(CPU_TEMP_BUF_NLONGS * sizeof(long))= ); + tcg_debug_assert(offset >=3D 0); + tcg_debug_assert(offset < (TCG_STATIC_CALL_ARGS_SIZE + + TCG_STATIC_FRAME_SIZE)); } } =20 @@ -360,11 +346,25 @@ static void tcg_out_movi(TCGContext *s, TCGType type, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 -static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { uint8_t *old_code_ptr =3D s->code_ptr; + const TCGHelperInfo *info; + uint8_t which; + + info =3D g_hash_table_lookup(helper_table, (gpointer)arg); + if (info->cif->rtype =3D=3D &ffi_type_void) { + which =3D 0; + } else if (info->cif->rtype->size =3D=3D 4) { + which =3D 1; + } else { + tcg_debug_assert(info->cif->rtype->size =3D=3D 8); + which =3D 2; + } tcg_out_op_t(s, INDEX_op_call); - tcg_out_i(s, (uintptr_t)arg); + tcg_out8(s, which); + tcg_out_i(s, (uintptr_t)info); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 @@ -629,11 +629,9 @@ static void tcg_target_init(TCGContext *s) s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); =20 - /* We use negative offsets from "sp" so that we can distinguish - stores that might pretend to be call arguments. */ - tcg_set_frame(s, TCG_REG_CALL_STACK, - -CPU_TEMP_BUF_NLONGS * sizeof(long), - CPU_TEMP_BUF_NLONGS * sizeof(long)); + /* The call arguments come first, followed by the temp storage. */ + tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, + TCG_STATIC_FRAME_SIZE); } =20 /* Generate global QEMU prologue and epilogue code. */ --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612405859; cv=none; d=zohomail.com; s=zohoarc; b=TtPCNaWeRh6KmtH3paeCyKk2EeHX9TiwtBMBpAvehYlZpc1mYD4T9LSunKSYSZq1zNovCQDGDBMhUkIyLdf0JjvfG56MsB0qObIP4WsgTMLHtNMSnHysiCyeaR+hNh4oOkhSYMKxaK7TtPk2GyFx3ogtATPMbo7zxDIbyDr0w+Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612405859; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YQBNB7jLXwaZJSYBL0BvoU6n3wPE6zwxayv+Hpeg13U=; b=YZKspj7qdwhya6+iVZsu1iQNGGYvfxY4/ZPxqA5tV7qRtoZBhhoV8u7h1WtXboJ+dBjGa/KyOYOsqm9Bva5Mr/2ngtOglR1I42qKMWAqiISxZyUOowrWlhkC9K2mGmpK/bN+7O2a5EpAtNx9qbxKMU6TE62bsBK9P6YT2idhG04= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612405859355594.2073865601476; Wed, 3 Feb 2021 18:30:59 -0800 (PST) Received: from localhost ([::1]:38306 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7UQ3-0005x0-8v for importer@patchew.org; Wed, 03 Feb 2021 21:30:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45262) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Tjh-0006Cl-F2 for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:47:12 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:36058) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tjd-00048r-DR for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:47:09 -0500 Received: by mail-pl1-x634.google.com with SMTP id e9so898042plh.3 for ; Wed, 03 Feb 2021 17:47:04 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.47.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:47:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YQBNB7jLXwaZJSYBL0BvoU6n3wPE6zwxayv+Hpeg13U=; b=uXpTlARhhPLGPSnuVDZU8sjiGNGdW5EXwqXne5QuPo2m5mq4baN+1dAVNZeyRC8ldl gwbfi/jhdkTsxiIPppl9gDL591Gr4BIOD9+EqsoHuxnHySXDo5KdFZvHU0uExJLDOOOb 0kTOH7fDtAkLYStcfaB3DvPYckJ9b00LKS4J6ytMQzwgH/UvGIv7fUWpTFhLkiPUxKMY hjRu4057ezcvufKh+gs0oId5SI9YErJR4jwz+cE6FLe89mWIpxfkuzXbYGid6rMD4M9/ IDVjLc6m6dwHmurHvrqbM+bqL2D8CfLixz60iMciKyWoAkKXhPRLFcCl8eBqT9BxktqO 972g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YQBNB7jLXwaZJSYBL0BvoU6n3wPE6zwxayv+Hpeg13U=; b=r9o0Jeau9sDbuYZLpO2MwG/c9rpkZkrzKtyvj5E7/FSYfgHk9CK2aT6KeeimjJldxM TKnMTcrEurEvu6UMRqhWiUYe1D72WQgBJcQwIVLvYeswb1BH+mEHcmdJHDfgMv1h1/lU JoS92c0HInOGlHBCcmzOYFl6HQFwHWaQsAg8kQ99eVYbwBzXCzLJxGUCxVF0+vghjI6o Tu/MtjwX8wsiHqbvkCbUTE91MT5lk2yMX9H4Di6ZT7jvjCR4UBxiZOz6E1Nj1GDBlj84 lm7v179hbbV2e5gE8iZxnnyfTsBLX7cy0HR5qp245HPCQMsbNGwu1+gsf725YQg41XCT Lqag== X-Gm-Message-State: AOAM531mn4Ew2O+MpbdOq8qZcBwqcUEYFC3QT7DX1sGVA7SXCrEcD9qG 8EcIDjtcppytcVy3eNePNJo1OggtymkNELrs X-Google-Smtp-Source: ABdhPJySFzIeHZqIVVrCLVi8EQ/TnsUOn3bhbG73BG+r3sO5lcmFTCa572TXbrSMgTzvIdDBky0yBw== X-Received: by 2002:a17:902:70c3:b029:de:af88:f17e with SMTP id l3-20020a17090270c3b02900deaf88f17emr5777031plt.3.1612403224131; Wed, 03 Feb 2021 17:47:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 64/93] tcg/tci: Improve tcg_target_call_clobber_regs Date: Wed, 3 Feb 2021 15:44:40 -1000 Message-Id: <20210204014509.882821-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The current setting is much too pessimistic. Indicating only the one or two registers that are actually assigned after a call should avoid unnecessary movement between the register array and the stack array. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8d75482546..4dae09deda 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -623,8 +623,14 @@ static void tcg_target_init(TCGContext *s) tcg_target_available_regs[TCG_TYPE_I32] =3D BIT(TCG_TARGET_NB_REGS) - = 1; /* Registers available for 64 bit operations. */ tcg_target_available_regs[TCG_TYPE_I64] =3D BIT(TCG_TARGET_NB_REGS) - = 1; - /* TODO: Which registers should be set here? */ - tcg_target_call_clobber_regs =3D BIT(TCG_TARGET_NB_REGS) - 1; + /* + * The interpreter "registers" are in the local stack frame and + * cannot be clobbered by the called helper functions. However, + * the interpreter assumes a 64-bit return value and assigns to + * the return value registers. + */ + tcg_target_call_clobber_regs =3D + MAKE_64BIT_MASK(TCG_REG_R0, 64 / TCG_TARGET_REG_BITS); =20 s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612406218; cv=none; d=zohomail.com; s=zohoarc; b=hjCov85iy4P7NtF3H504iAh+T0/+52jl9spselimkYcJHfEEMylgEomWrOzW+dbSPkGdC6oeyWFoc5cCUTDigbJppNzboEV1wD4SoRowhkaTKha3Zgs7vMK/Kixy3aO0Reraz+Wx7VOuG74sfOh+tG8Lhbxp+cNzTf3noxx2fvY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612406218; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LAWykP8xawhD0n2LEjnvxt6U+It9ZnMCGaTxxtC6jn0=; b=EUBi5UpklPgvCyZ3ItLfpNjtIUCWtVPooh7xnUSrPerQRELBpbK97lh5hX4TYV3fq+WNiuDgLZwx3mEUPTa6KmdoVsdJ5ucihvlFOlJW7SmlYkfocvYHveN4mR+t9TEgXFb8a1SbfjctFfMT6b9nYCykGIGmKRtC7Fc1D0CuxzY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612406218582477.0024571124227; Wed, 3 Feb 2021 18:36:58 -0800 (PST) Received: from localhost ([::1]:57124 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7UVt-0005XT-Ai for importer@patchew.org; Wed, 03 Feb 2021 21:36:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45280) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Tjj-0006D9-AB for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:47:12 -0500 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:39193) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tje-00049J-V4 for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:47:11 -0500 Received: by mail-pj1-x102a.google.com with SMTP id d2so820872pjs.4 for ; Wed, 03 Feb 2021 17:47:06 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.47.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:47:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LAWykP8xawhD0n2LEjnvxt6U+It9ZnMCGaTxxtC6jn0=; b=YGX1wPtCD2Ap8FPJxD1u9xl6GRm8bV1wPkAN/ScfYkHiHzeWPipbnbmzIPZjU6h+lB BwEs0JgZnBAbBOgvdkgEl/hCczUb4ouloF2Cmpfy4bxjhnkendyEnLrcvVI6OoHtQ55a uvm9Kwead7s8U+2JJLbZ+kYBSN1ViIFLHuB70KYYU9a1RuYkm4EXzTVoC+RtAGiGE7/J pRVNh2EcPEpsF4maDwVY50OYBwaHYVkHFQjPp+eS+5vllbYZn47l26TjIFA/hXPFhJX5 fKeYFZUkZMtApMOab3kn6/14XbZArQrFqfMd5qfDArbd70FMWqllCF59g1oynGiBQ1jV tDeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LAWykP8xawhD0n2LEjnvxt6U+It9ZnMCGaTxxtC6jn0=; b=YH6DJlzYpnIAr77q3A/UHAJ/lhAEeCrFSD2SxOU1mQBQz6/dxgnlKXfY8sIZvu60zX ZbEnjkrZyAb4e24uEwMhp0ULK2h/5P4uxgX/RNPn/gknM6hOXl1LCwWZaHa0A94vIaUE s2eoUkBQUUh2RqjFfuo+cPNDxc8hJMAcXkRPAB4UUwwWhibn4Lj0CUbSwf4nDeXc+WIs XbXJ6F6fPm2Q7n7nU2LmrpjO8gYgcZGRgdaYC/DmCOjYck7hortXoXyS8gnESgGG3/X+ MdigynzvOKXQFNYOFySzbjNS8iGYUv2E9VRLharZfP0SDhmfk+SlL1Bhhcf6DKhQVqXB IQ1w== X-Gm-Message-State: AOAM533gjeQBkPYfH70E3hYUOXqc+jP1+UpFfMKQvjmz2DmG2knA0nmC 2hT8wfDDeXZ3wUp0bY0wCYGL+KyqGDje2N5G X-Google-Smtp-Source: ABdhPJwB9ct52ywpGtTNuKyVMpYwBcIrz7raZURjJonyAJ2urPxdZehjLNrx0gIlLc/+bZ2LBx5QQA== X-Received: by 2002:a17:902:70c6:b029:df:d62a:8c69 with SMTP id l6-20020a17090270c6b02900dfd62a8c69mr5597285plt.20.1612403225526; Wed, 03 Feb 2021 17:47:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 65/93] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Date: Wed, 3 Feb 2021 15:44:41 -1000 Message-Id: <20210204014509.882821-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" As the only call-clobbered regs for TCI, these should receive the least priority. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 4dae09deda..53edc50a3b 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -170,8 +170,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcod= e op) } =20 static const int tcg_target_reg_alloc_order[] =3D { - TCG_REG_R0, - TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, TCG_REG_R4, @@ -186,6 +184,8 @@ static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, + TCG_REG_R1, + TCG_REG_R0, }; =20 #if MAX_OPC_PARAM_IARGS !=3D 6 --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612406024; cv=none; d=zohomail.com; s=zohoarc; b=hIm51tIac3ZBFWC9xwLx1ynP5bwv5CgsE8/+opm3gXkrX2wzMcMm2coagRZb5d0x886UmcPRZleX6Pq5Vl73EKZLItYlmRY1WAukWA9JJ8sFubZm0dMdVLdmG22G7bBpJztv/MRkIhgV+XEfzmObCg9EwJt2znJGmNwbEeIm67U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612406024; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=akuogNqTsRbdFKyineyOU7+0wNNNt+eZ2/k7lVk1LqY=; b=fhVxU7oYQqWQ74KsMsqOAmAZGGLHgKEiiGuV0Ncc8BbXrTDdWUyeZ4ZC/koGJFPms0unPsx4OdA4raw92JEWJxJLrOZJz5G5rItbUHOxWF94BzPlWpvIYMGeGBy8Pdddb6BH0KVjrLKz9nQlzM1MQMVO3+SfqdNJ6L2qDcEyLDY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612406024482952.4756049700305; Wed, 3 Feb 2021 18:33:44 -0800 (PST) Received: from localhost ([::1]:46710 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7USl-0001Am-Dr for importer@patchew.org; Wed, 03 Feb 2021 21:33:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45316) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Tjm-0006DL-33 for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:47:16 -0500 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:43298) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tjg-00049e-Ic for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:47:13 -0500 Received: by mail-pg1-x532.google.com with SMTP id n10so1017256pgl.10 for ; Wed, 03 Feb 2021 17:47:08 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.47.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:47:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=akuogNqTsRbdFKyineyOU7+0wNNNt+eZ2/k7lVk1LqY=; b=sIm0cUPbbgveHZSAfIhqybZBzqYbIspHWJnBiFvzKaPhf7QiH1NFM6mT3byN2HvB9K fua2Pc3InkRp2epkA30w7Td5kQMoVd0Jd0vhqhO8R3X5i+2D/6ZylG9yhAr88LOBYlxv OLaV3mDS5JHQOnpqtPd1k3V3/1xStT6gTFT9lIlD/ELwDoywmnsrv/JvxmHkmg993SbL X2ew7alHZnUFS076Cohm9YFmz45QO7ws9liy2RS4caRzNLTUyKnp862ItobhpMjUtfdD nBKhzewpnsb7nHdzWIAATiMkspxm+PQywKy9vSXpMS1Y2Y4vggeIiiqtRvP/lwvdU1aC fPag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=akuogNqTsRbdFKyineyOU7+0wNNNt+eZ2/k7lVk1LqY=; b=PlrOkUUn48iMdj9iAHskrS66A/AyLfZlKkA83W6y5QZaTAoKcEv7DzcnpyzESNhiIC IQESTRo5hQ9PGfR8LL7U2gESwbDkii36oUzshqA+K0cd/RMSuYZzsmv+gzqX6YoyZXfs earQHASURNgim3ZiXGmbcx6eCjJWe3HwkzhPlIc7WuaVtsiWummTPOgF4L+eF2yyFZID LwHlhn0z4UHFwng9621wL0vfiDHNt4o3p9iAq8mdP7Baf+y/biXODJfF33LuzH0lsLgJ Jqv/9/5nJbopsFp8q8dYqon21oJ+0rNYn7AJgx0/sqgGwHr6IpofqiKHfMY8MYdlCNqy KgRQ== X-Gm-Message-State: AOAM531WPt3MRPORW+3DI+RzXWTuZdSfB2OYmYkYlPxZdkhnSWqPIgkt y8F+UFysw1YX9H8EzhFjpxehRKq4PAMhFvZU X-Google-Smtp-Source: ABdhPJxJJSq9W8skWn67Cr1yv0/DVWMPwwDr3v/O/WBxTGdkRDcB7KJrrOFwoF679TYa3FfjoVS1hQ== X-Received: by 2002:aa7:80ca:0:b029:1c1:b636:ecc2 with SMTP id a10-20020aa780ca0000b02901c1b636ecc2mr5841449pfn.20.1612403227117; Wed, 03 Feb 2021 17:47:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 66/93] tcg/tci: Push opcode emit into each case Date: Wed, 3 Feb 2021 15:44:42 -1000 Message-Id: <20210204014509.882821-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We're about to split out bytecode output into helpers, but we can't do that one at a time if tcg_out_op_t is being done outside of the switch. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 53edc50a3b..050d514853 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -385,40 +385,48 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, { uint8_t *old_code_ptr =3D s->code_ptr; =20 - tcg_out_op_t(s, opc); - switch (opc) { case INDEX_op_exit_tb: + tcg_out_op_t(s, opc); tcg_out_i(s, args[0]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_goto_tb: tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); /* indirect jump method. */ + tcg_out_op_t(s, opc); tcg_out_i(s, (uintptr_t)(s->tb_jmp_target_addr + args[0])); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; set_jmp_reset_offset(s, args[0]); break; =20 case INDEX_op_br: + tcg_out_op_t(s, opc); tci_out_label(s, arg_label(args[0])); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(setcond) + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out8(s, args[3]); /* condition */ + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */ + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); tcg_out_r(s, args[4]); tcg_out8(s, args[5]); /* condition */ + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; #endif =20 @@ -436,10 +444,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, CASE_64(st32) CASE_64(st) stack_bounds_check(args[1], args[2]); + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_debug_assert(args[2] =3D=3D (int32_t)args[2]); tcg_out32(s, args[2]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(add) @@ -462,12 +472,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ + tcg_out_op_t(s, opc); { TCGArg pos =3D args[3], len =3D args[4]; TCGArg max =3D opc =3D=3D INDEX_op_deposit_i32 ? 32 : 64; @@ -481,13 +494,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, tcg_out8(s, pos); tcg_out8(s, len); } + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(brcond) + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out8(s, args[2]); /* condition */ tci_out_label(s, arg_label(args[3])); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ @@ -503,48 +519,59 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); tcg_out_r(s, args[4]); tcg_out_r(s, args[5]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; case INDEX_op_brcond2_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); tcg_out8(s, args[4]); /* condition */ tci_out_label(s, arg_label(args[5])); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; case INDEX_op_mulu2_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; #endif =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_st_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, *args++); tcg_out_r(s, *args++); if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { tcg_out_r(s, *args++); } tcg_out32(s, *args++); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: + tcg_out_op_t(s, opc); tcg_out_r(s, *args++); if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_out_r(s, *args++); @@ -554,9 +581,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, tcg_out_r(s, *args++); } tcg_out32(s, *args++); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_mb: + tcg_out_op_t(s, opc); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ @@ -565,7 +595,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, default: tcg_abort(); } - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg= 1, --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 84 +++++++++++++++++++--------------------- 1 file changed, 39 insertions(+), 45 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 050d514853..707f801099 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -283,32 +283,38 @@ static void stack_bounds_check(TCGReg base, target_lo= ng offset) } } =20 -static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg= 1, - intptr_t arg2) +static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, intptr_t i2) { uint8_t *old_code_ptr =3D s->code_ptr; =20 - stack_bounds_check(arg1, arg2); - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_op_t(s, INDEX_op_ld_i32); - tcg_out_r(s, ret); - tcg_out_r(s, arg1); - tcg_out32(s, arg2); - } else { - tcg_debug_assert(type =3D=3D TCG_TYPE_I64); -#if TCG_TARGET_REG_BITS =3D=3D 64 - tcg_out_op_t(s, INDEX_op_ld_i64); - tcg_out_r(s, ret); - tcg_out_r(s, arg1); - tcg_debug_assert(arg2 =3D=3D (int32_t)arg2); - tcg_out32(s, arg2); -#else - TODO(); -#endif - } + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_debug_assert(i2 =3D=3D (int32_t)i2); + tcg_out32(s, i2); + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, + intptr_t offset) +{ + stack_bounds_check(base, offset); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_rrs(s, INDEX_op_ld_i32, val, base, offset); + break; +#if TCG_TARGET_REG_BITS =3D=3D 64 + case TCG_TYPE_I64: + tcg_out_op_rrs(s, INDEX_op_ld_i64, val, base, offset); + break; +#endif + default: + g_assert_not_reached(); + } +} + static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { uint8_t *old_code_ptr =3D s->code_ptr; @@ -444,12 +450,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, CASE_64(st32) CASE_64(st) stack_bounds_check(args[1], args[2]); - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_debug_assert(args[2] =3D=3D (int32_t)args[2]); - tcg_out32(s, args[2]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrs(s, opc, args[0], args[1], args[2]); break; =20 CASE_32_64(add) @@ -597,29 +598,22 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, } } =20 -static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg= 1, - intptr_t arg2) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, + intptr_t offset) { - uint8_t *old_code_ptr =3D s->code_ptr; - - stack_bounds_check(arg1, arg2); - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_op_t(s, INDEX_op_st_i32); - tcg_out_r(s, arg); - tcg_out_r(s, arg1); - tcg_out32(s, arg2); - } else { - tcg_debug_assert(type =3D=3D TCG_TYPE_I64); + stack_bounds_check(base, offset); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_rrs(s, INDEX_op_st_i32, val, base, offset); + break; #if TCG_TARGET_REG_BITS =3D=3D 64 - tcg_out_op_t(s, INDEX_op_st_i64); - tcg_out_r(s, arg); - tcg_out_r(s, arg1); - tcg_out32(s, arg2); -#else - TODO(); + case TCG_TYPE_I64: + tcg_out_op_rrs(s, INDEX_op_st_i64, val, base, offset); + break; #endif + default: + g_assert_not_reached(); } - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 707f801099..1e3f2c4049 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -283,6 +283,16 @@ static void stack_bounds_check(TCGReg base, target_lon= g offset) } } =20 +static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tci_out_label(s, l0); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -408,9 +418,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, break; =20 case INDEX_op_br: - tcg_out_op_t(s, opc); - tci_out_label(s, arg_label(args[0])); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_l(s, opc, arg_label(args[0])); break; =20 CASE_32_64(setcond) --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612406630; cv=none; d=zohomail.com; s=zohoarc; b=YUrMaibH2OvF5He8Syw91ADFi4EasYPO0HCFvS0+/WJOPpM7+m2XE4WVXu56Lwh8vW98MmQWNH7P7Uat1Ro50Ljv0oti5EXQYA1OOqoCh4OaV9xFAillrXzoqQjkSNhGz7aPyOOQ+BQf/Vkvl2JNPwsNtSbb+m6CWvb/XEVpEUc= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 1e3f2c4049..cb0cbbb8da 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -293,6 +293,16 @@ static void tcg_out_op_l(TCGContext *s, TCGOpcode op, = TCGLabel *l0) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_i(s, (uintptr_t)p0); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -403,17 +413,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, =20 switch (opc) { case INDEX_op_exit_tb: - tcg_out_op_t(s, opc); - tcg_out_i(s, args[0]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_p(s, opc, (void *)args[0]); break; =20 case INDEX_op_goto_tb: tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D 0); /* indirect jump method. */ - tcg_out_op_t(s, opc); - tcg_out_i(s, (uintptr_t)(s->tb_jmp_target_addr + args[0])); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_p(s, opc, s->tb_jmp_target_addr + args[0]); set_jmp_reset_offset(s, args[0]); break; =20 --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.47.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:47:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Kpfe6JZmwXM15Cw7O9Ulgnnkm0DVoqv1s4+DGCwKajc=; b=sqtsnxO4M+CXXiGZF9Srv4vrSMPBv3HsqqheH0oRaXdnfVSl3kE5Pfq2lole0x75GT 4rk7MXmu/+YVw+cg+ExOK9na01KD8yNXgEz6lF8iaSY34OV3bcjQh2j9GHtvbJ45YlVe TXXNh16V3FRRs8X/zACOvJ2Cs9/eMhqYH0sWq5ggOYFC7KTApY61bqNyJumTyn9iTeYq 1PHLHmm6fkyP+UwY4UD4ppHNUehP4XY2L55lVaombD7oZXvxornX2GxEkgQGSEDakoS1 2ps5HV3npcokVqbqL3CMQY+ABZ7AqWJK8KCoym04GfuTu5XbMj034iAO9LsnLuOv5rTH 9bUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Kpfe6JZmwXM15Cw7O9Ulgnnkm0DVoqv1s4+DGCwKajc=; b=pBkh3rcPmuT7CDTno6amfkTkI0SX7MeMx3ucTGCKrYryj54RlBohfwZcdZ64SrbD7w IybuKe+bsWnlo7wOcR22ws+0Wu8nYZy/uGFLctViRwueij8a3bCUC+8Rd4Kvolm/7eLF E+eEX+JncPfMhiZvZSnk5Xv1ajwt74dUR8C3wgav4iaz3h2wBdozzHp0UQrkRWJtNArm sKoRXtlAMqydYujuy6p45j+XKVnmByukGDxwctRItbLeZustBOXulE4WkttsKnKRWe1B pr5vnGpkv3nhCHkOa3H0KsfOMr03e2vzptz93txn8QRBfReXZA4W58gKY0HYw9zgi8Yc W5eA== X-Gm-Message-State: AOAM531qnn2kBN7T7w7ZL863O0FUDkdedYdb2v4ESAAv+/jzT44mBies wtYP/+frXTHfScvZgNg6FUuRA6wloWZgy/GU X-Google-Smtp-Source: ABdhPJxJ3DgnaEofA7Li2sZIXy6p9T1EXExenKMP6SLUGs1Fgn/KoWlFqheqXnuD7AbIpAzKP3OBKw== X-Received: by 2002:a65:5283:: with SMTP id y3mr6468591pgp.174.1612403233216; Wed, 03 Feb 2021 17:47:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 70/93] tcg/tci: Split out tcg_out_op_rr Date: Wed, 3 Feb 2021 15:44:46 -1000 Message-Id: <20210204014509.882821-71-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" At the same time, validate the type argument in tcg_out_mov. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index cb0cbbb8da..272e3ca70b 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -303,6 +303,17 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, = void *p0) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -337,16 +348,18 @@ static void tcg_out_ld(TCGContext *s, TCGType type, T= CGReg val, TCGReg base, =20 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { - uint8_t *old_code_ptr =3D s->code_ptr; - tcg_debug_assert(ret !=3D arg); -#if TCG_TARGET_REG_BITS =3D=3D 32 - tcg_out_op_t(s, INDEX_op_mov_i32); -#else - tcg_out_op_t(s, INDEX_op_mov_i64); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_rr(s, INDEX_op_mov_i32, ret, arg); + break; +#if TCG_TARGET_REG_BITS =3D=3D 64 + case TCG_TYPE_I64: + tcg_out_op_rr(s, INDEX_op_mov_i64, ret, arg); + break; #endif - tcg_out_r(s, ret); - tcg_out_r(s, arg); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + default: + g_assert_not_reached(); + } return true; } =20 @@ -534,10 +547,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rr(s, opc, args[0], args[1]); break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612406572; cv=none; d=zohomail.com; s=zohoarc; b=m4aSQUzEeHsBe9qcgPZiPX9U4zUS1RSmHiAHX8xgP0ZYFeBSNVFIL29vtBXt8K4eFveJfV5fsYaZk/XPv76qdYxl9ea3wUC2oZ58Co1j27pJB8EK8VpuphuP1uDImJjx9vYLWIBJUC1YVtSrcV9cDveCqD3oQgRt6+tZJwQLYUE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612406572; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RzFAVc3cWW3yr0pGO36GqM64ymG+VJfs9mt8bjfFgIQ=; b=GGU8V/aBdDDIILX3C8XdTHO3VWz1vr6DIewdmmkAqt6M7yHnxdkvrJ23zqhMh920nGEApXWsPstRSjeJ9pY/9EJ5/rMzjaGjRhaO0ADgYWBeivy23zSWyv3ImtlPHju/2HJvMEOd002jLpbsJKOabEHffY7ZjxaQo9/54jXAjZA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161240657238630.794876426565907; Wed, 3 Feb 2021 18:42:52 -0800 (PST) Received: from localhost ([::1]:41586 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7Ubb-0002x3-9T for importer@patchew.org; Wed, 03 Feb 2021 21:42:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45444) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Tjz-0006Hb-Pv for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:47:27 -0500 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:38935) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tjp-0004Cr-WF for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:47:27 -0500 Received: by mail-pf1-x436.google.com with SMTP id e19so1069424pfh.6 for ; Wed, 03 Feb 2021 17:47:15 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 272e3ca70b..546424c2bd 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -314,6 +314,19 @@ static void tcg_out_op_rr(TCGContext *s, TCGOpcode op,= TCGReg r0, TCGReg r1) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -500,11 +513,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrr(s, opc, args[0], args[1], args[2]); break; =20 CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.47.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:47:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QUs6bZlAERttu34ccVgcqABRUHJrBFMHH0LXLYX1oZo=; b=Bqmlt0r3Db+fjsBSQj9sptkfcBIOqh/cN0mdklasHUs4TQY5qbrLLPxL4w8kfka711 DSYs7h2xiNMkMyGU8nVUA4O9RD+hTkQcxmjttEJ/3xs8v9ZFWMh0+zOk6kM7P6c2FyY4 2A+tRBg6FYicFVDlAPHhy5gRbvYdDpD2JmAYyvYNjT+xx8jwMZH2QXKVvQ4WkALS9E78 9lXL6VFFl6Ack1PxlTFsQr92V09MWYWRvBGzYSvPT+kbGGF4aoe8xb0TG9e1qM5c80es Lg9qIwhQqZg1QX1cmvFbNAAeTP71DXmrLz0Q4odpFGR9AFFNGHwcFOCA5R9Ug0YaeybU kukQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QUs6bZlAERttu34ccVgcqABRUHJrBFMHH0LXLYX1oZo=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 546424c2bd..5848779208 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -341,6 +341,20 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out8(s, c3); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, intptr_t offset) { @@ -454,12 +468,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, break; =20 CASE_32_64(setcond) - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out8(s, args[3]); /* condition */ - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrc(s, opc, args[0], args[1], args[2], args[3]); break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 5848779208..8eda159dde 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -355,6 +355,25 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 +static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, + TCGReg r3, TCGReg r4, TCGCond c5) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out_r(s, r4); + tcg_out8(s, c5); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} +#endif + static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, intptr_t offset) { @@ -473,15 +492,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, =20 #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: - /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */ - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - tcg_out_r(s, args[4]); - tcg_out8(s, args[5]); /* condition */ - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrrrc(s, opc, args[0], args[1], args[2], + args[3], args[4], args[5]); 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.47.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:47:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6fN3MzHzuWIrC3R6bdCZxAnV3xyNnPemffGo42IAOp8=; b=xkvRnbgWZeun6WPN2tb/1XcIyq7nwXk6TRMtnW3lWzWUgj7533DS+qXjYyvhmi+t1H iKh7ZYGF+oaBNEkWL9+9QtLSND/SZQAlW35PkpB8XzhyuYAujiaVH2+q7pzoD0iLXJsu x3GD5R6ocb/jbTF5OfWwtm/UoyXmdSObOCRJUOI4ZN3lZOosBEUHU2vTScwQXkpKtGdL 8rICHYrITT7ip7Sm6/MA8sQw+Fz3rj7tkqkK8nQYwlAB+Wi2QLfbH1LaPORcwLNf1FcJ KZPGexkCPk9T6x9KMHjSVzP9SsZ2PJbMx1xzYhoZy7XFQxFxfiKL/dLazfsLZZoEHFtj ScKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6fN3MzHzuWIrC3R6bdCZxAnV3xyNnPemffGo42IAOp8=; b=uLMKslAsZMbkDuLgVgvfWA+PiDU9N6Tiebwf/C3sz1aEK6Dh7CqPoqN3tPDo0yEe44 HG3bjcyxMAD4clMVEZ09GiguQ0FPknn4/ROJscW/bzj9DHOhGb16nMWiuqRQsCFGT+bc KRf1l95V/XFLCxoOlcx6KzR/1oE9z/8INQb92upeyYoLVplLVAKk7H6Whyky2VSWqsfE Pcr5FLnNw+iR4Xu8qKwx9MZOL1NL3g+ZQGgfxzuAbTosxPO7EVRqo3uSIm3M8zxmJgaT 4AOTlc0xXS0YVDrm14d6N/0a7rLBmubx2r/V222fRMG7TZAEUGX1eYiFKXvhCNyut86G Pung== X-Gm-Message-State: AOAM533zI8wYQiLFGnoT1/NO6vLWRQvLMPdlAyiEh8TpSLiOzfHvxE6a Yz0C5/1+tqjEK6VinvsNvQ75yl13w5XTKgd4 X-Google-Smtp-Source: ABdhPJyCVteZ6xwL1danXEXLagKHPeiZx0dPREJSJGlmm2kSQ6pk7PfkZ2/s2I4urJsm3cW8vp1f4Q== X-Received: by 2002:a63:4c0e:: with SMTP id z14mr6535732pga.408.1612403239353; Wed, 03 Feb 2021 17:47:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 74/93] tcg/tci: Split out tcg_out_op_rrrbb Date: Wed, 3 Feb 2021 15:44:50 -1000 Message-Id: <20210204014509.882821-75-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8eda159dde..6c743a8fbd 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -355,6 +355,21 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out8(s, b3); + tcg_out8(s, b4); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + #if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, @@ -538,7 +553,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, break; =20 CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ - tcg_out_op_t(s, opc); { TCGArg pos =3D args[3], len =3D args[4]; TCGArg max =3D opc =3D=3D INDEX_op_deposit_i32 ? 32 : 64; @@ -546,13 +560,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, tcg_debug_assert(pos < max); tcg_debug_assert(pos + len <=3D max); =20 - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out8(s, pos); - tcg_out8(s, len); + tcg_out_op_rrrbb(s, opc, args[0], args[1], args[2], pos, len); } - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 CASE_32_64(brcond) --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612407132; cv=none; d=zohomail.com; s=zohoarc; b=ZwYxHyuB1SdRlUSI+0xPvjZS6e/TJH2J5hxvxzXrCcd3v+qqRj8hGQcS0vF8VYS3vQtfcurwgFvdKCr7Ep/rTPcTrRTfNTIqWOCAzF4bsMkHbSdZMJSyE2vmueoPY138Qq2dC2j6aukFErPRt2G/03MupK6oJdyoT+CKcjlTbDs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612407132; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=p6E9LDuPBslW5lnZ+lbP25axObg1A1JUNAlm8q5oVbA=; b=UO4In2msS7+X3gt5Ye20w97UBbH/arp03jDykiV1tQINZ2n8wWP/Xabd6wz74esaCg+Uv9LbZKq2stvn/nQ2WNO4+0HP2fgIV7PTul8QITb1woN0fltlfwj5G0X1GIkqY6d4keoSe+O4xD4bsH08ZL+LK22D0qiSDkfX/hXD7sI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612407132085491.60933010616577; Wed, 3 Feb 2021 18:52:12 -0800 (PST) Received: from localhost ([::1]:42762 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7Ukc-0007KU-U9 for importer@patchew.org; Wed, 03 Feb 2021 21:52:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45518) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Tk5-0006OL-9V for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:47:33 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:40260) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tjv-0004DZ-5s for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:47:33 -0500 Received: by mail-pj1-x1030.google.com with SMTP id z9so818955pjl.5 for ; Wed, 03 Feb 2021 17:47:21 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 6c743a8fbd..8cc63124d4 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -341,6 +341,20 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrcl(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGCond c2, TCGLabel *l3) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out8(s, c2); + tci_out_label(s, l3); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { @@ -565,12 +579,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, break; =20 CASE_32_64(brcond) - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out8(s, args[2]); /* condition */ - tci_out_label(s, arg_label(args[3])); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrcl(s, opc, args[0], args[1], args[2], arg_label(args[= 3])); break; =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8cc63124d4..f7595fbd65 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -401,6 +401,23 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode= op, =20 old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } + +static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, + TCGReg r3, TCGReg r4, TCGReg r5) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out_r(s, r4); + tcg_out_r(s, r5); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} #endif =20 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, @@ -601,14 +618,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - tcg_out_r(s, args[4]); - tcg_out_r(s, args[5]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2], + args[3], args[4], args[5]); break; case INDEX_op_brcond2_i32: tcg_out_op_t(s, opc); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f7595fbd65..c2bbd85130 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -385,6 +385,20 @@ static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode = op, TCGReg r0, } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 +static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) @@ -632,12 +646,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; case INDEX_op_mulu2_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); break; #endif =20 --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c2bbd85130..fb4aacaca3 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -399,6 +399,23 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrrcl(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, + TCGCond c4, TCGLabel *l5) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out8(s, c4); + tci_out_label(s, l5); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) @@ -636,14 +653,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, args[3], args[4], args[5]); break; case INDEX_op_brcond2_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - tcg_out8(s, args[4]); /* condition */ - tci_out_label(s, arg_label(args[5])); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_rrrrcl(s, opc, args[0], args[1], args[2], + args[3], args[4], arg_label(args[5])); break; case INDEX_op_mulu2_i32: tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612406874; cv=none; d=zohomail.com; s=zohoarc; b=ZTxcKibk1OglMzmeUViHQZOdXikYsWxbL5sJH78SMdYTgufsr10lgsNF40ycU9nM6z/z177QHTLOJz3NC6AXmpeasEcZuY6EAmAg32jHngbi4jDFnTOjiUhRnaTyMkuDXqdHAp78Xe1esCzQBiP/svi5PW/lTYfCyB71J2CF5Y4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612406874; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UtDE8Pm65Grc/U22TwT0AwuyG4b+N8yR6xVz8cz41eM=; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.47.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:47:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UtDE8Pm65Grc/U22TwT0AwuyG4b+N8yR6xVz8cz41eM=; b=iUn2gDuytfVBb9/COd2Ua1DDJO0yMDr97GUDsUrBuRy88g2FtpAqAI9+cNNnvHJgcU /J9TojRnRRgF53QHPmJeSTDA/CVEtP+Vljh1L7cggNDUZ241jznN7Z3m+NPU1tUcBGdk LPJTMV9qbb74bpp4Zjr3GLQ6pFCYvtpQ1y7qv5NvrWJ/9IAL6nRabv3WCR6sMOTC4Ncx Rg/2chIjDUQkhkbI+FJaDv2I5GXJm3qmRYtG8oDn+a8OtUnbqQ1hOlm5XJ9j3M+opm51 jvYKxNR606EVTHk81oBMFfN3jLz5BSk6s4sxni+N+d/zd2zmmdCm7Tm6mYjZ4V0RUAug weVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UtDE8Pm65Grc/U22TwT0AwuyG4b+N8yR6xVz8cz41eM=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 70 ++++++++++++++++++++++++++++++---------- 1 file changed, 53 insertions(+), 17 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index fb4aacaca3..f93772f01f 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -314,6 +314,19 @@ static void tcg_out_op_rr(TCGContext *s, TCGOpcode op,= TCGReg r0, TCGReg r1) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrm(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGArg m2) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out32(s, m2); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2) { @@ -369,6 +382,20 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrm(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGArg m3) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out32(s, m3); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4) { @@ -384,6 +411,21 @@ static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode = op, TCGReg r0, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrrm(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, TCGReg r2, TCGReg r3, TCGArg m4) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out32(s, m4); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + #if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) @@ -663,29 +705,23 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_st_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, *args++); - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); + } else { + tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); } - tcg_out32(s, *args++); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: - tcg_out_op_t(s, opc); - tcg_out_r(s, *args++); - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_r(s, *args++); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); + } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); + } else { + tcg_out_op_rrrrm(s, opc, args[0], args[1], + args[2], args[3], args[4]); } - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out32(s, *args++); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_mb: --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 70 ++++++++++++++++++++++++++++++---------- 1 file changed, 53 insertions(+), 17 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index fb4aacaca3..f93772f01f 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -314,6 +314,19 @@ static void tcg_out_op_rr(TCGContext *s, TCGOpcode op,= TCGReg r0, TCGReg r1) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrm(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGArg m2) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out32(s, m2); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2) { @@ -369,6 +382,20 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrm(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGArg m3) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out32(s, m3); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4) { @@ -384,6 +411,21 @@ static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode = op, TCGReg r0, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_rrrrm(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, TCGReg r2, TCGReg r3, TCGArg m4) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out32(s, m4); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + #if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) @@ -663,29 +705,23 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_st_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, *args++); - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); + } else { + tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); } - tcg_out32(s, *args++); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: - tcg_out_op_t(s, opc); - tcg_out_r(s, *args++); - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_r(s, *args++); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); + } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); + } else { + tcg_out_op_rrrrm(s, opc, args[0], args[1], + args[2], args[3], args[4]); } - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out32(s, *args++); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; break; =20 case INDEX_op_mb: --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f93772f01f..eeafec6d44 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -303,6 +303,15 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, = void *p0) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_v(TCGContext *s, TCGOpcode op) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { uint8_t *old_code_ptr =3D s->code_ptr; @@ -587,8 +596,6 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_= unit *arg) static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { - uint8_t *old_code_ptr =3D s->code_ptr; - switch (opc) { case INDEX_op_exit_tb: tcg_out_op_p(s, opc, (void *)args[0]); @@ -725,8 +732,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, break; =20 case INDEX_op_mb: - tcg_out_op_t(s, opc); - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_v(s, opc); break; =20 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index eeafec6d44..e4a5872b2a 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -312,6 +312,18 @@ static void tcg_out_op_v(TCGContext *s, TCGOpcode op) old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_np(TCGContext *s, TCGOpcode op, + uint8_t n0, const void *p1) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out8(s, n0); + tcg_out_i(s, (uintptr_t)p1); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { uint8_t *old_code_ptr =3D s->code_ptr; @@ -561,7 +573,6 @@ static void tcg_out_movi(TCGContext *s, TCGType type, =20 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { - uint8_t *old_code_ptr =3D s->code_ptr; const TCGHelperInfo *info; uint8_t which; =20 @@ -574,11 +585,8 @@ static void tcg_out_call(TCGContext *s, const tcg_insn= _unit *arg) tcg_debug_assert(info->cif->rtype->size =3D=3D 8); which =3D 2; } - tcg_out_op_t(s, INDEX_op_call); - tcg_out8(s, which); - tcg_out_i(s, (uintptr_t)info); =20 - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_op_np(s, INDEX_op_call, which, info); } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 50 ++++++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 15 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index e4a5872b2a..c2d2bd24d7 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -324,6 +324,31 @@ static void tcg_out_op_np(TCGContext *s, TCGOpcode op, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 +static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t = i1) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out32(s, i1); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + +#if TCG_TARGET_REG_BITS =3D=3D 64 +static void tcg_out_op_rI(TCGContext *s, TCGOpcode op, + TCGReg r0, uint64_t i1) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out64(s, i1); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} +#endif + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { uint8_t *old_code_ptr =3D s->code_ptr; @@ -550,25 +575,20 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, = TCGReg ret, TCGReg arg) } =20 static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg t0, tcg_target_long arg) + TCGReg ret, tcg_target_long arg) { - uint8_t *old_code_ptr =3D s->code_ptr; - uint32_t arg32 =3D arg; - if (type =3D=3D TCG_TYPE_I32 || arg =3D=3D arg32) { - tcg_out_op_t(s, INDEX_op_tci_movi_i32); - tcg_out_r(s, t0); - tcg_out32(s, arg32); - } else { - tcg_debug_assert(type =3D=3D TCG_TYPE_I64); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_ri(s, INDEX_op_tci_movi_i32, ret, arg); + break; #if TCG_TARGET_REG_BITS =3D=3D 64 - tcg_out_op_t(s, INDEX_op_tci_movi_i64); - tcg_out_r(s, t0); - tcg_out64(s, arg); -#else - TODO(); + case TCG_TYPE_I64: + tcg_out_op_rI(s, INDEX_op_tci_movi_i64, ret, arg); + break; #endif + default: + g_assert_not_reached(); } - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612407289; cv=none; d=zohomail.com; s=zohoarc; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id 78sm3588463pfx.127.2021.02.03.17.55.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:55:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=j84CVB2/9NSVvHC05jyj/ExvjNOevKnlsYLw94URCgw=; b=ZuUkcMSw6Kg/ha7AJdzh+FWdLdVkv2o9xXbKFKN0HE8XiQkild0h2Z0tiK+ng4Aar1 a4vxG/5pw0H4ZhQ+qqwq5CzYe5frfwzEc6ajirzRwRc/pYUexUauY1+gC3dfNSk2JRg/ obGic6BWE9i6VvYrzBi2U31coZGZ+EN85yOucLX0OAuSURKCRvf1AsxqDUE85PCJrOJN 4+AsXE2bx+mszqugC5IRKwnobORGkjY0G0QuEDp1FC7rEdRqpvJmWBATGHDSDbdJD6Mj XEjQoxzg0rl3oQ2BE2TnN30K6+enHp1td/Wf/4UdGTOk4zkxNsUPxzTnIAfrPO85fBjj sENg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j84CVB2/9NSVvHC05jyj/ExvjNOevKnlsYLw94URCgw=; b=ELZcMMMMMEuj69lZDtUCh9hk118tFSK4LLCbiFxKtqu4CvVaQt7FdsfXu7IPaf2xCw 0aw3zZOLmVf12gjuL/L+Isw+KergMHoNDCkYSJzHxw1XaH+ZPYzlZqtizvzIkiYevJgx 1LP21UipQXXXUWNhMW3Ae1410aqWE43HAFPHmlV10oQIg952EQbjz3fX8w+FPxKdBvRN LogIxjJ/XYQMDL66NOrIWE1z5yN1mLL3qWPrhZv9y+WtuRlcYdOBmJ5e9mLMPWtJUUgz d0QqfHiu6b0ZHf4XXQfUIEDyRXt3Ls8qG29w4Y3zklNh09ps+oHFpTkDwtCHMvAE/q2q 4sxA== X-Gm-Message-State: AOAM5326nIw1nQLVXHUujvhujOHnBYwmncIVYxAs43PmxcgD57RcaYtR /vPWfv0YDH1UvmXgwtW/9St31m4ZjWQAm0Il X-Google-Smtp-Source: ABdhPJxDBf2xjHm4YXcc4fZdX9fLTSX8aUQTzEEaErQ5GRLBKGexrMDnQ6hFzuOqqtnBINvs3308gQ== X-Received: by 2002:a17:90a:4dc1:: with SMTP id r1mr5967650pjl.12.1612403751853; Wed, 03 Feb 2021 17:55:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 83/93] tcg/tci: Reserve r13 for a temporary Date: Wed, 3 Feb 2021 15:55:48 -1000 Message-Id: <20210204015548.885449-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We're about to adjust the offset range on host memory ops, and the format of branches. Both will require a temporary. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 1 + tcg/tci/tcg-target.c.inc | 1 + 2 files changed, 2 insertions(+) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 4df10e2e83..1558a6e44e 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -155,6 +155,7 @@ typedef enum { TCG_REG_R14, TCG_REG_R15, =20 + TCG_REG_TMP =3D TCG_REG_R13, TCG_AREG0 =3D TCG_REG_R14, TCG_REG_CALL_STACK =3D TCG_REG_R15, } TCGReg; diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c2d2bd24d7..b29e75425d 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -829,6 +829,7 @@ static void tcg_target_init(TCGContext *s) MAKE_64BIT_MASK(TCG_REG_R0, 64 / TCG_TARGET_REG_BITS); =20 s->reserved_regs =3D 0; + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); =20 /* The call arguments come first, followed by the temp storage. */ --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612407076; cv=none; d=zohomail.com; s=zohoarc; b=kWQ9LtznnLBDk3WhMt1FRSSJ+KU6Imxuuh6rCIKYOLITTDYkUPwzVCndc5Rlqch7Gng8LlE5wVYnlEgeyf9Aafw3/PXV+50hFmDPeZ7DDyCM7rH5p0Pd4lHIKrQW+SEwqzD9DSBVN5LLHgRiZ0V9o9JsGF4rxhSxXY8ZuIMlWXc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612407076; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=B9R5rR38+7XqiIyLeWWFMRDiEMmeppRUcow0M2UfyuA=; b=iN8uuECDLumUcNWhCN5BAUcU6zRCBZ4TQGMb36vm89LHH1hpIIAe6euZ6BI86fFSHNjkiNg7tTUESjxh0PGIBqiiYzjq+tMklY89euDaL4heSMnhn9O6E5P3CQfm4KJZmANRNHDU6uHBU/JnxG/Z1ZN9hsRihUTWsFTEB/mFsb8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612407076830727.7574940867373; Wed, 3 Feb 2021 18:51:16 -0800 (PST) Received: from localhost ([::1]:40178 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7Ujj-00066J-L7 for importer@patchew.org; Wed, 03 Feb 2021 21:51:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47010) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7TsU-0000UX-H6 for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:56:14 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:35093) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7TsR-0006rE-TD for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:56:14 -0500 Received: by mail-pf1-x434.google.com with SMTP id w14so1098799pfi.2 for ; Wed, 03 Feb 2021 17:56:11 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id s1sm3218165pjg.17.2021.02.03.17.56.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:56:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B9R5rR38+7XqiIyLeWWFMRDiEMmeppRUcow0M2UfyuA=; b=DKE4Mw8yMXsTj/dAkKPmuGw5wSrpXbp0kui9ioYWRLe0uP6eWNe9j4hv1m2C9H/tCG +3dMbch8lYBt3lg3z7YBZGRWTGxECvwkBH3rD/hEy2CqleviE+fPaWJUWhoQYUk0UBNH 6NC9qwLO7KWXtdB83TXQNNOKoU9hTiDGPxhn/m/zTbggxT3p0J6TjnLNUKywHDHqhDaf iym9MxMBcVsdFHNNdermf6iGxQjrvLFk4XK06dNA6scPTfQTMJdXHnnSdoGm9HHIqYQj BRjhYOss+LOC/QnHn4Esj/LUk2xqv7DZKm3MSB6A0iE832DZkMEnRIyDx70icplDFmkN 5V9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B9R5rR38+7XqiIyLeWWFMRDiEMmeppRUcow0M2UfyuA=; b=CUpMMaheBh8skSa6SBDJXRxUT3hCzF70AbdW8iO3FNWqY8tgr3j9KLZ/jzy5MVjhjs 6e6BWn8JDaSgAtBC16s97dkMnlwnCGaoZvN15ItYi0L68zdCdv4tzBV00jFqsL6XDuNM 9nr6/Ckz0JBRiHo2Z8ufg+wc3Bz+d+n8aWhVndo5bVh3OcP3WPsQSyrZoJnzzM+B4mwm M5aCqpKIyimGqxxxyR7IqT504oqw5TYaJzUjbo6g9lIA0p6DXxCF7bJiik7wHeNCNL/a gvRkUgfB+qKXIc2MpLhI9MToEmiHiU92KczQZ9XEgSWog/SoqwVVhMfVp69+Gf8oWhdL y5Tw== X-Gm-Message-State: AOAM532OsiFwr6XaqV0y4muR28vkzzrbWC2Lzmi6afDTQFDiTHftP5UE OiPSEEGvAcZZZ1AUaU4p3JAkS80eE4JBhFyM X-Google-Smtp-Source: ABdhPJza1/8/To96va1xMuV1h4IdZ09iYLUIlVw1Un3M8HLR/M3fhp0bPQLS3UasozNFBZd213vUKg== X-Received: by 2002:a62:3503:0:b029:1aa:6f15:b9fe with SMTP id c3-20020a6235030000b02901aa6f15b9femr5771737pfa.65.1612403770414; Wed, 03 Feb 2021 17:56:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 84/93] tcg/tci: Emit setcond before brcond Date: Wed, 3 Feb 2021 15:56:07 -1000 Message-Id: <20210204015607.885503-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The encoding planned for tci does not have enough room for brcond2, with 4 registers and a condition as input as well as the label. Resolve the condition into TCG_REG_TMP, and relax brcond to one register plus a label, considering the condition to always be reg !=3D 0. Signed-off-by: Richard Henderson --- tcg/tci.c | 68 ++++++++++------------------------------ tcg/tci/tcg-target.c.inc | 52 +++++++++++------------------- 2 files changed, 35 insertions(+), 85 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index d27db9f720..e7268b13e1 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -141,6 +141,16 @@ static void tci_args_nl(const uint8_t **tb_ptr, uint8_= t *n0, void **l1) check_size(start, tb_ptr); } =20 +static void tci_args_rl(const uint8_t **tb_ptr, TCGReg *r0, void **l1) +{ + const uint8_t *start =3D *tb_ptr; + + *r0 =3D tci_read_r(tb_ptr); + *l1 =3D (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); +} + static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { @@ -212,19 +222,6 @@ static void tci_args_rrs(const uint8_t **tb_ptr, check_size(start, tb_ptr); } =20 -static void tci_args_rrcl(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3) -{ - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *c2 =3D tci_read_b(tb_ptr); - *l3 =3D (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); -} - static void tci_args_rrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { @@ -293,21 +290,6 @@ static void tci_args_rrrr(const uint8_t **tb_ptr, check_size(start, tb_ptr); } =20 -static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, - TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) -{ - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *r3 =3D tci_read_r(tb_ptr); - *c4 =3D tci_read_b(tb_ptr); - *l5 =3D (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); -} - static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) { @@ -723,8 +705,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i32: - tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); - if (tci_compare32(regs[r0], regs[r1], condition)) { + tci_args_rl(&tb_ptr, &r0, &ptr); + if ((uint32_t)regs[r0]) { tb_ptr =3D ptr; } break; @@ -741,15 +723,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, T2 =3D tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; - case INDEX_op_brcond2_i32: - tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr); - T1 =3D tci_uint64(regs[r1], regs[r0]); - T2 =3D tci_uint64(regs[r3], regs[r2]); - if (tci_compare64(T1, T2, condition)) { - tb_ptr =3D ptr; - continue; - } - break; case INDEX_op_mulu2_i32: tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); @@ -877,8 +850,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i64: - tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); - if (tci_compare64(regs[r0], regs[r1], condition)) { + tci_args_rl(&tb_ptr, &r0, &ptr); + if (regs[r0]) { tb_ptr =3D ptr; } break; @@ -1188,9 +1161,9 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr); - info->fprintf_func(info->stream, "%-12s %s,%s,%s,%p", - op_name, str_r(r0), str_r(r1), str_c(c), ptr); + tci_args_rl(&tb_ptr, &r0, &ptr); + info->fprintf_func(info->stream, "%-12s %s,0,ne,%p", + op_name, str_r(r0), ptr); break; =20 case INDEX_op_setcond_i32: @@ -1315,13 +1288,6 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) str_r(r3), str_r(r4), str_c(c)); break; =20 - case INDEX_op_brcond2_i32: - tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &c, &ptr); - info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%p", - op_name, str_r(r0), str_r(r1), - str_r(r2), str_r(r3), str_c(c), ptr); - break; - case INDEX_op_mulu2_i32: tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index b29e75425d..e06d4e9380 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -349,6 +349,17 @@ static void tcg_out_op_rI(TCGContext *s, TCGOpcode op, } #endif =20 +static void tcg_out_op_rl(TCGContext *s, TCGOpcode op, TCGReg r0, TCGLabel= *l1) +{ + uint8_t *old_code_ptr =3D s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tci_out_label(s, l1); + + old_code_ptr[1] =3D s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { uint8_t *old_code_ptr =3D s->code_ptr; @@ -400,20 +411,6 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 -static void tcg_out_op_rrcl(TCGContext *s, TCGOpcode op, - TCGReg r0, TCGReg r1, TCGCond c2, TCGLabel *l3) -{ - uint8_t *old_code_ptr =3D s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out8(s, c2); - tci_out_label(s, l3); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; -} - static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { @@ -487,23 +484,6 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode o= p, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 -static void tcg_out_op_rrrrcl(TCGContext *s, TCGOpcode op, - TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, - TCGCond c4, TCGLabel *l5) -{ - uint8_t *old_code_ptr =3D s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out8(s, c4); - tci_out_label(s, l5); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; -} - static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) @@ -704,7 +684,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, break; =20 CASE_32_64(brcond) - tcg_out_op_rrcl(s, opc, args[0], args[1], args[2], arg_label(args[= 3])); + tcg_out_op_rrrc(s, (opc =3D=3D INDEX_op_brcond_i32 + ? INDEX_op_setcond_i32 : INDEX_op_setcond_i64), + TCG_REG_TMP, args[0], args[1], args[2]); + tcg_out_op_rl(s, opc, TCG_REG_TMP, arg_label(args[3])); break; =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ @@ -730,8 +713,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, args[3], args[4], args[5]); break; case INDEX_op_brcond2_i32: - tcg_out_op_rrrrcl(s, opc, args[0], args[1], args[2], - args[3], args[4], arg_label(args[5])); + tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, TCG_REG_TMP, + args[0], args[1], args[2], args[3], args[4]); + tcg_out_op_rl(s, INDEX_op_brcond_i32, TCG_REG_TMP, arg_label(args[= 5])); break; case INDEX_op_mulu2_i32: tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612407290; cv=none; d=zohomail.com; s=zohoarc; b=HKnIIgWkeVyNUQL5Z/oUo0wmgcJpAB96VWp/WIA9Uucbw5zAqVfrQehA+MOjwVN3zOF2BDuNvaYZBUPtKWPraGuMuCg/+oiUZGA/22fxv6AUShlQq9nMUj9nxUF5ldcxMGF3VjMS8TwLXcO0MMa1j8jsyQAbueLe9ACQJiZi8Wg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612407290; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5KjNyz2z06X1nzffKUJIUfEvh2+8GuNK8mnSHukJjZc=; b=DBzdpv/WyhvJr38BUAm4rN5aJ2tDS/BUWE1ZN1i2gfvEwY7vs9e8fwONUhQMwBw0ld6RNFiRk2o8p8Y/ABJ1Y4AYKv4rPxlrX1O/irpdlcHhhjXJ54Ob7N54oQxGOQXcvUz/2TArC/CXy4F5Y9E5zIAtYQbs4AUC/KpgH7kkGZo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612407290631519.7305184733117; Wed, 3 Feb 2021 18:54:50 -0800 (PST) Received: from localhost ([::1]:51190 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7UnB-0002T1-JR for importer@patchew.org; Wed, 03 Feb 2021 21:54:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Tsm-0000oQ-Oi for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:56:34 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:36078) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tsk-0006wR-6u for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:56:32 -0500 Received: by mail-pl1-x62d.google.com with SMTP id e9so909162plh.3 for ; Wed, 03 Feb 2021 17:56:29 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id a18sm1432841pfr.220.2021.02.03.17.56.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:56:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5KjNyz2z06X1nzffKUJIUfEvh2+8GuNK8mnSHukJjZc=; b=y98clrTjWIslQr7/0N1ZO/1eufhFRNXArBMNDrLF3Dvpv3FwkLYxxJ8qNZ2eMJ7PcS 8Rz5a93IuM8lRMEPPCWrg8f+QHcPDfavmyLcj6EUxvx/sW2H0iLvWDR3Mpc3h/oaysjk mnvLqOh5CGSfrIr13WD5hAL44ooylfq8ZXuhH00yd/8xDlTrmKoKhNdQtKshFs5tcpTB smem7YenO9FjFc7xQ1M5fac9KYjTziXY7zzESgU5R14Q/2Xox1RykGpZekn7SDPuhHkF SYmuYIXHx5I01NeVKL/78JKeo5FdGYXec8Apb4BOSNO2HzN4+pNzVnB4CvPm/PUzSA7k Xcfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5KjNyz2z06X1nzffKUJIUfEvh2+8GuNK8mnSHukJjZc=; b=eeV1FujTDTBSTnqFxcYp3HRV+ElAI3GYJGKI9+oIpcgbyEqd6gJEiOfKwEjsZFNxRR gK2GAx5rQEmJqH63qygAPmOtzko9Y/OfIzRXhEBuBg7pGButfQ38INxLTHdbScihHweJ BgFvYswRWT60ZJXXEEHym65zfJxtWeA49pJAIElKrqi7NVPqhfGlqN8abfuoSQuAboqj vov4NazwJeD7vR0AXZuStWPzEnaEAUDTxqccPcUdHm8OX/oV87rIG0+DixkyM3PdZM3k l+cTomCjcYB2+wVmnXP/514BLjTSMmYWuPimYEzFcetY99PybQgOS6PJNBPJPulmlLb1 ZajA== X-Gm-Message-State: AOAM530tYpm9c6QI1uG1OST/9DzTojB0xAY2IiK0ZwYsWGiwvpQJiW6M iottn9thZfi56urbIJBCI2L0wu6tZ+HfMH6P X-Google-Smtp-Source: ABdhPJySEGL0NvHgj7Bjbsj8UNW6yDvbXeJkrieXBMwWacPdOfIz/pf9KoiFTeXDlqoJZQpwMwfyBA== X-Received: by 2002:a17:90a:bb82:: with SMTP id v2mr5947807pjr.178.1612403788981; Wed, 03 Feb 2021 17:56:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 85/93] tcg/tci: Remove tci_write_reg Date: Wed, 3 Feb 2021 15:56:26 -1000 Message-Id: <20210204015626.885554-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Inline it into its one caller, tci_write_reg64. Drop the asserts that are redundant with tcg_read_r. Signed-off-by: Richard Henderson --- tcg/tci.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index e7268b13e1..4f81cbb904 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -36,20 +36,11 @@ =20 __thread uintptr_t tci_tb_ptr; =20 -static void -tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) -{ - tci_assert(index < TCG_TARGET_NB_REGS); - tci_assert(index !=3D TCG_AREG0); - tci_assert(index !=3D TCG_REG_CALL_STACK); - regs[index] =3D value; -} - static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, uint32_t low_index, uint64_t value) { - tci_write_reg(regs, low_index, value); - tci_write_reg(regs, high_index, value >> 32); + regs[low_index] =3D value; + regs[high_index] =3D value >> 32; } =20 /* Create a 64 bit value from two 32 bit values. */ --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612407459; cv=none; d=zohomail.com; s=zohoarc; b=TcjUzGOJo6osNU1HXm9013GPnCDi4Ah6JJkcGNnAbnC8Rif1OXWJgIHC4HOZ0NsNGHgZewGTqFSZs8bhU1EqFq8kVGCT9HshRWMKN03TB+wQkwnkadk4kNpFvUL2hzLQZ5f6EWrZpuPsxInNnAbyp6j+GOMT41N1WaMByyQKamo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612407459; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kzUnbpFd4N7AqVaseztP0v4eZMlcZVSSr/zLlepL4IA=; b=ITTpdVxZxKsllG3masoxK9oChHha/qdGcT+z67bPUX3qqkCsHroslWXCdnNyZ2Pk3JJsYcOnFR27NscNs1RHcTexH6JDQB/nEq/9otg58yBJKdJQQcZz/XEEJytYsyLPI2HQwBi/R1F7L73AHpc9Pi3tlsxCWQraA0ziajyZ9Tk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612407459773449.5329918071683; Wed, 3 Feb 2021 18:57:39 -0800 (PST) Received: from localhost ([::1]:60034 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7Upu-0006EG-HS for importer@patchew.org; Wed, 03 Feb 2021 21:57:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47136) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Tt9-0001Cy-5t for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:56:55 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:42524) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tt4-00076R-J6 for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:56:54 -0500 Received: by mail-pl1-x633.google.com with SMTP id s15so890952plr.9 for ; Wed, 03 Feb 2021 17:56:49 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id l13sm3222390pjq.30.2021.02.03.17.56.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:56:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kzUnbpFd4N7AqVaseztP0v4eZMlcZVSSr/zLlepL4IA=; b=lmL2/T428QnpkEah5HXAYc+5a0JwCcKvT17Hdj3FIsN641G0YU3XXvYPNguIMV2x6j QnQlzywxJWfhTncjDeebU9Ai6Q+f2edW7ITATUl8tS7YG9lQSo1OaDKmy+kaRc4JgDgN ysxbC6xLcqBprCgSJCYvWhfZp924koSboP47KSjW41MzpehirMFaAaH4yQWyjiOykkYV yDLmYfX/EFJBMU4uon3r0NGpDckcxpAp3YPQFl0nUo8fXFu9ZXzHSk8LGa2QYcG9vA9s Hx2WcwKqowocGGWJtIBiOFW3juTFPhB4lkpPVj2D6i/5ghaOB6eEhbR2HJxp1+3HiFr3 Gn4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kzUnbpFd4N7AqVaseztP0v4eZMlcZVSSr/zLlepL4IA=; b=pPsvbUS1tAiEXjGLK7Ftwn6Iia2SDxFhBKIPBLK6iMJT9TrYTdloGpYfFVwKrDIEJx 245vap+IhLBOrVzNV2mPC+qXIixP4p1LKVnDfhGc3/sQGnTzAAEgR4Cw6Ldw/CWFslzL 3Tm/T7e1NJGyJP65OWJvFD4rRu6+5x0PtNj42LIBuhP7BX74+20ko+9y+sL742MwM8br nFLPbnQt6bIMNnKIvyaAmXPISYjyYogWENzl/z/xYEELlOUkiAKpYkVBCwEm4FfD+dQG N13VZ4Gojp+MUStFGKjoFDQEOQhBOTOOlQzfluu8ttq0jZXzqixJ1rs/CW8UY4x456Rh H2EQ== X-Gm-Message-State: AOAM531NMttsbxR9gX2TrcmwHKkP1q+081lob+YN7o5W1fgy5RoIoEMQ Yrls+uJhPrOkoLNXlOkK3/PXhM/aa/unoBCG X-Google-Smtp-Source: ABdhPJw4IEH9CMwoecppM3+FAnPN7OhiueYHVsWEzBP13imEdz7jFUz2d5arUL5SjoeOvqk3WZssmA== X-Received: by 2002:a17:90a:de2:: with SMTP id 89mr5735238pjv.26.1612403807757; Wed, 03 Feb 2021 17:56:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 86/93] tcg/tci: Change encoding to uint32_t units Date: Wed, 3 Feb 2021 15:56:44 -1000 Message-Id: <20210204015644.885606-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This removes all of the problems with unaligned accesses to the bytecode stream. With an 8-bit opcode at the bottom, we have 24 bits remaining, which are generally split into 6 4-bit slots. This fits well with the maximum length opcodes, e.g. INDEX_op_add2_i386, which have 6 register operands. We have, in previous patches, rearranged things such that there are no operations with a label, which have more than one other operand. Which leaves us with a 20-bit field in which to encode a label, giving us a maximum TB size of 512k -- easily large. Change the INDEX_op_tci_movi_{i32,i64} opcodes to tci_mov[il]. The former puts the immediate in the upper 20 bits of the insn, like we do for the label displacement. The later uses a label to reference an entry in the constant pool. Thus, in the worst case we still have a single memory reference for any constant, but now the constants are out-of-line of the bytecode and can be shared between different moves saving space. Change INDEX_op_call to use a label to reference a pair of pointers in the constant pool. This removes the only slightly dodgy link with the layout of struct TCGHelperInfo. The re-encode cannot be done in pieces. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 4 +- tcg/tci/tcg-target.h | 3 +- tcg/tci.c | 534 +++++++++++++++------------------------ tcg/tci/tcg-target.c.inc | 386 +++++++++++++--------------- tcg/tci/README | 20 +- 5 files changed, 380 insertions(+), 567 deletions(-) diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index bbb0884af8..5bbec858aa 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -277,8 +277,8 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) =20 #ifdef TCG_TARGET_INTERPRETER /* These opcodes are only for use between the tci generator and interprete= r. */ -DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) -DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) +DEF(tci_movi, 1, 0, 1, TCG_OPF_NOT_PRESENT) +DEF(tci_movl, 1, 0, 1, TCG_OPF_NOT_PRESENT) #endif =20 #undef TLADDR_ARGS diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 1558a6e44e..d953f2ead3 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -41,7 +41,7 @@ #define TCG_TARGET_H =20 #define TCG_TARGET_INTERPRETER 1 -#define TCG_TARGET_INSN_UNIT_SIZE 1 +#define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 =20 #if UINTPTR_MAX =3D=3D UINT32_MAX @@ -165,6 +165,7 @@ typedef enum { #define TCG_TARGET_STACK_ALIGN 8 =20 #define HAVE_TCG_QEMU_TB_EXEC +#define TCG_TARGET_NEED_POOL_LABELS =20 /* We could notice __i386__ or __s390x__ and reduce the barriers depending on the host. But if you want performance, you use the normal backend. diff --git a/tcg/tci.c b/tcg/tci.c index 4f81cbb904..c4f0a7e82d 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -49,49 +49,6 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low) return ((uint64_t)high << 32) + low; } =20 -/* Read constant byte from bytecode. */ -static uint8_t tci_read_b(const uint8_t **tb_ptr) -{ - return *(tb_ptr[0]++); -} - -/* Read register number from bytecode. */ -static TCGReg tci_read_r(const uint8_t **tb_ptr) -{ - uint8_t regno =3D tci_read_b(tb_ptr); - tci_assert(regno < TCG_TARGET_NB_REGS); - return regno; -} - -/* Read constant (native size) from bytecode. */ -static tcg_target_ulong tci_read_i(const uint8_t **tb_ptr) -{ - tcg_target_ulong value =3D *(const tcg_target_ulong *)(*tb_ptr); - *tb_ptr +=3D sizeof(value); - return value; -} - -/* Read unsigned constant (32 bit) from bytecode. */ -static uint32_t tci_read_i32(const uint8_t **tb_ptr) -{ - uint32_t value =3D *(const uint32_t *)(*tb_ptr); - *tb_ptr +=3D sizeof(value); - return value; -} - -/* Read signed constant (32 bit) from bytecode. */ -static int32_t tci_read_s32(const uint8_t **tb_ptr) -{ - int32_t value =3D *(const int32_t *)(*tb_ptr); - *tb_ptr +=3D sizeof(value); - return value; -} - -static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) -{ - return tci_read_i(tb_ptr); -} - /* * Load sets of arguments all at once. The naming convention is: * tci_args_ @@ -106,209 +63,128 @@ static tcg_target_ulong tci_read_label(const uint8_t= **tb_ptr) * s =3D signed ldst offset */ =20 -static void check_size(const uint8_t *start, const uint8_t **tb_ptr) +static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0) { - const uint8_t *old_code_ptr =3D start - 2; - uint8_t op_size =3D old_code_ptr[1]; - tci_assert(*tb_ptr =3D=3D old_code_ptr + op_size); + int diff =3D sextract32(insn, 12, 20); + *l0 =3D diff ? (void *)tb_ptr + diff : NULL; } =20 -static void tci_args_l(const uint8_t **tb_ptr, void **l0) +static void tci_args_nl(uint32_t insn, const void *tb_ptr, + uint8_t *n0, void **l1) { - const uint8_t *start =3D *tb_ptr; - - *l0 =3D (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); + *n0 =3D extract32(insn, 8, 4); + *l1 =3D sextract32(insn, 12, 20) + (void *)tb_ptr; } =20 -static void tci_args_nl(const uint8_t **tb_ptr, uint8_t *n0, void **l1) +static void tci_args_rl(uint32_t insn, const void *tb_ptr, + TCGReg *r0, void **l1) { - const uint8_t *start =3D *tb_ptr; - - *n0 =3D tci_read_b(tb_ptr); - *l1 =3D (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *l1 =3D sextract32(insn, 12, 20) + (void *)tb_ptr; } =20 -static void tci_args_rl(const uint8_t **tb_ptr, TCGReg *r0, void **l1) +static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *l1 =3D (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); } =20 -static void tci_args_rr(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1) +static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_target_ulong *i1) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *i1 =3D sextract32(insn, 12, 20); } =20 -static void tci_args_ri(const uint8_t **tb_ptr, - TCGReg *r0, tcg_target_ulong *i1) +static void tci_args_rrm(uint32_t insn, TCGReg *r0, + TCGReg *r1, TCGMemOpIdx *m2) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *i1 =3D tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *m2 =3D extract32(insn, 20, 12); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -static void tci_args_rI(const uint8_t **tb_ptr, - TCGReg *r0, tcg_target_ulong *i1) +static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *i1 =3D tci_read_i(tb_ptr); - - check_size(start, tb_ptr); -} -#endif - -static void tci_args_rrm(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2) -{ - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *m2 =3D tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); } =20 -static void tci_args_rrr(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, TCGReg *r2) +static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i= 2) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *i2 =3D sextract32(insn, 16, 16); } =20 -static void tci_args_rrs(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, int32_t *i2) -{ - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *i2 =3D tci_read_s32(tb_ptr); - - check_size(start, tb_ptr); -} - -static void tci_args_rrrc(const uint8_t **tb_ptr, +static void tci_args_rrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *c3 =3D tci_read_b(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *c3 =3D extract32(insn, 20, 4); } =20 -static void tci_args_rrrm(const uint8_t **tb_ptr, +static void tci_args_rrrm(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx = *m3) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *m3 =3D tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *m3 =3D extract32(insn, 20, 12); } =20 -static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, +static void tci_args_rrrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, uint8_t *i3, uint8_t *i4) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *i3 =3D tci_read_b(tb_ptr); - *i4 =3D tci_read_b(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *i3 =3D extract32(insn, 20, 6); + *i4 =3D extract32(insn, 26, 6); } =20 -static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, - TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4) +static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGReg *r4) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *r3 =3D tci_read_r(tb_ptr); - *m4 =3D tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *r3 =3D extract32(insn, 20, 4); + *r4 =3D extract32(insn, 24, 4); } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 -static void tci_args_rrrr(const uint8_t **tb_ptr, +static void tci_args_rrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *r3 =3D tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *r3 =3D extract32(insn, 20, 4); } =20 -static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, +static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *r3 =3D tci_read_r(tb_ptr); - *r4 =3D tci_read_r(tb_ptr); - *c5 =3D tci_read_b(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *r3 =3D extract32(insn, 20, 4); + *r4 =3D extract32(insn, 24, 4); + *c5 =3D extract32(insn, 28, 4); } =20 -static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, +static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { - const uint8_t *start =3D *tb_ptr; - - *r0 =3D tci_read_r(tb_ptr); - *r1 =3D tci_read_r(tb_ptr); - *r2 =3D tci_read_r(tb_ptr); - *r3 =3D tci_read_r(tb_ptr); - *r4 =3D tci_read_r(tb_ptr); - *r5 =3D tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *r3 =3D extract32(insn, 20, 4); + *r4 =3D extract32(insn, 24, 4); + *r5 =3D extract32(insn, 28, 4); } #endif =20 @@ -464,7 +340,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCG= Cond condition) uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, const void *v_tb_ptr) { - const uint8_t *tb_ptr =3D v_tb_ptr; + const uint32_t *tb_ptr =3D v_tb_ptr; tcg_target_ulong regs[TCG_TARGET_NB_REGS]; uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) / sizeof(uint64_t)]; @@ -476,8 +352,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_assert(tb_ptr); =20 for (;;) { - TCGOpcode opc =3D tb_ptr[0]; - TCGReg r0, r1, r2, r3; + uint32_t insn; + TCGOpcode opc; + TCGReg r0, r1, r2, r3, r4; tcg_target_ulong t1; TCGCond condition; target_ulong taddr; @@ -485,23 +362,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r4, r5; + TCGReg r5; uint64_t T1, T2; #endif TCGMemOpIdx oi; int32_t ofs; void *ptr; =20 - /* Skip opcode and size entry. */ - tb_ptr +=3D 2; + insn =3D *tb_ptr++; + opc =3D extract32(insn, 0, 8); =20 switch (opc) { case INDEX_op_call: - /* - * We are passed a pointer to the TCGHelperInfo, which contains - * the function pointer followed by the ffi_cif pointer. - */ - tci_args_nl(&tb_ptr, &len, &ptr); + tci_args_nl(insn, tb_ptr, &len, &ptr); =20 /* Helper functions may need to access the "return address" */ tci_tb_ptr =3D (uintptr_t)tb_ptr; @@ -519,8 +392,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, } =20 /* - * Call the helper function. Any result winds up - * "left-aligned" in the stack[0] slot. + * We are passed a pointer into the constant pool, which + * contains a pair of the function pointer and the cif pointer. + * Any result winds up "left-aligned" in the stack[0] slot. */ { void **pptr =3D ptr; @@ -545,76 +419,80 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; =20 case INDEX_op_br: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); tb_ptr =3D ptr; continue; case INDEX_op_setcond_i32: - tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] =3D tci_compare32(regs[r1], regs[r2], condition); break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: - tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &condition); + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); T1 =3D tci_uint64(regs[r2], regs[r1]); T2 =3D tci_uint64(regs[r4], regs[r3]); regs[r0] =3D tci_compare64(T1, T2, condition); break; #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: - tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] =3D tci_compare64(regs[r1], regs[r2], condition); break; #endif CASE_32_64(mov) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D regs[r1]; break; - case INDEX_op_tci_movi_i32: - tci_args_ri(&tb_ptr, &r0, &t1); + case INDEX_op_tci_movi: + tci_args_ri(insn, &r0, &t1); regs[r0] =3D t1; break; + case INDEX_op_tci_movl: + tci_args_rl(insn, tb_ptr, &r0, &ptr); + regs[r0] =3D *(tcg_target_ulong *)ptr; + break; =20 /* Load/store operations (32 bit). */ =20 CASE_32_64(ld8u) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(uint8_t *)ptr; break; CASE_32_64(ld8s) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(int8_t *)ptr; break; CASE_32_64(ld16u) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(uint16_t *)ptr; break; CASE_32_64(ld16s) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(int16_t *)ptr; break; case INDEX_op_ld_i32: CASE_64(ld32u) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(uint32_t *)ptr; break; CASE_32_64(st8) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); *(uint8_t *)ptr =3D regs[r0]; break; CASE_32_64(st16) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); *(uint16_t *)ptr =3D regs[r0]; break; case INDEX_op_st_i32: CASE_64(st32) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); *(uint32_t *)ptr =3D regs[r0]; break; @@ -622,171 +500,166 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArch= State *env, /* Arithmetic operations (mixed 32/64 bit). */ =20 CASE_32_64(add) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] + regs[r2]; break; CASE_32_64(sub) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] - regs[r2]; break; CASE_32_64(mul) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] * regs[r2]; break; CASE_32_64(and) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] & regs[r2]; break; CASE_32_64(or) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] | regs[r2]; break; CASE_32_64(xor) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] ^ regs[r2]; break; =20 /* Arithmetic operations (32 bit). */ =20 case INDEX_op_div_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (int32_t)regs[r1] / (int32_t)regs[r2]; break; case INDEX_op_divu_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint32_t)regs[r1] / (uint32_t)regs[r2]; break; case INDEX_op_rem_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (int32_t)regs[r1] % (int32_t)regs[r2]; break; case INDEX_op_remu_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint32_t)regs[r1] % (uint32_t)regs[r2]; break; =20 /* Shift/rotate operations (32 bit). */ =20 case INDEX_op_shl_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint32_t)regs[r1] << (regs[r2] & 31); break; case INDEX_op_shr_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint32_t)regs[r1] >> (regs[r2] & 31); break; case INDEX_op_sar_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (int32_t)regs[r1] >> (regs[r2] & 31); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D rol32(regs[r1], regs[r2] & 31); break; case INDEX_op_rotr_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D ror32(regs[r1], regs[r2] & 31); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: - tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] =3D deposit32(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i32: - tci_args_rl(&tb_ptr, &r0, &ptr); + tci_args_rl(insn, tb_ptr, &r0, &ptr); if ((uint32_t)regs[r0]) { tb_ptr =3D ptr; } break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: - tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 =3D tci_uint64(regs[r3], regs[r2]); T2 =3D tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 + T2); break; case INDEX_op_sub2_i32: - tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 =3D tci_uint64(regs[r3], regs[r2]); T2 =3D tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; case INDEX_op_mulu2_i32: - tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D (int8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 CASE_32_64(ext16s) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D (int16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 CASE_32_64(ext8u) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D (uint8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 CASE_32_64(ext16u) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D (uint16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 CASE_32_64(bswap16) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D bswap16(regs[r1]); break; #endif #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 CASE_32_64(bswap32) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D bswap32(regs[r1]); break; #endif #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 CASE_32_64(not) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D ~regs[r1]; break; #endif #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 CASE_32_64(neg) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D -regs[r1]; break; #endif #if TCG_TARGET_REG_BITS =3D=3D 64 - case INDEX_op_tci_movi_i64: - tci_args_rI(&tb_ptr, &r0, &t1); - regs[r0] =3D t1; - break; - /* Load/store operations (64 bit). */ =20 case INDEX_op_ld32s_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(int32_t *)ptr; break; case INDEX_op_ld_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); regs[r0] =3D *(uint64_t *)ptr; break; case INDEX_op_st_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr =3D (void *)(regs[r1] + ofs); *(uint64_t *)ptr =3D regs[r0]; break; @@ -794,71 +667,71 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, /* Arithmetic operations (64 bit). */ =20 case INDEX_op_div_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (int64_t)regs[r1] / (int64_t)regs[r2]; break; case INDEX_op_divu_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint64_t)regs[r1] / (uint64_t)regs[r2]; break; case INDEX_op_rem_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (int64_t)regs[r1] % (int64_t)regs[r2]; break; case INDEX_op_remu_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint64_t)regs[r1] % (uint64_t)regs[r2]; break; =20 /* Shift/rotate operations (64 bit). */ =20 case INDEX_op_shl_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] << (regs[r2] & 63); break; case INDEX_op_shr_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] >> (regs[r2] & 63); break; case INDEX_op_sar_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (int64_t)regs[r1] >> (regs[r2] & 63); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D rol64(regs[r1], regs[r2] & 63); break; case INDEX_op_rotr_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D ror64(regs[r1], regs[r2] & 63); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: - tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] =3D deposit64(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i64: - tci_args_rl(&tb_ptr, &r0, &ptr); + tci_args_rl(insn, tb_ptr, &r0, &ptr); if (regs[r0]) { tb_ptr =3D ptr; } break; case INDEX_op_ext32s_i64: case INDEX_op_ext_i32_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D (int32_t)regs[r1]; break; case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D (uint32_t)regs[r1]; break; #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] =3D bswap64(regs[r1]); break; #endif @@ -867,20 +740,20 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, /* QEMU specific operations. */ =20 case INDEX_op_exit_tb: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); return (uintptr_t)ptr; =20 case INDEX_op_goto_tb: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); tb_ptr =3D *(void **)ptr; break; =20 case INDEX_op_qemu_ld_i32: if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; } else { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr =3D tci_uint64(regs[r2], regs[r1]); } switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { @@ -916,14 +789,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_qemu_ld_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr =3D regs[r2]; } else { - tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); taddr =3D tci_uint64(regs[r3], regs[r2]); + oi =3D regs[r4]; } switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: @@ -974,10 +848,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_qemu_st_i32: if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; } else { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr =3D tci_uint64(regs[r2], regs[r1]); } tmp32 =3D regs[r0]; @@ -1004,16 +878,17 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchS= tate *env, =20 case INDEX_op_qemu_st_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; tmp64 =3D regs[r0]; } else { if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr =3D regs[r2]; } else { - tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); taddr =3D tci_uint64(regs[r3], regs[r2]); + oi =3D regs[r4]; } tmp64 =3D tci_uint64(regs[r1], regs[r0]); } @@ -1097,14 +972,14 @@ static const char *str_c(TCGCond c) /* Disassemble TCI bytecode. */ int print_insn_tci(bfd_vma addr, disassemble_info *info) { - uint8_t buf[256]; - int length, status; + const uint32_t *tb_ptr =3D (const void *)(uintptr_t)addr; const TCGOpDef *def; const char *op_name; + uint32_t insn; TCGOpcode op; - TCGReg r0, r1, r2, r3; + TCGReg r0, r1, r2, r3, r4; #if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r4, r5; + TCGReg r5; #endif tcg_target_ulong i1; int32_t s2; @@ -1112,71 +987,54 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) TCGMemOpIdx oi; uint8_t pos, len; void *ptr; - const uint8_t *tb_ptr; =20 - status =3D info->read_memory_func(addr, buf, 2, info); - if (status !=3D 0) { - info->memory_error_func(status, addr, info); - return -1; - } - op =3D buf[0]; - length =3D buf[1]; + /* TCI is always the host, so we don't need to load indirect. */ + insn =3D *tb_ptr++; =20 - if (length < 2) { - info->fprintf_func(info->stream, "invalid length %d", length); - return 1; - } - - status =3D info->read_memory_func(addr + 2, buf + 2, length - 2, info); - if (status !=3D 0) { - info->memory_error_func(status, addr + 2, info); - return -1; - } + info->fprintf_func(info->stream, "%08x ", insn); =20 + op =3D extract32(insn, 0, 8); def =3D &tcg_op_defs[op]; op_name =3D def->name; - tb_ptr =3D buf + 2; =20 switch (op) { case INDEX_op_br: case INDEX_op_exit_tb: case INDEX_op_goto_tb: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); break; =20 case INDEX_op_call: - tci_args_nl(&tb_ptr, &len, &ptr); + tci_args_nl(insn, tb_ptr, &len, &ptr); info->fprintf_func(info->stream, "%-12s %d,%p", op_name, len, ptr= ); break; =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - tci_args_rl(&tb_ptr, &r0, &ptr); + tci_args_rl(insn, tb_ptr, &r0, &ptr); info->fprintf_func(info->stream, "%-12s %s,0,ne,%p", op_name, str_r(r0), ptr); break; =20 case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &c); + tci_args_rrrc(insn, &r0, &r1, &r2, &c); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_c= (c)); break; =20 - case INDEX_op_tci_movi_i32: - tci_args_ri(&tb_ptr, &r0, &i1); + case INDEX_op_tci_movi: + tci_args_ri(insn, &r0, &i1); info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "", op_name, str_r(r0), i1); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 - case INDEX_op_tci_movi_i64: - tci_args_rI(&tb_ptr, &r0, &i1); - info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "", - op_name, str_r(r0), i1); + case INDEX_op_tci_movl: + tci_args_rl(insn, tb_ptr, &r0, &ptr); + info->fprintf_func(info->stream, "%-12s %s,%p", + op_name, str_r(r0), ptr); break; -#endif =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: @@ -1197,7 +1055,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) case INDEX_op_st32_i64: case INDEX_op_st_i32: case INDEX_op_st_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &s2); + tci_args_rrs(insn, &r0, &r1, &s2); info->fprintf_func(info->stream, "%-12s %s,%s,%d", op_name, str_r(r0), str_r(r1), s2); break; @@ -1224,7 +1082,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) case INDEX_op_not_i64: case INDEX_op_neg_i32: case INDEX_op_neg_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); info->fprintf_func(info->stream, "%-12s %s,%s", op_name, str_r(r0), str_r(r1)); break; @@ -1259,28 +1117,28 @@ int print_insn_tci(bfd_vma addr, disassemble_info *= info) case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); info->fprintf_func(info->stream, "%-12s %s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2)); break; =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%d,%d", op_name, str_r(r0), str_r(r1), str_r(r2), pos, = len); break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: - tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &c); + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3), str_r(r4), str_c(c)); break; =20 case INDEX_op_mulu2_i32: - tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3)); @@ -1288,7 +1146,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) =20 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3), str_r(r4), str_r(r5)); @@ -1306,30 +1164,38 @@ int print_insn_tci(bfd_vma addr, disassemble_info *= info) len +=3D DIV_ROUND_UP(TARGET_LONG_BITS, TCG_TARGET_REG_BITS); switch (len) { case 2: - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); info->fprintf_func(info->stream, "%-12s %s,%s,%x", op_name, str_r(r0), str_r(r1), oi); break; case 3: - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%x", op_name, str_r(r0), str_r(r1), str_r(r2), o= i); break; case 4: - tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); - info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%x", + tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s", op_name, str_r(r0), str_r(r1), - str_r(r2), str_r(r3), oi); + str_r(r2), str_r(r3), str_r(r4)); break; default: g_assert_not_reached(); } break; =20 + case 0: + /* tcg_out_nop_fill uses zeros */ + if (insn =3D=3D 0) { + info->fprintf_func(info->stream, "align"); + break; + } + /* fall through */ + default: info->fprintf_func(info->stream, "illegal opcode %d", op); break; } =20 - return length; + return sizeof(insn); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index e06d4e9380..0df8384be7 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -22,20 +22,7 @@ * THE SOFTWARE. */ =20 -/* TODO list: - * - See TODO comments in code. - */ - -/* Marker for missing code. */ -#define TODO() \ - do { \ - fprintf(stderr, "TODO %s:%u: %s()\n", \ - __FILE__, __LINE__, __func__); \ - tcg_abort(); \ - } while (0) - -/* Bitfield n...m (in 32 bit value). */ -#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) +#include "../tcg-pool.c.inc" =20 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { @@ -226,52 +213,16 @@ static const char *const tcg_target_reg_names[TCG_TAR= GET_NB_REGS] =3D { static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - /* tcg_out_reloc always uses the same type, addend. */ - tcg_debug_assert(type =3D=3D sizeof(tcg_target_long)); + intptr_t diff =3D value - (intptr_t)(code_ptr + 1); + tcg_debug_assert(addend =3D=3D 0); - tcg_debug_assert(value !=3D 0); - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_patch32(code_ptr, value); - } else { - tcg_patch64(code_ptr, value); - } - return true; -} - -/* Write value (native size). */ -static void tcg_out_i(TCGContext *s, tcg_target_ulong v) -{ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out32(s, v); - } else { - tcg_out64(s, v); - } -} - -/* Write opcode. */ -static void tcg_out_op_t(TCGContext *s, TCGOpcode op) -{ - tcg_out8(s, op); - tcg_out8(s, 0); -} - -/* Write register. */ -static void tcg_out_r(TCGContext *s, TCGArg t0) -{ - tcg_debug_assert(t0 < TCG_TARGET_NB_REGS); - tcg_out8(s, t0); -} - -/* Write label. */ -static void tci_out_label(TCGContext *s, TCGLabel *label) -{ - if (label->has_value) { - tcg_out_i(s, label->u.value); - tcg_debug_assert(label->u.value); - } else { - tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), label, 0); - s->code_ptr +=3D sizeof(tcg_target_ulong); + tcg_debug_assert(type =3D=3D 20); + + if (diff =3D=3D sextract32(diff, 0, type)) { + tcg_patch32(code_ptr, deposit32(*code_ptr, 32 - type, type, diff)); + return true; } + return false; } =20 static void stack_bounds_check(TCGReg base, target_long offset) @@ -285,251 +236,236 @@ static void stack_bounds_check(TCGReg base, target_= long offset) =20 static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tci_out_label(s, l0); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_reloc(s, s->code_ptr, 20, l0, 0); + insn =3D deposit32(insn, 0, 8, op); + tcg_out32(s, insn); } =20 static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; + intptr_t diff; =20 - tcg_out_op_t(s, op); - tcg_out_i(s, (uintptr_t)p0); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + /* Special case for exit_tb: map null -> 0. */ + if (p0 =3D=3D NULL) { + diff =3D 0; + } else { + diff =3D p0 - (void *)(s->code_ptr + 1); + tcg_debug_assert(diff !=3D 0); + if (diff !=3D sextract32(diff, 0, 20)) { + tcg_raise_tb_overflow(s); + } + } + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 12, 20, diff); + tcg_out32(s, insn); } =20 static void tcg_out_op_v(TCGContext *s, TCGOpcode op) { - uint8_t *old_code_ptr =3D s->code_ptr; - - tcg_out_op_t(s, op); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; -} - -static void tcg_out_op_np(TCGContext *s, TCGOpcode op, - uint8_t n0, const void *p1) -{ - uint8_t *old_code_ptr =3D s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out8(s, n0); - tcg_out_i(s, (uintptr_t)p1); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out32(s, (uint8_t)op); } =20 static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t = i1) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out32(s, i1); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_debug_assert(i1 =3D=3D sextract32(i1, 0, 20)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 20, i1); + tcg_out32(s, insn); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -static void tcg_out_op_rI(TCGContext *s, TCGOpcode op, - TCGReg r0, uint64_t i1) -{ - uint8_t *old_code_ptr =3D s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out64(s, i1); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; -} -#endif - static void tcg_out_op_rl(TCGContext *s, TCGOpcode op, TCGReg r0, TCGLabel= *l1) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tci_out_label(s, l1); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_out_reloc(s, s->code_ptr, 20, l1, 0); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + tcg_out32(s, insn); } =20 static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrm(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGArg m2) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out32(s, m2); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_debug_assert(m2 =3D=3D extract32(m2, 0, 12)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 20, 12, m2); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_debug_assert(i2 =3D=3D (int32_t)i2); - tcg_out32(s, i2); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_debug_assert(i2 =3D=3D sextract32(i2, 0, 16)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 16, i2); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out8(s, c3); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 4, c3); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrrm(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGArg m3) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out32(s, m3); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_debug_assert(m3 =3D=3D extract32(m3, 0, 12)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 12, m3); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out8(s, b3); - tcg_out8(s, b4); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + tcg_debug_assert(b3 =3D=3D extract32(b3, 0, 6)); + tcg_debug_assert(b4 =3D=3D extract32(b4, 0, 6)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 6, b3); + insn =3D deposit32(insn, 26, 6, b4); + tcg_out32(s, insn); } =20 -static void tcg_out_op_rrrrm(TCGContext *s, TCGOpcode op, TCGReg r0, - TCGReg r1, TCGReg r2, TCGReg r3, TCGArg m4) +static void tcg_out_op_rrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out32(s, m4); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 4, r3); + insn =3D deposit32(insn, 24, 4, r4); + tcg_out32(s, insn); } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 4, r3); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out_r(s, r4); - tcg_out8(s, c5); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 4, r3); + insn =3D deposit32(insn, 24, 4, r4); + insn =3D deposit32(insn, 28, 4, c5); + tcg_out32(s, insn); } =20 static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGReg r5) { - uint8_t *old_code_ptr =3D s->code_ptr; + tcg_insn_unit insn =3D 0; =20 - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out_r(s, r4); - tcg_out_r(s, r5); - - old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 4, r3); + insn =3D deposit32(insn, 24, 4, r4); + insn =3D deposit32(insn, 28, 4, r5); + tcg_out32(s, insn); } #endif =20 +static void tcg_out_ldst(TCGContext *s, TCGOpcode op, TCGReg val, + TCGReg base, intptr_t offset) +{ + stack_bounds_check(base, offset); + if (offset !=3D sextract32(offset, 0, 16)) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); + tcg_out_op_rrr(s, (TCG_TARGET_REG_BITS =3D=3D 32 + ? INDEX_op_add_i32 : INDEX_op_add_i64), + TCG_REG_TMP, TCG_REG_TMP, base); + base =3D TCG_REG_TMP; + offset =3D 0; + } + tcg_out_op_rrs(s, op, val, base, offset); +} + static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, intptr_t offset) { - stack_bounds_check(base, offset); switch (type) { case TCG_TYPE_I32: - tcg_out_op_rrs(s, INDEX_op_ld_i32, val, base, offset); + tcg_out_ldst(s, INDEX_op_ld_i32, val, base, offset); break; #if TCG_TARGET_REG_BITS =3D=3D 64 case TCG_TYPE_I64: - tcg_out_op_rrs(s, INDEX_op_ld_i64, val, base, offset); + tcg_out_ldst(s, INDEX_op_ld_i64, val, base, offset); break; #endif default: @@ -559,22 +495,33 @@ static void tcg_out_movi(TCGContext *s, TCGType type, { switch (type) { case TCG_TYPE_I32: - tcg_out_op_ri(s, INDEX_op_tci_movi_i32, ret, arg); - break; #if TCG_TARGET_REG_BITS =3D=3D 64 + arg =3D (int32_t)arg; + /* fall through */ case TCG_TYPE_I64: - tcg_out_op_rI(s, INDEX_op_tci_movi_i64, ret, arg); - break; #endif + break; default: g_assert_not_reached(); } + + if (arg =3D=3D sextract32(arg, 0, 20)) { + tcg_out_op_ri(s, INDEX_op_tci_movi, ret, arg); + } else { + tcg_insn_unit insn =3D 0; + + new_pool_label(s, arg, 20, s->code_ptr, 0); + insn =3D deposit32(insn, 0, 8, INDEX_op_tci_movl); + insn =3D deposit32(insn, 8, 4, ret); + tcg_out32(s, insn); + } } =20 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { const TCGHelperInfo *info; uint8_t which; + tcg_insn_unit insn =3D 0; =20 info =3D g_hash_table_lookup(helper_table, (gpointer)arg); if (info->cif->rtype =3D=3D &ffi_type_void) { @@ -586,7 +533,11 @@ static void tcg_out_call(TCGContext *s, const tcg_insn= _unit *arg) which =3D 2; } =20 - tcg_out_op_np(s, INDEX_op_call, which, info); + new_pool_l2(s, 20, s->code_ptr, 0, + (uintptr_t)info->func, (uintptr_t)info->cif); + insn =3D deposit32(insn, 0, 8, INDEX_op_call); + insn =3D deposit32(insn, 8, 4, which); + tcg_out32(s, insn); } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -644,8 +595,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, case INDEX_op_st_i32: CASE_64(st32) CASE_64(st) - stack_bounds_check(args[1], args[2]); - tcg_out_op_rrs(s, opc, args[0], args[1], args[2]); + tcg_out_ldst(s, opc, args[0], args[1], args[2]); break; =20 CASE_32_64(add) @@ -738,8 +688,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); } else { - tcg_out_op_rrrrm(s, opc, args[0], args[1], - args[2], args[3], args[4]); + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, args[4]); + tcg_out_op_rrrrr(s, opc, args[0], args[1], + args[2], args[3], TCG_REG_TMP); } break; =20 @@ -787,6 +738,11 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, return arg_ct->ct & TCG_CT_CONST; } =20 +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + memset(p, 0, sizeof(*p) * count); +} + static void tcg_target_init(TCGContext *s) { #if defined(CONFIG_DEBUG_TCG_INTERPRETER) diff --git a/tcg/tci/README b/tcg/tci/README index 9bb7d7a5d3..f72a40a395 100644 --- a/tcg/tci/README +++ b/tcg/tci/README @@ -23,10 +23,12 @@ This is what TCI (Tiny Code Interpreter) does. Like each TCG host frontend, TCI implements the code generator in tcg-target.c.inc, tcg-target.h. Both files are in directory tcg/tci. =20 -The additional file tcg/tci.c adds the interpreter. +The additional file tcg/tci.c adds the interpreter and disassembler. =20 -The bytecode consists of opcodes (same numeric values as those used by -TCG), command length and arguments of variable size and number. +The bytecode consists of opcodes (with only a few exceptions, with +the same same numeric values and semantics as used by TCG), and up +to six arguments packed into a 32-bit integer. See comments in tci.c +for details on the encoding. =20 3) Usage =20 @@ -39,11 +41,6 @@ suggest using this option. Setting it automatically woul= d need additional code in configure which must be fixed when new native TCG implementations are added. =20 -System emulation should work on any 32 or 64 bit host. -User mode emulation might work. Maybe a new linker script (*.ld) -is needed. Byte order might be wrong (on big endian hosts) -and need fixes in configure. - For hosts with native TCG, the interpreter TCI can be enabled by =20 configure --enable-tcg-interpreter @@ -118,13 +115,6 @@ u1 =3D linux-user-test works in the interpreter. These opcodes raise a runtime exception, so it is possible to see where code must be added. =20 -* The pseudo code is not optimized and still ugly. For hosts with special - alignment requirements, it needs some fixes (maybe aligned bytecode - would also improve speed for hosts which support byte alignment). - -* A better disassembler for the pseudo code would be nice (a very primitive - disassembler is included in tcg-target.c.inc). - * It might be useful to have a runtime option which selects the native TCG or TCI, so QEMU would have to include two TCGs. Today, selecting TCI is a configure option, so you need two compilations of QEMU. --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612407452; cv=none; d=zohomail.com; s=zohoarc; b=bUUKAmDfAOH7i6lgHX6h9wBChwxCh/mDSp3ili79CaJXDsgwDCbyDTSyGRO16G2j9FemhGXdjw/YHnicuafdREy/pmmwQ3gAPocrChO2cnZGCRTBEhcnTwF1yiMAKHWh+lVLS1Z5wP0LGviuUielCXR3npDeVAUn2WkDuILw02c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612407452; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZqOw+gxfHcL+GE2Ru72t2p+WgkIxr/f1vF2n8FMDX2k=; b=D97Ioa7bs5GNOcppkg3VBdLH3vqUAxOC/gF0gl/n7Tz1liGuXc+G4IFaoCrUZaamchEQaeH+B73dnzAA3NtJDgKfSBTcnacrHBcGaQESih8KmAEfd9Sn6kARUOCsBPHLvMiPg763mV9KuRCYsREaR+b8HrR96d7ltDdiIarn9ls= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612407452697723.0150970990396; Wed, 3 Feb 2021 18:57:32 -0800 (PST) Received: from localhost ([::1]:59564 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7Upn-00062R-M6 for importer@patchew.org; Wed, 03 Feb 2021 21:57:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47202) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7TtR-0001Nf-4y for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:57:13 -0500 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:35995) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7TtL-0007Bz-GM for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:57:09 -0500 Received: by mail-pf1-x42e.google.com with SMTP id y142so1094307pfb.3 for ; Wed, 03 Feb 2021 17:57:07 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id y200sm266845pfc.103.2021.02.03.17.57.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:57:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZqOw+gxfHcL+GE2Ru72t2p+WgkIxr/f1vF2n8FMDX2k=; b=GpBqUzAnFIKA/lbJ3a8umNNPl+oG24xZ0UdZ8oKz1mn7VZFCCo1EfbYlFwGFy8WGPQ o0aQbOf3nxXl7s80ni068/A8n3minVkl8icb7S1jzS9vDA+cJi8c6MsFOcxQAs5IdDfu ykkhh2e7jFCa2KMNCEu9wfusoX+vP2pXEYSumbAkLtU17Xe8CDQxolHPJSiGFIfRKsJw UJu71QYQ2sD3UiL6XwVDWF6OEaAqytayo/AMQ+4A+F64vUVHxFdLrD5V5r5ZkqtwLtCw 8GOGJqjXcf10YMOY4Zq9r5sXdjord0i1mewqDyBfvzkDr34VAwiZC8pbGHyMTpXF4wkN 15Xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZqOw+gxfHcL+GE2Ru72t2p+WgkIxr/f1vF2n8FMDX2k=; b=DDangCWOk3W7l1bKffLqQuGwzPSX9VvkAIFuw8LTNp+mdPIw4+pKEEyK/F4RwgfLUA 0q04iBMtTw30EkfFI/g5CmTa8tdfUo9TTZ6o4RXMXrkEycedwUjzOardB9hpfv1Nw0PU 3Wt9Lhy9og7vY1k5txxqX1VrRKYrAWozI7YRAPar7XcV6y1S1oJ0jig8xpTVfFIhTb1q xrjWvTxWrcNDPKDwFa3P7TLFFrZyVc71sQcXowgrbJwHcOOzgNVNj1f7/EgMusT1dSjq BPrTtB3N7Dd4z7BQC+XR1v80hzJsXBs41HTcSNWwiOFUVi8gCE1RETiOVvObJ8Fw/80X yWZQ== X-Gm-Message-State: AOAM533RGaqxhY/PHERc0VrYyYY1ff4KPByxCAlcrZzEuAbKmc6zAU+P cL3baiMKgZV0biwsCcDrKCqoJtcws4GfVB4E X-Google-Smtp-Source: ABdhPJw8YAGGSOfchXDPc0aAFQC1R3//pvtuhgktJZQYJ7wG0vIamt6JSVjcl3tXaUv2UtcpjO4+TA== X-Received: by 2002:a63:4f09:: with SMTP id d9mr6793173pgb.70.1612403826136; Wed, 03 Feb 2021 17:57:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 87/93] tcg/tci: Implement goto_ptr Date: Wed, 3 Feb 2021 15:57:03 -1000 Message-Id: <20210204015703.885660-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This operation is critical to staying within the interpretation loop longer, which avoids the overhead of setup and teardown for many TBs. The check in tcg_prologue_init is disabled because TCI does want to use NULL to indicate exit, as opposed to branching to a real epilogue. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-con-set.h | 1 + tcg/tci/tcg-target.h | 2 +- tcg/tcg.c | 2 ++ tcg/tci.c | 19 +++++++++++++++++++ tcg/tci/tcg-target.c.inc | 16 ++++++++++++++++ 5 files changed, 39 insertions(+), 1 deletion(-) diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h index 316730f32c..ae2dc3b844 100644 --- a/tcg/tci/tcg-target-con-set.h +++ b/tcg/tci/tcg-target-con-set.h @@ -9,6 +9,7 @@ * Each operand should be a sequence of constraint letters as defined by * tcg-target-con-str.h; the constraint combination is inclusive or. */ +C_O0_I1(r) C_O0_I2(r, r) C_O0_I3(r, r, r) C_O0_I4(r, r, r, r) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index d953f2ead3..17911d3297 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -86,7 +86,7 @@ #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 -#define TCG_TARGET_HAS_goto_ptr 0 +#define TCG_TARGET_HAS_goto_ptr 1 #define TCG_TARGET_HAS_direct_jump 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 diff --git a/tcg/tcg.c b/tcg/tcg.c index 92aec0d238..ce80adcfbe 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1314,10 +1314,12 @@ void tcg_prologue_init(TCGContext *s) } #endif =20 +#ifndef CONFIG_TCG_INTERPRETER /* Assert that goto_ptr is implemented completely. */ if (TCG_TARGET_HAS_goto_ptr) { tcg_debug_assert(tcg_code_gen_epilogue !=3D NULL); } +#endif } =20 void tcg_func_start(TCGContext *s) diff --git a/tcg/tci.c b/tcg/tci.c index c4f0a7e82d..a6e30d31a9 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -69,6 +69,11 @@ static void tci_args_l(uint32_t insn, const void *tb_ptr= , void **l0) *l0 =3D diff ? (void *)tb_ptr + diff : NULL; } =20 +static void tci_args_r(uint32_t insn, TCGReg *r0) +{ + *r0 =3D extract32(insn, 8, 4); +} + static void tci_args_nl(uint32_t insn, const void *tb_ptr, uint8_t *n0, void **l1) { @@ -748,6 +753,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tb_ptr =3D *(void **)ptr; break; =20 + case INDEX_op_goto_ptr: + tci_args_r(insn, &r0); + ptr =3D (void *)regs[r0]; + if (!ptr) { + return 0; + } + tb_ptr =3D ptr; + break; + case INDEX_op_qemu_ld_i32: if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { tci_args_rrm(insn, &r0, &r1, &oi); @@ -1005,6 +1019,11 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); break; =20 + case INDEX_op_goto_ptr: + tci_args_r(insn, &r0); + info->fprintf_func(info->stream, "%-12s %s", op_name, str_r(r0)); + break; + case INDEX_op_call: tci_args_nl(insn, tb_ptr, &len, &ptr); info->fprintf_func(info->stream, "%-12s %d,%p", op_name, len, ptr= ); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 0df8384be7..db29bc6e54 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -27,6 +27,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { switch (op) { + case INDEX_op_goto_ptr: + return C_O0_I1(r); + case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: @@ -263,6 +266,15 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, = void *p0) tcg_out32(s, insn); } =20 +static void tcg_out_op_r(TCGContext *s, TCGOpcode op, TCGReg r0) +{ + tcg_insn_unit insn =3D 0; + + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + tcg_out32(s, insn); +} + static void tcg_out_op_v(TCGContext *s, TCGOpcode op) { tcg_out32(s, (uint8_t)op); @@ -567,6 +579,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, set_jmp_reset_offset(s, args[0]); break; =20 + case INDEX_op_goto_ptr: + tcg_out_op_r(s, opc, args[0]); + break; + case INDEX_op_br: tcg_out_op_l(s, opc, arg_label(args[0])); break; --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612407602; cv=none; d=zohomail.com; s=zohoarc; b=QYiWwk5HU9PeogRlQzwOsL5dDpolJ9sI8S8/U/vB0XcpswGqj54n1nv9zJ0CSTRoqA9KblPxq4+pBD3rBtNyCuHOcV4RW5LcQwF6BLCvZpXxHF/086Hj3J+Y8L/4gaQjBo+IHDgbaiBqDwKm50mNU31fPUSzyZxElA9O91sx1XA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612407602; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lLuTVZMheh+w94V9lSybCso+88KsI23VfpQyYgw6vik=; b=kgKzaY5m3Mtvx1mavtYWjTNBwuvVUy6KZE3ZLrkNRUnppESRZTk4VFW3p+GlHJNSmuywHL15AyLLwvBqlnfGa458AqfW18zlWMZwrM+kYr9+UYGy8cRvxO6a7iDVzlob9oFRvb7OT9zdRKUoS8fYIIC/onm/3JOEsSHK78sshK8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612407602428905.4211752730131; Wed, 3 Feb 2021 19:00:02 -0800 (PST) Received: from localhost ([::1]:39740 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7UsD-00017x-2Z for importer@patchew.org; Wed, 03 Feb 2021 22:00:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47286) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7Ttj-0001xb-Fw for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:57:35 -0500 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:38604) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tte-0007Gt-CL for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:57:31 -0500 Received: by mail-pg1-x52b.google.com with SMTP id o16so1053047pgg.5 for ; Wed, 03 Feb 2021 17:57:25 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id p15sm3610684pfn.172.2021.02.03.17.57.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:57:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lLuTVZMheh+w94V9lSybCso+88KsI23VfpQyYgw6vik=; b=T84PwoRa2Bfd4ZzTRRQ3ZFeC4XpI1P6LuRY8EnN4aIOOf2qKBaYY0z+QtuNgVhwDVO yfyhJ9DImz3JpcFpFuEIq2eoaPcUfME5SlswIPlsq0/AEg5wcAnttmeEuB6b7S7L9vq1 n3Cj8qGM6MMT5L9+VgWsGckLhv2Lk8F+P+XOJm0zmctJYSk5lhW0HXYri8kzswZRP/1v Cn08ZucRpt1QCPDrlHFN0MkYcnpKgUuS5YwdBCMhedsqcZxNaWku3zHZ/TZOt49OVZBT 0/8jRSEdReujHq6qtQHJcra5UXHJMDA5XQ6sUl/oxHOGvSGWABt1ObtXz/lnPerv5yrt 213Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lLuTVZMheh+w94V9lSybCso+88KsI23VfpQyYgw6vik=; b=Y2WgTBN0JWOrxdA+veGDK1mkMYpUT+lmqwOuTEma5i/LxY9+DF+K2VuiXjmQF1Nd29 M8iJQmxwfroopedPDvK0csXkFlBYyww++EaIp+nUP5VEOx0koehA0DCIEDVMXKc3z7pS z5Z59M0WPeMxCiWemmyj7Xj3uY9YnTpTyEbLKxQixH0j7wGR9OsUaO7sQ1k27oEw71VP ij3LlCwDlU9QF/DqZS2bctdN02lL7Rh2B76cDVxPFZhLL4F0kynnUOGR58gk07UVGWZU YmQI5mqZWdl4BjYre84D/2SFOSb57cN8OQBxd/kheHjh0oHI/em6Xv00PfO0UWd6SRl1 5Njw== X-Gm-Message-State: AOAM533tKs9fZjsfIFQAJKgBvzNRGr3yyfA4p2pmt+Sd13X+5zprGEaz SRy3ebFwpBQXgnh3j9YcxM5tYU+LYisYqaHi X-Google-Smtp-Source: ABdhPJxzODLJ1Xk9SMa+FBPDVWuSbMXq6naZ7Ul9flqcmE8yKAP3hlAp0ko92Q62xLXYGad9dNrb1g== X-Received: by 2002:a65:418b:: with SMTP id a11mr6528127pgq.231.1612403844972; Wed, 03 Feb 2021 17:57:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 88/93] tcg/tci: Implement movcond Date: Wed, 3 Feb 2021 15:57:21 -1000 Message-Id: <20210204015721.885711-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" When this opcode is not available in the backend, tcg middle-end will expand this as a series of 5 opcodes. So implementing this saves bytecode space. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 4 ++-- tcg/tci.c | 16 +++++++++++++++- tcg/tci/tcg-target.c.inc | 10 +++++++--- 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 17911d3297..f53773a555 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -82,7 +82,7 @@ #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_orc_i32 0 #define TCG_TARGET_HAS_rot_i32 1 -#define TCG_TARGET_HAS_movcond_i32 0 +#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 @@ -119,7 +119,7 @@ #define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_orc_i64 0 #define TCG_TARGET_HAS_rot_i64 1 -#define TCG_TARGET_HAS_movcond_i64 0 +#define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_add2_i32 0 #define TCG_TARGET_HAS_sub2_i32 0 diff --git a/tcg/tci.c b/tcg/tci.c index a6e30d31a9..2a39f8f5a0 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -169,6 +169,7 @@ static void tci_args_rrrr(uint32_t insn, *r2 =3D extract32(insn, 16, 4); *r3 =3D extract32(insn, 20, 4); } +#endif =20 static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) @@ -181,6 +182,7 @@ static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, = TCGReg *r1, *c5 =3D extract32(insn, 28, 4); } =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { @@ -431,6 +433,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] =3D tci_compare32(regs[r1], regs[r2], condition); break; + case INDEX_op_movcond_i32: + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); + tmp32 =3D tci_compare32(regs[r1], regs[r2], condition); + regs[r0] =3D regs[tmp32 ? r3 : r4]; + break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); @@ -443,6 +450,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] =3D tci_compare64(regs[r1], regs[r2], condition); break; + case INDEX_op_movcond_i64: + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); + tmp32 =3D tci_compare64(regs[r1], regs[r2], condition); + regs[r0] =3D regs[tmp32 ? r3 : r4]; + break; #endif CASE_32_64(mov) tci_args_rr(insn, &r0, &r1); @@ -1148,7 +1160,8 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) op_name, str_r(r0), str_r(r1), str_r(r2), pos, = len); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", @@ -1156,6 +1169,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) str_r(r3), str_r(r4), str_c(c)); break; =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_mulu2_i32: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index db29bc6e54..a0c458a60a 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -133,9 +133,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpco= de op) return C_O0_I4(r, r, r, r); case INDEX_op_mulu2_i32: return C_O2_I2(r, r, r, r); +#endif + + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: return C_O1_I4(r, r, r, r, r); -#endif =20 case INDEX_op_qemu_ld_i32: return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS @@ -419,6 +422,7 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, insn =3D deposit32(insn, 20, 4, r3); tcg_out32(s, insn); } +#endif =20 static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, @@ -436,6 +440,7 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode = op, tcg_out32(s, insn); } =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGReg r5) @@ -591,12 +596,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, tcg_out_op_rrrc(s, opc, args[0], args[1], args[2], args[3]); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 + CASE_32_64(movcond) case INDEX_op_setcond2_i32: tcg_out_op_rrrrrc(s, opc, args[0], args[1], args[2], args[3], args[4], args[5]); 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id s65sm3681085pfc.95.2021.02.03.17.57.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:57:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rhMhsBiepdz6ZgRnVQ9WJVuiU6dgvoZgG9ax0hIWeII=; b=dv0kRLdxnki77yl79jdX5C7LDWxj0itfIMxMUn0eY9MHaxJ+Dr/dYZThufsoEvZFoE ah4KL5oooiCeQ0u1/01G/zi52dJlJPRiQ1CG76Y60ar70ok+393+mvtPBaZACwZaPsEz LU15Mx06TZJAWYEF+uCfho0lf787NUZ9oyr/FzoGVESJG4t5bu37SEOLXuODOUXjAMHE 0MnG9+W7rfX8VanX7A7+f1MXuwQkg1eee1zIbq3hgMyuTI9sjibYPSdH9wlGD7WKSPcS YT7KaDGTrtEC2Ntg87ks/3AQ5MMXD/UutiT6obz7+MY+VhKGK9JIoQqe2PgV7ns+b7fy FxCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rhMhsBiepdz6ZgRnVQ9WJVuiU6dgvoZgG9ax0hIWeII=; b=fsxY/DYC0LvJTdIjSZ3G4y+My86hf2dueZNh1NGFa8vQgXNB51cYYuDL4dx9J5OokR I2xjAFaxKnrNPS5b2+pmcl+IePCddOnqXp1FKPAD5NrWgtGMlgGV1D64o4fao2qgwi44 oiSRNrVvw8BouqsvT1yTifYcfk8bJ7cSwzGUg75y3D+WL15kXQ4PYP7unOdmmAixKq2o a7RBYdFJ6EV6T/nBf5VEFc5i4s9hbvpbEASeNahXI3knXIFsFOUPUJvEiV196m7VUbVv +XnIP2XU0NcTbwULMFxBnKChOCq49F+N7PhUzaJSR8lpX7znashCM7NTzYSQJyQ4clvX 9x1g== X-Gm-Message-State: AOAM533pUUgckQGkmT+r9rIoLAcqG8GgN9Ynr+CtFeCJuD5i2yV3ZJU4 d9StCUFX4Jr7rOR+tRb6CaqGt/YT+RYragl0 X-Google-Smtp-Source: ABdhPJyw+1+6vfpHmtjXjey676Ug8pZ+ceyBMzp4wORGURMN6ELajWbqVnP8T2fH3stZzMaxmVsoIg== X-Received: by 2002:a62:5505:0:b029:1c9:2c59:b1ff with SMTP id j5-20020a6255050000b02901c92c59b1ffmr5553008pfb.69.1612403863656; Wed, 03 Feb 2021 17:57:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 89/93] tcg/tci: Implement andc, orc, eqv, nand, nor Date: Wed, 3 Feb 2021 15:57:40 -1000 Message-Id: <20210204015740.885763-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These were already present in tcg-target.c.inc, but not in the interpreter. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 20 ++++++++++---------- tcg/tci.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 10 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index f53773a555..5945272a43 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -67,20 +67,20 @@ #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 #define TCG_TARGET_HAS_ext16u_i32 1 -#define TCG_TARGET_HAS_andc_i32 0 +#define TCG_TARGET_HAS_andc_i32 1 #define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_extract_i32 0 #define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_extract2_i32 0 -#define TCG_TARGET_HAS_eqv_i32 0 -#define TCG_TARGET_HAS_nand_i32 0 -#define TCG_TARGET_HAS_nor_i32 0 +#define TCG_TARGET_HAS_eqv_i32 1 +#define TCG_TARGET_HAS_nand_i32 1 +#define TCG_TARGET_HAS_nor_i32 1 #define TCG_TARGET_HAS_clz_i32 0 #define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_ctpop_i32 0 #define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_not_i32 1 -#define TCG_TARGET_HAS_orc_i32 0 +#define TCG_TARGET_HAS_orc_i32 1 #define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_muls2_i32 0 @@ -108,16 +108,16 @@ #define TCG_TARGET_HAS_ext8u_i64 1 #define TCG_TARGET_HAS_ext16u_i64 1 #define TCG_TARGET_HAS_ext32u_i64 1 -#define TCG_TARGET_HAS_andc_i64 0 -#define TCG_TARGET_HAS_eqv_i64 0 -#define TCG_TARGET_HAS_nand_i64 0 -#define TCG_TARGET_HAS_nor_i64 0 +#define TCG_TARGET_HAS_andc_i64 1 +#define TCG_TARGET_HAS_eqv_i64 1 +#define TCG_TARGET_HAS_nand_i64 1 +#define TCG_TARGET_HAS_nor_i64 1 #define TCG_TARGET_HAS_clz_i64 0 #define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_ctpop_i64 0 #define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_not_i64 1 -#define TCG_TARGET_HAS_orc_i64 0 +#define TCG_TARGET_HAS_orc_i64 1 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_muls2_i64 0 diff --git a/tcg/tci.c b/tcg/tci.c index 2a39f8f5a0..9c17947e6b 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -540,6 +540,36 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] ^ regs[r2]; break; +#if TCG_TARGET_HAS_andc_i32 || TCG_TARGET_HAS_andc_i64 + CASE_32_64(andc) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] & ~regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_orc_i32 || TCG_TARGET_HAS_orc_i64 + CASE_32_64(orc) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] | ~regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64 + CASE_32_64(eqv) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D ~(regs[r1] ^ regs[r2]); + break; +#endif +#if TCG_TARGET_HAS_nand_i32 || TCG_TARGET_HAS_nand_i64 + CASE_32_64(nand) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D ~(regs[r1] & regs[r2]); + break; +#endif +#if TCG_TARGET_HAS_nor_i32 || TCG_TARGET_HAS_nor_i64 + CASE_32_64(nor) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D ~(regs[r1] | regs[r2]); + break; +#endif =20 /* Arithmetic operations (32 bit). */ =20 @@ -1130,6 +1160,16 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + case INDEX_op_eqv_i32: + case INDEX_op_eqv_i64: + case INDEX_op_nand_i32: + case INDEX_op_nand_i64: + case INDEX_op_nor_i32: + case INDEX_op_nor_i64: case INDEX_op_div_i32: case INDEX_op_div_i64: case INDEX_op_rem_i32: --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 8 ++++---- tcg/tci.c | 42 ++++++++++++++++++++++++++++++++++++++++ tcg/tci/tcg-target.c.inc | 32 ++++++++++++++++++++++++++++++ 3 files changed, 78 insertions(+), 4 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 5945272a43..60b67b196b 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -69,8 +69,8 @@ #define TCG_TARGET_HAS_ext16u_i32 1 #define TCG_TARGET_HAS_andc_i32 1 #define TCG_TARGET_HAS_deposit_i32 1 -#define TCG_TARGET_HAS_extract_i32 0 -#define TCG_TARGET_HAS_sextract_i32 0 +#define TCG_TARGET_HAS_extract_i32 1 +#define TCG_TARGET_HAS_sextract_i32 1 #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_eqv_i32 1 #define TCG_TARGET_HAS_nand_i32 1 @@ -97,8 +97,8 @@ #define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_deposit_i64 1 -#define TCG_TARGET_HAS_extract_i64 0 -#define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_extract_i64 1 +#define TCG_TARGET_HAS_sextract_i64 1 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_rem_i64 1 diff --git a/tcg/tci.c b/tcg/tci.c index 9c17947e6b..831a3bb97e 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -122,6 +122,15 @@ static void tci_args_rrs(uint32_t insn, TCGReg *r0, TC= GReg *r1, int32_t *i2) *i2 =3D sextract32(insn, 16, 16); } =20 +static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, + uint8_t *i2, uint8_t *i3) +{ + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *i2 =3D extract32(insn, 16, 6); + *i3 =3D extract32(insn, 22, 6); +} + static void tci_args_rrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { @@ -619,6 +628,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] =3D deposit32(regs[r1], pos, len, regs[r2]); break; +#endif +#if TCG_TARGET_HAS_extract_i32 + case INDEX_op_extract_i32: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] =3D extract32(regs[r1], pos, len); + break; +#endif +#if TCG_TARGET_HAS_sextract_i32 + case INDEX_op_sextract_i32: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] =3D sextract32(regs[r1], pos, len); + break; #endif case INDEX_op_brcond_i32: tci_args_rl(insn, tb_ptr, &r0, &ptr); @@ -759,6 +780,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] =3D deposit64(regs[r1], pos, len, regs[r2]); break; +#endif +#if TCG_TARGET_HAS_extract_i64 + case INDEX_op_extract_i64: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] =3D extract64(regs[r1], pos, len); + break; +#endif +#if TCG_TARGET_HAS_sextract_i64 + case INDEX_op_sextract_i64: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] =3D sextract64(regs[r1], pos, len); + break; #endif case INDEX_op_brcond_i64: tci_args_rl(insn, tb_ptr, &r0, &ptr); @@ -1200,6 +1233,15 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) op_name, str_r(r0), str_r(r1), str_r(r2), pos, = len); break; =20 + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + case INDEX_op_sextract_i32: + case INDEX_op_sextract_i64: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + info->fprintf_func(info->stream, "%-12s %s,%s,%d,%d", + op_name, str_r(r0), str_r(r1), pos, len); + break; + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index a0c458a60a..cedd0328df 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -63,6 +63,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode= op) case INDEX_op_bswap32_i32: case INDEX_op_bswap32_i64: case INDEX_op_bswap64_i64: + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + case INDEX_op_sextract_i32: + case INDEX_op_sextract_i64: return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: @@ -352,6 +356,21 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, tcg_out32(s, insn); } =20 +static void tcg_out_op_rrbb(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, uint8_t b2, uint8_t b3) +{ + tcg_insn_unit insn =3D 0; + + tcg_debug_assert(b2 =3D=3D extract32(b2, 0, 6)); + tcg_debug_assert(b3 =3D=3D extract32(b3, 0, 6)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 6, b2); + insn =3D deposit32(insn, 22, 6, b3); + tcg_out32(s, insn); +} + static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { @@ -653,6 +672,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c= onst TCGArg *args, } break; =20 + CASE_32_64(extract) /* Optional (TCG_TARGET_HAS_extract_*). */ + CASE_32_64(sextract) /* Optional (TCG_TARGET_HAS_sextract_*). */ + { + TCGArg pos =3D args[2], len =3D args[3]; + TCGArg max =3D tcg_op_defs[opc].flags & TCG_OPF_64BIT ? 64 : 3= 2; + + tcg_debug_assert(pos < max); + tcg_debug_assert(pos + len <=3D max); + + tcg_out_op_rrbb(s, opc, args[0], args[1], pos, len); + } + break; + CASE_32_64(brcond) tcg_out_op_rrrc(s, (opc =3D=3D INDEX_op_brcond_i32 ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 12 +++++------ tcg/tci.c | 44 ++++++++++++++++++++++++++++++++++++++++ tcg/tci/tcg-target.c.inc | 9 ++++++++ 3 files changed, 59 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 60b67b196b..59859bd8a6 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -75,9 +75,9 @@ #define TCG_TARGET_HAS_eqv_i32 1 #define TCG_TARGET_HAS_nand_i32 1 #define TCG_TARGET_HAS_nor_i32 1 -#define TCG_TARGET_HAS_clz_i32 0 -#define TCG_TARGET_HAS_ctz_i32 0 -#define TCG_TARGET_HAS_ctpop_i32 0 +#define TCG_TARGET_HAS_clz_i32 1 +#define TCG_TARGET_HAS_ctz_i32 1 +#define TCG_TARGET_HAS_ctpop_i32 1 #define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_orc_i32 1 @@ -112,9 +112,9 @@ #define TCG_TARGET_HAS_eqv_i64 1 #define TCG_TARGET_HAS_nand_i64 1 #define TCG_TARGET_HAS_nor_i64 1 -#define TCG_TARGET_HAS_clz_i64 0 -#define TCG_TARGET_HAS_ctz_i64 0 -#define TCG_TARGET_HAS_ctpop_i64 0 +#define TCG_TARGET_HAS_clz_i64 1 +#define TCG_TARGET_HAS_ctz_i64 1 +#define TCG_TARGET_HAS_ctpop_i64 1 #define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_orc_i64 1 diff --git a/tcg/tci.c b/tcg/tci.c index 831a3bb97e..35f2c4bfbb 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -598,6 +598,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint32_t)regs[r1] % (uint32_t)regs[r2]; break; +#if TCG_TARGET_HAS_clz_i32 + case INDEX_op_clz_i32: + tci_args_rrr(insn, &r0, &r1, &r2); + tmp32 =3D regs[r1]; + regs[r0] =3D tmp32 ? clz32(tmp32) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctz_i32 + case INDEX_op_ctz_i32: + tci_args_rrr(insn, &r0, &r1, &r2); + tmp32 =3D regs[r1]; + regs[r0] =3D tmp32 ? ctz32(tmp32) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctpop_i32 + case INDEX_op_ctpop_i32: + tci_args_rr(insn, &r0, &r1); + regs[r0] =3D ctpop32(regs[r1]); + break; +#endif =20 /* Shift/rotate operations (32 bit). */ =20 @@ -750,6 +770,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint64_t)regs[r1] % (uint64_t)regs[r2]; break; +#if TCG_TARGET_HAS_clz_i64 + case INDEX_op_clz_i64: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] ? clz64(regs[r1]) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctz_i64 + case INDEX_op_ctz_i64: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] ? ctz64(regs[r1]) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctpop_i64 + case INDEX_op_ctpop_i64: + tci_args_rr(insn, &r0, &r1); + regs[r0] =3D ctpop64(regs[r1]); + break; +#endif =20 /* Shift/rotate operations (64 bit). */ =20 @@ -1176,6 +1214,8 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) case INDEX_op_not_i64: case INDEX_op_neg_i32: case INDEX_op_neg_i64: + case INDEX_op_ctpop_i32: + case INDEX_op_ctpop_i64: tci_args_rr(insn, &r0, &r1); info->fprintf_func(info->stream, "%-12s %s,%s", op_name, str_r(r0), str_r(r1)); @@ -1221,6 +1261,10 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: + case INDEX_op_clz_i32: + case INDEX_op_clz_i64: + case INDEX_op_ctz_i32: + case INDEX_op_ctz_i64: tci_args_rrr(insn, &r0, &r1, &r2); info->fprintf_func(info->stream, "%-12s %s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2)); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index cedd0328df..664d715440 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -67,6 +67,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode = op) case INDEX_op_extract_i64: case INDEX_op_sextract_i32: case INDEX_op_sextract_i64: + case INDEX_op_ctpop_i32: + case INDEX_op_ctpop_i64: return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: @@ -122,6 +124,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpco= de op) case INDEX_op_setcond_i64: case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: + case INDEX_op_clz_i32: + case INDEX_op_clz_i64: + case INDEX_op_ctz_i32: + case INDEX_op_ctz_i64: return C_O1_I2(r, r, r); =20 case INDEX_op_brcond_i32: @@ -657,6 +663,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(clz) /* Optional (TCG_TARGET_HAS_clz_*). */ + CASE_32_64(ctz) /* Optional (TCG_TARGET_HAS_ctz_*). */ tcg_out_op_rrr(s, opc, args[0], args[1], args[2]); break; =20 @@ -705,6 +713,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ + CASE_32_64(ctpop) /* Optional (TCG_TARGET_HAS_ctpop_*). */ tcg_out_op_rr(s, opc, args[0], args[1]); break; =20 --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612407820; cv=none; d=zohomail.com; s=zohoarc; b=KJvghmtzIKp1V6IopCbqju5rMbQJ6GQpWdGIu7TLmSM0FiH1XmHcAmoyNo7Z8gLONm5W8iw928izhv5iH4UIW70ngYYBmKtTCzrl2Vyb0CfHsLUkGDLtb8b80QMGqKRcoAqD94VWldg7P/RsffTorz/VaNsiZOhrqA/DoY+zVSI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612407820; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=K7frB2t4HRQY2QCd4vmgctpTB+qUKaU+sWJuOgxV4RM=; b=Wf3VjxYZip94E0Pl2KIF0wrhR95nx+rL1e4nvwXDmdZWwMAga16oTPOGKT5XNg1G5S56Sl1PNU5szh+JRS395CVTXR244s/jRSHfnDCEGwskm51E6iU6/nrm7m9tHrjUSYiZWeYnoXdRcM/jCLQ+gscXkrRlAgHXXoc2XyjmAUo= ARC-Authentication-Results: i=1; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id x17sm3562973pff.180.2021.02.03.17.58.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:58:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=K7frB2t4HRQY2QCd4vmgctpTB+qUKaU+sWJuOgxV4RM=; b=L3peDv4H7aEltwWOcPCZ8688ephTfrKHliYyspBi2HozLSZ6Em/Pje8JSVzMXqZlt9 riTF+c1w7ROp1fGEV4ITqXTONZXsm4p+2DWUMNsb8YKV8u6TmEbDTXFJ01ouGFIJdSvL RFrhAgMjFeNXO7xvyq54aDtya1dVVTj4CRRBT/hOqer0IwOH39D4R6T5Ec9v8IyBWati OIRG/RQ1L2PIUa0SFhUVzFXggQOwnleyYvjzxHbzxNoYvJ76ZN+4tWQ6gbu8odJJSEgg 5FM+N00GP7oFtCmBtXKd6JnqlzCfvQRYCvGKgoDUwyCfUnJNmjVKoUVZ2RTFRO254JYi unqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K7frB2t4HRQY2QCd4vmgctpTB+qUKaU+sWJuOgxV4RM=; b=e61ajFuXPr5+dpskVxbw1KGTUWqcsJSl+PSPny7Gz1PurKce8SafQ2aYut20J5zTpt d9Hgoc3rruHejeGUS/LfdDgpppexVqey6ooaQtBzqzyaLfo6ZgjW+Anl1DF2uv3RkvN1 85Wqtfj85mnRDt83yLawE0tpa+EfQm3VU5NLzB6S28l59UqnYgQyrACftUxHM1LRhhfq y5DI8YKiMQ18lknbkG2WSHO5J7znaChCTu+tz/SRHzEjVUpw3S0J2F5u6zU53+qB36nH /Am0e/fcYBD2Q6ZxYO5MKweBWnD8qwj3frzM6vCDouAg+WgdV1ydYjypH/bSJBahc1Dc Od4A== X-Gm-Message-State: AOAM530IW1Gttmbz/IeGA3KNDZ1Fc3dzJ5+ET9nuSqzLHz/cfPFkGI2s b3GmwvSoPMblQeOo1yhYo1ze79ntsoCpQPMa X-Google-Smtp-Source: ABdhPJxdtT2blUegOZo2LUHx6Zqfy9wTE1TOuU13jH7eeV2SHkzrcYI1amSGtkA93hysca86G2w/Uw== X-Received: by 2002:a63:d143:: with SMTP id c3mr6826866pgj.86.1612403919564; Wed, 03 Feb 2021 17:58:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 92/93] tcg/tci: Implement mulu2, muls2 Date: Wed, 3 Feb 2021 15:58:36 -1000 Message-Id: <20210204015836.885930-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We already had mulu2_i32 for a 32-bit host; expand this to 64-bit hosts as well. The muls2_i32 and the 64-bit opcodes are new. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 8 ++++---- tcg/tci.c | 35 +++++++++++++++++++++++++++++------ tcg/tci/tcg-target.c.inc | 16 ++++++++++------ 3 files changed, 43 insertions(+), 16 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 59859bd8a6..71a44bbfb0 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -83,7 +83,7 @@ #define TCG_TARGET_HAS_orc_i32 1 #define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 -#define TCG_TARGET_HAS_muls2_i32 0 +#define TCG_TARGET_HAS_muls2_i32 1 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 @@ -120,13 +120,13 @@ #define TCG_TARGET_HAS_orc_i64 1 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 -#define TCG_TARGET_HAS_muls2_i64 0 +#define TCG_TARGET_HAS_muls2_i64 1 #define TCG_TARGET_HAS_add2_i32 0 #define TCG_TARGET_HAS_sub2_i32 0 -#define TCG_TARGET_HAS_mulu2_i32 0 +#define TCG_TARGET_HAS_mulu2_i32 1 #define TCG_TARGET_HAS_add2_i64 0 #define TCG_TARGET_HAS_sub2_i64 0 -#define TCG_TARGET_HAS_mulu2_i64 0 +#define TCG_TARGET_HAS_mulu2_i64 1 #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 #else diff --git a/tcg/tci.c b/tcg/tci.c index 35f2c4bfbb..5d83b2d957 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -39,7 +39,7 @@ __thread uintptr_t tci_tb_ptr; static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, uint32_t low_index, uint64_t value) { - regs[low_index] =3D value; + regs[low_index] =3D (uint32_t)value; regs[high_index] =3D value >> 32; } =20 @@ -169,7 +169,6 @@ static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, T= CGReg *r1, *r4 =3D extract32(insn, 24, 4); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) { @@ -178,7 +177,6 @@ static void tci_args_rrrr(uint32_t insn, *r2 =3D extract32(insn, 16, 4); *r3 =3D extract32(insn, 20, 4); } -#endif =20 static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) @@ -680,11 +678,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, T2 =3D tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; +#endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ +#if TCG_TARGET_HAS_mulu2_i32 case INDEX_op_mulu2_i32: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); - tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); + tmp64 =3D (uint64_t)(uint32_t)regs[r2] * (uint32_t)regs[r3]; + tci_write_reg64(regs, r1, r0, tmp64); break; -#endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ +#endif +#if TCG_TARGET_HAS_muls2_i32 + case INDEX_op_muls2_i32: + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); + tmp64 =3D (int64_t)(int32_t)regs[r2] * (int32_t)regs[r3]; + tci_write_reg64(regs, r1, r0, tmp64); + break; +#endif #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) tci_args_rr(insn, &r0, &r1); @@ -788,6 +796,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, regs[r0] =3D ctpop64(regs[r1]); break; #endif +#if TCG_TARGET_HAS_mulu2_i64 + case INDEX_op_mulu2_i64: + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); + mulu64(®s[r0], ®s[r1], regs[r2], regs[r3]); + break; +#endif +#if TCG_TARGET_HAS_muls2_i64 + case INDEX_op_muls2_i64: + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); + muls64(®s[r0], ®s[r1], regs[r2], regs[r3]); + break; +#endif =20 /* Shift/rotate operations (64 bit). */ =20 @@ -1295,14 +1315,17 @@ int print_insn_tci(bfd_vma addr, disassemble_info *= info) str_r(r3), str_r(r4), str_c(c)); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_mulu2_i32: + case INDEX_op_mulu2_i64: + case INDEX_op_muls2_i32: + case INDEX_op_muls2_i64: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3)); break; =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 664d715440..eb48633fba 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -141,10 +141,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) return C_O2_I4(r, r, r, r, r, r); case INDEX_op_brcond2_i32: return C_O0_I4(r, r, r, r); - case INDEX_op_mulu2_i32: - return C_O2_I2(r, r, r, r); #endif =20 + case INDEX_op_mulu2_i32: + case INDEX_op_mulu2_i64: + case INDEX_op_muls2_i32: + case INDEX_op_muls2_i64: + return C_O2_I2(r, r, r, r); + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: @@ -434,7 +438,6 @@ static void tcg_out_op_rrrrr(TCGContext *s, TCGOpcode o= p, TCGReg r0, tcg_out32(s, insn); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) { @@ -447,7 +450,6 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, insn =3D deposit32(insn, 20, 4, r3); tcg_out32(s, insn); } -#endif =20 static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, @@ -728,10 +730,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, args[0], args[1], args[2], args[3], args[4]); tcg_out_op_rl(s, INDEX_op_brcond_i32, TCG_REG_TMP, arg_label(args[= 5])); break; - case INDEX_op_mulu2_i32: +#endif + + CASE_32_64(mulu2) + CASE_32_64(muls2) tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); break; -#endif =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_st_i32: --=20 2.25.1 From nobody Wed May 15 21:48:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id s11sm3513983pfu.69.2021.02.03.17.58.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:58:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ykwqi1nfU63kykOjWC2hHHptQCv8OjjZ7CWKjmVZrJc=; b=EyzgyV3qoF5b5CYIQbmuLD93bPKuzXNeVS3xOXCQkn1Xi+3YzhOuXKKNTfvZgoPy+a mXC9QfyU4zQRnUMj3KQOAJx6BsIken6AheLLg9D36E+1k0orSvPqBgBWEFxCPZH73JVR z3wjFHq69iC/rjM3s9cKNvCEqAvRL6XzMg40qJL1Ebje3CGgWpG8wCY26p15jxuB8enU /wGVyijULMPE8ZcQ2dMJ5mTykiFggdSw8ETboSk3sUWw2B7LyitXO3c2iQqDf8uCMkJO eBbXsKlL7K9kAe8oeVgeZmBUsr1Wk1VytEBM9boYHRjBenZpaSeKgVrdLVGdkT+9GsIi EK5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ykwqi1nfU63kykOjWC2hHHptQCv8OjjZ7CWKjmVZrJc=; b=sGx5vTfeZkLcWFIC1qizfOcODlt7ZMPdqhEnQD9Fyv5wkdG3zvjRLj4MXa6/Z5ZG/Q 9G5eent5K9Q7PXa0j9rGW5kjwKoIo24QWr931Mj1O22A6UeDyThsCO+C/dYgilGRDgFD g82qBBGbvqHS9QYC3qYQUWXhRJJCFizAajwGFAJWVJse5gKST1yp4YYvgrzjUJbhSKyd ivpLgYPd2hpQkEWBQBN8oPLnWEooEtY+FiApgTelhDTZEph12SStQ+i+Y/IrgKbOOyun ttqhjGVA5YkjZj1CmoRcBIBgtmnvD9yVsKTcvLNO7zr2hcRmtQIfdaVeMiKuJflYorAf O9JA== X-Gm-Message-State: AOAM531WBeJUiHt36fDvLaYqEAetnxWAIc4Gt1f8u2as25VKStpoYb6D xNvyOcv+3Ml8cutmv84lvpM+dQjAZjc8M2ju X-Google-Smtp-Source: ABdhPJymWHRHGarZl6iTnqC0OJgLdttaKme0esncyGbADfPHz0XI8ruYwd0eZ8Cph5f9mhF0NmDY7A== X-Received: by 2002:a63:f404:: with SMTP id g4mr6581708pgi.114.1612403938056; Wed, 03 Feb 2021 17:58:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 93/93] tcg/tci: Implement add2, sub2 Date: Wed, 3 Feb 2021 15:58:55 -1000 Message-Id: <20210204015855.885981-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We already had the 32-bit versions for a 32-bit host; expand this to 64-bit hosts as well. The 64-bit opcodes are new. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 8 ++++---- tcg/tci.c | 40 ++++++++++++++++++++++++++-------------- tcg/tci/tcg-target.c.inc | 15 ++++++++------- 3 files changed, 38 insertions(+), 25 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 71a44bbfb0..515b3c7a56 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -121,11 +121,11 @@ #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_muls2_i64 1 -#define TCG_TARGET_HAS_add2_i32 0 -#define TCG_TARGET_HAS_sub2_i32 0 +#define TCG_TARGET_HAS_add2_i32 1 +#define TCG_TARGET_HAS_sub2_i32 1 #define TCG_TARGET_HAS_mulu2_i32 1 -#define TCG_TARGET_HAS_add2_i64 0 -#define TCG_TARGET_HAS_sub2_i64 0 +#define TCG_TARGET_HAS_add2_i64 1 +#define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_mulu2_i64 1 #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 diff --git a/tcg/tci.c b/tcg/tci.c index 5d83b2d957..ee16142f48 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -189,7 +189,6 @@ static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, = TCGReg *r1, *c5 =3D extract32(insn, 28, 4); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { @@ -200,7 +199,6 @@ static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, = TCGReg *r1, *r4 =3D extract32(insn, 24, 4); *r5 =3D extract32(insn, 28, 4); } -#endif =20 static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { @@ -368,17 +366,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, for (;;) { uint32_t insn; TCGOpcode opc; - TCGReg r0, r1, r2, r3, r4; + TCGReg r0, r1, r2, r3, r4, r5; tcg_target_ulong t1; TCGCond condition; target_ulong taddr; uint8_t pos, len; uint32_t tmp32; uint64_t tmp64; -#if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r5; uint64_t T1, T2; -#endif TCGMemOpIdx oi; int32_t ofs; void *ptr; @@ -665,20 +660,22 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, tb_ptr =3D ptr; } break; -#if TCG_TARGET_REG_BITS =3D=3D 32 +#if TCG_TARGET_REG_BITS =3D=3D 32 || TCG_TARGET_HAS_add2_i32 case INDEX_op_add2_i32: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 =3D tci_uint64(regs[r3], regs[r2]); T2 =3D tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 + T2); break; +#endif +#if TCG_TARGET_REG_BITS =3D=3D 32 || TCG_TARGET_HAS_sub2_i32 case INDEX_op_sub2_i32: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 =3D tci_uint64(regs[r3], regs[r2]); T2 =3D tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; -#endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ +#endif #if TCG_TARGET_HAS_mulu2_i32 case INDEX_op_mulu2_i32: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); @@ -808,6 +805,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, muls64(®s[r0], ®s[r1], regs[r2], regs[r3]); break; #endif +#if TCG_TARGET_HAS_add2_i64 + case INDEX_op_add2_i64: + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); + T1 =3D regs[r2] + regs[r4]; + T2 =3D regs[r3] + regs[r5] + (T1 < regs[r2]); + regs[r0] =3D T1; + regs[r1] =3D T2; + break; +#endif +#if TCG_TARGET_HAS_add2_i64 + case INDEX_op_sub2_i64: + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); + T1 =3D regs[r2] - regs[r4]; + T2 =3D regs[r3] - regs[r5] - (regs[r2] < regs[r4]); + regs[r0] =3D T1; + regs[r1] =3D T2; + break; +#endif =20 /* Shift/rotate operations (64 bit). */ =20 @@ -1124,10 +1139,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) const char *op_name; uint32_t insn; TCGOpcode op; - TCGReg r0, r1, r2, r3, r4; -#if TCG_TARGET_REG_BITS =3D=3D 32 - TCGReg r5; -#endif + TCGReg r0, r1, r2, r3, r4, r5; tcg_target_ulong i1; int32_t s2; TCGCond c; @@ -1325,15 +1337,15 @@ int print_insn_tci(bfd_vma addr, disassemble_info *= info) str_r(r2), str_r(r3)); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_add2_i32: + case INDEX_op_add2_i64: case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3), str_r(r4), str_r(r5)); break; -#endif =20 case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index eb48633fba..9b2e2c32a1 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -134,11 +134,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_brcond_i64: return C_O0_I2(r, r); =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 - /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */ case INDEX_op_add2_i32: + case INDEX_op_add2_i64: case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: return C_O2_I4(r, r, r, r, r, r); + +#if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_brcond2_i32: return C_O0_I4(r, r, r, r); #endif @@ -467,7 +469,6 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode = op, tcg_out32(s, insn); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGReg r5) @@ -483,7 +484,6 @@ static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode = op, insn =3D deposit32(insn, 28, 4, r5); tcg_out32(s, insn); } -#endif =20 static void tcg_out_ldst(TCGContext *s, TCGOpcode op, TCGReg val, TCGReg base, intptr_t offset) @@ -719,12 +719,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, = const TCGArg *args, tcg_out_op_rr(s, opc, args[0], args[1]); break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 - case INDEX_op_add2_i32: - case INDEX_op_sub2_i32: + CASE_32_64(add2) + CASE_32_64(sub2) tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2], args[3], args[4], args[5]); break; + +#if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_brcond2_i32: tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, TCG_REG_TMP, args[0], args[1], args[2], args[3], args[4]); --=20 2.25.1