From nobody Fri May 17 13:37:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1612372087; cv=none; d=zohomail.com; s=zohoarc; b=oA5w1DLT3TccHVG1/5ursxYysEj0rgfSKBtR64JdGnDO2jVA7ZDQZguy2STEALkqtW7DLNTIl8bJGt19MPX04zKLjbB7xdp9y7f79b68K/V0DhT3UeGfCETKSmHPidYbzEPbadCpq748NrWLTDRrDS71g3LgNj3ac7oy/FrWRRU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612372087; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=AZlrT42e82kcT/iAmGBEbWchNqzK9+FvZAd3dN4LTLY=; b=jcuAxs4ZgCUn9zWQWBfNHUesoS9n9tu7A7xegDtyNEsMs/Stvd94a7oDd12CNXvo2toBlfsiL7M2/vaBRBMI3nSBc4Qfuc+p1tHkcWqcMBnNKz8CdKjTXFJmY3FBpUJAtV9yqNOwklEo+xKZ+ggfWgQoQipFXiVfh05TU1UQ7QI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612372087706418.024830964188; Wed, 3 Feb 2021 09:08:07 -0800 (PST) Received: from localhost ([::1]:57404 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7LdN-0005G2-FW for importer@patchew.org; Wed, 03 Feb 2021 12:08:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60570) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7LS5-0004xD-An; Wed, 03 Feb 2021 11:56:26 -0500 Received: from unifiededge.gtri.gatech.edu ([130.207.205.170]:29222) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7LS2-00082b-Lq; Wed, 03 Feb 2021 11:56:24 -0500 Received: from tybee.core.gtri.org (10.41.1.49) by exedge06.gtri.dmz (10.41.104.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.2.721.2; Wed, 3 Feb 2021 11:56:20 -0500 Received: from localhost.localdomain (10.41.0.30) by tybee.core.gtri.org (10.41.1.49) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2106.2; Wed, 3 Feb 2021 11:56:19 -0500 Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; d=gtri.gatech.edu; s=unifiededge; c=simple/simple; t=1612371380; h=from:subject:to:date:message-id; bh=X2wnTu4NMcpKV+EZTbug/3AW40/hzSkCyt8FKBp28i8=; b=OoqbucPfEVYaWadrKJtfu6uNqHghv0HI9WBwwiIfOiKiKt665QkcXETN0VKD4zXxQpYdosFLuXl 4KSXGl4DWVVVsRMciogQtJqcLsFFbQtuhKRwdEOLAPe56BOaQyP7ALDh8IltgP7SxVX+HisRoY0vt ugmbUvbxieFQuKNYlzQizgSoz968MYHFWmjTWHL2CpC/Q8YgILurtoxMRnmUlNYrQVQVJ2JF5jKGB qvvydmZVDOZBrhiM7WWoVvzB0AzlFUyWZDV4mhSK2IAYRpXCAMCl29wOZ+yKRhwgW5AQm62FC7Uun vFAc9+lHMWXyZZxZAjUnyPKS2WmMGNeaGuHQ== To: Subject: [PATCH v2 1/1] target/arm: Fix SCR RES1 handling Date: Wed, 3 Feb 2021 11:55:52 -0500 Message-ID: <20210203165552.16306-2-michael.nawrocki@gtri.gatech.edu> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210203165552.16306-1-michael.nawrocki@gtri.gatech.edu> References: <20210203165552.16306-1-michael.nawrocki@gtri.gatech.edu> MIME-Version: 1.0 X-ClientProxiedBy: hatteras.core.gtri.org (10.41.22.72) To tybee.core.gtri.org (10.41.1.49) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=130.207.205.170; envelope-from=Michael.Nawrocki@gtri.gatech.edu; helo=unifiededge.gtri.gatech.edu X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, Mike Nawrocki Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Mike Nawrocki From: michael.nawrocki--- via X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The FW and AW bits of SCR_EL3 are RES1 only in some contexts. Force them to 1 only when there is no support for AArch32 at EL1 or above. The reset value will be 0x30 only if the CPU is AArch64-only; if there is support for AArch32 at EL1 or above, it will be reset to 0. Also adds helper function isar_feature_aa64_aa32_el1 to check if AArch32 is supported at EL1 or above. Signed-off-by: Mike Nawrocki Reviewed-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ target/arm/helper.c | 16 ++++++++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d080239863..39633f73f3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4033,6 +4033,11 @@ static inline bool isar_feature_aa64_aa32(const ARMI= SARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >=3D 2; } =20 +static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2; +} + static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 47e266d7e6..e529cdbfd0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2024,7 +2024,10 @@ static void scr_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) ARMCPU *cpu =3D env_archcpu(env); =20 if (ri->state =3D=3D ARM_CP_STATE_AA64) { - value |=3D SCR_FW | SCR_AW; /* these two bits are RES1. */ + if (arm_feature(env, ARM_FEATURE_AARCH64) && + !cpu_isar_feature(aa64_aa32_el1, cpu)) { + value |=3D SCR_FW | SCR_AW; /* these two bits are RES1. = */ + } valid_mask &=3D ~SCR_NET; =20 if (cpu_isar_feature(aa64_lor, cpu)) { @@ -2063,6 +2066,15 @@ static void scr_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) raw_write(env, ri, value); } =20 +static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* + * scr_write will set the RES1 bits on an AArch64-only CPU. + * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise. + */ + scr_write(env, ri, 0); +} + static CPAccessResult access_aa64_tid2(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -5785,7 +5797,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { { .name =3D "SCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.scr_= el3), - .resetvalue =3D 0, .writefn =3D scr_write }, + .resetfn =3D scr_reset, .writefn =3D scr_write }, { .name =3D "SCR", .type =3D ARM_CP_ALIAS | ARM_CP_NEWEL, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, --=20 2.20.1