From nobody Fri Dec 19 04:28:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1612289230; cv=none; d=zohomail.com; s=zohoarc; b=bYIbes4BK0BJCyoi33pM2SzpfEdts781KddwsViczt8jXLBvvoh0KNbuoArNHesJ8JabyYBhSe3XTuzynUD5QJQjGJ91iQ5PBiK7JPB0K202Cx5tY7CGCeoxO0A4XqQhWt7s1IdbUyDdBrV9r7Y6Tedc8j4eyCKYsEFbcYFDXFQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612289230; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8r7FNnpkrncdt3Og1knfFavndfs/SPtYUNjSL/xsxQA=; b=YnUFfFHkog0qt5QbQlFiKKBhCG1BAE2d/iV2wv9ccP+paFM2tyPKJG376kFvdIirYUTGcFSP+3Eqmp+HN43RPPSzZNrf2k+zW8x0ADE1feKA5MXB6OJEoAnl4brLu5FAfI3ayPgIA2CauNufSGyQ0wCYbpUuWnzcQyxtBM7Eooo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612289230432515.5281146877904; Tue, 2 Feb 2021 10:07:10 -0800 (PST) Received: from localhost ([::1]:33314 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l704y-00086U-V0 for importer@patchew.org; Tue, 02 Feb 2021 13:07:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45404) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6zts-0005Nf-5S for qemu-devel@nongnu.org; Tue, 02 Feb 2021 12:55:44 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:32997) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6zti-0002Fa-UC for qemu-devel@nongnu.org; Tue, 02 Feb 2021 12:55:38 -0500 Received: by mail-wr1-x433.google.com with SMTP id 7so21454214wrz.0 for ; Tue, 02 Feb 2021 09:55:25 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm4142283wmj.32.2021.02.02.09.55.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Feb 2021 09:55:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8r7FNnpkrncdt3Og1knfFavndfs/SPtYUNjSL/xsxQA=; b=z2hjqgCngx5vHvGpr0UODXdgSXXGPRap9MXKWZ1ObsvVKHob1JPM0uyY21j+YMBNpj j5AVliWAn3otqWGH1InSC0hvsUf+Ez2/taVhMkaslxzD5vNJZlJsVvWMx+yJ2AHli7Fp cQA+Y/fc12tIXegYs+zgmXCBqMAfxufzPCxIZe8d1DhEKEj+N+bANNLfaBzLPO6odfsP oYGRZEZzELoEcJeQ4oP+/fGOSth2L0WSoSeHFOBo0tEntVdMP4L3oFFCeB234W5BYtj0 /dq4NvySmr0hBveDbhoPM9uAfhlfldOtOGRJ7yeEzFjvYLFCv4H7L0wqlPzt86dEZMI7 J0YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8r7FNnpkrncdt3Og1knfFavndfs/SPtYUNjSL/xsxQA=; b=j4gr+b4iP7o4Bfr5rYpRxEVjF7k7VSGMllYbj7bdSzz6FXyTODPAR63cBlSIfTWz7M hz9s9NRoZKs3rRbfeKHnaATeIEpOOvq1Ll1GYZEi6FaWq2GeNNQZ4rw3PtEvPK6OlNjx o3NMUV9kEagGk4XoTcSj1jey3BedErwJp0EhUsPjGe8w00q3ltWj/7zRMaGWufMMPgLx /hbyiX9MLStaEn5bPhvEtWkrQOrUYjMr0YbEVoosuhq+5drk2uWn1wRrumw0eFSEwR6l Xs57Nv4H1ZlixqagWbGGaLj9a1hJyhZotzlzpwAOflZfEgx1a8d6Xd/iEFDvfRy8+FqV mW3g== X-Gm-Message-State: AOAM533OrPzCi4Y1uab9/PphGrMGFaFVJtLKyvpGyOlDBb/A0NLuZ9t4 BcX8JHCktgmVuiG97ZswvjfAGKSsKIzU3A== X-Google-Smtp-Source: ABdhPJy/s+NJdeUREBWgi0chBe+bPbQrvLa83i8YXs+5i42t2gger7O0x6Xy01GnZkOiAcDrS+Yvjg== X-Received: by 2002:a5d:6947:: with SMTP id r7mr24716975wrw.150.1612288524660; Tue, 02 Feb 2021 09:55:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/21] hw/ssi: imx_spi: Use a macro for number of chip selects supported Date: Tue, 2 Feb 2021 17:55:01 +0000 Message-Id: <20210202175517.28729-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210202175517.28729-1-peter.maydell@linaro.org> References: <20210202175517.28729-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Bin Meng Avoid using a magic number (4) everywhere for the number of chip selects supported. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Juan Quintela Message-id: 20210129132323.30946-2-bmeng.cn@gmail.com Signed-off-by: Peter Maydell --- include/hw/ssi/imx_spi.h | 5 ++++- hw/ssi/imx_spi.c | 4 ++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/hw/ssi/imx_spi.h b/include/hw/ssi/imx_spi.h index b82b17f3643..eeaf49bbac3 100644 --- a/include/hw/ssi/imx_spi.h +++ b/include/hw/ssi/imx_spi.h @@ -77,6 +77,9 @@ =20 #define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH) =20 +/* number of chip selects supported */ +#define ECSPI_NUM_CS 4 + #define TYPE_IMX_SPI "imx.spi" OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI) =20 @@ -89,7 +92,7 @@ struct IMXSPIState { =20 qemu_irq irq; =20 - qemu_irq cs_lines[4]; + qemu_irq cs_lines[ECSPI_NUM_CS]; =20 SSIBus *bus; =20 diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index d8885ae454e..e605049a213 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -361,7 +361,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, = uint64_t value, =20 /* We are in master mode */ =20 - for (i =3D 0; i < 4; i++) { + for (i =3D 0; i < ECSPI_NUM_CS; i++) { qemu_set_irq(s->cs_lines[i], i =3D=3D imx_spi_selected_channel(s) ? 0 : 1); } @@ -424,7 +424,7 @@ static void imx_spi_realize(DeviceState *dev, Error **e= rrp) sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); =20 - for (i =3D 0; i < 4; ++i) { + for (i =3D 0; i < ECSPI_NUM_CS; ++i) { sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } =20 --=20 2.20.1