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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm4142283wmj.32.2021.02.02.09.55.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Feb 2021 09:55:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=gdtHlIrMwoP0z47d98DhPSjo1F4nkYLQdfh3htMSjrQ=; b=vOqC/9B8jUykf+sWEebCVJ9gTxI7mAUTbmVJwuvSKsGN7/NT28JEgSBRxhbmz3XOua IfGqaoN+G/IOTdvKNGXOo7AM133kgFaI/YfOKlEszVHM9uqL1jbiwUSIJCAyaffu3GRp LhU5k6EcJUVvwoxDd71RquE+b5YBXWKRWAS22YFOWYyb9AdZtjX600Qt4Be972jKo94a Pk3dwZVNZTMTz5yZHJre4jtHNyE6YcgKtziG2qaiZBVqKzyUtGnsGwn1Zh2v8oXmyaCp HlTasuvkA2/vfDkejFB0Z+69EuDFKVLWpIjXAgRQ8aKbHUy1aZWJUEIAMZyXRPUw+Prg wzJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gdtHlIrMwoP0z47d98DhPSjo1F4nkYLQdfh3htMSjrQ=; b=BbHDAu4fYpGdobigVlZqz0BJj9YW7tkaNTiaMHZj0UKD6c8mdVFdQUb3JA70wi9Wd0 5f/nrQUvo6Bydh6ZkMnqszFk4aKilcQXTAuNoioa/s2XhGBfxgo469inYPkgqNW4fMEs im1vJmUR557qCQU9EsoXzN+3uV77wcJlSApsONKlovONpacvxlpCWqHcaznSuhbJju6c LC8OKBWTERSVLzcikY6SKpzAQGUaOjOY/XEc3Yn7zTSEKxls5rxIiNIwSjpRu3gjwCG9 vgoDcv25zOIIQIGfWXTXDbizJxKK0tQsZK/2wDjwfVPqlJT12lX3lthmUZwJZBO75mw9 Qf6w== X-Gm-Message-State: AOAM531XXnh0AMUZMiLkfI6H9bmKOwPyjNGR4h7fg2zO8StGG5mFr+Yx pZ6iQF7tAbnpxSE782TH/yAwKJLCf8zGvw== X-Google-Smtp-Source: ABdhPJzIDg+tqfNi88bXatjfuLgan0o7rWeJrc6KdiIrK+QN4bXnJ0HKPz1vKe4K1tSN0nslfBQxBQ== X-Received: by 2002:a1c:e255:: with SMTP id z82mr4604528wmg.93.1612288530812; Tue, 02 Feb 2021 09:55:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/21] hw/ssi: imx_spi: Disable chip selects when controller is disabled Date: Tue, 2 Feb 2021 17:55:07 +0000 Message-Id: <20210202175517.28729-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210202175517.28729-1-peter.maydell@linaro.org> References: <20210202175517.28729-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Xuzhou Cheng When a write to ECSPI_CONREG register to disable the SPI controller, imx_spi_soft_reset() is called to reset the controller, but chip select lines should have been disabled, otherwise the state machine of any devices (e.g.: SPI flashes) connected to the SPI master is stuck to its last state and responds incorrectly to any follow-up commands. Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210129132323.30946-8-bmeng.cn@gmail.com Signed-off-by: Peter Maydell --- hw/ssi/imx_spi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 4cfbb73e35e..2fb65498c3b 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -254,9 +254,15 @@ static void imx_spi_common_reset(IMXSPIState *s) =20 static void imx_spi_soft_reset(IMXSPIState *s) { + int i; + imx_spi_common_reset(s); =20 imx_spi_update_irq(s); + + for (i =3D 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } } =20 static void imx_spi_reset(DeviceState *dev) --=20 2.20.1