From nobody Mon Feb 9 21:19:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612228130; cv=none; d=zohomail.com; s=zohoarc; b=ETi+iWlz7th/666QDB/Kp0phoM99Izog8K4uydlqrn2Hh+anWDOIdCc+/1g8AWEdztyTWfqT4a0IInj434hL5abr025e8QUCHgGPsXTjeFDwhXD0YaKGuKsVhZZYoTgN4XmT3wymzHVv/9KYeNWZEfS/+NYRBxA//+dkAw5/EkE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612228130; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cfmiANCwZhMRsFIz41bMOcoBmkwpF/BF6txTZuUEHG8=; b=A96cOcu08a650yU7XEcAyW4+DlCbU7LQKdG8o1Iu2l1iy/zPDPiYLo1FI8+EhoioyaWq6q3AgR3IrJ8NEVfh3nzuHKtnCldaXjpbi9g252EYhYniA85TcIoxWtrquKVgui1Vb4435pwkWSRIcjmiGxL0fTQr+wNcnukaUi4GIhM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612228130836404.0283216632821; Mon, 1 Feb 2021 17:08:50 -0800 (PST) Received: from localhost ([::1]:58246 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6kBV-0000Ho-IS for importer@patchew.org; Mon, 01 Feb 2021 20:08:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47130) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k3C-0008Kb-Em for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:14 -0500 Received: from mga18.intel.com ([134.134.136.126]:33366) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k37-0001pl-7n for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:14 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 16:59:59 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 16:59:58 -0800 IronPort-SDR: OXNMgyiP7d7YxOErsq1tcbyVal1g7qJcYEdxIT9T0ysFrlX3Rz5lRPUjSWBB8dMFla0VK7DVPj 0Wh0qqIW6LFw== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457083" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457083" IronPort-SDR: 3VGnYAkJjEEgAa8923cebRlxcrHpnkefdI0AJFfWy06eMgzm70BfHLl4fdOfwVcLelQ0ycQN79 vJGY13dSm2JA== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764071" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 06/31] hw/cxl/device: Add memory device utilities Date: Mon, 1 Feb 2021 16:59:23 -0800 Message-Id: <20210202005948.241655-7-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Memory devices implement extra capabilities on top of CXL devices. This adds support for that. A large part of memory devices is the mailbox/command interface. All of the mailbox handling is done in the mailbox-utils library. Longer term, new CXL devices that are being emulated may want to handle commands differently, and therefore would need a mechanism to opt in/out of the specific generic handlers. As such, this is considered sufficient for now, but may need more depth in the future. Signed-off-by: Ben Widawsky --- hw/cxl/cxl-device-utils.c | 38 ++++++++++++++++++++++++++++++++++++- include/hw/cxl/cxl_device.h | 18 +++++++++++++++++- 2 files changed, 54 insertions(+), 2 deletions(-) diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c index 6602606f3d..639ace523d 100644 --- a/hw/cxl/cxl-device-utils.c +++ b/hw/cxl/cxl-device-utils.c @@ -130,6 +130,31 @@ static void mailbox_reg_write(void *opaque, hwaddr off= set, uint64_t value, cxl_process_mailbox(cxl_dstate); } =20 +static uint64_t mdev_reg_read(void *opaque, hwaddr offset, unsigned size) +{ + uint64_t retval =3D 0; + + retval =3D FIELD_DP64(retval, CXL_MEM_DEV_STS, MEDIA_STATUS, 1); + retval =3D FIELD_DP64(retval, CXL_MEM_DEV_STS, MBOX_READY, 1); + + return retval; +} + +static const MemoryRegionOps mdev_ops =3D { + .read =3D mdev_reg_read, + .write =3D NULL, /* memory device register is read only */ + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + .unaligned =3D false, + }, + .impl =3D { + .min_access_size =3D 8, + .max_access_size =3D 8, + }, +}; + static const MemoryRegionOps mailbox_ops =3D { .read =3D mailbox_reg_read, .write =3D mailbox_reg_write, @@ -187,6 +212,9 @@ void cxl_device_register_block_init(Object *obj, CXLDev= iceState *cxl_dstate) "device-status", CXL_DEVICE_REGISTERS_LENGTH); memory_region_init_io(&cxl_dstate->mailbox, obj, &mailbox_ops, cxl_dst= ate, "mailbox", CXL_MAILBOX_REGISTERS_LENGTH); + memory_region_init_io(&cxl_dstate->memory_device, obj, &mdev_ops, + cxl_dstate, "memory device caps", + CXL_MEMORY_DEVICE_REGISTERS_LENGTH); =20 memory_region_add_subregion(&cxl_dstate->device_registers, 0, &cxl_dstate->caps); @@ -196,6 +224,9 @@ void cxl_device_register_block_init(Object *obj, CXLDev= iceState *cxl_dstate) memory_region_add_subregion(&cxl_dstate->device_registers, CXL_MAILBOX_REGISTERS_OFFSET, &cxl_dstate->mailbox); + memory_region_add_subregion(&cxl_dstate->device_registers, + CXL_MEMORY_DEVICE_REGISTERS_OFFSET, + &cxl_dstate->memory_device); } =20 static void device_reg_init_common(CXLDeviceState *cxl_dstate) { } @@ -208,10 +239,12 @@ static void mailbox_reg_init_common(CXLDeviceState *c= xl_dstate) cxl_dstate->payload_size =3D CXL_MAILBOX_MAX_PAYLOAD_SIZE; } =20 +static void memdev_reg_init_common(CXLDeviceState *cxl_dstate) { } + void cxl_device_register_init_common(CXLDeviceState *cxl_dstate) { uint32_t *cap_hdrs =3D cxl_dstate->caps_reg_state32; - const int cap_count =3D 2; + const int cap_count =3D 3; =20 /* CXL Device Capabilities Array Register */ ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_ID, 0); @@ -224,5 +257,8 @@ void cxl_device_register_init_common(CXLDeviceState *cx= l_dstate) cxl_device_cap_init(cxl_dstate, MAILBOX, 2); mailbox_reg_init_common(cxl_dstate); =20 + cxl_device_cap_init(cxl_dstate, MEMORY_DEVICE, 0x4000); + memdev_reg_init_common(cxl_dstate); + assert(cxl_initialize_mailbox(cxl_dstate) =3D=3D 0); } diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index af91bec10c..0cc5354ba4 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -72,15 +72,20 @@ #define CXL_MAILBOX_REGISTERS_LENGTH \ (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE) =20 +#define CXL_MEMORY_DEVICE_REGISTERS_OFFSET \ + (CXL_MAILBOX_REGISTERS_OFFSET + CXL_MAILBOX_REGISTERS_LENGTH) +#define CXL_MEMORY_DEVICE_REGISTERS_LENGTH 0x8 + #define CXL_MMIO_SIZE \ CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_REGISTERS_LENGTH + \ - CXL_MAILBOX_REGISTERS_LENGTH + CXL_MAILBOX_REGISTERS_LENGTH + CXL_MEMORY_DEVICE_REGISTERS_LENGTH =20 typedef struct cxl_device_state { MemoryRegion device_registers; =20 /* mmio for device capabilities array - 8.2.8.2 */ MemoryRegion device; + MemoryRegion memory_device; struct { MemoryRegion caps; uint32_t caps_reg_state32[CXL_CAPS_SIZE / 4]; @@ -145,6 +150,9 @@ REG32(CXL_DEV_CAP_ARRAY2, 4) /* We're going to pretend = it's 64b */ CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE, CXL_DEVICE_CAP_HDR1_OFFSET) CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET = + \ CXL_DEVICE_CAP_REG_SIZE) +CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MEMORY_DEVICE, + CXL_DEVICE_CAP_HDR1_OFFSET + + CXL_DEVICE_CAP_REG_SIZE * 2) =20 int cxl_initialize_mailbox(CXLDeviceState *cxl_dstate); void cxl_process_mailbox(CXLDeviceState *cxl_dstate); @@ -197,4 +205,12 @@ REG32(CXL_DEV_BG_CMD_STS, 0x18) =20 REG32(CXL_DEV_CMD_PAYLOAD, 0x20) =20 +/* XXX: actually a 64b registers */ +REG32(CXL_MEM_DEV_STS, 0) + FIELD(CXL_MEM_DEV_STS, FATAL, 0, 1) + FIELD(CXL_MEM_DEV_STS, FW_HALT, 1, 1) + FIELD(CXL_MEM_DEV_STS, MEDIA_STATUS, 2, 2) + FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1) + FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3) + #endif --=20 2.30.0