From nobody Mon Feb 9 03:12:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612227743; cv=none; d=zohomail.com; s=zohoarc; b=kOhLh9c1XciJ1giOXWXifKLRPyBMC+R3kjs99DUWb6kkpu8mI39ZDMyb+s8bzeEnF2/yXOG07mA5bcgDl//t4O9TBcg/gGxuKcbCK8Nr1RmH29wpE/0iEWeLLqHDmsCsvKrJixMmAKOjl3jTgSVeSjjfVot5daylveNZJK5x+24= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612227743; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AXNy9UliYRNerU7loYyHDXKhVR+Se/7tUMV8dfqOQIc=; b=cnae9ynMT55lm7f3VKtOcbfIZnD6ogXFQjkkYzr1/Er5MNhgZmrG4++dUt2J6viJp6OeWVbHU9xhMsH1WmXx0s2UMm2lpa/cmlBLJPdZ9P+enPToVmfNDBzGrrbLEOEmwWLzSlPax0XbFXPBFwGbekNNnOoiPjZAlZTkVHCTo9I= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612227743079587.9057882220051; Mon, 1 Feb 2021 17:02:23 -0800 (PST) Received: from localhost ([::1]:40992 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6k5F-0001Qo-9I for importer@patchew.org; Mon, 01 Feb 2021 20:02:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k34-00087L-7A for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:06 -0500 Received: from mga18.intel.com ([134.134.136.126]:33363) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k2z-0001oo-Hd for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:05 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 16:59:54 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 16:59:53 -0800 IronPort-SDR: mHPHklThosMsouhLKukn0HSoaDZQ24s8Bjg4iOhOWHJFbXW/B3RZ0gF0Fi25kY7yxzraL3ANzd IpdKwfLWur7w== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457076" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457076" IronPort-SDR: ohOd2fvk0iUmqWddqrIq/4W+/dDXel0bsAoOQ5YfgKofVN26VvHWaa+ayyqy/y0LfJnaY21jk/ OVKY2JODiCnw== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764024" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 01/31] hw/pci/cxl: Add a CXL component type (interface) Date: Mon, 1 Feb 2021 16:59:18 -0800 Message-Id: <20210202005948.241655-2-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" A CXL component is a hardware entity that implements CXL component registers from the CXL 2.0 spec (8.2.3). Currently these represent 3 general types. 1. Host Bridge 2. Ports (root, upstream, downstream) 3. Devices (memory, other) A CXL component can be conceptually thought of as a PCIe device with extra functionality when enumerated and enabled. For this reason, CXL does here, and will continue to add on to existing PCI code paths. Host bridges will typically need to be handled specially and so they can implement this newly introduced interface or not. All other components should implement this interface. Implementing this interface allows the core pci code to treat these devices as special where appropriate. Signed-off-by: Ben Widawsky --- hw/pci/pci.c | 10 ++++++++++ include/hw/pci/pci.h | 8 ++++++++ 2 files changed, 18 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 512e9042ff..a45ca326ed 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -194,6 +194,11 @@ static const TypeInfo pci_bus_info =3D { .class_init =3D pci_bus_class_init, }; =20 +static const TypeInfo cxl_interface_info =3D { + .name =3D INTERFACE_CXL_DEVICE, + .parent =3D TYPE_INTERFACE, +}; + static const TypeInfo pcie_interface_info =3D { .name =3D INTERFACE_PCIE_DEVICE, .parent =3D TYPE_INTERFACE, @@ -2091,6 +2096,10 @@ static void pci_qdev_realize(DeviceState *qdev, Erro= r **errp) pci_dev->cap_present |=3D QEMU_PCI_CAP_EXPRESS; } =20 + if (object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE)) { + pci_dev->cap_present |=3D QEMU_PCIE_CAP_CXL; + } + pci_dev =3D do_pci_register_device(pci_dev, object_get_typename(OBJECT(qdev)), pci_dev->devfn, errp); @@ -2817,6 +2826,7 @@ static void pci_register_types(void) type_register_static(&pci_bus_info); type_register_static(&pcie_bus_info); type_register_static(&conventional_pci_interface_info); + type_register_static(&cxl_interface_info); type_register_static(&pcie_interface_info); type_register_static(&pci_device_type_info); } diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 66db08462f..528cef341c 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -195,6 +195,8 @@ enum { QEMU_PCIE_LNKSTA_DLLLA =3D (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 QEMU_PCIE_EXTCAP_INIT =3D (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), +#define QEMU_PCIE_CXL_BITNR 10 + QEMU_PCIE_CAP_CXL =3D (1 << QEMU_PCIE_CXL_BITNR), }; =20 #define TYPE_PCI_DEVICE "pci-device" @@ -202,6 +204,12 @@ typedef struct PCIDeviceClass PCIDeviceClass; DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass, PCI_DEVICE, TYPE_PCI_DEVICE) =20 +/* + * Implemented by devices that can be plugged on CXL buses. In the spec, t= his is + * actually a "CXL Component, but we name it device to match the PCI namin= g. + */ +#define INTERFACE_CXL_DEVICE "cxl-device" + /* Implemented by devices that can be plugged on PCI Express buses */ #define INTERFACE_PCIE_DEVICE "pci-express-device" =20 --=20 2.30.0