From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612227743; cv=none; d=zohomail.com; s=zohoarc; b=kOhLh9c1XciJ1giOXWXifKLRPyBMC+R3kjs99DUWb6kkpu8mI39ZDMyb+s8bzeEnF2/yXOG07mA5bcgDl//t4O9TBcg/gGxuKcbCK8Nr1RmH29wpE/0iEWeLLqHDmsCsvKrJixMmAKOjl3jTgSVeSjjfVot5daylveNZJK5x+24= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612227743; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AXNy9UliYRNerU7loYyHDXKhVR+Se/7tUMV8dfqOQIc=; b=cnae9ynMT55lm7f3VKtOcbfIZnD6ogXFQjkkYzr1/Er5MNhgZmrG4++dUt2J6viJp6OeWVbHU9xhMsH1WmXx0s2UMm2lpa/cmlBLJPdZ9P+enPToVmfNDBzGrrbLEOEmwWLzSlPax0XbFXPBFwGbekNNnOoiPjZAlZTkVHCTo9I= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612227743079587.9057882220051; Mon, 1 Feb 2021 17:02:23 -0800 (PST) Received: from localhost ([::1]:40992 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6k5F-0001Qo-9I for importer@patchew.org; Mon, 01 Feb 2021 20:02:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k34-00087L-7A for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:06 -0500 Received: from mga18.intel.com ([134.134.136.126]:33363) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k2z-0001oo-Hd for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:05 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 16:59:54 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 16:59:53 -0800 IronPort-SDR: mHPHklThosMsouhLKukn0HSoaDZQ24s8Bjg4iOhOWHJFbXW/B3RZ0gF0Fi25kY7yxzraL3ANzd IpdKwfLWur7w== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457076" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457076" IronPort-SDR: ohOd2fvk0iUmqWddqrIq/4W+/dDXel0bsAoOQ5YfgKofVN26VvHWaa+ayyqy/y0LfJnaY21jk/ OVKY2JODiCnw== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764024" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 01/31] hw/pci/cxl: Add a CXL component type (interface) Date: Mon, 1 Feb 2021 16:59:18 -0800 Message-Id: <20210202005948.241655-2-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" A CXL component is a hardware entity that implements CXL component registers from the CXL 2.0 spec (8.2.3). Currently these represent 3 general types. 1. Host Bridge 2. Ports (root, upstream, downstream) 3. Devices (memory, other) A CXL component can be conceptually thought of as a PCIe device with extra functionality when enumerated and enabled. For this reason, CXL does here, and will continue to add on to existing PCI code paths. Host bridges will typically need to be handled specially and so they can implement this newly introduced interface or not. All other components should implement this interface. Implementing this interface allows the core pci code to treat these devices as special where appropriate. Signed-off-by: Ben Widawsky --- hw/pci/pci.c | 10 ++++++++++ include/hw/pci/pci.h | 8 ++++++++ 2 files changed, 18 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 512e9042ff..a45ca326ed 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -194,6 +194,11 @@ static const TypeInfo pci_bus_info =3D { .class_init =3D pci_bus_class_init, }; =20 +static const TypeInfo cxl_interface_info =3D { + .name =3D INTERFACE_CXL_DEVICE, + .parent =3D TYPE_INTERFACE, +}; + static const TypeInfo pcie_interface_info =3D { .name =3D INTERFACE_PCIE_DEVICE, .parent =3D TYPE_INTERFACE, @@ -2091,6 +2096,10 @@ static void pci_qdev_realize(DeviceState *qdev, Erro= r **errp) pci_dev->cap_present |=3D QEMU_PCI_CAP_EXPRESS; } =20 + if (object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE)) { + pci_dev->cap_present |=3D QEMU_PCIE_CAP_CXL; + } + pci_dev =3D do_pci_register_device(pci_dev, object_get_typename(OBJECT(qdev)), pci_dev->devfn, errp); @@ -2817,6 +2826,7 @@ static void pci_register_types(void) type_register_static(&pci_bus_info); type_register_static(&pcie_bus_info); type_register_static(&conventional_pci_interface_info); + type_register_static(&cxl_interface_info); type_register_static(&pcie_interface_info); type_register_static(&pci_device_type_info); } diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 66db08462f..528cef341c 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -195,6 +195,8 @@ enum { QEMU_PCIE_LNKSTA_DLLLA =3D (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 QEMU_PCIE_EXTCAP_INIT =3D (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), +#define QEMU_PCIE_CXL_BITNR 10 + QEMU_PCIE_CAP_CXL =3D (1 << QEMU_PCIE_CXL_BITNR), }; =20 #define TYPE_PCI_DEVICE "pci-device" @@ -202,6 +204,12 @@ typedef struct PCIDeviceClass PCIDeviceClass; DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass, PCI_DEVICE, TYPE_PCI_DEVICE) =20 +/* + * Implemented by devices that can be plugged on CXL buses. In the spec, t= his is + * actually a "CXL Component, but we name it device to match the PCI namin= g. + */ +#define INTERFACE_CXL_DEVICE "cxl-device" + /* Implemented by devices that can be plugged on PCI Express buses */ #define INTERFACE_PCIE_DEVICE "pci-express-device" =20 --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612227743; cv=none; d=zohomail.com; s=zohoarc; b=kdNXg3Wd9ZbHdmO2dD6kaTgn/S2oRyI8zysRS5k3CZw4/zKkeKaU8H/rjOfYubnL0xToXqIr06DXDf7sGL9Q7gSSzwsoFUD/PqWqAtHMffy9B3AwENrL89GaJ45kcm2pvxGJ/R/Ft/RYuvpkcC34feJbe0FJrdpIs7S3rGNSWHU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612227743; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gCL0lxSkU6IH7bp6EWtBDxAlnjv7pXyesW0Sxcy9l/o=; b=TmhDSb0iQrIljv5cT5VPXFRbbFPP2iH6E5rAifoly+jEVoX/bllBSxVwFdiQB+n0G4BLM8hGeu1n9wbJpDXxSyCNGkp8cuUMYkJAYxiUhK8DtQ0Du3U6/DxxdpP3h2ffSjcOnaESQZX6WjQErnSgCdjsbq01Hf/ECJ3iXcqckQc= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612227743100879.8228418917611; Mon, 1 Feb 2021 17:02:23 -0800 (PST) Received: from localhost ([::1]:41104 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6k5F-0001Tf-M4 for importer@patchew.org; Mon, 01 Feb 2021 20:02:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47042) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k34-00087H-1U for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:06 -0500 Received: from mga18.intel.com ([134.134.136.126]:33366) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k2z-0001pl-JE for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:05 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 16:59:55 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 16:59:54 -0800 IronPort-SDR: woYSvdb3Zkmr8nks/qhmL3KMyUNNdF6sbC7xsweSXCxo0f3SNwP0UNKSt2pNIfIrTULLN6EoRd zchUQmyURlMA== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457077" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457077" IronPort-SDR: 3LfPx3CY5mtbYftr84/UTMJO9S0RLWk1FUusjnDLLMQXM/7TtJuCQmyRBOh5uC3EdVHJQJe7e+ g9lhk05a4X0w== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764038" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 02/31] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Date: Mon, 1 Feb 2021 16:59:19 -0800 Message-Id: <20210202005948.241655-3-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" A CXL 2.0 component is any entity in the CXL topology. All components have a analogous function in PCIe. Except for the CXL host bridge, all have a PCIe config space that is accessible via the common PCIe mechanisms. CXL components are enumerated via DVSEC fields in the extended PCIe header space. CXL components will minimally implement some subset of CXL.mem and CXL.cache registers defined in 8.2.5 of the CXL 2.0 specification. Two headers and a utility library are introduced to support the minimum functionality needed to enumerate components. The cxl_pci header manages bits associated with PCI, specifically the DVSEC and related fields. The cxl_component.h variant has data structures and APIs that are useful for drivers implementing any of the CXL 2.0 components. The library takes care of making use of the DVSEC bits and the CXL.[mem|cache] registers. Per spec, the registers are little endian. None of the mechanisms required to enumerate a CXL capable hostbridge are introduced at this point. Note that the CXL.mem and CXL.cache registers used are always 4B wide. It's possible in the future that this constraint will not hold. Signed-off-by: Ben Widawsky --- MAINTAINERS | 6 + hw/Kconfig | 1 + hw/cxl/Kconfig | 3 + hw/cxl/cxl-component-utils.c | 208 +++++++++++++++++++++++++++++++++ hw/cxl/meson.build | 3 + hw/meson.build | 1 + include/hw/cxl/cxl.h | 17 +++ include/hw/cxl/cxl_component.h | 187 +++++++++++++++++++++++++++++ include/hw/cxl/cxl_pci.h | 138 ++++++++++++++++++++++ 9 files changed, 564 insertions(+) create mode 100644 hw/cxl/Kconfig create mode 100644 hw/cxl/cxl-component-utils.c create mode 100644 hw/cxl/meson.build create mode 100644 include/hw/cxl/cxl.h create mode 100644 include/hw/cxl/cxl_component.h create mode 100644 include/hw/cxl/cxl_pci.h diff --git a/MAINTAINERS b/MAINTAINERS index bcd88668bc..981dc92e25 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2234,6 +2234,12 @@ F: qapi/block*.json F: qapi/transaction.json T: git https://repo.or.cz/qemu/armbru.git block-next =20 +Compute Express Link +M: Ben Widawsky +S: Supported +F: hw/cxl/ +F: include/hw/cxl/ + Dirty Bitmaps M: Eric Blake M: Vladimir Sementsov-Ogievskiy diff --git a/hw/Kconfig b/hw/Kconfig index 5ad3c6b5a4..c03650c5ed 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -6,6 +6,7 @@ source audio/Kconfig source block/Kconfig source char/Kconfig source core/Kconfig +source cxl/Kconfig source display/Kconfig source dma/Kconfig source gpio/Kconfig diff --git a/hw/cxl/Kconfig b/hw/cxl/Kconfig new file mode 100644 index 0000000000..8e67519b16 --- /dev/null +++ b/hw/cxl/Kconfig @@ -0,0 +1,3 @@ +config CXL + bool + default y if PCI_EXPRESS diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c new file mode 100644 index 0000000000..8d56ad5c7d --- /dev/null +++ b/hw/cxl/cxl-component-utils.c @@ -0,0 +1,208 @@ +/* + * CXL Utility library for components + * + * Copyright(C) 2020 Intel Corporation. + * + * This work is licensed under the terms of the GNU GPL, version 2. See the + * COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/pci/pci.h" +#include "hw/cxl/cxl.h" + +static uint64_t cxl_cache_mem_read_reg(void *opaque, hwaddr offset, + unsigned size) +{ + CXLComponentState *cxl_cstate =3D opaque; + ComponentRegisters *cregs =3D &cxl_cstate->crb; + + assert(size =3D=3D 4); + + if (cregs->special_ops && cregs->special_ops->read) { + return cregs->special_ops->read(cxl_cstate, offset, size); + } else { + return cregs->cache_mem_registers[offset / 4]; + } +} + +static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t = value, + unsigned size) +{ + CXLComponentState *cxl_cstate =3D opaque; + ComponentRegisters *cregs =3D &cxl_cstate->crb; + + assert(size =3D=3D 4); + + if (cregs->special_ops && cregs->special_ops->write) { + cregs->special_ops->write(cxl_cstate, offset, value, size); + } else { + cregs->cache_mem_registers[offset / 4] =3D value; + } +} + +/* + * 8.2.3 + * The access restrictions specified in Section 8.2.2 also apply to CXL = 2.0 + * Component Registers. + * + * 8.2.2 + * =E2=80=A2 A 32 bit register shall be accessed as a 4 Bytes quantity. = Partial + * reads are not permitted. + * =E2=80=A2 A 64 bit register shall be accessed as a 8 Bytes quantity. = Partial + * reads are not permitted. + * + * As of the spec defined today, only 4 byte registers exist. + */ +static const MemoryRegionOps cache_mem_ops =3D { + .read =3D cxl_cache_mem_read_reg, + .write =3D cxl_cache_mem_write_reg, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +void cxl_component_register_block_init(Object *obj, + CXLComponentState *cxl_cstate, + const char *type) +{ + ComponentRegisters *cregs =3D &cxl_cstate->crb; + + memory_region_init(&cregs->component_registers, obj, type, + CXL2_COMPONENT_BLOCK_SIZE); + + /* io registers controls link which we don't care about in QEMU */ + memory_region_init_io(&cregs->io, obj, NULL, cregs, ".io", + CXL2_COMPONENT_IO_REGION_SIZE); + memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs, + ".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE); + + memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io= ); + memory_region_add_subregion(&cregs->component_registers, + CXL2_COMPONENT_IO_REGION_SIZE, + &cregs->cache_mem); +} + +static void ras_init_common(uint32_t *reg_state) +{ + reg_state[R_CXL_RAS_UNC_ERR_STATUS] =3D 0; + reg_state[R_CXL_RAS_UNC_ERR_MASK] =3D 0x1efff; + reg_state[R_CXL_RAS_UNC_ERR_SEVERITY] =3D 0x1efff; + reg_state[R_CXL_RAS_COR_ERR_STATUS] =3D 0; + reg_state[R_CXL_RAS_COR_ERR_MASK] =3D 0x3f; + reg_state[R_CXL_RAS_ERR_CAP_CTRL] =3D 0; /* CXL switches and devices m= ust set */ +} + +static void hdm_init_common(uint32_t *reg_state) +{ + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT,= 0); + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL, HDM_DECODE= R_ENABLE, 0); +} + +void cxl_component_register_init_common(uint32_t *reg_state, enum reg_type= type) +{ + int caps =3D 0; + switch (type) { + case CXL2_DOWNSTREAM_PORT: + case CXL2_DEVICE: + /* CAP, RAS, Link */ + caps =3D 2; + break; + case CXL2_UPSTREAM_PORT: + case CXL2_TYPE3_DEVICE: + case CXL2_LOGICAL_DEVICE: + /* + HDM */ + caps =3D 3; + break; + case CXL2_ROOT_PORT: + /* + Extended Security, + Snoop */ + caps =3D 5; + break; + default: + abort(); + } + + memset(reg_state, 0, 0x1000); + + /* CXL Capability Header Register */ + ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ID, 1); + ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, VERSION, 1); + ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, = 1); + ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ARRAY_SIZE, caps); + + +#define init_cap_reg(reg, id, version) = \ + _Static_assert(CXL_##reg##_REGISTERS_OFFSET !=3D 0, "Invalid cap offse= t\n");\ + do { = \ + int which =3D R_CXL_##reg##_CAPABILITY_HEADER; = \ + reg_state[which] =3D FIELD_DP32(reg_state[which], = \ + CXL_##reg##_CAPABILITY_HEADER, ID, i= d); \ + reg_state[which] =3D = \ + FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, = \ + VERSION, version); = \ + reg_state[which] =3D = \ + FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, PT= R, \ + CXL_##reg##_REGISTERS_OFFSET); = \ + } while (0) + + init_cap_reg(RAS, 2, 1); + ras_init_common(reg_state); + + init_cap_reg(LINK, 4, 2); + + if (caps < 3) { + return; + } + + init_cap_reg(HDM, 5, 1); + hdm_init_common(reg_state); + + if (caps < 5) { + return; + } + + init_cap_reg(EXTSEC, 6, 1); + init_cap_reg(SNOOP, 8, 1); + +#undef init_cap_reg +} + +/* + * Helper to creates a DVSEC header for a CXL entity. The caller is respon= sible + * for tracking the valid offset. + * + * This function will build the DVSEC header on behalf of the caller and t= hen + * copy in the remaining data for the vendor specific bits. + */ +void cxl_component_create_dvsec(CXLComponentState *cxl, uint16_t length, + uint16_t type, uint8_t rev, uint8_t *body) +{ + PCIDevice *pdev =3D cxl->pdev; + uint16_t offset =3D cxl->dvsec_offset; + + assert(offset >=3D PCI_CFG_SPACE_SIZE && + ((offset + length) < PCI_CFG_SPACE_EXP_SIZE)); + assert((length & 0xf000) =3D=3D 0); + assert((rev & ~0xf) =3D=3D 0); + + /* Create the DVSEC in the MCFG space */ + pcie_add_capability(pdev, PCI_EXT_CAP_ID_DVSEC, 1, offset, length); + pci_set_long(pdev->config + offset + PCIE_DVSEC_HEADER1_OFFSET, + (length << 20) | (rev << 16) | CXL_VENDOR_ID); + pci_set_word(pdev->config + offset + PCIE_DVSEC_ID_OFFSET, type); + memcpy(pdev->config + offset + sizeof(struct dvsec_header), + body + sizeof(struct dvsec_header), + length - sizeof(struct dvsec_header)); + + /* Update state for future DVSEC additions */ + range_init_nofail(&cxl->dvsecs[type], cxl->dvsec_offset, length); + cxl->dvsec_offset +=3D length; +} diff --git a/hw/cxl/meson.build b/hw/cxl/meson.build new file mode 100644 index 0000000000..00c3876a0f --- /dev/null +++ b/hw/cxl/meson.build @@ -0,0 +1,3 @@ +softmmu_ss.add(when: 'CONFIG_CXL', if_true: files( + 'cxl-component-utils.c', +)) diff --git a/hw/meson.build b/hw/meson.build index 010de7219c..3e440c341a 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -6,6 +6,7 @@ subdir('block') subdir('char') subdir('core') subdir('cpu') +subdir('cxl') subdir('display') subdir('dma') subdir('gpio') diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h new file mode 100644 index 0000000000..55f6cc30a5 --- /dev/null +++ b/include/hw/cxl/cxl.h @@ -0,0 +1,17 @@ +/* + * QEMU CXL Support + * + * Copyright (c) 2020 Intel + * + * This work is licensed under the terms of the GNU GPL, version 2. See the + * COPYING file in the top-level directory. + */ + +#ifndef CXL_H +#define CXL_H + +#include "cxl_pci.h" +#include "cxl_component.h" + +#endif + diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h new file mode 100644 index 0000000000..762feb54da --- /dev/null +++ b/include/hw/cxl/cxl_component.h @@ -0,0 +1,187 @@ +/* + * QEMU CXL Component + * + * Copyright (c) 2020 Intel + * + * This work is licensed under the terms of the GNU GPL, version 2. See the + * COPYING file in the top-level directory. + */ + +#ifndef CXL_COMPONENT_H +#define CXL_COMPONENT_H + +/* CXL 2.0 - 8.2.4 */ +#define CXL2_COMPONENT_IO_REGION_SIZE 0x1000 +#define CXL2_COMPONENT_CM_REGION_SIZE 0x1000 +#define CXL2_COMPONENT_BLOCK_SIZE 0x10000 + +#include "qemu/range.h" +#include "qemu/typedefs.h" +#include "hw/register.h" + +enum reg_type { + CXL2_DEVICE, + CXL2_TYPE3_DEVICE, + CXL2_LOGICAL_DEVICE, + CXL2_ROOT_PORT, + CXL2_UPSTREAM_PORT, + CXL2_DOWNSTREAM_PORT +}; + +/* + * Capability registers are defined at the top of the CXL.cache/mem region= and + * are packed. For our purposes we will always define the caps in the same + * order. + * CXL 2.0 - 8.2.5 Table 142 for details. + */ + +/* CXL 2.0 - 8.2.5.1 */ +REG32(CXL_CAPABILITY_HEADER, 0) + FIELD(CXL_CAPABILITY_HEADER, ID, 0, 16) + FIELD(CXL_CAPABILITY_HEADER, VERSION, 16, 4) + FIELD(CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 20, 4) + FIELD(CXL_CAPABILITY_HEADER, ARRAY_SIZE, 24, 8) + +#define CXLx_CAPABILITY_HEADER(type, offset) \ + REG32(CXL_##type##_CAPABILITY_HEADER, offset) \ + FIELD(CXL_##type##_CAPABILITY_HEADER, ID, 0, 16) \ + FIELD(CXL_##type##_CAPABILITY_HEADER, VERSION, 16, 4) \ + FIELD(CXL_##type##_CAPABILITY_HEADER, PTR, 20, 12) +CXLx_CAPABILITY_HEADER(RAS, 0x4) +CXLx_CAPABILITY_HEADER(LINK, 0x8) +CXLx_CAPABILITY_HEADER(HDM, 0xc) +CXLx_CAPABILITY_HEADER(EXTSEC, 0x10) +CXLx_CAPABILITY_HEADER(SNOOP, 0x14) + +/* + * Capability structures contain the actual registers that the CXL compone= nt + * implements. Some of these are specific to certain types of components, = but + * this implementation leaves enough space regardless. + */ +/* 8.2.5.9 - CXL RAS Capability Structure */ +#define CXL_RAS_REGISTERS_OFFSET 0x80 /* Give ample space for caps before = this */ +#define CXL_RAS_REGISTERS_SIZE 0x58 +REG32(CXL_RAS_UNC_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET) +REG32(CXL_RAS_UNC_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x4) +REG32(CXL_RAS_UNC_ERR_SEVERITY, CXL_RAS_REGISTERS_OFFSET + 0x8) +REG32(CXL_RAS_COR_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET + 0xc) +REG32(CXL_RAS_COR_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x10) +REG32(CXL_RAS_ERR_CAP_CTRL, CXL_RAS_REGISTERS_OFFSET + 0x14) +/* Offset 0x18 - 0x58 reserved for RAS logs */ + +/* 8.2.5.10 - CXL Security Capability Structure */ +#define CXL_SEC_REGISTERS_OFFSET (CXL_RAS_REGISTERS_OFFSET + CXL_RAS_REGIS= TERS_SIZE) +#define CXL_SEC_REGISTERS_SIZE 0 /* We don't implement 1.1 downstream po= rts */ + +/* 8.2.5.11 - CXL Link Capability Structure */ +#define CXL_LINK_REGISTERS_OFFSET (CXL_SEC_REGISTERS_OFFSET + CXL_SEC_REGI= STERS_SIZE) +#define CXL_LINK_REGISTERS_SIZE 0x38 + +/* 8.2.5.12 - CXL HDM Decoder Capability Structure */ +#define HDM_DECODE_MAX 10 /* 8.2.5.12.1 */ +#define CXL_HDM_REGISTERS_OFFSET \ + (CXL_LINK_REGISTERS_OFFSET + CXL_LINK_REGISTERS_SIZE) /* 8.2.5.12 */ +#define CXL_HDM_REGISTERS_SIZE (0x20 + HDM_DECODE_MAX * 10) +#define HDM_DECODER_INIT(n) = \ + REG32(CXL_HDM_DECODER##n##_BASE_LO, = \ + CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x10) = \ + FIELD(CXL_HDM_DECODER##n##_BASE_LO, L, 28, 4) = \ + REG32(CXL_HDM_DECODER##n##_BASE_HI, = \ + CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x14) = \ + REG32(CXL_HDM_DECODER##n##_SIZE_LO, = \ + CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x18) = \ + REG32(CXL_HDM_DECODER##n##_SIZE_HI, = \ + CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x1C) = \ + REG32(CXL_HDM_DECODER##n##_CTRL, = \ + CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x20) = \ + FIELD(CXL_HDM_DECODER##n##_CTRL, IG, 0, 4) = \ + FIELD(CXL_HDM_DECODER##n##_CTRL, IW, 4, 4) = \ + FIELD(CXL_HDM_DECODER##n##_CTRL, LOCK_ON_COMMIT, 8, 1) = \ + FIELD(CXL_HDM_DECODER##n##_CTRL, COMMIT, 9, 1) = \ + FIELD(CXL_HDM_DECODER##n##_CTRL, COMMITTED, 10, 1) = \ + FIELD(CXL_HDM_DECODER##n##_CTRL, ERROR, 11, 1) = \ + FIELD(CXL_HDM_DECODER##n##_CTRL, TYPE, 12, 1) = \ + REG32(CXL_HDM_DECODER##n##_TARGET_LIST_LO, 0x24) = \ + REG32(CXL_HDM_DECODER##n##_TARGET_LIST_HI, 0x28) + +REG32(CXL_HDM_DECODER_CAPABILITY, CXL_HDM_REGISTERS_OFFSET) + FIELD(CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT, 0, 4) + FIELD(CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 4, 4) + FIELD(CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 8, 1) + FIELD(CXL_HDM_DECODER_CAPABILITY, INTELEAVE_4K, 9, 1) + FIELD(CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 10, 1) +REG32(CXL_HDM_DECODER_GLOBAL_CONTROL, CXL_HDM_REGISTERS_OFFSET + 4) + FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, POISON_ON_ERR_EN, 0, 1) + FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, HDM_DECODER_ENABLE, 1, 1) + +HDM_DECODER_INIT(0); + +/* 8.2.5.13 - CXL Extended Security Capability Structure (Root complex onl= y) */ +#define EXTSEC_ENTRY_MAX 256 +#define CXL_EXTSEC_REGISTERS_OFFSET (CXL_HDM_REGISTERS_OFFSET + CXL_HDM_RE= GISTERS_SIZE) +#define CXL_EXTSEC_REGISTERS_SIZE (8 * EXTSEC_ENTRY_MAX + 4) + +/* 8.2.5.14 - CXL IDE Capability Structure */ +#define CXL_IDE_REGISTERS_OFFSET (CXL_EXTSEC_REGISTERS_OFFSET + CXL_EXTSEC= _REGISTERS_SIZE) +#define CXL_IDE_REGISTERS_SIZE 0 + +/* 8.2.5.15 - CXL Snoop Filter Capability Structure */ +#define CXL_SNOOP_REGISTERS_OFFSET (CXL_IDE_REGISTERS_OFFSET + CXL_IDE_REG= ISTERS_SIZE) +#define CXL_SNOOP_REGISTERS_SIZE 0x8 + +_Static_assert((CXL_SNOOP_REGISTERS_OFFSET + CXL_SNOOP_REGISTERS_SIZE) < 0= x1000, + "No space for registers"); + +typedef struct component_registers { + /* + * Main memory region to be registered with QEMU core. + */ + MemoryRegion component_registers; + + /* + * 8.2.4 Table 141: + * 0x0000 - 0x0fff CXL.io registers + * 0x1000 - 0x1fff CXL.cache and CXL.mem + * 0x2000 - 0xdfff Implementation specific + * 0xe000 - 0xe3ff CXL ARB/MUX registers + * 0xe400 - 0xffff RSVD + */ + uint32_t io_registers[CXL2_COMPONENT_IO_REGION_SIZE >> 2]; + MemoryRegion io; + + uint32_t cache_mem_registers[CXL2_COMPONENT_CM_REGION_SIZE >> 2]; + MemoryRegion cache_mem; + + MemoryRegion impl_specific; + MemoryRegion arb_mux; + MemoryRegion rsvd; + + /* special_ops is used for any component that needs any specific handl= ing */ + MemoryRegionOps *special_ops; +} ComponentRegisters; + +/* + * A CXL component represents all entities in a CXL hierarchy. This includ= es, + * host bridges, root ports, upstream/downstream switch ports, and devices + */ +typedef struct cxl_component { + ComponentRegisters crb; + union { + struct { + Range dvsecs[CXL20_MAX_DVSEC]; + uint16_t dvsec_offset; + struct PCIDevice *pdev; + }; + }; +} CXLComponentState; + +void cxl_component_register_block_init(Object *obj, + CXLComponentState *cxl_cstate, + const char *type); +void cxl_component_register_init_common(uint32_t *reg_state, + enum reg_type type); + +void cxl_component_create_dvsec(CXLComponentState *cxl_cstate, uint16_t le= ngth, + uint16_t type, uint8_t rev, uint8_t *body); + +#endif diff --git a/include/hw/cxl/cxl_pci.h b/include/hw/cxl/cxl_pci.h new file mode 100644 index 0000000000..a53c2e5ae7 --- /dev/null +++ b/include/hw/cxl/cxl_pci.h @@ -0,0 +1,138 @@ +/* + * QEMU CXL PCI interfaces + * + * Copyright (c) 2020 Intel + * + * This work is licensed under the terms of the GNU GPL, version 2. See the + * COPYING file in the top-level directory. + */ + +#ifndef CXL_PCI_H +#define CXL_PCI_H + +#include "hw/pci/pci.h" +#include "hw/pci/pcie.h" + +#define CXL_VENDOR_ID 0x1e98 + +#define PCIE_DVSEC_HEADER1_OFFSET 0x4 /* Offset from start of extend cap */ +#define PCIE_DVSEC_ID_OFFSET 0x8 + +#define PCIE_CXL_DEVICE_DVSEC_LENGTH 0x38 +#define PCIE_CXL1_DEVICE_DVSEC_REVID 0 +#define PCIE_CXL2_DEVICE_DVSEC_REVID 1 + +#define EXTENSIONS_PORT_DVSEC_LENGTH 0x28 +#define EXTENSIONS_PORT_DVSEC_REVID 0 + +#define GPF_PORT_DVSEC_LENGTH 0x10 +#define GPF_PORT_DVSEC_REVID 0 + +#define PCIE_FLEXBUS_PORT_DVSEC_LENGTH_2_0 0x14 +#define PCIE_FLEXBUS_PORT_DVSEC_REVID_2_0 1 + +#define REG_LOC_DVSEC_LENGTH 0x24 +#define REG_LOC_DVSEC_REVID 0 + +enum { + PCIE_CXL_DEVICE_DVSEC =3D 0, + NON_CXL_FUNCTION_MAP_DVSEC =3D 2, + EXTENSIONS_PORT_DVSEC =3D 3, + GPF_PORT_DVSEC =3D 4, + GPF_DEVICE_DVSEC =3D 5, + PCIE_FLEXBUS_PORT_DVSEC =3D 7, + REG_LOC_DVSEC =3D 8, + MLD_DVSEC =3D 9, + CXL20_MAX_DVSEC +}; + +struct dvsec_header { + uint32_t cap_hdr; + uint32_t dv_hdr1; + uint16_t dv_hdr2; +} __attribute__((__packed__)); +_Static_assert(sizeof(struct dvsec_header) =3D=3D 10, + "dvsec header size incorrect"); + +/* + * CXL 2.0 devices must implement certain DVSEC IDs, and can [optionally] + * implement others. + * + * CXL 2.0 Device: 0, [2], 5, 8 + * CXL 2.0 RP: 3, 4, 7, 8 + * CXL 2.0 Upstream Port: [2], 7, 8 + * CXL 2.0 Downstream Port: 3, 4, 7, 8 + */ + +/* CXL 2.0 - 8.1.5 (ID 0003) */ +struct extensions_dvsec_port { + struct dvsec_header hdr; + uint16_t status; + uint16_t control; + uint8_t alt_bus_base; + uint8_t alt_bus_limit; + uint16_t alt_memory_base; + uint16_t alt_memory_limit; + uint16_t alt_prefetch_base; + uint16_t alt_prefetch_limit; + uint32_t alt_prefetch_base_high; + uint32_t alt_prefetch_base_low; + uint32_t rcrb_base; + uint32_t rcrb_base_high; +}; +_Static_assert(sizeof(struct extensions_dvsec_port) =3D=3D 0x28, + "extensions dvsec port size incorrect"); +#define PORT_CONTROL_OVERRIDE_OFFSET 0xc +#define PORT_CONTROL_UNMASK_SBR 1 +#define PORT_CONTROL_ALT_MEMID_EN 4 + +/* CXL 2.0 - 8.1.6 GPF DVSEC (ID 0004) */ +struct dvsec_port_gpf { + struct dvsec_header hdr; + uint16_t rsvd; + uint16_t phase1_ctrl; + uint16_t phase2_ctrl; +}; +_Static_assert(sizeof(struct dvsec_port_gpf) =3D=3D 0x10, + "dvsec port GPF size incorrect"); + +/* CXL 2.0 - 8.1.8/8.2.1.3 Flexbus DVSEC (ID 0007) */ +struct dvsec_port_flexbus { + struct dvsec_header hdr; + uint16_t cap; + uint16_t ctrl; + uint16_t status; + uint32_t rcvd_mod_ts_data; +}; +_Static_assert(sizeof(struct dvsec_port_flexbus) =3D=3D 0x14, + "dvsec port flexbus size incorrect"); + +/* CXL 2.0 - 8.1.9 Register Locator DVSEC (ID 0008) */ +struct dvsec_register_locator { + struct dvsec_header hdr; + uint16_t rsvd; + uint32_t reg0_base_lo; + uint32_t reg0_base_hi; + uint32_t reg1_base_lo; + uint32_t reg1_base_hi; + uint32_t reg2_base_lo; + uint32_t reg2_base_hi; +}; +_Static_assert(sizeof(struct dvsec_register_locator) =3D=3D 0x24, + "dvsec register locator size incorrect"); + +/* BAR Equivalence Indicator */ +#define BEI_BAR_10H 0 +#define BEI_BAR_14H 1 +#define BEI_BAR_18H 2 +#define BEI_BAR_1cH 3 +#define BEI_BAR_20H 4 +#define BEI_BAR_24H 5 + +/* Register Block Identifier */ +#define RBI_EMPTY 0 +#define RBI_COMPONENT_REG (1 << 8) +#define RBI_BAR_VIRT_ACL (2 << 8) +#define RBI_CXL_DEVICE_REG (3 << 8) + +#endif --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 01 Feb 2021 20:00:08 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 16:59:56 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 16:59:55 -0800 IronPort-SDR: mRpCREb/Wyq4TgtKP1Cbr2UNdqeGNhcTEAeA+mhuagE5/8H9c6vTVTrq2NS7LUZ6KIoiIsYTeu ChW5v4E28mBA== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457079" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457079" IronPort-SDR: eprYjPG4hF3fBy0jm6V08RghzcD8Ab0d9RBbbTjE9spCO/4Na4rflnb/CvosCM+qwA4Tubs6Ag sy4AIGh0FHDw== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764052" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 03/31] hw/cxl/device: Introduce a CXL device (8.2.8) Date: Mon, 1 Feb 2021 16:59:20 -0800 Message-Id: <20210202005948.241655-4-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" A CXL device is a type of CXL component. Conceptually, a CXL device would be a leaf node in a CXL topology. From an emulation perspective, CXL devices are the most complex and so the actual implementation is reserved for discrete commits. This new device type is specifically catered towards the eventual implementation of a Type3 CXL.mem device, 8.2.8.5 in the CXL 2.0 specification. Signed-off-by: Ben Widawsky Reviewed-by: Jonathan Cameron --- include/hw/cxl/cxl.h | 1 + include/hw/cxl/cxl_device.h | 155 ++++++++++++++++++++++++++++++++++++ 2 files changed, 156 insertions(+) create mode 100644 include/hw/cxl/cxl_device.h diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h index 55f6cc30a5..23f52c4cf9 100644 --- a/include/hw/cxl/cxl.h +++ b/include/hw/cxl/cxl.h @@ -12,6 +12,7 @@ =20 #include "cxl_pci.h" #include "cxl_component.h" +#include "cxl_device.h" =20 #endif =20 diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h new file mode 100644 index 0000000000..a85f250503 --- /dev/null +++ b/include/hw/cxl/cxl_device.h @@ -0,0 +1,155 @@ +/* + * QEMU CXL Devices + * + * Copyright (c) 2020 Intel + * + * This work is licensed under the terms of the GNU GPL, version 2. See the + * COPYING file in the top-level directory. + */ + +#ifndef CXL_DEVICE_H +#define CXL_DEVICE_H + +#include "hw/register.h" + +/* + * The following is how a CXL device's MMIO space is laid out. The only + * requirement from the spec is that the capabilities array and the capabi= lity + * headers start at offset 0 and are contiguously packed. The headers them= selves + * provide offsets to the register fields. For this emulation, registers w= ill + * start at offset 0x80 (m =3D=3D 0x80). No secondary mailbox is implement= ed which + * means that n =3D m + sizeof(mailbox registers) + sizeof(device register= s). + * + * This is roughly described in 8.2.8 Figure 138 of the CXL 2.0 spec. + * + * n + PAYLOAD_SIZE_MAX +---------------------------------+ + * | | + * ^ | | + * | | | + * | | | + * | | | + * | | Command Payload | + * | | | + * | | | + * | | | + * | | | + * | | | + * n +---------------------------------+ + * ^ | | + * | | Device Capability Registers | + * | | x, mailbox, y | + * | | | + * m +---------------------------------+ + * ^ | Device Capability Header y | + * | +---------------------------------+ + * | | Device Capability Header Mailbox| + * | +------------- -------------------- + * | | Device Capability Header x | + * | +---------------------------------+ + * | | | + * | | | + * | | Device Cap Array[0..n] | + * | | | + * | | | + * | | | + * 0 +---------------------------------+ + */ + +#define CXL_DEVICE_CAP_HDR1_OFFSET 0x10 /* Figure 138 */ +#define CXL_DEVICE_CAP_REG_SIZE 0x10 /* 8.2.8.2 */ +#define CXL_DEVICE_CAPS_MAX 4 /* 8.2.8.2.1 + 8.2.8.5 */ + +#define CXL_DEVICE_REGISTERS_OFFSET 0x80 /* Read comment above */ +#define CXL_DEVICE_REGISTERS_LENGTH 0x8 /* 8.2.8.3.1 */ + +#define CXL_MAILBOX_REGISTERS_OFFSET \ + (CXL_DEVICE_REGISTERS_OFFSET + CXL_DEVICE_REGISTERS_LENGTH) +#define CXL_MAILBOX_REGISTERS_SIZE 0x20 +#define CXL_MAILBOX_PAYLOAD_SHIFT 11 +#define CXL_MAILBOX_MAX_PAYLOAD_SIZE (1 << CXL_MAILBOX_PAYLOAD_SHIFT) +#define CXL_MAILBOX_REGISTERS_LENGTH \ + (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE) + +typedef struct cxl_device_state { + MemoryRegion device_registers; + + /* mmio for device capabilities array - 8.2.8.2 */ + MemoryRegion caps; + + /* mmio for the device status registers 8.2.8.3 */ + MemoryRegion device; + + /* mmio for the mailbox registers 8.2.8.4 */ + MemoryRegion mailbox; + + /* memory region for persistent memory, HDM */ + MemoryRegion *pmem; + + /* memory region for volatile memory, HDM */ + MemoryRegion *vmem; +} CXLDeviceState; + +/* Initialize the register block for a device */ +void cxl_device_register_block_init(Object *obj, CXLDeviceState *dev); + +/* Set up default values for the register block */ +void cxl_device_register_init_common(CXLDeviceState *dev); + +/* CXL 2.0 - 8.2.8.1 */ +REG32(CXL_DEV_CAP_ARRAY, 0) /* 48b!?!?! */ + FIELD(CXL_DEV_CAP_ARRAY, CAP_ID, 0, 16) + FIELD(CXL_DEV_CAP_ARRAY, CAP_VERSION, 16, 8) +REG32(CXL_DEV_CAP_ARRAY2, 4) /* We're going to pretend it's 64b */ + FIELD(CXL_DEV_CAP_ARRAY2, CAP_COUNT, 0, 16) + +/* + * Helper macro to initialize capability headers for CXL devices. + * + * In the 8.2.8.2, this is listed as a 128b register, but in 8.2.8, it say= s: + * > No registers defined in Section 8.2.8 are larger than 64-bits wide so= that + * > is the maximum access size allowed for these registers. If this rule = is not + * > followed, the behavior is undefined + * + * Here we've chosen to make it 4 dwords. The spec allows any pow2 multiple + * access to be used for a register (2 qwords, 8 words, 128 bytes). + */ +#define CXL_DEVICE_CAPABILITY_HEADER_REGISTER(n, offset) = \ + REG32(CXL_DEV_##n##_CAP_HDR0, offset) \ + FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_ID, 0, 16) \ + FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_VERSION, 16, 8) \ + REG32(CXL_DEV_##n##_CAP_HDR1, offset + 4) \ + FIELD(CXL_DEV_##n##_CAP_HDR1, CAP_OFFSET, 0, 32) \ + REG32(CXL_DEV_##n##_CAP_HDR2, offset + 8) \ + FIELD(CXL_DEV_##n##_CAP_HDR2, CAP_LENGTH, 0, 32) + +CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE, CXL_DEVICE_CAP_HDR1_OFFSET) +CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET = + \ + CXL_DEVICE_CAP_REG_SIZE) + +REG32(CXL_DEV_MAILBOX_CAP, 0) + FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5) + FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1) + FIELD(CXL_DEV_MAILBOX_CAP, BG_INT_CAP, 6, 1) + FIELD(CXL_DEV_MAILBOX_CAP, MSI_N, 7, 4) + +REG32(CXL_DEV_MAILBOX_CTRL, 4) + FIELD(CXL_DEV_MAILBOX_CTRL, DOORBELL, 0, 1) + FIELD(CXL_DEV_MAILBOX_CTRL, INT_EN, 1, 1) + FIELD(CXL_DEV_MAILBOX_CTRL, BG_INT_EN, 2, 1) + +/* XXX: actually a 64b register */ +REG32(CXL_DEV_MAILBOX_STS, 0x10) + FIELD(CXL_DEV_MAILBOX_STS, BG_OP, 0, 1) + FIELD(CXL_DEV_MAILBOX_STS, ERRNO, 32, 16) + FIELD(CXL_DEV_MAILBOX_STS, VENDOR_ERRNO, 48, 16) + +/* XXX: actually a 64b register */ +REG32(CXL_DEV_BG_CMD_STS, 0x18) + FIELD(CXL_DEV_BG_CMD_STS, BG, 0, 16) + FIELD(CXL_DEV_BG_CMD_STS, DONE, 16, 7) + FIELD(CXL_DEV_BG_CMD_STS, ERRNO, 32, 16) + FIELD(CXL_DEV_BG_CMD_STS, VENDOR_ERRNO, 48, 16) + +REG32(CXL_DEV_CMD_PAYLOAD, 0x20) + +#endif --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 01 Feb 2021 20:00:10 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 16:59:57 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 16:59:56 -0800 IronPort-SDR: HAvCrRuKXA05MjA05w9I/IJASdUZdHKsCLFtWlid+O76vP/Gk/tax5omP8NLMECRHW1jIHxE+6 C48jWBRz7YoQ== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457081" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457081" IronPort-SDR: iBBfz+pcKucWJNRI1+lm3P5UU2TShZ24qGllhR0/lM7uXjMxiIaP1PnK+THCDwwviclJYzRzPO bSdYohOK03bQ== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764060" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 04/31] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Date: Mon, 1 Feb 2021 16:59:21 -0800 Message-Id: <20210202005948.241655-5-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" This implements all device MMIO up to the first capability. That includes the CXL Device Capabilities Array Register, as well as all of the CXL Device Capability Header Registers. The latter are filled in as they are implemented in the following patches. Endianness and alignment are managed by softmmu memory core. Signed-off-by: Ben Widawsky --- hw/cxl/cxl-device-utils.c | 105 ++++++++++++++++++++++++++++++++++++ hw/cxl/meson.build | 1 + include/hw/cxl/cxl_device.h | 27 +++++++++- 3 files changed, 132 insertions(+), 1 deletion(-) create mode 100644 hw/cxl/cxl-device-utils.c diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c new file mode 100644 index 0000000000..bb15ad9a0f --- /dev/null +++ b/hw/cxl/cxl-device-utils.c @@ -0,0 +1,105 @@ +/* + * CXL Utility library for devices + * + * Copyright(C) 2020 Intel Corporation. + * + * This work is licensed under the terms of the GNU GPL, version 2. See the + * COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/cxl/cxl.h" + +/* + * Device registers have no restrictions per the spec, and so fall back to= the + * default memory mapped register rules in 8.2: + * Software shall use CXL.io Memory Read and Write to access memory mapp= ed + * register defined in this section. Unless otherwise specified, software + * shall restrict the accesses width based on the following: + * =E2=80=A2 A 32 bit register shall be accessed as a 1 Byte, 2 Bytes = or 4 Bytes + * quantity. + * =E2=80=A2 A 64 bit register shall be accessed as a 1 Byte, 2 Bytes, 4= Bytes or 8 + * Bytes + * =E2=80=A2 The address shall be a multiple of the access width, e.g. w= hen + * accessing a register as a 4 Byte quantity, the address shall be + * multiple of 4. + * =E2=80=A2 The accesses shall map to contiguous bytes.If these rules a= re not + * followed, the behavior is undefined + */ + +static uint64_t caps_reg_read(void *opaque, hwaddr offset, unsigned size) +{ + CXLDeviceState *cxl_dstate =3D opaque; + + return cxl_dstate->caps_reg_state32[offset / 4]; +} + +static uint64_t dev_reg_read(void *opaque, hwaddr offset, unsigned size) +{ + return 0; +} + +static const MemoryRegionOps dev_ops =3D { + .read =3D dev_reg_read, + .write =3D NULL, /* status register is read only */ + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + .unaligned =3D false, + }, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, +}; + +static const MemoryRegionOps caps_ops =3D { + .read =3D caps_reg_read, + .write =3D NULL, /* caps registers are read only */ + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + .unaligned =3D false, + }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +void cxl_device_register_block_init(Object *obj, CXLDeviceState *cxl_dstat= e) +{ + /* This will be a BAR, so needs to be rounded up to pow2 for PCI spec = */ + memory_region_init(&cxl_dstate->device_registers, obj, "device-registe= rs", + pow2ceil(CXL_MMIO_SIZE)); + + memory_region_init_io(&cxl_dstate->caps, obj, &caps_ops, cxl_dstate, + "cap-array", CXL_DEVICE_REGISTERS_OFFSET - 0); + memory_region_init_io(&cxl_dstate->device, obj, &dev_ops, cxl_dstate, + "device-status", CXL_DEVICE_REGISTERS_LENGTH); + + memory_region_add_subregion(&cxl_dstate->device_registers, 0, + &cxl_dstate->caps); + memory_region_add_subregion(&cxl_dstate->device_registers, + CXL_DEVICE_REGISTERS_OFFSET, + &cxl_dstate->device); +} + +static void device_reg_init_common(CXLDeviceState *cxl_dstate) { } + +void cxl_device_register_init_common(CXLDeviceState *cxl_dstate) +{ + uint32_t *cap_hdrs =3D cxl_dstate->caps_reg_state32; + const int cap_count =3D 1; + + /* CXL Device Capabilities Array Register */ + ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_ID, 0); + ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_VERSION, 1); + ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY2, CAP_COUNT, cap_count); + + cxl_device_cap_init(cxl_dstate, DEVICE, 1); + device_reg_init_common(cxl_dstate); +} diff --git a/hw/cxl/meson.build b/hw/cxl/meson.build index 00c3876a0f..47154d6850 100644 --- a/hw/cxl/meson.build +++ b/hw/cxl/meson.build @@ -1,3 +1,4 @@ softmmu_ss.add(when: 'CONFIG_CXL', if_true: files( 'cxl-component-utils.c', + 'cxl-device-utils.c', )) diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index a85f250503..f3bcf19410 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -58,6 +58,8 @@ #define CXL_DEVICE_CAP_HDR1_OFFSET 0x10 /* Figure 138 */ #define CXL_DEVICE_CAP_REG_SIZE 0x10 /* 8.2.8.2 */ #define CXL_DEVICE_CAPS_MAX 4 /* 8.2.8.2.1 + 8.2.8.5 */ +#define CXL_CAPS_SIZE \ + (CXL_DEVICE_CAP_REG_SIZE * CXL_DEVICE_CAPS_MAX + 1) /* +1 for header */ =20 #define CXL_DEVICE_REGISTERS_OFFSET 0x80 /* Read comment above */ #define CXL_DEVICE_REGISTERS_LENGTH 0x8 /* 8.2.8.3.1 */ @@ -70,11 +72,18 @@ #define CXL_MAILBOX_REGISTERS_LENGTH \ (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE) =20 +#define CXL_MMIO_SIZE \ + CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_REGISTERS_LENGTH + \ + CXL_MAILBOX_REGISTERS_LENGTH + typedef struct cxl_device_state { MemoryRegion device_registers; =20 /* mmio for device capabilities array - 8.2.8.2 */ - MemoryRegion caps; + struct { + MemoryRegion caps; + uint32_t caps_reg_state32[CXL_CAPS_SIZE / 4]; + }; =20 /* mmio for the device status registers 8.2.8.3 */ MemoryRegion device; @@ -126,6 +135,22 @@ CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE, CXL_DEVI= CE_CAP_HDR1_OFFSET) CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET = + \ CXL_DEVICE_CAP_REG_SIZE) =20 +#define cxl_device_cap_init(dstate, reg, cap_id) = \ + do { = \ + uint32_t *cap_hdrs =3D dstate->caps_reg_state32; = \ + int which =3D R_CXL_DEV_##reg##_CAP_HDR0; = \ + cap_hdrs[which] =3D = \ + FIELD_DP32(cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_ID, = cap_id); \ + cap_hdrs[which] =3D FIELD_DP32( = \ + cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_VERSION, 1); = \ + cap_hdrs[which + 1] =3D = \ + FIELD_DP32(cap_hdrs[which + 1], CXL_DEV_##reg##_CAP_HDR1, = \ + CAP_OFFSET, CXL_##reg##_REGISTERS_OFFSET); = \ + cap_hdrs[which + 2] =3D = \ + FIELD_DP32(cap_hdrs[which + 2], CXL_DEV_##reg##_CAP_HDR2, = \ + CAP_LENGTH, CXL_##reg##_REGISTERS_LENGTH); = \ + } while (0) + REG32(CXL_DEV_MAILBOX_CAP, 0) FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5) FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1) --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612227921; cv=none; d=zohomail.com; s=zohoarc; b=hTnFxtnFmlXENBDy20zWFvI9OytqTCVlNUxQAXrdAQMrPhO07Vvxx5h56HUcuEcEc6vDxFO1pKvjCh6YyggiKmvnD9rijHwAfa+BvnIYQv9N1kpbX+r2veweySmvoQ6QhvD0SAhhqHUUC1/CeYExIyUN9zO5SX/Skjj31UYnLRI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612227921; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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d="scan'208";a="581764066" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 05/31] hw/cxl/device: Implement basic mailbox (8.2.8.4) Date: Mon, 1 Feb 2021 16:59:22 -0800 Message-Id: <20210202005948.241655-6-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This is the beginning of implementing mailbox support for CXL 2.0 devices. The implementation recognizes when the doorbell is rung, handles the command/payload, clears the doorbell while returning error codes and data. Generally the mailbox mechanism is designed to permit communication between the host OS and the firmware running on the device. For our purposes, we emulate both the firmware, implemented primarily in cxl-mailbox-utils.c, and the hardware. No commands are implemented yet. Signed-off-by: Ben Widawsky --- hw/cxl/cxl-device-utils.c | 125 ++++++++++++++++++++++- hw/cxl/cxl-mailbox-utils.c | 197 ++++++++++++++++++++++++++++++++++++ hw/cxl/meson.build | 1 + include/hw/cxl/cxl.h | 3 + include/hw/cxl/cxl_device.h | 28 ++++- 5 files changed, 349 insertions(+), 5 deletions(-) create mode 100644 hw/cxl/cxl-mailbox-utils.c diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c index bb15ad9a0f..6602606f3d 100644 --- a/hw/cxl/cxl-device-utils.c +++ b/hw/cxl/cxl-device-utils.c @@ -40,6 +40,111 @@ static uint64_t dev_reg_read(void *opaque, hwaddr offse= t, unsigned size) return 0; } =20 +static uint64_t mailbox_reg_read(void *opaque, hwaddr offset, unsigned siz= e) +{ + CXLDeviceState *cxl_dstate =3D opaque; + + switch (size) { + case 8: + return cxl_dstate->mbox_reg_state64[offset / 8]; + case 4: + return cxl_dstate->mbox_reg_state32[offset / 4]; + default: + g_assert_not_reached(); + } +} + +static void mailbox_mem_writel(uint32_t *reg_state, hwaddr offset, + uint64_t value) +{ + switch (offset) { + case A_CXL_DEV_MAILBOX_CTRL: + /* fallthrough */ + case A_CXL_DEV_MAILBOX_CAP: + /* RO register */ + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s Unexpected 32-bit access to 0x%" PRIx64 " (WI)\n= ", + __func__, offset); + break; + } + + reg_state[offset / 4] =3D value; +} + +static void mailbox_mem_writeq(uint64_t *reg_state, hwaddr offset, + uint64_t value) +{ + switch (offset) { + case A_CXL_DEV_MAILBOX_CMD: + break; + case A_CXL_DEV_BG_CMD_STS: + /* BG not supported */ + /* fallthrough */ + case A_CXL_DEV_MAILBOX_STS: + /* Read only register, will get updated by the state machine */ + return; + default: + qemu_log_mask(LOG_UNIMP, + "%s Unexpected 64-bit access to 0x%" PRIx64 " (WI)\n= ", + __func__, offset); + return; + } + + + reg_state[offset / 8] =3D value; +} + +static void mailbox_reg_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + CXLDeviceState *cxl_dstate =3D opaque; + + if (offset >=3D A_CXL_DEV_CMD_PAYLOAD) { + memcpy(cxl_dstate->mbox_reg_state + offset, &value, size); + return; + } + + /* + * Lock is needed to prevent concurrent writes as well as to prevent w= rites + * coming in while the firmware is processing. Without background comm= ands + * or the second mailbox implemented, this serves no purpose since the + * memory access is synchronized at a higher level (per memory region). + */ + RCU_READ_LOCK_GUARD(); + + switch (size) { + case 4: + mailbox_mem_writel(cxl_dstate->mbox_reg_state32, offset, value); + break; + case 8: + mailbox_mem_writeq(cxl_dstate->mbox_reg_state64, offset, value); + break; + default: + g_assert_not_reached(); + } + + if (ARRAY_FIELD_EX32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTR= L, + DOORBELL)) + cxl_process_mailbox(cxl_dstate); +} + +static const MemoryRegionOps mailbox_ops =3D { + .read =3D mailbox_reg_read, + .write =3D mailbox_reg_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + .unaligned =3D false, + }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 8, + }, +}; + static const MemoryRegionOps dev_ops =3D { .read =3D dev_reg_read, .write =3D NULL, /* status register is read only */ @@ -80,20 +185,33 @@ void cxl_device_register_block_init(Object *obj, CXLDe= viceState *cxl_dstate) "cap-array", CXL_DEVICE_REGISTERS_OFFSET - 0); memory_region_init_io(&cxl_dstate->device, obj, &dev_ops, cxl_dstate, "device-status", CXL_DEVICE_REGISTERS_LENGTH); + memory_region_init_io(&cxl_dstate->mailbox, obj, &mailbox_ops, cxl_dst= ate, + "mailbox", CXL_MAILBOX_REGISTERS_LENGTH); =20 memory_region_add_subregion(&cxl_dstate->device_registers, 0, &cxl_dstate->caps); memory_region_add_subregion(&cxl_dstate->device_registers, CXL_DEVICE_REGISTERS_OFFSET, &cxl_dstate->device); + memory_region_add_subregion(&cxl_dstate->device_registers, + CXL_MAILBOX_REGISTERS_OFFSET, + &cxl_dstate->mailbox); } =20 static void device_reg_init_common(CXLDeviceState *cxl_dstate) { } =20 +static void mailbox_reg_init_common(CXLDeviceState *cxl_dstate) +{ + /* 2048 payload size, with no interrupt or background support */ + ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP, + PAYLOAD_SIZE, CXL_MAILBOX_PAYLOAD_SHIFT); + cxl_dstate->payload_size =3D CXL_MAILBOX_MAX_PAYLOAD_SIZE; +} + void cxl_device_register_init_common(CXLDeviceState *cxl_dstate) { uint32_t *cap_hdrs =3D cxl_dstate->caps_reg_state32; - const int cap_count =3D 1; + const int cap_count =3D 2; =20 /* CXL Device Capabilities Array Register */ ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_ID, 0); @@ -102,4 +220,9 @@ void cxl_device_register_init_common(CXLDeviceState *cx= l_dstate) =20 cxl_device_cap_init(cxl_dstate, DEVICE, 1); device_reg_init_common(cxl_dstate); + + cxl_device_cap_init(cxl_dstate, MAILBOX, 2); + mailbox_reg_init_common(cxl_dstate); + + assert(cxl_initialize_mailbox(cxl_dstate) =3D=3D 0); } diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c new file mode 100644 index 0000000000..466055b01a --- /dev/null +++ b/hw/cxl/cxl-mailbox-utils.c @@ -0,0 +1,197 @@ +/* + * CXL Utility library for mailbox interface + * + * Copyright(C) 2020 Intel Corporation. + * + * This work is licensed under the terms of the GNU GPL, version 2. See the + * COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/cxl/cxl.h" +#include "hw/pci/pci.h" +#include "qemu/log.h" +#include "qemu/uuid.h" + +/* + * How to add a new command, example. The command set FOO, with cmd BAR. + * 1. Add the command set and cmd to the enum. + * FOO =3D 0x7f, + * #define BAR 0 + * 2. Forward declare the handler. + * declare_mailbox_handler(FOO_BAR); + * 3. Add the command to the cxl_cmd_set[][] + * CXL_CMD(FOO, BAR, 0, 0), + * 4. Implement your handler + * define_mailbox_handler(FOO_BAR) { ... return CXL_MBOX_SUCCESS; } + * + * + * Writing the handler: + * The handler will provide the &struct cxl_cmd, the &CXLDeviceState, a= nd the + * in/out length of the payload. The handler is responsible for consumi= ng the + * payload from cmd->payload and operating upon it as necessary. It mus= t then + * fill the output data into cmd->payload (overwriting what was there), + * setting the length, and returning a valid return code. + * + * XXX: The handler need not worry about endianess. The payload is read o= ut of + * a register interface that already deals with it. + */ + +/* 8.2.8.4.5.1 Command Return Codes */ +typedef enum { + CXL_MBOX_SUCCESS =3D 0x0, + CXL_MBOX_BG_STARTED =3D 0x1, + CXL_MBOX_INVALID_INPUT =3D 0x2, + CXL_MBOX_UNSUPPORTED =3D 0x3, + CXL_MBOX_INTERNAL_ERROR =3D 0x4, + CXL_MBOX_RETRY_REQUIRED =3D 0x5, + CXL_MBOX_BUSY =3D 0x6, + CXL_MBOX_MEDIA_DISABLED =3D 0x7, + CXL_MBOX_FW_XFER_IN_PROGRESS =3D 0x8, + CXL_MBOX_FW_XFER_OUT_OF_ORDER =3D 0x9, + CXL_MBOX_FW_AUTH_FAILED =3D 0xa, + CXL_MBOX_FW_INVALID_SLOT =3D 0xb, + CXL_MBOX_FW_ROLLEDBACK =3D 0xc, + CXL_MBOX_FW_REST_REQD =3D 0xd, + CXL_MBOX_INVALID_HANDLE =3D 0xe, + CXL_MBOX_INVALID_PA =3D 0xf, + CXL_MBOX_INJECT_POISON_LIMIT =3D 0x10, + CXL_MBOX_PERMANENT_MEDIA_FAILURE =3D 0x11, + CXL_MBOX_ABORTED =3D 0x12, + CXL_MBOX_INVALID_SECURITY_STATE =3D 0x13, + CXL_MBOX_INCORRECT_PASSPHRASE =3D 0x14, + CXL_MBOX_UNSUPPORTED_MAILBOX =3D 0x15, + CXL_MBOX_INVALID_PAYLOAD_LENGTH =3D 0x16, + CXL_MBOX_MAX =3D 0x17 +} ret_code; + +struct cxl_cmd; +typedef ret_code (*opcode_handler)(struct cxl_cmd *cmd, + CXLDeviceState *cxl_dstate, uint16_t *l= en); +struct cxl_cmd { + const char *name; + opcode_handler handler; + ssize_t in; + uint16_t effect; /* Reported in CEL */ + uint8_t *payload; +}; + +#define define_mailbox_handler(name) \ + static ret_code cmd_##name(struct cxl_cmd *cmd, \ + CXLDeviceState *cxl_dstate, uint16_t *len) +#define declare_mailbox_handler(name) define_mailbox_handler(name) + +#define define_mailbox_handler_zeroed(name, size) \ + uint16_t __zero##name =3D size; = \ + static ret_code cmd_##name(struct cxl_cmd *cmd, \ + CXLDeviceState *cxl_dstate, uint16_t *len) \ + { \ + *len =3D __zero##name; = \ + memset(cmd->payload, 0, *len); \ + return CXL_MBOX_SUCCESS; \ + } +#define define_mailbox_handler_const(name, data) \ + static ret_code cmd_##name(struct cxl_cmd *cmd, \ + CXLDeviceState *cxl_dstate, uint16_t *len) \ + { \ + *len =3D sizeof(data); = \ + memcpy(cmd->payload, data, *len); \ + return CXL_MBOX_SUCCESS; \ + } +#define define_mailbox_handler_nop(name) \ + static ret_code cmd_##name(struct cxl_cmd *cmd, \ + CXLDeviceState *cxl_dstate, uint16_t *len) \ + { \ + return CXL_MBOX_SUCCESS; \ + } + +#define CXL_CMD(s, c, in, cel_effect) \ + [s][c] =3D { stringify(s##_##c), cmd_##s##_##c, in, cel_effect } + +static struct cxl_cmd cxl_cmd_set[256][256] =3D {}; + +#undef CXL_CMD + +QemuUUID cel_uuid; + +void cxl_process_mailbox(CXLDeviceState *cxl_dstate) +{ + uint16_t ret =3D CXL_MBOX_SUCCESS; + struct cxl_cmd *cxl_cmd; + uint64_t status_reg; + opcode_handler h; + + /* + * current state of mailbox interface + * mbox_cap_reg =3D cxl_dstate->reg_state32[R_CXL_DEV_MAILBOX_CAP]; + * mbox_ctrl_reg =3D cxl_dstate->reg_state32[R_CXL_DEV_MAILBOX_CTRL]; + * status_reg =3D *(uint64_t *)&cxl_dstate->reg_state[A_CXL_DEV_MAILB= OX_STS]; + */ + uint64_t command_reg =3D + *(uint64_t *)&cxl_dstate->mbox_reg_state[A_CXL_DEV_MAILBOX_CMD]; + + /* Check if we have to do anything */ + if (!ARRAY_FIELD_EX32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CT= RL, + DOORBELL)) { + qemu_log_mask(LOG_UNIMP, "Corrupt internal state for firmware\n"); + return; + } + + uint8_t set =3D FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND_S= ET); + uint8_t cmd =3D FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND); + uint16_t len =3D FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, LENGTH); + cxl_cmd =3D &cxl_cmd_set[set][cmd]; + h =3D cxl_cmd->handler; + if (!h) { + goto handled; + } + + if (len !=3D cxl_cmd->in) { + ret =3D CXL_MBOX_INVALID_PAYLOAD_LENGTH; + } + + cxl_cmd->payload =3D cxl_dstate->mbox_reg_state + A_CXL_DEV_CMD_PAYLOA= D; + ret =3D (*h)(cxl_cmd, cxl_dstate, &len); + assert(len <=3D cxl_dstate->payload_size); + +handled: + /* + * Set the return code + * XXX: it's a 64b register, but we're not setting the vendor, so we c= an get + * away with this + */ + status_reg =3D FIELD_DP64(0, CXL_DEV_MAILBOX_STS, ERRNO, ret); + + /* + * Set the return length + */ + command_reg =3D FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND_S= ET, 0); + command_reg =3D FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND, = 0); + command_reg =3D FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, LENGTH, l= en); + + cxl_dstate->mbox_reg_state64[A_CXL_DEV_MAILBOX_CMD / 8] =3D command_re= g; + cxl_dstate->mbox_reg_state64[A_CXL_DEV_MAILBOX_STS / 8] =3D status_reg; + + /* Tell the host we're done */ + ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL, + DOORBELL, 0); +} + +int cxl_initialize_mailbox(CXLDeviceState *cxl_dstate) +{ + const char *cel_uuidstr =3D "0da9c0b5-bf41-4b78-8f79-96b1623b3f17"; + + for (int i =3D 0; i < 256; i++) { + for (int j =3D 0; j < 256; j++) { + if (cxl_cmd_set[i][j].handler) { + struct cxl_cmd *c =3D &cxl_cmd_set[i][j]; + + cxl_dstate->cel_log[cxl_dstate->cel_size].opcode =3D (i <<= 8) | j; + cxl_dstate->cel_log[cxl_dstate->cel_size].effect =3D c->ef= fect; + cxl_dstate->cel_size++; + } + } + } + + return qemu_uuid_parse(cel_uuidstr, &cel_uuid); +} diff --git a/hw/cxl/meson.build b/hw/cxl/meson.build index 47154d6850..0eca715d10 100644 --- a/hw/cxl/meson.build +++ b/hw/cxl/meson.build @@ -1,4 +1,5 @@ softmmu_ss.add(when: 'CONFIG_CXL', if_true: files( 'cxl-component-utils.c', 'cxl-device-utils.c', + 'cxl-mailbox-utils.c', )) diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h index 23f52c4cf9..362cda40de 100644 --- a/include/hw/cxl/cxl.h +++ b/include/hw/cxl/cxl.h @@ -14,5 +14,8 @@ #include "cxl_component.h" #include "cxl_device.h" =20 +#define COMPONENT_REG_BAR_IDX 0 +#define DEVICE_REG_BAR_IDX 2 + #endif =20 diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index f3bcf19410..af91bec10c 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -80,16 +80,27 @@ typedef struct cxl_device_state { MemoryRegion device_registers; =20 /* mmio for device capabilities array - 8.2.8.2 */ + MemoryRegion device; struct { MemoryRegion caps; uint32_t caps_reg_state32[CXL_CAPS_SIZE / 4]; }; =20 - /* mmio for the device status registers 8.2.8.3 */ - MemoryRegion device; - /* mmio for the mailbox registers 8.2.8.4 */ - MemoryRegion mailbox; + struct { + MemoryRegion mailbox; + uint16_t payload_size; + union { + uint8_t mbox_reg_state[CXL_MAILBOX_REGISTERS_LENGTH]; + uint32_t mbox_reg_state32[CXL_MAILBOX_REGISTERS_LENGTH / 4]; + uint64_t mbox_reg_state64[CXL_MAILBOX_REGISTERS_LENGTH / 8]; + }; + struct { + uint16_t opcode; + uint16_t effect; + } cel_log[1 << 16]; + size_t cel_size; + }; =20 /* memory region for persistent memory, HDM */ MemoryRegion *pmem; @@ -135,6 +146,9 @@ CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE, CXL_DEVIC= E_CAP_HDR1_OFFSET) CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET = + \ CXL_DEVICE_CAP_REG_SIZE) =20 +int cxl_initialize_mailbox(CXLDeviceState *cxl_dstate); +void cxl_process_mailbox(CXLDeviceState *cxl_dstate); + #define cxl_device_cap_init(dstate, reg, cap_id) = \ do { = \ uint32_t *cap_hdrs =3D dstate->caps_reg_state32; = \ @@ -162,6 +176,12 @@ REG32(CXL_DEV_MAILBOX_CTRL, 4) FIELD(CXL_DEV_MAILBOX_CTRL, INT_EN, 1, 1) FIELD(CXL_DEV_MAILBOX_CTRL, BG_INT_EN, 2, 1) =20 +/* XXX: actually a 64b register */ +REG32(CXL_DEV_MAILBOX_CMD, 8) + FIELD(CXL_DEV_MAILBOX_CMD, COMMAND, 0, 8) + FIELD(CXL_DEV_MAILBOX_CMD, COMMAND_SET, 8, 8) + FIELD(CXL_DEV_MAILBOX_CMD, LENGTH, 16, 20) + /* XXX: actually a 64b register */ REG32(CXL_DEV_MAILBOX_STS, 0x10) FIELD(CXL_DEV_MAILBOX_STS, BG_OP, 0, 1) --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612228130; cv=none; d=zohomail.com; s=zohoarc; b=ETi+iWlz7th/666QDB/Kp0phoM99Izog8K4uydlqrn2Hh+anWDOIdCc+/1g8AWEdztyTWfqT4a0IInj434hL5abr025e8QUCHgGPsXTjeFDwhXD0YaKGuKsVhZZYoTgN4XmT3wymzHVv/9KYeNWZEfS/+NYRBxA//+dkAw5/EkE= ARC-Message-Signature: i=1; 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Mon, 01 Feb 2021 20:08:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47130) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k3C-0008Kb-Em for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:14 -0500 Received: from mga18.intel.com ([134.134.136.126]:33366) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k37-0001pl-7n for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:14 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 16:59:59 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 16:59:58 -0800 IronPort-SDR: OXNMgyiP7d7YxOErsq1tcbyVal1g7qJcYEdxIT9T0ysFrlX3Rz5lRPUjSWBB8dMFla0VK7DVPj 0Wh0qqIW6LFw== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457083" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457083" IronPort-SDR: 3VGnYAkJjEEgAa8923cebRlxcrHpnkefdI0AJFfWy06eMgzm70BfHLl4fdOfwVcLelQ0ycQN79 vJGY13dSm2JA== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764071" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 06/31] hw/cxl/device: Add memory device utilities Date: Mon, 1 Feb 2021 16:59:23 -0800 Message-Id: <20210202005948.241655-7-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Memory devices implement extra capabilities on top of CXL devices. This adds support for that. A large part of memory devices is the mailbox/command interface. All of the mailbox handling is done in the mailbox-utils library. Longer term, new CXL devices that are being emulated may want to handle commands differently, and therefore would need a mechanism to opt in/out of the specific generic handlers. As such, this is considered sufficient for now, but may need more depth in the future. Signed-off-by: Ben Widawsky --- hw/cxl/cxl-device-utils.c | 38 ++++++++++++++++++++++++++++++++++++- include/hw/cxl/cxl_device.h | 18 +++++++++++++++++- 2 files changed, 54 insertions(+), 2 deletions(-) diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c index 6602606f3d..639ace523d 100644 --- a/hw/cxl/cxl-device-utils.c +++ b/hw/cxl/cxl-device-utils.c @@ -130,6 +130,31 @@ static void mailbox_reg_write(void *opaque, hwaddr off= set, uint64_t value, cxl_process_mailbox(cxl_dstate); } =20 +static uint64_t mdev_reg_read(void *opaque, hwaddr offset, unsigned size) +{ + uint64_t retval =3D 0; + + retval =3D FIELD_DP64(retval, CXL_MEM_DEV_STS, MEDIA_STATUS, 1); + retval =3D FIELD_DP64(retval, CXL_MEM_DEV_STS, MBOX_READY, 1); + + return retval; +} + +static const MemoryRegionOps mdev_ops =3D { + .read =3D mdev_reg_read, + .write =3D NULL, /* memory device register is read only */ + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + .unaligned =3D false, + }, + .impl =3D { + .min_access_size =3D 8, + .max_access_size =3D 8, + }, +}; + static const MemoryRegionOps mailbox_ops =3D { .read =3D mailbox_reg_read, .write =3D mailbox_reg_write, @@ -187,6 +212,9 @@ void cxl_device_register_block_init(Object *obj, CXLDev= iceState *cxl_dstate) "device-status", CXL_DEVICE_REGISTERS_LENGTH); memory_region_init_io(&cxl_dstate->mailbox, obj, &mailbox_ops, cxl_dst= ate, "mailbox", CXL_MAILBOX_REGISTERS_LENGTH); + memory_region_init_io(&cxl_dstate->memory_device, obj, &mdev_ops, + cxl_dstate, "memory device caps", + CXL_MEMORY_DEVICE_REGISTERS_LENGTH); =20 memory_region_add_subregion(&cxl_dstate->device_registers, 0, &cxl_dstate->caps); @@ -196,6 +224,9 @@ void cxl_device_register_block_init(Object *obj, CXLDev= iceState *cxl_dstate) memory_region_add_subregion(&cxl_dstate->device_registers, CXL_MAILBOX_REGISTERS_OFFSET, &cxl_dstate->mailbox); + memory_region_add_subregion(&cxl_dstate->device_registers, + CXL_MEMORY_DEVICE_REGISTERS_OFFSET, + &cxl_dstate->memory_device); } =20 static void device_reg_init_common(CXLDeviceState *cxl_dstate) { } @@ -208,10 +239,12 @@ static void mailbox_reg_init_common(CXLDeviceState *c= xl_dstate) cxl_dstate->payload_size =3D CXL_MAILBOX_MAX_PAYLOAD_SIZE; } =20 +static void memdev_reg_init_common(CXLDeviceState *cxl_dstate) { } + void cxl_device_register_init_common(CXLDeviceState *cxl_dstate) { uint32_t *cap_hdrs =3D cxl_dstate->caps_reg_state32; - const int cap_count =3D 2; + const int cap_count =3D 3; =20 /* CXL Device Capabilities Array Register */ ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_ID, 0); @@ -224,5 +257,8 @@ void cxl_device_register_init_common(CXLDeviceState *cx= l_dstate) cxl_device_cap_init(cxl_dstate, MAILBOX, 2); mailbox_reg_init_common(cxl_dstate); =20 + cxl_device_cap_init(cxl_dstate, MEMORY_DEVICE, 0x4000); + memdev_reg_init_common(cxl_dstate); + assert(cxl_initialize_mailbox(cxl_dstate) =3D=3D 0); } diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index af91bec10c..0cc5354ba4 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -72,15 +72,20 @@ #define CXL_MAILBOX_REGISTERS_LENGTH \ (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE) =20 +#define CXL_MEMORY_DEVICE_REGISTERS_OFFSET \ + (CXL_MAILBOX_REGISTERS_OFFSET + CXL_MAILBOX_REGISTERS_LENGTH) +#define CXL_MEMORY_DEVICE_REGISTERS_LENGTH 0x8 + #define CXL_MMIO_SIZE \ CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_REGISTERS_LENGTH + \ - CXL_MAILBOX_REGISTERS_LENGTH + CXL_MAILBOX_REGISTERS_LENGTH + CXL_MEMORY_DEVICE_REGISTERS_LENGTH =20 typedef struct cxl_device_state { MemoryRegion device_registers; =20 /* mmio for device capabilities array - 8.2.8.2 */ MemoryRegion device; + MemoryRegion memory_device; struct { MemoryRegion caps; uint32_t caps_reg_state32[CXL_CAPS_SIZE / 4]; @@ -145,6 +150,9 @@ REG32(CXL_DEV_CAP_ARRAY2, 4) /* We're going to pretend = it's 64b */ CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE, CXL_DEVICE_CAP_HDR1_OFFSET) CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET = + \ CXL_DEVICE_CAP_REG_SIZE) +CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MEMORY_DEVICE, + CXL_DEVICE_CAP_HDR1_OFFSET + + CXL_DEVICE_CAP_REG_SIZE * 2) =20 int cxl_initialize_mailbox(CXLDeviceState *cxl_dstate); void cxl_process_mailbox(CXLDeviceState *cxl_dstate); @@ -197,4 +205,12 @@ REG32(CXL_DEV_BG_CMD_STS, 0x18) =20 REG32(CXL_DEV_CMD_PAYLOAD, 0x20) =20 +/* XXX: actually a 64b registers */ +REG32(CXL_MEM_DEV_STS, 0) + FIELD(CXL_MEM_DEV_STS, FATAL, 0, 1) + FIELD(CXL_MEM_DEV_STS, FW_HALT, 1, 1) + FIELD(CXL_MEM_DEV_STS, MEDIA_STATUS, 2, 2) + FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1) + FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3) + #endif --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 01 Feb 2021 20:00:13 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:00 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 16:59:59 -0800 IronPort-SDR: 3dnXW9ms152GRcdciXMyOaskypecV1tu8Cu2VafHtSFtjnu9Vo8M92MQJc+mc8Z2UBuWqUVXPh ow8+FDPjDcGg== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457084" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457084" IronPort-SDR: mmUmXCN6J2aJPC/ijizScyMOh8a5yeq8Jfhd/bSRJrt5lPYT6Uovz6ZiY4ubdqmo2Xo6wUVAgU HCUDzXSmFCYw== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764074" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 07/31] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Date: Mon, 1 Feb 2021 16:59:24 -0800 Message-Id: <20210202005948.241655-8-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Using the previously implemented stubbed helpers, it is now possible to easily add the missing, required commands to the implementation. Signed-off-by: Ben Widawsky --- hw/cxl/cxl-mailbox-utils.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 466055b01a..7c939a1851 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -37,6 +37,14 @@ * a register interface that already deals with it. */ =20 +enum { + EVENTS =3D 0x01, + #define GET_RECORDS 0x0 + #define CLEAR_RECORDS 0x1 + #define GET_INTERRUPT_POLICY 0x2 + #define SET_INTERRUPT_POLICY 0x3 +}; + /* 8.2.8.4.5.1 Command Return Codes */ typedef enum { CXL_MBOX_SUCCESS =3D 0x0, @@ -105,10 +113,23 @@ struct cxl_cmd { return CXL_MBOX_SUCCESS; \ } =20 +define_mailbox_handler_zeroed(EVENTS_GET_RECORDS, 0x20); +define_mailbox_handler_nop(EVENTS_CLEAR_RECORDS); +define_mailbox_handler_zeroed(EVENTS_GET_INTERRUPT_POLICY, 4); +define_mailbox_handler_nop(EVENTS_SET_INTERRUPT_POLICY); + +#define IMMEDIATE_CONFIG_CHANGE (1 << 1) +#define IMMEDIATE_LOG_CHANGE (1 << 4) + #define CXL_CMD(s, c, in, cel_effect) \ [s][c] =3D { stringify(s##_##c), cmd_##s##_##c, in, cel_effect } =20 -static struct cxl_cmd cxl_cmd_set[256][256] =3D {}; +static struct cxl_cmd cxl_cmd_set[256][256] =3D { + CXL_CMD(EVENTS, GET_RECORDS, 1, 0), + CXL_CMD(EVENTS, CLEAR_RECORDS, ~0, IMMEDIATE_LOG_CHANGE), + CXL_CMD(EVENTS, GET_INTERRUPT_POLICY, 0, 0), + CXL_CMD(EVENTS, SET_INTERRUPT_POLICY, 4, IMMEDIATE_CONFIG_CHANGE), +}; =20 #undef CXL_CMD =20 --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612228398; cv=none; d=zohomail.com; s=zohoarc; b=VDNv5fKoVlmhazJ1tf9VRz4Q68oFVo2yB83+BaQg1aq08WoEVd5MUoMv/7RDNtA+TCP4nRrSs3S6GQD+Wj/YuOXs9sCWOSdbIFK4e88hh6yPvJH6GDndXiOIQyJYQ8fbP/MYr71nI2LaPUvTdIHTHk90RDFdb5JstU/kl2JXj1E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612228398; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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d="scan'208";a="581764084" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 08/31] hw/cxl/device: Timestamp implementation (8.2.9.3) Date: Mon, 1 Feb 2021 16:59:25 -0800 Message-Id: <20210202005948.241655-9-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Per spec, timestamp appears to be a free-running counter from a value set by the host via the Set Timestamp command (0301h). There are references to the epoch, which seem like a red herring. Therefore, the implementation implements the timestamp as freerunning counter from the last value that was issued by the Set Timestamp command. Signed-off-by: Ben Widawsky --- hw/cxl/cxl-mailbox-utils.c | 53 +++++++++++++++++++++++++++++++++++++ include/hw/cxl/cxl_device.h | 6 +++++ 2 files changed, 59 insertions(+) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 7c939a1851..3d36614c0c 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -43,6 +43,9 @@ enum { #define CLEAR_RECORDS 0x1 #define GET_INTERRUPT_POLICY 0x2 #define SET_INTERRUPT_POLICY 0x3 + TIMESTAMP =3D 0x03, + #define GET 0x0 + #define SET 0x1 }; =20 /* 8.2.8.4.5.1 Command Return Codes */ @@ -117,8 +120,11 @@ define_mailbox_handler_zeroed(EVENTS_GET_RECORDS, 0x20= ); define_mailbox_handler_nop(EVENTS_CLEAR_RECORDS); define_mailbox_handler_zeroed(EVENTS_GET_INTERRUPT_POLICY, 4); define_mailbox_handler_nop(EVENTS_SET_INTERRUPT_POLICY); +declare_mailbox_handler(TIMESTAMP_GET); +declare_mailbox_handler(TIMESTAMP_SET); =20 #define IMMEDIATE_CONFIG_CHANGE (1 << 1) +#define IMMEDIATE_POLICY_CHANGE (1 << 3) #define IMMEDIATE_LOG_CHANGE (1 << 4) =20 #define CXL_CMD(s, c, in, cel_effect) \ @@ -129,10 +135,57 @@ static struct cxl_cmd cxl_cmd_set[256][256] =3D { CXL_CMD(EVENTS, CLEAR_RECORDS, ~0, IMMEDIATE_LOG_CHANGE), CXL_CMD(EVENTS, GET_INTERRUPT_POLICY, 0, 0), CXL_CMD(EVENTS, SET_INTERRUPT_POLICY, 4, IMMEDIATE_CONFIG_CHANGE), + CXL_CMD(TIMESTAMP, GET, 0, 0), + CXL_CMD(TIMESTAMP, SET, 8, IMMEDIATE_POLICY_CHANGE), }; =20 #undef CXL_CMD =20 +/* + * 8.2.9.3.1 + */ +define_mailbox_handler(TIMESTAMP_GET) +{ + struct timespec ts; + uint64_t delta; + + if (!cxl_dstate->timestamp.set) { + *(uint64_t *)cmd->payload =3D 0; + goto done; + } + + /* First find the delta from the last time the host set the time. */ + clock_gettime(CLOCK_REALTIME, &ts); + delta =3D (ts.tv_sec * NANOSECONDS_PER_SECOND + ts.tv_nsec) - + cxl_dstate->timestamp.last_set; + + /* Then adjust the actual time */ + stq_le_p(cmd->payload, cxl_dstate->timestamp.host_set + delta); + +done: + *len =3D 8; + return CXL_MBOX_SUCCESS; +} + +/* + * 8.2.9.3.2 + */ +define_mailbox_handler(TIMESTAMP_SET) +{ + struct timespec ts; + + clock_gettime(CLOCK_REALTIME, &ts); + + cxl_dstate->timestamp.set =3D true; + cxl_dstate->timestamp.last_set =3D + ts.tv_sec * NANOSECONDS_PER_SECOND + ts.tv_nsec; + + cxl_dstate->timestamp.host_set =3D le64_to_cpu(*(uint64_t *)cmd->paylo= ad); + + *len =3D 0; + return CXL_MBOX_SUCCESS; +} + QemuUUID cel_uuid; =20 void cxl_process_mailbox(CXLDeviceState *cxl_dstate) diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 0cc5354ba4..ca5328a581 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -107,6 +107,12 @@ typedef struct cxl_device_state { size_t cel_size; }; =20 + struct { + bool set; + uint64_t last_set; + uint64_t host_set; + } timestamp; + /* memory region for persistent memory, HDM */ MemoryRegion *pmem; =20 --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612228398; cv=none; d=zohomail.com; s=zohoarc; b=AdILQnRjZfjYIXJhLVoZge6VCSYc1hmly9iRhTVgT7TUKS9xp+FtgtpLIG/8AslbxSZXuecRiybdDBgZgcmUOuWSCMjimypT5XSyY6FV5NmhcWYC4CSOdeO20P6YztatykbgokDAbOSnp9KtXMJZKsq7IWPK6lcPq5nNj4iqxEc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612228398; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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d="scan'208";a="581764114" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 09/31] hw/cxl/device: Add log commands (8.2.9.4) + CEL Date: Mon, 1 Feb 2021 16:59:26 -0800 Message-Id: <20210202005948.241655-10-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" CXL specification provides for the ability to obtain logs from the device. Logs are either spec defined, like the "Command Effects Log" (CEL), or vendor specific. UUIDs are defined for all log types. The CEL is a mechanism to provide information to the host about which commands are supported. It is useful both to determine which spec'd optional commands are supported, as well as provide a list of vendor specified commands that might be used. The CEL is already created as part of mailbox initialization, but here it is now exported to hosts that use these log commands. Signed-off-by: Ben Widawsky --- hw/cxl/cxl-mailbox-utils.c | 67 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 3d36614c0c..3f0ae8b9e5 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -46,6 +46,9 @@ enum { TIMESTAMP =3D 0x03, #define GET 0x0 #define SET 0x1 + LOGS =3D 0x04, + #define GET_SUPPORTED 0x0 + #define GET_LOG 0x1 }; =20 /* 8.2.8.4.5.1 Command Return Codes */ @@ -122,6 +125,8 @@ define_mailbox_handler_zeroed(EVENTS_GET_INTERRUPT_POLI= CY, 4); define_mailbox_handler_nop(EVENTS_SET_INTERRUPT_POLICY); declare_mailbox_handler(TIMESTAMP_GET); declare_mailbox_handler(TIMESTAMP_SET); +declare_mailbox_handler(LOGS_GET_SUPPORTED); +declare_mailbox_handler(LOGS_GET_LOG); =20 #define IMMEDIATE_CONFIG_CHANGE (1 << 1) #define IMMEDIATE_POLICY_CHANGE (1 << 3) @@ -137,6 +142,8 @@ static struct cxl_cmd cxl_cmd_set[256][256] =3D { CXL_CMD(EVENTS, SET_INTERRUPT_POLICY, 4, IMMEDIATE_CONFIG_CHANGE), CXL_CMD(TIMESTAMP, GET, 0, 0), CXL_CMD(TIMESTAMP, SET, 8, IMMEDIATE_POLICY_CHANGE), + CXL_CMD(LOGS, GET_SUPPORTED, 0, 0), + CXL_CMD(LOGS, GET_LOG, 0x18, 0), }; =20 #undef CXL_CMD @@ -188,6 +195,66 @@ define_mailbox_handler(TIMESTAMP_SET) =20 QemuUUID cel_uuid; =20 +/* 8.2.9.4.1 */ +define_mailbox_handler(LOGS_GET_SUPPORTED) +{ + struct { + uint16_t entries; + uint8_t rsvd[6]; + struct { + QemuUUID uuid; + uint32_t size; + } log_entries[1]; + } __attribute__((packed)) *supported_logs =3D (void *)cmd->payload; + _Static_assert(sizeof(*supported_logs) =3D=3D 0x1c, "Bad supported log= size"); + + supported_logs->entries =3D 1; + supported_logs->log_entries[0].uuid =3D cel_uuid; + supported_logs->log_entries[0].size =3D 4 * cxl_dstate->cel_size; + + *len =3D sizeof(*supported_logs); + return CXL_MBOX_SUCCESS; +} + +/* 8.2.9.4.2 */ +define_mailbox_handler(LOGS_GET_LOG) +{ + struct { + QemuUUID uuid; + uint32_t offset; + uint32_t length; + } __attribute__((packed, __aligned__(16))) *get_log =3D (void *)cmd->p= ayload; + + /* + * 8.2.9.4.2 + * The device shall return Invalid Parameter if the Offset or Length + * fields attempt to access beyond the size of the log as reported b= y Get + * Supported Logs. + * + * XXX: Spec is wrong, "Invalid Parameter" isn't a thing. + * XXX: Spec doesn't address incorrect UUID incorrectness. + * + * The CEL buffer is large enough to fit all commands in the emulation= , so + * the only possible failure would be if the mailbox itself isn't big + * enough. + */ + if (get_log->offset + get_log->length > cxl_dstate->payload_size) { + return CXL_MBOX_INVALID_INPUT; + } + + if (!qemu_uuid_is_equal(&get_log->uuid, &cel_uuid)) { + return CXL_MBOX_UNSUPPORTED; + } + + /* Store off everything to local variables so we can wipe out the payl= oad */ + *len =3D get_log->length; + + memmove(cmd->payload, cxl_dstate->cel_log + get_log->offset, + get_log->length); + + return CXL_MBOX_SUCCESS; +} + void cxl_process_mailbox(CXLDeviceState *cxl_dstate) { uint16_t ret =3D CXL_MBOX_SUCCESS; --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612228269; cv=none; d=zohomail.com; s=zohoarc; b=k+QAVeh4ZqiZpG3LlYXdjrAwRt1afnqPRR7JehNk2tSdj/j2dn7aFfa/uGzLvxwfbYzk8TnN6ITyIb5qebMV2RggoAVc/gol+KvFOdY4XCzHyyh+VCfhGlrfYC90cW9c2pn0w7xZVp+aspbYC0pyJACAJvhozAF90+LAPxCDGlo= ARC-Message-Signature: i=1; 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Mon, 01 Feb 2021 20:11:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47160) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k3F-0008NW-Mn for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:18 -0500 Received: from mga18.intel.com ([134.134.136.126]:33366) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k3C-0001pl-Sm for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:17 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:03 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:02 -0800 IronPort-SDR: 9pADIWwGqbGWaNObvIUay0f4+fZpmd4BSzlLItMbpTvj9cZ5Sxy7m7ffHX5OTPHKPXHiPBCjOq uLHOxvop2BBQ== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457095" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457095" IronPort-SDR: 1tYPthxBJp+5IJLJM/J4PqEwVO8Fh0L1C3aEi0byhdJNvuYDCglGaPMNkSJGeCWqz2G802pfdk P8Q9YsIr0zqw== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764121" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 10/31] hw/pxb: Use a type for realizing expanders Date: Mon, 1 Feb 2021 16:59:27 -0800 Message-Id: <20210202005948.241655-11-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This opens up the possibility for more types of expanders (other than PCI and PCIe). We'll need this to create a CXL expander. Signed-off-by: Ben Widawsky --- hw/pci-bridge/pci_expander_bridge.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index aedded1064..232b7ce305 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -24,6 +24,8 @@ #include "hw/boards.h" #include "qom/object.h" =20 +enum BusType { PCI, PCIE }; + #define TYPE_PXB_BUS "pxb-bus" typedef struct PXBBus PXBBus; DECLARE_INSTANCE_CHECKER(PXBBus, PXB_BUS, @@ -214,7 +216,8 @@ static gint pxb_compare(gconstpointer a, gconstpointer = b) 0; } =20 -static void pxb_dev_realize_common(PCIDevice *dev, bool pcie, Error **errp) +static void pxb_dev_realize_common(PCIDevice *dev, enum BusType type, + Error **errp) { PXBDev *pxb =3D convert_to_pxb(dev); DeviceState *ds, *bds =3D NULL; @@ -239,7 +242,7 @@ static void pxb_dev_realize_common(PCIDevice *dev, bool= pcie, Error **errp) } =20 ds =3D qdev_new(TYPE_PXB_HOST); - if (pcie) { + if (type =3D=3D PCIE) { bus =3D pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCI= E_BUS); } else { bus =3D pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_P= XB_BUS); @@ -287,7 +290,7 @@ static void pxb_dev_realize(PCIDevice *dev, Error **err= p) return; } =20 - pxb_dev_realize_common(dev, false, errp); + pxb_dev_realize_common(dev, PCI, errp); } =20 static void pxb_dev_exitfn(PCIDevice *pci_dev) @@ -339,7 +342,7 @@ static void pxb_pcie_dev_realize(PCIDevice *dev, Error = **errp) return; } =20 - pxb_dev_realize_common(dev, true, errp); + pxb_dev_realize_common(dev, PCIE, errp); } =20 static void pxb_pcie_dev_class_init(ObjectClass *klass, void *data) --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; 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Mon, 1 Feb 2021 17:17:24 -0800 (PST) Received: from localhost ([::1]:46632 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6kJn-0007iF-1Q for importer@patchew.org; Mon, 01 Feb 2021 20:17:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47220) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k3U-0008Td-CH for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:32 -0500 Received: from mga18.intel.com ([134.134.136.126]:33362) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k3O-0001oN-I4 for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:32 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:05 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:03 -0800 IronPort-SDR: O+VHADExQJePcc+q/fRqxNlp9KDY/IOpOLI2aXrsmcrdQw3U5EHGZH/qPMF9DCUws1HH+W/EDH 3P9UIjp4J9Iw== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457097" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457097" IronPort-SDR: /gEJ8FGvVSFyktaNEKB3hnudKHJubw7ZcMgXlHJ5KR2Uy1gOlbLHuyn3mX2iMni5NBQYdwUl/H lR7jjJrH1zlw== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764134" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 11/31] hw/pci/cxl: Create a CXL bus type Date: Mon, 1 Feb 2021 16:59:28 -0800 Message-Id: <20210202005948.241655-12-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The easiest way to differentiate a CXL bus, and a PCIE bus is using a flag. A CXL bus, in hardware, is backward compatible with PCIE, and therefore the code tries pretty hard to keep them in sync as much as possible. The other way to implement this would be to try to cast the bus to the correct type. This is less code and useful for debugging via simply looking at the flags. Signed-off-by: Ben Widawsky --- hw/pci-bridge/pci_expander_bridge.c | 9 ++++++++- include/hw/pci/pci_bus.h | 7 +++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 232b7ce305..88c45dc3b5 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -24,7 +24,7 @@ #include "hw/boards.h" #include "qom/object.h" =20 -enum BusType { PCI, PCIE }; +enum BusType { PCI, PCIE, CXL }; =20 #define TYPE_PXB_BUS "pxb-bus" typedef struct PXBBus PXBBus; @@ -35,6 +35,10 @@ DECLARE_INSTANCE_CHECKER(PXBBus, PXB_BUS, DECLARE_INSTANCE_CHECKER(PXBBus, PXB_PCIE_BUS, TYPE_PXB_PCIE_BUS) =20 +#define TYPE_PXB_CXL_BUS "pxb-cxl-bus" +DECLARE_INSTANCE_CHECKER(PXBBus, PXB_CXL_BUS, + TYPE_PXB_CXL_BUS) + struct PXBBus { /*< private >*/ PCIBus parent_obj; @@ -244,6 +248,9 @@ static void pxb_dev_realize_common(PCIDevice *dev, enum= BusType type, ds =3D qdev_new(TYPE_PXB_HOST); if (type =3D=3D PCIE) { bus =3D pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCI= E_BUS); + } else if (type =3D=3D CXL) { + bus =3D pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_CXL= _BUS); + bus->flags |=3D PCI_BUS_CXL; } else { bus =3D pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_P= XB_BUS); bds =3D qdev_new("pci-bridge"); diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h index 347440d42c..eb94e7e85c 100644 --- a/include/hw/pci/pci_bus.h +++ b/include/hw/pci/pci_bus.h @@ -24,6 +24,8 @@ enum PCIBusFlags { PCI_BUS_IS_ROOT =3D 0x0001, /* PCIe extended configuration space is accessible on this bus */ PCI_BUS_EXTENDED_CONFIG_SPACE =3D 0x0002, + /* This is a CXL Type BUS */ + PCI_BUS_CXL =3D 0x0004, }; =20 struct PCIBus { @@ -53,6 +55,11 @@ struct PCIBus { Notifier machine_done; }; =20 +static inline bool pci_bus_is_cxl(PCIBus *bus) +{ + return !!(bus->flags & PCI_BUS_CXL); +} + static inline bool pci_bus_is_root(PCIBus *bus) { return !!(bus->flags & PCI_BUS_IS_ROOT); --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 01 Feb 2021 20:00:29 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:05 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:04 -0800 IronPort-SDR: IUuC+zgA52nm+VDz4idN97wKraFevvCx66BVkDFP8z90KuV0synH1Pv8oBZhLizAB/r0A49OTp JdLHPaAtei/g== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457098" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457098" IronPort-SDR: gHipUTDnqhUjRZG9D/Meip7LOPQ1FilQ3Th8lxVvNpdH6l7mtKwBlaCJFhxcj6vB2PPFJ6x7C2 gmMIwjsPVelw== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764150" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 12/31] hw/pxb: Allow creation of a CXL PXB (host bridge) Date: Mon, 1 Feb 2021 16:59:29 -0800 Message-Id: <20210202005948.241655-13-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This works like adding a typical pxb device, except the name is 'pxb-cxl' instead of 'pxb-pcie'. An example command line would be as follows: -device pxb-cxl,id=3Dcxl.0,bus=3D"pcie.0",bus_nr=3D1 A CXL PXB is backward compatible with PCIe. What this means in practice is that an operating system that is unaware of CXL should still be able to enumerate this topology as if it were PCIe. One can create multiple CXL PXB host bridges, but a host bridge can only be connected to the main root bus. Host bridges cannot appear elsewhere in the topology. Note that as of this patch, the ACPI tables needed for the host bridge (specifically, an ACPI object in _SB named ACPI0016 and the CEDT) aren't created. So while this patch internally creates it, it cannot be properly used by an operating system or other system software. Upcoming patches will allow creating multiple host bridges. v2: Remove vendor and device ID (Ben) Signed-off-by: Ben Widawsky --- hw/pci-bridge/pci_expander_bridge.c | 67 ++++++++++++++++++++++++++++- hw/pci/pci.c | 7 +++ include/hw/pci/pci.h | 6 +++ 3 files changed, 78 insertions(+), 2 deletions(-) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 88c45dc3b5..b42592e1ff 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -56,6 +56,10 @@ DECLARE_INSTANCE_CHECKER(PXBDev, PXB_DEV, DECLARE_INSTANCE_CHECKER(PXBDev, PXB_PCIE_DEV, TYPE_PXB_PCIE_DEVICE) =20 +#define TYPE_PXB_CXL_DEVICE "pxb-cxl" +DECLARE_INSTANCE_CHECKER(PXBDev, PXB_CXL_DEV, + TYPE_PXB_CXL_DEVICE) + struct PXBDev { /*< private >*/ PCIDevice parent_obj; @@ -67,6 +71,11 @@ struct PXBDev { =20 static PXBDev *convert_to_pxb(PCIDevice *dev) { + /* A CXL PXB's parent bus is PCIe, so the normal check won't work */ + if (object_dynamic_cast(OBJECT(dev), TYPE_PXB_CXL_DEVICE)) { + return PXB_CXL_DEV(dev); + } + return pci_bus_is_express(pci_get_bus(dev)) ? PXB_PCIE_DEV(dev) : PXB_DEV(dev); } @@ -111,11 +120,20 @@ static const TypeInfo pxb_pcie_bus_info =3D { .class_init =3D pxb_bus_class_init, }; =20 +static const TypeInfo pxb_cxl_bus_info =3D { + .name =3D TYPE_PXB_CXL_BUS, + .parent =3D TYPE_CXL_BUS, + .instance_size =3D sizeof(PXBBus), + .class_init =3D pxb_bus_class_init, +}; + static const char *pxb_host_root_bus_path(PCIHostState *host_bridge, PCIBus *rootbus) { - PXBBus *bus =3D pci_bus_is_express(rootbus) ? - PXB_PCIE_BUS(rootbus) : PXB_BUS(rootbus); + PXBBus *bus =3D pci_bus_is_cxl(rootbus) ? + PXB_CXL_BUS(rootbus) : + pci_bus_is_express(rootbus) ? PXB_PCIE_BUS(rootbus) : + PXB_BUS(rootbus); =20 snprintf(bus->bus_path, 8, "0000:%02x", pxb_bus_num(rootbus)); return bus->bus_path; @@ -380,13 +398,58 @@ static const TypeInfo pxb_pcie_dev_info =3D { }, }; =20 +static void pxb_cxl_dev_realize(PCIDevice *dev, Error **errp) +{ + /* A CXL PXB's parent bus is still PCIe */ + if (!pci_bus_is_express(pci_get_bus(dev))) { + error_setg(errp, "pxb-cxl devices cannot reside on a PCI bus"); + return; + } + + pxb_dev_realize_common(dev, CXL, errp); +} + +static void pxb_cxl_dev_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->realize =3D pxb_cxl_dev_realize; + k->exit =3D pxb_dev_exitfn; + /* + * XXX: These types of bridges don't actually show up in the hierarchy= so + * vendor, device, class, etc. ids are intentionally left out. + */ + + dc->desc =3D "CXL Host Bridge"; + device_class_set_props(dc, pxb_dev_properties); + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + + /* Host bridges aren't hotpluggable. FIXME: spec reference */ + dc->hotpluggable =3D false; +} + +static const TypeInfo pxb_cxl_dev_info =3D { + .name =3D TYPE_PXB_CXL_DEVICE, + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(PXBDev), + .class_init =3D pxb_cxl_dev_class_init, + .interfaces =3D + (InterfaceInfo[]){ + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + {}, + }, +}; + static void pxb_register_types(void) { type_register_static(&pxb_bus_info); type_register_static(&pxb_pcie_bus_info); + type_register_static(&pxb_cxl_bus_info); type_register_static(&pxb_host_info); type_register_static(&pxb_dev_info); type_register_static(&pxb_pcie_dev_info); + type_register_static(&pxb_cxl_dev_info); } =20 type_init(pxb_register_types) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index a45ca326ed..adbe8aa260 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -222,6 +222,12 @@ static const TypeInfo pcie_bus_info =3D { .class_init =3D pcie_bus_class_init, }; =20 +static const TypeInfo cxl_bus_info =3D { + .name =3D TYPE_CXL_BUS, + .parent =3D TYPE_PCIE_BUS, + .class_init =3D pcie_bus_class_init, +}; + static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); static void pci_update_mappings(PCIDevice *d); static void pci_irq_handler(void *opaque, int irq_num, int level); @@ -2825,6 +2831,7 @@ static void pci_register_types(void) { type_register_static(&pci_bus_info); type_register_static(&pcie_bus_info); + type_register_static(&cxl_bus_info); type_register_static(&conventional_pci_interface_info); type_register_static(&cxl_interface_info); type_register_static(&pcie_interface_info); diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 528cef341c..bde3697bee 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -406,6 +406,7 @@ typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, = int pin); #define TYPE_PCI_BUS "PCI" OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS) #define TYPE_PCIE_BUS "PCIE" +#define TYPE_CXL_BUS "CXL" =20 bool pci_bus_is_express(PCIBus *bus); =20 @@ -754,6 +755,11 @@ static inline void pci_irq_pulse(PCIDevice *pci_dev) pci_irq_deassert(pci_dev); } =20 +static inline int pci_is_cxl(const PCIDevice *d) +{ + return d->cap_present & QEMU_PCIE_CAP_CXL; +} + static inline int pci_is_express(const PCIDevice *d) { return d->cap_present & QEMU_PCI_CAP_EXPRESS; --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612228724; cv=none; d=zohomail.com; s=zohoarc; b=XjSJf0kCoAwZTofwKEy8uYZPBEtDs6Rp5PAzrMoPT7+RRR0MTm9+93CpLEcUnRNCMb9kBvGzonZ9NPlSbyh0DG4ig/GJ0IqMBeEFdkyI3Om23uLzzm1wEU3RSkldbeNLUS9ajGKY42AXcwBsNYJ5aCiCS67SQs+CyTo3eITo5hM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612228724; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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d="scan'208";a="581764159" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 13/31] qtest: allow DSDT acpi table changes Date: Mon, 1 Feb 2021 16:59:30 -0800 Message-Id: <20210202005948.241655-14-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Ben Widawsky --- tests/qtest/bios-tables-test-allowed-diff.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..5c695cdf37 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,22 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/pc/DSDT", +"tests/data/acpi/pc/DSDT.acpihmat", +"tests/data/acpi/pc/DSDT.bridge", +"tests/data/acpi/pc/DSDT.cphp", +"tests/data/acpi/pc/DSDT.dimmpxm", +"tests/data/acpi/pc/DSDT.hpbridge", +"tests/data/acpi/pc/DSDT.hpbrroot", +"tests/data/acpi/pc/DSDT.ipmikcs", +"tests/data/acpi/pc/DSDT.memhp", +"tests/data/acpi/pc/DSDT.numamem", +"tests/data/acpi/pc/DSDT.roothp", +"tests/data/acpi/q35/DSDT", +"tests/data/acpi/q35/DSDT.acpihmat", +"tests/data/acpi/q35/DSDT.bridge", +"tests/data/acpi/q35/DSDT.cphp", +"tests/data/acpi/q35/DSDT.dimmpxm", +"tests/data/acpi/q35/DSDT.ipmibt", +"tests/data/acpi/q35/DSDT.memhp", +"tests/data/acpi/q35/DSDT.mmio64", +"tests/data/acpi/q35/DSDT.numamem", +"tests/data/acpi/q35/DSDT.tis", --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612228643; cv=none; d=zohomail.com; s=zohoarc; b=HPlRlQpjQcrJ7/+EGhculiB64OBNCD5PuZSpd/e/SE8JoG5hC5AxIoEQyS2NGDjO7MhKx38SG89/MufAK6NNNrGao+OuvqRZTlxgJMOfvrT+3QRFjbS9Yi3sPTsrZwhWL3UXKk7PNqKebNC+kD1ADMsKmWv4L4qCfdXzjKmD0+U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612228643; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+8OYv+zKAtrvea/Ch9GvrJ59kZFx8XqNko7mxuEOsOc=; b=jRxvsUBrn9y1nC0V4/gmQ0N51Ye4SHIYH58oZ/UDegXE2dlzHQrneBrpClL8B2OcFhx3rMKZcYzLW7ueniimYlsdnzf++IccjfehmvK6nv29eVpKB9gq/66j55JFzS9zicz5in3ifUTR7I0WoaszHlKK6R+q5QQXlsrg7mynn2s= ARC-Authentication-Results: i=1; mx.zohomail.com; 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Mon, 01 Feb 2021 20:00:42 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:07 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:06 -0800 IronPort-SDR: clkptAjWh/dotHQGGS07WVcCbttpst25HP9paxfz1IN936YMIdwOdpZngXE3+LCjCzeoKQQkco t2aS7c1swUaw== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457103" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457103" IronPort-SDR: 55TZ0ovYLRe5Qef1wyRQSM8qlunqtTzUIbMUttc0SZJ0amwZRlJdbHAJCl36WcG2WDZ4Dqs+TK Up1ujQQ1yXfw== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764166" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 14/31] acpi/pci: Consolidate host bridge setup Date: Mon, 1 Feb 2021 16:59:31 -0800 Message-Id: <20210202005948.241655-15-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This cleanup will make it easier to add support for CXL to the mix. Signed-off-by: Ben Widawsky --- hw/i386/acpi-build.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index f56d699c7f..cf6eb54c22 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1194,6 +1194,20 @@ static void build_smb0(Aml *table, I2CBus *smbus, in= t devnr, int func) aml_append(table, scope); } =20 +enum { PCI, PCIE }; +static void init_pci_acpi(Aml *dev, int uid, int type) +{ + if (type =3D=3D PCI) { + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); + aml_append(dev, aml_name_decl("_UID", aml_int(uid))); + } else { + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); + aml_append(dev, aml_name_decl("_UID", aml_int(uid))); + aml_append(dev, build_q35_osc_method()); + } +} + static void build_dsdt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm, AcpiMiscInfo *misc, @@ -1222,9 +1236,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, if (misc->is_piix4) { sb_scope =3D aml_scope("_SB"); dev =3D aml_device("PCI0"); - aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); + init_pci_acpi(dev, 0, PCI); aml_append(dev, aml_name_decl("_ADR", aml_int(0))); - aml_append(dev, aml_name_decl("_UID", aml_int(0))); aml_append(sb_scope, dev); aml_append(dsdt, sb_scope); =20 @@ -1238,11 +1251,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } else { sb_scope =3D aml_scope("_SB"); dev =3D aml_device("PCI0"); - aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); - aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); + init_pci_acpi(dev, 0, PCIE); aml_append(dev, aml_name_decl("_ADR", aml_int(0))); - aml_append(dev, aml_name_decl("_UID", aml_int(0))); - aml_append(dev, build_q35_osc_method()); aml_append(sb_scope, dev); =20 if (pm->smi_on_cpuhp) { @@ -1345,15 +1355,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, =20 scope =3D aml_scope("\\_SB"); dev =3D aml_device("PC%.02X", bus_num); - aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); - if (pci_bus_is_express(bus)) { - aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"= ))); - aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"= ))); - aml_append(dev, build_q35_osc_method()); - } else { - aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"= ))); - } + init_pci_acpi(dev, bus_num, pci_bus_is_express(bus) ? PCIE : P= CI); =20 if (numa_node !=3D NUMA_NODE_UNASSIGNED) { aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612228891; cv=none; d=zohomail.com; s=zohoarc; b=bJxRX6w/tr+eyTHtCTNG/fParkQ4MkxcwsktGwICReqZzuKZsNnOHPgcBDDjuWedonSUngnih10Awg09Y1ML42KVIfHju8WdGvUvJmM9boZhqkhibduio43/bEZB2VUBDFosp0oifjpG93sPVCr6M5scbIVyu2va6BnIiEM3i/o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612228891; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yFhAeSNqdJUl4C0EeKlMKec3MNMNYnjbBwXei3zTXdU=; b=RvalgvtjXZ4on+d1SMKnMsbzsOqQAvMuR+hQA6I0w8XZ5M6CYmHuuko6fpTyn/DJDiHN/FDvR91BMjAprpWm8jEpal8abkN63cLcEoV8Xi7/SCcDPO0RA5AVRSA95x7XmWUBuJiH4hiyaektn6Q75uLdIkkrID+xsYKO1OehaUU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612228891343910.066992431485; Mon, 1 Feb 2021 17:21:31 -0800 (PST) Received: from localhost ([::1]:58162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6kNm-0004PE-4t for importer@patchew.org; Mon, 01 Feb 2021 20:21:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47272) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k3h-00006F-Dp for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:45 -0500 Received: from mga18.intel.com ([134.134.136.126]:33362) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k3e-0001oN-OV for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:45 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:08 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:07 -0800 IronPort-SDR: MnhFke9bW5tfmgHtx0FygDkY+nwPLe0SX3V6louz7ypQWJu5kTf2FXcby0huP8BzrrYjDd3PsP pqjd4WsCeJAg== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457105" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457105" IronPort-SDR: /z+0pVwxwNMP7YQ71xrIx2eOCE87V6iPya0VYdTKpVRu5XlaZMS1WjFSd6MB5O4hAR/gVp+vLf kaOBinkJf38w== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764177" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 15/31] tests/acpi: remove stale allowed tables Date: Mon, 1 Feb 2021 16:59:32 -0800 Message-Id: <20210202005948.241655-16-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SUBJ_WIPE_DEBT=1.004 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Scope (_SB) { Device (PCI0) { Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardwa= re ID - Name (_ADR, Zero) // _ADR: Address Name (_UID, Zero) // _UID: Unique ID + Name (_ADR, Zero) // _ADR: Address Signed-off-by: Ben Widawsky --- tests/data/acpi/pc/DSDT | Bin 5065 -> 5065 bytes tests/data/acpi/pc/DSDT.acpihmat | Bin 6390 -> 6390 bytes tests/data/acpi/pc/DSDT.bridge | Bin 6924 -> 6924 bytes tests/data/acpi/pc/DSDT.cphp | Bin 5529 -> 5529 bytes tests/data/acpi/pc/DSDT.dimmpxm | Bin 6719 -> 6719 bytes tests/data/acpi/pc/DSDT.hpbridge | Bin 5026 -> 5026 bytes tests/data/acpi/pc/DSDT.hpbrroot | Bin 3084 -> 3084 bytes tests/data/acpi/pc/DSDT.ipmikcs | Bin 5137 -> 5137 bytes tests/data/acpi/pc/DSDT.memhp | Bin 6424 -> 6424 bytes tests/data/acpi/pc/DSDT.numamem | Bin 5071 -> 5071 bytes tests/data/acpi/pc/DSDT.roothp | Bin 5261 -> 5261 bytes tests/data/acpi/q35/DSDT | Bin 7801 -> 7801 bytes tests/data/acpi/q35/DSDT.acpihmat | Bin 9126 -> 9126 bytes tests/data/acpi/q35/DSDT.bridge | Bin 7819 -> 7819 bytes tests/data/acpi/q35/DSDT.cphp | Bin 8265 -> 8265 bytes tests/data/acpi/q35/DSDT.dimmpxm | Bin 9455 -> 9455 bytes tests/data/acpi/q35/DSDT.ipmibt | Bin 7876 -> 7876 bytes tests/data/acpi/q35/DSDT.memhp | Bin 9160 -> 9160 bytes tests/data/acpi/q35/DSDT.mmio64 | Bin 8932 -> 8932 bytes tests/data/acpi/q35/DSDT.numamem | Bin 7807 -> 7807 bytes tests/qtest/bios-tables-test-allowed-diff.h | 21 -------------------- 21 files changed, 21 deletions(-) diff --git a/tests/data/acpi/pc/DSDT b/tests/data/acpi/pc/DSDT index f6173df1d598767a79aa34ad7585ad7d45c5d4f3..b516745128e3f1a297b6327e905= 7026a2d16229c 100644 GIT binary patch delta 20 bcmX@9eo}oxJ7=3Dh;3j;^Iqf5}n36{bDOsEE~ delta 20 bcmX@9eo}oxJEx;d5CcbisHe-u36{bDOlAhI diff --git a/tests/data/acpi/pc/DSDT.acpihmat b/tests/data/acpi/pc/DSDT.acp= ihmat index 67f3f7249eaaa9404ebf0f2d0a324b8c8e3bd445..aeae285c6434ae6cf3c53660e34= 425727a497871 100644 GIT binary patch delta 20 bcmexn_|0%aJ7=3Dh;3j;^Iqf5}n3271lRUHRT delta 20 bcmexn_|0%aJEx;d5CcbisHe-u3271lRNDtm diff --git a/tests/data/acpi/pc/DSDT.bridge b/tests/data/acpi/pc/DSDT.bridge index 643390f4c4138b37fc481656d3f555d0eeedcb02..4cd26a87dd11d96e10bf6de786b= 9d56ebfe0a4f9 100644 GIT binary patch delta 20 bcmeA%>oJ?q&Kc_I!oU&l=3Dn}MXLX8vvMneXi delta 20 bcmeA%>oJ?q>k9#J~|B>glp^LX8vvMgaz# diff --git a/tests/data/acpi/pc/DSDT.cphp b/tests/data/acpi/pc/DSDT.cphp index 1ddcf7d8812f5d8d4d38fe7e7b35fd5885806046..fecb784812cbb2308ef58acf4a2= c580f56d35c39 100644 GIT binary patch delta 20 bcmbQKJyUx^J7=3Dh;3j;^Iqf5}n37nz;MY;wk delta 20 bcmbQKJyUx^JEx;d5CcbisHe-u37nz;MR*1% diff --git a/tests/data/acpi/pc/DSDT.dimmpxm b/tests/data/acpi/pc/DSDT.dimm= pxm index c44385cc01879324738ffb7f997b8cdd762cbf97..f2c31e150ead16e4931367a6dab= 42704950a21e9 100644 GIT binary patch delta 20 bcmdmQvfpGvJ7=3Dh;3j;^Iqf5}n3F{>RP4WjY delta 20 bcmdmQvfpGvJEx;d5CcbisHe-u3F{>RO|Sglp^LJcglp^!e3zkMNS6( diff --git a/tests/data/acpi/q35/DSDT b/tests/data/acpi/q35/DSDT index d25cd7072932886d6967f4023faac1e1fa6e836c..17e2aebde98e0a3161d93e9b2e2= 00737b13699ac 100644 GIT binary patch delta 21 dcmexq^V4R+R}_#>)Z#RX+z< diff --git a/tests/data/acpi/q35/DSDT.acpihmat b/tests/data/acpi/q35/DSDT.a= cpihmat index 722e06af83abcde203a2b96a8ec81fd3bab9fc98..7b3d659352a0923822f6a5db1db= d0a6ad853c446 100644 GIT binary patch delta 21 dcmZ4HzRZ2XR}__9y`WOK1lA diff --git a/tests/data/acpi/q35/DSDT.bridge b/tests/data/acpi/q35/DSDT.bri= dge index 06bac139d668ddfc7914e258b471a303c9dbd192..5961b55b1067c3090b2f1f4cd33= 86d71efee241d 100644 GIT binary patch delta 21 ccmeCS?Y5mTdE(4QHja2lmmr4CQjCSN09fk=3D{{R30 delta 19 acmeCS?Y5mTnZ?m1h+*Qy=3DFL)!g|Yxf4F-?^ diff --git a/tests/data/acpi/q35/DSDT.cphp b/tests/data/acpi/q35/DSDT.cphp index 2b933ac482e6883efccbd7d6c96089602f2c0b4d..09c92d52f92bb346ed807945b96= 38cad958446f8 100644 GIT binary patch delta 21 dcmX@R}_>dONFPN@dc diff --git a/tests/data/acpi/q35/DSDT.dimmpxm b/tests/data/acpi/q35/DSDT.di= mmpxm index bd8f8305b028ef20f9b6d1a0c69ac428d027e3d1..1da97afb32dddafefe7f27934ac= bcb7d56a67489 100644 GIT binary patch delta 21 dcmaFw`QCHFR}_UR4GFR)YuH diff --git a/tests/data/acpi/q35/DSDT.ipmibt b/tests/data/acpi/q35/DSDT.ipm= ibt index a8f868e23c25688ab1c0371016c071f23e9d732f..c7e68432b66e7b4d03284c882c6= 5bbf3066825dc 100644 GIT binary patch delta 21 dcmX?Nd&G9aR}_u95`+PJ;(K diff --git a/tests/data/acpi/q35/DSDT.memhp b/tests/data/acpi/q35/DSDT.memhp index 9a802e4c67022386442976d5cb997ea3fc57b58f..3af457dd550461b2d2ea85aa85d= 7740452913b34 100644 GIT binary patch delta 21 dcmX@%e!_jiR}_u2TX4P;>`i diff --git a/tests/data/acpi/q35/DSDT.mmio64 b/tests/data/acpi/q35/DSDT.mmi= o64 index 948c2dc7264c31932b490ca00691a7c4d9aefdb0..a4d20f676ac173e6846dcd4e076= 220d512215963 100644 GIT binary patch delta 21 dcmaFj`owj@R}_o>Bw=3DR96SD diff --git a/tests/data/acpi/q35/DSDT.numamem b/tests/data/acpi/q35/DSDT.nu= mamem index 44ec1b0af400da6d298284aa959aa38add7e6dd5..bbab0d10a2a064528519fa69e90= c799430129b75 100644 GIT binary patch delta 21 dcmexw^WSE|R}_rpf{URwD;$ diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index 5c695cdf37..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,22 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/pc/DSDT", -"tests/data/acpi/pc/DSDT.acpihmat", -"tests/data/acpi/pc/DSDT.bridge", -"tests/data/acpi/pc/DSDT.cphp", -"tests/data/acpi/pc/DSDT.dimmpxm", -"tests/data/acpi/pc/DSDT.hpbridge", -"tests/data/acpi/pc/DSDT.hpbrroot", -"tests/data/acpi/pc/DSDT.ipmikcs", -"tests/data/acpi/pc/DSDT.memhp", -"tests/data/acpi/pc/DSDT.numamem", -"tests/data/acpi/pc/DSDT.roothp", -"tests/data/acpi/q35/DSDT", -"tests/data/acpi/q35/DSDT.acpihmat", -"tests/data/acpi/q35/DSDT.bridge", -"tests/data/acpi/q35/DSDT.cphp", -"tests/data/acpi/q35/DSDT.dimmpxm", -"tests/data/acpi/q35/DSDT.ipmibt", -"tests/data/acpi/q35/DSDT.memhp", -"tests/data/acpi/q35/DSDT.mmio64", -"tests/data/acpi/q35/DSDT.numamem", -"tests/data/acpi/q35/DSDT.tis", --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612227760; cv=none; d=zohomail.com; s=zohoarc; b=ScRv1wrzxYlrFjdMmJ3RswR1Scl78wThwNJdQACq0/wfcqAQqZeYFp+Vj5KWbPLLaMKs5ioZfeqJiEsIdj88MqoKuB8SKp9KTuohuhtSdWGMLdWnWIhZEslhh5VKUsIQ/Gu+yesfe4ZohjJvN0GGdV/+/j/iPXoLa5G+GUy1W5w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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id 1l6k5W-0001xs-R8 for importer@patchew.org; Mon, 01 Feb 2021 20:02:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47276) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k3i-00006t-Em for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:46 -0500 Received: from mga18.intel.com ([134.134.136.126]:33366) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k3f-0001pl-Fs for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:46 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:09 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:08 -0800 IronPort-SDR: Tp41OQs5jUbJCfKp5inVisNbN9pEt2NtViE8JIAfFyQlCuD8rAkNic8r0TtepwINvikpan8EZt /Nt07WiKSnXA== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457107" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457107" IronPort-SDR: 66pgPRPKliFHeiZ9KLirc1el9oCBXFzHR6lTahiifdmdUV2pCMs1fbyxkQc8gWYBGyTerYSDlf NLuB6opBQpcA== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764190" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 16/31] hw/pci: Plumb _UID through host bridges Date: Mon, 1 Feb 2021 16:59:33 -0800 Message-Id: <20210202005948.241655-17-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Currently, QEMU makes _UID equivalent to the bus number (_BBN). While there is nothing wrong with doing it this way, CXL spec has a heavy reliance on _UID to identify host bridges and there is no link to the bus number. Having a distinct UID solves two problems. The first is it gets us around the limitation of 256 (current max bus number). The second is it allows us to replicate hardware configurations where bus number and uid aren't equivalent. The latter has benefits for our development and debugging using QEMU. The other way to do this would be to implement the expanded bus numbering, but having an explicit uid makes more sense when trying to replicate real hardware configurations. The QEMU commandline to utilize this would be: -device pxb-cxl,id=3Dcxl.0,bus=3D"pcie.0",bus_nr=3D1,uid=3Dx Signed-off-by: Ben Widawsky -- I'm guessing this patch will be somewhat controversial. For early CXL work, this can be dropped without too much heartache. --- hw/i386/acpi-build.c | 3 ++- hw/pci-bridge/pci_expander_bridge.c | 19 +++++++++++++++++++ hw/pci/pci.c | 11 +++++++++++ include/hw/pci/pci.h | 1 + include/hw/pci/pci_bus.h | 1 + 5 files changed, 34 insertions(+), 1 deletion(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index cf6eb54c22..145a503e92 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1343,6 +1343,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, QLIST_FOREACH(bus, &bus->child, sibling) { uint8_t bus_num =3D pci_bus_num(bus); uint8_t numa_node =3D pci_bus_numa_node(bus); + int32_t uid =3D pci_bus_uid(bus); =20 /* look only for expander root buses */ if (!pci_bus_is_root(bus)) { @@ -1356,7 +1357,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, scope =3D aml_scope("\\_SB"); dev =3D aml_device("PC%.02X", bus_num); aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); - init_pci_acpi(dev, bus_num, pci_bus_is_express(bus) ? PCIE : P= CI); + init_pci_acpi(dev, uid, pci_bus_is_express(bus) ? PCIE : PCI); =20 if (numa_node !=3D NUMA_NODE_UNASSIGNED) { aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index b42592e1ff..5021b60435 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -67,6 +67,7 @@ struct PXBDev { =20 uint8_t bus_nr; uint16_t numa_node; + int32_t uid; }; =20 static PXBDev *convert_to_pxb(PCIDevice *dev) @@ -98,12 +99,20 @@ static uint16_t pxb_bus_numa_node(PCIBus *bus) return pxb->numa_node; } =20 +static int32_t pxb_bus_uid(PCIBus *bus) +{ + PXBDev *pxb =3D convert_to_pxb(bus->parent_dev); + + return pxb->uid; +} + static void pxb_bus_class_init(ObjectClass *class, void *data) { PCIBusClass *pbc =3D PCI_BUS_CLASS(class); =20 pbc->bus_num =3D pxb_bus_num; pbc->numa_node =3D pxb_bus_numa_node; + pbc->uid =3D pxb_bus_uid; } =20 static const TypeInfo pxb_bus_info =3D { @@ -329,6 +338,7 @@ static Property pxb_dev_properties[] =3D { /* Note: 0 is not a legal PXB bus number. */ DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0), DEFINE_PROP_UINT16("numa_node", PXBDev, numa_node, NUMA_NODE_UNASSIGNE= D), + DEFINE_PROP_INT32("uid", PXBDev, uid, -1), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -400,12 +410,21 @@ static const TypeInfo pxb_pcie_dev_info =3D { =20 static void pxb_cxl_dev_realize(PCIDevice *dev, Error **errp) { + PXBDev *pxb =3D convert_to_pxb(dev); + /* A CXL PXB's parent bus is still PCIe */ if (!pci_bus_is_express(pci_get_bus(dev))) { error_setg(errp, "pxb-cxl devices cannot reside on a PCI bus"); return; } =20 + if (pxb->uid < 0) { + error_setg(errp, "pxb-cxl devices must have a valid uid (0-2147483= 647)"); + return; + } + + /* FIXME: Check that uid doesn't collide with UIDs of other host bridg= es */ + pxb_dev_realize_common(dev, CXL, errp); } =20 diff --git a/hw/pci/pci.c b/hw/pci/pci.c index adbe8aa260..bf019d91a0 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -170,6 +170,11 @@ static uint16_t pcibus_numa_node(PCIBus *bus) return NUMA_NODE_UNASSIGNED; } =20 +static int32_t pcibus_uid(PCIBus *bus) +{ + return -1; +} + static void pci_bus_class_init(ObjectClass *klass, void *data) { BusClass *k =3D BUS_CLASS(klass); @@ -184,6 +189,7 @@ static void pci_bus_class_init(ObjectClass *klass, void= *data) =20 pbc->bus_num =3D pcibus_num; pbc->numa_node =3D pcibus_numa_node; + pbc->uid =3D pcibus_uid; } =20 static const TypeInfo pci_bus_info =3D { @@ -530,6 +536,11 @@ int pci_bus_numa_node(PCIBus *bus) return PCI_BUS_GET_CLASS(bus)->numa_node(bus); } =20 +int pci_bus_uid(PCIBus *bus) +{ + return PCI_BUS_GET_CLASS(bus)->uid(bus); +} + static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, const VMStateField *field) { diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index bde3697bee..a46de48ccd 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -463,6 +463,7 @@ static inline int pci_dev_bus_num(const PCIDevice *dev) } =20 int pci_bus_numa_node(PCIBus *bus); +int pci_bus_uid(PCIBus *bus); void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d, void *opaqu= e), void *opaque); diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h index eb94e7e85c..3c9fbc55bb 100644 --- a/include/hw/pci/pci_bus.h +++ b/include/hw/pci/pci_bus.h @@ -17,6 +17,7 @@ struct PCIBusClass { =20 int (*bus_num)(PCIBus *bus); uint16_t (*numa_node)(PCIBus *bus); + int32_t (*uid)(PCIBus *bus); }; =20 enum PCIBusFlags { --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612227953; cv=none; d=zohomail.com; s=zohoarc; b=eWZqlUJBj+I3q0S/Q6kA7ag46TF4fzjXPhaEw4ZdnT1RLP/SK52gNR8DT3XAG6fIpmbCXwQ4PClrw7V332heTGfa9gHVTUoaw2AhndLm+dG3hEy7QuN9eZ9g2vMT5vCCdKn0sdBLNUeQxN81vfKyQAbSyxBvdrig/KTqd7uxSLI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612227953; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kWAJM+qdfgy4vasvD3yGhz5hqkVwAPLSxPp47Yhym+I=; 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d="scan'208";a="581764196" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 17/31] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Date: Mon, 1 Feb 2021 16:59:34 -0800 Message-Id: <20210202005948.241655-18-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" CXL host bridges themselves may have MMIO. Since host bridges don't have a BAR they are treated as special for MMIO. Signed-off-by: Ben Widawsky -- It's arbitrarily chosen here to pick 0xD0000000 as the base for the host bridge MMIO. I'm not sure what the right way to find free space for platform hardcoded things like this is. --- hw/pci-bridge/pci_expander_bridge.c | 53 ++++++++++++++++++++++++++++- include/hw/cxl/cxl.h | 2 ++ 2 files changed, 54 insertions(+), 1 deletion(-) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 5021b60435..226a8a5fff 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -17,6 +17,7 @@ #include "hw/pci/pci_host.h" #include "hw/qdev-properties.h" #include "hw/pci/pci_bridge.h" +#include "hw/cxl/cxl.h" #include "qemu/range.h" #include "qemu/error-report.h" #include "qemu/module.h" @@ -70,6 +71,12 @@ struct PXBDev { int32_t uid; }; =20 +typedef struct CXLHost { + PCIHostState parent_obj; + + CXLComponentState cxl_cstate; +} CXLHost; + static PXBDev *convert_to_pxb(PCIDevice *dev) { /* A CXL PXB's parent bus is PCIe, so the normal check won't work */ @@ -85,6 +92,9 @@ static GList *pxb_dev_list; =20 #define TYPE_PXB_HOST "pxb-host" =20 +#define TYPE_PXB_CXL_HOST "pxb-cxl-host" +#define PXB_CXL_HOST(obj) OBJECT_CHECK(CXLHost, (obj), TYPE_PXB_CXL_HOST) + static int pxb_bus_num(PCIBus *bus) { PXBDev *pxb =3D convert_to_pxb(bus->parent_dev); @@ -198,6 +208,46 @@ static const TypeInfo pxb_host_info =3D { .class_init =3D pxb_host_class_init, }; =20 +static void pxb_cxl_realize(DeviceState *dev, Error **errp) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + PCIHostState *phb =3D PCI_HOST_BRIDGE(dev); + CXLHost *cxl =3D PXB_CXL_HOST(dev); + CXLComponentState *cxl_cstate =3D &cxl->cxl_cstate; + struct MemoryRegion *mr =3D &cxl_cstate->crb.component_registers; + + cxl_component_register_block_init(OBJECT(dev), cxl_cstate, + TYPE_PXB_CXL_HOST); + sysbus_init_mmio(sbd, mr); + + /* FIXME: support multiple host bridges. */ + sysbus_mmio_map(sbd, 0, CXL_HOST_BASE + + memory_region_size(mr) * pci_bus_uid(phb->bus)= ); +} + +static void pxb_cxl_host_class_init(ObjectClass *class, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(class); + PCIHostBridgeClass *hc =3D PCI_HOST_BRIDGE_CLASS(class); + + hc->root_bus_path =3D pxb_host_root_bus_path; + dc->fw_name =3D "cxl"; + dc->realize =3D pxb_cxl_realize; + /* Reason: Internal part of the pxb/pxb-pcie device, not usable by its= elf */ + dc->user_creatable =3D false; +} + +/* + * This is a device to handle the MMIO for a CXL host bridge. It does noth= ing + * else. + */ +static const TypeInfo cxl_host_info =3D { + .name =3D TYPE_PXB_CXL_HOST, + .parent =3D TYPE_PCI_HOST_BRIDGE, + .instance_size =3D sizeof(CXLHost), + .class_init =3D pxb_cxl_host_class_init, +}; + /* * Registers the PXB bus as a child of pci host root bus. */ @@ -272,7 +322,7 @@ static void pxb_dev_realize_common(PCIDevice *dev, enum= BusType type, dev_name =3D dev->qdev.id; } =20 - ds =3D qdev_new(TYPE_PXB_HOST); + ds =3D qdev_new(type =3D=3D CXL ? TYPE_PXB_CXL_HOST : TYPE_PXB_HOST); if (type =3D=3D PCIE) { bus =3D pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCI= E_BUS); } else if (type =3D=3D CXL) { @@ -466,6 +516,7 @@ static void pxb_register_types(void) type_register_static(&pxb_pcie_bus_info); type_register_static(&pxb_cxl_bus_info); type_register_static(&pxb_host_info); + type_register_static(&cxl_host_info); type_register_static(&pxb_dev_info); type_register_static(&pxb_pcie_dev_info); type_register_static(&pxb_cxl_dev_info); diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h index 362cda40de..6bc344f205 100644 --- a/include/hw/cxl/cxl.h +++ b/include/hw/cxl/cxl.h @@ -17,5 +17,7 @@ #define COMPONENT_REG_BAR_IDX 0 #define DEVICE_REG_BAR_IDX 2 =20 +#define CXL_HOST_BASE 0xD0000000 + #endif =20 --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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01 Feb 2021 17:00:12 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:11 -0800 IronPort-SDR: LLjl9dId0EOxVSz9uC1CUyR2Rq+Vh80Omn+Tc4ajSJlNrhNBEdnrER6+ywco0W6kCCDICNpfkD TH71dX2NokaQ== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457115" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457115" IronPort-SDR: fF9IOuRHIl0X7iApqGnvAC4ei7SpfPO8/Kg9lnCYwux8Ixg6T8RxdYYooUTRp0rYFWm3fkelpT ec8R3eUHYXrQ== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764204" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 18/31] acpi/pxb/cxl: Reserve host bridge MMIO Date: Mon, 1 Feb 2021 16:59:35 -0800 Message-Id: <20210202005948.241655-19-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" For all host bridges, reserve MMIO space with _CRS. The MMIO for the host bridge lives in a magically hard coded space in the system's physical address space. The standard mechanism to tell the OS about regions which can't be used for host bridges is _CRS. Signed-off-by: Ben Widawsky --- hw/i386/acpi-build.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 145a503e92..ecdc10b148 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -28,6 +28,7 @@ #include "qemu/bitmap.h" #include "qemu/error-report.h" #include "hw/pci/pci.h" +#include "hw/cxl/cxl.h" #include "hw/core/cpu.h" #include "target/i386/cpu.h" #include "hw/misc/pvpanic.h" @@ -1194,7 +1195,7 @@ static void build_smb0(Aml *table, I2CBus *smbus, int= devnr, int func) aml_append(table, scope); } =20 -enum { PCI, PCIE }; +enum { PCI, PCIE, CXL }; static void init_pci_acpi(Aml *dev, int uid, int type) { if (type =3D=3D PCI) { @@ -1344,20 +1345,28 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, uint8_t bus_num =3D pci_bus_num(bus); uint8_t numa_node =3D pci_bus_numa_node(bus); int32_t uid =3D pci_bus_uid(bus); + int type; =20 /* look only for expander root buses */ if (!pci_bus_is_root(bus)) { continue; } =20 + type =3D pci_bus_is_cxl(bus) ? CXL : + pci_bus_is_express(bus) ? PCIE : = PCI; + if (bus_num < root_bus_limit) { root_bus_limit =3D bus_num - 1; } =20 scope =3D aml_scope("\\_SB"); - dev =3D aml_device("PC%.02X", bus_num); + if (type =3D=3D CXL) { + dev =3D aml_device("CXL%.01X", pci_bus_uid(bus)); + } else { + dev =3D aml_device("PC%.02X", bus_num); + } aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); - init_pci_acpi(dev, uid, pci_bus_is_express(bus) ? PCIE : PCI); + init_pci_acpi(dev, uid, type); =20 if (numa_node !=3D NUMA_NODE_UNASSIGNED) { aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); @@ -1369,6 +1378,13 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dev, aml_name_decl("_CRS", crs)); aml_append(scope, dev); aml_append(dsdt, scope); + + /* Handle the ranges for the PXB expanders */ + if (type =3D=3D CXL) { + uint64_t base =3D CXL_HOST_BASE + uid * 0x10000; + crs_range_insert(crs_range_set.mem_ranges, base, + base + 0x10000 - 1); + } } } =20 --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612229068; cv=none; d=zohomail.com; s=zohoarc; b=YJYQJGH7OI86WVZDljnXAZ28N4awLxBxCbYaB1ADii0gggauS/hfXNYQ9NcJiEc6Pd1DLpFpVy75SmFlMuYDazX2c31Xo8I9Slr1E0bjQlwm6RHSg7krgtz6ffjoXgrJFssLKgl87StzudmbGnz7Q7uRqgn6Vkv6iGni1SmyHDg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612229068; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+UuYah34VVDNzx4wjopZUjAypW3xywEl7TpBB9oBg7g=; b=m6aYiU8eLQ32lTEFyMSvqT76eDGODIbJDJIkEwI9uMZ14RUM4es06gnsNo5qLToNdKW56PK9f6TV2yR11S1frgqngVlVmRoXGt+wL7Y0+WUE1BrtP5E/V4xlzkIfD2zUJgBO/IczMXqqrNIm52x9yNK1JWxCsVoURMf1oLgZxHQ= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612229068963672.1560723062504; Mon, 1 Feb 2021 17:24:28 -0800 (PST) Received: from localhost ([::1]:36580 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6kQe-0007Rb-0O for importer@patchew.org; Mon, 01 Feb 2021 20:24:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47364) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k3w-0000MS-20 for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:01:00 -0500 Received: from mga18.intel.com ([134.134.136.126]:33366) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k3s-0001pl-Sy for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:00:59 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:13 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:12 -0800 IronPort-SDR: futqNCTXA48wLxzhpSKcJIloHQ4wqTfPb16FwxcUR0X/YyEzRkSR2fwbJDvwvKJSguxD5rk/sE eGm5eMpy3c9A== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457120" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457120" IronPort-SDR: FYatNKh1bKlHg5LO8aWoXMiMyAxZBiKK6Ye2x1T0yzfL3E/KwA0WsvPbqbDuaEyaolUPdSMoNp rLsZ1fZfoheQ== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764212" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 19/31] hw/pxb/cxl: Add "windows" for host bridges Date: Mon, 1 Feb 2021 16:59:36 -0800 Message-Id: <20210202005948.241655-20-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" In a bare metal CXL capable system, system firmware will program physical address ranges on the host. This is done by programming internal registers that aren't typically known to OS. These address ranges might be contiguous or interleaved across host bridges. For a QEMU guest a new construct is introduced allowing passing a memory backend to the host bridge for this same purpose. Each memory backend needs to be passed to the host bridge as well as any device that will be emulating that memory (not implemented here). I'm hopeful the interleaving work in the link can be re-purposed here (see Link). An example to create a host bridges with a 512M window at 0x4c0000000 -object memory-backend-file,id=3Dcxl-mem1,share,mem-path=3Dcxl-type3,size= =3D512M -device pxb-cxl,id=3Dcxl.0,bus=3Dpcie.0,bus_nr=3D52,uid=3D0,len-memory-bas= e=3D1,memory-base\[0\]=3D0x4c0000000,memory\[0\]=3Dcxl-mem1 Link: https://lists.nongnu.org/archive/html/qemu-devel/2020-08/msg03680.html Signed-off-by: Ben Widawsky --- hw/pci-bridge/pci_expander_bridge.c | 65 +++++++++++++++++++++++++++-- include/hw/cxl/cxl.h | 1 + 2 files changed, 62 insertions(+), 4 deletions(-) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 226a8a5fff..af1450c69d 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -69,12 +69,19 @@ struct PXBDev { uint8_t bus_nr; uint16_t numa_node; int32_t uid; + struct cxl_dev { + HostMemoryBackend *memory_window[CXL_WINDOW_MAX]; + + uint32_t num_windows; + hwaddr *window_base[CXL_WINDOW_MAX]; + } cxl; }; =20 typedef struct CXLHost { PCIHostState parent_obj; =20 CXLComponentState cxl_cstate; + PXBDev *dev; } CXLHost; =20 static PXBDev *convert_to_pxb(PCIDevice *dev) @@ -213,16 +220,31 @@ static void pxb_cxl_realize(DeviceState *dev, Error *= *errp) SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); PCIHostState *phb =3D PCI_HOST_BRIDGE(dev); CXLHost *cxl =3D PXB_CXL_HOST(dev); + struct cxl_dev *cxl_dev =3D &cxl->dev->cxl; CXLComponentState *cxl_cstate =3D &cxl->cxl_cstate; struct MemoryRegion *mr =3D &cxl_cstate->crb.component_registers; + int uid =3D pci_bus_uid(phb->bus); =20 cxl_component_register_block_init(OBJECT(dev), cxl_cstate, TYPE_PXB_CXL_HOST); sysbus_init_mmio(sbd, mr); =20 - /* FIXME: support multiple host bridges. */ - sysbus_mmio_map(sbd, 0, CXL_HOST_BASE + - memory_region_size(mr) * pci_bus_uid(phb->bus)= ); + sysbus_mmio_map(sbd, 0, CXL_HOST_BASE + memory_region_size(mr) * uid); + + /* + * A CXL host bridge can exist without a fixed memory window, but it w= ould + * only operate in legacy PCIe mode. + */ + if (!cxl_dev->memory_window[uid]) { + warn_report( + "CXL expander bridge created without window. Consider using %s= ", + "memdev[0]=3D"); + return; + } + + mr =3D host_memory_backend_get_memory(cxl_dev->memory_window[uid]); + sysbus_init_mmio(sbd, mr); + sysbus_mmio_map(sbd, 1 + uid, *cxl_dev->window_base[uid]); } =20 static void pxb_cxl_host_class_init(ObjectClass *class, void *data) @@ -328,6 +350,7 @@ static void pxb_dev_realize_common(PCIDevice *dev, enum= BusType type, } else if (type =3D=3D CXL) { bus =3D pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_CXL= _BUS); bus->flags |=3D PCI_BUS_CXL; + PXB_CXL_HOST(ds)->dev =3D PXB_CXL_DEV(dev); } else { bus =3D pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_P= XB_BUS); bds =3D qdev_new("pci-bridge"); @@ -389,6 +412,8 @@ static Property pxb_dev_properties[] =3D { DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0), DEFINE_PROP_UINT16("numa_node", PXBDev, numa_node, NUMA_NODE_UNASSIGNE= D), DEFINE_PROP_INT32("uid", PXBDev, uid, -1), + DEFINE_PROP_ARRAY("window-base", PXBDev, cxl.num_windows, cxl.window_b= ase, + qdev_prop_uint64, hwaddr), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -460,7 +485,9 @@ static const TypeInfo pxb_pcie_dev_info =3D { =20 static void pxb_cxl_dev_realize(PCIDevice *dev, Error **errp) { - PXBDev *pxb =3D convert_to_pxb(dev); + PXBDev *pxb =3D PXB_CXL_DEV(dev); + struct cxl_dev *cxl =3D &pxb->cxl; + int count =3D 0; =20 /* A CXL PXB's parent bus is still PCIe */ if (!pci_bus_is_express(pci_get_bus(dev))) { @@ -476,6 +503,23 @@ static void pxb_cxl_dev_realize(PCIDevice *dev, Error = **errp) /* FIXME: Check that uid doesn't collide with UIDs of other host bridg= es */ =20 pxb_dev_realize_common(dev, CXL, errp); + + for (unsigned i =3D 0; i < CXL_WINDOW_MAX; i++) { + if (!cxl->memory_window[i]) { + continue; + } + + count++; + } + + if (!count) { + warn_report("memory-windows should be set when creating CXL host b= ridges"); + } + + if (count !=3D cxl->num_windows) { + error_setg(errp, "window bases count (%d) must match window count = (%d)", + cxl->num_windows, count); + } } =20 static void pxb_cxl_dev_class_init(ObjectClass *klass, void *data) @@ -496,6 +540,19 @@ static void pxb_cxl_dev_class_init(ObjectClass *klass,= void *data) =20 /* Host bridges aren't hotpluggable. FIXME: spec reference */ dc->hotpluggable =3D false; + + /* + * Below is moral equivalent of: + * DEFINE_PROP_ARRAY("memdev", PXBDev, window_count, windows, + * qdev_prop_memory_device, HostMemoryBackend) + */ + for (unsigned i =3D 0; i < CXL_WINDOW_MAX; i++) { + g_autofree char *name =3D g_strdup_printf("memdev[%u]", i); + object_class_property_add_link(klass, name, TYPE_MEMORY_BACKEND, + offsetof(PXBDev, cxl.memory_window[i]), + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + } } =20 static const TypeInfo pxb_cxl_dev_info =3D { diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h index 6bc344f205..b1e5f4a8fa 100644 --- a/include/hw/cxl/cxl.h +++ b/include/hw/cxl/cxl.h @@ -18,6 +18,7 @@ #define DEVICE_REG_BAR_IDX 2 =20 #define CXL_HOST_BASE 0xD0000000 +#define CXL_WINDOW_MAX 10 =20 #endif =20 --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612229017520761.6231929253123; Mon, 1 Feb 2021 17:23:37 -0800 (PST) Received: from localhost ([::1]:34114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6kPo-0006Nz-6H for importer@patchew.org; Mon, 01 Feb 2021 20:23:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47414) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k4A-0000dx-Ow for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:01:15 -0500 Received: from mga18.intel.com ([134.134.136.126]:33363) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k43-0001oo-Sa for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:01:14 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:14 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:13 -0800 IronPort-SDR: P0isRkn4xcJkAuJ/8k3UL02PvAaAWOpGr9xkNOi6R+OuVZKCxZf+huIPKQXM324VddY/1IClm3 JByZ2VkTyrSw== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457122" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457122" IronPort-SDR: CZBVFaKseC7DWOUrzq30v1KzUXWZgvts35DNpi0dlKTIIDhB33zKPGERse2OZ3C3iL50MfU6fk Ejz5j8ttGKZQ== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764219" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 20/31] hw/cxl/rp: Add a root port Date: Mon, 1 Feb 2021 16:59:37 -0800 Message-Id: <20210202005948.241655-21-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" This adds just enough of a root port implementation to be able to enumerate root ports (creating the required DVSEC entries). What's not here yet is the MMIO nor the ability to write some of the DVSEC entries. This can be added with the qemu commandline by adding a rootport to a specific CXL host bridge. For example: -device cxl-rp,id=3Drp0,bus=3D"cxl.0",addr=3D0.0,chassis=3D4 Like the host bridge patch, the ACPI tables aren't generated at this point and so system software cannot use it. Signed-off-by: Ben Widawsky --- hw/pci-bridge/Kconfig | 5 + hw/pci-bridge/cxl_root_port.c | 231 +++++++++++++++++++++++++++++++++ hw/pci-bridge/meson.build | 1 + hw/pci-bridge/pcie_root_port.c | 6 +- hw/pci/pci.c | 4 +- 5 files changed, 245 insertions(+), 2 deletions(-) create mode 100644 hw/pci-bridge/cxl_root_port.c diff --git a/hw/pci-bridge/Kconfig b/hw/pci-bridge/Kconfig index f8df4315ba..02614f49aa 100644 --- a/hw/pci-bridge/Kconfig +++ b/hw/pci-bridge/Kconfig @@ -27,3 +27,8 @@ config DEC_PCI =20 config SIMBA bool + +config CXL + bool + default y if PCI_EXPRESS && PXB + depends on PCI_EXPRESS && MSI_NONBROKEN && PXB diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c new file mode 100644 index 0000000000..6c3b215bb3 --- /dev/null +++ b/hw/pci-bridge/cxl_root_port.c @@ -0,0 +1,231 @@ +/* + * CXL 2.0 Root Port Implementation + * + * Copyright(C) 2020 Intel Corporation. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/range.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/pcie_port.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "qapi/error.h" +#include "hw/cxl/cxl.h" + +#define CXL_ROOT_PORT_DID 0x7075 + +/* Copied from the gen root port which we derive */ +#define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100 +#define GEN_PCIE_ROOT_PORT_ACS_OFFSET \ + (GEN_PCIE_ROOT_PORT_AER_OFFSET + PCI_ERR_SIZEOF) +#define CXL_ROOT_PORT_DVSEC_OFFSET \ + (GEN_PCIE_ROOT_PORT_ACS_OFFSET + PCI_ACS_SIZEOF) + +typedef struct CXLRootPort { + /*< private >*/ + PCIESlot parent_obj; + + CXLComponentState cxl_cstate; + PCIResReserve res_reserve; +} CXLRootPort; + +#define TYPE_CXL_ROOT_PORT "cxl-rp" +DECLARE_INSTANCE_CHECKER(CXLRootPort, CXL_ROOT_PORT, TYPE_CXL_ROOT_PORT) + +static void latch_registers(CXLRootPort *crp) +{ + uint32_t *reg_state =3D crp->cxl_cstate.crb.cache_mem_registers; + + cxl_component_register_init_common(reg_state, CXL2_ROOT_PORT); +} + +static void build_dvsecs(CXLComponentState *cxl) +{ + uint8_t *dvsec; + + dvsec =3D (uint8_t *)&(struct extensions_dvsec_port){ 0 }; + cxl_component_create_dvsec(cxl, EXTENSIONS_PORT_DVSEC_LENGTH, + EXTENSIONS_PORT_DVSEC, + EXTENSIONS_PORT_DVSEC_REVID, dvsec); + + dvsec =3D (uint8_t *)&(struct dvsec_port_gpf){ + .rsvd =3D 0, + .phase1_ctrl =3D 1, /* 1=CE=BCs timeout */ + .phase2_ctrl =3D 1, /* 1=CE=BCs timeout */ + }; + cxl_component_create_dvsec(cxl, GPF_PORT_DVSEC_LENGTH, GPF_PORT_DVSEC, + GPF_PORT_DVSEC_REVID, dvsec); + + dvsec =3D (uint8_t *)&(struct dvsec_port_flexbus){ + .cap =3D 0x26, /* IO, Mem, non-MLD */ + .ctrl =3D 0, + .status =3D 0x26, /* same */ + .rcvd_mod_ts_data =3D 0xef, /* WTF? */ + }; + cxl_component_create_dvsec(cxl, PCIE_FLEXBUS_PORT_DVSEC_LENGTH_2_0, + PCIE_FLEXBUS_PORT_DVSEC, + PCIE_FLEXBUS_PORT_DVSEC_REVID_2_0, dvsec); + + dvsec =3D (uint8_t *)&(struct dvsec_register_locator){ + .rsvd =3D 0, + .reg0_base_lo =3D RBI_COMPONENT_REG | COMPONENT_REG_BAR_IDX, + .reg0_base_hi =3D 0, + }; + cxl_component_create_dvsec(cxl, REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC, + REG_LOC_DVSEC_REVID, dvsec); +} + +static void cxl_rp_realize(DeviceState *dev, Error **errp) +{ + PCIDevice *pci_dev =3D PCI_DEVICE(dev); + PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(dev); + CXLRootPort *crp =3D CXL_ROOT_PORT(dev); + CXLComponentState *cxl_cstate =3D &crp->cxl_cstate; + ComponentRegisters *cregs =3D &cxl_cstate->crb; + MemoryRegion *component_bar =3D &cregs->component_registers; + Error *local_err =3D NULL; + + rpc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + int rc =3D + pci_bridge_qemu_reserve_cap_init(pci_dev, 0, crp->res_reserve, err= p); + if (rc < 0) { + rpc->parent_class.exit(pci_dev); + return; + } + + if (!crp->res_reserve.io || crp->res_reserve.io =3D=3D -1) { + pci_word_test_and_clear_mask(pci_dev->wmask + PCI_COMMAND, + PCI_COMMAND_IO); + pci_dev->wmask[PCI_IO_BASE] =3D 0; + pci_dev->wmask[PCI_IO_LIMIT] =3D 0; + } + + cxl_cstate->dvsec_offset =3D CXL_ROOT_PORT_DVSEC_OFFSET; + cxl_cstate->pdev =3D pci_dev; + build_dvsecs(&crp->cxl_cstate); + + cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate, + TYPE_CXL_ROOT_PORT); + + pci_register_bar(pci_dev, COMPONENT_REG_BAR_IDX, + PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64, + component_bar); +} + +static void cxl_rp_reset(DeviceState *dev) +{ + PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(dev); + CXLRootPort *crp =3D CXL_ROOT_PORT(dev); + + rpc->parent_reset(dev); + + latch_registers(crp); +} + +static Property gen_rp_props[] =3D { + DEFINE_PROP_UINT32("bus-reserve", CXLRootPort, res_reserve.bus, -1), + DEFINE_PROP_SIZE("io-reserve", CXLRootPort, res_reserve.io, -1), + DEFINE_PROP_SIZE("mem-reserve", CXLRootPort, res_reserve.mem_non_pref,= -1), + DEFINE_PROP_SIZE("pref32-reserve", CXLRootPort, res_reserve.mem_pref_3= 2, + -1), + DEFINE_PROP_SIZE("pref64-reserve", CXLRootPort, res_reserve.mem_pref_6= 4, + -1), + DEFINE_PROP_END_OF_LIST() +}; + +static void cxl_rp_dvsec_write_config(PCIDevice *dev, uint32_t addr, + uint32_t val, int len) +{ + CXLRootPort *crp =3D CXL_ROOT_PORT(dev); + + if (range_contains(&crp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC], add= r)) { + uint8_t *reg =3D &dev->config[addr]; + addr -=3D crp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC].lob; + if (addr =3D=3D PORT_CONTROL_OVERRIDE_OFFSET) { + if (pci_get_word(reg) & PORT_CONTROL_UNMASK_SBR) { + /* unmask SBR */ + } + if (pci_get_word(reg) & PORT_CONTROL_ALT_MEMID_EN) { + /* Alt Memory & ID Space Enable */ + } + } + } +} + +static void cxl_rp_write_config(PCIDevice *d, uint32_t address, uint32_t v= al, + int len) +{ + uint16_t slt_ctl, slt_sta; + + pcie_cap_slot_get(d, &slt_ctl, &slt_sta); + pci_bridge_write_config(d, address, val, len); + pcie_cap_flr_write_config(d, address, val, len); + pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len); + pcie_aer_write_config(d, address, val, len); + + cxl_rp_dvsec_write_config(d, address, val, len); +} + +static void cxl_root_port_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(oc); + PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_CLASS(oc); + + k->vendor_id =3D PCI_VENDOR_ID_INTEL; + k->device_id =3D CXL_ROOT_PORT_DID; + dc->desc =3D "CXL Root Port"; + k->revision =3D 0; + device_class_set_props(dc, gen_rp_props); + k->config_write =3D cxl_rp_write_config; + + device_class_set_parent_realize(dc, cxl_rp_realize, &rpc->parent_reali= ze); + device_class_set_parent_reset(dc, cxl_rp_reset, &rpc->parent_reset); + + rpc->aer_offset =3D GEN_PCIE_ROOT_PORT_AER_OFFSET; + rpc->acs_offset =3D GEN_PCIE_ROOT_PORT_ACS_OFFSET; + + /* + * Explain + */ + dc->hotpluggable =3D false; +} + +static const TypeInfo cxl_root_port_info =3D { + .name =3D TYPE_CXL_ROOT_PORT, + .parent =3D TYPE_PCIE_ROOT_PORT, + .instance_size =3D sizeof(CXLRootPort), + .class_init =3D cxl_root_port_class_init, + .interfaces =3D (InterfaceInfo[]) { + { INTERFACE_CXL_DEVICE }, + { } + }, +}; + +static void cxl_register(void) +{ + type_register_static(&cxl_root_port_info); +} + +type_init(cxl_register); diff --git a/hw/pci-bridge/meson.build b/hw/pci-bridge/meson.build index daab8acf2a..b6d26a03d5 100644 --- a/hw/pci-bridge/meson.build +++ b/hw/pci-bridge/meson.build @@ -5,6 +5,7 @@ pci_ss.add(when: 'CONFIG_IOH3420', if_true: files('ioh3420.= c')) pci_ss.add(when: 'CONFIG_PCIE_PORT', if_true: files('pcie_root_port.c', 'g= en_pcie_root_port.c', 'pcie_pci_bridge.c')) pci_ss.add(when: 'CONFIG_PXB', if_true: files('pci_expander_bridge.c')) pci_ss.add(when: 'CONFIG_XIO3130', if_true: files('xio3130_upstream.c', 'x= io3130_downstream.c')) +pci_ss.add(when: 'CONFIG_CXL', if_true: files('cxl_root_port.c')) =20 # NewWorld PowerMac pci_ss.add(when: 'CONFIG_DEC_PCI', if_true: files('dec.c')) diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index f1cfe9d14a..460e48269d 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -67,7 +67,11 @@ static void rp_realize(PCIDevice *d, Error **errp) int rc; =20 pci_config_set_interrupt_pin(d->config, 1); - pci_bridge_initfn(d, TYPE_PCIE_BUS); + if (d->cap_present & QEMU_PCIE_CAP_CXL) { + pci_bridge_initfn(d, TYPE_CXL_BUS); + } else { + pci_bridge_initfn(d, TYPE_PCIE_BUS); + } pcie_port_init_reg(d); =20 rc =3D pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id, diff --git a/hw/pci/pci.c b/hw/pci/pci.c index bf019d91a0..eb325704e7 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2668,7 +2668,9 @@ static void pci_device_class_base_init(ObjectClass *k= lass, void *data) object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DE= VICE); ObjectClass *pcie =3D object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE); - assert(conventional || pcie); + ObjectClass *cxl =3D + object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE); + assert(conventional || pcie || cxl); } } =20 --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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01 Feb 2021 17:00:15 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:14 -0800 IronPort-SDR: 0BH8SrgwhnuEGLCRg7yjfduj84/qy4ANxRBVytmoFm6xXmtg7Vbs+kzXPlH0+SEYV8s14Ym9VR Z07I7vHYG6yQ== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457125" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457125" IronPort-SDR: seOBrf+c3vsF1vfxF+wKU7/Fr/1gbkOglHHQ+5k0SR2XYu7rZuslZmzxVQu80/pw7BahOv/Zuk aSHI/3rzzdxw== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764224" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 21/31] hw/cxl/device: Add a memory device (8.2.8.5) Date: Mon, 1 Feb 2021 16:59:38 -0800 Message-Id: <20210202005948.241655-22-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" A CXL memory device (AKA Type 3) is a CXL component that contains some combination of volatile and persistent memory. It also implements the previously defined mailbox interface as well as the memory device firmware interface. Although the memory device is configured like a normal PCIe device, the memory traffic is on an entirely separate bus conceptually (using the same physical wires as PCIe, but different protocol). The guest physical address for the memory device is part of a larger window which is owned by the platform. Currently, this is hardcoded as an object property on host bridge (PXB) creation, but that will need to change for interleaving. The following example will create a 256M device in a 512M window: -object "memory-backend-file,id=3Dcxl-mem1,share,mem-path=3Dcxl-type3,size= =3D512M" -device "cxl-type3,bus=3Drp0,memdev=3Dcxl-mem1,id=3Dcxl-pmem0,size=3D256M" Signed-off-by: Ben Widawsky --- hw/core/numa.c | 3 + hw/cxl/cxl-mailbox-utils.c | 41 ++++++ hw/i386/pc.c | 1 + hw/mem/Kconfig | 5 + hw/mem/cxl_type3.c | 281 +++++++++++++++++++++++++++++++++++++ hw/mem/meson.build | 1 + hw/pci/pcie.c | 30 ++++ include/hw/cxl/cxl.h | 2 + include/hw/cxl/cxl_pci.h | 22 +++ include/hw/pci/pci_ids.h | 1 + monitor/hmp-cmds.c | 15 ++ qapi/machine.json | 1 + 12 files changed, 403 insertions(+) create mode 100644 hw/mem/cxl_type3.c diff --git a/hw/core/numa.c b/hw/core/numa.c index 68cee65f61..cd7df371e6 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -770,6 +770,9 @@ static void numa_stat_memory_devices(NumaNodeMem node_m= em[]) node_mem[pcdimm_info->node].node_plugged_mem +=3D pcdimm_info->size; break; + case MEMORY_DEVICE_INFO_KIND_CXL: + /* FINISHME */ + break; case MEMORY_DEVICE_INFO_KIND_VIRTIO_PMEM: vpi =3D value->u.virtio_pmem.data; /* TODO: once we support numa, assign to right node */ diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 3f0ae8b9e5..f92dfad882 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -49,6 +49,8 @@ enum { LOGS =3D 0x04, #define GET_SUPPORTED 0x0 #define GET_LOG 0x1 + IDENTIFY =3D 0x40, + #define MEMORY_DEVICE 0x0 }; =20 /* 8.2.8.4.5.1 Command Return Codes */ @@ -127,6 +129,7 @@ declare_mailbox_handler(TIMESTAMP_GET); declare_mailbox_handler(TIMESTAMP_SET); declare_mailbox_handler(LOGS_GET_SUPPORTED); declare_mailbox_handler(LOGS_GET_LOG); +declare_mailbox_handler(IDENTIFY_MEMORY_DEVICE); =20 #define IMMEDIATE_CONFIG_CHANGE (1 << 1) #define IMMEDIATE_POLICY_CHANGE (1 << 3) @@ -144,6 +147,7 @@ static struct cxl_cmd cxl_cmd_set[256][256] =3D { CXL_CMD(TIMESTAMP, SET, 8, IMMEDIATE_POLICY_CHANGE), CXL_CMD(LOGS, GET_SUPPORTED, 0, 0), CXL_CMD(LOGS, GET_LOG, 0x18, 0), + CXL_CMD(IDENTIFY, MEMORY_DEVICE, 0, 0), }; =20 #undef CXL_CMD @@ -255,6 +259,43 @@ define_mailbox_handler(LOGS_GET_LOG) return CXL_MBOX_SUCCESS; } =20 +/* 8.2.9.5.1.1 */ +define_mailbox_handler(IDENTIFY_MEMORY_DEVICE) +{ + struct { + char fw_revision[0x10]; + uint64_t total_capacity; + uint64_t volatile_capacity; + uint64_t persistent_capacity; + uint64_t partition_align; + uint16_t info_event_log_size; + uint16_t warning_event_log_size; + uint16_t failure_event_log_size; + uint16_t fatal_event_log_size; + uint32_t lsa_size; + uint8_t poison_list_max_mer[3]; + uint16_t inject_poison_limit; + uint8_t poison_caps; + uint8_t qos_telemetry_caps; + } __attribute__((packed)) *id; + _Static_assert(sizeof(*id) =3D=3D 0x43, "Bad identify size"); + + if (memory_region_size(cxl_dstate->pmem) < (256 << 20)) { + return CXL_MBOX_INTERNAL_ERROR; + } + + id =3D (void *)cmd->payload; + memset(id, 0, sizeof(*id)); + + /* PMEM only */ + snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 0); + id->total_capacity =3D memory_region_size(cxl_dstate->pmem); + id->persistent_capacity =3D memory_region_size(cxl_dstate->pmem); + + *len =3D sizeof(*id); + return CXL_MBOX_SUCCESS; +} + void cxl_process_mailbox(CXLDeviceState *cxl_dstate) { uint16_t ret =3D CXL_MBOX_SUCCESS; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 5458f61d10..5d41809b37 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -79,6 +79,7 @@ #include "acpi-build.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" +#include "hw/cxl/cxl.h" #include "qapi/error.h" #include "qapi/qapi-visit-common.h" #include "qapi/visitor.h" diff --git a/hw/mem/Kconfig b/hw/mem/Kconfig index a0ef2cf648..7d9d1ced3e 100644 --- a/hw/mem/Kconfig +++ b/hw/mem/Kconfig @@ -10,3 +10,8 @@ config NVDIMM default y depends on (PC || PSERIES || ARM_VIRT) select MEM_DEVICE + +config CXL_MEM_DEVICE + bool + default y if CXL + select MEM_DEVICE diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c new file mode 100644 index 0000000000..4e9a016448 --- /dev/null +++ b/hw/mem/cxl_type3.c @@ -0,0 +1,281 @@ +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qemu/error-report.h" +#include "hw/mem/memory-device.h" +#include "hw/mem/pc-dimm.h" +#include "hw/pci/pci.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/range.h" +#include "qemu/rcu.h" +#include "sysemu/hostmem.h" +#include "hw/cxl/cxl.h" + +typedef struct cxl_type3_dev { + /* Private */ + PCIDevice parent_obj; + + /* Properties */ + uint64_t size; + HostMemoryBackend *hostmem; + + /* State */ + CXLComponentState cxl_cstate; + CXLDeviceState cxl_dstate; +} CXLType3Dev; + +#define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV) + +static void build_dvsecs(CXLType3Dev *ct3d) +{ + CXLComponentState *cxl_cstate =3D &ct3d->cxl_cstate; + uint8_t *dvsec; + + dvsec =3D (uint8_t *)&(struct dvsec_device){ + .cap =3D 0x1e, + .ctrl =3D 0x6, + .status2 =3D 0x2, + .range1_size_hi =3D 0, + .range1_size_lo =3D (2 << 5) | (2 << 2) | 0x3 | ct3d->size, + .range1_base_hi =3D 0, + .range1_base_lo =3D 0, + }; + cxl_component_create_dvsec(cxl_cstate, PCIE_CXL_DEVICE_DVSEC_LENGTH, + PCIE_CXL_DEVICE_DVSEC, + PCIE_CXL2_DEVICE_DVSEC_REVID, dvsec); + + dvsec =3D (uint8_t *)&(struct dvsec_register_locator){ + .rsvd =3D 0, + .reg0_base_lo =3D RBI_COMPONENT_REG | COMPONENT_REG_BAR_IDX, + .reg0_base_hi =3D 0, + .reg1_base_lo =3D RBI_CXL_DEVICE_REG | DEVICE_REG_BAR_IDX, + .reg1_base_hi =3D 0, + }; + cxl_component_create_dvsec(cxl_cstate, REG_LOC_DVSEC_LENGTH, REG_LOC_D= VSEC, + REG_LOC_DVSEC_REVID, dvsec); +} + +static void ct3_instance_init(Object *obj) +{ + /* MemoryDeviceClass *mdc =3D MEMORY_DEVICE_GET_CLASS(obj); */ +} + +static void ct3_finalize(Object *obj) +{ + CXLType3Dev *ct3d =3D CT3(obj); + + g_free(ct3d->cxl_dstate.pmem); +} + +#ifdef SET_PMEM_PADDR +static void cxl_set_addr(CXLType3Dev *ct3d, hwaddr addr, Error **errp) +{ + MemoryDeviceClass *mdc =3D MEMORY_DEVICE_GET_CLASS(ct3d); + mdc->set_addr(MEMORY_DEVICE(ct3d), addr, errp); +} +#endif + +static void cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) +{ + MemoryRegionSection mrs; + MemoryRegion *pmem; + MemoryRegion *mr; + uint64_t offset =3D 0; + size_t remaining_size; + + if (!ct3d->hostmem) { + error_setg(errp, "memdev property must be set"); + return; + } + + /* FIXME: need to check mr is the host bridge's MR */ + mr =3D host_memory_backend_get_memory(ct3d->hostmem); + + /* Create our new subregion */ + pmem =3D g_new(MemoryRegion, 1); + + /* Find the first free space in the window */ + WITH_RCU_READ_LOCK_GUARD() + { + mrs =3D memory_region_find(mr, offset, 1); + while (mrs.mr && mrs.mr !=3D mr) { + offset +=3D memory_region_size(mrs.mr); + mrs =3D memory_region_find(mr, offset, 1); + } + } + + remaining_size =3D memory_region_size(mr) - offset; + if (remaining_size < ct3d->size) { + g_free(pmem); + error_setg(errp, + "Not enough free space (%zd) required for device (%" PR= Id64 ")", + remaining_size, ct3d->size); + } + + memory_region_set_nonvolatile(pmem, true); + memory_region_set_enabled(pmem, false); + memory_region_init_alias(pmem, OBJECT(ct3d), "cxl_type3-memory", mr, 0, + ct3d->size); + ct3d->cxl_dstate.pmem =3D pmem; + +#ifdef SET_PMEM_PADDR + /* This path will initialize the memory device as if BIOS had done it = */ + cxl_set_addr(ct3d, mr->addr + offset, errp); + memory_region_set_enabled(pmem, true); +#endif +} + +static MemoryRegion *cxl_md_get_memory_region(MemoryDeviceState *md, + Error **errp) +{ + CXLType3Dev *ct3d =3D CT3(md); + + if (!ct3d->cxl_dstate.pmem) { + cxl_setup_memory(ct3d, errp); + } + + return ct3d->cxl_dstate.pmem; +} + +static void ct3_realize(PCIDevice *pci_dev, Error **errp) +{ + CXLType3Dev *ct3d =3D CT3(pci_dev); + CXLComponentState *cxl_cstate =3D &ct3d->cxl_cstate; + ComponentRegisters *regs =3D &cxl_cstate->crb; + MemoryRegion *mr =3D ®s->component_registers; + uint8_t *pci_conf =3D pci_dev->config; + + if (!ct3d->cxl_dstate.pmem) { + cxl_setup_memory(ct3d, errp); + } + + pci_config_set_prog_interface(pci_conf, 0x10); + pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_CXL); + + pcie_endpoint_cap_init(pci_dev, 0x80); + cxl_cstate->dvsec_offset =3D 0x100; + + ct3d->cxl_cstate.pdev =3D pci_dev; + build_dvsecs(ct3d); + + cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate, + TYPE_CXL_TYPE3_DEV); + + pci_register_bar( + pci_dev, COMPONENT_REG_BAR_IDX, + PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, mr); + + cxl_device_register_block_init(OBJECT(pci_dev), &ct3d->cxl_dstate); + pci_register_bar(pci_dev, DEVICE_REG_BAR_IDX, + PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64, + &ct3d->cxl_dstate.device_registers); +} + +static uint64_t cxl_md_get_addr(const MemoryDeviceState *md) +{ + CXLType3Dev *ct3d =3D CT3(md); + MemoryRegion *pmem =3D ct3d->cxl_dstate.pmem; + + assert(pmem->alias); + return pmem->alias_offset; +} + +static void cxl_md_set_addr(MemoryDeviceState *md, uint64_t addr, Error **= errp) +{ + CXLType3Dev *ct3d =3D CT3(md); + MemoryRegion *pmem =3D ct3d->cxl_dstate.pmem; + + assert(pmem->alias); + memory_region_set_alias_offset(pmem, addr); + memory_region_set_address(pmem, addr); +} + +static void ct3d_reset(DeviceState *dev) +{ + CXLType3Dev *ct3d =3D CT3(dev); + uint32_t *reg_state =3D ct3d->cxl_cstate.crb.cache_mem_registers; + + cxl_component_register_init_common(reg_state, CXL2_TYPE3_DEVICE); + cxl_device_register_init_common(&ct3d->cxl_dstate); +} + +static Property ct3_props[] =3D { + DEFINE_PROP_SIZE("size", CXLType3Dev, size, -1), + DEFINE_PROP_LINK("memdev", CXLType3Dev, hostmem, TYPE_MEMORY_BACKEND, + HostMemoryBackend *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void pc_dimm_md_fill_device_info(const MemoryDeviceState *md, + MemoryDeviceInfo *info) +{ + PCDIMMDeviceInfo *di =3D g_new0(PCDIMMDeviceInfo, 1); + const DeviceClass *dc =3D DEVICE_GET_CLASS(md); + const DeviceState *dev =3D DEVICE(md); + CXLType3Dev *ct3d =3D CT3(md); + + if (dev->id) { + di->has_id =3D true; + di->id =3D g_strdup(dev->id); + } + + di->hotplugged =3D dev->hotplugged; + di->hotpluggable =3D dc->hotpluggable; + di->addr =3D cxl_md_get_addr(md); + di->slot =3D 0; + di->node =3D 0; + di->size =3D memory_device_get_region_size(md, NULL); + di->memdev =3D object_get_canonical_path(OBJECT(ct3d->hostmem)); + + info->u.cxl.data =3D di; + info->type =3D MEMORY_DEVICE_INFO_KIND_CXL; +} + +static void ct3_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + PCIDeviceClass *pc =3D PCI_DEVICE_CLASS(oc); + MemoryDeviceClass *mdc =3D MEMORY_DEVICE_CLASS(oc); + + pc->realize =3D ct3_realize; + pc->class_id =3D PCI_CLASS_STORAGE_EXPRESS; + pc->vendor_id =3D PCI_VENDOR_ID_INTEL; + pc->device_id =3D 0xd93; /* LVF for now */ + pc->revision =3D 1; + + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); + dc->desc =3D "CXL PMEM Device (Type 3)"; + dc->reset =3D ct3d_reset; + device_class_set_props(dc, ct3_props); + + mdc->get_memory_region =3D cxl_md_get_memory_region; + mdc->get_addr =3D cxl_md_get_addr; + mdc->fill_device_info =3D pc_dimm_md_fill_device_info; + mdc->get_plugged_size =3D memory_device_get_region_size; + mdc->set_addr =3D cxl_md_set_addr; +} + +static const TypeInfo ct3d_info =3D { + .name =3D TYPE_CXL_TYPE3_DEV, + .parent =3D TYPE_PCI_DEVICE, + .class_init =3D ct3_class_init, + .instance_size =3D sizeof(CXLType3Dev), + .instance_init =3D ct3_instance_init, + .instance_finalize =3D ct3_finalize, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_MEMORY_DEVICE }, + { INTERFACE_CXL_DEVICE }, + { INTERFACE_PCIE_DEVICE }, + {} + }, +}; + +static void ct3d_registers(void) +{ + type_register_static(&ct3d_info); +} + +type_init(ct3d_registers); diff --git a/hw/mem/meson.build b/hw/mem/meson.build index 0d22f2b572..d13c3ed117 100644 --- a/hw/mem/meson.build +++ b/hw/mem/meson.build @@ -3,5 +3,6 @@ mem_ss.add(files('memory-device.c')) mem_ss.add(when: 'CONFIG_DIMM', if_true: files('pc-dimm.c')) mem_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_mc.c')) mem_ss.add(when: 'CONFIG_NVDIMM', if_true: files('nvdimm.c')) +mem_ss.add(when: 'CONFIG_CXL_MEM_DEVICE', if_true: files('cxl_type3.c')) =20 softmmu_ss.add_all(when: 'CONFIG_MEM_DEVICE', if_true: mem_ss) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index d4010cf8f3..1ecf6f6a55 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -20,6 +20,7 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" +#include "hw/mem/memory-device.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pcie.h" #include "hw/pci/msix.h" @@ -27,6 +28,8 @@ #include "hw/pci/pci_bus.h" #include "hw/pci/pcie_regs.h" #include "hw/pci/pcie_port.h" +#include "hw/cxl/cxl.h" +#include "hw/boards.h" #include "qemu/range.h" =20 //#define DEBUG_PCIE @@ -419,6 +422,28 @@ void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug= _dev, DeviceState *dev, } =20 pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev), dev, errp); + +#ifdef CXL_MEM_DEVICE + /* + * FIXME: + * if (object_dynamic_cast(OBJECT(dev), TYPE_CXL_TYPE3_DEV)) { + * HotplugHandler *hotplug_ctrl; + * Error *local_err =3D NULL; + * hotplug_ctrl =3D qdev_get_hotplug_handler(dev); + * if (hotplug_ctrl) { + * hotplug_handler_pre_plug(hotplug_ctrl, dev, &local_err); + * if (local_err) { + * error_propagate(errp, local_err); + * return; + * } + * } + */ + + if (object_dynamic_cast(OBJECT(dev), TYPE_CXL_TYPE3_DEV)) { + memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(qdev_get_machin= e()), + NULL, errp); + } +#endif } =20 void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, @@ -455,6 +480,11 @@ void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev= , DeviceState *dev, pcie_cap_slot_event(hotplug_pdev, PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP); } + +#ifdef CXL_MEM_DEVICE + if (object_dynamic_cast(OBJECT(dev), TYPE_CXL_TYPE3_DEV)) + memory_device_plug(MEMORY_DEVICE(dev), MACHINE(qdev_get_machine())= ); +#endif } =20 void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h index b1e5f4a8fa..809ed7de60 100644 --- a/include/hw/cxl/cxl.h +++ b/include/hw/cxl/cxl.h @@ -17,6 +17,8 @@ #define COMPONENT_REG_BAR_IDX 0 #define DEVICE_REG_BAR_IDX 2 =20 +#define TYPE_CXL_TYPE3_DEV "cxl-type3" + #define CXL_HOST_BASE 0xD0000000 #define CXL_WINDOW_MAX 10 =20 diff --git a/include/hw/cxl/cxl_pci.h b/include/hw/cxl/cxl_pci.h index a53c2e5ae7..9ec28c9feb 100644 --- a/include/hw/cxl/cxl_pci.h +++ b/include/hw/cxl/cxl_pci.h @@ -64,6 +64,28 @@ _Static_assert(sizeof(struct dvsec_header) =3D=3D 10, * CXL 2.0 Downstream Port: 3, 4, 7, 8 */ =20 +/* CXL 2.0 - 8.1.3 (ID 0001) */ +struct dvsec_device { + struct dvsec_header hdr; + uint16_t cap; + uint16_t ctrl; + uint16_t status; + uint16_t ctrl2; + uint16_t status2; + uint16_t lock; + uint16_t cap2; + uint32_t range1_size_hi; + uint32_t range1_size_lo; + uint32_t range1_base_hi; + uint32_t range1_base_lo; + uint32_t range2_size_hi; + uint32_t range2_size_lo; + uint32_t range2_base_hi; + uint32_t range2_base_lo; +}; +_Static_assert(sizeof(struct dvsec_device) =3D=3D 0x38, + "dvsec device size incorrect"); + /* CXL 2.0 - 8.1.5 (ID 0003) */ struct extensions_dvsec_port { struct dvsec_header hdr; diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h index 11f8ab7149..76bf3ed590 100644 --- a/include/hw/pci/pci_ids.h +++ b/include/hw/pci/pci_ids.h @@ -53,6 +53,7 @@ #define PCI_BASE_CLASS_MEMORY 0x05 #define PCI_CLASS_MEMORY_RAM 0x0500 #define PCI_CLASS_MEMORY_FLASH 0x0501 +#define PCI_CLASS_MEMORY_CXL 0x0502 #define PCI_CLASS_MEMORY_OTHER 0x0580 =20 #define PCI_BASE_CLASS_BRIDGE 0x06 diff --git a/monitor/hmp-cmds.c b/monitor/hmp-cmds.c index a48bc1e904..1c8edfb136 100644 --- a/monitor/hmp-cmds.c +++ b/monitor/hmp-cmds.c @@ -1884,6 +1884,21 @@ void hmp_info_memory_devices(Monitor *mon, const QDi= ct *qdict) monitor_printf(mon, " hotpluggable: %s\n", di->hotpluggable ? "true" : "false"); break; + case MEMORY_DEVICE_INFO_KIND_CXL: + di =3D value->u.cxl.data; + monitor_printf(mon, "Memory device [%s]: \"%s\"\n", + MemoryDeviceInfoKind_str(value->type), + di->id ? di->id : ""); + monitor_printf(mon, " addr: 0x%" PRIx64 "\n", di->addr); + monitor_printf(mon, " slot: %" PRId64 "\n", di->slot); + monitor_printf(mon, " node: %" PRId64 "\n", di->node); + monitor_printf(mon, " size: %" PRIu64 "\n", di->size); + monitor_printf(mon, " memdev: %s\n", di->memdev); + monitor_printf(mon, " hotplugged: %s\n", + di->hotplugged ? "true" : "false"); + monitor_printf(mon, " hotpluggable: %s\n", + di->hotpluggable ? "true" : "false"); + break; case MEMORY_DEVICE_INFO_KIND_VIRTIO_PMEM: vpi =3D value->u.virtio_pmem.data; monitor_printf(mon, "Memory device [%s]: \"%s\"\n", diff --git a/qapi/machine.json b/qapi/machine.json index 330189efe3..aa96d662bd 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -1394,6 +1394,7 @@ { 'union': 'MemoryDeviceInfo', 'data': { 'dimm': 'PCDIMMDeviceInfo', 'nvdimm': 'PCDIMMDeviceInfo', + 'cxl': 'PCDIMMDeviceInfo', 'virtio-pmem': 'VirtioPMEMDeviceInfo', 'virtio-mem': 'VirtioMEMDeviceInfo' } --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612228157; cv=none; d=zohomail.com; s=zohoarc; b=nyk/+RPLkQgKDYKFJmmYcEnfkjZkGk6uL9Yr8vVVk4imBEEox5OvGUpUqOAIMMODs3wmIjLlnDOAFELaDw82hmAlK3yfM+M5/wrXwVwst/Xz/qLltT1rnin410JxpHmMg2C/eZW5Gdc85Ae/G5yvpgPw0WCCcJlriKNQCVnqQjg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612228157; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/d5Nkjs2/GdjoerNI0qNs7ypxMALHeILm+xqPmVzjB8=; b=Kbu02CHw+lCmKiunkGAhpV/ixliqtKm3mPH15aXmlGpivSfCTgiu0uUDPWHRreo9QgJMuHYz89hxjwYGSUvsgTgctt/aLlt2pEDxxNzFZLYkjoHaYE1ci2B0ZyocEdt/otwFXqeNF/vMIWc7poIm7mXC6Pb9pVti9gx6/40uIgY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612228157210869.3045586697813; Mon, 1 Feb 2021 17:09:17 -0800 (PST) Received: from localhost ([::1]:59246 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6kBv-0000jd-Jz for importer@patchew.org; Mon, 01 Feb 2021 20:09:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47422) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k4B-0000eu-NN for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:01:17 -0500 Received: from mga18.intel.com ([134.134.136.126]:33366) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k46-0001pl-HT for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:01:15 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:16 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:15 -0800 IronPort-SDR: qEkkxzZh2+sJWfqYIYt6NH6FCW6xfRpScKpAxWuaN+GEqJiN4IzyxWWfBK3OFRbMfd440MRpVW OqIhMQY7mr8w== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457128" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457128" IronPort-SDR: mj/WECK9mex43OGDJQ+sNJnmkCYCD8EO8/Ml13pY/nuQpmCNcku2zKN22Y7S0EIvuKBzv/Ngg9 E8+RnkBnvchw== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764231" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 22/31] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Date: Mon, 1 Feb 2021 16:59:39 -0800 Message-Id: <20210202005948.241655-23-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" A device's volatile and persistent memory are known Host Defined Memory (HDM) regions. The mechanism by which the device is programmed to claim the addresses associated with those regions is through dedicated logic known as the HDM decoder. In order to allow the OS to properly program the HDMs, the HDM decoders must be modeled. There are two ways the HDM decoders can be implemented, the legacy mechanism is through the PCIe DVSEC programming from CXL 1.1 (8.1.3.8), and MMIO is found in 8.2.5.12 of the spec. For now, 8.1.3.8 is not implemented. Much of CXL device logic is implemented in cxl-utils. The HDM decoder however is implemented directly by the device implementation. The generic cxl-utils probably should be the correct place to put this since HDM decoders aren't unique to a type3 device. It is however easier at the moment, and requires less design consideration to simply implement it in the device, and figure out how to consolidate it later. Signed-off-by: Ben Widawsky --- hw/mem/cxl_type3.c | 92 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 84 insertions(+), 8 deletions(-) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 4e9a016448..fe02c3b63c 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -57,6 +57,84 @@ static void build_dvsecs(CXLType3Dev *ct3d) REG_LOC_DVSEC_REVID, dvsec); } =20 +static void cxl_set_addr(CXLType3Dev *ct3d, hwaddr addr, Error **errp) +{ + MemoryDeviceClass *mdc =3D MEMORY_DEVICE_GET_CLASS(ct3d); + mdc->set_addr(MEMORY_DEVICE(ct3d), addr, errp); +} + +static void hdm_decoder_commit(CXLType3Dev *ct3d, int which) +{ + MemoryRegion *pmem =3D ct3d->cxl_dstate.pmem; + MemoryRegion *mr =3D host_memory_backend_get_memory(ct3d->hostmem); + Range window, device; + ComponentRegisters *cregs =3D &ct3d->cxl_cstate.crb; + uint32_t *cache_mem =3D cregs->cache_mem_registers; + uint64_t offset, size; + Error *err =3D NULL; + + assert(which =3D=3D 0); + + ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMIT, 0); + ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERROR, 0); + + offset =3D ((uint64_t)cache_mem[R_CXL_HDM_DECODER0_BASE_HI] << 32) | + cache_mem[R_CXL_HDM_DECODER0_BASE_LO]; + size =3D ((uint64_t)cache_mem[R_CXL_HDM_DECODER0_SIZE_HI] << 32) | + cache_mem[R_CXL_HDM_DECODER0_SIZE_LO]; + + range_init_nofail(&window, mr->addr, memory_region_size(mr)); + range_init_nofail(&device, offset, size); + + if (!range_contains_range(&window, &device)) { + ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERROR, 1); + return; + } + + /* + * FIXME: Support resizing. + * Maybe just memory_region_ram_resize(pmem, size, &err)? + */ + if (size !=3D memory_region_size(pmem)) { + ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERROR, 1); + return; + } + + cxl_set_addr(ct3d, offset, &err); + if (err) { + ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERROR, 1); + return; + } + memory_region_set_enabled(pmem, true); + + ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); +} + +static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value, un= signed size) +{ + CXLComponentState *cxl_cstate =3D opaque; + ComponentRegisters *cregs =3D &cxl_cstate->crb; + CXLType3Dev *ct3d =3D container_of(cxl_cstate, CXLType3Dev, cxl_cstate= ); + uint32_t *cache_mem =3D cregs->cache_mem_registers; + bool should_commit =3D false; + int which_hdm =3D -1; + + assert(size =3D=3D 4); + + switch (offset) { + case A_CXL_HDM_DECODER0_CTRL: + should_commit =3D FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT); + which_hdm =3D 0; + break; + default: + break; + } + + stl_le_p((uint8_t *)cache_mem + offset, value); + if (should_commit) + hdm_decoder_commit(ct3d, which_hdm); +} + static void ct3_instance_init(Object *obj) { /* MemoryDeviceClass *mdc =3D MEMORY_DEVICE_GET_CLASS(obj); */ @@ -65,18 +143,13 @@ static void ct3_instance_init(Object *obj) static void ct3_finalize(Object *obj) { CXLType3Dev *ct3d =3D CT3(obj); + CXLComponentState *cxl_cstate =3D &ct3d->cxl_cstate; + ComponentRegisters *regs =3D &cxl_cstate->crb; =20 + g_free((void *)regs->special_ops); g_free(ct3d->cxl_dstate.pmem); } =20 -#ifdef SET_PMEM_PADDR -static void cxl_set_addr(CXLType3Dev *ct3d, hwaddr addr, Error **errp) -{ - MemoryDeviceClass *mdc =3D MEMORY_DEVICE_GET_CLASS(ct3d); - mdc->set_addr(MEMORY_DEVICE(ct3d), addr, errp); -} -#endif - static void cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) { MemoryRegionSection mrs; @@ -160,6 +233,9 @@ static void ct3_realize(PCIDevice *pci_dev, Error **err= p) ct3d->cxl_cstate.pdev =3D pci_dev; build_dvsecs(ct3d); =20 + regs->special_ops =3D g_new0(MemoryRegionOps, 1); + regs->special_ops->write =3D ct3d_reg_write; + cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate, TYPE_CXL_TYPE3_DEV); =20 --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612229336; cv=none; d=zohomail.com; s=zohoarc; b=CV6GgI0kRFQGsryYPc3mm6+kE9cTK6g8En5liJL5aReddxTFH43+UYvXypbV7i+WHsCMoRZCuxNYbxrVz4mapDanZULwnuchOKpmn4I2M7t5g7bzBQCiRqsV35PppX3pN3Uh5jK+Xxzah1SrA6he3zFjPNfOULGiBFIlcLxeJA4= ARC-Message-Signature: i=1; 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Mon, 01 Feb 2021 20:28:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47462) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k4M-0000x9-Pw for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:01:26 -0500 Received: from mga18.intel.com ([134.134.136.126]:33362) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k4J-0001oN-U3 for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:01:26 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:17 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:16 -0800 IronPort-SDR: L2PSbzAn6ccboNMbygQ6ZMfVj0butL+yFB8MQ0J7wYVO4x2WrKm3G1Hfhu2HDcGM5Q1vAeHO+M ptcHDRtzSNJg== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457131" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457131" IronPort-SDR: igPEtCJBQAVYH0h5q3JeBrncHErwJBfITlk40tuBdeQUHH4RSBkNIb46UlBDJpII+m3ZbzPNw/ pn9/em4UOMNg== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764235" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 23/31] acpi/cxl: Add _OSC implementation (9.14.2) Date: Mon, 1 Feb 2021 16:59:40 -0800 Message-Id: <20210202005948.241655-24-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" CXL 2.0 specification adds 2 new dwords to the existing _OSC definition from PCIe. The new dwords are accessed with a new uuid. This implementation supports what is in the specification. We are currently in the process of trying to define a new definition for _OSC. See later work for an explanation. Signed-off-by: Ben Widawsky --- hw/acpi/Kconfig | 5 ++ hw/acpi/cxl.c | 104 ++++++++++++++++++++++++++++++++++++++++++ hw/acpi/meson.build | 1 + hw/i386/acpi-build.c | 12 ++++- include/hw/acpi/cxl.h | 23 ++++++++++ 5 files changed, 144 insertions(+), 1 deletion(-) create mode 100644 hw/acpi/cxl.c create mode 100644 include/hw/acpi/cxl.h diff --git a/hw/acpi/Kconfig b/hw/acpi/Kconfig index 1932f66af8..b27907953e 100644 --- a/hw/acpi/Kconfig +++ b/hw/acpi/Kconfig @@ -5,6 +5,7 @@ config ACPI_X86 bool select ACPI select ACPI_NVDIMM + select ACPI_CXL select ACPI_CPU_HOTPLUG select ACPI_MEMORY_HOTPLUG select ACPI_HMAT @@ -42,3 +43,7 @@ config ACPI_VMGENID depends on PC =20 config ACPI_HW_REDUCED + +config ACPI_CXL + bool + depends on ACPI diff --git a/hw/acpi/cxl.c b/hw/acpi/cxl.c new file mode 100644 index 0000000000..7124d5a1a3 --- /dev/null +++ b/hw/acpi/cxl.c @@ -0,0 +1,104 @@ +/* + * CXL ACPI Implementation + * + * Copyright(C) 2020 Intel Corporation. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + */ + +#include "qemu/osdep.h" +#include "hw/cxl/cxl.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/aml-build.h" +#include "hw/acpi/bios-linker-loader.h" +#include "hw/acpi/cxl.h" +#include "qapi/error.h" +#include "qemu/uuid.h" + +static Aml *__build_cxl_osc_method(void) +{ + Aml *method, *if_uuid, *else_uuid, *if_arg1_not_1, *if_cxl, *if_caps_m= asked; + Aml *a_ctrl =3D aml_local(0); + Aml *a_cdw1 =3D aml_name("CDW1"); + + method =3D aml_method("_OSC", 4, AML_NOTSERIALIZED); + aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW= 1")); + + /* 9.14.2.1.4 */ + if_uuid =3D aml_if( + aml_lor(aml_equal(aml_arg(0), + aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766= ")), + aml_equal(aml_arg(0), + aml_touuid("68F2D50B-C469-4D8A-BD3D-941A103FD3FC= ")))); + aml_append(if_uuid, aml_create_dword_field(aml_arg(3), aml_int(4), "CD= W2")); + aml_append(if_uuid, aml_create_dword_field(aml_arg(3), aml_int(8), "CD= W3")); + + aml_append(if_uuid, aml_store(aml_name("CDW3"), a_ctrl)); + + /* This is all the same as what's used for PCIe */ + aml_append(if_uuid, + aml_and(aml_name("CTRL"), aml_int(0x1F), aml_name("CTRL"))); + + if_arg1_not_1 =3D aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))= ); + /* Unknown revision */ + aml_append(if_arg1_not_1, aml_or(a_cdw1, aml_int(0x08), a_cdw1)); + aml_append(if_uuid, if_arg1_not_1); + + if_caps_masked =3D aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)= )); + /* Capability bits were masked */ + aml_append(if_caps_masked, aml_or(a_cdw1, aml_int(0x10), a_cdw1)); + aml_append(if_uuid, if_caps_masked); + + aml_append(if_uuid, aml_store(aml_name("CDW2"), aml_name("SUPP"))); + aml_append(if_uuid, aml_store(aml_name("CDW3"), aml_name("CTRL"))); + + if_cxl =3D aml_if(aml_equal( + aml_arg(0), aml_touuid("68F2D50B-C469-4D8A-BD3D-941A103FD3FC"))); + /* CXL support field */ + aml_append(if_cxl, aml_create_dword_field(aml_arg(3), aml_int(12), "CD= W4")); + /* CXL capabilities */ + aml_append(if_cxl, aml_create_dword_field(aml_arg(3), aml_int(16), "CD= W5")); + aml_append(if_cxl, aml_store(aml_name("CDW4"), aml_name("SUPC"))); + aml_append(if_cxl, aml_store(aml_name("CDW5"), aml_name("CTRC"))); + + /* CXL 2.0 Port/Device Register access */ + aml_append(if_cxl, + aml_or(aml_name("CDW5"), aml_int(0x1), aml_name("CDW5"))); + aml_append(if_uuid, if_cxl); + + /* Update DWORD3 (the return value) */ + aml_append(if_uuid, aml_store(a_ctrl, aml_name("CDW3"))); + + aml_append(if_uuid, aml_return(aml_arg(3))); + aml_append(method, if_uuid); + + else_uuid =3D aml_else(); + + /* unrecognized uuid */ + aml_append(else_uuid, + aml_or(aml_name("CDW1"), aml_int(0x4), aml_name("CDW1"))); + aml_append(else_uuid, aml_return(aml_arg(3))); + aml_append(method, else_uuid); + + return method; +} + +void build_cxl_osc_method(Aml *dev) +{ + aml_append(dev, aml_name_decl("SUPP", aml_int(0))); + aml_append(dev, aml_name_decl("CTRL", aml_int(0))); + aml_append(dev, aml_name_decl("SUPC", aml_int(0))); + aml_append(dev, aml_name_decl("CTRC", aml_int(0))); + aml_append(dev, __build_cxl_osc_method()); +} diff --git a/hw/acpi/meson.build b/hw/acpi/meson.build index dd69577212..9f5c5ced28 100644 --- a/hw/acpi/meson.build +++ b/hw/acpi/meson.build @@ -10,6 +10,7 @@ acpi_ss.add(when: 'CONFIG_ACPI_CPU_HOTPLUG', if_true: fil= es('cpu_hotplug.c')) acpi_ss.add(when: 'CONFIG_ACPI_MEMORY_HOTPLUG', if_true: files('memory_hot= plug.c')) acpi_ss.add(when: 'CONFIG_ACPI_NVDIMM', if_true: files('nvdimm.c')) acpi_ss.add(when: 'CONFIG_ACPI_PCI', if_true: files('pci.c')) +acpi_ss.add(when: 'CONFIG_ACPI_CXL', if_true: files('cxl.c')) acpi_ss.add(when: 'CONFIG_ACPI_VMGENID', if_true: files('vmgenid.c')) acpi_ss.add(when: 'CONFIG_ACPI_HW_REDUCED', if_true: files('generic_event_= device.c')) acpi_ss.add(when: 'CONFIG_ACPI_HMAT', if_true: files('hmat.c')) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index ecdc10b148..2c2293b55f 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -66,6 +66,7 @@ #include "hw/acpi/aml-build.h" #include "hw/acpi/utils.h" #include "hw/acpi/pci.h" +#include "hw/acpi/cxl.h" =20 #include "qom/qom-qobject.h" #include "hw/i386/amd_iommu.h" @@ -1201,11 +1202,20 @@ static void init_pci_acpi(Aml *dev, int uid, int ty= pe) if (type =3D=3D PCI) { aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); aml_append(dev, aml_name_decl("_UID", aml_int(uid))); - } else { + } else if (type =3D=3D PCIE) { aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); aml_append(dev, aml_name_decl("_UID", aml_int(uid))); aml_append(dev, build_q35_osc_method()); + } else /* CXL */ { + struct Aml *pkg =3D aml_package(2); + + aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); + aml_append(pkg, aml_eisaid("PNP0A08")); + aml_append(pkg, aml_eisaid("PNP0A03")); + aml_append(dev, aml_name_decl("_CID", pkg)); + aml_append(dev, aml_name_decl("_UID", aml_int(uid))); + build_cxl_osc_method(dev); } } =20 diff --git a/include/hw/acpi/cxl.h b/include/hw/acpi/cxl.h new file mode 100644 index 0000000000..7b8f3b8a2e --- /dev/null +++ b/include/hw/acpi/cxl.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2020 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef HW_ACPI_CXL_H +#define HW_ACPI_CXL_H + +void build_cxl_osc_method(Aml *dev); + +#endif --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612228830; cv=none; d=zohomail.com; s=zohoarc; b=Sl3qOs4G37ElWkdwqJ3OV8ycOO3+KzHcwf1nqtG3+a2taiCq/n2ZVgpazFr2xMXD9RJ6JpNbBHt1hT6o6zwMl9fNGZRxvgJWsQH0FkSy2KkfFy+BdhAc5oql4wZ6jNCu4wazxplOOQ6zKLQdSJLtVX7J/N3q28eSC5+IM2jeU1I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612228830; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wT3pGUMaGTE29I3tGXU48Oxw7wbJmayGpm9HMBtQV3o=; b=R4fX7bb/sjYkx9sHszkVJ562YTOn+S2alj/a9cfU9GiqYNzKtBkV6xHHt0YocrTlYhtuRNaTHtb5XVvdEJrgwUbjP1BA5p8M4ycLOWNtrU+0nmPzyr1yKtira9K4YFsF+7jNHipdcDcYAXokr4wWYsdEQAm/fmXICPxPExEkcig= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612228830536223.38160912850935; Mon, 1 Feb 2021 17:20:30 -0800 (PST) Received: from localhost ([::1]:54964 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6kMn-0002te-Aa for importer@patchew.org; Mon, 01 Feb 2021 20:20:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47500) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k4O-00010I-9M for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:01:28 -0500 Received: from mga18.intel.com ([134.134.136.126]:33363) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k4L-0001oo-9G for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:01:27 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:18 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:17 -0800 IronPort-SDR: Q6eeAiz7dXi6DNB79jFjN7MByfYC+sYt/sArO2U/8GflF8RGJtts+g0lzYJRoqjaLvreYvoRw9 VZvglNxLu1ng== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457133" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457133" IronPort-SDR: cbjFCVgWKjZKIlQOD7cz4MGPr2tHuwTP6hiUvPQQ1hcV/myKKH4k0kLszb0fUs7c9gdAq2GwZf LuqsWrScKNiQ== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764247" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 24/31] tests/acpi: allow CEDT table addition Date: Mon, 1 Feb 2021 16:59:41 -0800 Message-Id: <20210202005948.241655-25-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Ben Widawsky --- tests/data/acpi/pc/CEDT | 0 tests/data/acpi/q35/CEDT | 0 tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ 3 files changed, 2 insertions(+) create mode 100644 tests/data/acpi/pc/CEDT create mode 100644 tests/data/acpi/q35/CEDT diff --git a/tests/data/acpi/pc/CEDT b/tests/data/acpi/pc/CEDT new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/q35/CEDT b/tests/data/acpi/q35/CEDT new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..9b07f1e1ff 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,3 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/pc/CEDT", +"tests/data/acpi/q35/CEDT", --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 01 Feb 2021 20:01:29 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:19 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:18 -0800 IronPort-SDR: w1dxdG5wSafwD+zv7CQ9n9S1sdZXZvEXAVcpd1a+HAJw4go4Kw3Wm4mcrb9RvPYLOv4TrFr22R PE4GRH6gwBMA== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457135" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457135" IronPort-SDR: NgEq2Mwl/JcOSGg864CBT/HUUoL6e4npNZM+RZu8acCb3VhepGbNBRPNaCCl1PvOgoxY+jtdIP 9hadoR1T4+Gw== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764257" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 25/31] acpi/cxl: Create the CEDT (9.14.1) Date: Mon, 1 Feb 2021 16:59:42 -0800 Message-Id: <20210202005948.241655-26-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The CXL Early Discovery Table is defined in the CXL 2.0 specification as a way for the OS to get CXL specific information from the system firmware. CXL 2.0 specification adds an _HID, ACPI0016, for CXL capable host bridges, with a _CID of PNP0A08 (PCIe host bridge). CXL aware software is able to use this initiate the proper _OSC method, and get the _UID which is referenced by the CEDT. Therefore the existence of an ACPI0016 device allows a CXL aware driver perform the necessary actions. For a CXL capable OS, this works. For a CXL unaware OS, this works. CEDT awaremess requires more. The motivation for ACPI0017 is to provide the possibility of having a Linux CXL module that can work on a legacy Linux kernel. Linux core PCI/ACPI which won't be built as a module, will see the _CID of PNP0A08 and bind a driver to it. If we later loaded a driver for ACPI0016, Linux won't be able to bind it to the hardware because it has already bound the PNP0A08 driver. The ACPI0017 device is an opportunity to have an object to bind a driver will be used by a Linux driver to walk the CXL topology and do everything that we would have preferred to do with ACPI0016. There is another motivation for an ACPI0017 device which isn't implemented here. An operating system needs an attach point for a non-volatile region provider that understands cross-hostbridge interleaving. Since QEMU emulation doesn't support interleaving yet, this is more important on the OS side, for now. As of CXL 2.0 spec, only 1 sub structure is defined, the CXL Host Bridge Structure (CHBS) which is primarily useful for telling the OS exactly where the MMIO for the host bridge is. v2: Update CHBS to spec released definition v3: squash ACPI0017 in now that it's ratified. Link: https://lore.kernel.org/linux-cxl/20210115034911.nkgpzc756d6qmjpl@int= el.com/T/#t Signed-off-by: Ben Widawsky --- hw/acpi/cxl.c | 69 +++++++++++++++++++++++++++++ hw/i386/acpi-build.c | 25 ++++++++++- hw/pci-bridge/pci_expander_bridge.c | 21 +-------- include/hw/acpi/cxl.h | 4 ++ include/hw/pci/pci_bridge.h | 25 +++++++++++ 5 files changed, 123 insertions(+), 21 deletions(-) diff --git a/hw/acpi/cxl.c b/hw/acpi/cxl.c index 7124d5a1a3..68db0fe3a8 100644 --- a/hw/acpi/cxl.c +++ b/hw/acpi/cxl.c @@ -18,14 +18,83 @@ */ =20 #include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/pci_host.h" #include "hw/cxl/cxl.h" +#include "hw/mem/memory-device.h" #include "hw/acpi/acpi.h" #include "hw/acpi/aml-build.h" #include "hw/acpi/bios-linker-loader.h" #include "hw/acpi/cxl.h" +#include "hw/acpi/cxl.h" #include "qapi/error.h" #include "qemu/uuid.h" =20 +static void cedt_build_chbs(GArray *table_data, PXBDev *cxl) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(cxl->cxl.cxl_host_bridge); + struct MemoryRegion *mr =3D sbd->mmio[0].memory; + + /* Type */ + build_append_int_noprefix(table_data, 0, 1); + + /* Reserved */ + build_append_int_noprefix(table_data, 0, 1); + + /* Record Length */ + build_append_int_noprefix(table_data, 32, 2); + + /* UID */ + build_append_int_noprefix(table_data, cxl->uid, 4); + + /* Version */ + build_append_int_noprefix(table_data, 1, 4); + + /* Reserved */ + build_append_int_noprefix(table_data, 0, 4); + + /* Base */ + build_append_int_noprefix(table_data, mr->addr, 8); + + /* Length */ + build_append_int_noprefix(table_data, memory_region_size(mr), 8); +} + +static int cxl_foreach_pxb_hb(Object *obj, void *opaque) +{ + Aml *cedt =3D opaque; + + if (object_dynamic_cast(obj, TYPE_PXB_CXL_DEVICE)) { + PXBDev *pxb =3D PXB_CXL_DEV(obj); + + cedt_build_chbs(cedt->buf, pxb); + } + + return 0; +} + +void cxl_build_cedt(GArray *table_offsets, GArray *table_data, + BIOSLinker *linker) +{ + const int cedt_start =3D table_data->len; + Aml *cedt; + + cedt =3D init_aml_allocator(); + + /* reserve space for CEDT header */ + acpi_add_table(table_offsets, table_data); + acpi_data_push(cedt->buf, sizeof(AcpiTableHeader)); + + object_child_foreach_recursive(object_get_root(), cxl_foreach_pxb_hb, = cedt); + + /* copy AML table into ACPI tables blob and patch header there */ + g_array_append_vals(table_data, cedt->buf->data, cedt->buf->len); + build_header(linker, table_data, (void *)(table_data->data + cedt_star= t), + "CEDT", table_data->len - cedt_start, 1, NULL, NULL); + free_aml_allocator(); +} + static Aml *__build_cxl_osc_method(void) { Aml *method, *if_uuid, *else_uuid, *if_arg1_not_1, *if_cxl, *if_caps_m= asked; diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 2c2293b55f..7706856c49 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -75,6 +75,8 @@ #include "hw/acpi/ipmi.h" #include "hw/acpi/hmat.h" =20 +#include "hw/acpi/cxl.h" + /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows * a little bit, there should be plenty of free space since the DSDT @@ -1219,6 +1221,19 @@ static void init_pci_acpi(Aml *dev, int uid, int typ= e) } } =20 +static void build_acpi0017(Aml *table) +{ + Aml *dev; + Aml *scope; + + scope =3D aml_scope("_SB"); + dev =3D aml_device("CXLM"); + aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); + + aml_append(scope, dev); + aml_append(table, scope); +} + static void build_dsdt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm, AcpiMiscInfo *misc, @@ -1235,6 +1250,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, int root_bus_limit =3D 0xFF; PCIBus *bus =3D NULL; TPMIf *tpm =3D tpm_find(); + bool cxl_present =3D false; int i; VMBusBridge *vmbus_bridge =3D vmbus_bridge_find(); =20 @@ -1371,7 +1387,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, =20 scope =3D aml_scope("\\_SB"); if (type =3D=3D CXL) { - dev =3D aml_device("CXL%.01X", pci_bus_uid(bus)); + dev =3D aml_device("CXL%.01X", uid); } else { dev =3D aml_device("PC%.02X", bus_num); } @@ -1391,6 +1407,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, =20 /* Handle the ranges for the PXB expanders */ if (type =3D=3D CXL) { + cxl_present =3D true; uint64_t base =3D CXL_HOST_BASE + uid * 0x10000; crs_range_insert(crs_range_set.mem_ranges, base, base + 0x10000 - 1); @@ -1398,6 +1415,10 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } } =20 + if (cxl_present) { + build_acpi0017(dsdt); + } + /* * At this point crs_range_set has all the ranges used by pci * busses *other* than PCI0. These ranges will be excluded from @@ -2278,6 +2299,8 @@ void acpi_build(AcpiBuildTables *tables, MachineState= *machine) machine->nvdimms_state, machine->ram_slots); } =20 + cxl_build_cedt(table_offsets, tables_blob, tables->linker); + acpi_add_table(table_offsets, tables_blob); build_waet(tables_blob, tables->linker); =20 diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index af1450c69d..6458d5b76e 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -57,26 +57,6 @@ DECLARE_INSTANCE_CHECKER(PXBDev, PXB_DEV, DECLARE_INSTANCE_CHECKER(PXBDev, PXB_PCIE_DEV, TYPE_PXB_PCIE_DEVICE) =20 -#define TYPE_PXB_CXL_DEVICE "pxb-cxl" -DECLARE_INSTANCE_CHECKER(PXBDev, PXB_CXL_DEV, - TYPE_PXB_CXL_DEVICE) - -struct PXBDev { - /*< private >*/ - PCIDevice parent_obj; - /*< public >*/ - - uint8_t bus_nr; - uint16_t numa_node; - int32_t uid; - struct cxl_dev { - HostMemoryBackend *memory_window[CXL_WINDOW_MAX]; - - uint32_t num_windows; - hwaddr *window_base[CXL_WINDOW_MAX]; - } cxl; -}; - typedef struct CXLHost { PCIHostState parent_obj; =20 @@ -351,6 +331,7 @@ static void pxb_dev_realize_common(PCIDevice *dev, enum= BusType type, bus =3D pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_CXL= _BUS); bus->flags |=3D PCI_BUS_CXL; PXB_CXL_HOST(ds)->dev =3D PXB_CXL_DEV(dev); + PXB_CXL_DEV(dev)->cxl.cxl_host_bridge =3D ds; } else { bus =3D pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_P= XB_BUS); bds =3D qdev_new("pci-bridge"); diff --git a/include/hw/acpi/cxl.h b/include/hw/acpi/cxl.h index 7b8f3b8a2e..db2063f8c9 100644 --- a/include/hw/acpi/cxl.h +++ b/include/hw/acpi/cxl.h @@ -18,6 +18,10 @@ #ifndef HW_ACPI_CXL_H #define HW_ACPI_CXL_H =20 +#include "hw/acpi/bios-linker-loader.h" + +void cxl_build_cedt(GArray *table_offsets, GArray *table_data, + BIOSLinker *linker); void build_cxl_osc_method(Aml *dev); =20 #endif diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index a94d350034..50dd7fdf33 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -28,6 +28,7 @@ =20 #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" +#include "hw/cxl/cxl.h" #include "qom/object.h" =20 typedef struct PCIBridgeWindows PCIBridgeWindows; @@ -81,6 +82,30 @@ struct PCIBridge { #define PCI_BRIDGE_DEV_PROP_MSI "msi" #define PCI_BRIDGE_DEV_PROP_SHPC "shpc" =20 +struct PXBDev { + /*< private >*/ + PCIDevice parent_obj; + /*< public >*/ + + uint8_t bus_nr; + uint16_t numa_node; + int32_t uid; + + struct cxl_dev { + HostMemoryBackend *memory_window[CXL_WINDOW_MAX]; + + uint32_t num_windows; + hwaddr *window_base[CXL_WINDOW_MAX]; + + void *cxl_host_bridge; /* Pointer to a CXLHost */ + } cxl; +}; + +typedef struct PXBDev PXBDev; +#define TYPE_PXB_CXL_DEVICE "pxb-cxl" +DECLARE_INSTANCE_CHECKER(PXBDev, PXB_CXL_DEV, + TYPE_PXB_CXL_DEVICE) + int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, uint16_t svid, uint16_t ssid, Error **errp); --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; 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01 Feb 2021 17:00:19 -0800 IronPort-SDR: 8L4aHyKKWVtPtFLWoeyJLCz10ckM8UMr0fi0vo6xyW6R5HZphByk/Z8Ayw/TQJCzr+CAb+7S29 4YcKXndWUgaw== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457138" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457138" IronPort-SDR: szHpHkEB6C+oRtvKQRdrkrz1rx3RiRZtvYZYUqXU2QITVjCeoPVnHjhR+bLvtlLFJAFYGvUGrz jQx1egXaE6FQ== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764264" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 26/31] tests/acpi: Add new CEDT files Date: Mon, 1 Feb 2021 16:59:43 -0800 Message-Id: <20210202005948.241655-27-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Ben Widawsky --- tests/data/acpi/pc/CEDT | Bin 0 -> 36 bytes tests/data/acpi/q35/CEDT | Bin 0 -> 36 bytes tests/qtest/bios-tables-test-allowed-diff.h | 2 -- 3 files changed, 2 deletions(-) diff --git a/tests/data/acpi/pc/CEDT b/tests/data/acpi/pc/CEDT index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..ebf9b54b0b27d9efca53359c3c2= e560511f0e165 100644 GIT binary patch literal 36 kcmZ>EbqP^nU|?X};NEbqP^nU|?X};N (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612229364976562.4943851919782; Mon, 1 Feb 2021 17:29:24 -0800 (PST) Received: from localhost ([::1]:47248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6kVP-0003jy-SG for importer@patchew.org; Mon, 01 Feb 2021 20:29:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47542) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k4b-0001Cl-V1 for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:01:41 -0500 Received: from mga18.intel.com ([134.134.136.126]:33363) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k4Y-0001oo-MA for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:01:41 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:21 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:20 -0800 IronPort-SDR: 3TsdDgCIPMB778c1+pO7bXZm9acEOZzYOzUXhgWmrQ+7LFPU36FwLi/V3Q21cgbFC5QHhIU36d U6XV0cKuN8zQ== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457142" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457142" IronPort-SDR: o8unHbL+Q7kfvn/BzE0nugN5IyABc3t75wJiLb2iU2DkxyzQ0LnwUzjx0UOP8+XpHs3E6r/8pq h8tnnGZoP38Q== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764272" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 27/31] hw/cxl/device: Add some trivial commands Date: Mon, 1 Feb 2021 16:59:44 -0800 Message-Id: <20210202005948.241655-28-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" GET_FW_INFO and GET_PARTITION_INFO, for this emulation, is equivalent to info already returned in the IDENTIFY command. To have a more robust implementation, add those. Signed-off-by: Ben Widawsky --- hw/cxl/cxl-mailbox-utils.c | 65 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index f92dfad882..dc8e0eb08e 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -43,6 +43,8 @@ enum { #define CLEAR_RECORDS 0x1 #define GET_INTERRUPT_POLICY 0x2 #define SET_INTERRUPT_POLICY 0x3 + FIRMWARE_UPDATE =3D 0x02, + #define GET_INFO 0x0 TIMESTAMP =3D 0x03, #define GET 0x0 #define SET 0x1 @@ -51,6 +53,8 @@ enum { #define GET_LOG 0x1 IDENTIFY =3D 0x40, #define MEMORY_DEVICE 0x0 + CCLS =3D 0x41, + #define GET_PARTITION_INFO 0x0 }; =20 /* 8.2.8.4.5.1 Command Return Codes */ @@ -125,11 +129,13 @@ define_mailbox_handler_zeroed(EVENTS_GET_RECORDS, 0x2= 0); define_mailbox_handler_nop(EVENTS_CLEAR_RECORDS); define_mailbox_handler_zeroed(EVENTS_GET_INTERRUPT_POLICY, 4); define_mailbox_handler_nop(EVENTS_SET_INTERRUPT_POLICY); +declare_mailbox_handler(FIRMWARE_UPDATE_GET_INFO); declare_mailbox_handler(TIMESTAMP_GET); declare_mailbox_handler(TIMESTAMP_SET); declare_mailbox_handler(LOGS_GET_SUPPORTED); declare_mailbox_handler(LOGS_GET_LOG); declare_mailbox_handler(IDENTIFY_MEMORY_DEVICE); +declare_mailbox_handler(CCLS_GET_PARTITION_INFO); =20 #define IMMEDIATE_CONFIG_CHANGE (1 << 1) #define IMMEDIATE_POLICY_CHANGE (1 << 3) @@ -143,15 +149,50 @@ static struct cxl_cmd cxl_cmd_set[256][256] =3D { CXL_CMD(EVENTS, CLEAR_RECORDS, ~0, IMMEDIATE_LOG_CHANGE), CXL_CMD(EVENTS, GET_INTERRUPT_POLICY, 0, 0), CXL_CMD(EVENTS, SET_INTERRUPT_POLICY, 4, IMMEDIATE_CONFIG_CHANGE), + CXL_CMD(FIRMWARE_UPDATE, GET_INFO, 0, 0), CXL_CMD(TIMESTAMP, GET, 0, 0), CXL_CMD(TIMESTAMP, SET, 8, IMMEDIATE_POLICY_CHANGE), CXL_CMD(LOGS, GET_SUPPORTED, 0, 0), CXL_CMD(LOGS, GET_LOG, 0x18, 0), CXL_CMD(IDENTIFY, MEMORY_DEVICE, 0, 0), + CXL_CMD(CCLS, GET_PARTITION_INFO, 0, 0), }; =20 #undef CXL_CMD =20 +/* + * 8.2.9.2.1 + */ +define_mailbox_handler(FIRMWARE_UPDATE_GET_INFO) +{ + struct { + uint8_t slots_supported; + uint8_t slot_info; + uint8_t caps; + uint8_t rsvd[0xd]; + char fw_rev1[0x10]; + char fw_rev2[0x10]; + char fw_rev3[0x10]; + char fw_rev4[0x10]; + } __attribute__((packed)) *fw_info; + _Static_assert(sizeof(*fw_info) =3D=3D 0x50, "Bad firmware info size"); + + if (memory_region_size(cxl_dstate->pmem) < (256 << 20)) { + return CXL_MBOX_INTERNAL_ERROR; + } + + fw_info =3D (void *)cmd->payload; + memset(fw_info, 0, sizeof(*fw_info)); + + fw_info->slots_supported =3D 2; + fw_info->slot_info =3D BIT(0) | BIT(3); + fw_info->caps =3D 0; + snprintf(fw_info->fw_rev1, 0x10, "BWFW VERSION %02d", 0); + + *len =3D sizeof(*fw_info); + return CXL_MBOX_SUCCESS; +} + /* * 8.2.9.3.1 */ @@ -296,6 +337,30 @@ define_mailbox_handler(IDENTIFY_MEMORY_DEVICE) return CXL_MBOX_SUCCESS; } =20 +define_mailbox_handler(CCLS_GET_PARTITION_INFO) +{ + struct { + uint64_t active_vmem; + uint64_t active_pmem; + uint64_t next_vmem; + uint64_t next_pmem; + } __attribute__((packed)) *part_info =3D (void *)cmd->payload; + _Static_assert(sizeof(*part_info) =3D=3D 0x20, "Bad get partition info= size"); + + if (memory_region_size(cxl_dstate->pmem) < (256 << 20)) { + return CXL_MBOX_INTERNAL_ERROR; + } + + /* PMEM only */ + part_info->active_vmem =3D 0; + part_info->next_vmem =3D 0; + part_info->active_pmem =3D memory_region_size(cxl_dstate->pmem); + part_info->next_pmem =3D part_info->active_pmem; + + *len =3D sizeof(*part_info); + return CXL_MBOX_SUCCESS; +} + void cxl_process_mailbox(CXLDeviceState *cxl_dstate) { uint16_t ret =3D CXL_MBOX_SUCCESS; --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612228856; cv=none; d=zohomail.com; s=zohoarc; b=SXu+8JF7l33rTZpGUvs360LdB0VnXwvuFm/s6Jsj6tKO4z6NnItGy/KvrgXEGvRZDQco6OiSMtG3tFleHCb5rJsseWQq0wIyvrWDg72GAdqHC6PQvRUFyVqTue9QoAZBwtIpro18g4GgzLeUogsMUDjbJKHOjSEypXMZGREm08E= ARC-Message-Signature: i=1; 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Mon, 01 Feb 2021 20:20:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47550) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k4d-0001Gs-Fg for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:01:43 -0500 Received: from mga18.intel.com ([134.134.136.126]:33366) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k4a-0001pl-JF for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:01:43 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:22 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:21 -0800 IronPort-SDR: QduUGKMH09nFd/16ONe+nAC2Pri87rWRFNybHJ5TdfwOjsss9kjwHruUaiciWT5L5lIs7wIj5W Ha8ulZkvMsTQ== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457143" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457143" IronPort-SDR: k0REhMz+lyLKzjTCvQ7dQ6nkrBk5hl9cmIC4smyfGvqNkxh1rni2rHirnyBDBREHQJVHL5eo+/ C8Y0AfBE7XZQ== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764279" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 28/31] hw/cxl/device: Plumb real LSA sizing Date: Mon, 1 Feb 2021 16:59:45 -0800 Message-Id: <20210202005948.241655-29-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This should introduce no change. Subsequent work will make use of this new class member. Signed-off-by: Ben Widawsky --- hw/cxl/cxl-mailbox-utils.c | 4 ++++ hw/mem/cxl_type3.c | 24 +++++++++--------------- include/hw/cxl/cxl.h | 1 - include/hw/cxl/cxl_device.h | 24 ++++++++++++++++++++++++ 4 files changed, 37 insertions(+), 16 deletions(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index dc8e0eb08e..2637250c7b 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -321,6 +321,9 @@ define_mailbox_handler(IDENTIFY_MEMORY_DEVICE) } __attribute__((packed)) *id; _Static_assert(sizeof(*id) =3D=3D 0x43, "Bad identify size"); =20 + CXLType3Dev *ct3d =3D container_of(cxl_dstate, CXLType3Dev, cxl_dstate= ); + CXLType3Class *cvc =3D CXL_TYPE3_DEV_GET_CLASS(ct3d); + if (memory_region_size(cxl_dstate->pmem) < (256 << 20)) { return CXL_MBOX_INTERNAL_ERROR; } @@ -332,6 +335,7 @@ define_mailbox_handler(IDENTIFY_MEMORY_DEVICE) snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 0); id->total_capacity =3D memory_region_size(cxl_dstate->pmem); id->persistent_capacity =3D memory_region_size(cxl_dstate->pmem); + id->lsa_size =3D cvc->get_lsa_size(ct3d); =20 *len =3D sizeof(*id); return CXL_MBOX_SUCCESS; diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index fe02c3b63c..074d1dd41f 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -13,21 +13,6 @@ #include "sysemu/hostmem.h" #include "hw/cxl/cxl.h" =20 -typedef struct cxl_type3_dev { - /* Private */ - PCIDevice parent_obj; - - /* Properties */ - uint64_t size; - HostMemoryBackend *hostmem; - - /* State */ - CXLComponentState cxl_cstate; - CXLDeviceState cxl_dstate; -} CXLType3Dev; - -#define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV) - static void build_dvsecs(CXLType3Dev *ct3d) { CXLComponentState *cxl_cstate =3D &ct3d->cxl_cstate; @@ -310,11 +295,17 @@ static void pc_dimm_md_fill_device_info(const MemoryD= eviceState *md, info->type =3D MEMORY_DEVICE_INFO_KIND_CXL; } =20 +static uint64_t get_lsa_size(CXLType3Dev *ct3d) +{ + return 0; +} + static void ct3_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); PCIDeviceClass *pc =3D PCI_DEVICE_CLASS(oc); MemoryDeviceClass *mdc =3D MEMORY_DEVICE_CLASS(oc); + CXLType3Class *cvc =3D CXL_TYPE3_DEV_CLASS(oc); =20 pc->realize =3D ct3_realize; pc->class_id =3D PCI_CLASS_STORAGE_EXPRESS; @@ -332,11 +323,14 @@ static void ct3_class_init(ObjectClass *oc, void *dat= a) mdc->fill_device_info =3D pc_dimm_md_fill_device_info; mdc->get_plugged_size =3D memory_device_get_region_size; mdc->set_addr =3D cxl_md_set_addr; + + cvc->get_lsa_size =3D get_lsa_size; } =20 static const TypeInfo ct3d_info =3D { .name =3D TYPE_CXL_TYPE3_DEV, .parent =3D TYPE_PCI_DEVICE, + .class_size =3D sizeof(struct CXLType3Class), .class_init =3D ct3_class_init, .instance_size =3D sizeof(CXLType3Dev), .instance_init =3D ct3_instance_init, diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h index 809ed7de60..c7ca42930f 100644 --- a/include/hw/cxl/cxl.h +++ b/include/hw/cxl/cxl.h @@ -23,4 +23,3 @@ #define CXL_WINDOW_MAX 10 =20 #endif - diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index ca5328a581..a79a0f106c 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -219,4 +219,28 @@ REG32(CXL_MEM_DEV_STS, 0) FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1) FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3) =20 +typedef struct cxl_type3_dev { + /* Private */ + PCIDevice parent_obj; + + /* Properties */ + uint64_t size; + HostMemoryBackend *hostmem; + HostMemoryBackend *lsa; + + /* State */ + CXLComponentState cxl_cstate; + CXLDeviceState cxl_dstate; +} CXLType3Dev; + +#define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV) + +struct CXLType3Class { + /* Private */ + PCIDeviceClass parent_class; + + /* public */ + uint64_t (*get_lsa_size)(CXLType3Dev *ct3d); +}; + #endif --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612229025; cv=none; d=zohomail.com; s=zohoarc; b=KyV9XuLKdtY1xqeF9x3V12vLrmoHNhWRLQo/SEKZFV1EXK6qH9v7GcO4yzE3TbJBbFVAxRmoBv6XD535NuncVSv207jExIqEng6eArhLM4SPcwwfftYGM7wZ7prpdzh1V0VM2+T1b9ykv9SErI+9zcZpSf/zNZgESrzH3DquwEw= ARC-Message-Signature: i=1; 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Mon, 01 Feb 2021 20:23:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47594) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k4p-0001V3-FY for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:01:59 -0500 Received: from mga18.intel.com ([134.134.136.126]:33362) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k4l-0001oN-NL for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:01:54 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:23 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:22 -0800 IronPort-SDR: v05LDNdUfQN9Z96HEcf9T2zTDQaqrHy40/dITgGD4aeRwJqzeDVj/Vy5sX3zXq0H05SDfnbF6G MgCMOtRVeJwA== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457146" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457146" IronPort-SDR: K5rtL84rOMlfk3+mYrpCwOa5uyv/QLL33wWhM5EoS8q+XBr6WDnBBL6tm/IqjH58lyNIVy9R8i 7tqIK7pfGqbQ== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764287" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 29/31] hw/cxl/device: Implement get/set LSA Date: Mon, 1 Feb 2021 16:59:46 -0800 Message-Id: <20210202005948.241655-30-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Ben Widawsky --- hw/cxl/cxl-mailbox-utils.c | 50 +++++++++++++++++++++++++++++++++ hw/mem/cxl_type3.c | 56 ++++++++++++++++++++++++++++++++++++- include/hw/cxl/cxl_device.h | 9 ++++++ 3 files changed, 114 insertions(+), 1 deletion(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 2637250c7b..c133cf0341 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -55,6 +55,8 @@ enum { #define MEMORY_DEVICE 0x0 CCLS =3D 0x41, #define GET_PARTITION_INFO 0x0 + #define GET_LSA 0x2 + #define SET_LSA 0x3 }; =20 /* 8.2.8.4.5.1 Command Return Codes */ @@ -136,8 +138,11 @@ declare_mailbox_handler(LOGS_GET_SUPPORTED); declare_mailbox_handler(LOGS_GET_LOG); declare_mailbox_handler(IDENTIFY_MEMORY_DEVICE); declare_mailbox_handler(CCLS_GET_PARTITION_INFO); +declare_mailbox_handler(CCLS_GET_LSA); +declare_mailbox_handler(CCLS_SET_LSA); =20 #define IMMEDIATE_CONFIG_CHANGE (1 << 1) +#define IMMEDIATE_DATA_CHANGE (1 << 1) #define IMMEDIATE_POLICY_CHANGE (1 << 3) #define IMMEDIATE_LOG_CHANGE (1 << 4) =20 @@ -156,6 +161,8 @@ static struct cxl_cmd cxl_cmd_set[256][256] =3D { CXL_CMD(LOGS, GET_LOG, 0x18, 0), CXL_CMD(IDENTIFY, MEMORY_DEVICE, 0, 0), CXL_CMD(CCLS, GET_PARTITION_INFO, 0, 0), + CXL_CMD(CCLS, GET_LSA, 0, 0), + CXL_CMD(CCLS, SET_LSA, ~0, IMMEDIATE_CONFIG_CHANGE | IMMEDIATE_DATA_CH= ANGE), }; =20 #undef CXL_CMD @@ -365,6 +372,49 @@ define_mailbox_handler(CCLS_GET_PARTITION_INFO) return CXL_MBOX_SUCCESS; } =20 +define_mailbox_handler(CCLS_GET_LSA) +{ + struct { + uint32_t offset; + uint32_t length; + } __attribute__((packed, __aligned__(16))) *get_lsa; + CXLType3Dev *ct3d =3D container_of(cxl_dstate, CXLType3Dev, cxl_dstate= ); + CXLType3Class *cvc =3D CXL_TYPE3_DEV_GET_CLASS(ct3d); + uint32_t offset, length; + + get_lsa =3D (void *)cmd->payload; + offset =3D get_lsa->offset; + length =3D get_lsa->length; + + *len =3D 0; + if (offset + length > cvc->get_lsa_size(ct3d)) { + return CXL_MBOX_INVALID_INPUT; + } + + *len =3D cvc->get_lsa(ct3d, get_lsa, length, offset); + return CXL_MBOX_SUCCESS; +} + +define_mailbox_handler(CCLS_SET_LSA) +{ + struct { + uint32_t offset; + uint32_t rsvd; + void *data; + } __attribute__((packed, __aligned__(16))) *set_lsa =3D (void *)cmd->p= ayload; + CXLType3Dev *ct3d =3D container_of(cxl_dstate, CXLType3Dev, cxl_dstate= ); + CXLType3Class *cvc =3D CXL_TYPE3_DEV_GET_CLASS(ct3d); + uint16_t plen =3D *len; + + *len =3D 0; + if ((set_lsa->offset + plen) > cvc->get_lsa_size(ct3d)) { + return CXL_MBOX_INVALID_INPUT; + } + + cvc->set_lsa(ct3d, set_lsa->data, plen, set_lsa->offset); + return CXL_MBOX_SUCCESS; +} + void cxl_process_mailbox(CXLDeviceState *cxl_dstate) { uint16_t ret =3D CXL_MBOX_SUCCESS; diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 074d1dd41f..d091e645aa 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -8,6 +8,7 @@ #include "qapi/error.h" #include "qemu/log.h" #include "qemu/module.h" +#include "qemu/pmem.h" #include "qemu/range.h" #include "qemu/rcu.h" #include "sysemu/hostmem.h" @@ -148,6 +149,11 @@ static void cxl_setup_memory(CXLType3Dev *ct3d, Error = **errp) return; } =20 + if (!ct3d->lsa) { + error_setg(errp, "lsa property must be set"); + return; + } + /* FIXME: need to check mr is the host bridge's MR */ mr =3D host_memory_backend_get_memory(ct3d->hostmem); =20 @@ -267,6 +273,8 @@ static Property ct3_props[] =3D { DEFINE_PROP_SIZE("size", CXLType3Dev, size, -1), DEFINE_PROP_LINK("memdev", CXLType3Dev, hostmem, TYPE_MEMORY_BACKEND, HostMemoryBackend *), + DEFINE_PROP_LINK("lsa", CXLType3Dev, lsa, TYPE_MEMORY_BACKEND, + HostMemoryBackend *), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -297,7 +305,51 @@ static void pc_dimm_md_fill_device_info(const MemoryDe= viceState *md, =20 static uint64_t get_lsa_size(CXLType3Dev *ct3d) { - return 0; + MemoryRegion *mr; + + mr =3D host_memory_backend_get_memory(ct3d->lsa); + return memory_region_size(mr); +} + +static void validate_lsa_access(MemoryRegion *mr, uint64_t size, + uint64_t offset) +{ + assert(offset + size <=3D memory_region_size(mr)); + assert(offset + size > offset); +} + +static uint64_t get_lsa(CXLType3Dev *ct3d, void *buf, uint64_t size, + uint64_t offset) +{ + MemoryRegion *mr; + void *lsa; + + mr =3D host_memory_backend_get_memory(ct3d->lsa); + validate_lsa_access(mr, size, offset); + + lsa =3D memory_region_get_ram_ptr(mr) + offset; + memcpy(buf, lsa, size); + + return size; +} + +static void set_lsa(CXLType3Dev *ct3d, const void *buf, uint64_t size, + uint64_t offset) +{ + MemoryRegion *mr; + void *lsa; + + mr =3D host_memory_backend_get_memory(ct3d->lsa); + validate_lsa_access(mr, size, offset); + + lsa =3D memory_region_get_ram_ptr(mr) + offset; + memcpy(lsa, buf, size); + memory_region_set_dirty(mr, offset, size); + + /* + * Just like the PMEM, if the guest is not allowed to exit gracefully,= label + * updates will get lost. + */ } =20 static void ct3_class_init(ObjectClass *oc, void *data) @@ -325,6 +377,8 @@ static void ct3_class_init(ObjectClass *oc, void *data) mdc->set_addr =3D cxl_md_set_addr; =20 cvc->get_lsa_size =3D get_lsa_size; + cvc->get_lsa =3D get_lsa; + cvc->set_lsa =3D set_lsa; } =20 static const TypeInfo ct3d_info =3D { diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index a79a0f106c..1869876ef6 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -233,7 +233,11 @@ typedef struct cxl_type3_dev { CXLDeviceState cxl_dstate; } CXLType3Dev; =20 +#ifndef TYPE_CXL_TYPE3_DEV +#define TYPE_CXL_TYPE3_DEV "cxl-type3" +#endif #define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV) +OBJECT_DECLARE_TYPE(CXLType3Device, CXLType3Class, CXL_TYPE3_DEV) =20 struct CXLType3Class { /* Private */ @@ -241,6 +245,11 @@ struct CXLType3Class { =20 /* public */ uint64_t (*get_lsa_size)(CXLType3Dev *ct3d); + + uint64_t (*get_lsa)(CXLType3Dev *ct3d, void *buf, uint64_t size, + uint64_t offset); + void (*set_lsa)(CXLType3Dev *ct3d, const void *buf, uint64_t size, + uint64_t offset); }; =20 #endif --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612229236; cv=none; d=zohomail.com; s=zohoarc; b=IZbXTS2n4evW8m9Booe/QwIls+h6pwJll3VflGjJSe2HfYPZvcLoZu8n2l9g7CvrOZPR6A4aCu8tjlTNExN+EA4Hvn/7cNRNxn8GNdG74rBJJ8Y1bI+nDwU0DM3Bsl/qJ1lLboakVEdm6tf7hRh0qirB02HamGGhJW2TvKpfpsE= ARC-Message-Signature: i=1; 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Mon, 01 Feb 2021 20:27:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47628) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k4t-0001WF-EO for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:02:00 -0500 Received: from mga18.intel.com ([134.134.136.126]:33363) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k4m-0001oo-HT for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:01:58 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:25 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:23 -0800 IronPort-SDR: ZoNO510NHYEyvrmvx/33j0XVcH3CzpXsPfyZ7SzAn3CWJBMJuRTcOLZ2z2UpITjGszAvbDX1pM 5VVBoAPIXpuQ== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457148" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457148" IronPort-SDR: gaLajS1KKfepojaxXY1K+YOXX8MADJ1ZoGGUwHtf/ghOeEx57GILnkCQG9RuYGUgOnmczUNVsm TRCA2X7hVlwA== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764293" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 30/31] qtest/cxl: Add very basic sanity tests Date: Mon, 1 Feb 2021 16:59:47 -0800 Message-Id: <20210202005948.241655-31-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Ben Widawsky --- tests/qtest/cxl-test.c | 93 +++++++++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 4 ++ 2 files changed, 97 insertions(+) create mode 100644 tests/qtest/cxl-test.c diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c new file mode 100644 index 0000000000..00eca14faa --- /dev/null +++ b/tests/qtest/cxl-test.c @@ -0,0 +1,93 @@ +/* + * QTest testcase for CXL + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +#define QEMU_PXB_CMD "-machine q35 -object memory-backend-file,id=3Dcxl-me= m1," \ + "share,mem-path=3D%s,size=3D512M " = \ + "-device pxb-cxl,id=3Dcxl.0,bus=3Dpcie.0,bus_nr=3D52,= uid=3D0," \ + "len-window-base=3D1,window-base[0]=3D0x4c0000000,mem= dev[0]=3Dcxl-mem1" +#define QEMU_RP "-device cxl-rp,id=3Drp0,bus=3Dcxl.0,addr=3D0.0,chassis=3D= 0,slot=3D0" + +#define QEMU_T3D "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem1,id=3Dcxl-p= mem0,size=3D256M" + +static void cxl_basic_hb(void) +{ + qtest_start("-machine q35,cxl"); + qtest_end(); +} + +static void cxl_basic_pxb(void) +{ + qtest_start("-machine q35 -device pxb-cxl,bus=3Dpcie.0,uid=3D0"); + qtest_end(); +} + +static void cxl_pxb_with_window(void) +{ + GString *cmdline; + char template[] =3D "/tmp/cxl-test-XXXXXX"; + const char *tmpfs; + + tmpfs =3D mkdtemp(template); + + cmdline =3D g_string_new(NULL); + g_string_printf(cmdline, QEMU_PXB_CMD, tmpfs); + + qtest_start(cmdline->str); + qtest_end(); + + g_string_free(cmdline, TRUE); +} + +static void cxl_root_port(void) +{ + GString *cmdline; + char template[] =3D "/tmp/cxl-test-XXXXXX"; + const char *tmpfs; + + tmpfs =3D mkdtemp(template); + + cmdline =3D g_string_new(NULL); + g_string_printf(cmdline, QEMU_PXB_CMD " %s", tmpfs, QEMU_RP); + + qtest_start(cmdline->str); + qtest_end(); + + g_string_free(cmdline, TRUE); +} + +static void cxl_t3d(void) +{ + GString *cmdline; + char template[] =3D "/tmp/cxl-test-XXXXXX"; + const char *tmpfs; + + tmpfs =3D mkdtemp(template); + + cmdline =3D g_string_new(NULL); + g_string_printf(cmdline, QEMU_PXB_CMD " %s %s", tmpfs, QEMU_RP, QEMU_T= 3D); + + qtest_start(cmdline->str); + qtest_end(); + + g_string_free(cmdline, TRUE); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); + qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); + qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); + qtest_add_func("/pci/cxl/root_port", cxl_root_port); + qtest_add_func("/pci/cxl/type3_device", cxl_t3d); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index c83bc211b6..554152b7c5 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -22,6 +22,9 @@ qtests_pci =3D \ (config_all_devices.has_key('CONFIG_VGA') ? ['display-vga-test'] : []) += \ (config_all_devices.has_key('CONFIG_IVSHMEM_DEVICE') ? ['ivshmem-test'] = : []) =20 +qtests_cxl =3D \ + (config_all_devices.has_key('CONFIG_CXL') ? ['cxl-test'] : []) + qtests_i386 =3D \ (slirp.found() ? ['pxe-test', 'test-netfilter'] : []) + \ (config_host.has_key('CONFIG_POSIX') ? ['test-filter-mirror'] : []) + = \ @@ -48,6 +51,7 @@ qtests_i386 =3D \ (config_all_devices.has_key('CONFIG_TPM_TIS_ISA') ? ['tpm-tis-swtpm-test= '] : []) + \ (config_all_devices.has_key('CONFIG_RTL8139_PCI') ? ['rtl8139-test'] : [= ]) + \ qtests_pci + = \ + qtests_cxl + = \ ['fdc-test', 'ide-test', 'hd-geo-test', --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1612229463; cv=none; d=zohomail.com; s=zohoarc; b=dhVFQppRcDIHGIG/nDUX/4cy9H6hl/tbmovYy0X0FmlHsW6v1Ghr61MkGafnYeA2m2fCX3+33MLKfNMGh8xx7ReWRVo7hit2DH04HxkqhwCd3pi0YAA/AlRXt+NA8rdoGmd/4vLP5oVx3Ry1WYV/GstorxtSFvp5dtRsgi+1les= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612229463; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1xuQm9dCAoMnZfCMcPxV/LX7s7WP3Uk2sxyDikI/Nf0=; b=kTEhy/N8yHXMnByrIVaV+DEtMABB/mfatou8J7hVTggUd0/xSdQixtTVvAfprbAyv+JVGUnbaTlDlakIblZxcbAO/lc9FAI7eJ3QIGWAWlygAO5+RlVkDxeEeUyXoOiN7s83EfyCnyqJU+tBdafBV8WOWJpttLM3PrRH9RU/18I= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612229463846297.94050567121815; Mon, 1 Feb 2021 17:31:03 -0800 (PST) Received: from localhost ([::1]:51464 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6kX0-0005aw-H9 for importer@patchew.org; Mon, 01 Feb 2021 20:31:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47630) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k4v-0001Wd-3x for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:02:02 -0500 Received: from mga18.intel.com ([134.134.136.126]:33366) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6k4o-0001pl-21 for qemu-devel@nongnu.org; Mon, 01 Feb 2021 20:01:59 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:26 -0800 Received: from jambrizm-mobl1.amr.corp.intel.com (HELO bwidawsk-mobl5.local) ([10.252.133.15]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2021 17:00:25 -0800 IronPort-SDR: RbWNhIq66FHjwOzQqMs31xx+5y3RRMUNCrdp3uqWrudqLBdxtJ9WLlibjiyLHZSI33h+zfyyrH 0pU/WL83b8EA== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="168457152" X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="168457152" IronPort-SDR: pID+Kk5wCa5xaL+elfLvZdOkQuGpMMDz8H4DHkOjyytAIxzDnvaSzejO8eGDm8HB+SuaiPLV+k +ZKSh/sVum1w== X-IronPort-AV: E=Sophos;i="5.79,393,1602572400"; d="scan'208";a="581764297" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 31/31] WIP: i386/cxl: Initialize a host bridge Date: Mon, 1 Feb 2021 16:59:48 -0800 Message-Id: <20210202005948.241655-32-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.126; envelope-from=ben.widawsky@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ben Widawsky , David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , Markus Armbruster , linux-cxl@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This patch allows initializing the primary host bridge as a CXL capable hostbridge. Signed-off-by: Ben Widawsky -- This patch is WIP. --- hw/arm/virt.c | 1 + hw/core/machine.c | 26 ++++++++++++++++++++++++++ hw/i386/acpi-build.c | 8 +++++++- hw/i386/microvm.c | 1 + hw/i386/pc.c | 1 + hw/ppc/spapr.c | 2 ++ include/hw/boards.h | 2 ++ include/hw/cxl/cxl.h | 4 ++++ 8 files changed, 44 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 399da73454..fd5f5b656c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2547,6 +2547,7 @@ static void virt_machine_class_init(ObjectClass *oc, = void *data) hc->unplug_request =3D virt_machine_device_unplug_request_cb; hc->unplug =3D virt_machine_device_unplug_cb; mc->nvdimm_supported =3D true; + mc->cxl_supported =3D false; mc->auto_enable_numa_with_memhp =3D true; mc->auto_enable_numa_with_memdev =3D true; mc->default_ram_id =3D "mach-virt.ram"; diff --git a/hw/core/machine.c b/hw/core/machine.c index de3b8f1b31..c739803854 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -30,6 +30,7 @@ #include "sysemu/qtest.h" #include "hw/pci/pci.h" #include "hw/mem/nvdimm.h" +#include "hw/cxl/cxl.h" #include "migration/global_state.h" #include "migration/vmstate.h" =20 @@ -502,6 +503,20 @@ static void machine_set_nvdimm_persistence(Object *obj= , const char *value, nvdimms_state->persistence_string =3D g_strdup(value); } =20 +static bool machine_get_cxl(Object *obj, Error **errp) +{ + MachineState *ms =3D MACHINE(obj); + + return ms->cxl_devices_state->is_enabled; +} + +static void machine_set_cxl(Object *obj, bool value, Error **errp) +{ + MachineState *ms =3D MACHINE(obj); + + ms->cxl_devices_state->is_enabled =3D value; +} + void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *= type) { QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type)); @@ -903,6 +918,16 @@ static void machine_initfn(Object *obj) "Valid values are cpu, mem-ctrl"); } =20 + if (mc->cxl_supported) { + Object *obj =3D OBJECT(ms); + + ms->cxl_devices_state =3D g_new0(CXLState, 1); + object_property_add_bool(obj, "cxl", machine_get_cxl, machine_set_= cxl); + object_property_set_description(obj, "cxl", + "Set on/off to enable/disable " + "CXL instantiation"); + } + if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { ms->numa_state =3D g_new0(NumaState, 1); object_property_add_bool(obj, "hmat", @@ -939,6 +964,7 @@ static void machine_finalize(Object *obj) g_free(ms->device_memory); g_free(ms->nvdimms_state); g_free(ms->numa_state); + g_free(ms->cxl_devices_state); } =20 bool machine_usb(MachineState *machine) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 7706856c49..2250e6d27b 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -53,6 +53,7 @@ #include "sysemu/numa.h" #include "sysemu/reset.h" #include "hw/hyperv/vmbus-bridge.h" +#include "hw/cxl/cxl.h" =20 /* Supported chipsets: */ #include "hw/southbridge/piix.h" @@ -1277,8 +1278,13 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, build_piix4_pci0_int(dsdt); } else { sb_scope =3D aml_scope("_SB"); + /* + * XXX: CXL spec calls this "CXL0", but that would require lots of + * changes throughout and so even for CXL enabled, we call it "PCI= 0" + */ dev =3D aml_device("PCI0"); - init_pci_acpi(dev, 0, PCIE); + init_pci_acpi(dev, 0, + machine->cxl_devices_state->is_enabled ? CXL : PCIE); aml_append(dev, aml_name_decl("_ADR", aml_int(0))); aml_append(sb_scope, dev); =20 diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index edf2b0f061..970b299a69 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -688,6 +688,7 @@ static void microvm_class_init(ObjectClass *oc, void *d= ata) mc->auto_enable_numa_with_memdev =3D false; mc->default_cpu_type =3D TARGET_DEFAULT_CPU_TYPE; mc->nvdimm_supported =3D false; + mc->cxl_supported =3D false; mc->default_ram_id =3D "microvm.ram"; =20 /* Avoid relying too much on kernel components */ diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 5d41809b37..7350eeea9c 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1725,6 +1725,7 @@ static void pc_machine_class_init(ObjectClass *oc, vo= id *data) hc->unplug =3D pc_machine_device_unplug_cb; mc->default_cpu_type =3D TARGET_DEFAULT_CPU_TYPE; mc->nvdimm_supported =3D true; + mc->cxl_supported =3D true; mc->default_ram_id =3D "pc.ram"; =20 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 6c47466fc2..9773dbd83c 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4440,6 +4440,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power9_v2.0"); mc->has_hotpluggable_cpus =3D true; mc->nvdimm_supported =3D true; + mc->cxl_supported =3D false; smc->resize_hpt_default =3D SPAPR_RESIZE_HPT_ENABLED; fwc->get_dev_path =3D spapr_get_fw_dev_path; nc->nmi_monitor_handler =3D spapr_nmi; @@ -4600,6 +4601,7 @@ static void spapr_machine_4_2_class_options(MachineCl= ass *mc) smc->default_caps.caps[SPAPR_CAP_FWNMI] =3D SPAPR_CAP_OFF; smc->rma_limit =3D 16 * GiB; mc->nvdimm_supported =3D false; + mc->cxl_supported =3D false; } =20 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); diff --git a/include/hw/boards.h b/include/hw/boards.h index 17b1f3f0b9..808f73e134 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -206,6 +206,7 @@ struct MachineClass { bool ignore_boot_device_suffixes; bool smbus_no_migration_support; bool nvdimm_supported; + bool cxl_supported; bool numa_mem_supported; bool auto_enable_numa; const char *default_ram_id; @@ -292,6 +293,7 @@ struct MachineState { CPUArchIdList *possible_cpus; CpuTopology smp; struct NVDIMMState *nvdimms_state; + struct CXLState *cxl_devices_state; struct NumaState *numa_state; }; =20 diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h index c7ca42930f..784b4f7a04 100644 --- a/include/hw/cxl/cxl.h +++ b/include/hw/cxl/cxl.h @@ -22,4 +22,8 @@ #define CXL_HOST_BASE 0xD0000000 #define CXL_WINDOW_MAX 10 =20 +typedef struct CXLState { + bool is_enabled; +} CXLState; + #endif --=20 2.30.0 From nobody Tue May 7 02:40:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1615505313; cv=none; d=zohomail.com; s=zohoarc; b=b/eJsz5SpfyD89Qs2Kye7G4JSfA8BkcBQciGX9SWrz8yRU107rTG62SekQmgGIlYFcG0EA7bSySXsX7KFc+JUtzTJSue0dpq/lihGahhRLhVfSnzqi1O6sc95l7x/1wtzp1L60Ai1GsHrFQZJeZvXHD6Ooyu/ttRv+iqdSc6BHA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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a="175871736" X-IronPort-AV: E=Sophos;i="5.81,241,1610438400"; d="scan'208";a="175871736" IronPort-SDR: teaSKXpLvFcQarF53R16lOalW9EtB027bxO6LzssNKNPFOuQQJO8O0XJ41Pf7Pzj9LqsVIcbsG 3tF3ugbpvS6w== X-IronPort-AV: E=Sophos;i="5.81,241,1610438400"; d="scan'208";a="404233888" From: Ben Widawsky To: qemu-devel@nongnu.org Subject: [RFC PATCH] hw/mem/cxl_type3: Go back to subregions Date: Thu, 11 Mar 2021 15:27:16 -0800 Message-Id: <20210311232716.3914084-1-ben.widawsky@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.20; envelope-from=ben.widawsky@intel.com; helo=mga02.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Igor Mammedov , Ben Widawsky , Chris Browy , "Michael S. Tsirkin" , Jonathan Cameron Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Each device allocates its memory (persistent only for now) out of a container memory that represents a "window" that would be defined by the host bridge. For example, a host bridge may claim all traffic from 0x0 - 0x4000; it might then also direct 0x1000-0x1fff to a specific CXL device. Change the memory region type claiming 0x1000-0x1fff from an alias, to a subregion. v1 and v2 of the patch series both used a subregion. There were two issues with this and so for v3, an alias was chosen mimicking nvdimm. The switch to alias left an issue in the implementation. There's logic that check to make sure two memory regions (ie. two devices under the same host bridge) couldn't collide. While hardware doesn't make this guarantee, it's nice for driver debug. There is no clean way to do that with an alias. More importantly, this change was inspired by implementing support for both volatile and persistent memory. In that case, you may have multiple devices which the BIOS is going to assign address ranges to. Since we are the BIOS in this case, having a way of finding used space in the memory window so that you can allocate the next chunk is easily accomplished here. With this, I have the following output from `info mtree` 0000004c00000000-0000004c1fffffff (prio 0, ram): cxl-mem1 0000004c00000000-0000004c0fffffff (prio 1, i/o): cxl_type3-memory And `info memory-devices` Memory device [cxl]: "cxl-pmem0" addr: 0x4c00000000 slot: 0 node: 0 size: 268435456 memdev: /objects/cxl-mem1 hotplugged: false hotpluggable: true This functionality has been tested with a WIP linux patch which amounts to this: reg =3D readl(cxlm->regs.hdm_decoder + CXL_HDM_DECODER_CAP_OFFSET); dev_err(dev, "decoder cap:\n" "\tcount: %lu\n", FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, reg)); writel(0x4c, cxlm->regs.hdm_decoder + CXL_HDM_DECODER0_BASE_HIGH_OFF= SET); writel(0, cxlm->regs.hdm_decoder + CXL_HDM_DECODER0_BASE_LOW_OFFSET); writel(0, cxlm->regs.hdm_decoder + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET= ); writel(256 << 20, cxlm->regs.hdm_decoder + CXL_HDM_DECODER0_SIZE_LOW= _OFFSET); writel(BIT(9), cxlm->regs.hdm_decoder + CXL_HDM_DECODER0_CTRL_OFFSE= T); tmp =3D ioremap_uc(0x4c00000000, 4096); writel(0x20, tmp); Cc: Jonathan Cameron Signed-off-by: Ben Widawsky --- hw/mem/cxl_type3.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index bf33ddb915..33991079a6 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -46,7 +46,9 @@ static void build_dvsecs(CXLType3Dev *ct3d) static void cxl_set_addr(CXLType3Dev *ct3d, hwaddr addr, Error **errp) { MemoryDeviceClass *mdc =3D MEMORY_DEVICE_GET_CLASS(ct3d); - mdc->set_addr(MEMORY_DEVICE(ct3d), addr, errp); + MemoryRegion *mr =3D host_memory_backend_get_memory(ct3d->hostmem); + + mdc->set_addr(MEMORY_DEVICE(ct3d), addr - mr->addr, errp); } =20 static void hdm_decoder_commit(CXLType3Dev *ct3d, int which) @@ -180,13 +182,13 @@ static void cxl_setup_memory(CXLType3Dev *ct3d, Error= **errp) =20 memory_region_set_nonvolatile(pmem, true); memory_region_set_enabled(pmem, false); - memory_region_init_alias(pmem, OBJECT(ct3d), "cxl_type3-memory", mr, 0, - ct3d->size); + memory_region_init(pmem, OBJECT(ct3d), "cxl_type3-memory", ct3d->size); + memory_region_add_subregion_overlap(mr, 0, pmem, 1); ct3d->cxl_dstate.pmem =3D pmem; =20 #ifdef SET_PMEM_PADDR /* This path will initialize the memory device as if BIOS had done it = */ - cxl_set_addr(ct3d, mr->addr + offset, errp); + cxl_set_addr(ct3d, offset, errp); memory_region_set_enabled(pmem, true); #endif } @@ -246,8 +248,11 @@ static uint64_t cxl_md_get_addr(const MemoryDeviceStat= e *md) CXLType3Dev *ct3d =3D CT3(md); MemoryRegion *pmem =3D ct3d->cxl_dstate.pmem; =20 - assert(pmem->alias); - return pmem->alias_offset; + if (pmem) { + return pmem->addr + pmem->container->addr; + } + + return 0; } =20 static void cxl_md_set_addr(MemoryDeviceState *md, uint64_t addr, Error **= errp) @@ -255,8 +260,6 @@ static void cxl_md_set_addr(MemoryDeviceState *md, uint= 64_t addr, Error **errp) CXLType3Dev *ct3d =3D CT3(md); MemoryRegion *pmem =3D ct3d->cxl_dstate.pmem; =20 - assert(pmem->alias); - memory_region_set_alias_offset(pmem, addr); memory_region_set_address(pmem, addr); } =20 --=20 2.30.2