From nobody Fri May 17 01:29:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1612192999; cv=none; d=zohomail.com; s=zohoarc; b=OLYLeRoOUYGf/15ctjh5LVDVyStOHur0sPde601UrjW1ktP7iqSrQJcG5FZrF76dzVO2UGtSjFu2TRmFbASRr0oty5+U1iC1cybnoAwSjgAYjbpsotJeTX48M+fb6fgIk8z33DnvwF5GYUv6LiUrsD/Lb7Cvdeda+0tqCbamhpU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612192999; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9foF8QuxCyCvsDXW0Shrq40+s4xKr7CQMLLqU2pg0fU=; b=FtHjd+sbpRL5BY/5uzF02L0h7LxAPicMt3gSgAKctTFp6gfhZFDjlbLtEjKHDJmj+B1fRlHHW4uE0n3KqWt7AL/JOtgiYE5rRqfSfFSccOvXhHftPk3U+UwBBSyQeTHBPnnSnvka0HB41SX78xt12wybGb99vxLlcMvsM6wM4vs= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612192999950518.0126911209396; Mon, 1 Feb 2021 07:23:19 -0800 (PST) Received: from localhost ([::1]:37362 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6b2s-0006Iw-N7 for importer@patchew.org; Mon, 01 Feb 2021 10:23:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36204) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6b02-0003IL-9F for qemu-devel@nongnu.org; Mon, 01 Feb 2021 10:20:24 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]:2083) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6azu-00032q-2Z for qemu-devel@nongnu.org; Mon, 01 Feb 2021 10:20:22 -0500 Received: from fraeml743-chm.china.huawei.com (unknown [172.18.147.200]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4DTs2c4nLjz67jbC; Mon, 1 Feb 2021 23:15:36 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml743-chm.china.huawei.com (10.206.15.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Mon, 1 Feb 2021 16:20:12 +0100 Received: from lhrphicprd00229.huawei.com (10.123.41.22) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Mon, 1 Feb 2021 15:20:11 +0000 From: Jonathan Cameron To: Subject: [RFC PATCH 1/4] include/standard-headers/linux/pci_regs: temp hack to add necessary DOE definitions. Date: Mon, 1 Feb 2021 23:16:26 +0800 Message-ID: <20210201151629.29656-2-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20210201151629.29656-1-Jonathan.Cameron@huawei.com> References: <20210201151629.29656-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.123.41.22] X-ClientProxiedBy: lhreml751-chm.china.huawei.com (10.201.108.201) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Ben Widawsky , "Michael S . Tsirkin" , Jonathan Cameron , Vishal Verma , f.fangjian@huawei.com, Chris Browy , f4bug@amsat.org, linuxarm@openeuler.org, jcm@redhat.com, Prashant V Agarwal , Igor Mammedov , Dan Williams Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Jonathan Cameron --- include/standard-headers/linux/pci_regs.h | 33 ++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-h= eaders/linux/pci_regs.h index e709ae8235..7e852d3dd0 100644 --- a/include/standard-headers/linux/pci_regs.h +++ b/include/standard-headers/linux/pci_regs.h @@ -730,7 +730,8 @@ #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ -#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT +#define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DOE =20 #define PCI_EXT_CAP_DSN_SIZEOF 12 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 @@ -1092,4 +1093,34 @@ #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 =20 +/* Data Object Exchange */ +#define PCI_DOE_CAP 0x04 +#define PCI_DOE_CAP_INT_SUPPORT 0x00000001 +#define PCI_DOE_CAP_INT_MSG_NUM 0x00000FFE + +#define PCI_DOE_CTRL 0x08 +#define PCI_DOE_CTRL_DOE_ABORT 0x00000001 +#define PCI_DOE_CTRL_DOE_INT_EN 0x00000002 +#define PCI_DOE_CTRL_DOE_GO 0x80000000 + +#define PCI_DOE_STATUS 0x0c +#define PCI_DOE_STATUS_DOE_BUSY 0x00000001 +#define PCI_DOE_STATUS_INT_STATUS 0x00000002 +#define PCI_DOE_STATUS_DOE_ERROR 0x00000004 +#define PCI_DOE_STATUS_DATA_OBJECT_READY 0x80000000 + +#define PCI_DOE_WRITE_MAILBOX 0x10 +#define PCI_DOE_READ_MAILBOX 0x14 + +/* Data Object Format DOE ECN 6.xx.1 */ +#define PCI_DATA_OBJ_DW0_VID 0x0000ffff +#define PCI_DATA_OBJ_DW0_TYPE 0x00ff0000 +#define PCI_DATA_OBJ_DW1_LEN 0x0003ffff + +/* DOE Discover Data Object */ +#define PCI_DOE_DIS_OBJ_TYPE 0x1 +#define PCI_DOE_DIS_REQ_D0_DW0_INDEX 0x000000ff +#define PCI_DOE_DIS_RSP_DO_DW0_VID 0x0000ffff +#define PCI_DOE_DIS_RSP_D0_DW0_PROT 0x00ff0000 +#define PCI_DOE_DIS_RSP_D0_DW0_NEXT_INDEX 0xff000000 #endif /* LINUX_PCI_REGS_H */ --=20 2.19.1 From nobody Fri May 17 01:29:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1612193107; cv=none; d=zohomail.com; s=zohoarc; b=diB3BwTwEUXroUzRBewXR1hENT/SOdhjaiTjV40PlN9phP7kMTFPxs+mOExzytOe4c0gzhnOR+sRhcMAF279VzDBl2LfqUbtHbV8idPQj22/2564Q2xOQNHgcK9SUF0y+RUuXLs9ZM5PAEObVYAPnRxxE3sfGHc2v2glVf5iHts= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612193107; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eD/jUFdm6ds3VyJ8iYZ1X3MKfhv5Te4fW4KNm3ueCGU=; b=QPTig7RN7FQ/qUa4zF9leSexfezKAMg56Gc0hVgJic3WiGSAYwFSXNT8/ddPqEkmj6vBpwjOK8SvSc/k3U8YnXlwmUngbOy01l/3II5mz3WYBUaI0m6zd7cHYH1LZhGySDEWESYB5lCxPRi1NBZDE8M8wx5E2ctd8iDVi2EB7V0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612193107396679.0476699820161; Mon, 1 Feb 2021 07:25:07 -0800 (PST) Received: from localhost ([::1]:44364 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6b4c-00010X-69 for importer@patchew.org; Mon, 01 Feb 2021 10:25:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36326) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6b0S-0003hI-I7 for qemu-devel@nongnu.org; Mon, 01 Feb 2021 10:20:48 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]:2084) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6b0P-0003JF-TX for qemu-devel@nongnu.org; Mon, 01 Feb 2021 10:20:48 -0500 Received: from fraeml742-chm.china.huawei.com (unknown [172.18.147.200]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4DTs4W6JZKz67jCc; Mon, 1 Feb 2021 23:17:15 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml742-chm.china.huawei.com (10.206.15.223) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Mon, 1 Feb 2021 16:20:43 +0100 Received: from lhrphicprd00229.huawei.com (10.123.41.22) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Mon, 1 Feb 2021 15:20:42 +0000 From: Jonathan Cameron To: Subject: [RFC PATCH 2/4] hw/pci/pcie_doe: Introduce utility functions for PCIe DOE Date: Mon, 1 Feb 2021 23:16:27 +0800 Message-ID: <20210201151629.29656-3-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20210201151629.29656-1-Jonathan.Cameron@huawei.com> References: <20210201151629.29656-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.123.41.22] X-ClientProxiedBy: lhreml751-chm.china.huawei.com (10.201.108.201) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Ben Widawsky , "Michael S . Tsirkin" , Jonathan Cameron , Vishal Verma , f.fangjian@huawei.com, Chris Browy , f4bug@amsat.org, linuxarm@openeuler.org, jcm@redhat.com, Prashant V Agarwal , Igor Mammedov , Dan Williams Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This implements the ECN to the PCI 5.0 specification available at https://members.pcisig.com/wg/PCI-SIG/document/14143 Does not currently support interrupts. Note that currently no attempt is made to clean up allocated memory. Signed-off-by: Jonathan Cameron --- hw/pci/meson.build | 2 +- hw/pci/pcie_doe.c | 257 +++++++++++++++++++++++++++++++++++++++ include/hw/pci/doe.h | 40 ++++++ include/hw/pci/pci_ids.h | 2 + 4 files changed, 300 insertions(+), 1 deletion(-) diff --git a/hw/pci/meson.build b/hw/pci/meson.build index 5c4bbac817..7336620ee3 100644 --- a/hw/pci/meson.build +++ b/hw/pci/meson.build @@ -11,7 +11,7 @@ pci_ss.add(files( # The functions in these modules can be used by devices too. Since we # allow plugging PCIe devices into PCI buses, include them even if # CONFIG_PCI_EXPRESS=3Dn. -pci_ss.add(files('pcie.c', 'pcie_aer.c')) +pci_ss.add(files('pcie.c', 'pcie_aer.c', 'pcie_doe.c')) softmmu_ss.add(when: 'CONFIG_PCI_EXPRESS', if_true: files('pcie_port.c', '= pcie_host.c')) softmmu_ss.add_all(when: 'CONFIG_PCI', if_true: pci_ss) =20 diff --git a/hw/pci/pcie_doe.c b/hw/pci/pcie_doe.c new file mode 100644 index 0000000000..8739c41280 --- /dev/null +++ b/hw/pci/pcie_doe.c @@ -0,0 +1,257 @@ +/* + * pcie_doe.c + * utility functions for pci express data object exchange introduced + * in PCI 5.0 Data Object Exchange (DOE) ECN + * + * Copyright (c) 2021 Jonathan Cameron + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qemu/error-report.h" +#include "hw/pci/pci.h" +#include "hw/pci/doe.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/range.h" +#include "qemu/rcu.h" +#include "sysemu/hostmem.h" + +struct doe_handler { + uint16_t vendor_id; + uint8_t object_type; + doe_msg_handler_t handler; + void *priv; +}; + +static void doe_set_ctl(PCIEDOE *doe, uint32_t val) +{ + /* Abort */ + if (val & PCI_DOE_CTRL_DOE_ABORT) { + doe->req_index =3D 0; + doe->rsp_index =3D 0; + doe->req_length =3D 0; + doe->error =3D false; + doe->data_object_ready =3D false; + } + + if (val & PCI_DOE_CTRL_DOE_GO) { + GList *l; + uint16_t vendor_id =3D doe->store[0] & PCI_DATA_OBJ_DW0_VID; + uint8_t object_type =3D (doe->store[0] & PCI_DATA_OBJ_DW0_TYPE) >> + ctz32(PCI_DATA_OBJ_DW0_TYPE); + if ((doe->req_index !=3D 3) || (doe->req_length !=3D 3)) { + /* + * Not entirely clear what should happen if req_length is corr= ect + * buf insufficient data has been received. + */ + doe->error =3D true; + return; + } + /* Discovery protocol - DOE ECN */ + if (vendor_id =3D=3D PCI_VENDOR_ID_PCI_SIG && + object_type =3D=3D PCI_DOE_DIS_OBJ_TYPE) { + uint8_t index =3D doe->store[2] & PCI_DOE_DIS_REQ_D0_DW0_INDEX; + doe->store[1] =3D 3; + if (index =3D=3D 0) { + /* First entry is this one, the discovery protocol itself = */ + uint8_t next; + + if (doe->cb_list) { + next =3D index + 1; + } else { + next =3D 0; + } + doe->store[2] =3D + (next << ctz32(PCI_DOE_DIS_RSP_D0_DW0_NEXT_INDEX)) | + (0 << ctz32(PCI_DOE_DIS_RSP_D0_DW0_PROT)) | + 0x0001; + } else { + /* Other entries based on register callbacks */ + uint8_t next; + struct doe_handler *h; + + h =3D g_list_nth_data(doe->cb_list, index - 1); + /* + * Off end of list, Table 7-x4 in DOE ECN - + * Vendor ID 0xFFFF if no more indices + */ + if (h =3D=3D NULL) { + doe->store[2] =3D 0xFFFF; + } else { + if (g_list_nth(doe->cb_list, index)) { + next =3D index + 1; + } else { + next =3D 0; + } + doe->store[2] =3D + (next << ctz32(PCI_DOE_DIS_RSP_D0_DW0_NEXT_INDEX))= | + (h->object_type << ctz32(PCI_DOE_DIS_RSP_D0_DW0_PR= OT)) | + h->vendor_id; + } + } + doe->data_object_ready =3D true; + doe->rsp_index =3D 0; + } else { + for (l =3D doe->cb_list; l !=3D NULL; l =3D l->next) { + struct doe_handler *h =3D l->data; + if (h->vendor_id =3D=3D vendor_id && + h->object_type =3D=3D object_type) { + int ret =3D h->handler(doe, h->vendor_id, h->object_ty= pe, + h->priv); + if (ret) { + /* + * No response so as per 6.xx.1 in DOE ECN + * "... within 1 second after the DOE Go bit was S= et + * in the DOE Control register, otherwise the DOE + * instance must Set the DOE Error bit in the DOE + * Status register.." + */ + doe->error =3D true; + break; + } + doe->data_object_ready =3D true; + doe->rsp_index =3D 0; + break; + } + } + /* Comamnd not handled */ + if (l =3D=3D NULL) { + doe->error =3D true; + } + } + /* Reset input index to allow for a new message */ + doe->req_index =3D 0; + } +} + +static void doe_set_write_mailbox(PCIEDOE *doe, uint32_t val) +{ + if (doe->req_index =3D=3D 1) { + if (val & 0x3FFFF) { + doe->req_length =3D val & PCI_DATA_OBJ_DW1_LEN; + } else { + doe->req_length =3D 1 << 18; + } + } + if (doe->req_length && doe->req_index =3D=3D doe->req_length) { + /* + * 6.xx.1 Data Objects + * If the DW transferred does not match the indicated Length + * for a data object, then the data object must be + * silently discarded + */ + return; + } + doe->store[doe->req_index] =3D val; + doe->req_index++; +} + +static uint32_t doe_get_read_mailbox(PCIEDOE *doe) +{ + uint32_t val; + + if (doe->rsp_index =3D=3D 0) { + doe->rsp_length =3D doe->store[1] & PCI_DATA_OBJ_DW1_LEN; + } + if (!doe->data_object_ready) { + /* Underflow of the Read Data Mailbox Mechanism */ + doe->error =3D true; + return 0; + } + + val =3D doe->store[doe->rsp_index]; + doe->rsp_index++; + if (doe->rsp_index =3D=3D doe->rsp_length) { + doe->rsp_index =3D -1; + doe->data_object_ready =3D false; + } + + return val; +} + +static uint32_t doe_get_status(PCIEDOE *doe) +{ + uint32_t val =3D 0; + + if (doe->busy) { + val |=3D PCI_DOE_STATUS_DOE_BUSY; + } + /* bit 1: interrupt not yet supported */ + if (doe->error) { + val |=3D PCI_DOE_STATUS_DOE_ERROR; + } + if (doe->data_object_ready) { + val |=3D PCI_DOE_STATUS_DATA_OBJECT_READY; + } + + return val; +} + +void doe_add_message_handler(PCIEDOE *doe, uint16_t vendor_id, + uint8_t object_type, + const doe_msg_handler_t handler, void *priv) +{ + struct doe_handler *h =3D g_malloc0(sizeof(*handler)); + + h->vendor_id =3D vendor_id; + h->object_type =3D object_type; + h->handler =3D handler; + h->priv =3D priv; + doe->cb_list =3D g_list_append(doe->cb_list, h); +} + +uint32_t pcie_doe_ecap(PCIEDOE *doe, PCIDevice *d, uint16_t offset) +{ + doe->doe_base =3D offset; + /* Length field is 18 bits and is in dwords */ + doe->store =3D g_malloc0((1 << 18) * sizeof(uint32_t)); + + pcie_add_capability(d, PCI_EXT_CAP_ID_DOE, 1, offset, 0x18); + offset +=3D 0x18; + + return offset; +} + +void pcie_doe_write(PCIEDOE *doe, uint32_t addr, uint32_t val, int len) +{ + if (len !=3D 4) { + return; + } + + switch (addr - doe->doe_base) { + case PCI_DOE_CTRL: + doe_set_ctl(doe, val); + break; + case PCI_DOE_WRITE_MAILBOX: + doe_set_write_mailbox(doe, val); + break; + } +} + +uint32_t pcie_doe_read(PCIEDOE *doe, uint32_t addr, int len, int *found) +{ + if (len !=3D 4) { + *found =3D 0; + return 0; + } + + *found =3D 1; + switch (addr - doe->doe_base) { + case PCI_DOE_CAP: + return 0; /* No interrupt support */ + case PCI_DOE_STATUS: + return doe_get_status(doe); + case PCI_DOE_READ_MAILBOX: + return doe_get_read_mailbox(doe); + default: + *found =3D 0; + return 0; + } +} + diff --git a/include/hw/pci/doe.h b/include/hw/pci/doe.h new file mode 100644 index 0000000000..364c866c53 --- /dev/null +++ b/include/hw/pci/doe.h @@ -0,0 +1,40 @@ +/* + * PCIE DOE emulation. + * + * Copyright (c) 2021 Jonathan Cameron + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef QEMU_PCIE_DOE_H_ +#define QEMU_PCIE_DOE_H_ +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/module.h" + +typedef struct pcie_doe { + uint32_t doe_base; + GList *cb_list; + int req_index; + int req_length; + int rsp_index; + int rsp_length; + bool data_object_ready; + bool error; + bool busy; + uint32_t *store; +} PCIEDOE; + +typedef int (*doe_msg_handler_t)(PCIEDOE *doe, uint16_t vendor_id, + uint8_t object_type, void *priv); + +uint32_t pcie_doe_ecap(PCIEDOE *doe, PCIDevice *d, uint16_t offset); +void doe_add_message_handler(PCIEDOE *doe, uint16_t vendor_id, + uint8_t object_type, + const doe_msg_handler_t handler, void *priv); +uint32_t pcie_doe_read(PCIEDOE *doe, uint32_t addr, int len, int *found); +void pcie_doe_write(PCIEDOE *doe, uint32_t addr, uint32_t val, int len); +#endif diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h index 76bf3ed590..636b2e8017 100644 --- a/include/hw/pci/pci_ids.h +++ b/include/hw/pci/pci_ids.h @@ -157,6 +157,8 @@ =20 /* Vendors and devices. Sort key: vendor first, device next. */ =20 +#define PCI_VENDOR_ID_PCI_SIG 0x0001 + #define PCI_VENDOR_ID_LSI_LOGIC 0x1000 #define PCI_DEVICE_ID_LSI_53C810 0x0001 #define PCI_DEVICE_ID_LSI_53C895A 0x0012 --=20 2.19.1 From nobody Fri May 17 01:29:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1612192998; cv=none; d=zohomail.com; s=zohoarc; b=XM+7Caf9dQMVQmUdMPY6f9ke4BeWHRnRne8PpjgQPEAb5HG5kF9r0YZwiA1whF8XbDDZyIijUA/OnjK2y9fZey0LJuVnqBQlZIExyWjKyeGxK4iXCQ0v59zCWt2JR31l3vQ3XM+v+H+wT1jhfw487hb0sJDXYP9vHhp03c0f2uI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612192998; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=B2/j2Z3kkdIVnYIxjD28YvbG0+WhAWuMUKDaqcXgxC4=; b=JICk8IrW5RmORpicb7qkMlfYi9tpiCod0+DTCch3LACOtHwfga/eavjatNZd1iYjZLE32yTGXassCa2tw2CMMy+6s11EAHxa1RSl5eQX4FHlhQZlmUlqA0U+JyLDqftIxRbhOaQRuB9aza4Luc2/Cb411RZb11U38MLVDI0cec0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612192998643763.2889402927548; Mon, 1 Feb 2021 07:23:18 -0800 (PST) Received: from localhost ([::1]:37278 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6b2r-0006Gi-FQ for importer@patchew.org; Mon, 01 Feb 2021 10:23:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36472) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6b11-0004SI-2O for qemu-devel@nongnu.org; Mon, 01 Feb 2021 10:21:23 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]:2085) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6b0x-0003WJ-Ok for qemu-devel@nongnu.org; Mon, 01 Feb 2021 10:21:22 -0500 Received: from fraeml740-chm.china.huawei.com (unknown [172.18.147.226]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4DTs3n6lVzz67flr; Mon, 1 Feb 2021 23:16:37 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml740-chm.china.huawei.com (10.206.15.221) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Mon, 1 Feb 2021 16:21:13 +0100 Received: from lhrphicprd00229.huawei.com (10.123.41.22) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Mon, 1 Feb 2021 15:21:13 +0000 From: Jonathan Cameron To: Subject: [RFC PATCH 3/4] hw/cxl/cxl-cdat: Initial CDAT implementation for use by CXL devices Date: Mon, 1 Feb 2021 23:16:28 +0800 Message-ID: <20210201151629.29656-4-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20210201151629.29656-1-Jonathan.Cameron@huawei.com> References: <20210201151629.29656-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.123.41.22] X-ClientProxiedBy: lhreml751-chm.china.huawei.com (10.201.108.201) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Ben Widawsky , "Michael S . Tsirkin" , Jonathan Cameron , Vishal Verma , f.fangjian@huawei.com, Chris Browy , f4bug@amsat.org, linuxarm@openeuler.org, jcm@redhat.com, Prashant V Agarwal , Igor Mammedov , Dan Williams Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" CDAT is an ACPI like format defined by the CXL consortium. It is available from https://www.uefi.org/node/4093 Here support for managing all the entires is introduced, along with an implementation of a callback for a DOE mailbox which may be used to read these values from CXL hardware by either firmware or an OS. Signed-off-by: Jonathan Cameron --- hw/cxl/cxl-cdat.c | 252 ++++++++++++++++++++++++++++++++++++++ hw/cxl/meson.build | 1 + include/hw/cxl/cxl_cdat.h | 101 +++++++++++++++ 3 files changed, 354 insertions(+) diff --git a/hw/cxl/cxl-cdat.c b/hw/cxl/cxl-cdat.c new file mode 100644 index 0000000000..6ed4c15cc0 --- /dev/null +++ b/hw/cxl/cxl-cdat.c @@ -0,0 +1,252 @@ +/* + * Support for CDAT entires as defined in + * Coherent Device Attribute Table (CDAT) Specification rev 1.02 + * Available from uefi.org. + * + * Copyright (c) 2021 Jonathan Cameron + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qemu/error-report.h" +#include "hw/mem/memory-device.h" +#include "hw/mem/pc-dimm.h" +#include "hw/pci/pci.h" +#include "hw/pci/doe.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/range.h" +#include "qemu/rcu.h" +#include "sysemu/hostmem.h" +#include "sysemu/numa.h" +#include "hw/cxl/cxl.h" + +void cdat_add_dsmas(CXLCDAT *cdat, uint8_t dsmad_handle, uint8_t flags, + uint64_t dpa_base, uint64_t dpa_length) +{ + struct cxl_cdat_dsmas *dsmas =3D g_malloc0(sizeof(*dsmas)); + dsmas->dsmad_handle =3D dsmad_handle; + dsmas->flags =3D flags; + dsmas->dpa_base =3D dpa_base; + dsmas->dpa_length =3D dpa_length; + cdat->dsmas_list =3D g_list_append(cdat->dsmas_list, dsmas); +} + +void cdat_add_dslbis(CXLCDAT *cdat, uint8_t handle, uint8_t flags, + uint8_t data_type, uint64_t base_unit, + uint16_t entry0, uint16_t entry1, uint16_t entry2) +{ + struct cxl_cdat_dslbis *dslbis =3D g_malloc0(sizeof(*dslbis)); + dslbis->handle =3D handle; + dslbis->flags =3D flags; + dslbis->data_type =3D data_type; + dslbis->entry_base_unit =3D base_unit; + dslbis->entries[0] =3D entry0; + dslbis->entries[1] =3D entry1; + dslbis->entries[2] =3D entry2; + cdat->dslbis_list =3D g_list_append(cdat->dslbis_list, dslbis); +} + +void cdat_add_dsmscis(CXLCDAT *cdat, uint8_t dsmas_handle, + uint64_t memory_sc_size, uint64_t cache_attrs) +{ + struct cxl_cdat_dsmscis *dsmscis =3D g_malloc(sizeof(*dsmscis)); + dsmscis->dsmas_handle =3D dsmas_handle; + dsmscis->memory_side_cache_size =3D memory_sc_size; + dsmscis->cache_attributes =3D cache_attrs; + cdat->dsmscis_list =3D g_list_append(cdat->dsmscis_list, dsmscis); +} + +void cdat_add_dsis(CXLCDAT *cdat, uint8_t flags, uint8_t handle) +{ + struct cxl_cdat_dsis *dsis =3D g_malloc(sizeof(*dsis)); + dsis->flags =3D flags; + dsis->handle =3D handle; + cdat->dsis_list =3D g_list_append(cdat->dsis_list, dsis); +} + +void cdat_add_dsemts(CXLCDAT *cdat, uint8_t dsmas_handle, + uint8_t efi_mem_type_attr, uint64_t dpa_offset, + uint64_t dpa_length) +{ + struct cxl_cdat_dsemts *dsemts =3D g_malloc(sizeof(*dsemts)); + dsemts->dsmas_handle =3D dsmas_handle; + dsemts->efi_mem_type_attr =3D efi_mem_type_attr; + dsemts->dpa_offset =3D dpa_offset; + dsemts->dpa_length =3D dpa_length; + cdat->dsemts_list =3D g_list_append(cdat->dsemts_list, dsemts); +} + +struct cxl_cdat_sslbis *cdat_add_sslbis(CXLCDAT *cdat, uint8_t num_entries, + uint8_t data_type, uint64_t base_u= nit) +{ + struct cxl_cdat_sslbis *sslbis =3D + g_malloc(sizeof(*sslbis) + num_entries * sizeof(sslbis->entries[0]= )); + sslbis->num_entries =3D num_entries; + sslbis->data_type =3D data_type; + sslbis->base_unit =3D base_unit; + cdat->sslbis_list =3D g_list_append(cdat->sslbis_list, sslbis); + return sslbis; +} + +int cdata_sslbis_set_entry(struct cxl_cdat_sslbis *sslbis, uint8_t index, + uint16_t portx, uint16_t porty, uint16_t val) +{ + struct cxl_cdat_sslbis_entry *entry; + if (index >=3D sslbis->num_entries) { + return -1; + } + entry =3D &sslbis->entries[index]; + entry->port_x_id =3D portx; + entry->port_y_id =3D porty; + entry->val =3D val; + return 0; +} + +int cxl_table_access(PCIEDOE *doe, uint16_t vendor_id, uint8_t object_type, + void *priv) +{ + uint8_t table_type; + int total_entries; + uint16_t entry_handle; + CXLCDAT *cdat =3D priv; + uint16_t next_entry; + + if (doe->req_length !=3D 3) { + /* optional error for unexpected command length */ + return -1; + } + + if ((doe->store[2] & CXL_DOE_TABLE_ACCESS_DW2_RCODE) !=3D 0) { + /* + * Only table access code currently supported. + * Error indication is lack of Data Object Ready + */ + return -1; + } + + table_type =3D (doe->store[2] & CXL_DOE_TABLE_ACCESS_DW2_TYPE) >> + ctz32(CXL_DOE_TABLE_ACCESS_DW2_TYPE); + if (table_type !=3D 0) { + /* Unsuported table ID so just don't set Data Object Ready */ + return -1; + } + entry_handle =3D (doe->store[2] & CXL_DOE_TABLE_ACCESS_DW2_ENTRYHANDLE= ) >> + ctz32(CXL_DOE_TABLE_ACCESS_DW2_ENTRYHANDLE); + + /* Assume entry handle =3D=3D CDAT structure index */ + total_entries =3D g_list_length(cdat->dsmas_list) + + g_list_length(cdat->dslbis_list) + + g_list_length(cdat->dsmscis_list) + + g_list_length(cdat->dsis_list) + + g_list_length(cdat->dsemts_list) + + g_list_length(cdat->sslbis_list); + if (entry_handle + 1 =3D=3D total_entries) { + next_entry =3D 0xFFFF; + } else { + next_entry =3D entry_handle + 1; + } + + if (entry_handle < g_list_length(cdat->dsmas_list)) { + const int dsmas_len =3D 24; + struct cxl_cdat_dsmas *dsmas =3D + g_list_nth_data(cdat->dsmas_list, entry_handle); + + doe->store[1] =3D 3 + dsmas_len / sizeof(uint32_t); + doe->store[2] =3D next_entry << 16; + doe->store[3] =3D (dsmas_len << 16) | CXL_CDAT_DSMAS_TYPE; + + /* cxl version of proximity domain */ + doe->store[4] =3D dsmas->dsmad_handle; + /* flags in 2nd byte of [4] (bit 2 is non volatile) */ + doe->store[4] |=3D (dsmas->flags << 8); + doe->store[5] =3D dsmas->dpa_base & 0xFFFFFFFF; + doe->store[6] =3D (dsmas->dpa_base >> 32) & 0xFFFFFFFF; + doe->store[7] =3D dsmas->dpa_length & 0xFFFFFFFF; + doe->store[8] =3D (dsmas->dpa_length >> 32) & 0xFFFFFFFF; + return 0; + } + entry_handle -=3D g_list_length(cdat->dsmas_list); + if (entry_handle < g_list_length(cdat->dslbis_list)) { + const int dslbis_len =3D 24; + struct cxl_cdat_dslbis *dslbis =3D + g_list_nth_data(cdat->dslbis_list, entry_handle); + + doe->store[1] =3D 3 + dslbis_len / sizeof(uint32_t); + doe->store[2] =3D next_entry << 16; + doe->store[3] =3D (dslbis_len << 16) | CXL_CDAT_DSLBIS_TYPE; + + doe->store[4] =3D (dslbis->data_type << 24) | (dslbis->flags << 8)= | + dslbis->handle; + doe->store[5] =3D dslbis->entry_base_unit & 0xFFFFFFFF; + doe->store[6] =3D (dslbis->entry_base_unit >> 32) & 0xFFFFFFFF; + doe->store[7] =3D (dslbis->entries[1] << 16) | dslbis->entries[0]; + doe->store[8] =3D dslbis->entries[2]; + return 0; + } + entry_handle -=3D g_list_length(cdat->dslbis_list); + if (entry_handle < g_list_length(cdat->dsmscis_list)) { + const int dsmscis_len =3D 20; + struct cxl_cdat_dsmscis *dsmscis =3D + g_list_nth_data(cdat->dsmscis_list, entry_handle); + + doe->store[1] =3D 3 + dsmscis_len / sizeof(uint32_t); + doe->store[2] =3D next_entry << 16; + doe->store[3] =3D (dsmscis_len << 16) | CXL_CDAT_DSMSCIS_TYPE; + doe->store[4] =3D dsmscis->dsmas_handle; + doe->store[5] =3D dsmscis->memory_side_cache_size & 0xffffffff; + doe->store[6] =3D (dsmscis->memory_side_cache_size >> 32) & 0xffff= ffff; + doe->store[7] =3D dsmscis->cache_attributes; + } + entry_handle -=3D g_list_length(cdat->dsmscis_list); + if (entry_handle < g_list_length(cdat->dsis_list)) { + const int dsis_len =3D 8; + struct cxl_cdat_dsis *dsis =3D + g_list_nth_data(cdat->dsis_list, entry_handle); + + doe->store[1] =3D 3 + dsis_len / sizeof(uint32_t); + doe->store[2] =3D next_entry << 16; + doe->store[3] =3D (dsis_len << 16) | CXL_CDAT_DSMSCIS_TYPE; + doe->store[4] =3D (dsis->handle << 8) | dsis->flags; + } + entry_handle -=3D g_list_length(cdat->dsis_list); + if (entry_handle < g_list_length(cdat->dsemts_list)) { + const int dsemts_len =3D 24; + struct cxl_cdat_dsemts *dsemts =3D + g_list_nth_data(cdat->dsemts_list, entry_handle); + + doe->store[1] =3D 3 + dsemts_len / sizeof(uint32_t); + doe->store[2] =3D next_entry << 16; + doe->store[3] =3D (dsemts_len << 16) | CXL_CDAT_DSEMTS_TYPE; + doe->store[4] =3D (dsemts->efi_mem_type_attr << 8) | dsemts->dsmas= _handle; + doe->store[5] =3D dsemts->dpa_offset & 0xffffffff; + doe->store[6] =3D (dsemts->dpa_offset >> 32) & 0xffffffff; + doe->store[7] =3D dsemts->dpa_length & 0xffffffff; + doe->store[8] =3D (dsemts->dpa_length >> 32) & 0xffffffff; + } + entry_handle -=3D g_list_length(cdat->dsemts_list); + if (entry_handle < g_list_length(cdat->sslbis_list)) { + struct cxl_cdat_sslbis *sslbis =3D + g_list_nth_data(cdat->sslbis_list, entry_handle); + int sslbis_len =3D 16 + 8 * sslbis->num_entries; + int i; + + doe->store[1] =3D 3 + sslbis_len / sizeof(uint32_t); + doe->store[2] =3D next_entry << 16; + doe->store[3] =3D (sslbis_len << 16) | CXL_CDAT_SSLBIS_TYPE; + doe->store[4] =3D sslbis->data_type; + doe->store[5] =3D sslbis->base_unit & 0xffffffff; + doe->store[6] =3D (sslbis->base_unit >> 32) & 0xffffffff; + for (i =3D 0; i < sslbis->num_entries; i++) { + doe->store[7 + i * 2] =3D (sslbis->entries[i].port_y_id << 8) | + sslbis->entries[i].port_x_id; + doe->store[7 + i * 2 + 1] =3D sslbis->entries[i].val; + } + } + + return -1; +} diff --git a/hw/cxl/meson.build b/hw/cxl/meson.build index 0eca715d10..9e2e5f4094 100644 --- a/hw/cxl/meson.build +++ b/hw/cxl/meson.build @@ -2,4 +2,5 @@ softmmu_ss.add(when: 'CONFIG_CXL', if_true: files( 'cxl-component-utils.c', 'cxl-device-utils.c', 'cxl-mailbox-utils.c', + 'cxl-cdat.c', )) diff --git a/include/hw/cxl/cxl_cdat.h b/include/hw/cxl/cxl_cdat.h new file mode 100644 index 0000000000..d0226c463c --- /dev/null +++ b/include/hw/cxl/cxl_cdat.h @@ -0,0 +1,101 @@ +/* + * Support for CDAT entires as defined in + * Coherent Device Attribute Table (CDAT) Specification rev 1.02 + * Available from uefi.org. + * + * Copyright (c) 2021 Jonathan Cameron + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ +#ifndef QEMU_CXL_CDAT_H +#define QEMU_CXL_CDAT_H +#include "hw/pci/doe.h" +/* DW2 is common to the request and response */ +#define CXL_DOE_TABLE_ACCESS_DW2_RCODE 0x000000ff +#define CXL_DOE_TABLE_ACCESS_DW2_TYPE 0x0000ff00 +#define CXL_DOE_TABLE_ACCESS_DW2_ENTRYHANDLE 0xffff0000 + +#define CXL_CDAT_DSMAS_TYPE 0 +#define CXL_CDAT_DSLBIS_TYPE 1 +#define CXL_CDAT_DSMSCIS_TYPE 2 +#define CXL_CDAT_DSIS_TYPE 3 +#define CXL_CDAT_DSEMTS_TYPE 4 +#define CXL_CDAT_SSLBIS_TYPE 5 + +struct cxl_cdat_dsmas { + uint8_t dsmad_handle; + uint8_t flags; +#define CDAT_DSMAS_FLAG_NV (1 << 2) + uint64_t dpa_base; + uint64_t dpa_length; +}; + +struct cxl_cdat_dslbis { + uint8_t handle; + uint8_t flags; + uint8_t data_type; + uint64_t entry_base_unit; + uint16_t entries[3]; /* 6 bytes */ +}; + +struct cxl_cdat_dsmscis { + uint8_t dsmas_handle; + uint64_t memory_side_cache_size; + uint32_t cache_attributes; +}; + +struct cxl_cdat_dsis { + uint8_t flags; +#define CDAT_DSIS_MEMORY_ATTACHED 0x01 + uint8_t handle; +}; + +struct cxl_cdat_dsemts { + uint8_t dsmas_handle; + uint8_t efi_mem_type_attr; + uint64_t dpa_offset; + uint64_t dpa_length; +}; + +struct cxl_cdat_sslbis_entry { + uint16_t port_x_id; + uint16_t port_y_id; + uint16_t val; +}; + +struct cxl_cdat_sslbis { + uint8_t num_entries; /* needed to compute length */ + uint8_t data_type; + uint64_t base_unit; + struct cxl_cdat_sslbis_entry entries[]; +}; + +typedef struct cxl_cdat { + GList *dsmas_list; + GList *dslbis_list; + GList *dsmscis_list; + GList *dsis_list; + GList *dsemts_list; + GList *sslbis_list; +} CXLCDAT; + +void cdat_add_dsmas(CXLCDAT *cdat, uint8_t dsmad_handle, uint8_t flags, + uint64_t dpa_base, uint64_t dpa_length); +void cdat_add_dslbis(CXLCDAT *cdat, uint8_t handle, uint8_t flags, + uint8_t data_type, uint64_t base_unit, + uint16_t entry0, uint16_t entry1, uint16_t entry2); +void cdat_add_dsmscis(CXLCDAT *cdat, uint8_t dsmas_handle, + uint64_t memory_sc_size, uint64_t cache_attrs); +void cdat_add_dsis(CXLCDAT *cdat, uint8_t flags, uint8_t handle); +void cdat_add_dsemts(CXLCDAT *cdat, uint8_t dsmas_handle, + uint8_t efi_mem_type_attr, uint64_t dpa_offset, + uint64_t dpa_length); +struct cxl_cdat_sslbis *cdat_add_sslbis(CXLCDAT *cdat, uint8_t num_entries, + uint8_t data_type, uint64_t base_u= nit); +int cdata_sslbis_set_entry(struct cxl_cdat_sslbis *sslbis, uint8_t index, + uint16_t portx, uint16_t pory, uint16_t val); + +int cxl_table_access(PCIEDOE *doe, uint16_t vendor_id, uint8_t object_type, + void *priv); +#endif --=20 2.19.1 From nobody Fri May 17 01:29:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 1 Feb 2021 16:21:43 +0100 Received: from lhrphicprd00229.huawei.com (10.123.41.22) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Mon, 1 Feb 2021 15:21:43 +0000 From: Jonathan Cameron To: Subject: [RFC PATCH 4/4] hw/mem/cxl_type3: Enabled DOE mailbox for access to CDAT Date: Mon, 1 Feb 2021 23:16:29 +0800 Message-ID: <20210201151629.29656-5-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20210201151629.29656-1-Jonathan.Cameron@huawei.com> References: <20210201151629.29656-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.123.41.22] X-ClientProxiedBy: lhreml751-chm.china.huawei.com (10.201.108.201) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Tsirkin" , Jonathan Cameron , Vishal Verma , f.fangjian@huawei.com, Chris Browy , f4bug@amsat.org, linuxarm@openeuler.org, jcm@redhat.com, Prashant V Agarwal , Igor Mammedov , Dan Williams Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This enables basic read back of CDAT entries via a DOE mailbox in the devices PCI config space. Note that for now a few possible entries are provided that don't make a lot of sense for current instances of this device. It will need to be made somewhat dynamic and possibly require additional command line parameters. Signed-off-by: Jonathan Cameron --- hw/mem/cxl_type3.c | 49 ++++++++++++++++++++++++++++++++++++++++++-- include/hw/cxl/cxl.h | 1 + 2 files changed, 48 insertions(+), 2 deletions(-) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index dee5a8884b..3449f02090 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -4,6 +4,7 @@ #include "hw/mem/memory-device.h" #include "hw/mem/pc-dimm.h" #include "hw/pci/pci.h" +#include "hw/pci/doe.h" #include "hw/qdev-properties.h" #include "qapi/error.h" #include "qemu/log.h" @@ -11,6 +12,7 @@ #include "qemu/range.h" #include "qemu/rcu.h" #include "sysemu/hostmem.h" +#include "sysemu/numa.h" #include "hw/cxl/cxl.h" =20 typedef struct cxl_type3_dev { @@ -21,6 +23,9 @@ typedef struct cxl_type3_dev { uint64_t size; HostMemoryBackend *hostmem; =20 + PCIEDOE doe; + CXLCDAT cdat; + /* State */ CXLComponentState cxl_cstate; CXLDeviceState cxl_dstate; @@ -28,7 +33,7 @@ typedef struct cxl_type3_dev { =20 #define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV) =20 -static void build_dvsecs(CXLType3Dev *ct3d) +static int build_dvsecs(CXLType3Dev *ct3d) { CXLComponentState *cxl_cstate =3D &ct3d->cxl_cstate; uint8_t *dvsec; @@ -55,6 +60,7 @@ static void build_dvsecs(CXLType3Dev *ct3d) }; cxl_component_create_dvsec(cxl_cstate, REG_LOC_DVSEC_LENGTH, REG_LOC_D= VSEC, REG_LOC_DVSEC_REVID, dvsec); + return cxl_cstate->dvsec_offset; } =20 static void hdm_decoder_commit(CXLType3Dev *ct3d, int which) @@ -201,6 +207,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **err= p) ComponentRegisters *regs =3D &cxl_cstate->crb; MemoryRegion *mr =3D ®s->component_registers; uint8_t *pci_conf =3D pci_dev->config; + int offset; =20 if (!ct3d->cxl_dstate.pmem) { cxl_setup_memory(ct3d, errp); @@ -213,7 +220,21 @@ static void ct3_realize(PCIDevice *pci_dev, Error **er= rp) cxl_cstate->dvsec_offset =3D 0x100; =20 ct3d->cxl_cstate.pdev =3D pci_dev; - build_dvsecs(ct3d); + offset =3D build_dvsecs(ct3d); + + /* Build DOE - no interrupt for now */ + offset =3D pcie_doe_ecap(&ct3d->doe, pci_dev, offset); + doe_add_message_handler(&ct3d->doe, 0x1e98, 0x2, &cxl_table_access, + &ct3d->cdat); + + /* Store entires of CDAT for read back from DOE */ + cdat_add_dsmas(&ct3d->cdat, 0, CDAT_DSMAS_FLAG_NV, 0x3345000000, + 0x0001000000); + cdat_add_dsmas(&ct3d->cdat, 1, 0, 0x33460000000, 0x00010000000); + cdat_add_dslbis(&ct3d->cdat, 0, HMAT_LB_MEM_MEMORY, + (uint8_t)HMAT_LB_DATA_ACCESS_LATENCY, + 1000, /* microsecs */ + 90, 0, 0); =20 #ifndef SET_PMEM_PADDR regs->special_ops =3D g_new0(MemoryRegionOps, 1); @@ -287,6 +308,28 @@ static void pc_dimm_md_fill_device_info(const MemoryDe= viceState *md, info->type =3D MEMORY_DEVICE_INFO_KIND_CXL; } =20 +static void ct3d_config_write(PCIDevice *pci_dev, uint32_t addr, uint32_t = val, int len) +{ + CXLType3Dev *ct3d =3D CT3(pci_dev); + + pci_default_write_config(pci_dev, addr, val, len); + pcie_doe_write(&ct3d->doe, addr, val, len); + +} + +static uint32_t ct3d_config_read(PCIDevice *pci_dev, uint32_t addr, int le= n) +{ + CXLType3Dev *ct3d =3D CT3(pci_dev); + int found =3D 0; + uint32_t val; + + val =3D pcie_doe_read(&ct3d->doe, addr, len, &found); + if (found) { + return val; + } + return pci_default_read_config(pci_dev, addr, len); +} + static void ct3_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -298,6 +341,8 @@ static void ct3_class_init(ObjectClass *oc, void *data) pc->vendor_id =3D PCI_VENDOR_ID_INTEL; pc->device_id =3D 0xd93; /* LVF for now */ pc->revision =3D 1; + pc->config_write =3D ct3d_config_write; + pc->config_read =3D ct3d_config_read; =20 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->desc =3D "CXL PMEM Device (Type 3)"; diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h index 6961e47076..ec3b4d7398 100644 --- a/include/hw/cxl/cxl.h +++ b/include/hw/cxl/cxl.h @@ -13,6 +13,7 @@ #include "cxl_pci.h" #include "cxl_component.h" #include "cxl_device.h" +#include "cxl_cdat.h" =20 #define COMPONENT_REG_BAR_IDX 0 #define DEVICE_REG_BAR_IDX 2 --=20 2.19.1