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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id b13sm22561953wrt.31.2021.01.31.08.44.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 08:44:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LWcS/B5Wc5Bm+4irRgdKOqKVWu12IJGBF6ND+Mb33fs=; b=anoCizJ7OAjnCNZnGdVmDBAHuktDHRQIsqoI5jgJYZn0zabHpm+jNdkCc+vqnzx63K 9Ue3/lGyWMfxiEL+PbGytv660/CWvKx0LtvBq6SHX4el2j5FHGltHuwJ3nXA8JOTYy8Y iXZx4FrY+V8E62QX1y0RXHieCv8z5Zseev1NXebkXSgdUQN/FPNrg1cR6Q4VXnF9gzyV HQwP4YXE9tKiVKXaYoXs7q352dgP12TfcJ5EujAmVbHflq8m71fk9M+lvZLlSWZyvTnW HatxuF37Yb/ik2lUQO153PgGoWYpKWOiQ9jGtF+uecCTryM5nYTdMtlPD/IDQ5KjlCuY tvQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=LWcS/B5Wc5Bm+4irRgdKOqKVWu12IJGBF6ND+Mb33fs=; b=H9hU1BouX/6u24gEXsyY1wWEUd4lgb0aGcVcNLhWrMvTUgq4gOz7jh1QeknkFfXAm0 6Q+KT0AcmqAPp7uUSB4AIYXBbq5EiiiF6uVrEj1riurUzEhX8xUXNLtfsM/IO8I5G3zO o/9lBSN6rz8pWhSjk+yuzAdlUW7tysXYUaoC/Yj80m8pI0I7ValQHrjI8+fF4t4Cs18f bvqHkwW1cU64EAKOx2LoVY4rE7uWkfkAkpVkERJDEkoy6Reuy0Q6A/Y0LsApfox3/79t 6B55GysIrXDoIGArJWJaegy//gyn3e5cwTxt3hTTQu5mEHYUy8KESWCelcddGq18C07C ChwA== X-Gm-Message-State: AOAM531EBIRp2zpM+FucCvUybyilwUw3cCLQI+yqh3h/3N9ODh2fqI8/ lsFvGzeX4Wtof+uaQCf0hpEKMvG+djo= X-Google-Smtp-Source: ABdhPJxYIw/qvvO3O2JOAKYBup7Fp378tFGnJbB6mqrew5n+HG+MMMbyz42p5+bVyP5zlgZbtYsqgg== X-Received: by 2002:a1c:7211:: with SMTP id n17mr3899005wmc.102.1612111455278; Sun, 31 Jan 2021 08:44:15 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 1/5] hw/arm: Use Kconfig 'default y' syntax instead of default-configs Date: Sun, 31 Jan 2021 17:44:02 +0100 Message-Id: <20210131164406.349825-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131164406.349825-1-f4bug@amsat.org> References: <20210131164406.349825-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Machines can be automatically selected using the Kconfig 'default y' syntax. This change allow deselecting these machines without having to modify default-configs/ files. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- default-configs/devices/aarch64-softmmu.mak | 3 --- default-configs/devices/arm-softmmu.mak | 2 -- hw/arm/Kconfig | 4 ++++ 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/default-configs/devices/aarch64-softmmu.mak b/default-configs/= devices/aarch64-softmmu.mak index a4202f56817..a94c7786919 100644 --- a/default-configs/devices/aarch64-softmmu.mak +++ b/default-configs/devices/aarch64-softmmu.mak @@ -2,6 +2,3 @@ =20 # We support all the 32 bit boards so need all their config include arm-softmmu.mak - -CONFIG_XLNX_VERSAL=3Dy -CONFIG_SBSA_REF=3Dy diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devi= ces/arm-softmmu.mak index 0fc80d7d6df..7d55c156bab 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -3,14 +3,12 @@ # CONFIG_PCI_DEVICES=3Dn # CONFIG_TEST_DEVICES=3Dn =20 -CONFIG_ARM_VIRT=3Dy CONFIG_CUBIEBOARD=3Dy CONFIG_EXYNOS4=3Dy CONFIG_REALVIEW=3Dy CONFIG_VEXPRESS=3Dy CONFIG_ZYNQ=3Dy CONFIG_NPCM7XX=3Dy -CONFIG_RASPI=3Dy CONFIG_SABRELITE=3Dy CONFIG_FSL_IMX7=3Dy CONFIG_FSL_IMX6UL=3Dy diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 768830cc28c..043710be3df 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -1,5 +1,6 @@ config ARM_VIRT bool + default y if ARM imply PCI_DEVICES imply TEST_DEVICES imply VFIO_AMD_XGBE @@ -224,6 +225,7 @@ config REALVIEW =20 config SBSA_REF bool + default y if AARCH64 imply PCI_DEVICES select AHCI select ARM_SMMUV3 @@ -341,6 +343,7 @@ config ALLWINNER_H3 =20 config RASPI bool + default y if ARM select FRAMEBUFFER select PL011 # UART select SDHCI @@ -382,6 +385,7 @@ config XLNX_ZYNQMP_ARM =20 config XLNX_VERSAL bool + default y if AARCH64 select ARM_GIC select PL011 select CADENCE --=20 2.26.2 From nobody Fri May 17 00:15:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) client-ip=209.85.221.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1612111462; cv=none; d=zohomail.com; s=zohoarc; b=letfzHrbOCNKDdXOk/4wEPpOBJp4TfSZ4suHVI9P15wtKSBk27/hgQ4v9pajT0TVguUFeHWKVmRKvJhIVQwGzZQO0/J8MLijYjo0wUxRrrxdZLVHQXLPf4a24RLEy7WIPXW0+LiJwnMzNmCF7u+fqHxFar/341vla5GGT0gsVNI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612111462; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ti3pGdZyEpwOiFw7/yoi3CPSUbET3rJXN1FI6GYYqTs=; b=NaFGfeZBzMLSL7dfPjsvHfteqKe2kwnPqMkUeZOgiDU9zlJggKXKoWXejB0g9WIDl6U9/HHVxnwUbT+G3m4CZMcJ6FgNjsOeJfGaWJj13BjEWfYivkkc4hX5RipxMDqTg5CFSc1hLn5DuQnHgekTwIebzwNFCKW1OmVT5Aitz1U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) by mx.zohomail.com with SMTPS id 1612111462378314.87120570444233; Sun, 31 Jan 2021 08:44:22 -0800 (PST) Received: by mail-wr1-f54.google.com with SMTP id z6so13961021wrq.10 for ; Sun, 31 Jan 2021 08:44:21 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id m184sm19779832wmf.12.2021.01.31.08.44.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 08:44:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ti3pGdZyEpwOiFw7/yoi3CPSUbET3rJXN1FI6GYYqTs=; b=WJZAC5oI/+0J1i4hjINE/PpdCPxgSq7PhS84z14HABHVkvXxR3dyxfxgnhG9k1VCic JOXkt/OvHylX/FFFtyd0WuN8m2gH+o0oaaqYP+TsUAXmujpFrnRf9V7KMKf2I7GE+tHD b5v3QIuxJEGs3lGQq7J1Vio0QlDrLgbr3foiv8c3KRrrZtJS80I22PhO6Qp1fJ3UmmQx fJEn4LithI/Mgz5y7kjyVQmvgaYk8yuCBOI2WjcjjLBpMryHfONwBK2auaZG1l3XkvtM 7sKPUJIYiRwuMkE+jGwI8cTwamVxs6EGugcyKEMgHb++Lz4l7VTxW50VCyd8MvLVZfqh MGig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Ti3pGdZyEpwOiFw7/yoi3CPSUbET3rJXN1FI6GYYqTs=; b=CBrrTQ4rGGlkvmJkKbE3I0O0rHKgGCnnnH400MvEBJ+k1zw1QLhF6tua3Wam4O0Sn2 ASXnCBQhQNC0CAMghTQtfxxs8OCu8Z+4IffYWacMzOfMoFPVyD79RzBAqmPIdCAPIibg dgG//Um3Fbw52+WTomU4NTDqjiXEPo1BHkB4bNhvmdjJM+HBauS8MQ6emd0gO1LICfTQ 3tTAuMOLgnimuvs3u4rvGZP9CoSjA4WKrncLgEnFhpETUYD7xYoJlNm32A3v29UOe9+x pAxfoCgNvesGnuZ+wKwPzDWU1+EnhTbe96Gc/gHZ620/4gbRSKNHKXPvS+NlxVRDIrry KHBQ== X-Gm-Message-State: AOAM532uu36jVFU0eh/mWjiWQ+kokc5P0mzQilxkBUqTElaUZJMoFcbi K1VVa9wK2pIsUfkbAJHh+XY= X-Google-Smtp-Source: ABdhPJyiPKUqMKiYoPKOERdZKupUQY1NbrLiW0EKYwuuOeb8WmWIw8PZQzp6KCcCGrvM0TsBOD28YQ== X-Received: by 2002:a05:6000:104:: with SMTP id o4mr14080822wrx.419.1612111460654; Sun, 31 Jan 2021 08:44:20 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/5] hw/arm: Restrict ARMv7 A-profile cpus to TCG accel Date: Sun, 31 Jan 2021 17:44:03 +0100 Message-Id: <20210131164406.349825-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131164406.349825-1-f4bug@amsat.org> References: <20210131164406.349825-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) KVM requires the target cpu to be at least ARMv8 architecture (support on ARMv7 has been dropped in commit 82bf7ae84ce: "target/arm: Remove KVM support for 32-bit Arm hosts"). The following machines are no more built when TCG is disabled: - cubieboard cubietech cubieboard (Cortex-A8) - mcimx6ul-evk Freescale i.MX6UL Evaluation Kit (Cortex A7) - mcimx7d-sabre Freescale i.MX7 DUAL SABRE (Cortex A7) - npcm750-evb Nuvoton NPCM750 Evaluation Board (Cortex A9) - nuri Samsung NURI board (Exynos4210) - orangepi-pc Orange Pi PC (Cortex-A7) - quanta-gsj Quanta GSJ (Cortex A9) - realview-pb-a8 ARM RealView Platform Baseboard for Cortex-A8 - realview-pbx-a9 ARM RealView Platform Baseboard Explore for Cortex= -A9 - sabrelite Freescale i.MX6 Quad SABRE Lite Board (Cortex A9) - smdkc210 Samsung SMDKC210 board (Exynos4210) - vexpress-a15 ARM Versatile Express for Cortex-A15 - vexpress-a9 ARM Versatile Express for Cortex-A9 - xilinx-zynq-a9 Xilinx Zynq Platform Baseboard for Cortex-A9 Reported-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- default-configs/devices/arm-softmmu.mak | 10 ---------- hw/arm/Kconfig | 11 +++++++++++ 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devi= ces/arm-softmmu.mak index 7d55c156bab..1ffa3dbe4bf 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -3,13 +3,3 @@ # CONFIG_PCI_DEVICES=3Dn # CONFIG_TEST_DEVICES=3Dn =20 -CONFIG_CUBIEBOARD=3Dy -CONFIG_EXYNOS4=3Dy -CONFIG_REALVIEW=3Dy -CONFIG_VEXPRESS=3Dy -CONFIG_ZYNQ=3Dy -CONFIG_NPCM7XX=3Dy -CONFIG_SABRELITE=3Dy -CONFIG_FSL_IMX7=3Dy -CONFIG_FSL_IMX6UL=3Dy -CONFIG_ALLWINNER_H3=3Dy diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 043710be3df..263f22a80c1 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -39,6 +39,7 @@ config CHEETAH =20 config CUBIEBOARD bool + default y if TCG && ARM select ALLWINNER_A10 =20 config DIGIC @@ -50,6 +51,7 @@ config DIGIC =20 config EXYNOS4 bool + default y if TCG && ARM select A9MPCORE select I2C select LAN9118 @@ -198,6 +200,7 @@ config Z2 =20 config REALVIEW bool + default y if TCG && ARM imply PCI_DEVICES imply PCI_TESTDEV select SMC91C111 @@ -241,6 +244,7 @@ config SBSA_REF =20 config SABRELITE bool + default y if TCG && ARM select FSL_IMX6 select SSI_M25P80 =20 @@ -292,6 +296,7 @@ config VERSATILE =20 config VEXPRESS bool + default y if TCG && ARM select A9MPCORE select A15MPCORE select ARM_MPTIMER @@ -307,6 +312,7 @@ config VEXPRESS =20 config ZYNQ bool + default y if TCG && ARM select A9MPCORE select CADENCE # UART select PFLASH_CFI02 @@ -331,6 +337,7 @@ config ALLWINNER_A10 =20 config ALLWINNER_H3 bool + default y if TCG && ARM select ALLWINNER_A10_PIT select ALLWINNER_SUN8I_EMAC select SERIAL @@ -395,6 +402,7 @@ config XLNX_VERSAL =20 config NPCM7XX bool + default y if TCG && ARM select A9MPCORE select ARM_GIC select PL310 # cache controller @@ -424,6 +432,7 @@ config FSL_IMX31 =20 config FSL_IMX6 bool + default y if TCG && ARM select A9MPCORE select IMX select IMX_FEC @@ -467,6 +476,7 @@ config MPS2 =20 config FSL_IMX7 bool + default y if TCG && ARM imply PCI_DEVICES imply TEST_DEVICES select A15MPCORE @@ -484,6 +494,7 @@ config ARM_SMMUV3 =20 config FSL_IMX6UL bool + default y if TCG && ARM select A15MPCORE select IMX select IMX_FEC --=20 2.26.2 From nobody Fri May 17 00:15:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1612111469; cv=none; d=zohomail.com; s=zohoarc; b=cYkYXQZ0oLtdC0/0GGq1ri7vAPNBzMMDTgxlCW5vdpJPeb2AA14hxG9sD6cgvl/XL/RFG57PRL26tRiyRG0bHCAZKA99QMBpY2qfOg2DdO/a/dV2S7Q6BW+0HWc4g/tyhXhzp0CQLPxrVReGL/UTetaBlgBxx0FkzNfuls1PgK0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612111469; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=A+TdNI5pWxQ6NaQfL/aha6oCVCEm83H0PFBTmvUQ5ms=; b=IEPPLO/x6i4cERzL/WaDMKi5BmFLimgFEabuwGI8hfu2APMx1tq9hmf3wg1rhwabWnN30IWHl6TCUbnQLEeNX4jlf74tiyIDkbpTcM+zVbOo1bGE1g+lHKR1P029EsCgYC4J/92yn6Is2wlAHxQ7dQpEbAUgqXzdcQ2rfcD6Fe4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by mx.zohomail.com with SMTPS id 1612111469766476.4519462633174; Sun, 31 Jan 2021 08:44:29 -0800 (PST) Received: by mail-wr1-f42.google.com with SMTP id v15so14048714wrx.4 for ; Sun, 31 Jan 2021 08:44:27 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id v126sm19002105wma.22.2021.01.31.08.44.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 08:44:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A+TdNI5pWxQ6NaQfL/aha6oCVCEm83H0PFBTmvUQ5ms=; b=SznLTWifMrDliGHi8VQAsrfbKvE0Mzhx+KuzQNsXJVmm0AVFRXm678y5WMozpfyPsO dpCMEsUSlzErF6ULbuo316ffU54Q+hQZQ6H6Bhc7A8GDjif2ewnoH0MbDhiUwuvvOc7z ULSxH3b5+EcfYFlnUbtRm3cvD5qwArsIiExEtovw1py5XOPeNSOfq+LL18CoB+TeHnK9 P+OTZm70y3ykKutL6f/IpwXiWhV0vdhzf5321HH0fiMhOJdB5cHDv9LXUdkV4vkGiHDc XwbQ7Pp5pj+AVtNXcK0tKNI99Rjg4zg79JJ7ci9u+m46GX6wIaZBT9YkZ1YoZJKetGsD ibfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=A+TdNI5pWxQ6NaQfL/aha6oCVCEm83H0PFBTmvUQ5ms=; b=SAjFAK/I+/Mg4cAnt1GB+JBBSmnDiY125MXiyZWhlW2yD7SH/H5ioanS7hsO/JQoKn +6gsjv347G5iK2N0edjUk1oUU4GfLsesw2Q6FwiQEKYG4/HCVxDA0Q6/bgpARaJBQ2wN eoZ6Te1JM44hGBXLWq+8E0pOBzkbLDkHJPSYMqUjzPHJ/9qa+1cuF1gKO3Jh7N8VpC7w uhpzcWiRZnmSJd9fPQNw/Agg8SpQHS2FY1AlphZCtCas96GdvhXReBTMeELJK8GMxIx2 /v20zmE3gP97EdUvgmPXdq1HpqF2s633FHsWYyvb/zqsG6Qttwr6hwps5FOQfLH4dD2F HwLw== X-Gm-Message-State: AOAM531NSYbWsljKMX76MjGTHHibWhPFzyDTcC+DLB9UbYplbS8N5kYU JU1Cd6U5Tnj1scX+7LZsZu8= X-Google-Smtp-Source: ABdhPJzxpKQQxeqoGJtXGTCcPmPkAx+MnA7m9uRujmV7nCTTG/OZNkeh6uHK+oiUqjtGd5j8HFKcAg== X-Received: by 2002:a5d:4242:: with SMTP id s2mr14449388wrr.108.1612111466023; Sun, 31 Jan 2021 08:44:26 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 3/5] target/arm: Restrict v8M IDAU to TCG Date: Sun, 31 Jan 2021 17:44:04 +0100 Message-Id: <20210131164406.349825-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131164406.349825-1-f4bug@amsat.org> References: <20210131164406.349825-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) IDAU is specific to M-profile. KVM only supports A-profile. Restrict this interface to TCG, as it is pointless (and confusing) on a KVM-only build. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- target/arm/cpu.c | 7 ------- target/arm/cpu_tcg.c | 8 ++++++++ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 40142ac141e..d0853fae5ae 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2352,12 +2352,6 @@ static const TypeInfo arm_cpu_type_info =3D { .class_init =3D arm_cpu_class_init, }; =20 -static const TypeInfo idau_interface_type_info =3D { - .name =3D TYPE_IDAU_INTERFACE, - .parent =3D TYPE_INTERFACE, - .class_size =3D sizeof(IDAUInterfaceClass), -}; - static void arm_cpu_register_types(void) { const size_t cpu_count =3D ARRAY_SIZE(arm_cpus); @@ -2371,7 +2365,6 @@ static void arm_cpu_register_types(void) if (cpu_count) { size_t i; =20 - type_register_static(&idau_interface_type_info); for (i =3D 0; i < cpu_count; ++i) { arm_cpu_register(&arm_cpus[i]); } diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 3e1c9b40353..bddfbf5e3a9 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -11,6 +11,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internals.h" +#include "target/arm/idau.h" =20 /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) @@ -719,10 +720,17 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { { .name =3D "pxa270-c5", .initfn =3D pxa270c5_initfn }, }; =20 +static const TypeInfo idau_interface_type_info =3D { + .name =3D TYPE_IDAU_INTERFACE, + .parent =3D TYPE_INTERFACE, + .class_size =3D sizeof(IDAUInterfaceClass), +}; + static void arm_tcg_cpu_register_types(void) { size_t i; =20 + type_register_static(&idau_interface_type_info); for (i =3D 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) { arm_cpu_register(&arm_tcg_cpus[i]); } --=20 2.26.2 From nobody Fri May 17 00:15:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) client-ip=209.85.128.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1612111473; cv=none; d=zohomail.com; s=zohoarc; b=EIN6rKSCZqJw6Dk4Rb/2dKNkvtgeZeFGyLDU9cMip/z7QUmQhLTMJeZGktFckFg52ON1wLwj2swBLezdwCps1PsQWV6Aq2jGtn79VdkR9BvuhKXgSXD8cdloTmbpSWo36OUEuOwP7LTB/PKKOksmM78c8COcDZ0NClmNEUDM5rQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612111473; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=P3RGtYOfTPa/4QX/PpSq+3Pw4Nd81ZJXrAdtTbdsm7Q=; b=PoewJBLKQ5NTCE7o/wtTSN7vYKmi7GNvOr66vX+2apVlVpJeIJzngIgS3RqeQw4kn4Cz/sARKo3yO+n7diL6nfO14bpLcVpn2EgQsH35AqYU4uvhRkfZVrjPdQP3lZuF8tDcKz1QX+H7GtNKwMcFQHS9qOIa56vPQHPPzbH+Ck0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) by mx.zohomail.com with SMTPS id 161211147326473.1687145497682; Sun, 31 Jan 2021 08:44:33 -0800 (PST) Received: by mail-wm1-f44.google.com with SMTP id s24so9974784wmj.0 for ; Sun, 31 Jan 2021 08:44:32 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id d3sm26664724wrp.79.2021.01.31.08.44.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 08:44:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P3RGtYOfTPa/4QX/PpSq+3Pw4Nd81ZJXrAdtTbdsm7Q=; b=A/dTHcDqqwc/tv3bQIAUAgwkqkP9ogdiVYTHvGv4iS35a2bxwgVuewcC+imA8Fy/Dm 9z8r+8Dz2f4j2yM5Zjwu7RZFN9ZeJlnWYz+El1ZewH64ly3EXRycrTgWz5utguWbI3mP f63oCoK/vERG7govyVTx2HOnU19BwZgdqHP3uDAIO+SKM9bWxBYaLsuvq+ZAA0cFYjHd owSiGCbvLHh86Ik9nixpSBy3859VTpWySRlnKU6AJz47ETY6a9riCJxSMbDvFccJjdOE v0Jn+pon3g2pbVh7IOiSWTYVuMokX3myMIN+wwIvYvgAmkbMxtGS0MAwfUsVAMlDlC01 e7EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=P3RGtYOfTPa/4QX/PpSq+3Pw4Nd81ZJXrAdtTbdsm7Q=; b=FaPnXCL+jzb4o+xSDUm4JkvcOFluOladLAeag4DUynWp6un4imoHhquM2LTPnTzqeC pRFcwjRLPm2a4lQHGsWp/oawyADUDO3cTHJG92mzwtCIsP9gzTvDkPCMvhJhsYYMs6M6 lI6BAzBvDg6BSwjT+GZ7SSOm/08phUbLx83774JSbu1fNpzj9eOktvnBftRSpSWqDkpB J/BH40U9lPxP4bogpUCrjoBLah46AioITuVGOSIcXtgb0WPGdiPaWLWej32PqF+mDxIf 41VU7TmBMZoojihFYRgNRSSsnMa1Ef97qZNUJke34jFXj4Dl2aJc3LFsFVuNW/8fNXms iQ/Q== X-Gm-Message-State: AOAM532eUtK6Ov7mjV0Cj1h29WJN+ubT4o6bZYgFAbY/G+8PD+WdHhYk g8uDZxi/GEheS1u5+pB0ggc= X-Google-Smtp-Source: ABdhPJyBJV9qNbR5DPTz0HUp0DyXl1ZIzB9xoOCs3LTwCfRoVPiZP6SqvsQYCveB1TIND08YEA7Xkg== X-Received: by 2002:a1c:9e4d:: with SMTP id h74mr7608936wme.103.1612111471488; Sun, 31 Jan 2021 08:44:31 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 4/5] target/arm/cpu: Update coding style to make checkpatch.pl happy Date: Sun, 31 Jan 2021 17:44:05 +0100 Message-Id: <20210131164406.349825-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131164406.349825-1-f4bug@amsat.org> References: <20210131164406.349825-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We will move this code in the next commit. Clean it up first to avoid checkpatch.pl errors. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- target/arm/cpu.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d0853fae5ae..2d8312267f7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1956,7 +1956,8 @@ static void cortex_a8_initfn(Object *obj) } =20 static const ARMCPRegInfo cortexa9_cp_reginfo[] =3D { - /* power_control should be set to maximum latency. Again, + /* + * power_control should be set to maximum latency. Again, * default to 0 and set by private hook */ { .name =3D "A9_PWRCTL", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 0, @@ -1993,7 +1994,8 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); - /* Note that A9 supports the MP extensions even for + /* + * Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different * and valid configurations; we don't model A9UP). */ @@ -2030,7 +2032,8 @@ static uint64_t a15_l2ctlr_read(CPUARMState *env, con= st ARMCPRegInfo *ri) { MachineState *ms =3D MACHINE(qdev_get_machine()); =20 - /* Linux wants the number of processors from here. + /* + * Linux wants the number of processors from here. * Might as well set the interrupt-controller bit too. */ return ((ms->smp.cpus - 1) << 24) | (1 << 23); @@ -2077,7 +2080,8 @@ static void cortex_a7_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01240000; cpu->isar.id_mmfr3 =3D 0x02102211; - /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but + /* + * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but * table 4-41 gives 0x02101110, which includes the arm div insns. */ cpu->isar.id_isar0 =3D 0x02101110; --=20 2.26.2 From nobody Fri May 17 00:15:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) client-ip=209.85.221.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1612111479; cv=none; d=zohomail.com; s=zohoarc; b=A+GmDXeKOPuhBlWmQuv3Uboy0kNgKKFCZ/5Mle50lNzafGAgahNNsD6jnmhfUHgVpGP43xhV7LYnLBf4lqu5Z21xO0bbIYCRa536rpX1iKIp/N64963a/YudhnhiDoiR0Y3nf+8xntFWAieH84S9TR1dPFwbMJhiOv/00neyhfk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612111479; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HAQsUmSJv4RsQU5o8at7OdfU6YsAfj1cwMNlNa7h8w0=; b=TmRAtFbtSDeJJHh8/o2wnGzVc8RqZM+6ghd3X3p1+Fs6Mhfnu5V5ZJb2gJXStACjtIFYjg38GNODgV2R0IbvrbmMkEWg1zO/UYMDHxmrWcbt9qx6u0bkuUtraEmj+HStrcAFb+m8uxJWOCJpFhOyjRzPu3OnnlsP3plyOs+qP8w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) by mx.zohomail.com with SMTPS id 1612111479043616.0862258671292; Sun, 31 Jan 2021 08:44:39 -0800 (PST) Received: by mail-wr1-f46.google.com with SMTP id g10so14027502wrx.1 for ; Sun, 31 Jan 2021 08:44:38 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id e16sm23643904wrp.24.2021.01.31.08.44.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 08:44:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HAQsUmSJv4RsQU5o8at7OdfU6YsAfj1cwMNlNa7h8w0=; b=vO8GS+iB+KSqO9O7llYrgD3yQDaBw0NTqXO/AIDpoQlTFvU5BdFxQ5Xmi9Yq7DHU5M XVaYjGfP1kOkKpI84MNDF6ii8nD0AMFUAO/zswYYuzRm8a0wOw20L+tw/jl1c/t4ZXoS aP+g3laMj14w0FAtzJwXz2dWuTMbBp1a8yLZ9uDUfscUOuJkDijwLG2wXx81E7uGbwEN 3Z68lQeaXlALlBXfbL0XXuMoPY3acbqrHrL74iAPrv96KhShA2FIdQgLLlnQ8ByQ3KTf KFORs1RtxZq1ebUQ4png+sGXuF/A4e0lSzp4mNZaIcTpg9i4nbP5TzmeieMVL18isJMU Gy5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=HAQsUmSJv4RsQU5o8at7OdfU6YsAfj1cwMNlNa7h8w0=; b=A0/oMgo8TNkDWrZ2LhNL8hRSDS8pnrvWKdmakLJSChoSfZMMZOgzcJIImjHoGZoaC2 E3gUpr8E27EVGnlrub/qqAI3gzhxLUz0HcxGqY5OnEjmo8jE1yUT9geA9onS33YFIkLU J2hyXumOCTqsbqdFxREctLWtGiTnYdS0CyOo2CViTB06KuCRxLMWezZcFTM/DxFHvF/y TMAjbxqhF9knlbriK+fbGka8tw2+X8/Hef2yvggXJeHCE86HjQejpL3wCNhP01f3jKNn GZ4GXjZLIYfAJZ5AKkQiBfKr5STu8dpBOMbmY/0eAvTUq3xcPRumkufUqxXGDnjwYR3T N5xw== X-Gm-Message-State: AOAM532F2vBX7v4nKPAetNxS25BnOh0i6lKYnXqwI94DjofuNWmVYUDF sPT7dj9cUxTR+SYSqiMjjzM= X-Google-Smtp-Source: ABdhPJwY9NgrzsoxviLa/LENSWrK/Wolx0RxjKY6AcjLe2BJb/XGu6d/umDr0/dSrPadU+FvU4iaSw== X-Received: by 2002:a5d:4391:: with SMTP id i17mr14233857wrq.57.1612111477032; Sun, 31 Jan 2021 08:44:37 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 5/5] target/arm: Restrict v7A TCG cpus to TCG accel Date: Sun, 31 Jan 2021 17:44:06 +0100 Message-Id: <20210131164406.349825-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131164406.349825-1-f4bug@amsat.org> References: <20210131164406.349825-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) KVM requires the target cpu to be at least ARMv8 architecture (support on ARMv7 has been dropped in commit 82bf7ae84ce: "target/arm: Remove KVM support for 32-bit Arm hosts"). A KVM-only build won't be able to run TCG cpus, move the v7A CPU definitions to cpu_tcg.c. Reported-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- target/arm/cpu.c | 327 ------------------------------------------- target/arm/cpu_tcg.c | 310 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 310 insertions(+), 327 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2d8312267f7..3f10614778b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1906,323 +1906,6 @@ static ObjectClass *arm_cpu_class_by_name(const cha= r *cpu_model) return oc; } =20 -/* CPU models. These are not needed for the AArch64 linux-user build. */ -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) - -static const ARMCPRegInfo cortexa8_cp_reginfo[] =3D { - { .name =3D "L2LOCKDOWN", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 = =3D 1, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2AUXCR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 2, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -static void cortex_a8_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a8"; - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_EL3); - cpu->midr =3D 0x410fc080; - cpu->reset_fpsid =3D 0x410330c0; - cpu->isar.mvfr0 =3D 0x11110222; - cpu->isar.mvfr1 =3D 0x00011111; - cpu->ctr =3D 0x82048004; - cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x1031; - cpu->isar.id_pfr1 =3D 0x11; - cpu->isar.id_dfr0 =3D 0x400; - cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x31100003; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01202000; - cpu->isar.id_mmfr3 =3D 0x11; - cpu->isar.id_isar0 =3D 0x00101111; - cpu->isar.id_isar1 =3D 0x12112111; - cpu->isar.id_isar2 =3D 0x21232031; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x00111142; - cpu->isar.dbgdidr =3D 0x15141000; - cpu->clidr =3D (1 << 27) | (2 << 24) | 3; - cpu->ccsidr[0] =3D 0xe007e01a; /* 16k L1 dcache. */ - cpu->ccsidr[1] =3D 0x2007e01a; /* 16k L1 icache. */ - cpu->ccsidr[2] =3D 0xf0000000; /* No L2 icache. */ - cpu->reset_auxcr =3D 2; - define_arm_cp_regs(cpu, cortexa8_cp_reginfo); -} - -static const ARMCPRegInfo cortexa9_cp_reginfo[] =3D { - /* - * power_control should be set to maximum latency. Again, - * default to 0 and set by private hook - */ - { .name =3D "A9_PWRCTL", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_power_control) }, - { .name =3D "A9_DIAG", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D = 0, .opc2 =3D 1, - .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_diagnostic) }, - { .name =3D "A9_PWRDIAG", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_power_diagnostic) }, - { .name =3D "NEONBUSY", .cp =3D 15, .crn =3D 15, .crm =3D 1, .opc1 =3D= 0, .opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, - /* TLB lockdown control */ - { .name =3D "TLB_LOCKR", .cp =3D 15, .crn =3D 15, .crm =3D 4, .opc1 = =3D 5, .opc2 =3D 2, - .access =3D PL1_W, .resetvalue =3D 0, .type =3D ARM_CP_NOP }, - { .name =3D "TLB_LOCKW", .cp =3D 15, .crn =3D 15, .crm =3D 4, .opc1 = =3D 5, .opc2 =3D 4, - .access =3D PL1_W, .resetvalue =3D 0, .type =3D ARM_CP_NOP }, - { .name =3D "TLB_VA", .cp =3D 15, .crn =3D 15, .crm =3D 5, .opc1 =3D 5= , .opc2 =3D 2, - .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, - { .name =3D "TLB_PA", .cp =3D 15, .crn =3D 15, .crm =3D 6, .opc1 =3D 5= , .opc2 =3D 2, - .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, - { .name =3D "TLB_ATTR", .cp =3D 15, .crn =3D 15, .crm =3D 7, .opc1 =3D= 5, .opc2 =3D 2, - .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, - REGINFO_SENTINEL -}; - -static void cortex_a9_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a9"; - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_EL3); - /* - * Note that A9 supports the MP extensions even for - * A9UP and single-core A9MP (which are both different - * and valid configurations; we don't model A9UP). - */ - set_feature(&cpu->env, ARM_FEATURE_V7MP); - set_feature(&cpu->env, ARM_FEATURE_CBAR); - cpu->midr =3D 0x410fc090; - cpu->reset_fpsid =3D 0x41033090; - cpu->isar.mvfr0 =3D 0x11110222; - cpu->isar.mvfr1 =3D 0x01111111; - cpu->ctr =3D 0x80038003; - cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x1031; - cpu->isar.id_pfr1 =3D 0x11; - cpu->isar.id_dfr0 =3D 0x000; - cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x00100103; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01230000; - cpu->isar.id_mmfr3 =3D 0x00002111; - cpu->isar.id_isar0 =3D 0x00101111; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x00111142; - cpu->isar.dbgdidr =3D 0x35141000; - cpu->clidr =3D (1 << 27) | (1 << 24) | 3; - cpu->ccsidr[0] =3D 0xe00fe019; /* 16k L1 dcache. */ - cpu->ccsidr[1] =3D 0x200fe019; /* 16k L1 icache. */ - define_arm_cp_regs(cpu, cortexa9_cp_reginfo); -} - -#ifndef CONFIG_USER_ONLY -static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - MachineState *ms =3D MACHINE(qdev_get_machine()); - - /* - * Linux wants the number of processors from here. - * Might as well set the interrupt-controller bit too. - */ - return ((ms->smp.cpus - 1) << 24) | (1 << 23); -} -#endif - -static const ARMCPRegInfo cortexa15_cp_reginfo[] =3D { -#ifndef CONFIG_USER_ONLY - { .name =3D "L2CTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1,= .opc2 =3D 2, - .access =3D PL1_RW, .resetvalue =3D 0, .readfn =3D a15_l2ctlr_read, - .writefn =3D arm_cp_write_ignore, }, -#endif - { .name =3D "L2ECTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -static void cortex_a7_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a7"; - set_feature(&cpu->env, ARM_FEATURE_V7VE); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A7; - cpu->midr =3D 0x410fc075; - cpu->reset_fpsid =3D 0x41023075; - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x11111111; - cpu->ctr =3D 0x84448003; - cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x00001131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_dfr0 =3D 0x02010555; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01240000; - cpu->isar.id_mmfr3 =3D 0x02102211; - /* - * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but - * table 4-41 gives 0x02101110, which includes the arm div insns. - */ - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x10011142; - cpu->isar.dbgdidr =3D 0x3515f005; - cpu->clidr =3D 0x0a200023; - cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ - cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ - define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ -} - -static void cortex_a15_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a15"; - set_feature(&cpu->env, ARM_FEATURE_V7VE); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A15; - cpu->midr =3D 0x412fc0f1; - cpu->reset_fpsid =3D 0x410430f0; - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x11111111; - cpu->ctr =3D 0x8444c004; - cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x00001131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_dfr0 =3D 0x02010555; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01240000; - cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x10011142; - cpu->isar.dbgdidr =3D 0x3515f021; - cpu->clidr =3D 0x0a200023; - cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ - cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ - define_arm_cp_regs(cpu, cortexa15_cp_reginfo); -} - -#ifndef TARGET_AARCH64 -/* - * -cpu max: a CPU with as many features enabled as our emulation supports. - * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; - * this only needs to handle 32 bits, and need not care about KVM. - */ -static void arm_max_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cortex_a15_initfn(obj); - - /* old-style VFP short-vector support */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); - -#ifdef CONFIG_USER_ONLY - /* - * We don't set these in system emulation mode for the moment, - * since we don't correctly set (all of) the ID registers to - * advertise them. - */ - set_feature(&cpu->env, ARM_FEATURE_V8); - { - uint32_t t; - - t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D t; - - t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - cpu->isar.id_isar6 =3D t; - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D t; - - t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D t; - } -#endif -} -#endif - -#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ - -static const ARMCPUInfo arm_cpus[] =3D { -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) - { .name =3D "cortex-a7", .initfn =3D cortex_a7_initfn }, - { .name =3D "cortex-a8", .initfn =3D cortex_a8_initfn }, - { .name =3D "cortex-a9", .initfn =3D cortex_a9_initfn }, - { .name =3D "cortex-a15", .initfn =3D cortex_a15_initfn }, -#ifndef TARGET_AARCH64 - { .name =3D "max", .initfn =3D arm_max_initfn }, -#endif -#ifdef CONFIG_USER_ONLY - { .name =3D "any", .initfn =3D arm_max_initfn }, -#endif -#endif -}; - static Property arm_cpu_properties[] =3D { DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), @@ -2358,21 +2041,11 @@ static const TypeInfo arm_cpu_type_info =3D { =20 static void arm_cpu_register_types(void) { - const size_t cpu_count =3D ARRAY_SIZE(arm_cpus); - type_register_static(&arm_cpu_type_info); =20 #ifdef CONFIG_KVM type_register_static(&host_arm_cpu_type_info); #endif - - if (cpu_count) { - size_t i; - - for (i =3D 0; i < cpu_count; ++i) { - arm_cpu_register(&arm_cpus[i]); - } - } } =20 type_init(arm_cpu_register_types) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index bddfbf5e3a9..1572620fba9 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -12,6 +12,9 @@ #include "cpu.h" #include "internals.h" #include "target/arm/idau.h" +#if !defined(CONFIG_USER_ONLY) +#include "hw/boards.h" +#endif =20 /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) @@ -252,6 +255,236 @@ static void arm11mpcore_initfn(Object *obj) cpu->reset_auxcr =3D 1; } =20 +static const ARMCPRegInfo cortexa8_cp_reginfo[] =3D { + { .name =3D "L2LOCKDOWN", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 = =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2AUXCR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +static void cortex_a8_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a8"; + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_EL3); + cpu->midr =3D 0x410fc080; + cpu->reset_fpsid =3D 0x410330c0; + cpu->isar.mvfr0 =3D 0x11110222; + cpu->isar.mvfr1 =3D 0x00011111; + cpu->ctr =3D 0x82048004; + cpu->reset_sctlr =3D 0x00c50078; + cpu->isar.id_pfr0 =3D 0x1031; + cpu->isar.id_pfr1 =3D 0x11; + cpu->isar.id_dfr0 =3D 0x400; + cpu->id_afr0 =3D 0; + cpu->isar.id_mmfr0 =3D 0x31100003; + cpu->isar.id_mmfr1 =3D 0x20000000; + cpu->isar.id_mmfr2 =3D 0x01202000; + cpu->isar.id_mmfr3 =3D 0x11; + cpu->isar.id_isar0 =3D 0x00101111; + cpu->isar.id_isar1 =3D 0x12112111; + cpu->isar.id_isar2 =3D 0x21232031; + cpu->isar.id_isar3 =3D 0x11112131; + cpu->isar.id_isar4 =3D 0x00111142; + cpu->isar.dbgdidr =3D 0x15141000; + cpu->clidr =3D (1 << 27) | (2 << 24) | 3; + cpu->ccsidr[0] =3D 0xe007e01a; /* 16k L1 dcache. */ + cpu->ccsidr[1] =3D 0x2007e01a; /* 16k L1 icache. */ + cpu->ccsidr[2] =3D 0xf0000000; /* No L2 icache. */ + cpu->reset_auxcr =3D 2; + define_arm_cp_regs(cpu, cortexa8_cp_reginfo); +} + +static const ARMCPRegInfo cortexa9_cp_reginfo[] =3D { + /* + * power_control should be set to maximum latency. Again, + * default to 0 and set by private hook + */ + { .name =3D "A9_PWRCTL", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_power_control) }, + { .name =3D "A9_DIAG", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D = 0, .opc2 =3D 1, + .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_diagnostic) }, + { .name =3D "A9_PWRDIAG", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_power_diagnostic) }, + { .name =3D "NEONBUSY", .cp =3D 15, .crn =3D 15, .crm =3D 1, .opc1 =3D= 0, .opc2 =3D 0, + .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, + /* TLB lockdown control */ + { .name =3D "TLB_LOCKR", .cp =3D 15, .crn =3D 15, .crm =3D 4, .opc1 = =3D 5, .opc2 =3D 2, + .access =3D PL1_W, .resetvalue =3D 0, .type =3D ARM_CP_NOP }, + { .name =3D "TLB_LOCKW", .cp =3D 15, .crn =3D 15, .crm =3D 4, .opc1 = =3D 5, .opc2 =3D 4, + .access =3D PL1_W, .resetvalue =3D 0, .type =3D ARM_CP_NOP }, + { .name =3D "TLB_VA", .cp =3D 15, .crn =3D 15, .crm =3D 5, .opc1 =3D 5= , .opc2 =3D 2, + .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, + { .name =3D "TLB_PA", .cp =3D 15, .crn =3D 15, .crm =3D 6, .opc1 =3D 5= , .opc2 =3D 2, + .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, + { .name =3D "TLB_ATTR", .cp =3D 15, .crn =3D 15, .crm =3D 7, .opc1 =3D= 5, .opc2 =3D 2, + .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, + REGINFO_SENTINEL +}; + +static void cortex_a9_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a9"; + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_EL3); + /* + * Note that A9 supports the MP extensions even for + * A9UP and single-core A9MP (which are both different + * and valid configurations; we don't model A9UP). + */ + set_feature(&cpu->env, ARM_FEATURE_V7MP); + set_feature(&cpu->env, ARM_FEATURE_CBAR); + cpu->midr =3D 0x410fc090; + cpu->reset_fpsid =3D 0x41033090; + cpu->isar.mvfr0 =3D 0x11110222; + cpu->isar.mvfr1 =3D 0x01111111; + cpu->ctr =3D 0x80038003; + cpu->reset_sctlr =3D 0x00c50078; + cpu->isar.id_pfr0 =3D 0x1031; + cpu->isar.id_pfr1 =3D 0x11; + cpu->isar.id_dfr0 =3D 0x000; + cpu->id_afr0 =3D 0; + cpu->isar.id_mmfr0 =3D 0x00100103; + cpu->isar.id_mmfr1 =3D 0x20000000; + cpu->isar.id_mmfr2 =3D 0x01230000; + cpu->isar.id_mmfr3 =3D 0x00002111; + cpu->isar.id_isar0 =3D 0x00101111; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232041; + cpu->isar.id_isar3 =3D 0x11112131; + cpu->isar.id_isar4 =3D 0x00111142; + cpu->isar.dbgdidr =3D 0x35141000; + cpu->clidr =3D (1 << 27) | (1 << 24) | 3; + cpu->ccsidr[0] =3D 0xe00fe019; /* 16k L1 dcache. */ + cpu->ccsidr[1] =3D 0x200fe019; /* 16k L1 icache. */ + define_arm_cp_regs(cpu, cortexa9_cp_reginfo); +} + +#ifndef CONFIG_USER_ONLY +static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + + /* + * Linux wants the number of processors from here. + * Might as well set the interrupt-controller bit too. + */ + return ((ms->smp.cpus - 1) << 24) | (1 << 23); +} +#endif + +static const ARMCPRegInfo cortexa15_cp_reginfo[] =3D { +#ifndef CONFIG_USER_ONLY + { .name =3D "L2CTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1,= .opc2 =3D 2, + .access =3D PL1_RW, .resetvalue =3D 0, .readfn =3D a15_l2ctlr_read, + .writefn =3D arm_cp_write_ignore, }, +#endif + { .name =3D "L2ECTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +static void cortex_a7_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a7"; + set_feature(&cpu->env, ARM_FEATURE_V7VE); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A7; + cpu->midr =3D 0x410fc075; + cpu->reset_fpsid =3D 0x41023075; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x11111111; + cpu->ctr =3D 0x84448003; + cpu->reset_sctlr =3D 0x00c50078; + cpu->isar.id_pfr0 =3D 0x00001131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x02010555; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01240000; + cpu->isar.id_mmfr3 =3D 0x02102211; + /* + * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but + * table 4-41 gives 0x02101110, which includes the arm div insns. + */ + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232041; + cpu->isar.id_isar3 =3D 0x11112131; + cpu->isar.id_isar4 =3D 0x10011142; + cpu->isar.dbgdidr =3D 0x3515f005; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ + cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ + define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ +} + +static void cortex_a15_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a15"; + set_feature(&cpu->env, ARM_FEATURE_V7VE); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A15; + cpu->midr =3D 0x412fc0f1; + cpu->reset_fpsid =3D 0x410430f0; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x11111111; + cpu->ctr =3D 0x8444c004; + cpu->reset_sctlr =3D 0x00c50078; + cpu->isar.id_pfr0 =3D 0x00001131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x02010555; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x20000000; + cpu->isar.id_mmfr2 =3D 0x01240000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232041; + cpu->isar.id_isar3 =3D 0x11112131; + cpu->isar.id_isar4 =3D 0x10011142; + cpu->isar.dbgdidr =3D 0x3515f021; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ + cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ + define_arm_cp_regs(cpu, cortexa15_cp_reginfo); +} + static void cortex_m0_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -675,6 +908,73 @@ static void arm_v7m_class_init(ObjectClass *oc, void *= data) cc->gdb_core_xml_file =3D "arm-m-profile.xml"; } =20 +#ifndef TARGET_AARCH64 +/* + * -cpu max: a CPU with as many features enabled as our emulation supports. + * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; + * this only needs to handle 32 bits, and need not care about KVM. + */ +static void arm_max_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cortex_a15_initfn(obj); + + /* old-style VFP short-vector support */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + +#ifdef CONFIG_USER_ONLY + /* + * We don't set these in system emulation mode for the moment, + * since we don't correctly set (all of) the ID registers to + * advertise them. + */ + set_feature(&cpu->env, ARM_FEATURE_V8); + { + uint32_t t; + + t =3D cpu->isar.id_isar5; + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D t; + + t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + cpu->isar.id_isar6 =3D t; + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + t =3D cpu->isar.id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D t; + + t =3D cpu->isar.id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D t; + } +#endif +} +#endif + static const ARMCPUInfo arm_tcg_cpus[] =3D { { .name =3D "arm926", .initfn =3D arm926_initfn }, { .name =3D "arm946", .initfn =3D arm946_initfn }, @@ -688,6 +988,10 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { { .name =3D "arm1136", .initfn =3D arm1136_initfn }, { .name =3D "arm1176", .initfn =3D arm1176_initfn }, { .name =3D "arm11mpcore", .initfn =3D arm11mpcore_initfn }, + { .name =3D "cortex-a7", .initfn =3D cortex_a7_initfn }, + { .name =3D "cortex-a8", .initfn =3D cortex_a8_initfn }, + { .name =3D "cortex-a9", .initfn =3D cortex_a9_initfn }, + { .name =3D "cortex-a15", .initfn =3D cortex_a15_initfn }, { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, @@ -718,6 +1022,12 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { { .name =3D "pxa270-b1", .initfn =3D pxa270b1_initfn }, { .name =3D "pxa270-c0", .initfn =3D pxa270c0_initfn }, { .name =3D "pxa270-c5", .initfn =3D pxa270c5_initfn }, +#ifndef TARGET_AARCH64 + { .name =3D "max", .initfn =3D arm_max_initfn }, +#endif +#ifdef CONFIG_USER_ONLY + { .name =3D "any", .initfn =3D arm_max_initfn }, +#endif }; =20 static const TypeInfo idau_interface_type_info =3D { --=20 2.26.2