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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id d133sm9247265pfd.6.2021.01.29.12.10.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 12:10:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OyWA4EsPCVawv9oYLu1X0a+rhhmIgXsXz2Cg+CqfoCA=; b=gzQHmA585Np1v1BdauhVLjeEuf/LbGnYDD+1LSbaxUjMDfq3fmOrbBZSiwIxqsxeUX PvoU81N/JVWtMMvqddqxd+97btEPTu5lDgBPq1haqLrqwrEn7cyggfl3RKn2VslS9xCn 11xKgXnGmGhQIt56/y64uPcUXa8iOZfCZFtVl64yYjgWZj64N4hfxH1fUd/YUocL/uJJ vTF9yad4viGEl50jvdJAp03i75wPLzVN3JPjQHm4iE1QrW+8SuDVz9vwMjfaSl4gcui+ jVSQ4/WaldyP/Bv9wXQjWRWjKEt1GdzJ3ZY53yA07XB1QyD51i7AxatpJMg4Mk4iN6+n ZSAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OyWA4EsPCVawv9oYLu1X0a+rhhmIgXsXz2Cg+CqfoCA=; b=szuOLIkF3q/pCNGvRk7JJxpDgrogfVSe9D3zsI19QjArrdxqGdVucNCPO2nyf4Z4sx sYgwrXNdR9p1kDYaGbKYhfoTo8kzgR42Ol5HVLHk2cWu8nXzebQ1LRa2TjbMXQDRnBzG vJgN5pIVWgrL6Zu8KeVvdMdbcd5BeVBm7T08PwDIngpMkDzfB0jLlbLe2ktsa944QRZf tgCDNQV3dErU5n98E+cxbbuyWzHTvM84Udi1+kLwiPRAwE1kuoF0P2HIpmief7lMe439 QwUrDWGsk6D//eumWclgxvsVTNet6UARY7KH3HULCATVoBdddqT6Iz2qNb2d+CFoRCXk KoIQ== X-Gm-Message-State: AOAM530YZlMrQEngMgKJ4FnVMIYjdFtAm5Dm3t+vzfEGz5REvXlZpmp7 +J72N3it4v+efgXPzCH/MVI+yJEeNs3WzPwN X-Google-Smtp-Source: ABdhPJyJP7EV49IvXZagCgKHSAZZ+4p5AXp13Hv0Xeq9j8alWCznkCojhM1o78u1Im6eoIPS6xOB/w== X-Received: by 2002:a17:90a:6c66:: with SMTP id x93mr5716850pjj.223.1611951040159; Fri, 29 Jan 2021 12:10:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 05/24] tcg/i386: Split out target constraints to tcg-target-con-str.h Date: Fri, 29 Jan 2021 10:10:09 -1000 Message-Id: <20210129201028.787853-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129201028.787853-1-richard.henderson@linaro.org> References: <20210129201028.787853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This eliminates the target-specific function target_parse_constraint and folds it into the single caller, process_op_defs. Since this is done directly into the switch statement, duplicates are compilation errors rather than silently ignored at runtime. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/i386/tcg-target-con-str.h | 33 +++++++++++++++++ tcg/i386/tcg-target.h | 1 + tcg/tcg.c | 33 ++++++++++++++--- tcg/i386/tcg-target.c.inc | 69 ----------------------------------- 4 files changed, 62 insertions(+), 74 deletions(-) create mode 100644 tcg/i386/tcg-target-con-str.h diff --git a/tcg/i386/tcg-target-con-str.h b/tcg/i386/tcg-target-con-str.h new file mode 100644 index 0000000000..24e6bcb80d --- /dev/null +++ b/tcg/i386/tcg-target-con-str.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define i386 target-specific operand constraints. + * Copyright (c) 2021 Linaro + * + */ + +/* + * Define constraint letters for register sets: + * REGS(letter, register_mask) + */ +REGS('a', 1u << TCG_REG_EAX) +REGS('b', 1u << TCG_REG_EBX) +REGS('c', 1u << TCG_REG_ECX) +REGS('d', 1u << TCG_REG_EDX) +REGS('S', 1u << TCG_REG_ESI) +REGS('D', 1u << TCG_REG_EDI) + +REGS('r', ALL_GENERAL_REGS) +REGS('x', ALL_VECTOR_REGS) +REGS('q', ALL_BYTEL_REGS) /* regs that can be used as a byte operand */ +REGS('Q', ALL_BYTEH_REGS) /* regs with a second byte (e.g. %ah) */ +REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_ld/st */ +REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_st8_i32 data = */ + +/* + * Define constraint letters for constants: + * CONST(letter, TCG_CT_CONST_* bit set) + */ +CONST('e', TCG_CT_CONST_S32) +CONST('I', TCG_CT_CONST_I32) +CONST('W', TCG_CT_CONST_WSZ) +CONST('Z', TCG_CT_CONST_U32) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b693d3692d..77693e13ea 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -235,5 +235,6 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CON_STR_H =20 #endif diff --git a/tcg/tcg.c b/tcg/tcg.c index 9e1b0d73c7..8cfa28ed84 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -103,8 +103,10 @@ static void tcg_register_jit_int(const void *buf, size= _t size, __attribute__((unused)); =20 /* Forward declarations for functions declared and used in tcg-target.c.in= c. */ +#ifndef TCG_TARGET_CON_STR_H static const char *target_parse_constraint(TCGArgConstraint *ct, const char *ct_str, TCGType typ= e); +#endif static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg= 1, intptr_t arg2); static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); @@ -2415,7 +2417,6 @@ static void process_op_defs(TCGContext *s) for (op =3D 0; op < NB_OPS; op++) { TCGOpDef *def =3D &tcg_op_defs[op]; const TCGTargetOpDef *tdefs; - TCGType type; int i, nb_args; =20 if (def->flags & TCG_OPF_NOT_PRESENT) { @@ -2431,7 +2432,6 @@ static void process_op_defs(TCGContext *s) /* Missing TCGTargetOpDef entry. */ tcg_debug_assert(tdefs !=3D NULL); =20 - type =3D (def->flags & TCG_OPF_64BIT ? TCG_TYPE_I64 : TCG_TYPE_I32= ); for (i =3D 0; i < nb_args; i++) { const char *ct_str =3D tdefs->args_ct_str[i]; /* Incomplete TCGTargetOpDef entry. */ @@ -2463,11 +2463,34 @@ static void process_op_defs(TCGContext *s) def->args_ct[i].ct |=3D TCG_CT_CONST; ct_str++; break; + +#ifdef TCG_TARGET_CON_STR_H + /* Include all of the target-specific constraints. */ + +#undef CONST +#define CONST(CASE, MASK) \ + case CASE: def->args_ct[i].ct |=3D MASK; ct_str++; break; +#define REGS(CASE, MASK) \ + case CASE: def->args_ct[i].regs |=3D MASK; ct_str++; break; + +#include "tcg-target-con-str.h" + +#undef REGS +#undef CONST default: - ct_str =3D target_parse_constraint(&def->args_ct[i], - ct_str, type); /* Typo in TCGTargetOpDef constraint. */ - tcg_debug_assert(ct_str !=3D NULL); + g_assert_not_reached(); +#else + default: + { + TCGType type =3D (def->flags & TCG_OPF_64BIT + ? TCG_TYPE_I64 : TCG_TYPE_I32); + ct_str =3D target_parse_constraint(&def->args_ct[i= ], + ct_str, type); + /* Typo in TCGTargetOpDef constraint. */ + tcg_debug_assert(ct_str !=3D NULL); + } +#endif } } } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 4feb7e2aa1..d3cf97748a 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -209,75 +209,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, return true; } =20 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch(*ct_str++) { - case 'a': - tcg_regset_set_reg(ct->regs, TCG_REG_EAX); - break; - case 'b': - tcg_regset_set_reg(ct->regs, TCG_REG_EBX); - break; - case 'c': - tcg_regset_set_reg(ct->regs, TCG_REG_ECX); - break; - case 'd': - tcg_regset_set_reg(ct->regs, TCG_REG_EDX); - break; - case 'S': - tcg_regset_set_reg(ct->regs, TCG_REG_ESI); - break; - case 'D': - tcg_regset_set_reg(ct->regs, TCG_REG_EDI); - break; - case 'q': - /* A register that can be used as a byte operand. */ - ct->regs |=3D ALL_BYTEL_REGS; - break; - case 'Q': - /* A register with an addressable second byte (e.g. %ah). */ - ct->regs |=3D ALL_BYTEH_REGS; - break; - case 'r': - /* A general register. */ - ct->regs |=3D ALL_GENERAL_REGS; - break; - case 'W': - /* With TZCNT/LZCNT, we can have operand-size as an input. */ - ct->ct |=3D TCG_CT_CONST_WSZ; - break; - case 'x': - /* A vector register. */ - ct->regs |=3D ALL_VECTOR_REGS; - break; - - case 'L': - /* qemu_ld/st data+address constraint */ - ct->regs |=3D ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS; - break; - case 's': - /* qemu_st8_i32 data constraint */ - ct->regs |=3D ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS; - break; - - case 'e': - ct->ct |=3D TCG_CT_CONST_S32; - break; - case 'Z': - ct->ct |=3D TCG_CT_CONST_U32; - break; - case 'I': - ct->ct |=3D TCG_CT_CONST_I32; - break; - - default: - return NULL; - } - return ct_str; -} - /* test if a constant matches the constraint */ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) --=20 2.25.1