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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/s390/tcg-target-con-set.h | 29 ++++++++ tcg/s390/tcg-target.h | 1 + tcg/s390/tcg-target.c.inc | 121 ++++++++++++++-------------------- 3 files changed, 81 insertions(+), 70 deletions(-) create mode 100644 tcg/s390/tcg-target-con-set.h diff --git a/tcg/s390/tcg-target-con-set.h b/tcg/s390/tcg-target-con-set.h new file mode 100644 index 0000000000..31985e4903 --- /dev/null +++ b/tcg/s390/tcg-target-con-set.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define S390 target-specific constraint sets. + * Copyright (c) 2021 Linaro + */ + +/* + * C_On_Im(...) defines a constraint set with outputs and inputs. + * Each operand should be a sequence of constraint letters as defined by + * tcg-target-con-str.h; the constraint combination is inclusive or. + */ +C_O0_I1(r) +C_O0_I2(L, L) +C_O0_I2(r, r) +C_O0_I2(r, ri) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, 0, ri) +C_O1_I2(r, 0, rI) +C_O1_I2(r, 0, rJ) +C_O1_I2(r, r, ri) +C_O1_I2(r, rZ, r) +C_O1_I4(r, r, ri, r, 0) +C_O1_I4(r, r, ri, rI, 0) +C_O2_I2(b, a, 0, r) +C_O2_I3(b, a, 0, 1, r) +C_O2_I4(r, r, 0, 1, rA, r) +C_O2_I4(r, r, 0, 1, ri, r) +C_O2_I4(r, r, 0, 1, r, r) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 641464eea4..7aafd25a46 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -159,5 +159,6 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CON_SET_H =20 #endif diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 3fec7fec5f..b67470137c 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -2274,27 +2274,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, } } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; - static const TCGTargetOpDef L_L =3D { .args_ct_str =3D { "L", "L" } }; - static const TCGTargetOpDef r_ri =3D { .args_ct_str =3D { "r", "ri" } = }; - static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; - static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; - static const TCGTargetOpDef r_0_rI =3D { .args_ct_str =3D { "r", "0", = "rI" } }; - static const TCGTargetOpDef r_0_rJ =3D { .args_ct_str =3D { "r", "0", = "rJ" } }; - static const TCGTargetOpDef a2_r - =3D { .args_ct_str =3D { "r", "r", "0", "1", "r", "r" } }; - static const TCGTargetOpDef a2_ri - =3D { .args_ct_str =3D { "r", "r", "0", "1", "ri", "r" } }; - static const TCGTargetOpDef a2_rA - =3D { .args_ct_str =3D { "r", "r", "0", "1", "rA", "r" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: @@ -2308,6 +2292,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: + return C_O1_I1(r, r); + case INDEX_op_st8_i32: case INDEX_op_st8_i64: case INDEX_op_st16_i32: @@ -2315,11 +2301,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_st_i32: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &r_r; + return C_O0_I2(r, r); =20 case INDEX_op_add_i32: case INDEX_op_add_i64: - return &r_r_ri; + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + case INDEX_op_clz_i64: + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + return C_O1_I2(r, r, ri); + case INDEX_op_sub_i32: case INDEX_op_sub_i64: case INDEX_op_and_i32: @@ -2328,35 +2325,33 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: - return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); + return (s390_facilities & FACILITY_DISTINCT_OPS + ? C_O1_I2(r, r, ri) + : C_O1_I2(r, 0, ri)); =20 case INDEX_op_mul_i32: /* If we have the general-instruction-extensions, then we have MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ - return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_r= I); + return (s390_facilities & FACILITY_GEN_INST_EXT + ? C_O1_I2(r, 0, ri) + : C_O1_I2(r, 0, rI)); + case INDEX_op_mul_i64: - return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_r= I); + return (s390_facilities & FACILITY_GEN_INST_EXT + ? C_O1_I2(r, 0, rJ) + : C_O1_I2(r, 0, rI)); =20 case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: - return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); - - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - return &r_r_ri; - - case INDEX_op_rotl_i32: - case INDEX_op_rotl_i64: - case INDEX_op_rotr_i32: - case INDEX_op_rotr_i64: - return &r_r_ri; + return (s390_facilities & FACILITY_DISTINCT_OPS + ? C_O1_I2(r, r, ri) + : C_O1_I2(r, 0, ri)); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_ri; + return C_O0_I2(r, ri); =20 case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: @@ -2379,63 +2374,49 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_extu_i32_i64: case INDEX_op_extract_i32: case INDEX_op_extract_i64: - return &r_r; - - case INDEX_op_clz_i64: - case INDEX_op_setcond_i32: - case INDEX_op_setcond_i64: - return &r_r_ri; + return C_O1_I1(r, r); =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return &r_L; + return C_O1_I1(r, L); case INDEX_op_qemu_st_i64: case INDEX_op_qemu_st_i32: - return &L_L; + return C_O0_I2(L, L); =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - { - static const TCGTargetOpDef dep - =3D { .args_ct_str =3D { "r", "rZ", "r" } }; - return &dep; - } + return C_O1_I2(r, rZ, r); + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - { - static const TCGTargetOpDef movc - =3D { .args_ct_str =3D { "r", "r", "ri", "r", "0" } }; - static const TCGTargetOpDef movc_l - =3D { .args_ct_str =3D { "r", "r", "ri", "rI", "0" } }; - return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &= movc); - } + return (s390_facilities & FACILITY_LOAD_ON_COND2 + ? C_O1_I4(r, r, ri, rI, 0) + : C_O1_I4(r, r, ri, r, 0)); + case INDEX_op_div2_i32: case INDEX_op_div2_i64: case INDEX_op_divu2_i32: case INDEX_op_divu2_i64: - { - static const TCGTargetOpDef div2 - =3D { .args_ct_str =3D { "b", "a", "0", "1", "r" } }; - return &div2; - } + return C_O2_I3(b, a, 0, 1, r); + case INDEX_op_mulu2_i64: - { - static const TCGTargetOpDef mul2 - =3D { .args_ct_str =3D { "b", "a", "0", "r" } }; - return &mul2; - } + return C_O2_I2(b, a, 0, r); =20 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r); + return (s390_facilities & FACILITY_EXT_IMM + ? C_O2_I4(r, r, 0, 1, ri, r) + : C_O2_I4(r, r, 0, 1, r, r)); + case INDEX_op_add2_i64: case INDEX_op_sub2_i64: - return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r); + return (s390_facilities & FACILITY_EXT_IMM + ? C_O2_I4(r, r, 0, 1, rA, r) + : C_O2_I4(r, r, 0, 1, r, r)); =20 default: - break; + g_assert_not_reached(); } - return NULL; } =20 static void query_s390_facilities(void) --=20 2.25.1