From nobody Wed Nov 13 07:16:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611952061; cv=none; d=zohomail.com; s=zohoarc; b=maLqUOiq0kleZYgGrSgos2Ohky21ew9vHu6sF4RMLRtBO6lRy+GI5sCLYhVLbVbgom5OsqdNaBXox3oaibMsTlewOUin8gU1ZKOExs0xYx4qwVLvsycSGGivaMCa92yTU4vDaOBDaXpR1NVulyNZynf3ZXRdTMos1dGr3LVMvDY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611952061; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rkcGYRpavy8b7NvBkTDEXauxxj6OsYUBpOL3Xp6QZQ8=; b=iahAcMIah5701STefpkl1LbMWlOmuxdydb3rqKvAoxfuw0LppkUqpGlZtlPN8LgGK2HwXL8apHsChsnU7YbKvcTUIWQ9S8WNDwEPXKYXglgyhajqCw7i2kbYQn+niwqWqllwh1mRgH9+BYBOCZ9m4aLv0Tm3eJZlA/w0I5uIRho= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611952061489346.9510266389167; Fri, 29 Jan 2021 12:27:41 -0800 (PST) Received: from localhost ([::1]:57234 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5aMm-0001aO-Ck for importer@patchew.org; Fri, 29 Jan 2021 15:27:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49296) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5a6k-0006vX-GP for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:11:06 -0500 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:36847) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5a6i-0008BQ-4Y for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:11:06 -0500 Received: by mail-pf1-x42b.google.com with SMTP id u67so6925919pfb.3 for ; Fri, 29 Jan 2021 12:11:03 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id d133sm9247265pfd.6.2021.01.29.12.11.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 12:11:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rkcGYRpavy8b7NvBkTDEXauxxj6OsYUBpOL3Xp6QZQ8=; b=nyXM916uZOBPQXSmAYYpm/A8qEshPgcR1Vnk0na03otWuvROXD8VzGwpRTvMVTi76x Al86pYEfSshoj4Tjlla/Zl/u11+djXyxiwZAMx6DZYkZ3czQNlFEcrzudifd1ev+Gt72 ILfiqhOf0IGnEiOQdy/WGiFF3z1RsplTdWoeWcnB3k1pVu5WbP721BUKCbWWgnxoBdrz YMna4T/TX0ZtWEJkHSFH+FfJis7DQ02H+5KSRmAFoCKE5qBwRDRlD7aNT+MB21FpwnAQ Q2lK2gPF1XZtixAF3EbU57cGZU96RYi887UXZgFyhQcwcNYsdiJNniyuixyHu/l/o5KH eu8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rkcGYRpavy8b7NvBkTDEXauxxj6OsYUBpOL3Xp6QZQ8=; b=KspWpy889TAjoxI6j/uH7DyEiWw2qP8rmQrKJXVbWCcxsIMuAA/cHpbDzKtea95dY+ KDMbVrOcVKQF08aYmFTAGSZqgIOl90GvQAMwOlWl49wsAonnwjiXG4WzxLDpswWP2m63 nekAIDkdQp1jmBP2f9pqrnW7B7tLDly+FU1ef0AAuTNCOxWAuRsnDCdunRvOZiend4jY plwAB/gC9EcyyAm+pKMMJJ8Keer3entKS8Yj/keV6mmaOx6AlUkl2wf7ndfkg1DZrQr+ elvwsdRdqqhGmhWKv2N288ke3zuABcpz+NEU3lFNRY2PhDhm0n3Va42p7JttQrDKbiwS wUDg== X-Gm-Message-State: AOAM530lv2+BLCrmBNHwBfm03zVDGRx9cfcuWcSphE2mr5vCiOkC4bRb RuCy5MdeBc4qXtwHnb3791/X+ewglY4HW769 X-Google-Smtp-Source: ABdhPJybw9oQfrO86NKDPkdMhxZuSE6NXyCqzZhj1mE5kJk/JV0WJBb5YLP2cBE7YM+5aEKQe837Vw== X-Received: by 2002:a63:6686:: with SMTP id a128mr6170089pgc.109.1611951062720; Fri, 29 Jan 2021 12:11:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 19/24] tcg/ppc: Split out constraint sets to tcg-target-con-set.h Date: Fri, 29 Jan 2021 10:10:23 -1000 Message-Id: <20210129201028.787853-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129201028.787853-1-richard.henderson@linaro.org> References: <20210129201028.787853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 42 +++++++++++ tcg/ppc/tcg-target.h | 1 + tcg/ppc/tcg-target.c.inc | 136 +++++++++++++++-------------------- 3 files changed, 99 insertions(+), 80 deletions(-) create mode 100644 tcg/ppc/tcg-target-con-set.h diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h new file mode 100644 index 0000000000..a1a345883d --- /dev/null +++ b/tcg/ppc/tcg-target-con-set.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define PowerPC target-specific constraint sets. + * Copyright (c) 2021 Linaro + */ + +/* + * C_On_Im(...) defines a constraint set with outputs and inputs. + * Each operand should be a sequence of constraint letters as defined by + * tcg-target-con-str.h; the constraint combination is inclusive or. + */ +C_O0_I1(r) +C_O0_I2(r, r) +C_O0_I2(r, ri) +C_O0_I2(S, S) +C_O0_I2(v, r) +C_O0_I3(S, S, S) +C_O0_I4(r, r, ri, ri) +C_O0_I4(S, S, S, S) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I1(v, r) +C_O1_I1(v, v) +C_O1_I1(v, vr) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, L, L) +C_O1_I2(r, rI, ri) +C_O1_I2(r, rI, rT) +C_O1_I2(r, r, r) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) +C_O1_I2(r, r, rT) +C_O1_I2(r, r, rU) +C_O1_I2(r, r, rZW) +C_O1_I2(v, v, v) +C_O1_I3(v, v, v, v) +C_O1_I4(r, r, ri, rZ, rZ) +C_O1_I4(r, r, r, ri, ri) +C_O2_I1(L, L, L) +C_O2_I2(L, L, L, L) +C_O2_I4(r, r, rI, rZM, r, r) +C_O2_I4(r, r, r, r, rI, rZM) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index d1339afc66..551f8d0fc9 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -185,5 +185,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CON_SET_H =20 #endif diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index e5aa8d2d10..4377d15d62 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3456,62 +3456,17 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,= unsigned vece, va_end(va); } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; - static const TCGTargetOpDef S_S =3D { .args_ct_str =3D { "S", "S" } }; - static const TCGTargetOpDef r_ri =3D { .args_ct_str =3D { "r", "ri" } = }; - static const TCGTargetOpDef r_r_r =3D { .args_ct_str =3D { "r", "r", "= r" } }; - static const TCGTargetOpDef r_L_L =3D { .args_ct_str =3D { "r", "L", "= L" } }; - static const TCGTargetOpDef L_L_L =3D { .args_ct_str =3D { "L", "L", "= L" } }; - static const TCGTargetOpDef S_S_S =3D { .args_ct_str =3D { "S", "S", "= S" } }; - static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; - static const TCGTargetOpDef r_r_rI =3D { .args_ct_str =3D { "r", "r", = "rI" } }; - static const TCGTargetOpDef r_r_rT =3D { .args_ct_str =3D { "r", "r", = "rT" } }; - static const TCGTargetOpDef r_r_rU =3D { .args_ct_str =3D { "r", "r", = "rU" } }; - static const TCGTargetOpDef r_rI_ri - =3D { .args_ct_str =3D { "r", "rI", "ri" } }; - static const TCGTargetOpDef r_rI_rT - =3D { .args_ct_str =3D { "r", "rI", "rT" } }; - static const TCGTargetOpDef r_r_rZW - =3D { .args_ct_str =3D { "r", "r", "rZW" } }; - static const TCGTargetOpDef L_L_L_L - =3D { .args_ct_str =3D { "L", "L", "L", "L" } }; - static const TCGTargetOpDef S_S_S_S - =3D { .args_ct_str =3D { "S", "S", "S", "S" } }; - static const TCGTargetOpDef movc - =3D { .args_ct_str =3D { "r", "r", "ri", "rZ", "rZ" } }; - static const TCGTargetOpDef dep - =3D { .args_ct_str =3D { "r", "0", "rZ" } }; - static const TCGTargetOpDef br2 - =3D { .args_ct_str =3D { "r", "r", "ri", "ri" } }; - static const TCGTargetOpDef setc2 - =3D { .args_ct_str =3D { "r", "r", "r", "ri", "ri" } }; - static const TCGTargetOpDef add2 - =3D { .args_ct_str =3D { "r", "r", "r", "r", "rI", "rZM" } }; - static const TCGTargetOpDef sub2 - =3D { .args_ct_str =3D { "r", "r", "rI", "rZM", "r", "r" } }; - static const TCGTargetOpDef v_r =3D { .args_ct_str =3D { "v", "r" } }; - static const TCGTargetOpDef v_vr =3D { .args_ct_str =3D { "v", "vr" } = }; - static const TCGTargetOpDef v_v =3D { .args_ct_str =3D { "v", "v" } }; - static const TCGTargetOpDef v_v_v =3D { .args_ct_str =3D { "v", "v", "= v" } }; - static const TCGTargetOpDef v_v_v_v - =3D { .args_ct_str =3D { "v", "v", "v", "v" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: case INDEX_op_ld16s_i32: case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: - case INDEX_op_st_i32: case INDEX_op_ctpop_i32: case INDEX_op_neg_i32: case INDEX_op_not_i32: @@ -3527,10 +3482,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: case INDEX_op_ctpop_i64: case INDEX_op_neg_i64: case INDEX_op_not_i64: @@ -3543,7 +3494,16 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_bswap32_i64: case INDEX_op_bswap64_i64: case INDEX_op_extract_i64: - return &r_r; + return C_O1_I1(r, r); + + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return C_O0_I2(r, r); =20 case INDEX_op_add_i32: case INDEX_op_and_i32: @@ -3566,10 +3526,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_rotl_i64: case INDEX_op_rotr_i64: case INDEX_op_setcond_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); + case INDEX_op_mul_i32: case INDEX_op_mul_i64: - return &r_r_rI; + return C_O1_I2(r, r, rI); + case INDEX_op_div_i32: case INDEX_op_divu_i32: case INDEX_op_nand_i32: @@ -3584,55 +3546,63 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_divu_i64: case INDEX_op_mulsh_i64: case INDEX_op_muluh_i64: - return &r_r_r; + return C_O1_I2(r, r, r); + case INDEX_op_sub_i32: - return &r_rI_ri; + return C_O1_I2(r, rI, ri); case INDEX_op_add_i64: - return &r_r_rT; + return C_O1_I2(r, r, rT); case INDEX_op_or_i64: case INDEX_op_xor_i64: - return &r_r_rU; + return C_O1_I2(r, r, rU); case INDEX_op_sub_i64: - return &r_rI_rT; + return C_O1_I2(r, rI, rT); case INDEX_op_clz_i32: case INDEX_op_ctz_i32: case INDEX_op_clz_i64: case INDEX_op_ctz_i64: - return &r_r_rZW; + return C_O1_I2(r, r, rZW); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_ri; + return C_O0_I2(r, ri); =20 case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return &movc; + return C_O1_I4(r, r, ri, rZ, rZ); case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return &dep; + return C_O1_I2(r, 0, rZ); case INDEX_op_brcond2_i32: - return &br2; + return C_O0_I4(r, r, ri, ri); case INDEX_op_setcond2_i32: - return &setc2; + return C_O1_I4(r, r, r, ri, ri); case INDEX_op_add2_i64: case INDEX_op_add2_i32: - return &add2; + return C_O2_I4(r, r, r, r, rI, rZM); case INDEX_op_sub2_i64: case INDEX_op_sub2_i32: - return &sub2; + return C_O2_I4(r, r, rI, rZM, r, r); =20 case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? &r_L : &r_L_L); + ? C_O1_I1(r, L) + : C_O1_I2(r, L, L)); + case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? &S_S : &S_S_S); + ? C_O0_I2(S, S) + : C_O0_I3(S, S, S)); + case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &r_L - : TARGET_LONG_BITS =3D=3D 32 ? &L_L_L : &L_L_L_L); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(L, L, L) + : C_O2_I2(L, L, L, L)); + case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &S_S - : TARGET_LONG_BITS =3D=3D 32 ? &S_S_S : &S_S_S_S); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(S, S) + : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(S, S, S) + : C_O0_I4(S, S, S, S)); =20 case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -3662,22 +3632,28 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_ppc_mulou_vec: case INDEX_op_ppc_pkum_vec: case INDEX_op_dup2_vec: - return &v_v_v; + return C_O1_I2(v, v, v); + case INDEX_op_not_vec: case INDEX_op_neg_vec: - return &v_v; + return C_O1_I1(v, v); + case INDEX_op_dup_vec: - return have_isa_3_00 ? &v_vr : &v_v; + return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v); + case INDEX_op_ld_vec: - case INDEX_op_st_vec: case INDEX_op_dupm_vec: - return &v_r; + return C_O1_I1(v, r); + + case INDEX_op_st_vec: + return C_O0_I2(v, r); + case INDEX_op_bitsel_vec: case INDEX_op_ppc_msum_vec: - return &v_v_v_v; + return C_O1_I3(v, v, v, v); =20 default: - return NULL; + g_assert_not_reached(); } } =20 --=20 2.25.1