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b=T4soCcczGiXfRCR6wefL+zI/vu4dCdWRgYFZpDUIQwodIqAQLV6NE9o87/ZOPF9lrL NfLf3zpTnFb9uqUj/turK5OFKv6azLEXLj5bxhk6kE/cv9L9mdQbHDULeZjkL5zOZ0wt jHAIsLJtHvk0kUe+hlikMLhhsb8i47a1OPHwn8jMfyODsDarfTvfgHWY3/mjwm2+uqHj m8RSDzzZdKH4Ae0QavEDVFwpxgOrGM4PcqC8X70FVyL3nEFl7sYN7E41AanB02Fw9bdw HZ625h7SEZKTnuYFJk+AALV9ZkYPG7MZZZNvN8dp8M9P4pqoOKC4u4X7SXrihQyRbyEB d51Q== X-Gm-Message-State: AOAM5326Rd/kc+RkL4wwdegCZqbSRMz/fgfXeumsmQlPZxMdHQyMcWjK YGhZ2IpwDIFhnRVqTmcwrnLQH3+cPVSArWoZ X-Google-Smtp-Source: ABdhPJwRi0use4LOrG3qbwYcYprWiKGiSI6z11+t9ZutsaQzaF/mnBRYB/UKaGnHlijk1fn+6ijkqg== X-Received: by 2002:a63:d446:: with SMTP id i6mr6427973pgj.446.1611951057991; Fri, 29 Jan 2021 12:10:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 16/24] tcg/aarch64: Split out constraint sets to tcg-target-con-set.h Date: Fri, 29 Jan 2021 10:10:20 -1000 Message-Id: <20210129201028.787853-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129201028.787853-1-richard.henderson@linaro.org> References: <20210129201028.787853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-set.h | 36 +++++++++++++ tcg/aarch64/tcg-target.h | 1 + tcg/aarch64/tcg-target.c.inc | 86 +++++++++++--------------------- 3 files changed, 65 insertions(+), 58 deletions(-) create mode 100644 tcg/aarch64/tcg-target-con-set.h diff --git a/tcg/aarch64/tcg-target-con-set.h b/tcg/aarch64/tcg-target-con-= set.h new file mode 100644 index 0000000000..d6c6866878 --- /dev/null +++ b/tcg/aarch64/tcg-target-con-set.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Define AArch64 target-specific constraint sets. + * Copyright (c) 2021 Linaro + */ + +/* + * C_On_Im(...) defines a constraint set with outputs and inputs. + * Each operand should be a sequence of constraint letters as defined by + * tcg-target-con-str.h; the constraint combination is inclusive or. + */ +C_O0_I1(r) +C_O0_I2(lZ, l) +C_O0_I2(r, rA) +C_O0_I2(rZ, r) +C_O0_I2(w, r) +C_O1_I1(r, l) +C_O1_I1(r, r) +C_O1_I1(w, r) +C_O1_I1(w, w) +C_O1_I1(w, wr) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, r, r) +C_O1_I2(r, r, rA) +C_O1_I2(r, r, rAL) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rL) +C_O1_I2(r, rZ, rZ) +C_O1_I2(w, 0, w) +C_O1_I2(w, w, w) +C_O1_I2(w, w, wN) +C_O1_I2(w, w, wO) +C_O1_I2(w, w, wZ) +C_O1_I3(w, w, w, w) +C_O1_I4(r, r, rA, rZ, rZ) +C_O2_I4(r, r, rZ, rZ, rA, rMZ) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 5ec30dba25..200e9b5e0e 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -155,5 +155,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CON_SET_H =20 #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 42037c98fa..3c1ee39fd4 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2547,42 +2547,11 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,= unsigned vece, va_end(va); } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef w_w =3D { .args_ct_str =3D { "w", "w" } }; - static const TCGTargetOpDef w_r =3D { .args_ct_str =3D { "w", "r" } }; - static const TCGTargetOpDef w_wr =3D { .args_ct_str =3D { "w", "wr" } = }; - static const TCGTargetOpDef r_l =3D { .args_ct_str =3D { "r", "l" } }; - static const TCGTargetOpDef r_rA =3D { .args_ct_str =3D { "r", "rA" } = }; - static const TCGTargetOpDef rZ_r =3D { .args_ct_str =3D { "rZ", "r" } = }; - static const TCGTargetOpDef lZ_l =3D { .args_ct_str =3D { "lZ", "l" } = }; - static const TCGTargetOpDef r_r_r =3D { .args_ct_str =3D { "r", "r", "= r" } }; - static const TCGTargetOpDef w_w_w =3D { .args_ct_str =3D { "w", "w", "= w" } }; - static const TCGTargetOpDef w_0_w =3D { .args_ct_str =3D { "w", "0", "= w" } }; - static const TCGTargetOpDef w_w_wO =3D { .args_ct_str =3D { "w", "w", = "wO" } }; - static const TCGTargetOpDef w_w_wN =3D { .args_ct_str =3D { "w", "w", = "wN" } }; - static const TCGTargetOpDef w_w_wZ =3D { .args_ct_str =3D { "w", "w", = "wZ" } }; - static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; - static const TCGTargetOpDef r_r_rA =3D { .args_ct_str =3D { "r", "r", = "rA" } }; - static const TCGTargetOpDef r_r_rL =3D { .args_ct_str =3D { "r", "r", = "rL" } }; - static const TCGTargetOpDef r_r_rAL - =3D { .args_ct_str =3D { "r", "r", "rAL" } }; - static const TCGTargetOpDef dep - =3D { .args_ct_str =3D { "r", "0", "rZ" } }; - static const TCGTargetOpDef ext2 - =3D { .args_ct_str =3D { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef movc - =3D { .args_ct_str =3D { "r", "r", "rA", "rZ", "rZ" } }; - static const TCGTargetOpDef add2 - =3D { .args_ct_str =3D { "r", "r", "rZ", "rZ", "rA", "rMZ" } }; - static const TCGTargetOpDef w_w_w_w - =3D { .args_ct_str =3D { "w", "w", "w", "w" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -2621,7 +2590,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_extract_i64: case INDEX_op_sextract_i32: case INDEX_op_sextract_i64: - return &r_r; + return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: case INDEX_op_st16_i32: @@ -2630,7 +2599,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &rZ_r; + return C_O0_I2(rZ, r); =20 case INDEX_op_add_i32: case INDEX_op_add_i64: @@ -2638,7 +2607,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_sub_i64: case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - return &r_r_rA; + return C_O1_I2(r, r, rA); =20 case INDEX_op_mul_i32: case INDEX_op_mul_i64: @@ -2652,7 +2621,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_remu_i64: case INDEX_op_muluh_i64: case INDEX_op_mulsh_i64: - return &r_r_r; + return C_O1_I2(r, r, r); =20 case INDEX_op_and_i32: case INDEX_op_and_i64: @@ -2666,7 +2635,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_orc_i64: case INDEX_op_eqv_i32: case INDEX_op_eqv_i64: - return &r_r_rL; + return C_O1_I2(r, r, rL); =20 case INDEX_op_shl_i32: case INDEX_op_shr_i32: @@ -2678,42 +2647,42 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_sar_i64: case INDEX_op_rotl_i64: case INDEX_op_rotr_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); =20 case INDEX_op_clz_i32: case INDEX_op_ctz_i32: case INDEX_op_clz_i64: case INDEX_op_ctz_i64: - return &r_r_rAL; + return C_O1_I2(r, r, rAL); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_rA; + return C_O0_I2(r, rA); =20 case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return &movc; + return C_O1_I4(r, r, rA, rZ, rZ); =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return &r_l; + return C_O1_I1(r, l); case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - return &lZ_l; + return C_O0_I2(lZ, l); =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return &dep; + return C_O1_I2(r, 0, rZ); =20 case INDEX_op_extract2_i32: case INDEX_op_extract2_i64: - return &ext2; + return C_O1_I2(r, rZ, rZ); =20 case INDEX_op_add2_i32: case INDEX_op_add2_i64: case INDEX_op_sub2_i32: case INDEX_op_sub2_i64: - return &add2; + return C_O2_I4(r, r, rZ, rZ, rA, rMZ); =20 case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -2731,35 +2700,36 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: case INDEX_op_aa64_sshl_vec: - return &w_w_w; + return C_O1_I2(w, w, w); case INDEX_op_not_vec: case INDEX_op_neg_vec: case INDEX_op_abs_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: - return &w_w; + return C_O1_I1(w, w); case INDEX_op_ld_vec: - case INDEX_op_st_vec: case INDEX_op_dupm_vec: - return &w_r; + return C_O1_I1(w, r); + case INDEX_op_st_vec: + return C_O0_I2(w, r); case INDEX_op_dup_vec: - return &w_wr; + return C_O1_I1(w, wr); case INDEX_op_or_vec: case INDEX_op_andc_vec: - return &w_w_wO; + return C_O1_I2(w, w, wO); case INDEX_op_and_vec: case INDEX_op_orc_vec: - return &w_w_wN; + return C_O1_I2(w, w, wN); case INDEX_op_cmp_vec: - return &w_w_wZ; + return C_O1_I2(w, w, wZ); case INDEX_op_bitsel_vec: - return &w_w_w_w; + return C_O1_I3(w, w, w, w); case INDEX_op_aa64_sli_vec: - return &w_0_w; + return C_O1_I2(w, 0, w); =20 default: - return NULL; + g_assert_not_reached(); } } =20 --=20 2.25.1