From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611951329; cv=none; d=zohomail.com; s=zohoarc; b=X9aL/MmCJ6Oe0nhqdxBbwmZnZ0ke/tdxNqc6v8l1UZZSDnNc8eDKAUp1SZ1BBuhYsqt9d0CETWFy8zSUXg/BDDoJEiOIdeZzQe1drokF1PFUVNpS0CMdDFWyW96gxHybMrqEDkXb/pTg0OedGBLsMaqSIbwkZQ+qPhLETlXAYe4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611951329; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/S1S8UJkodH9Fn5r/TRF3MeCOBnFTM9S6Ep0lCvcNE8=; b=CuzQoaqBvaLpOQetggdwnncMbPkxwGJiGtmyzQGBXC+P3udCV/v6catWHh2p7+BKz4ueE3PDU3Iyl7+3IA0+zZ2yW1vSuy7gwF7JhsPps75hKf4pQAROXo+RgEHIsfWzKnKXZACmR4nO3mwzPVHwjh2xMpCLl9kqsL3gX8eb9HI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611951329362359.21825558270757; Fri, 29 Jan 2021 12:15:29 -0800 (PST) Received: from localhost ([::1]:48892 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5aAx-0002uO-5S for importer@patchew.org; Fri, 29 Jan 2021 15:15:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48948) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5a6I-0005wi-Mv for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:39 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:33209) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5a6E-0007xy-AX for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:38 -0500 Received: by mail-pl1-x634.google.com with SMTP id d13so5901910plg.0 for ; Fri, 29 Jan 2021 12:10:33 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id d133sm9247265pfd.6.2021.01.29.12.10.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 12:10:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/S1S8UJkodH9Fn5r/TRF3MeCOBnFTM9S6Ep0lCvcNE8=; b=lmnahPEpbzaF0Lxm2nODiz7kAFOgShnSJrpdSnsMxxZjEJ1fD65XXuczeCle7kQiPD I++sgoYpsXy5wv2wdCCBGvlQd+o8aW2lc5XL9HYb7L13EoiHBKeoFeg6UripcMntQ1PO bxRIjKmoXcM7i0PEfaLafOnTkVakwosFet1h6tQYZ5yGZTfv/DeXcBDarspKWfuS5okr QuFDBVMFZVtVn/4d/5Sh3v5l0JMmL9qw9555G+8pdBfvGSom6ttDVLPwE/EA3qeJBQZB jblDulD33TXg2UBxWJlUQue17OtDkxytZp5YBaArOcKvTEwNJmsERkAj5CBXdLZD8JDU UzIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/S1S8UJkodH9Fn5r/TRF3MeCOBnFTM9S6Ep0lCvcNE8=; b=PslX7xtpIFvcR5fwCknlLNbMrthseapDbRW3mkycTL1u1K+VDsxFUMlc9yFl2dTLBb VLYf5vBTG7NEb9yxUXx0z2U+JBI2JcFduso3ggM6htmmnulgIq8xPYzXXi02b0bjKt3V 2TkIR5DAHz5rpjRjnHBGH8uv9lGxGnPEbv2JkJngcKU/TZ9rZnCfXOLfdBG1rIUJoFkm mNSeA2CYEMcI52q/GUuQsVUiEdL1AaxiXKhFHhLz+Fo8IEMhCuLlA00QhkGY9bYVRci7 /TJwbZNH6daFSzEqOsjdTrWY0xBJdDMOElPDpHkyzlRe924ok5kEy3tjEYK0dFbOhkYT T2kw== X-Gm-Message-State: AOAM531rLAeYhjQoYR7+CWTbipKypbqOyfB0urDE37gVnf0pkQJ/hTsg BIFCw9B9e5EQvFuHdtwBMrAPD5TwSrX9VyOF X-Google-Smtp-Source: ABdhPJwZxwYCnECxODTJ/9nuZCrNy5rV9eSgdYug31zBQrMyp1ZeoCWkILHsj+k2HTdFrdZXAJnPOw== X-Received: by 2002:a17:90a:9414:: with SMTP id r20mr5803904pjo.222.1611951032965; Fri, 29 Jan 2021 12:10:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 01/24] tcg/tci: Drop L and S constraints Date: Fri, 29 Jan 2021 10:10:05 -1000 Message-Id: <20210129201028.787853-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129201028.787853-1-richard.henderson@linaro.org> References: <20210129201028.787853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These are identical to the 'r' constraint. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 15981265db..9c45f5f88f 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -46,11 +46,11 @@ # define R64 "r" #endif #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS -# define L "L", "L" -# define S "S", "S" +# define L "r", "r" +# define S "r", "r" #else -# define L "L" -# define S "S" +# define L "r" +# define S "r" #endif =20 /* TODO: documentation. */ @@ -390,8 +390,6 @@ static const char *target_parse_constraint(TCGArgConstr= aint *ct, { switch (*ct_str++) { case 'r': - case 'L': /* qemu_ld constraint */ - case 'S': /* qemu_st constraint */ ct->regs =3D BIT(TCG_TARGET_NB_REGS) - 1; break; default: --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611951127; cv=none; d=zohomail.com; s=zohoarc; b=dS0v5jpMV7mpjE5hsHMRojx3WEPnhitAths25j4zVYN6fMxOCG8hXd8q7wv+hnyIxRR6mrlQE6A/jIrSVRRVqkk3IXauw8Q91umXXQp6CUGdKl15tMOQCrrfi3gmbInBtsdbb2B/v0QkpLO7Yfwx+GTiCWe04ortHyhf1vyDbTs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611951127; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BJ7K2GgfBNlUMSrPcIxO0xnk9cq6USQK317WPPixCjk=; b=nyVyNqnTkk/cCLts6UxTJOF+bdc0jo1t+bJi/RJeJK+tw/OcIMGSORRtTu4UPis9EimXMj/iLYRGZaW8iFayxbsjJOidmQ6O6sdaqf3M0eZCG1WweDysumdbxT3atwlSHKJidbeStOWb4/Z/e9BMyzt6g2PqjG8qGRzN86nCiRE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611951127613811.9664722223035; Fri, 29 Jan 2021 12:12:07 -0800 (PST) Received: from localhost ([::1]:40570 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5a7h-0007ll-PH for importer@patchew.org; Fri, 29 Jan 2021 15:12:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48956) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5a6J-0005x1-Ro for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:41 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:50379) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5a6H-0007zS-AW for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:39 -0500 Received: by mail-pj1-x1036.google.com with SMTP id md11so6369264pjb.0 for ; Fri, 29 Jan 2021 12:10:36 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id d133sm9247265pfd.6.2021.01.29.12.10.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 12:10:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BJ7K2GgfBNlUMSrPcIxO0xnk9cq6USQK317WPPixCjk=; b=gqRycE24vsHPc8BudlMFOTAjvj6trvjqRLX1pw/gvo9wrbsYohq+mub1U9VSptr7Ru 5vmpeJ71jn72iLLphewtEqRFZcr7rtg4qlC76DbgamgtORNknWMZdVvrdPLNuP34kUSm WrVXmU3whZ+DjJlq3/qw7wFteN2EqyKBWXsmKoQFKNodAc1clegnrkuVTL1rkt0EU1+S wO8afnH7bEdjTES8HXi83ubd9C9B5cUkhogtjg3VXq8ejfVfTxNQ9v2C2qPHkOu4MOTN giCZnw2b6cLWL8Ingn+/yID9XSqr+J+hwU3YvoGOBmYXx81DdBArBwCeB4Pr2qqbm+D4 naPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BJ7K2GgfBNlUMSrPcIxO0xnk9cq6USQK317WPPixCjk=; b=gHHTX+mVUS8L4lIOkZDRWxhjUkjBniMF16KCU+DliwbtOuntODxdKeiRKYf7vZAnKq nsJixkV/Zle4LHfLXyfUqAfn2u/4kP0Td6Muxf/LPJAeeA+CrWJuOVsoOFeUnneQZtZN 6j+HhiblAWnHo3/uGQh0XBUW7p2oAEv01Lw2Jgb68fdlmE57vLcQPhgOAiXiqM7He8CF RIlSPJXfeQQQelPYtXwFAw/G0Ita6uMxGOyNdDZdMqA7a1lueGlK00087wFM1iof6PPE amTz/wQ3Auuh79jCYh4Qf7r3o6dEnn3hwxtiI7/Itutx36a26gjKI7IcX0vz0xOP/sgH 9t8Q== X-Gm-Message-State: AOAM531SAcPDP8xYSNtHSXI2YwNVEJ7+LgnpQyn6xgHQrs+ITedBkWrp I7ThbWUvMmK2S5nom5F6HkEX9PkRjRh1jPOx X-Google-Smtp-Source: ABdhPJwPurwAywGQeXKktXnCoC8WGWD5jEEeHPvxusQNqPl4h/cGhi5/6+ZeD5zH0m11rzTEx+r12w== X-Received: by 2002:a17:90a:4494:: with SMTP id t20mr6036700pjg.155.1611951035739; Fri, 29 Jan 2021 12:10:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 02/24] tcg/tci: Remove TCG_TARGET_HAS_* ifdefs Date: Fri, 29 Jan 2021 10:10:06 -1000 Message-Id: <20210129201028.787853-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129201028.787853-1-richard.henderson@linaro.org> References: <20210129201028.787853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The opcodes always exist, regardless of whether or not they are enabled. Remove the unnecessary ifdefs. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 82 ---------------------------------------- 1 file changed, 82 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 9c45f5f88f..b62e14d5ce 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -71,70 +71,42 @@ static const TCGTargetOpDef tcg_target_op_defs[] =3D { { INDEX_op_add_i32, { R, RI, RI } }, { INDEX_op_sub_i32, { R, RI, RI } }, { INDEX_op_mul_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_div_i32 { INDEX_op_div_i32, { R, R, R } }, { INDEX_op_divu_i32, { R, R, R } }, { INDEX_op_rem_i32, { R, R, R } }, { INDEX_op_remu_i32, { R, R, R } }, -#elif TCG_TARGET_HAS_div2_i32 - { INDEX_op_div2_i32, { R, R, "0", "1", R } }, - { INDEX_op_divu2_i32, { R, R, "0", "1", R } }, -#endif /* TODO: Does R, RI, RI result in faster code than R, R, RI? If both operands are constants, we can optimize. */ { INDEX_op_and_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_andc_i32 { INDEX_op_andc_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_eqv_i32 { INDEX_op_eqv_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nand_i32 { INDEX_op_nand_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nor_i32 { INDEX_op_nor_i32, { R, RI, RI } }, -#endif { INDEX_op_or_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_orc_i32 { INDEX_op_orc_i32, { R, RI, RI } }, -#endif { INDEX_op_xor_i32, { R, RI, RI } }, { INDEX_op_shl_i32, { R, RI, RI } }, { INDEX_op_shr_i32, { R, RI, RI } }, { INDEX_op_sar_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_rot_i32 { INDEX_op_rotl_i32, { R, RI, RI } }, { INDEX_op_rotr_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_deposit_i32 { INDEX_op_deposit_i32, { R, "0", R } }, -#endif =20 { INDEX_op_brcond_i32, { R, RI } }, =20 { INDEX_op_setcond_i32, { R, R, RI } }, -#if TCG_TARGET_REG_BITS =3D=3D 64 { INDEX_op_setcond_i64, { R, R, RI } }, -#endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */ { INDEX_op_add2_i32, { R, R, R, R, R, R } }, { INDEX_op_sub2_i32, { R, R, R, R, R, R } }, { INDEX_op_brcond2_i32, { R, R, RI, RI } }, { INDEX_op_mulu2_i32, { R, R, R, R } }, { INDEX_op_setcond2_i32, { R, R, R, RI, RI } }, -#endif =20 -#if TCG_TARGET_HAS_not_i32 { INDEX_op_not_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_neg_i32 { INDEX_op_neg_i32, { R, R } }, -#endif =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 { INDEX_op_ld8u_i64, { R, R } }, { INDEX_op_ld8s_i64, { R, R } }, { INDEX_op_ld16u_i64, { R, R } }, @@ -151,81 +123,39 @@ static const TCGTargetOpDef tcg_target_op_defs[] =3D { { INDEX_op_add_i64, { R, RI, RI } }, { INDEX_op_sub_i64, { R, RI, RI } }, { INDEX_op_mul_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_div_i64 { INDEX_op_div_i64, { R, R, R } }, { INDEX_op_divu_i64, { R, R, R } }, { INDEX_op_rem_i64, { R, R, R } }, { INDEX_op_remu_i64, { R, R, R } }, -#elif TCG_TARGET_HAS_div2_i64 - { INDEX_op_div2_i64, { R, R, "0", "1", R } }, - { INDEX_op_divu2_i64, { R, R, "0", "1", R } }, -#endif { INDEX_op_and_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_andc_i64 { INDEX_op_andc_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_eqv_i64 { INDEX_op_eqv_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nand_i64 { INDEX_op_nand_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nor_i64 { INDEX_op_nor_i64, { R, RI, RI } }, -#endif { INDEX_op_or_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_orc_i64 { INDEX_op_orc_i64, { R, RI, RI } }, -#endif { INDEX_op_xor_i64, { R, RI, RI } }, { INDEX_op_shl_i64, { R, RI, RI } }, { INDEX_op_shr_i64, { R, RI, RI } }, { INDEX_op_sar_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_rot_i64 { INDEX_op_rotl_i64, { R, RI, RI } }, { INDEX_op_rotr_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_deposit_i64 { INDEX_op_deposit_i64, { R, "0", R } }, -#endif { INDEX_op_brcond_i64, { R, RI } }, =20 -#if TCG_TARGET_HAS_ext8s_i64 { INDEX_op_ext8s_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16s_i64 { INDEX_op_ext16s_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext32s_i64 { INDEX_op_ext32s_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext8u_i64 { INDEX_op_ext8u_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16u_i64 { INDEX_op_ext16u_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext32u_i64 { INDEX_op_ext32u_i64, { R, R } }, -#endif { INDEX_op_ext_i32_i64, { R, R } }, { INDEX_op_extu_i32_i64, { R, R } }, -#if TCG_TARGET_HAS_bswap16_i64 { INDEX_op_bswap16_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_bswap32_i64 { INDEX_op_bswap32_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_bswap64_i64 { INDEX_op_bswap64_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_not_i64 { INDEX_op_not_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_neg_i64 { INDEX_op_neg_i64, { R, R } }, -#endif -#endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ =20 { INDEX_op_qemu_ld_i32, { R, L } }, { INDEX_op_qemu_ld_i64, { R64, L } }, @@ -233,25 +163,13 @@ static const TCGTargetOpDef tcg_target_op_defs[] =3D { { INDEX_op_qemu_st_i32, { R, S } }, { INDEX_op_qemu_st_i64, { R64, S } }, =20 -#if TCG_TARGET_HAS_ext8s_i32 { INDEX_op_ext8s_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16s_i32 { INDEX_op_ext16s_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext8u_i32 { INDEX_op_ext8u_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16u_i32 { INDEX_op_ext16u_i32, { R, R } }, -#endif =20 -#if TCG_TARGET_HAS_bswap16_i32 { INDEX_op_bswap16_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_bswap32_i32 { INDEX_op_bswap32_i32, { R, R } }, -#endif =20 { INDEX_op_mb, { } }, { -1 }, --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id d133sm9247265pfd.6.2021.01.29.12.10.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 12:10:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=iOoIlpAzDYGxlsWXgbu6MecCT7nTlKWQqjPlQrCBgNU=; b=Vl5xMfqIIPPqj5495hG2ah2r9OX5PYkkHHBlmNE1a1aQleWt2W6lfz0Qd1jB8A7ExE fviF2MeH7Ce7mH1+MfMcZv/sQphLPBKgyXUfVM1jaZCCRG3Aei5LS1eK35Xp+CquR92q hTXI1uBA1VSkAEW1rEFllrRPwXgYeqbPedXu0N9UB1Fzk5N/V16kGw/1NOOcd4IPLCkF ED3y0OP0nH0DyPIeh59cbShCMtWhv+nfytaY5CbRKEfwsQdL0BDrnvqIB/dySTL5UbkB ZEL5Dzviwbx1ESGFNxStIuG97GL4oHT4+qdNuT0RrT6ZFoUIqv7Vl+HGQES1KBWoM6rb WslA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iOoIlpAzDYGxlsWXgbu6MecCT7nTlKWQqjPlQrCBgNU=; b=tVcKe1xhZE6gY4aRv0zMJUl3LZ/9Z4G2RSlAc5UspfpcUADU9Cqdoe6ZY+C7KR4KjW 02mhQvKx4B3SoWEl9H5tlM1W3IRM6fygOWvRNcs8t/HX7ZgXUUhVp+kxBtizpbifHokU JfcPJdGQlBqv6/dBhEhawfVAupkdyxtZq24YndDixG0+jtZhewS/4Z79KgqC/p+WYe8s M1QILboHrNBF3UUrglMJYftPB+qpa7XIS4vpdHGBKDlIqmD3v+2c3cstArYGkwduPnWm GAbDgOnqfanm5U6EHrfXcJcq2ifNMyaCrV6qeFK+73lIHxQG4z0xD79DrvqMd2OtHghS SprQ== X-Gm-Message-State: AOAM531QmklWGf7GUNbX2CiXUIPaHSB5gE14TIHnE1+GbhlF+UUJmfOn MD0cmb4E2evPlW+K7cbs8WW4fnc8FYptR60v X-Google-Smtp-Source: ABdhPJyDVSoxs7fOmj6swA1gw05dBZh1tv58FplB9ETb+kH5XlgwNp0FTEMUZpmVa6d5/kn2GKoWeg== X-Received: by 2002:a63:1e12:: with SMTP id e18mr6048158pge.173.1611951037069; Fri, 29 Jan 2021 12:10:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 03/24] tcg/i386: Move constraint type check to tcg_target_const_match Date: Fri, 29 Jan 2021 10:10:07 -1000 Message-Id: <20210129201028.787853-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129201028.787853-1-richard.henderson@linaro.org> References: <20210129201028.787853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Rather than check the type when filling in the constraint, check it when matching the constant. This removes the only use of the type argument to target_parse_constraint. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/i386/tcg-target.c.inc | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 050f3cb0b1..540debdf34 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -263,13 +263,13 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, break; =20 case 'e': - ct->ct |=3D (type =3D=3D TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONS= T_S32); + ct->ct |=3D TCG_CT_CONST_S32; break; case 'Z': - ct->ct |=3D (type =3D=3D TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONS= T_U32); + ct->ct |=3D TCG_CT_CONST_U32; break; case 'I': - ct->ct |=3D (type =3D=3D TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONS= T_I32); + ct->ct |=3D TCG_CT_CONST_I32; break; =20 default: @@ -286,14 +286,20 @@ static inline int tcg_target_const_match(tcg_target_l= ong val, TCGType type, if (ct & TCG_CT_CONST) { return 1; } - if ((ct & TCG_CT_CONST_S32) && val =3D=3D (int32_t)val) { - return 1; - } - if ((ct & TCG_CT_CONST_U32) && val =3D=3D (uint32_t)val) { - return 1; - } - if ((ct & TCG_CT_CONST_I32) && ~val =3D=3D (int32_t)~val) { - return 1; + if (type =3D=3D TCG_TYPE_I32) { + if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | TCG_CT_CONST_I32))= { + return 1; + } + } else { + if ((ct & TCG_CT_CONST_S32) && val =3D=3D (int32_t)val) { + return 1; + } + if ((ct & TCG_CT_CONST_U32) && val =3D=3D (uint32_t)val) { + return 1; + } + if ((ct & TCG_CT_CONST_I32) && ~val =3D=3D (int32_t)~val) { + return 1; + } } if ((ct & TCG_CT_CONST_WSZ) && val =3D=3D (type =3D=3D TCG_TYPE_I32 ? = 32 : 64)) { return 1; --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611951224; cv=none; d=zohomail.com; s=zohoarc; b=EQKUk4Fp9LX1HfiNDfby77lfILDDnxRbGOtlKJ80DpcIp60sHDubU6xiBfH/tJIFbqydr3uwpNTLdjuDxl607MAA81uAW2fyIIzYRL6bn2qtH4s6GjZinQRm5FBt67EcjXmQPzq7/r7GpE4a2qJDS0uWLwBS5Yic70FspcaNcbI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611951224; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HBBO7QZPtUwrm35LTuZ36OrNAjYmk4o8xxojo1oe3Y4=; b=FV8kq6k/FzIyg28lJ7VQNCdRe8R7w+eA5ygUpRXcw9aXUU9M0lj41BUPDnpHKBzqoNF0h9xry+BBlY1XLGeCYa6Bau4kBKusN1fWvcRBaxq4TuxrsjknPx9FslvqlZTpXY9u6xyspSFtVd3e5kDDi5ccTSAl+EzUOzYZuiP0iWA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611951224958120.96515161424861; Fri, 29 Jan 2021 12:13:44 -0800 (PST) Received: from localhost ([::1]:43986 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5a9E-0000pR-MZ for importer@patchew.org; Fri, 29 Jan 2021 15:13:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49008) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5a6O-000610-2v for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:44 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:37790) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5a6J-00080S-SS for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:43 -0500 Received: by mail-pl1-x62f.google.com with SMTP id q2so5896071plk.4 for ; Fri, 29 Jan 2021 12:10:39 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id d133sm9247265pfd.6.2021.01.29.12.10.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 12:10:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=HBBO7QZPtUwrm35LTuZ36OrNAjYmk4o8xxojo1oe3Y4=; b=piCzEltPqcsnGfT1rPl6QIF98ecXYtaSnEbFEpRsPdiwGMh47BYyf95/2aTGOOpjc7 S4ujmVdKpiBPl/CV4ocuNgF3dxqCNCrkhwT0VfQdwrGwQRk4yRSlPuQlSvWCIMW42glR WVWqYYok/eqMs1aLKuCfVPVYjVbGL5dUMc6/aHcUIKIEynDi6zvHNnHVxf2ITHdKE7NB EJQ78391VAnpYUYyLlW2xQCMva/h2r4xx2b4INNjOhgRPe5iS8cvR0vDkVeE2KmWUbnG GCZSE/f+/rUqtjuR54i0fAvbX9eASZ2nUE9EhfIN8QVi/iIXLvmSzi10CUwEE+jXgFsc 2+ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HBBO7QZPtUwrm35LTuZ36OrNAjYmk4o8xxojo1oe3Y4=; b=JuowPQ67QsygNGH+YmlEn3Jg/7jGLaWTdgMWrjngl1F7ppmqwckYM3qqdojRjAQt0L /aHEO2GBb9Fh0Um84qRxT2O4+zyafIezBzpgLQMk7IRo0P1rJE6P2aeDGezNogyy/dVS fAgYPY2kUI5bBpEAybxIssINt0EN9VECiAxuXb/rebrPvEuv8MRC5bRXzV3fFGFxd+WR WjwJXq3ICuq2VGMoOi9n/tS6FhlBJdG5ngpwNdrAkxdiJXfl85cYq+mQQwe/zmPkmR1I SernQJR/wV2ssz/3q6yAf5unEcMWRTTuzQRQVzeMa3IawGlk5vyJZFj7gwAKRfaGsYoO gFfA== X-Gm-Message-State: AOAM532xhX3Z83dIyZJ6GjemEYcXOlXbOmzp70rDtQXh9CF2i3eexPaC fHGeshsqeqPgajvxmTvtJFQy0glD2kJCK+r3 X-Google-Smtp-Source: ABdhPJy8kjrpub+iqbXIYBS9O3Opk7gFWxoHZdFLbHguI1KHcNnXVvZcZXpwWp+hmYybL9/pgmPFhA== X-Received: by 2002:a17:90a:4504:: with SMTP id u4mr6141101pjg.218.1611951038551; Fri, 29 Jan 2021 12:10:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 04/24] tcg/i386: Tidy register constraint definitions Date: Fri, 29 Jan 2021 10:10:08 -1000 Message-Id: <20210129201028.787853-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129201028.787853-1-richard.henderson@linaro.org> References: <20210129201028.787853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Create symbolic constants for all low-byte-addressable and second-byte-addressable registers. Create a symbol for the registers that need reserving for softmmu. There is no functional change for 's', as this letter is only used for i386. The BYTEL name is correct for the action we wish from the constraint. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/i386/tcg-target.c.inc | 40 +++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 540debdf34..4feb7e2aa1 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -132,6 +132,22 @@ static const int tcg_target_call_oarg_regs[] =3D { # define TCG_REG_L1 TCG_REG_EDX #endif =20 +#define ALL_BYTEH_REGS 0x0000000fu +#if TCG_TARGET_REG_BITS =3D=3D 64 +# define ALL_GENERAL_REGS 0x0000ffffu +# define ALL_VECTOR_REGS 0xffff0000u +# define ALL_BYTEL_REGS ALL_GENERAL_REGS +#else +# define ALL_GENERAL_REGS 0x000000ffu +# define ALL_VECTOR_REGS 0x00ff0000u +# define ALL_BYTEL_REGS ALL_BYTEH_REGS +#endif +#ifdef CONFIG_SOFTMMU +# define SOFTMMU_RESERVE_REGS ((1 << TCG_REG_L0) | (1 << TCG_REG_L1)) +#else +# define SOFTMMU_RESERVE_REGS 0 +#endif + /* The host compiler should supply to enable runtime features detection, as we're not going to go so far as our own inline assembly. If not available, default values will be assumed. */ @@ -193,14 +209,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, return true; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -#define ALL_GENERAL_REGS 0x0000ffffu -#define ALL_VECTOR_REGS 0xffff0000u -#else -#define ALL_GENERAL_REGS 0x000000ffu -#define ALL_VECTOR_REGS 0x00ff0000u -#endif - /* parse target specific constraints */ static const char *target_parse_constraint(TCGArgConstraint *ct, const char *ct_str, TCGType typ= e) @@ -226,11 +234,11 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, break; case 'q': /* A register that can be used as a byte operand. */ - ct->regs =3D TCG_TARGET_REG_BITS =3D=3D 64 ? 0xffff : 0xf; + ct->regs |=3D ALL_BYTEL_REGS; break; case 'Q': /* A register with an addressable second byte (e.g. %ah). */ - ct->regs =3D 0xf; + ct->regs |=3D ALL_BYTEH_REGS; break; case 'r': /* A general register. */ @@ -247,19 +255,11 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, =20 case 'L': /* qemu_ld/st data+address constraint */ - ct->regs =3D TCG_TARGET_REG_BITS =3D=3D 64 ? 0xffff : 0xff; -#ifdef CONFIG_SOFTMMU - tcg_regset_reset_reg(ct->regs, TCG_REG_L0); - tcg_regset_reset_reg(ct->regs, TCG_REG_L1); -#endif + ct->regs |=3D ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS; break; case 's': /* qemu_st8_i32 data constraint */ - ct->regs =3D 0xf; -#ifdef CONFIG_SOFTMMU - tcg_regset_reset_reg(ct->regs, TCG_REG_L0); - tcg_regset_reset_reg(ct->regs, TCG_REG_L1); -#endif + ct->regs |=3D ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS; break; =20 case 'e': --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611951346; cv=none; d=zohomail.com; s=zohoarc; b=SziYTIjN1/YIU1cPMMpBZ9Z1u4Y5y0CgqydoDVX1KBr68frUpYKe/pSXi5pb/oCWnM/J2Do/Ft00WbDQWe1R6PDyFroaZ8eltLTmxXQe17sqhX/W3kzuEVny4FCSe05190VItqH/x+RvULEp6ELgGJFSUKrceuTP9uCcBhTVIXU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611951346; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OyWA4EsPCVawv9oYLu1X0a+rhhmIgXsXz2Cg+CqfoCA=; b=lo/pEVUkVpdMOUrY0R29yGCOReEjCvfqQCPJqMRsDc6at2nbarHYUueHQnleJe9le6sAfqXcBAMAxn02rCKXUuJBFmsI72yBEJn08woWG+oldiBHjMKbNjou0ADxKnNXvZyCoKY/UNd/3Y3xD+QY14PsU7PAax0rlluF/8DgY44= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611951346192982.1178287544269; Fri, 29 Jan 2021 12:15:46 -0800 (PST) Received: from localhost ([::1]:49348 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5aBF-000371-2R for importer@patchew.org; Fri, 29 Jan 2021 15:15:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49016) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5a6O-00061n-HI for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:44 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:38518) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5a6L-00080c-LW for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:44 -0500 Received: by mail-pj1-x1035.google.com with SMTP id l18so6955355pji.3 for ; Fri, 29 Jan 2021 12:10:41 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id d133sm9247265pfd.6.2021.01.29.12.10.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 12:10:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OyWA4EsPCVawv9oYLu1X0a+rhhmIgXsXz2Cg+CqfoCA=; b=gzQHmA585Np1v1BdauhVLjeEuf/LbGnYDD+1LSbaxUjMDfq3fmOrbBZSiwIxqsxeUX PvoU81N/JVWtMMvqddqxd+97btEPTu5lDgBPq1haqLrqwrEn7cyggfl3RKn2VslS9xCn 11xKgXnGmGhQIt56/y64uPcUXa8iOZfCZFtVl64yYjgWZj64N4hfxH1fUd/YUocL/uJJ vTF9yad4viGEl50jvdJAp03i75wPLzVN3JPjQHm4iE1QrW+8SuDVz9vwMjfaSl4gcui+ jVSQ4/WaldyP/Bv9wXQjWRWjKEt1GdzJ3ZY53yA07XB1QyD51i7AxatpJMg4Mk4iN6+n ZSAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OyWA4EsPCVawv9oYLu1X0a+rhhmIgXsXz2Cg+CqfoCA=; b=szuOLIkF3q/pCNGvRk7JJxpDgrogfVSe9D3zsI19QjArrdxqGdVucNCPO2nyf4Z4sx sYgwrXNdR9p1kDYaGbKYhfoTo8kzgR42Ol5HVLHk2cWu8nXzebQ1LRa2TjbMXQDRnBzG vJgN5pIVWgrL6Zu8KeVvdMdbcd5BeVBm7T08PwDIngpMkDzfB0jLlbLe2ktsa944QRZf tgCDNQV3dErU5n98E+cxbbuyWzHTvM84Udi1+kLwiPRAwE1kuoF0P2HIpmief7lMe439 QwUrDWGsk6D//eumWclgxvsVTNet6UARY7KH3HULCATVoBdddqT6Iz2qNb2d+CFoRCXk KoIQ== X-Gm-Message-State: AOAM530YZlMrQEngMgKJ4FnVMIYjdFtAm5Dm3t+vzfEGz5REvXlZpmp7 +J72N3it4v+efgXPzCH/MVI+yJEeNs3WzPwN X-Google-Smtp-Source: ABdhPJyJP7EV49IvXZagCgKHSAZZ+4p5AXp13Hv0Xeq9j8alWCznkCojhM1o78u1Im6eoIPS6xOB/w== X-Received: by 2002:a17:90a:6c66:: with SMTP id x93mr5716850pjj.223.1611951040159; Fri, 29 Jan 2021 12:10:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 05/24] tcg/i386: Split out target constraints to tcg-target-con-str.h Date: Fri, 29 Jan 2021 10:10:09 -1000 Message-Id: <20210129201028.787853-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129201028.787853-1-richard.henderson@linaro.org> References: <20210129201028.787853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This eliminates the target-specific function target_parse_constraint and folds it into the single caller, process_op_defs. Since this is done directly into the switch statement, duplicates are compilation errors rather than silently ignored at runtime. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/i386/tcg-target-con-str.h | 33 +++++++++++++++++ tcg/i386/tcg-target.h | 1 + tcg/tcg.c | 33 ++++++++++++++--- tcg/i386/tcg-target.c.inc | 69 ----------------------------------- 4 files changed, 62 insertions(+), 74 deletions(-) create mode 100644 tcg/i386/tcg-target-con-str.h diff --git a/tcg/i386/tcg-target-con-str.h b/tcg/i386/tcg-target-con-str.h new file mode 100644 index 0000000000..24e6bcb80d --- /dev/null +++ b/tcg/i386/tcg-target-con-str.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define i386 target-specific operand constraints. + * Copyright (c) 2021 Linaro + * + */ + +/* + * Define constraint letters for register sets: + * REGS(letter, register_mask) + */ +REGS('a', 1u << TCG_REG_EAX) +REGS('b', 1u << TCG_REG_EBX) +REGS('c', 1u << TCG_REG_ECX) +REGS('d', 1u << TCG_REG_EDX) +REGS('S', 1u << TCG_REG_ESI) +REGS('D', 1u << TCG_REG_EDI) + +REGS('r', ALL_GENERAL_REGS) +REGS('x', ALL_VECTOR_REGS) +REGS('q', ALL_BYTEL_REGS) /* regs that can be used as a byte operand */ +REGS('Q', ALL_BYTEH_REGS) /* regs with a second byte (e.g. %ah) */ +REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_ld/st */ +REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_st8_i32 data = */ + +/* + * Define constraint letters for constants: + * CONST(letter, TCG_CT_CONST_* bit set) + */ +CONST('e', TCG_CT_CONST_S32) +CONST('I', TCG_CT_CONST_I32) +CONST('W', TCG_CT_CONST_WSZ) +CONST('Z', TCG_CT_CONST_U32) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b693d3692d..77693e13ea 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -235,5 +235,6 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CON_STR_H =20 #endif diff --git a/tcg/tcg.c b/tcg/tcg.c index 9e1b0d73c7..8cfa28ed84 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -103,8 +103,10 @@ static void tcg_register_jit_int(const void *buf, size= _t size, __attribute__((unused)); =20 /* Forward declarations for functions declared and used in tcg-target.c.in= c. */ +#ifndef TCG_TARGET_CON_STR_H static const char *target_parse_constraint(TCGArgConstraint *ct, const char *ct_str, TCGType typ= e); +#endif static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg= 1, intptr_t arg2); static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); @@ -2415,7 +2417,6 @@ static void process_op_defs(TCGContext *s) for (op =3D 0; op < NB_OPS; op++) { TCGOpDef *def =3D &tcg_op_defs[op]; const TCGTargetOpDef *tdefs; - TCGType type; int i, nb_args; =20 if (def->flags & TCG_OPF_NOT_PRESENT) { @@ -2431,7 +2432,6 @@ static void process_op_defs(TCGContext *s) /* Missing TCGTargetOpDef entry. */ tcg_debug_assert(tdefs !=3D NULL); =20 - type =3D (def->flags & TCG_OPF_64BIT ? TCG_TYPE_I64 : TCG_TYPE_I32= ); for (i =3D 0; i < nb_args; i++) { const char *ct_str =3D tdefs->args_ct_str[i]; /* Incomplete TCGTargetOpDef entry. */ @@ -2463,11 +2463,34 @@ static void process_op_defs(TCGContext *s) def->args_ct[i].ct |=3D TCG_CT_CONST; ct_str++; break; + +#ifdef TCG_TARGET_CON_STR_H + /* Include all of the target-specific constraints. */ + +#undef CONST +#define CONST(CASE, MASK) \ + case CASE: def->args_ct[i].ct |=3D MASK; ct_str++; break; +#define REGS(CASE, MASK) \ + case CASE: def->args_ct[i].regs |=3D MASK; ct_str++; break; + +#include "tcg-target-con-str.h" + +#undef REGS +#undef CONST default: - ct_str =3D target_parse_constraint(&def->args_ct[i], - ct_str, type); /* Typo in TCGTargetOpDef constraint. */ - tcg_debug_assert(ct_str !=3D NULL); + g_assert_not_reached(); +#else + default: + { + TCGType type =3D (def->flags & TCG_OPF_64BIT + ? TCG_TYPE_I64 : TCG_TYPE_I32); + ct_str =3D target_parse_constraint(&def->args_ct[i= ], + ct_str, type); + /* Typo in TCGTargetOpDef constraint. */ + tcg_debug_assert(ct_str !=3D NULL); + } +#endif } } } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 4feb7e2aa1..d3cf97748a 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -209,75 +209,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, return true; } =20 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch(*ct_str++) { - case 'a': - tcg_regset_set_reg(ct->regs, TCG_REG_EAX); - break; - case 'b': - tcg_regset_set_reg(ct->regs, TCG_REG_EBX); - break; - case 'c': - tcg_regset_set_reg(ct->regs, TCG_REG_ECX); - break; - case 'd': - tcg_regset_set_reg(ct->regs, TCG_REG_EDX); - break; - case 'S': - tcg_regset_set_reg(ct->regs, TCG_REG_ESI); - break; - case 'D': - tcg_regset_set_reg(ct->regs, TCG_REG_EDI); - break; - case 'q': - /* A register that can be used as a byte operand. */ - ct->regs |=3D ALL_BYTEL_REGS; - break; - case 'Q': - /* A register with an addressable second byte (e.g. %ah). */ - ct->regs |=3D ALL_BYTEH_REGS; - break; - case 'r': - /* A general register. */ - ct->regs |=3D ALL_GENERAL_REGS; - break; - case 'W': - /* With TZCNT/LZCNT, we can have operand-size as an input. */ - ct->ct |=3D TCG_CT_CONST_WSZ; - break; - case 'x': - /* A vector register. */ - ct->regs |=3D ALL_VECTOR_REGS; - break; - - case 'L': - /* qemu_ld/st data+address constraint */ - ct->regs |=3D ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS; - break; - case 's': - /* qemu_st8_i32 data constraint */ - ct->regs |=3D ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS; - break; - - case 'e': - ct->ct |=3D TCG_CT_CONST_S32; - break; - case 'Z': - ct->ct |=3D TCG_CT_CONST_U32; - break; - case 'I': - ct->ct |=3D TCG_CT_CONST_I32; - break; - - default: - return NULL; - } - return ct_str; -} - /* test if a constant matches the constraint */ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611951344; cv=none; d=zohomail.com; s=zohoarc; b=Wcau6rMX3siherc7Br1QIh4sm/7M5ESX/7WnHeVoHvbvBODS+BafoZIVgux3u2sseZDB5fWwYgLr7AKlTJbmL/fjvsWDyhuoezSj8BbykEYJUvwHYcB0bhao5kjn+AOb44wwoAPYz4xGYdvEhMd5UtdamnAIYVtzmXnj00izkn4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611951344; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rEiNCKP9SRGBYuPOUkrJxj3TyPoHI75PCJnqDanFink=; b=TJFivAmnbertp4rHMdC55SW5gJr4jH+vxwZGmpN+kCZx5Uw6iVngm37Jc0NHWxV4i7DsHHALdmeq6+hfsyir3vfvoC4rYbFNLVQQOnF+Vv5zUl56mU5EsAqsfrWGI9c1ayfbpvex7v60ATWj4n/ue1xYk9WD0O5Po+YWI0pOS+w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611951344336870.6921561257685; Fri, 29 Jan 2021 12:15:44 -0800 (PST) Received: from localhost ([::1]:49262 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5aBD-00034u-AL for importer@patchew.org; Fri, 29 Jan 2021 15:15:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49024) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5a6P-00063X-8Y for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:45 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:53110) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5a6N-00081e-3x for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:44 -0500 Received: by mail-pj1-x102c.google.com with SMTP id kx7so6371517pjb.2 for ; Fri, 29 Jan 2021 12:10:42 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id d133sm9247265pfd.6.2021.01.29.12.10.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 12:10:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rEiNCKP9SRGBYuPOUkrJxj3TyPoHI75PCJnqDanFink=; b=KJME9SDFSYy/6nmMPcpQjIbmWLgQDFMNX61Mt0OP8ZwIWacgZfuhgzaoo0U3aB5sZH Nde3GALh0tUitxtFOheig4CYaWsi7T8apMNf54/19/Ph9e/UDzNiG7rX6JyziCpvWu0I E382h14Cw+NjFsGeQgQ6GKsnRRSQJHJB/E2ebJ4DVOdjk18zv016VdJiH9tWKXqk6qzl +2m2zQCUiWBmFynCyr1995ASSujd5hDoMsc8gMUUnbuTGViJgsAMDMGS9OAFDyJX1BVi Y16A8dt14XLnJRZd33Qqj7+uhidfvqqmYLKAbZnCRA+AkhRUv9ch8bSw0sn8NlSXin6E 91FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rEiNCKP9SRGBYuPOUkrJxj3TyPoHI75PCJnqDanFink=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-con-str.h | 22 +++++++++++ tcg/arm/tcg-target.h | 1 + tcg/arm/tcg-target.c.inc | 74 +++++++++--------------------------- 3 files changed, 41 insertions(+), 56 deletions(-) create mode 100644 tcg/arm/tcg-target-con-str.h diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h new file mode 100644 index 0000000000..a0ab7747db --- /dev/null +++ b/tcg/arm/tcg-target-con-str.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define Arm target-specific operand constraints. + * Copyright (c) 2021 Linaro + */ + +/* + * Define constraint letters for register sets: + * REGS(letter, register_mask) + */ +REGS('r', ALL_GENERAL_REGS) +REGS('l', ALL_QLOAD_REGS) +REGS('s', ALL_QSTORE_REGS) + +/* + * Define constraint letters for constants: + * CONST(letter, TCG_CT_CONST_* bit set) + */ +CONST('I', TCG_CT_CONST_ARM) +CONST('K', TCG_CT_CONST_INV) +CONST('N', TCG_CT_CONST_NEG) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 8d1fee6327..16336cd545 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -142,5 +142,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CON_STR_H =20 #endif diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index c2b26b3c45..bbd41d2491 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -237,65 +237,27 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, #define TCG_CT_CONST_NEG 0x400 #define TCG_CT_CONST_ZERO 0x800 =20 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch (*ct_str++) { - case 'I': - ct->ct |=3D TCG_CT_CONST_ARM; - break; - case 'K': - ct->ct |=3D TCG_CT_CONST_INV; - break; - case 'N': /* The gcc constraint letter is L, already used here. */ - ct->ct |=3D TCG_CT_CONST_NEG; - break; - case 'Z': - ct->ct |=3D TCG_CT_CONST_ZERO; - break; +#define ALL_GENERAL_REGS 0xffffu =20 - case 'r': - ct->regs =3D 0xffff; - break; - - /* qemu_ld address */ - case 'l': - ct->regs =3D 0xffff; +/* + * r0-r2 will be overwritten when reading the tlb entry (softmmu only) + * and r0-r1 doing the byte swapping, so don't use these. + * r3 is removed for softmmu to avoid clashes with helper arguments. + */ #ifdef CONFIG_SOFTMMU - /* r0-r2,lr will be overwritten when reading the tlb entry, - so don't use these. */ - tcg_regset_reset_reg(ct->regs, TCG_REG_R0); - tcg_regset_reset_reg(ct->regs, TCG_REG_R1); - tcg_regset_reset_reg(ct->regs, TCG_REG_R2); - tcg_regset_reset_reg(ct->regs, TCG_REG_R3); - tcg_regset_reset_reg(ct->regs, TCG_REG_R14); +#define ALL_QLOAD_REGS \ + (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \ + (1 << TCG_REG_R2) | (1 << TCG_REG_R3) | \ + (1 << TCG_REG_R14))) +#define ALL_QSTORE_REGS \ + (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \ + (1 << TCG_REG_R2) | (1 << TCG_REG_R14) | \ + ((TARGET_LONG_BITS =3D=3D 64) << TCG_REG_R3))) +#else +#define ALL_QLOAD_REGS ALL_GENERAL_REGS +#define ALL_QSTORE_REGS \ + (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1))) #endif - break; - - /* qemu_st address & data */ - case 's': - ct->regs =3D 0xffff; - /* r0-r2 will be overwritten when reading the tlb entry (softmmu o= nly) - and r0-r1 doing the byte swapping, so don't use these. */ - tcg_regset_reset_reg(ct->regs, TCG_REG_R0); - tcg_regset_reset_reg(ct->regs, TCG_REG_R1); -#if defined(CONFIG_SOFTMMU) - /* Avoid clashes with registers being used for helper args */ - tcg_regset_reset_reg(ct->regs, TCG_REG_R2); -#if TARGET_LONG_BITS =3D=3D 64 - /* Avoid clashes with registers being used for helper args */ - tcg_regset_reset_reg(ct->regs, TCG_REG_R3); -#endif - tcg_regset_reset_reg(ct->regs, TCG_REG_R14); -#endif - break; - - default: - return NULL; - } - return ct_str; -} =20 static inline uint32_t rotl(uint32_t val, int n) { --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-str.h | 24 +++++++++++++++ tcg/aarch64/tcg-target.h | 1 + tcg/aarch64/tcg-target.c.inc | 51 +++++--------------------------- 3 files changed, 33 insertions(+), 43 deletions(-) create mode 100644 tcg/aarch64/tcg-target-con-str.h diff --git a/tcg/aarch64/tcg-target-con-str.h b/tcg/aarch64/tcg-target-con-= str.h new file mode 100644 index 0000000000..00adb64594 --- /dev/null +++ b/tcg/aarch64/tcg-target-con-str.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Define AArch64 target-specific operand constraints. + * Copyright (c) 2021 Linaro + */ + +/* + * Define constraint letters for register sets: + * REGS(letter, register_mask) + */ +REGS('r', ALL_GENERAL_REGS) +REGS('l', ALL_QLDST_REGS) +REGS('w', ALL_VECTOR_REGS) + +/* + * Define constraint letters for constants: + * CONST(letter, TCG_CT_CONST_* bit set) + */ +CONST('A', TCG_CT_CONST_AIMM) +CONST('L', TCG_CT_CONST_LIMM) +CONST('M', TCG_CT_CONST_MONE) +CONST('O', TCG_CT_CONST_ORRI) +CONST('N', TCG_CT_CONST_ANDI) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 5ec30dba25..4fc20b58ec 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -155,5 +155,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CON_STR_H =20 #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 23954ec7cf..42037c98fa 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -126,51 +126,16 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, #define TCG_CT_CONST_ORRI 0x1000 #define TCG_CT_CONST_ANDI 0x2000 =20 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch (*ct_str++) { - case 'r': /* general registers */ - ct->regs |=3D 0xffffffffu; - break; - case 'w': /* advsimd registers */ - ct->regs |=3D 0xffffffff00000000ull; - break; - case 'l': /* qemu_ld / qemu_st address, data_reg */ - ct->regs =3D 0xffffffffu; +#define ALL_GENERAL_REGS 0xffffffffu +#define ALL_VECTOR_REGS 0xffffffff00000000ull + #ifdef CONFIG_SOFTMMU - /* x0 and x1 will be overwritten when reading the tlb entry, - and x2, and x3 for helper args, better to avoid using them. */ - tcg_regset_reset_reg(ct->regs, TCG_REG_X0); - tcg_regset_reset_reg(ct->regs, TCG_REG_X1); - tcg_regset_reset_reg(ct->regs, TCG_REG_X2); - tcg_regset_reset_reg(ct->regs, TCG_REG_X3); +#define ALL_QLDST_REGS \ + (ALL_GENERAL_REGS & ~((1 << TCG_REG_X0) | (1 << TCG_REG_X1) | \ + (1 << TCG_REG_X2) | (1 << TCG_REG_X3))) +#else +#define ALL_QLDST_REGS ALL_GENERAL_REGS #endif - break; - case 'A': /* Valid for arithmetic immediate (positive or negative). */ - ct->ct |=3D TCG_CT_CONST_AIMM; - break; - case 'L': /* Valid for logical immediate. */ - ct->ct |=3D TCG_CT_CONST_LIMM; - break; - case 'M': /* minus one */ - ct->ct |=3D TCG_CT_CONST_MONE; - break; - case 'O': /* vector orr/bic immediate */ - ct->ct |=3D TCG_CT_CONST_ORRI; - break; - case 'N': /* vector orr/bic immediate, inverted */ - ct->ct |=3D TCG_CT_CONST_ANDI; - break; - case 'Z': /* zero */ - ct->ct |=3D TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} =20 /* Match a constant valid for addition (12-bit, optionally shifted). */ static inline bool is_aimm(uint64_t val) --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-str.h | 30 +++++++++++++++ tcg/ppc/tcg-target.h | 1 + tcg/ppc/tcg-target.c.inc | 73 ++++++++---------------------------- 3 files changed, 46 insertions(+), 58 deletions(-) create mode 100644 tcg/ppc/tcg-target-con-str.h diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h new file mode 100644 index 0000000000..298ca20d5b --- /dev/null +++ b/tcg/ppc/tcg-target-con-str.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define PowerPC target-specific operand constraints. + * Copyright (c) 2021 Linaro + */ + +/* + * Define constraint letters for register sets: + * REGS(letter, register_mask) + */ +REGS('r', ALL_GENERAL_REGS) +REGS('v', ALL_VECTOR_REGS) +REGS('A', 1u << TCG_REG_R3) +REGS('B', 1u << TCG_REG_R4) +REGS('C', 1u << TCG_REG_R5) +REGS('D', 1u << TCG_REG_R6) +REGS('L', ALL_QLOAD_REGS) +REGS('S', ALL_QSTORE_REGS) + +/* + * Define constraint letters for constants: + * CONST(letter, TCG_CT_CONST_* bit set) + */ +CONST('I', TCG_CT_CONST_S16) +CONST('J', TCG_CT_CONST_U16) +CONST('M', TCG_CT_CONST_MONE) +CONST('T', TCG_CT_CONST_S32) +CONST('U', TCG_CT_CONST_U32) +CONST('W', TCG_CT_CONST_WSZ) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index d1339afc66..40ed4b82dd 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -185,5 +185,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CON_STR_H =20 #endif diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index cf64892295..e5aa8d2d10 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -62,6 +62,21 @@ #define TCG_CT_CONST_MONE 0x2000 #define TCG_CT_CONST_WSZ 0x4000 =20 +#define ALL_GENERAL_REGS 0xffffffffu +#define ALL_VECTOR_REGS 0xffffffff00000000ull + +#ifdef CONFIG_SOFTMMU +#define ALL_QLOAD_REGS \ + (ALL_GENERAL_REGS & \ + ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5))) +#define ALL_QSTORE_REGS \ + (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \ + (1 << TCG_REG_R5) | (1 << TCG_REG_R6))) +#else +#define ALL_QLOAD_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3)) +#define ALL_QSTORE_REGS ALL_QLOAD_REGS +#endif + TCGPowerISA have_isa; static bool have_isel; bool have_altivec; @@ -222,64 +237,6 @@ static bool reloc_pc14(tcg_insn_unit *src_rw, const tc= g_insn_unit *target) return false; } =20 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch (*ct_str++) { - case 'A': case 'B': case 'C': case 'D': - tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A'); - break; - case 'r': - ct->regs =3D 0xffffffff; - break; - case 'v': - ct->regs =3D 0xffffffff00000000ull; - break; - case 'L': /* qemu_ld constraint */ - ct->regs =3D 0xffffffff; - tcg_regset_reset_reg(ct->regs, TCG_REG_R3); -#ifdef CONFIG_SOFTMMU - tcg_regset_reset_reg(ct->regs, TCG_REG_R4); - tcg_regset_reset_reg(ct->regs, TCG_REG_R5); -#endif - break; - case 'S': /* qemu_st constraint */ - ct->regs =3D 0xffffffff; - tcg_regset_reset_reg(ct->regs, TCG_REG_R3); -#ifdef CONFIG_SOFTMMU - tcg_regset_reset_reg(ct->regs, TCG_REG_R4); - tcg_regset_reset_reg(ct->regs, TCG_REG_R5); - tcg_regset_reset_reg(ct->regs, TCG_REG_R6); -#endif - break; - case 'I': - ct->ct |=3D TCG_CT_CONST_S16; - break; - case 'J': - ct->ct |=3D TCG_CT_CONST_U16; - break; - case 'M': - ct->ct |=3D TCG_CT_CONST_MONE; - break; - case 'T': - ct->ct |=3D TCG_CT_CONST_S32; - break; - case 'U': - ct->ct |=3D TCG_CT_CONST_U32; - break; - case 'W': - ct->ct |=3D TCG_CT_CONST_WSZ; - break; - case 'Z': - ct->ct |=3D TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* test if a constant matches the constraint */ static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611951552; cv=none; d=zohomail.com; s=zohoarc; b=C6SDvT8GN5X7wwugg3Jshph8/muzGxzNReClXXNuK8Jm9C7P/Dj+ALh/hRDlSV8zWVSEcbJc6ZL0AHFjtljWbAMuRFj7ytdV1ZJ5B6URDbfIDdDjPKMjpTYc4apfqoMs8qx6J+2XfgFltGfPqav6gOCns7TFmVKDa6D749lWtFs= ARC-Message-Signature: i=1; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id d133sm9247265pfd.6.2021.01.29.12.10.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 12:10:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nSEK3p+qxylOawpMIAYivHlEQIteSEhF1LMizEZTG7s=; b=FxLQijXnggCEea9Glr6nnqx0WAzTL/2qyTBsAkXba3kBv99WXB/SE2r3pBOP4eXDnS hZGs4sxIfUN9bcroSMc/NYoRA9yV77BmAWkA56yMJ2UP660WmFAXuu6YD8+7/qLDqIDz QzuIAxFBAeOGx3Rkts+/izmPawnK4gM1echVmyX/fVml4ZFgD5zMCiD/hOxeds8CyycM QVoyQtGBo93tpnHMwHklJqeL+c0w0P4U4o0lbv9YJ3cQ3YSe0n9ccHLadCvF5z2vmIls TYYnvkw0nCNZrC28YJ0l9/SyCw8A1oeVC/aydtlvDY6hNI918AQtqISHyOAvlsF+lqYu TiHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nSEK3p+qxylOawpMIAYivHlEQIteSEhF1LMizEZTG7s=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-con-str.h | 11 +++++++++++ tcg/tci/tcg-target.h | 2 ++ tcg/tci/tcg-target.c.inc | 14 -------------- 3 files changed, 13 insertions(+), 14 deletions(-) create mode 100644 tcg/tci/tcg-target-con-str.h diff --git a/tcg/tci/tcg-target-con-str.h b/tcg/tci/tcg-target-con-str.h new file mode 100644 index 0000000000..87c0f19e9c --- /dev/null +++ b/tcg/tci/tcg-target-con-str.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define TCI target-specific operand constraints. + * Copyright (c) 2021 Linaro + */ + +/* + * Define constraint letters for register sets: + * REGS(letter, register_mask) + */ +REGS('r', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS)) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index bb784e018e..ab832aecc3 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -207,4 +207,6 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, uintptr_t jmp_rx, /* no need to flush icache explicitly */ } =20 +#define TCG_TARGET_CON_STR_H + #endif /* TCG_TARGET_H */ diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index b62e14d5ce..493bbf1e39 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -302,20 +302,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, return true; } =20 -/* Parse target specific constraints. */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch (*ct_str++) { - case 'r': - ct->regs =3D BIT(TCG_TARGET_NB_REGS) - 1; - break; - default: - return NULL; - } - return ct_str; -} - #if defined(CONFIG_DEBUG_TCG_INTERPRETER) /* Show current bytecode. Used by tcg interpreter. */ void tci_disas(uint8_t opc) --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611951862; cv=none; d=zohomail.com; s=zohoarc; b=MBXg2rKpb4e5q0RYOGJEU3oeXY2WTNvIIp89i7U4l/NmfA/aFRpNNIOqIjqj+RehzMIp46Hbz7sphlrkWtPfDwD7mL8+F6dMjTm3uiKhWD+ohaZfAyOgUzW6Eqi4gnSkbH1FlfQkzDKVqNiuXz1nAkH38/GdnXm7qD5kM/fKo2g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611951862; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1em8pBHjBL7/5zdQ88dpF9TSGh7vMTgLGyFaaNNAAyM=; b=hP4/mRtdewUwUVb2sVaAO0uJaa6wSKheAQAGX9tfxWkJMc+0A0B87SVcxTXmSgTsomm2v7dbjEitQv8uTRVK+p7J9yS6gekQx/KJrMHkl9IXjH/4ruL53yFDYP04wm67feIQBs28RLjBbbZgOTfL222mNRq0Sk40k+g6Ur2NJjY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611951862571489.3195389631438; Fri, 29 Jan 2021 12:24:22 -0800 (PST) Received: from localhost ([::1]:44796 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5aJZ-0004qS-DT for importer@patchew.org; Fri, 29 Jan 2021 15:24:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49110) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5a6V-0006Kp-H2 for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:51 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:37786) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5a6T-00084N-Ez for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:51 -0500 Received: by mail-pl1-x62a.google.com with SMTP id q2so5896385plk.4 for ; Fri, 29 Jan 2021 12:10:48 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-str.h | 24 +++++++++++ tcg/mips/tcg-target.h | 1 + tcg/mips/tcg-target.c.inc | 77 ++++++++++------------------------- 3 files changed, 46 insertions(+), 56 deletions(-) create mode 100644 tcg/mips/tcg-target-con-str.h diff --git a/tcg/mips/tcg-target-con-str.h b/tcg/mips/tcg-target-con-str.h new file mode 100644 index 0000000000..e4b2965c72 --- /dev/null +++ b/tcg/mips/tcg-target-con-str.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define MIPS target-specific operand constraints. + * Copyright (c) 2021 Linaro + */ + +/* + * Define constraint letters for register sets: + * REGS(letter, register_mask) + */ +REGS('r', ALL_GENERAL_REGS) +REGS('L', ALL_QLOAD_REGS) +REGS('S', ALL_QSTORE_REGS) + +/* + * Define constraint letters for constants: + * CONST(letter, TCG_CT_CONST_* bit set) + */ +CONST('I', TCG_CT_CONST_U16) +CONST('J', TCG_CT_CONST_S16) +CONST('K', TCG_CT_CONST_P2M1) +CONST('N', TCG_CT_CONST_N16) +CONST('W', TCG_CT_CONST_WSZ) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c2c32fb38f..d850200855 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -207,5 +207,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif +#define TCG_TARGET_CON_STR_H =20 #endif diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 7293169ab2..432d38a010 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -171,67 +171,27 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, #define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ #define TCG_CT_CONST_WSZ 0x2000 /* word size */ =20 +#define ALL_GENERAL_REGS 0xffffffffu +#define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0)) + +#ifdef CONFIG_SOFTMMU +#define ALL_QLOAD_REGS \ + (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2)) +#define ALL_QSTORE_REGS \ + (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \ + ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \ + : (1 << TCG_REG_A1))) +#else +#define ALL_QLOAD_REGS NOA0_REGS +#define ALL_QSTORE_REGS NOA0_REGS +#endif + + static inline bool is_p2m1(tcg_target_long val) { return val && ((val + 1) & val) =3D=3D 0; } =20 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch(*ct_str++) { - case 'r': - ct->regs =3D 0xffffffff; - break; - case 'L': /* qemu_ld input arg constraint */ - ct->regs =3D 0xffffffff; - tcg_regset_reset_reg(ct->regs, TCG_REG_A0); -#if defined(CONFIG_SOFTMMU) - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_regset_reset_reg(ct->regs, TCG_REG_A2); - } -#endif - break; - case 'S': /* qemu_st constraint */ - ct->regs =3D 0xffffffff; - tcg_regset_reset_reg(ct->regs, TCG_REG_A0); -#if defined(CONFIG_SOFTMMU) - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_regset_reset_reg(ct->regs, TCG_REG_A2); - tcg_regset_reset_reg(ct->regs, TCG_REG_A3); - } else { - tcg_regset_reset_reg(ct->regs, TCG_REG_A1); - } -#endif - break; - case 'I': - ct->ct |=3D TCG_CT_CONST_U16; - break; - case 'J': - ct->ct |=3D TCG_CT_CONST_S16; - break; - case 'K': - ct->ct |=3D TCG_CT_CONST_P2M1; - break; - case 'N': - ct->ct |=3D TCG_CT_CONST_N16; - break; - case 'W': - ct->ct |=3D TCG_CT_CONST_WSZ; - break; - case 'Z': - /* We are cheating a bit here, using the fact that the register - ZERO is also the register number 0. Hence there is no need - to check for const_args in each instruction. */ - ct->ct |=3D TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* test if a constant matches the constraint */ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) @@ -1697,6 +1657,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, TCGArg a0, a1, a2; int c2; =20 + /* + * Note that many operands use the constraint set "rZ". + * We make use of the fact that 0 is the ZERO register, + * and hence such cases need not check for const_args. + */ a0 =3D args[0]; a1 =3D args[1]; a2 =3D args[2]; --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611951783; cv=none; d=zohomail.com; s=zohoarc; b=KSq37DzkI8qOWGzNuhgAvKXhRNRSFPAXbWJ/iMf+2uKjOZaOFvMg3jcQYni5v/xJ7yd9S8q7fx8ZWgQWdRa38iNyew9jN5+vVN+NIRiG67vXLFgHjyIoSvX0bKMyxgLR8o4czCfF1pwAwOnnHFHESGTlhq/MfqQAux6FJdIKZj0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611951783; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ek8RNt1cJCigIK6wEhL2V+rM7bS7+SN/XueD6pMUgtA=; b=IR9xKs33FDvUcIc0AdoSaV7mJ1fA0gVwbIhIIaXtPsTOTmYbhwY0TpMSl/do4bqK9C5oRCID/D1EL5KMikRhyvOCjgQhw1RvDSdrygajaOW075edFqO7qcNj9in4gIAk59UfW5wMcgzESUNdyHZ41z+XMABxIRlwVFUCxJhzALo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611951783680129.7728238071894; Fri, 29 Jan 2021 12:23:03 -0800 (PST) Received: from localhost ([::1]:37944 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5aII-00020r-M4 for importer@patchew.org; Fri, 29 Jan 2021 15:23:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49126) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5a6X-0006PA-73 for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:53 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:43142) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5a6V-00084X-5F for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:52 -0500 Received: by mail-pl1-x62f.google.com with SMTP id 8so555573plc.10 for ; Fri, 29 Jan 2021 12:10:50 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/riscv/tcg-target-con-str.h | 21 ++++++++++++++ tcg/riscv/tcg-target.h | 1 + tcg/riscv/tcg-target.c.inc | 52 +++++++++------------------------- 3 files changed, 35 insertions(+), 39 deletions(-) create mode 100644 tcg/riscv/tcg-target-con-str.h diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h new file mode 100644 index 0000000000..8d8afaee53 --- /dev/null +++ b/tcg/riscv/tcg-target-con-str.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define RISC-V target-specific operand constraints. + * Copyright (c) 2021 Linaro + */ + +/* + * Define constraint letters for register sets: + * REGS(letter, register_mask) + */ +REGS('r', ALL_GENERAL_REGS) +REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) + +/* + * Define constraint letters for constants: + * CONST(letter, TCG_CT_CONST_* bit set) + */ +CONST('I', TCG_CT_CONST_S12) +CONST('N', TCG_CT_CONST_N12) +CONST('M', TCG_CT_CONST_M12) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 727c8df418..daf3ef7b5c 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -171,5 +171,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 0 +#define TCG_TARGET_CON_STR_H =20 #endif diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 71c0badc02..20d5b5ef01 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -122,6 +122,19 @@ static const int tcg_target_call_oarg_regs[] =3D { #define TCG_CT_CONST_N12 0x400 #define TCG_CT_CONST_M12 0x800 =20 +#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) +/* + * For softmmu, we need to avoid conflicts with the first 5 + * argument registers to call the helper. Some of these are + * also used for the tlb lookup. + */ +#ifdef CONFIG_SOFTMMU +#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5) +#else +#define SOFTMMU_RESERVE_REGS 0 +#endif + + static inline tcg_target_long sextreg(tcg_target_long val, int pos, int le= n) { if (TCG_TARGET_REG_BITS =3D=3D 32) { @@ -131,45 +144,6 @@ static inline tcg_target_long sextreg(tcg_target_long = val, int pos, int len) } } =20 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch (*ct_str++) { - case 'r': - ct->regs =3D 0xffffffff; - break; - case 'L': - /* qemu_ld/qemu_st constraint */ - ct->regs =3D 0xffffffff; - /* qemu_ld/qemu_st uses TCG_REG_TMP0 */ -#if defined(CONFIG_SOFTMMU) - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]); - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]); - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]); - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]); - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]); -#endif - break; - case 'I': - ct->ct |=3D TCG_CT_CONST_S12; - break; - case 'N': - ct->ct |=3D TCG_CT_CONST_N12; - break; - case 'M': - ct->ct |=3D TCG_CT_CONST_M12; - break; - case 'Z': - /* we can use a zero immediate as a zero register argument. */ - ct->ct |=3D TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* test if a constant matches the constraint */ static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611951553; cv=none; d=zohomail.com; s=zohoarc; b=LpQVWMD6l0OhJE+CZJEVAz2+1EBxipRvffSL37Irlg1arJpTt1yIz1jUIIQLAHwIZ1p1thDpZvgMAHo8AU9FYysO5mfl8+Ml0PfBza/WwU2npvpwencMC/7sgs8k7o0/vm8FEGBDzcaLdefvcQWnLJgO2MmRdiHrEpn8BJgqNP0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611951553; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/xX/J9vMnowuMWo8/HanLANiLouFut86e12omyKqeRo=; b=i9Ns+h7A2fw2RgMyc4R6F7SuIid//vuWD0Z6ezhCN/4mbAaB+je5mI0uegJh0UYRcO/CPtgbz7M0OfUz1dyiImTZA2vQviOq7ySf7XgHEdl6OBKtTXBtBcZFH8g3bQMrLh6WQR8yRG9V7rOT/7grSfTkp1K1CSDMZ5GHUTD/v9g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611951553113136.8436239200695; Fri, 29 Jan 2021 12:19:13 -0800 (PST) Received: from localhost ([::1]:57972 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5aEZ-0006r2-Vz for importer@patchew.org; Fri, 29 Jan 2021 15:19:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49148) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5a6Y-0006TZ-Te for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:54 -0500 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:40743) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5a6W-000860-Pe for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:54 -0500 Received: by mail-pf1-x433.google.com with SMTP id i63so6912904pfg.7 for ; Fri, 29 Jan 2021 12:10:52 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id d133sm9247265pfd.6.2021.01.29.12.10.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 12:10:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/xX/J9vMnowuMWo8/HanLANiLouFut86e12omyKqeRo=; b=LXCwLTEdDUKjraKVnSlcA1VuYK+D8AofXPhzDEz8o4x6WYrs9aXDOZAA7GW3teoAaZ TrTc9LROnOpM08QEk4VO8dluToMTQXS0alcQ0f9xu0HH6Udxnj7XQ7VRzUWs4C0juJoR 4OPHjpNSprnfageJQFEAEdiJiXVfAYzRfhtrfIt6TJoZA25BO1WV4EwViYIC+yQb8gtk plTAr7/dZCabdpvyuz7UphDj+h73Bf9t9u/02qmXZ7xr9Ai9ln1+zrsZ7qD0bR3eSMop Es5xlIIv29A9k4ZnuH6DaVo8aGa++4n1AXGATEQ/DM1k7dlFaAe80gKj/ro4c1Ff1oEG DqXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/xX/J9vMnowuMWo8/HanLANiLouFut86e12omyKqeRo=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/s390/tcg-target-con-str.h | 28 ++++++++++++++++++ tcg/s390/tcg-target.h | 1 + tcg/s390/tcg-target.c.inc | 53 +++++++++-------------------------- 3 files changed, 42 insertions(+), 40 deletions(-) create mode 100644 tcg/s390/tcg-target-con-str.h diff --git a/tcg/s390/tcg-target-con-str.h b/tcg/s390/tcg-target-con-str.h new file mode 100644 index 0000000000..892d8f8c06 --- /dev/null +++ b/tcg/s390/tcg-target-con-str.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define S390 target-specific operand constraints. + * Copyright (c) 2021 Linaro + */ + +/* + * Define constraint letters for register sets: + * REGS(letter, register_mask) + */ +REGS('r', ALL_GENERAL_REGS) +REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) +/* + * A (single) even/odd pair for division. + * TODO: Add something to the register allocator to allow + * this kind of regno+1 pairing to be done more generally. + */ +REGS('a', 1u << TCG_REG_R2) +REGS('b', 1u << TCG_REG_R3) + +/* + * Define constraint letters for constants: + * CONST(letter, TCG_CT_CONST_* bit set) + */ +CONST('A', TCG_CT_CONST_S33) +CONST('I', TCG_CT_CONST_S16) +CONST('J', TCG_CT_CONST_S32) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 641464eea4..c43d6aba84 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -159,5 +159,6 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CON_STR_H =20 #endif diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 8517e55232..3fec7fec5f 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -42,6 +42,19 @@ #define TCG_CT_CONST_S33 0x400 #define TCG_CT_CONST_ZERO 0x800 =20 +#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16) +/* + * For softmmu, we need to avoid conflicts with the first 3 + * argument registers to perform the tlb lookup, and to call + * the helper function. + */ +#ifdef CONFIG_SOFTMMU +#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_R2, 3) +#else +#define SOFTMMU_RESERVE_REGS 0 +#endif + + /* Several places within the instruction set 0 means "no register" rather than TCG_REG_R0. */ #define TCG_REG_NONE 0 @@ -403,46 +416,6 @@ static bool patch_reloc(tcg_insn_unit *src_rw, int typ= e, return false; } =20 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch (*ct_str++) { - case 'r': /* all registers */ - ct->regs =3D 0xffff; - break; - case 'L': /* qemu_ld/st constraint */ - ct->regs =3D 0xffff; - tcg_regset_reset_reg(ct->regs, TCG_REG_R2); - tcg_regset_reset_reg(ct->regs, TCG_REG_R3); - tcg_regset_reset_reg(ct->regs, TCG_REG_R4); - break; - case 'a': /* force R2 for division */ - ct->regs =3D 0; - tcg_regset_set_reg(ct->regs, TCG_REG_R2); - break; - case 'b': /* force R3 for division */ - ct->regs =3D 0; - tcg_regset_set_reg(ct->regs, TCG_REG_R3); - break; - case 'A': - ct->ct |=3D TCG_CT_CONST_S33; - break; - case 'I': - ct->ct |=3D TCG_CT_CONST_S16; - break; - case 'J': - ct->ct |=3D TCG_CT_CONST_S32; - break; - case 'Z': - ct->ct |=3D TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* Test if a constant matches the constraint. */ static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id d133sm9247265pfd.6.2021.01.29.12.10.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 12:10:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=mc+ASukmT1uZXl4fvbEnBIBoVZRpInvW/7vs/PLRqwk=; b=JzLyQRfMWmHxdy0QKcZXnMp0EB/zGWle+N4MrkeZ5N5qFvwFODLWtAt1kSP478lAO5 tj3MxK18jokfK79XIVFHdKETCZ/kHABZW0TnNerJJyLEtzOQ28jD//6C394u2mAuqWIN R4xIA+XOlXCRSgL2fgTnrZAxIwfwu3ZT2bwkvhgqtnj/VBdPlgbFztuw/I9SPmIwDl9N dUkKiBlRqlOaZsL4RpuQUYilh+yixrd0sjuBXqRs1zZ/SybYbqiTMruFum73KBMQ29zb RBa/opc4gHmEI5C4pidAqbFQAzpO5bmX7oneMDidMJHvCEbSftYb23lTwW2VJiJiDYvQ 4I+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mc+ASukmT1uZXl4fvbEnBIBoVZRpInvW/7vs/PLRqwk=; b=IXlSLjKE7RgKEVlhddoLjDuito5AhvItU5hvhunUWq9U3N/Xgv7lgOqQPj9M3C41WA LcNcK1xpiNJTmy3BMvPHBmpxuzSA48Rmr5uvJd+cG0IAgNBLjTGjmFonwv2lWUYTXk+9 tBSp2CkaMKA56Hk/DxT2uTZxvBKKE+WF/9A4hkBTrFgn08wljN1WEqKwLA88OFKpSYp5 k6jL2Xlr1AuJR/Hgx4XqMmVf/QM4wt7FjOKZYppdIhv01uzxJPCnwmFOeA+iyKQWy+TC lEOVYLAM/I8glhfzK6D2b5utaCu2t4k5C78EztmLHSEoTJqZ8OOPF1x0LqNzbxLkKvF/ QUTQ== X-Gm-Message-State: AOAM533aZ28/ySR2ESghiCRetPrkXs48jFu+NTnzkMy0wAi5R6kO4nVD Rdv7wnbvq5d0Du7r0Fc6cnmxVFVmZZtttF4b X-Google-Smtp-Source: ABdhPJzz/ROAg8+8ZbDytO8zebhRaUOCuL1urTMn6mPkwxit/XaSU4ol5kEVGToy0zdRVY+U6kPhmw== X-Received: by 2002:a17:90a:6bc3:: with SMTP id w61mr6221715pjj.214.1611951052800; Fri, 29 Jan 2021 12:10:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 13/24] tcg/sparc: Split out target constraints to tcg-target-con-str.h Date: Fri, 29 Jan 2021 10:10:17 -1000 Message-Id: <20210129201028.787853-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129201028.787853-1-richard.henderson@linaro.org> References: <20210129201028.787853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/sparc/tcg-target-con-str.h | 23 ++++++++++ tcg/sparc/tcg-target.h | 5 +-- tcg/sparc/tcg-target.c.inc | 81 +++++++++++++--------------------- 3 files changed, 55 insertions(+), 54 deletions(-) create mode 100644 tcg/sparc/tcg-target-con-str.h diff --git a/tcg/sparc/tcg-target-con-str.h b/tcg/sparc/tcg-target-con-str.h new file mode 100644 index 0000000000..fdb25d9313 --- /dev/null +++ b/tcg/sparc/tcg-target-con-str.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define Sparc target-specific operand constraints. + * Copyright (c) 2021 Linaro + */ + +/* + * Define constraint letters for register sets: + * REGS(letter, register_mask) + */ +REGS('r', ALL_GENERAL_REGS) +REGS('R', ALL_GENERAL_REGS64) +REGS('s', ALL_QLDST_REGS) +REGS('S', ALL_QLDST_REGS64) +REGS('A', TARGET_LONG_BITS =3D=3D 64 ? ALL_QLDST_REGS64 : ALL_QLDST_REGS) + +/* + * Define constraint letters for constants: + * CONST(letter, TCG_CT_CONST_* bit set) + */ +CONST('I', TCG_CT_CONST_S11) +CONST('J', TCG_CT_CONST_S13) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 95ab9af955..5185b00524 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -66,10 +66,6 @@ typedef enum { TCG_REG_I7, } TCGReg; =20 -#define TCG_CT_CONST_S11 0x100 -#define TCG_CT_CONST_S13 0x200 -#define TCG_CT_CONST_ZERO 0x400 - /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_O6 =20 @@ -172,5 +168,6 @@ extern bool use_vis3_instructions; void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CON_STR_H =20 #endif diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 28b5b6559a..e291eb0b95 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -67,18 +67,38 @@ static const char * const tcg_target_reg_names[TCG_TARG= ET_NB_REGS] =3D { # define SPARC64 0 #endif =20 -/* Note that sparcv8plus can only hold 64 bit quantities in %g and %o - registers. These are saved manually by the kernel in full 64-bit - slots. The %i and %l registers are saved by the register window - mechanism, which only allocates space for 32 bits. Given that this - window spill/fill can happen on any signal, we must consider the - high bits of the %i and %l registers garbage at all times. */ -#if SPARC64 -# define ALL_64 0xffffffffu +#define TCG_CT_CONST_S11 0x100 +#define TCG_CT_CONST_S13 0x200 +#define TCG_CT_CONST_ZERO 0x400 + +/* + * For softmmu, we need to avoid conflicts with the first 3 + * argument registers to perform the tlb lookup, and to call + * the helper function. + */ +#ifdef CONFIG_SOFTMMU +#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_O0, 3) #else -# define ALL_64 0xffffu +#define SOFTMMU_RESERVE_REGS 0 #endif =20 +/* + * Note that sparcv8plus can only hold 64 bit quantities in %g and %o + * registers. These are saved manually by the kernel in full 64-bit + * slots. The %i and %l registers are saved by the register window + * mechanism, which only allocates space for 32 bits. Given that this + * window spill/fill can happen on any signal, we must consider the + * high bits of the %i and %l registers garbage at all times. + */ +#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) +#if SPARC64 +# define ALL_GENERAL_REGS64 ALL_GENERAL_REGS +#else +# define ALL_GENERAL_REGS64 MAKE_64BIT_MASK(0, 16) +#endif +#define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) +#define ALL_QLDST_REGS64 (ALL_GENERAL_REGS64 & ~SOFTMMU_RESERVE_REGS) + /* Define some temporary registers. T2 is used for constant generation. = */ #define TCG_REG_T1 TCG_REG_G1 #define TCG_REG_T2 TCG_REG_O7 @@ -320,45 +340,6 @@ static bool patch_reloc(tcg_insn_unit *src_rw, int typ= e, return true; } =20 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e) -{ - switch (*ct_str++) { - case 'r': - ct->regs =3D 0xffffffff; - break; - case 'R': - ct->regs =3D ALL_64; - break; - case 'A': /* qemu_ld/st address constraint */ - ct->regs =3D TARGET_LONG_BITS =3D=3D 64 ? ALL_64 : 0xffffffff; - reserve_helpers: - tcg_regset_reset_reg(ct->regs, TCG_REG_O0); - tcg_regset_reset_reg(ct->regs, TCG_REG_O1); - tcg_regset_reset_reg(ct->regs, TCG_REG_O2); - break; - case 's': /* qemu_st data 32-bit constraint */ - ct->regs =3D 0xffffffff; - goto reserve_helpers; - case 'S': /* qemu_st data 64-bit constraint */ - ct->regs =3D ALL_64; - goto reserve_helpers; - case 'I': - ct->ct |=3D TCG_CT_CONST_S11; - break; - case 'J': - ct->ct |=3D TCG_CT_CONST_S13; - break; - case 'Z': - ct->ct |=3D TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* test if a constant matches the constraint */ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) @@ -1746,8 +1727,8 @@ static void tcg_target_init(TCGContext *s) } #endif =20 - tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffff; - tcg_target_available_regs[TCG_TYPE_I64] =3D ALL_64; + tcg_target_available_regs[TCG_TYPE_I32] =3D ALL_GENERAL_REGS; + tcg_target_available_regs[TCG_TYPE_I64] =3D ALL_GENERAL_REGS64; =20 tcg_target_call_clobber_regs =3D 0; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1); --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611951973; cv=none; d=zohomail.com; s=zohoarc; b=Krqpd9CLEVLNy7SuZ7VNVi+nsym2NI0gr48+nWlz8OY8VjYYz/Fal6m1ZTubIWECDN188tRJ9FDD+mOZBoYqCoE29Rvm6XiQHfZqPzlhKWQBgyj1XZBx2Y3yAGWpNlaTpFxZWB01aYE4TOT2Dy33dSCvT6xN6an/r6zZbzX0HI8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611951973; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Y2Oa3ZEH5uoUGxC8/0DNuxe42IEbkJmpNsi7nZchOrE=; b=iICO+Vysn7dJYOznHMg094mPYRsvePjkm0R6D188ibauyxxtg3Op0/KMLBQF4S7Z5PKCoCzdsk1En4zdyBTMp4HMCJf/98v/dtmOpW8WtpQYGLCU6l9j5btq/WA4IsVGRR3N0Q4uUn+M1qhPfK+S6IN/jSxuStWcljRuH6elvJU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611951973497927.2550656284011; Fri, 29 Jan 2021 12:26:13 -0800 (PST) Received: from localhost ([::1]:51658 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5aLM-0007hV-EZ for importer@patchew.org; Fri, 29 Jan 2021 15:26:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49192) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5a6b-0006at-QY for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:57 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:42403) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5a6Z-00087e-MI for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:57 -0500 Received: by mail-pl1-x62b.google.com with SMTP id s15so5884689plr.9 for ; Fri, 29 Jan 2021 12:10:55 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id d133sm9247265pfd.6.2021.01.29.12.10.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 12:10:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y2Oa3ZEH5uoUGxC8/0DNuxe42IEbkJmpNsi7nZchOrE=; b=eHGJoA5RBXxhpS4Fhh6ZZv5vijSCYeU29U6XUaqZ5g7GmIHSznue3LAbOkAk7ygQ3v pEBPZls0Ejm5995NzAxAT6C4FhiLZJRq5OOdc0sP+JShM2nEtYax4vb6eLNjJt9NwReX JJlF9c4SPCwCtMc4cxXbtFiRsRVSz5pO3TmD2MD1GfA2+Wd0dth1rEGBO0saoWd72Rt3 c9WWxjD1BZfhJlTick+0dKHSIuP2uTHSsMjdledbhdHiF6Z70rsgQrh2pYmBHMMK1egZ M5HNbIUSMmrEoAO9wuKVdZLPUxMhPmT8fHtqC4+XjwwubOiDw/LXSL8B0NthRiI1d8k+ 3I/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y2Oa3ZEH5uoUGxC8/0DNuxe42IEbkJmpNsi7nZchOrE=; b=uI1P3ltQP5mi7ujCBZ4Px5qdIqcj2iI0k/eb/tWNINKr+C9dFV+ntg1Zx7h7qJ3u8K naguwrxCcmOStZUS+FDFWwAZ2RQ+9Y4FQMiNMjWdzIhhFeKgaNriCTcRrnstDPR/NFae NY2Ih9lXcEv68w3HUHjWNiZ03P9NQWUZJDAMWebVHUP+uOd37iCCcXCKRZNLYcx3yqZh BU8gUpLMrUYmFoAPVf3v0wcLD4ZoNtnrYat5xUSWSKyWUCF5U2fE5aISMtg0K6z+c4li sfJ4aZEq9x3X50dTvk03PsKhGdAPXDZBGwydZiSCiXMDUhU0Zx9g+gJHKjdQIJGswNi9 Pgyw== X-Gm-Message-State: AOAM530XI2Ayb4qfwTZ+jwF3VBG39s5dCOfwFUw5IkvoaSChTlpLU1/D yFrBoeRXrHl/h4KiPwZGWzdeRaAuZeX/YU6J X-Google-Smtp-Source: ABdhPJyzDF70Q762Jm/e7r7yAQNWWxNoulWHRase4lmIGS8ur3ff37SNMu0mkt/ZZt28VryRUlgHHA== X-Received: by 2002:a17:90b:180d:: with SMTP id lw13mr6040907pjb.94.1611951054512; Fri, 29 Jan 2021 12:10:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 14/24] tcg: Remove TCG_TARGET_CON_STR_H Date: Fri, 29 Jan 2021 10:10:18 -1000 Message-Id: <20210129201028.787853-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129201028.787853-1-richard.henderson@linaro.org> References: <20210129201028.787853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" All backends have now been converted to tcg-target-con-str.h, so we can remove the fallback code. Reviewed-by: Peter Maydell Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 - tcg/arm/tcg-target.h | 1 - tcg/i386/tcg-target.h | 1 - tcg/mips/tcg-target.h | 1 - tcg/ppc/tcg-target.h | 1 - tcg/riscv/tcg-target.h | 1 - tcg/s390/tcg-target.h | 1 - tcg/sparc/tcg-target.h | 1 - tcg/tci/tcg-target.h | 2 -- tcg/tcg.c | 16 ---------------- 10 files changed, 26 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 4fc20b58ec..5ec30dba25 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -155,6 +155,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CON_STR_H =20 #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 16336cd545..8d1fee6327 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -142,6 +142,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CON_STR_H =20 #endif diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 77693e13ea..b693d3692d 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -235,6 +235,5 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CON_STR_H =20 #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index d850200855..c2c32fb38f 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -207,6 +207,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif -#define TCG_TARGET_CON_STR_H =20 #endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 40ed4b82dd..d1339afc66 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -185,6 +185,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CON_STR_H =20 #endif diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index daf3ef7b5c..727c8df418 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -171,6 +171,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 0 -#define TCG_TARGET_CON_STR_H =20 #endif diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index c43d6aba84..641464eea4 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -159,6 +159,5 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CON_STR_H =20 #endif diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 5185b00524..f66f5d07dc 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -168,6 +168,5 @@ extern bool use_vis3_instructions; void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CON_STR_H =20 #endif diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index ab832aecc3..bb784e018e 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -207,6 +207,4 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, uintptr_t jmp_rx, /* no need to flush icache explicitly */ } =20 -#define TCG_TARGET_CON_STR_H - #endif /* TCG_TARGET_H */ diff --git a/tcg/tcg.c b/tcg/tcg.c index 8cfa28ed84..39bcdff8dc 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -103,10 +103,6 @@ static void tcg_register_jit_int(const void *buf, size= _t size, __attribute__((unused)); =20 /* Forward declarations for functions declared and used in tcg-target.c.in= c. */ -#ifndef TCG_TARGET_CON_STR_H -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType typ= e); -#endif static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg= 1, intptr_t arg2); static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); @@ -2464,7 +2460,6 @@ static void process_op_defs(TCGContext *s) ct_str++; break; =20 -#ifdef TCG_TARGET_CON_STR_H /* Include all of the target-specific constraints. */ =20 #undef CONST @@ -2480,17 +2475,6 @@ static void process_op_defs(TCGContext *s) default: /* Typo in TCGTargetOpDef constraint. */ g_assert_not_reached(); -#else - default: - { - TCGType type =3D (def->flags & TCG_OPF_64BIT - ? TCG_TYPE_I64 : TCG_TYPE_I32); - ct_str =3D target_parse_constraint(&def->args_ct[i= ], - ct_str, type); - /* Typo in TCGTargetOpDef constraint. */ - tcg_debug_assert(ct_str !=3D NULL); - } -#endif } } } --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611951791; cv=none; d=zohomail.com; s=zohoarc; b=I+iimU/BgjDOxRFi4GVMJ3Vt8S/Sq1shcDYcUwGvGlevaikXMoOCiynSVqmGpcdVUXFqyDUy/DIK2WLFZ9rIaBYLwC4MwolAu8QWo3G/6sSm2Ijz8WKKPHtm6kH1Y7B4ckUaaTTg0vnkfWmmj2KIrMj/wjn0FhBW67gxdzcHCxw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611951791; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ub1nQ8Juh5iPdbwapeH2zYEuiPf/Gb0rWV9s3PXu8aw=; b=Y996tSM7HEglStgjd+SJ/NfLmDVKyQsKJs/eq8Ncw+a+siX9slhLLYIVvUPJaYW6ss9W6ry8CgEh7pY2fJbOAv5tjxztgiPcfEaX8vbKaqvRNMNBDR/zQ4HfIhdToV8rd7FbqufOH52eWqlJ/SV//rOCE4g2OiQIs0zH47Zqy8M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611951791626665.6576890568692; Fri, 29 Jan 2021 12:23:11 -0800 (PST) Received: from localhost ([::1]:38146 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5aIQ-000266-FB for importer@patchew.org; Fri, 29 Jan 2021 15:23:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49210) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5a6e-0006gx-AB for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:11:00 -0500 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:46304) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5a6b-000887-HZ for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:10:59 -0500 Received: by mail-pg1-x52c.google.com with SMTP id r38so7387770pgk.13 for ; Fri, 29 Jan 2021 12:10:57 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id d133sm9247265pfd.6.2021.01.29.12.10.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 12:10:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ub1nQ8Juh5iPdbwapeH2zYEuiPf/Gb0rWV9s3PXu8aw=; b=xdC+CjGDaN5m50Vt6ZkgSde9MoVys2bmO2yyVMN4IBlqMivWEo4jHUyayUxZfwjyfo PSG3KAgjuB/m2Y06RNFy9vm5EDoMXF8NVeqV2zdMEn6X/CR6Va9YsVeuuVw3fCwD4wRl yGV8fSYOjQ6JuoBEW85Q3hMGXK7PBzn9sT2J3AnxLKqCg6QoocjTqUSiNulQ5nhwdD9d hFYdcnlW5wZ0iSb9a0BwPVh3Lyreh/+KKh4DL8m81SV8/7kKgar87T/6/QhDhcyvKGEd KMbGVbKTcVx9f1701o0vkfrtKiE/83n/J/m3u35vrDd9sXWJiVAtmrJFriFJalgaxCVE 2i5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ub1nQ8Juh5iPdbwapeH2zYEuiPf/Gb0rWV9s3PXu8aw=; b=MF+iiDFd0PbymsCcC62YdxSTs+iEAECsRzQRvG7gIq+RFqzNm3uk7pCs0EdchCb+IS wEeZub8xpf4ujdPOVg6n1crXfj9dtkFpYdDwP6x2I+Dgb1XVcUwt7NtdRd/wiwv3W2gL pIb489KOmbnRwP/MeTKxFkBSlYiCBE8rsBD4s5+4pZuOLGC80G4J9Zm4be2kuoSs1R7K MR81VSu35j+1Cb0JAVVjhUqXz25JGKl5oiJUkDIIHVTzL/nnr6A3zlFIbyq01UTJ0vg8 pX1AyFsm0w5q81YCmBr4AKbJE+ToQWF30mFn44x2rDq4ASoFGX0RoGosOoH7qlDcn4VF icgQ== X-Gm-Message-State: AOAM530BcBt6j93Su36LXklbU+s/x2CQ9OjYcbY8PvIRVRyAaiRS3HWG ecXQx51cJjP0lPPgpuMPTrQySZRFcRrWRCSf X-Google-Smtp-Source: ABdhPJzhwFSTar5uIzZaWxqJ/g639X384ay0MftcyB7FC2oB0FWGeT39N7AIHUlvEiP4zcrUaNu0Hg== X-Received: by 2002:a63:43c6:: with SMTP id q189mr6290836pga.245.1611951056128; Fri, 29 Jan 2021 12:10:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 15/24] tcg/i386: Split out constraint sets to tcg-target-con-set.h Date: Fri, 29 Jan 2021 10:10:19 -1000 Message-Id: <20210129201028.787853-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129201028.787853-1-richard.henderson@linaro.org> References: <20210129201028.787853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This exports the constraint sets from tcg_target_op_def to a place we will be able to manipulate more in future. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-con-set.h | 55 ++++++++++ tcg/i386/tcg-target.h | 1 + tcg/tcg.c | 119 +++++++++++++++++++++ tcg/i386/tcg-target.c.inc | 194 ++++++++++++---------------------- 4 files changed, 242 insertions(+), 127 deletions(-) create mode 100644 tcg/i386/tcg-target-con-set.h diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/i386/tcg-target-con-set.h new file mode 100644 index 0000000000..78774d1005 --- /dev/null +++ b/tcg/i386/tcg-target-con-set.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define i386 target-specific constraint sets. + * Copyright (c) 2021 Linaro + */ + +/* + * C_On_Im(...) defines a constraint set with outputs and inputs. + * Each operand should be a sequence of constraint letters as defined by + * tcg-target-con-str.h; the constraint combination is inclusive or. + * + * C_N1_Im(...) defines a constraint set with 1 output and inputs, + * except that the output must use a new register. + */ +C_O0_I1(r) +C_O0_I2(L, L) +C_O0_I2(qi, r) +C_O0_I2(re, r) +C_O0_I2(ri, r) +C_O0_I2(r, re) +C_O0_I2(s, L) +C_O0_I2(x, r) +C_O0_I3(L, L, L) +C_O0_I3(s, L, L) +C_O0_I4(L, L, L, L) +C_O0_I4(r, r, ri, ri) +C_O1_I1(r, 0) +C_O1_I1(r, L) +C_O1_I1(r, q) +C_O1_I1(r, r) +C_O1_I1(x, r) +C_O1_I1(x, x) +C_O1_I2(Q, 0, Q) +C_O1_I2(q, r, re) +C_O1_I2(r, 0, ci) +C_O1_I2(r, 0, r) +C_O1_I2(r, 0, re) +C_O1_I2(r, 0, reZ) +C_O1_I2(r, 0, ri) +C_O1_I2(r, 0, rI) +C_O1_I2(r, L, L) +C_O1_I2(r, r, re) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) +C_O1_I2(x, x, x) +C_N1_I2(r, r, r) +C_N1_I2(r, r, rW) +C_O1_I3(x, x, x, x) +C_O1_I4(r, r, re, r, 0) +C_O1_I4(r, r, r, ri, ri) +C_O2_I1(r, r, L) +C_O2_I2(a, d, a, r) +C_O2_I2(r, r, L, L) +C_O2_I3(a, d, 0, 1, r) +C_O2_I4(r, r, 0, 1, re, re) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b693d3692d..48a6f2a336 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -235,5 +235,6 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CON_SET_H =20 #endif diff --git a/tcg/tcg.c b/tcg/tcg.c index 39bcdff8dc..df9f32763e 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -69,7 +69,9 @@ /* Forward declarations for functions declared in tcg-target.c.inc and used here. */ static void tcg_target_init(TCGContext *s); +#ifndef TCG_TARGET_CON_SET_H static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode); +#endif static void tcg_target_qemu_prologue(TCGContext *s); static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend); @@ -347,6 +349,112 @@ static void set_jmp_reset_offset(TCGContext *s, int w= hich) s->tb_jmp_reset_offset[which] =3D tcg_current_code_size(s); } =20 +#ifdef TCG_TARGET_CON_SET_H +#define C_PFX1(P, A) P##A +#define C_PFX2(P, A, B) P##A##_##B +#define C_PFX3(P, A, B, C) P##A##_##B##_##C +#define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D +#define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E +#define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F + +/* Define an enumeration for the various combinations. */ + +#define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1), +#define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2), +#define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3), +#define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4), + +#define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1), +#define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2), +#define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3), +#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I= 4), + +#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2), + +#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1), +#define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2), +#define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I= 3), +#define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I= 3, I4), + +typedef enum { +#include "tcg-target-con-set.h" +} TCGConstraintSetIndex; + +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode); + +#undef C_O0_I1 +#undef C_O0_I2 +#undef C_O0_I3 +#undef C_O0_I4 +#undef C_O1_I1 +#undef C_O1_I2 +#undef C_O1_I3 +#undef C_O1_I4 +#undef C_N1_I2 +#undef C_O2_I1 +#undef C_O2_I2 +#undef C_O2_I3 +#undef C_O2_I4 + +/* Put all of the constraint sets into an array, indexed by the enum. */ + +#define C_O0_I1(I1) { .args_ct_str =3D { #I1 } }, +#define C_O0_I2(I1, I2) { .args_ct_str =3D { #I1, #I2 } }, +#define C_O0_I3(I1, I2, I3) { .args_ct_str =3D { #I1, #I2, #I3= } }, +#define C_O0_I4(I1, I2, I3, I4) { .args_ct_str =3D { #I1, #I2, #I3= , #I4 } }, + +#define C_O1_I1(O1, I1) { .args_ct_str =3D { #O1, #I1 } }, +#define C_O1_I2(O1, I1, I2) { .args_ct_str =3D { #O1, #I1, #I2= } }, +#define C_O1_I3(O1, I1, I2, I3) { .args_ct_str =3D { #O1, #I1, #I2= , #I3 } }, +#define C_O1_I4(O1, I1, I2, I3, I4) { .args_ct_str =3D { #O1, #I1, #I2= , #I3, #I4 } }, + +#define C_N1_I2(O1, I1, I2) { .args_ct_str =3D { "&" #O1, #I1,= #I2 } }, + +#define C_O2_I1(O1, O2, I1) { .args_ct_str =3D { #O1, #O2, #I1= } }, +#define C_O2_I2(O1, O2, I1, I2) { .args_ct_str =3D { #O1, #O2, #I1= , #I2 } }, +#define C_O2_I3(O1, O2, I1, I2, I3) { .args_ct_str =3D { #O1, #O2, #I1= , #I2, #I3 } }, +#define C_O2_I4(O1, O2, I1, I2, I3, I4) { .args_ct_str =3D { #O1, #O2, #I1= , #I2, #I3, #I4 } }, + +static const TCGTargetOpDef constraint_sets[] =3D { +#include "tcg-target-con-set.h" +}; + + +#undef C_O0_I1 +#undef C_O0_I2 +#undef C_O0_I3 +#undef C_O0_I4 +#undef C_O1_I1 +#undef C_O1_I2 +#undef C_O1_I3 +#undef C_O1_I4 +#undef C_N1_I2 +#undef C_O2_I1 +#undef C_O2_I2 +#undef C_O2_I3 +#undef C_O2_I4 + +/* Expand the enumerator to be returned from tcg_target_op_def(). */ + +#define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1) +#define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2) +#define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3) +#define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4) + +#define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1) +#define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2) +#define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3) +#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I= 4) + +#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2) + +#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1) +#define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2) +#define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I= 3) +#define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I= 3, I4) + +#endif /* TCG_TARGET_CON_SET_H */ + #include "tcg-target.c.inc" =20 /* compare a pointer @ptr and a tb_tc @s */ @@ -2424,9 +2532,20 @@ static void process_op_defs(TCGContext *s) continue; } =20 +#ifdef TCG_TARGET_CON_SET_H + /* + * Macro magic should make it impossible, but double-check that + * the array index is in range. Since the signness of an enum + * is implementation defined, force the result to unsigned. + */ + unsigned con_set =3D tcg_target_op_def(op); + tcg_debug_assert(con_set < ARRAY_SIZE(constraint_sets)); + tdefs =3D &constraint_sets[con_set]; +#else tdefs =3D tcg_target_op_def(op); /* Missing TCGTargetOpDef entry. */ tcg_debug_assert(tdefs !=3D NULL); +#endif =20 for (i =3D 0; i < nb_args; i++) { const char *ct_str =3D tdefs->args_ct_str[i]; diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index d3cf97748a..40326c2806 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2894,41 +2894,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode= opc, } } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef ri_r =3D { .args_ct_str =3D { "ri", "r" } = }; - static const TCGTargetOpDef re_r =3D { .args_ct_str =3D { "re", "r" } = }; - static const TCGTargetOpDef qi_r =3D { .args_ct_str =3D { "qi", "r" } = }; - static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef r_q =3D { .args_ct_str =3D { "r", "q" } }; - static const TCGTargetOpDef r_re =3D { .args_ct_str =3D { "r", "re" } = }; - static const TCGTargetOpDef r_0 =3D { .args_ct_str =3D { "r", "0" } }; - static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; - static const TCGTargetOpDef r_r_re =3D { .args_ct_str =3D { "r", "r", = "re" } }; - static const TCGTargetOpDef r_0_r =3D { .args_ct_str =3D { "r", "0", "= r" } }; - static const TCGTargetOpDef r_0_re =3D { .args_ct_str =3D { "r", "0", = "re" } }; - static const TCGTargetOpDef r_0_ci =3D { .args_ct_str =3D { "r", "0", = "ci" } }; - static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; - static const TCGTargetOpDef L_L =3D { .args_ct_str =3D { "L", "L" } }; - static const TCGTargetOpDef s_L =3D { .args_ct_str =3D { "s", "L" } }; - static const TCGTargetOpDef r_L_L =3D { .args_ct_str =3D { "r", "L", "= L" } }; - static const TCGTargetOpDef r_r_L =3D { .args_ct_str =3D { "r", "r", "= L" } }; - static const TCGTargetOpDef L_L_L =3D { .args_ct_str =3D { "L", "L", "= L" } }; - static const TCGTargetOpDef s_L_L =3D { .args_ct_str =3D { "s", "L", "= L" } }; - static const TCGTargetOpDef r_r_L_L - =3D { .args_ct_str =3D { "r", "r", "L", "L" } }; - static const TCGTargetOpDef L_L_L_L - =3D { .args_ct_str =3D { "L", "L", "L", "L" } }; - static const TCGTargetOpDef x_x =3D { .args_ct_str =3D { "x", "x" } }; - static const TCGTargetOpDef x_x_x =3D { .args_ct_str =3D { "x", "x", "= x" } }; - static const TCGTargetOpDef x_x_x_x - =3D { .args_ct_str =3D { "x", "x", "x", "x" } }; - static const TCGTargetOpDef x_r =3D { .args_ct_str =3D { "x", "r" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: @@ -2942,22 +2912,25 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: - return &r_r; + return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: case INDEX_op_st8_i64: - return &qi_r; + return C_O0_I2(qi, r); + case INDEX_op_st16_i32: case INDEX_op_st16_i64: case INDEX_op_st_i32: case INDEX_op_st32_i64: - return &ri_r; + return C_O0_I2(ri, r); + case INDEX_op_st_i64: - return &re_r; + return C_O0_I2(re, r); =20 case INDEX_op_add_i32: case INDEX_op_add_i64: - return &r_r_re; + return C_O1_I2(r, r, re); + case INDEX_op_sub_i32: case INDEX_op_sub_i64: case INDEX_op_mul_i32: @@ -2966,24 +2939,15 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: - return &r_0_re; + return C_O1_I2(r, 0, re); =20 case INDEX_op_and_i32: case INDEX_op_and_i64: - { - static const TCGTargetOpDef and - =3D { .args_ct_str =3D { "r", "0", "reZ" } }; - return ∧ - } - break; + return C_O1_I2(r, 0, reZ); + case INDEX_op_andc_i32: case INDEX_op_andc_i64: - { - static const TCGTargetOpDef andc - =3D { .args_ct_str =3D { "r", "r", "rI" } }; - return &andc; - } - break; + return C_O1_I2(r, r, rI); =20 case INDEX_op_shl_i32: case INDEX_op_shl_i64: @@ -2991,16 +2955,17 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_shr_i64: case INDEX_op_sar_i32: case INDEX_op_sar_i64: - return have_bmi2 ? &r_r_ri : &r_0_ci; + return have_bmi2 ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ci); + case INDEX_op_rotl_i32: case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: - return &r_0_ci; + return C_O1_I2(r, 0, ci); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_re; + return C_O0_I2(r, re); =20 case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: @@ -3012,13 +2977,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_not_i32: case INDEX_op_not_i64: case INDEX_op_extrh_i64_i32: - return &r_0; + return C_O1_I1(r, 0); =20 case INDEX_op_ext8s_i32: case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: case INDEX_op_ext8u_i64: - return &r_q; + return C_O1_I1(r, q); + case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: case INDEX_op_ext16u_i32: @@ -3033,110 +2999,83 @@ static const TCGTargetOpDef *tcg_target_op_def(TCG= Opcode op) case INDEX_op_sextract_i32: case INDEX_op_ctpop_i32: case INDEX_op_ctpop_i64: - return &r_r; + return C_O1_I1(r, r); + case INDEX_op_extract2_i32: case INDEX_op_extract2_i64: - return &r_0_r; + return C_O1_I2(r, 0, r); =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - { - static const TCGTargetOpDef dep - =3D { .args_ct_str =3D { "Q", "0", "Q" } }; - return &dep; - } + return C_O1_I2(Q, 0, Q); + case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - { - static const TCGTargetOpDef setc - =3D { .args_ct_str =3D { "q", "r", "re" } }; - return &setc; - } + return C_O1_I2(q, r, re); + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - { - static const TCGTargetOpDef movc - =3D { .args_ct_str =3D { "r", "r", "re", "r", "0" } }; - return &movc; - } + return C_O1_I4(r, r, re, r, 0); + case INDEX_op_div2_i32: case INDEX_op_div2_i64: case INDEX_op_divu2_i32: case INDEX_op_divu2_i64: - { - static const TCGTargetOpDef div2 - =3D { .args_ct_str =3D { "a", "d", "0", "1", "r" } }; - return &div2; - } + return C_O2_I3(a, d, 0, 1, r); + case INDEX_op_mulu2_i32: case INDEX_op_mulu2_i64: case INDEX_op_muls2_i32: case INDEX_op_muls2_i64: - { - static const TCGTargetOpDef mul2 - =3D { .args_ct_str =3D { "a", "d", "a", "r" } }; - return &mul2; - } + return C_O2_I2(a, d, a, r); + case INDEX_op_add2_i32: case INDEX_op_add2_i64: case INDEX_op_sub2_i32: case INDEX_op_sub2_i64: - { - static const TCGTargetOpDef arith2 - =3D { .args_ct_str =3D { "r", "r", "0", "1", "re", "re" } = }; - return &arith2; - } + return C_O2_I4(r, r, 0, 1, re, re); + case INDEX_op_ctz_i32: case INDEX_op_ctz_i64: - { - static const TCGTargetOpDef ctz[2] =3D { - { .args_ct_str =3D { "&r", "r", "r" } }, - { .args_ct_str =3D { "&r", "r", "rW" } }, - }; - return &ctz[have_bmi1]; - } + return have_bmi1 ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r); + case INDEX_op_clz_i32: case INDEX_op_clz_i64: - { - static const TCGTargetOpDef clz[2] =3D { - { .args_ct_str =3D { "&r", "r", "r" } }, - { .args_ct_str =3D { "&r", "r", "rW" } }, - }; - return &clz[have_lzcnt]; - } + return have_lzcnt ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r); =20 case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &r_L : &r_L_L; + return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS + ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); + case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &L_L : &L_L_L; + return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS + ? C_O0_I2(L, L) : C_O0_I3(L, L, L)); case INDEX_op_qemu_st8_i32: - return TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &s_L : &s_L_L; + return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS + ? C_O0_I2(s, L) : C_O0_I3(s, L, L)); + case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &r_L - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &r_r_L - : &r_r_L_L); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O2_I1(r, r= , L) + : C_O2_I2(r, r, L, L)); + case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &L_L - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &L_L_L - : &L_L_L_L); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(L, L) + : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O0_I3(L, L= , L) + : C_O0_I4(L, L, L, L)); =20 case INDEX_op_brcond2_i32: - { - static const TCGTargetOpDef b2 - =3D { .args_ct_str =3D { "r", "r", "ri", "ri" } }; - return &b2; - } + return C_O0_I4(r, r, ri, ri); + case INDEX_op_setcond2_i32: - { - static const TCGTargetOpDef s2 - =3D { .args_ct_str =3D { "r", "r", "r", "ri", "ri" } }; - return &s2; - } + return C_O1_I4(r, r, r, ri, ri); =20 case INDEX_op_ld_vec: - case INDEX_op_st_vec: case INDEX_op_dupm_vec: - return &x_r; + return C_O1_I1(x, r); + + case INDEX_op_st_vec: + return C_O0_I2(x, r); =20 case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -3171,21 +3110,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_dup2_vec: #endif - return &x_x_x; + return C_O1_I2(x, x, x); + case INDEX_op_abs_vec: case INDEX_op_dup_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: case INDEX_op_x86_psrldq_vec: - return &x_x; + return C_O1_I1(x, x); + case INDEX_op_x86_vpblendvb_vec: - return &x_x_x_x; + return C_O1_I3(x, x, x, x); =20 default: - break; + g_assert_not_reached(); } - return NULL; } =20 int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611952069; cv=none; d=zohomail.com; s=zohoarc; b=K7Ytk8Eh9hJSsHXsWR3QOsMwl0xi93j04n6PMKLT7L3FYChy7ntQxLeR+DCN8VbHvag3jgDNeIkVGIiM6Ccc77p5NSF36aD3g1CjKTiRR4xrl9FxxB1n2CqJhYGf24FT4XQ7FgQema0+C6N3VK3taF5/UlOoLPqEMScGRLoO7lU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611952069; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yh6CQ/u4FMynTm6CwOd3gnQrNiWMWBdGGe7JpvXoYoM=; b=WZs1+M5c/h+6R/PANjPpVcYQCV1GfKUA4wX5pSmbj6p9cBOt2HJopvqEeg/hFQD0HigajFkFAEHVVfsw2dIrEZ/POwyK7HCGB/DiDFWXu8EWPU+l3kzKIz4oIThqmcATw7QclGlUYGSTHxYujlqUh0nVN9q+bPpa3taQ0Xo4b/s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611952069687436.0405466627225; Fri, 29 Jan 2021 12:27:49 -0800 (PST) Received: from localhost ([::1]:58170 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5aMu-0001xL-EK for importer@patchew.org; Fri, 29 Jan 2021 15:27:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49224) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5a6f-0006k9-MX for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:11:01 -0500 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:36253) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5a6d-00088z-EV for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:11:01 -0500 Received: by mail-pg1-x52a.google.com with SMTP id c132so7418218pga.3 for ; Fri, 29 Jan 2021 12:10:58 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. 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b=T4soCcczGiXfRCR6wefL+zI/vu4dCdWRgYFZpDUIQwodIqAQLV6NE9o87/ZOPF9lrL NfLf3zpTnFb9uqUj/turK5OFKv6azLEXLj5bxhk6kE/cv9L9mdQbHDULeZjkL5zOZ0wt jHAIsLJtHvk0kUe+hlikMLhhsb8i47a1OPHwn8jMfyODsDarfTvfgHWY3/mjwm2+uqHj m8RSDzzZdKH4Ae0QavEDVFwpxgOrGM4PcqC8X70FVyL3nEFl7sYN7E41AanB02Fw9bdw HZ625h7SEZKTnuYFJk+AALV9ZkYPG7MZZZNvN8dp8M9P4pqoOKC4u4X7SXrihQyRbyEB d51Q== X-Gm-Message-State: AOAM5326Rd/kc+RkL4wwdegCZqbSRMz/fgfXeumsmQlPZxMdHQyMcWjK YGhZ2IpwDIFhnRVqTmcwrnLQH3+cPVSArWoZ X-Google-Smtp-Source: ABdhPJwRi0use4LOrG3qbwYcYprWiKGiSI6z11+t9ZutsaQzaF/mnBRYB/UKaGnHlijk1fn+6ijkqg== X-Received: by 2002:a63:d446:: with SMTP id i6mr6427973pgj.446.1611951057991; Fri, 29 Jan 2021 12:10:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 16/24] tcg/aarch64: Split out constraint sets to tcg-target-con-set.h Date: Fri, 29 Jan 2021 10:10:20 -1000 Message-Id: <20210129201028.787853-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129201028.787853-1-richard.henderson@linaro.org> References: <20210129201028.787853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-set.h | 36 +++++++++++++ tcg/aarch64/tcg-target.h | 1 + tcg/aarch64/tcg-target.c.inc | 86 +++++++++++--------------------- 3 files changed, 65 insertions(+), 58 deletions(-) create mode 100644 tcg/aarch64/tcg-target-con-set.h diff --git a/tcg/aarch64/tcg-target-con-set.h b/tcg/aarch64/tcg-target-con-= set.h new file mode 100644 index 0000000000..d6c6866878 --- /dev/null +++ b/tcg/aarch64/tcg-target-con-set.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Define AArch64 target-specific constraint sets. + * Copyright (c) 2021 Linaro + */ + +/* + * C_On_Im(...) defines a constraint set with outputs and inputs. + * Each operand should be a sequence of constraint letters as defined by + * tcg-target-con-str.h; the constraint combination is inclusive or. + */ +C_O0_I1(r) +C_O0_I2(lZ, l) +C_O0_I2(r, rA) +C_O0_I2(rZ, r) +C_O0_I2(w, r) +C_O1_I1(r, l) +C_O1_I1(r, r) +C_O1_I1(w, r) +C_O1_I1(w, w) +C_O1_I1(w, wr) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, r, r) +C_O1_I2(r, r, rA) +C_O1_I2(r, r, rAL) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rL) +C_O1_I2(r, rZ, rZ) +C_O1_I2(w, 0, w) +C_O1_I2(w, w, w) +C_O1_I2(w, w, wN) +C_O1_I2(w, w, wO) +C_O1_I2(w, w, wZ) +C_O1_I3(w, w, w, w) +C_O1_I4(r, r, rA, rZ, rZ) +C_O2_I4(r, r, rZ, rZ, rA, rMZ) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 5ec30dba25..200e9b5e0e 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -155,5 +155,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CON_SET_H =20 #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 42037c98fa..3c1ee39fd4 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2547,42 +2547,11 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,= unsigned vece, va_end(va); } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef w_w =3D { .args_ct_str =3D { "w", "w" } }; - static const TCGTargetOpDef w_r =3D { .args_ct_str =3D { "w", "r" } }; - static const TCGTargetOpDef w_wr =3D { .args_ct_str =3D { "w", "wr" } = }; - static const TCGTargetOpDef r_l =3D { .args_ct_str =3D { "r", "l" } }; - static const TCGTargetOpDef r_rA =3D { .args_ct_str =3D { "r", "rA" } = }; - static const TCGTargetOpDef rZ_r =3D { .args_ct_str =3D { "rZ", "r" } = }; - static const TCGTargetOpDef lZ_l =3D { .args_ct_str =3D { "lZ", "l" } = }; - static const TCGTargetOpDef r_r_r =3D { .args_ct_str =3D { "r", "r", "= r" } }; - static const TCGTargetOpDef w_w_w =3D { .args_ct_str =3D { "w", "w", "= w" } }; - static const TCGTargetOpDef w_0_w =3D { .args_ct_str =3D { "w", "0", "= w" } }; - static const TCGTargetOpDef w_w_wO =3D { .args_ct_str =3D { "w", "w", = "wO" } }; - static const TCGTargetOpDef w_w_wN =3D { .args_ct_str =3D { "w", "w", = "wN" } }; - static const TCGTargetOpDef w_w_wZ =3D { .args_ct_str =3D { "w", "w", = "wZ" } }; - static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; - static const TCGTargetOpDef r_r_rA =3D { .args_ct_str =3D { "r", "r", = "rA" } }; - static const TCGTargetOpDef r_r_rL =3D { .args_ct_str =3D { "r", "r", = "rL" } }; - static const TCGTargetOpDef r_r_rAL - =3D { .args_ct_str =3D { "r", "r", "rAL" } }; - static const TCGTargetOpDef dep - =3D { .args_ct_str =3D { "r", "0", "rZ" } }; - static const TCGTargetOpDef ext2 - =3D { .args_ct_str =3D { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef movc - =3D { .args_ct_str =3D { "r", "r", "rA", "rZ", "rZ" } }; - static const TCGTargetOpDef add2 - =3D { .args_ct_str =3D { "r", "r", "rZ", "rZ", "rA", "rMZ" } }; - static const TCGTargetOpDef w_w_w_w - =3D { .args_ct_str =3D { "w", "w", "w", "w" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -2621,7 +2590,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_extract_i64: case INDEX_op_sextract_i32: case INDEX_op_sextract_i64: - return &r_r; + return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: case INDEX_op_st16_i32: @@ -2630,7 +2599,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &rZ_r; + return C_O0_I2(rZ, r); =20 case INDEX_op_add_i32: case INDEX_op_add_i64: @@ -2638,7 +2607,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_sub_i64: case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - return &r_r_rA; + return C_O1_I2(r, r, rA); =20 case INDEX_op_mul_i32: case INDEX_op_mul_i64: @@ -2652,7 +2621,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_remu_i64: case INDEX_op_muluh_i64: case INDEX_op_mulsh_i64: - return &r_r_r; + return C_O1_I2(r, r, r); =20 case INDEX_op_and_i32: case INDEX_op_and_i64: @@ -2666,7 +2635,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_orc_i64: case INDEX_op_eqv_i32: case INDEX_op_eqv_i64: - return &r_r_rL; + return C_O1_I2(r, r, rL); =20 case INDEX_op_shl_i32: case INDEX_op_shr_i32: @@ -2678,42 +2647,42 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_sar_i64: case INDEX_op_rotl_i64: case INDEX_op_rotr_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); =20 case INDEX_op_clz_i32: case INDEX_op_ctz_i32: case INDEX_op_clz_i64: case INDEX_op_ctz_i64: - return &r_r_rAL; + return C_O1_I2(r, r, rAL); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_rA; + return C_O0_I2(r, rA); =20 case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return &movc; + return C_O1_I4(r, r, rA, rZ, rZ); =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return &r_l; + return C_O1_I1(r, l); case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - return &lZ_l; + return C_O0_I2(lZ, l); =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return &dep; + return C_O1_I2(r, 0, rZ); =20 case INDEX_op_extract2_i32: case INDEX_op_extract2_i64: - return &ext2; + return C_O1_I2(r, rZ, rZ); =20 case INDEX_op_add2_i32: case INDEX_op_add2_i64: case INDEX_op_sub2_i32: case INDEX_op_sub2_i64: - return &add2; + return C_O2_I4(r, r, rZ, rZ, rA, rMZ); =20 case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -2731,35 +2700,36 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: case INDEX_op_aa64_sshl_vec: - return &w_w_w; + return C_O1_I2(w, w, w); case INDEX_op_not_vec: case INDEX_op_neg_vec: case INDEX_op_abs_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: - return &w_w; + return C_O1_I1(w, w); case INDEX_op_ld_vec: - case INDEX_op_st_vec: case INDEX_op_dupm_vec: - return &w_r; + return C_O1_I1(w, r); + case INDEX_op_st_vec: + return C_O0_I2(w, r); case INDEX_op_dup_vec: - return &w_wr; + return C_O1_I1(w, wr); case INDEX_op_or_vec: case INDEX_op_andc_vec: - return &w_w_wO; + return C_O1_I2(w, w, wO); case INDEX_op_and_vec: case INDEX_op_orc_vec: - return &w_w_wN; + return C_O1_I2(w, w, wN); case INDEX_op_cmp_vec: - return &w_w_wZ; + return C_O1_I2(w, w, wZ); case INDEX_op_bitsel_vec: - return &w_w_w_w; + return C_O1_I3(w, w, w, w); case INDEX_op_aa64_sli_vec: - return &w_0_w; + return C_O1_I2(w, 0, w); =20 default: - return NULL; + g_assert_not_reached(); } } =20 --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611952182; cv=none; d=zohomail.com; s=zohoarc; b=lg1LnaPMp+5hGbALjlSYSj4fme9atRj15cUjUEm96DTSv+JENqkKU8TejUo1pKWDaECp5lfIdxrENcJBaAOt52Mq4hIAsssixqMyp7HAOTjlsMBrMYMY5N0W466Qyekvf8MAeWX7u3LlI3QX+HvTcbD9hwL0xY0FCB+wH3GEnAg= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-con-set.h | 35 ++++++++++++++ tcg/arm/tcg-target.h | 1 + tcg/arm/tcg-target.c.inc | 94 ++++++++++++------------------------ 3 files changed, 68 insertions(+), 62 deletions(-) create mode 100644 tcg/arm/tcg-target-con-set.h diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h new file mode 100644 index 0000000000..ab63e089c2 --- /dev/null +++ b/tcg/arm/tcg-target-con-set.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define Arm target-specific constraint sets. + * Copyright (c) 2021 Linaro + */ + +/* + * C_On_Im(...) defines a constraint set with outputs and inputs. + * Each operand should be a sequence of constraint letters as defined by + * tcg-target-con-str.h; the constraint combination is inclusive or. + */ +C_O0_I1(r) +C_O0_I2(r, r) +C_O0_I2(r, rIN) +C_O0_I2(s, s) +C_O0_I3(s, s, s) +C_O0_I4(r, r, rI, rI) +C_O0_I4(s, s, s, s) +C_O1_I1(r, l) +C_O1_I1(r, r) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, l, l) +C_O1_I2(r, r, r) +C_O1_I2(r, r, rI) +C_O1_I2(r, r, rIK) +C_O1_I2(r, r, rIN) +C_O1_I2(r, r, ri) +C_O1_I2(r, rZ, rZ) +C_O1_I4(r, r, r, rI, rI) +C_O1_I4(r, r, rIN, rIK, 0) +C_O2_I1(r, r, l) +C_O2_I2(r, r, l, l) +C_O2_I2(r, r, r, r) +C_O2_I4(r, r, r, r, rIN, rIK) +C_O2_I4(r, r, rI, rI, rIN, rIK) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 8d1fee6327..4d201b1216 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -142,5 +142,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CON_SET_H =20 #endif diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index bbd41d2491..8457108a87 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2036,57 +2036,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, } } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef s_s =3D { .args_ct_str =3D { "s", "s" } }; - static const TCGTargetOpDef r_l =3D { .args_ct_str =3D { "r", "l" } }; - static const TCGTargetOpDef r_r_r =3D { .args_ct_str =3D { "r", "r", "= r" } }; - static const TCGTargetOpDef r_r_l =3D { .args_ct_str =3D { "r", "r", "= l" } }; - static const TCGTargetOpDef r_l_l =3D { .args_ct_str =3D { "r", "l", "= l" } }; - static const TCGTargetOpDef s_s_s =3D { .args_ct_str =3D { "s", "s", "= s" } }; - static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; - static const TCGTargetOpDef r_r_rI =3D { .args_ct_str =3D { "r", "r", = "rI" } }; - static const TCGTargetOpDef r_r_rIN - =3D { .args_ct_str =3D { "r", "r", "rIN" } }; - static const TCGTargetOpDef r_r_rIK - =3D { .args_ct_str =3D { "r", "r", "rIK" } }; - static const TCGTargetOpDef r_r_r_r - =3D { .args_ct_str =3D { "r", "r", "r", "r" } }; - static const TCGTargetOpDef r_r_l_l - =3D { .args_ct_str =3D { "r", "r", "l", "l" } }; - static const TCGTargetOpDef s_s_s_s - =3D { .args_ct_str =3D { "s", "s", "s", "s" } }; - static const TCGTargetOpDef br - =3D { .args_ct_str =3D { "r", "rIN" } }; - static const TCGTargetOpDef ext2 - =3D { .args_ct_str =3D { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef dep - =3D { .args_ct_str =3D { "r", "0", "rZ" } }; - static const TCGTargetOpDef movc - =3D { .args_ct_str =3D { "r", "r", "rIN", "rIK", "0" } }; - static const TCGTargetOpDef add2 - =3D { .args_ct_str =3D { "r", "r", "r", "r", "rIN", "rIK" } }; - static const TCGTargetOpDef sub2 - =3D { .args_ct_str =3D { "r", "r", "rI", "rI", "rIN", "rIK" } }; - static const TCGTargetOpDef br2 - =3D { .args_ct_str =3D { "r", "r", "rI", "rI" } }; - static const TCGTargetOpDef setc2 - =3D { .args_ct_str =3D { "r", "r", "r", "rI", "rI" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: case INDEX_op_ld16s_i32: case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: - case INDEX_op_st_i32: case INDEX_op_neg_i32: case INDEX_op_not_i32: case INDEX_op_bswap16_i32: @@ -2096,62 +2056,72 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_ext16u_i32: case INDEX_op_extract_i32: case INDEX_op_sextract_i32: - return &r_r; + return C_O1_I1(r, r); + + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + return C_O0_I2(r, r); =20 case INDEX_op_add_i32: case INDEX_op_sub_i32: case INDEX_op_setcond_i32: - return &r_r_rIN; + return C_O1_I2(r, r, rIN); + case INDEX_op_and_i32: case INDEX_op_andc_i32: case INDEX_op_clz_i32: case INDEX_op_ctz_i32: - return &r_r_rIK; + return C_O1_I2(r, r, rIK); + case INDEX_op_mul_i32: case INDEX_op_div_i32: case INDEX_op_divu_i32: - return &r_r_r; + return C_O1_I2(r, r, r); + case INDEX_op_mulu2_i32: case INDEX_op_muls2_i32: - return &r_r_r_r; + return C_O2_I2(r, r, r, r); + case INDEX_op_or_i32: case INDEX_op_xor_i32: - return &r_r_rI; + return C_O1_I2(r, r, rI); + case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: case INDEX_op_rotl_i32: case INDEX_op_rotr_i32: - return &r_r_ri; + return C_O1_I2(r, r, ri); =20 case INDEX_op_brcond_i32: - return &br; + return C_O0_I2(r, rIN); case INDEX_op_deposit_i32: - return &dep; + return C_O1_I2(r, 0, rZ); case INDEX_op_extract2_i32: - return &ext2; + return C_O1_I2(r, rZ, rZ); case INDEX_op_movcond_i32: - return &movc; + return C_O1_I4(r, r, rIN, rIK, 0); case INDEX_op_add2_i32: - return &add2; + return C_O2_I4(r, r, r, r, rIN, rIK); case INDEX_op_sub2_i32: - return &sub2; + return C_O2_I4(r, r, rI, rI, rIN, rIK); case INDEX_op_brcond2_i32: - return &br2; + return C_O0_I4(r, r, rI, rI); case INDEX_op_setcond2_i32: - return &setc2; + return C_O1_I4(r, r, r, rI, rI); =20 case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS =3D=3D 32 ? &r_l : &r_l_l; + return TARGET_LONG_BITS =3D=3D 32 ? C_O1_I1(r, l) : C_O1_I2(r, l, = l); case INDEX_op_qemu_ld_i64: - return TARGET_LONG_BITS =3D=3D 32 ? &r_r_l : &r_r_l_l; + return TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, l) : C_O2_I2(r, = r, l, l); case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS =3D=3D 32 ? &s_s : &s_s_s; + return TARGET_LONG_BITS =3D=3D 32 ? C_O0_I2(s, s) : C_O0_I3(s, s, = s); case INDEX_op_qemu_st_i64: - return TARGET_LONG_BITS =3D=3D 32 ? &s_s_s : &s_s_s_s; + return TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, = s, s, s); =20 default: - return NULL; + g_assert_not_reached(); } } =20 --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611951964; cv=none; d=zohomail.com; s=zohoarc; b=bknip1Dxv0aLCIe04HfPgh+JSl1NMCvNKTL0eiYFRyZJWI9mTdgMfyJGKZ09h0LTY5DF/84eP8oFzRcBjDmLPQDQcMBNqrYqcQsmTo2TU5A8vWJL20roMVIngyVIkX9YDNRCeCuSQuqz4NBoozKql4Oa1VuMm18C+7Z7mF+3zE0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611951964; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VUVejRK81rsj4L29tUqUpPwwe85/JVUx2UgkVy5ibcg=; b=eczjbiParcv4NAlPMTKp9+IEj0HZN4aqXYRB848b5eQvemQOn45ko7l9lgtuL0Ed4YqBN628hBB6yglzNutx8wbpSmuUwQZkCYKI+zLqdotDynCov3h83AXSwtMTn+6Pbb/zCV78IHXu5lEXZVFNK9Ok+D+YKA9rxukaT3pAuNw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611951964532834.6174487654089; Fri, 29 Jan 2021 12:26:04 -0800 (PST) Received: from localhost ([::1]:51046 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5aLD-0007RA-Bj for importer@patchew.org; Fri, 29 Jan 2021 15:26:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49286) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5a6j-0006uI-VA for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:11:05 -0500 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:37163) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5a6g-0008AK-ET for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:11:05 -0500 Received: by mail-pf1-x436.google.com with SMTP id b145so127757pfb.4 for ; Fri, 29 Jan 2021 12:11:01 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h | 36 +++++++++++++ tcg/mips/tcg-target.h | 1 + tcg/mips/tcg-target.c.inc | 96 +++++++++++------------------------ 3 files changed, 66 insertions(+), 67 deletions(-) create mode 100644 tcg/mips/tcg-target-con-set.h diff --git a/tcg/mips/tcg-target-con-set.h b/tcg/mips/tcg-target-con-set.h new file mode 100644 index 0000000000..fe3e868a2f --- /dev/null +++ b/tcg/mips/tcg-target-con-set.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define MIPS target-specific constraint sets. + * Copyright (c) 2021 Linaro + */ + +/* + * C_On_Im(...) defines a constraint set with outputs and inputs. + * Each operand should be a sequence of constraint letters as defined by + * tcg-target-con-str.h; the constraint combination is inclusive or. + */ +C_O0_I1(r) +C_O0_I2(rZ, r) +C_O0_I2(rZ, rZ) +C_O0_I2(SZ, S) +C_O0_I3(SZ, S, S) +C_O0_I3(SZ, SZ, S) +C_O0_I4(rZ, rZ, rZ, rZ) +C_O0_I4(SZ, SZ, S, S) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, L, L) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) +C_O1_I2(r, r, rIK) +C_O1_I2(r, r, rJ) +C_O1_I2(r, r, rWZ) +C_O1_I2(r, rZ, rN) +C_O1_I2(r, rZ, rZ) +C_O1_I4(r, rZ, rZ, rZ, 0) +C_O1_I4(r, rZ, rZ, rZ, rZ) +C_O2_I1(r, r, L) +C_O2_I2(r, r, L, L) +C_O2_I2(r, r, r, r) +C_O2_I4(r, r, rZ, rZ, rN, rN) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c2c32fb38f..e520a9d6e3 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -207,5 +207,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif +#define TCG_TARGET_CON_SET_H =20 #endif diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 432d38a010..ab55f3109b 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2112,52 +2112,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, } } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; - static const TCGTargetOpDef rZ_r =3D { .args_ct_str =3D { "rZ", "r" } = }; - static const TCGTargetOpDef SZ_S =3D { .args_ct_str =3D { "SZ", "S" } = }; - static const TCGTargetOpDef rZ_rZ =3D { .args_ct_str =3D { "rZ", "rZ" = } }; - static const TCGTargetOpDef r_r_L =3D { .args_ct_str =3D { "r", "r", "= L" } }; - static const TCGTargetOpDef r_L_L =3D { .args_ct_str =3D { "r", "L", "= L" } }; - static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; - static const TCGTargetOpDef r_r_rI =3D { .args_ct_str =3D { "r", "r", = "rI" } }; - static const TCGTargetOpDef r_r_rJ =3D { .args_ct_str =3D { "r", "r", = "rJ" } }; - static const TCGTargetOpDef SZ_S_S =3D { .args_ct_str =3D { "SZ", "S",= "S" } }; - static const TCGTargetOpDef SZ_SZ_S - =3D { .args_ct_str =3D { "SZ", "SZ", "S" } }; - static const TCGTargetOpDef SZ_SZ_S_S - =3D { .args_ct_str =3D { "SZ", "SZ", "S", "S" } }; - static const TCGTargetOpDef r_rZ_rN - =3D { .args_ct_str =3D { "r", "rZ", "rN" } }; - static const TCGTargetOpDef r_rZ_rZ - =3D { .args_ct_str =3D { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef r_r_rIK - =3D { .args_ct_str =3D { "r", "r", "rIK" } }; - static const TCGTargetOpDef r_r_rWZ - =3D { .args_ct_str =3D { "r", "r", "rWZ" } }; - static const TCGTargetOpDef r_r_r_r - =3D { .args_ct_str =3D { "r", "r", "r", "r" } }; - static const TCGTargetOpDef r_r_L_L - =3D { .args_ct_str =3D { "r", "r", "L", "L" } }; - static const TCGTargetOpDef dep - =3D { .args_ct_str =3D { "r", "0", "rZ" } }; - static const TCGTargetOpDef movc - =3D { .args_ct_str =3D { "r", "rZ", "rZ", "rZ", "0" } }; - static const TCGTargetOpDef movc_r6 - =3D { .args_ct_str =3D { "r", "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef add2 - =3D { .args_ct_str =3D { "r", "r", "rZ", "rZ", "rN", "rN" } }; - static const TCGTargetOpDef br2 - =3D { .args_ct_str =3D { "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef setc2 - =3D { .args_ct_str =3D { "r", "rZ", "rZ", "rZ", "rZ" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -2190,7 +2149,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: case INDEX_op_extract_i64: - return &r_r; + return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: case INDEX_op_st16_i32: @@ -2199,14 +2158,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &rZ_r; + return C_O0_I2(rZ, r); =20 case INDEX_op_add_i32: case INDEX_op_add_i64: - return &r_r_rJ; + return C_O1_I2(r, r, rJ); case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return &r_rZ_rN; + return C_O1_I2(r, rZ, rN); case INDEX_op_mul_i32: case INDEX_op_mulsh_i32: case INDEX_op_muluh_i32: @@ -2225,20 +2184,20 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_remu_i64: case INDEX_op_nor_i64: case INDEX_op_setcond_i64: - return &r_rZ_rZ; + return C_O1_I2(r, rZ, rZ); case INDEX_op_muls2_i32: case INDEX_op_mulu2_i32: case INDEX_op_muls2_i64: case INDEX_op_mulu2_i64: - return &r_r_r_r; + return C_O2_I2(r, r, r, r); case INDEX_op_and_i32: case INDEX_op_and_i64: - return &r_r_rIK; + return C_O1_I2(r, r, rIK); case INDEX_op_or_i32: case INDEX_op_xor_i32: case INDEX_op_or_i64: case INDEX_op_xor_i64: - return &r_r_rI; + return C_O1_I2(r, r, rI); case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: @@ -2249,44 +2208,47 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_sar_i64: case INDEX_op_rotr_i64: case INDEX_op_rotl_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); case INDEX_op_clz_i32: case INDEX_op_clz_i64: - return &r_r_rWZ; + return C_O1_I2(r, r, rWZ); =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return &dep; + return C_O1_I2(r, 0, rZ); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &rZ_rZ; + return C_O0_I2(rZ, rZ); case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return use_mips32r6_instructions ? &movc_r6 : &movc; - + return (use_mips32r6_instructions + ? C_O1_I4(r, rZ, rZ, rZ, rZ) + : C_O1_I4(r, rZ, rZ, rZ, 0)); case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - return &add2; + return C_O2_I4(r, r, rZ, rZ, rN, rN); case INDEX_op_setcond2_i32: - return &setc2; + return C_O1_I4(r, rZ, rZ, rZ, rZ); case INDEX_op_brcond2_i32: - return &br2; + return C_O0_I4(rZ, rZ, rZ, rZ); =20 case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? &r_L : &r_L_L); + ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? &SZ_S : &SZ_S_S); + ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S)); case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &r_L - : TARGET_LONG_BITS =3D=3D 32 ? &r_r_L : &r_r_L_L); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, L) + : C_O2_I2(r, r, L, L)); case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &SZ_S - : TARGET_LONG_BITS =3D=3D 32 ? &SZ_SZ_S : &SZ_SZ_S_S); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(SZ, S) + : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(SZ, SZ, S) + : C_O0_I4(SZ, SZ, S, S)); =20 default: - return NULL; + g_assert_not_reached(); } } =20 --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611952061; cv=none; d=zohomail.com; s=zohoarc; b=maLqUOiq0kleZYgGrSgos2Ohky21ew9vHu6sF4RMLRtBO6lRy+GI5sCLYhVLbVbgom5OsqdNaBXox3oaibMsTlewOUin8gU1ZKOExs0xYx4qwVLvsycSGGivaMCa92yTU4vDaOBDaXpR1NVulyNZynf3ZXRdTMos1dGr3LVMvDY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611952061; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rkcGYRpavy8b7NvBkTDEXauxxj6OsYUBpOL3Xp6QZQ8=; b=iahAcMIah5701STefpkl1LbMWlOmuxdydb3rqKvAoxfuw0LppkUqpGlZtlPN8LgGK2HwXL8apHsChsnU7YbKvcTUIWQ9S8WNDwEPXKYXglgyhajqCw7i2kbYQn+niwqWqllwh1mRgH9+BYBOCZ9m4aLv0Tm3eJZlA/w0I5uIRho= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611952061489346.9510266389167; Fri, 29 Jan 2021 12:27:41 -0800 (PST) Received: from localhost ([::1]:57234 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5aMm-0001aO-Ck for importer@patchew.org; Fri, 29 Jan 2021 15:27:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49296) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5a6k-0006vX-GP for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:11:06 -0500 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:36847) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5a6i-0008BQ-4Y for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:11:06 -0500 Received: by mail-pf1-x42b.google.com with SMTP id u67so6925919pfb.3 for ; Fri, 29 Jan 2021 12:11:03 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 42 +++++++++++ tcg/ppc/tcg-target.h | 1 + tcg/ppc/tcg-target.c.inc | 136 +++++++++++++++-------------------- 3 files changed, 99 insertions(+), 80 deletions(-) create mode 100644 tcg/ppc/tcg-target-con-set.h diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h new file mode 100644 index 0000000000..a1a345883d --- /dev/null +++ b/tcg/ppc/tcg-target-con-set.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define PowerPC target-specific constraint sets. + * Copyright (c) 2021 Linaro + */ + +/* + * C_On_Im(...) defines a constraint set with outputs and inputs. + * Each operand should be a sequence of constraint letters as defined by + * tcg-target-con-str.h; the constraint combination is inclusive or. + */ +C_O0_I1(r) +C_O0_I2(r, r) +C_O0_I2(r, ri) +C_O0_I2(S, S) +C_O0_I2(v, r) +C_O0_I3(S, S, S) +C_O0_I4(r, r, ri, ri) +C_O0_I4(S, S, S, S) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I1(v, r) +C_O1_I1(v, v) +C_O1_I1(v, vr) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, L, L) +C_O1_I2(r, rI, ri) +C_O1_I2(r, rI, rT) +C_O1_I2(r, r, r) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) +C_O1_I2(r, r, rT) +C_O1_I2(r, r, rU) +C_O1_I2(r, r, rZW) +C_O1_I2(v, v, v) +C_O1_I3(v, v, v, v) +C_O1_I4(r, r, ri, rZ, rZ) +C_O1_I4(r, r, r, ri, ri) +C_O2_I1(L, L, L) +C_O2_I2(L, L, L, L) +C_O2_I4(r, r, rI, rZM, r, r) +C_O2_I4(r, r, r, r, rI, rZM) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index d1339afc66..551f8d0fc9 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -185,5 +185,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CON_SET_H =20 #endif diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index e5aa8d2d10..4377d15d62 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3456,62 +3456,17 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,= unsigned vece, va_end(va); } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; - static const TCGTargetOpDef S_S =3D { .args_ct_str =3D { "S", "S" } }; - static const TCGTargetOpDef r_ri =3D { .args_ct_str =3D { "r", "ri" } = }; - static const TCGTargetOpDef r_r_r =3D { .args_ct_str =3D { "r", "r", "= r" } }; - static const TCGTargetOpDef r_L_L =3D { .args_ct_str =3D { "r", "L", "= L" } }; - static const TCGTargetOpDef L_L_L =3D { .args_ct_str =3D { "L", "L", "= L" } }; - static const TCGTargetOpDef S_S_S =3D { .args_ct_str =3D { "S", "S", "= S" } }; - static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; - static const TCGTargetOpDef r_r_rI =3D { .args_ct_str =3D { "r", "r", = "rI" } }; - static const TCGTargetOpDef r_r_rT =3D { .args_ct_str =3D { "r", "r", = "rT" } }; - static const TCGTargetOpDef r_r_rU =3D { .args_ct_str =3D { "r", "r", = "rU" } }; - static const TCGTargetOpDef r_rI_ri - =3D { .args_ct_str =3D { "r", "rI", "ri" } }; - static const TCGTargetOpDef r_rI_rT - =3D { .args_ct_str =3D { "r", "rI", "rT" } }; - static const TCGTargetOpDef r_r_rZW - =3D { .args_ct_str =3D { "r", "r", "rZW" } }; - static const TCGTargetOpDef L_L_L_L - =3D { .args_ct_str =3D { "L", "L", "L", "L" } }; - static const TCGTargetOpDef S_S_S_S - =3D { .args_ct_str =3D { "S", "S", "S", "S" } }; - static const TCGTargetOpDef movc - =3D { .args_ct_str =3D { "r", "r", "ri", "rZ", "rZ" } }; - static const TCGTargetOpDef dep - =3D { .args_ct_str =3D { "r", "0", "rZ" } }; - static const TCGTargetOpDef br2 - =3D { .args_ct_str =3D { "r", "r", "ri", "ri" } }; - static const TCGTargetOpDef setc2 - =3D { .args_ct_str =3D { "r", "r", "r", "ri", "ri" } }; - static const TCGTargetOpDef add2 - =3D { .args_ct_str =3D { "r", "r", "r", "r", "rI", "rZM" } }; - static const TCGTargetOpDef sub2 - =3D { .args_ct_str =3D { "r", "r", "rI", "rZM", "r", "r" } }; - static const TCGTargetOpDef v_r =3D { .args_ct_str =3D { "v", "r" } }; - static const TCGTargetOpDef v_vr =3D { .args_ct_str =3D { "v", "vr" } = }; - static const TCGTargetOpDef v_v =3D { .args_ct_str =3D { "v", "v" } }; - static const TCGTargetOpDef v_v_v =3D { .args_ct_str =3D { "v", "v", "= v" } }; - static const TCGTargetOpDef v_v_v_v - =3D { .args_ct_str =3D { "v", "v", "v", "v" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: case INDEX_op_ld16s_i32: case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: - case INDEX_op_st_i32: case INDEX_op_ctpop_i32: case INDEX_op_neg_i32: case INDEX_op_not_i32: @@ -3527,10 +3482,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: case INDEX_op_ctpop_i64: case INDEX_op_neg_i64: case INDEX_op_not_i64: @@ -3543,7 +3494,16 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_bswap32_i64: case INDEX_op_bswap64_i64: case INDEX_op_extract_i64: - return &r_r; + return C_O1_I1(r, r); + + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return C_O0_I2(r, r); =20 case INDEX_op_add_i32: case INDEX_op_and_i32: @@ -3566,10 +3526,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_rotl_i64: case INDEX_op_rotr_i64: case INDEX_op_setcond_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); + case INDEX_op_mul_i32: case INDEX_op_mul_i64: - return &r_r_rI; + return C_O1_I2(r, r, rI); + case INDEX_op_div_i32: case INDEX_op_divu_i32: case INDEX_op_nand_i32: @@ -3584,55 +3546,63 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_divu_i64: case INDEX_op_mulsh_i64: case INDEX_op_muluh_i64: - return &r_r_r; + return C_O1_I2(r, r, r); + case INDEX_op_sub_i32: - return &r_rI_ri; + return C_O1_I2(r, rI, ri); case INDEX_op_add_i64: - return &r_r_rT; + return C_O1_I2(r, r, rT); case INDEX_op_or_i64: case INDEX_op_xor_i64: - return &r_r_rU; + return C_O1_I2(r, r, rU); case INDEX_op_sub_i64: - return &r_rI_rT; + return C_O1_I2(r, rI, rT); case INDEX_op_clz_i32: case INDEX_op_ctz_i32: case INDEX_op_clz_i64: case INDEX_op_ctz_i64: - return &r_r_rZW; + return C_O1_I2(r, r, rZW); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_ri; + return C_O0_I2(r, ri); =20 case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return &movc; + return C_O1_I4(r, r, ri, rZ, rZ); case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return &dep; + return C_O1_I2(r, 0, rZ); case INDEX_op_brcond2_i32: - return &br2; + return C_O0_I4(r, r, ri, ri); case INDEX_op_setcond2_i32: - return &setc2; + return C_O1_I4(r, r, r, ri, ri); case INDEX_op_add2_i64: case INDEX_op_add2_i32: - return &add2; + return C_O2_I4(r, r, r, r, rI, rZM); case INDEX_op_sub2_i64: case INDEX_op_sub2_i32: - return &sub2; + return C_O2_I4(r, r, rI, rZM, r, r); =20 case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? &r_L : &r_L_L); + ? C_O1_I1(r, L) + : C_O1_I2(r, L, L)); + case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? &S_S : &S_S_S); + ? C_O0_I2(S, S) + : C_O0_I3(S, S, S)); + case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &r_L - : TARGET_LONG_BITS =3D=3D 32 ? &L_L_L : &L_L_L_L); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(L, L, L) + : C_O2_I2(L, L, L, L)); + case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &S_S - : TARGET_LONG_BITS =3D=3D 32 ? &S_S_S : &S_S_S_S); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(S, S) + : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(S, S, S) + : C_O0_I4(S, S, S, S)); =20 case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -3662,22 +3632,28 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_ppc_mulou_vec: case INDEX_op_ppc_pkum_vec: case INDEX_op_dup2_vec: - return &v_v_v; + return C_O1_I2(v, v, v); + case INDEX_op_not_vec: case INDEX_op_neg_vec: - return &v_v; + return C_O1_I1(v, v); + case INDEX_op_dup_vec: - return have_isa_3_00 ? &v_vr : &v_v; + return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v); + case INDEX_op_ld_vec: - case INDEX_op_st_vec: case INDEX_op_dupm_vec: - return &v_r; + return C_O1_I1(v, r); + + case INDEX_op_st_vec: + return C_O0_I2(v, r); + case INDEX_op_bitsel_vec: case INDEX_op_ppc_msum_vec: - return &v_v_v_v; + return C_O1_I3(v, v, v, v); =20 default: - return NULL; + g_assert_not_reached(); } } =20 --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611951728; cv=none; d=zohomail.com; s=zohoarc; b=e372APy9E59ZlSQxj+E7m5uA0eiRp6ZlWnmzoujy0ydYEW2m65i4uhyhO0JROt6BZKQ2dx398HIh6JGAAlY77rm4caGJlC1OfDMnCU8vJZMWbRdQs12JuPIUopdZZZBTo9abgAbeSmNAlGBCYXdCLRsDBBdTI4p4FsHRkzInoE0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611951728; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dgFs0kRvG3YRS9ydc6sjoVZGH6LkBq65P9PIXpXmt7w=; b=WADFLWUe7MLxlQ/P82GLsAkeGJ0486tMBCA2yIYAUtkz9ePV8Bosu+z6FcYkyrRcyIeAd7C+p2PjkC5Ascr4j/7/hLykvOFyZQGgKzqQX/BjgRv2BDpDTnQSEw8N63YYdvWuQwLxJapMfcLgS0IFPJqRVhcpptfYCFgryxiRWv4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611951728047277.35932907913116; Fri, 29 Jan 2021 12:22:08 -0800 (PST) Received: from localhost ([::1]:35776 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5aHO-00016A-Os for importer@patchew.org; Fri, 29 Jan 2021 15:22:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49314) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5a6l-0006ya-Si for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:11:07 -0500 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:46312) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5a6j-0008Bd-Px for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:11:07 -0500 Received: by mail-pg1-x534.google.com with SMTP id r38so7387938pgk.13 for ; Fri, 29 Jan 2021 12:11:05 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 30 ++++++++++++ tcg/riscv/tcg-target.h | 1 + tcg/riscv/tcg-target.c.inc | 83 ++++++++++------------------------ 3 files changed, 54 insertions(+), 60 deletions(-) create mode 100644 tcg/riscv/tcg-target-con-set.h diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h new file mode 100644 index 0000000000..cf0ac4d751 --- /dev/null +++ b/tcg/riscv/tcg-target-con-set.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define RISC-V target-specific constraint sets. + * Copyright (c) 2021 Linaro + */ + +/* + * C_On_Im(...) defines a constraint set with outputs and inputs. + * Each operand should be a sequence of constraint letters as defined by + * tcg-target-con-str.h; the constraint combination is inclusive or. + */ +C_O0_I1(r) +C_O0_I2(LZ, L) +C_O0_I2(rZ, r) +C_O0_I2(rZ, rZ) +C_O0_I3(LZ, L, L) +C_O0_I3(LZ, LZ, L) +C_O0_I4(LZ, LZ, L, L) +C_O0_I4(rZ, rZ, rZ, rZ) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, L, L) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) +C_O1_I2(r, rZ, rN) +C_O1_I2(r, rZ, rZ) +C_O1_I4(r, rZ, rZ, rZ, rZ) +C_O2_I1(r, r, L) +C_O2_I2(r, r, L, L) +C_O2_I4(r, r, rZ, rZ, rM, rM) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 727c8df418..a998b951e4 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -171,5 +171,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 0 +#define TCG_TARGET_CON_SET_H =20 #endif diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 20d5b5ef01..e700c52067 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1543,50 +1543,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r - =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef r_r - =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef rZ_r - =3D { .args_ct_str =3D { "rZ", "r" } }; - static const TCGTargetOpDef rZ_rZ - =3D { .args_ct_str =3D { "rZ", "rZ" } }; - static const TCGTargetOpDef rZ_rZ_rZ_rZ - =3D { .args_ct_str =3D { "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef r_r_ri - =3D { .args_ct_str =3D { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI - =3D { .args_ct_str =3D { "r", "r", "rI" } }; - static const TCGTargetOpDef r_rZ_rN - =3D { .args_ct_str =3D { "r", "rZ", "rN" } }; - static const TCGTargetOpDef r_rZ_rZ - =3D { .args_ct_str =3D { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef r_rZ_rZ_rZ_rZ - =3D { .args_ct_str =3D { "r", "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef r_L - =3D { .args_ct_str =3D { "r", "L" } }; - static const TCGTargetOpDef r_r_L - =3D { .args_ct_str =3D { "r", "r", "L" } }; - static const TCGTargetOpDef r_L_L - =3D { .args_ct_str =3D { "r", "L", "L" } }; - static const TCGTargetOpDef r_r_L_L - =3D { .args_ct_str =3D { "r", "r", "L", "L" } }; - static const TCGTargetOpDef LZ_L - =3D { .args_ct_str =3D { "LZ", "L" } }; - static const TCGTargetOpDef LZ_L_L - =3D { .args_ct_str =3D { "LZ", "L", "L" } }; - static const TCGTargetOpDef LZ_LZ_L - =3D { .args_ct_str =3D { "LZ", "LZ", "L" } }; - static const TCGTargetOpDef LZ_LZ_L_L - =3D { .args_ct_str =3D { "LZ", "LZ", "L", "L" } }; - static const TCGTargetOpDef r_r_rZ_rZ_rM_rM - =3D { .args_ct_str =3D { "r", "r", "rZ", "rZ", "rM", "rM" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -1618,7 +1579,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: case INDEX_op_ext_i32_i64: - return &r_r; + return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: case INDEX_op_st16_i32: @@ -1627,7 +1588,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &rZ_r; + return C_O0_I2(rZ, r); =20 case INDEX_op_add_i32: case INDEX_op_and_i32: @@ -1637,11 +1598,11 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_and_i64: case INDEX_op_or_i64: case INDEX_op_xor_i64: - return &r_r_rI; + return C_O1_I2(r, r, rI); =20 case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return &r_rZ_rN; + return C_O1_I2(r, rZ, rN); =20 case INDEX_op_mul_i32: case INDEX_op_mulsh_i32: @@ -1659,7 +1620,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_rem_i64: case INDEX_op_remu_i64: case INDEX_op_setcond_i64: - return &r_rZ_rZ; + return C_O1_I2(r, rZ, rZ); =20 case INDEX_op_shl_i32: case INDEX_op_shr_i32: @@ -1667,39 +1628,41 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_shl_i64: case INDEX_op_shr_i64: case INDEX_op_sar_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &rZ_rZ; + return C_O0_I2(rZ, rZ); =20 case INDEX_op_add2_i32: case INDEX_op_add2_i64: case INDEX_op_sub2_i32: case INDEX_op_sub2_i64: - return &r_r_rZ_rZ_rM_rM; + return C_O2_I4(r, r, rZ, rZ, rM, rM); =20 case INDEX_op_brcond2_i32: - return &rZ_rZ_rZ_rZ; + return C_O0_I4(rZ, rZ, rZ, rZ); =20 case INDEX_op_setcond2_i32: - return &r_rZ_rZ_rZ_rZ; + return C_O1_I4(r, rZ, rZ, rZ, rZ); =20 case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &r_L : &r_L_L; + return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS + ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L; + return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS + ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L)); case INDEX_op_qemu_ld_i64: - return TCG_TARGET_REG_BITS =3D=3D 64 ? &r_L - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &r_r_L - : &r_r_L_L; + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O2_I1(r, r,= L) + : C_O2_I2(r, r, L, L)); case INDEX_op_qemu_st_i64: - return TCG_TARGET_REG_BITS =3D=3D 64 ? &LZ_L - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &LZ_LZ_L - : &LZ_LZ_L_L; + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(LZ, L) + : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O0_I3(LZ, L= Z, L) + : C_O0_I4(LZ, LZ, L, L)); =20 default: - return NULL; + g_assert_not_reached(); } } =20 --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611952289; cv=none; d=zohomail.com; s=zohoarc; b=hMvMU7IGTa4bgGRNke7yF6cJ6ITFJnjR1pm4h4vpjAAc1pelPIIL9xlm/ueNzfRbxMJm1f8dstoaRkjaojG9eDR9NefeCB8EpGXiQG9CJ2R4frNvEEqH5dvs9RpleLQvlPy9HgCEiGPzAilXpFz8UPsRysfTOIeqZsVe7ftzfGg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611952289; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=r9IaFnuOJyGGSYzX0XtrIiH13SIPJFOeAOWyCMY/qyI=; b=iXcB7i+ttH/OCw6mSB57kTmPOWEE3X4U1LpI6dAu2ul0ziRyntQEVF0ZKSiPR8Ev/hjYofwg5GQzzFWJiELNQ6WCl9a6gXcIDKrcxCZwOxc1OwZAZdQepxMwZcuZb6uvbgA3hpBhgPifFp10aC96W7zODCdJcpflrH+dv3RLsno= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611952289964247.00563371871772; Fri, 29 Jan 2021 12:31:29 -0800 (PST) Received: from localhost ([::1]:38680 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5aQS-0005cn-TP for importer@patchew.org; Fri, 29 Jan 2021 15:31:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49328) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5a6n-00072f-G6 for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:11:09 -0500 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:42266) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5a6l-0008Cq-An for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:11:09 -0500 Received: by mail-pf1-x42a.google.com with SMTP id w18so6907904pfu.9 for ; Fri, 29 Jan 2021 12:11:06 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id d133sm9247265pfd.6.2021.01.29.12.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 12:11:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=r9IaFnuOJyGGSYzX0XtrIiH13SIPJFOeAOWyCMY/qyI=; b=tlRLb++M8wfCcjdvZw0IRfS0L29rCq76ghCuJVMupjfyeR1H5Pan0CKy4AsMcnyTdZ /ASEJ+38wBkwGN1NzRU8h8GdW1PWH/RYLgMNQUgBtff/2jWXOY2BzDl0L75mLyc3AeeZ EQzQIkzPzNBQpqwtS1cDiDAqR46BEBRVvSN+EWMwFFeGFScWzG8kMpNbtUZbkRH84VcN p2bfoq1yJQkFsx2FSeJPACbGQ/Iquwl+UPg2Bt1EC+EEAVyLlknh55c4WeL6+37mgh4y AHhyq+7flidfU8S/L8Pv5y1GAgw1/M0fyUJf/wJsr81ZL3iI8usKk0V6U+hWL/il1bYA 7Hog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r9IaFnuOJyGGSYzX0XtrIiH13SIPJFOeAOWyCMY/qyI=; b=ZRTql/dJ2n9tE9b1dxSTn7VpltHVlCgLDeuWfwghF71qpxDU2CQ6JBGeA9XEKNHSvU 9B+y+ukQa/rWLiIVTxsfxdnJUQo8F7a7MX6bsapJfqIdtiMewSoMzAY1+UeQvfKieyd7 an/PVWtaXXufHfm22puPI78zCK2aWjHCRCkiBx604COdeXrnkhfynvEoKHffZEYd/Bi3 OqbP4wk1DYM9/TGCouVuZ9eBoaD5aj9Jcco6c3RrvKmYw4gAgdEjnpBRTg2772A9NHGc Q1qlCbQtFMpccic8sNXYP1C0ZGjeQ39MbOvMGYPlKsxvMRydUs8KCAFlwcxJYN/GdJp5 //9g== X-Gm-Message-State: AOAM5337YcwrOQ9S2RaSNGqqds0Pk8uUWe31kON2MzXjseveLD+cKxMY MpwYO8v92VD8HnV6BMLr8I/dwAvGHh4xuQVo X-Google-Smtp-Source: ABdhPJxUfI5ibBb1w8BEANehpnfdvJPn0Icj7SrjpCwE/PPccN9AHhKPempxT08NyPrLqthdNRh9VQ== X-Received: by 2002:a63:724a:: with SMTP id c10mr6465601pgn.124.1611951066049; Fri, 29 Jan 2021 12:11:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 21/24] tcg/s390: Split out constraint sets to tcg-target-con-set.h Date: Fri, 29 Jan 2021 10:10:25 -1000 Message-Id: <20210129201028.787853-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129201028.787853-1-richard.henderson@linaro.org> References: <20210129201028.787853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/s390/tcg-target-con-set.h | 29 ++++++++ tcg/s390/tcg-target.h | 1 + tcg/s390/tcg-target.c.inc | 121 ++++++++++++++-------------------- 3 files changed, 81 insertions(+), 70 deletions(-) create mode 100644 tcg/s390/tcg-target-con-set.h diff --git a/tcg/s390/tcg-target-con-set.h b/tcg/s390/tcg-target-con-set.h new file mode 100644 index 0000000000..31985e4903 --- /dev/null +++ b/tcg/s390/tcg-target-con-set.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define S390 target-specific constraint sets. + * Copyright (c) 2021 Linaro + */ + +/* + * C_On_Im(...) defines a constraint set with outputs and inputs. + * Each operand should be a sequence of constraint letters as defined by + * tcg-target-con-str.h; the constraint combination is inclusive or. + */ +C_O0_I1(r) +C_O0_I2(L, L) +C_O0_I2(r, r) +C_O0_I2(r, ri) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, 0, ri) +C_O1_I2(r, 0, rI) +C_O1_I2(r, 0, rJ) +C_O1_I2(r, r, ri) +C_O1_I2(r, rZ, r) +C_O1_I4(r, r, ri, r, 0) +C_O1_I4(r, r, ri, rI, 0) +C_O2_I2(b, a, 0, r) +C_O2_I3(b, a, 0, 1, r) +C_O2_I4(r, r, 0, 1, rA, r) +C_O2_I4(r, r, 0, 1, ri, r) +C_O2_I4(r, r, 0, 1, r, r) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 641464eea4..7aafd25a46 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -159,5 +159,6 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CON_SET_H =20 #endif diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 3fec7fec5f..b67470137c 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -2274,27 +2274,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, } } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; - static const TCGTargetOpDef L_L =3D { .args_ct_str =3D { "L", "L" } }; - static const TCGTargetOpDef r_ri =3D { .args_ct_str =3D { "r", "ri" } = }; - static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; - static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; - static const TCGTargetOpDef r_0_rI =3D { .args_ct_str =3D { "r", "0", = "rI" } }; - static const TCGTargetOpDef r_0_rJ =3D { .args_ct_str =3D { "r", "0", = "rJ" } }; - static const TCGTargetOpDef a2_r - =3D { .args_ct_str =3D { "r", "r", "0", "1", "r", "r" } }; - static const TCGTargetOpDef a2_ri - =3D { .args_ct_str =3D { "r", "r", "0", "1", "ri", "r" } }; - static const TCGTargetOpDef a2_rA - =3D { .args_ct_str =3D { "r", "r", "0", "1", "rA", "r" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: @@ -2308,6 +2292,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: + return C_O1_I1(r, r); + case INDEX_op_st8_i32: case INDEX_op_st8_i64: case INDEX_op_st16_i32: @@ -2315,11 +2301,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_st_i32: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &r_r; + return C_O0_I2(r, r); =20 case INDEX_op_add_i32: case INDEX_op_add_i64: - return &r_r_ri; + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + case INDEX_op_clz_i64: + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + return C_O1_I2(r, r, ri); + case INDEX_op_sub_i32: case INDEX_op_sub_i64: case INDEX_op_and_i32: @@ -2328,35 +2325,33 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: - return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); + return (s390_facilities & FACILITY_DISTINCT_OPS + ? C_O1_I2(r, r, ri) + : C_O1_I2(r, 0, ri)); =20 case INDEX_op_mul_i32: /* If we have the general-instruction-extensions, then we have MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ - return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_r= I); + return (s390_facilities & FACILITY_GEN_INST_EXT + ? C_O1_I2(r, 0, ri) + : C_O1_I2(r, 0, rI)); + case INDEX_op_mul_i64: - return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_r= I); + return (s390_facilities & FACILITY_GEN_INST_EXT + ? C_O1_I2(r, 0, rJ) + : C_O1_I2(r, 0, rI)); =20 case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: - return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); - - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - return &r_r_ri; - - case INDEX_op_rotl_i32: - case INDEX_op_rotl_i64: - case INDEX_op_rotr_i32: - case INDEX_op_rotr_i64: - return &r_r_ri; + return (s390_facilities & FACILITY_DISTINCT_OPS + ? C_O1_I2(r, r, ri) + : C_O1_I2(r, 0, ri)); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_ri; + return C_O0_I2(r, ri); =20 case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: @@ -2379,63 +2374,49 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_extu_i32_i64: case INDEX_op_extract_i32: case INDEX_op_extract_i64: - return &r_r; - - case INDEX_op_clz_i64: - case INDEX_op_setcond_i32: - case INDEX_op_setcond_i64: - return &r_r_ri; + return C_O1_I1(r, r); =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return &r_L; + return C_O1_I1(r, L); case INDEX_op_qemu_st_i64: case INDEX_op_qemu_st_i32: - return &L_L; + return C_O0_I2(L, L); =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - { - static const TCGTargetOpDef dep - =3D { .args_ct_str =3D { "r", "rZ", "r" } }; - return &dep; - } + return C_O1_I2(r, rZ, r); + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - { - static const TCGTargetOpDef movc - =3D { .args_ct_str =3D { "r", "r", "ri", "r", "0" } }; - static const TCGTargetOpDef movc_l - =3D { .args_ct_str =3D { "r", "r", "ri", "rI", "0" } }; - return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &= movc); - } + return (s390_facilities & FACILITY_LOAD_ON_COND2 + ? C_O1_I4(r, r, ri, rI, 0) + : C_O1_I4(r, r, ri, r, 0)); + case INDEX_op_div2_i32: case INDEX_op_div2_i64: case INDEX_op_divu2_i32: case INDEX_op_divu2_i64: - { - static const TCGTargetOpDef div2 - =3D { .args_ct_str =3D { "b", "a", "0", "1", "r" } }; - return &div2; - } + return C_O2_I3(b, a, 0, 1, r); + case INDEX_op_mulu2_i64: - { - static const TCGTargetOpDef mul2 - =3D { .args_ct_str =3D { "b", "a", "0", "r" } }; - return &mul2; - } + return C_O2_I2(b, a, 0, r); =20 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r); + return (s390_facilities & FACILITY_EXT_IMM + ? C_O2_I4(r, r, 0, 1, ri, r) + : C_O2_I4(r, r, 0, 1, r, r)); + case INDEX_op_add2_i64: case INDEX_op_sub2_i64: - return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r); + return (s390_facilities & FACILITY_EXT_IMM + ? C_O2_I4(r, r, 0, 1, rA, r) + : C_O2_I4(r, r, 0, 1, r, r)); =20 default: - break; + g_assert_not_reached(); } - return NULL; } =20 static void query_s390_facilities(void) --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611951881; cv=none; d=zohomail.com; s=zohoarc; b=LYEw2h5g2DBiut5i1w/3ocXBT76JVl+nsJDaeyGrP/d4Z1AvPln/7WtZO5vNGCYEaXxEkpWEC5Fshn8J76D5mFdGuZhBPpbdv8vLswuDc56GjzvOpHr0ERrn6lAniRF62Z2yL9ClGwnD6xV+KFbtMegh69Nmir8LmnH1k2qu2pE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611951881; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MrxaSWspF3/rQVGucPF5ZdPBIWEarIo2ZYIqCUeIYp8=; b=Hyb1OGYZFPJA3mWzX0sU3YK9giBIY72SHRwRbYBxv58s4rcjDxeIukmeNhGlQu1ZVJ/HF7fHsVU0unt4J/xprP646RM1jAsyNWznZv0LbG3NV3Tofnveny41RJEoC3xdOmU4maD3CIZhl/+wVSmMUN4xck1egkxfuEX9hgmH19M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1611951881563443.67358464901565; Fri, 29 Jan 2021 12:24:41 -0800 (PST) Received: from localhost ([::1]:45684 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5aJs-0005Cu-Io for importer@patchew.org; Fri, 29 Jan 2021 15:24:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49342) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5a6p-00076U-2M for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:11:11 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:34046) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5a6n-0008DP-1K for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:11:10 -0500 Received: by mail-pj1-x102d.google.com with SMTP id my11so6921185pjb.1 for ; Fri, 29 Jan 2021 12:11:08 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target-con-set.h | 32 +++++++++++++++ tcg/sparc/tcg-target.h | 1 + tcg/sparc/tcg-target.c.inc | 75 +++++++++++----------------------- 3 files changed, 56 insertions(+), 52 deletions(-) create mode 100644 tcg/sparc/tcg-target-con-set.h diff --git a/tcg/sparc/tcg-target-con-set.h b/tcg/sparc/tcg-target-con-set.h new file mode 100644 index 0000000000..3b751dc3fb --- /dev/null +++ b/tcg/sparc/tcg-target-con-set.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define Sparc target-specific constraint sets. + * Copyright (c) 2021 Linaro + */ + +/* + * C_On_Im(...) defines a constraint set with outputs and inputs. + * Each operand should be a sequence of constraint letters as defined by + * tcg-target-con-str.h; the constraint combination is inclusive or. + */ +C_O0_I1(r) +C_O0_I2(rZ, r) +C_O0_I2(RZ, r) +C_O0_I2(rZ, rJ) +C_O0_I2(RZ, RJ) +C_O0_I2(sZ, A) +C_O0_I2(SZ, A) +C_O1_I1(r, A) +C_O1_I1(R, A) +C_O1_I1(r, r) +C_O1_I1(r, R) +C_O1_I1(R, r) +C_O1_I1(R, R) +C_O1_I2(R, R, R) +C_O1_I2(r, rZ, rJ) +C_O1_I2(R, RZ, RJ) +C_O1_I4(r, rZ, rJ, rI, 0) +C_O1_I4(R, RZ, RJ, RI, 0) +C_O2_I2(r, r, rZ, rJ) +C_O2_I4(R, R, RZ, RZ, RJ, RI) +C_O2_I4(r, r, rZ, rZ, rJ, rJ) diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index f66f5d07dc..f50e8d50ee 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -168,5 +168,6 @@ extern bool use_vis3_instructions; void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CON_SET_H =20 #endif diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index e291eb0b95..3d50f985c6 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -1573,40 +1573,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } } =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; - static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef R_r =3D { .args_ct_str =3D { "R", "r" } }; - static const TCGTargetOpDef r_R =3D { .args_ct_str =3D { "r", "R" } }; - static const TCGTargetOpDef R_R =3D { .args_ct_str =3D { "R", "R" } }; - static const TCGTargetOpDef r_A =3D { .args_ct_str =3D { "r", "A" } }; - static const TCGTargetOpDef R_A =3D { .args_ct_str =3D { "R", "A" } }; - static const TCGTargetOpDef rZ_r =3D { .args_ct_str =3D { "rZ", "r" } = }; - static const TCGTargetOpDef RZ_r =3D { .args_ct_str =3D { "RZ", "r" } = }; - static const TCGTargetOpDef sZ_A =3D { .args_ct_str =3D { "sZ", "A" } = }; - static const TCGTargetOpDef SZ_A =3D { .args_ct_str =3D { "SZ", "A" } = }; - static const TCGTargetOpDef rZ_rJ =3D { .args_ct_str =3D { "rZ", "rJ" = } }; - static const TCGTargetOpDef RZ_RJ =3D { .args_ct_str =3D { "RZ", "RJ" = } }; - static const TCGTargetOpDef R_R_R =3D { .args_ct_str =3D { "R", "R", "= R" } }; - static const TCGTargetOpDef r_rZ_rJ - =3D { .args_ct_str =3D { "r", "rZ", "rJ" } }; - static const TCGTargetOpDef R_RZ_RJ - =3D { .args_ct_str =3D { "R", "RZ", "RJ" } }; - static const TCGTargetOpDef r_r_rZ_rJ - =3D { .args_ct_str =3D { "r", "r", "rZ", "rJ" } }; - static const TCGTargetOpDef movc_32 - =3D { .args_ct_str =3D { "r", "rZ", "rJ", "rI", "0" } }; - static const TCGTargetOpDef movc_64 - =3D { .args_ct_str =3D { "R", "RZ", "RJ", "RI", "0" } }; - static const TCGTargetOpDef add2_32 - =3D { .args_ct_str =3D { "r", "r", "rZ", "rZ", "rJ", "rJ" } }; - static const TCGTargetOpDef add2_64 - =3D { .args_ct_str =3D { "R", "R", "RZ", "RZ", "RJ", "RI" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -1615,12 +1586,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_ld_i32: case INDEX_op_neg_i32: case INDEX_op_not_i32: - return &r_r; + return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: case INDEX_op_st16_i32: case INDEX_op_st_i32: - return &rZ_r; + return C_O0_I2(rZ, r); =20 case INDEX_op_add_i32: case INDEX_op_mul_i32: @@ -1636,18 +1607,18 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_shr_i32: case INDEX_op_sar_i32: case INDEX_op_setcond_i32: - return &r_rZ_rJ; + return C_O1_I2(r, rZ, rJ); =20 case INDEX_op_brcond_i32: - return &rZ_rJ; + return C_O0_I2(rZ, rJ); case INDEX_op_movcond_i32: - return &movc_32; + return C_O1_I4(r, rZ, rJ, rI, 0); case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - return &add2_32; + return C_O2_I4(r, r, rZ, rZ, rJ, rJ); case INDEX_op_mulu2_i32: case INDEX_op_muls2_i32: - return &r_r_rZ_rJ; + return C_O2_I2(r, r, rZ, rJ); =20 case INDEX_op_ld8u_i64: case INDEX_op_ld8s_i64: @@ -1658,13 +1629,13 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_ld_i64: case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: - return &R_r; + return C_O1_I1(R, r); =20 case INDEX_op_st8_i64: case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &RZ_r; + return C_O0_I2(RZ, r); =20 case INDEX_op_add_i64: case INDEX_op_mul_i64: @@ -1680,39 +1651,39 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_shr_i64: case INDEX_op_sar_i64: case INDEX_op_setcond_i64: - return &R_RZ_RJ; + return C_O1_I2(R, RZ, RJ); =20 case INDEX_op_neg_i64: case INDEX_op_not_i64: case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: - return &R_R; + return C_O1_I1(R, R); =20 case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: - return &r_R; + return C_O1_I1(r, R); =20 case INDEX_op_brcond_i64: - return &RZ_RJ; + return C_O0_I2(RZ, RJ); case INDEX_op_movcond_i64: - return &movc_64; + return C_O1_I4(R, RZ, RJ, RI, 0); case INDEX_op_add2_i64: case INDEX_op_sub2_i64: - return &add2_64; + return C_O2_I4(R, R, RZ, RZ, RJ, RI); case INDEX_op_muluh_i64: - return &R_R_R; + return C_O1_I2(R, R, R); =20 case INDEX_op_qemu_ld_i32: - return &r_A; + return C_O1_I1(r, A); case INDEX_op_qemu_ld_i64: - return &R_A; + return C_O1_I1(R, A); case INDEX_op_qemu_st_i32: - return &sZ_A; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id d133sm9247265pfd.6.2021.01.29.12.11.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 12:11:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hhzjN25rBK3kyXshPz5EHgei+RmOJn1cjNGuP7J/ZVU=; b=cnNpAD3clItwBRrIrG/1MdsWCZqNeY2xrwR+DAvDMZMszHEAXKXma3wvACPDkBBP1n ClnEuZysOXPiuyZv/xfmMYdXrcTHmP34TvSuNe+V2cdLuplUMaEIzevP6CQ+vtrHnvPn YTcaBjunvU4IZAhDzy1k/kKDfmntQMcq1AYHnu6fg2uGD//IfDTF1YdW6tF0wepmNeSS broYWFuSwE2VxrSHtRhDZpotc3C828tqrITMlVUw59PsrIepLGDSmW7hJB3hoU2J3vOS M+ZbhEnWLrRTHuWPyOg7y0njv9Zq8GJrKxllr4m1O+DwgEV8/aXitIBfKlHxgkuFaaxd FRjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hhzjN25rBK3kyXshPz5EHgei+RmOJn1cjNGuP7J/ZVU=; b=bRDCGinAzP5ydH9iHy1WEb4SCuB5TdD4HJMTELswVDnh7V0Lq/oGDZYwnxjjkGL/Gc 02go2tTiEpdNLzK5Drzlf1x9I8kSNZ/nIcVxH1gFI918WJ/zasOTRQ2Z8wzRB7iXqhjs jBjLUKWnEJCsXd/44QSLHdYhjXZPrEcDDQhi9wvDK9SsBC2YxbbW2hhODGYgmVM7qYx0 8/cEpezX82JmL4mF5pc4dyAW+662tQYslgwhmFI3YIQ+CgpXJiBfgiuVwthlzPCetAz/ 34IUWuNS29Hr2+zpG6760JV7YjB8Ic4Tru6vgqn9tBQCa04k7RyEGsy03j+h4a5ogQfk 04bA== X-Gm-Message-State: AOAM533XbtRT/K9wD7cxYf0+T4Ywurt+x7OjfLKxJvbnWqLI5juBP20K lwYmEpG4gDMzrNW1Z1qaRcALCe1x20hVCLMV X-Google-Smtp-Source: ABdhPJw/v24o10PR0Jw5/681TKDVr7jIwloX8Tyg9TPKnFQdzg4KrciXyRlaysclm/ZUaxcs/nlyMw== X-Received: by 2002:a62:5344:0:b029:1c7:eeea:8bad with SMTP id h65-20020a6253440000b02901c7eeea8badmr5857071pfb.1.1611951069112; Fri, 29 Jan 2021 12:11:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 23/24] tcg/tci: Split out constraint sets to tcg-target-con-set.h Date: Fri, 29 Jan 2021 10:10:27 -1000 Message-Id: <20210129201028.787853-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129201028.787853-1-richard.henderson@linaro.org> References: <20210129201028.787853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This requires finishing the conversion to tcg_target_op_def. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/tci/tcg-target-con-set.h | 25 ++++ tcg/tci/tcg-target.h | 2 + tcg/tci/tcg-target.c.inc | 279 +++++++++++++++++------------------ 3 files changed, 161 insertions(+), 145 deletions(-) create mode 100644 tcg/tci/tcg-target-con-set.h diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h new file mode 100644 index 0000000000..38e82f7535 --- /dev/null +++ b/tcg/tci/tcg-target-con-set.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ +/* + * TCI target-specific constraint sets. + * Copyright (c) 2021 Linaro + */ + +/* + * C_On_Im(...) defines a constraint set with outputs and inputs. + * Each operand should be a sequence of constraint letters as defined by + * tcg-target-con-str.h; the constraint combination is inclusive or. + */ +C_O0_I2(r, r) +C_O0_I2(r, ri) +C_O0_I3(r, r, r) +C_O0_I4(r, r, ri, ri) +C_O0_I4(r, r, r, r) +C_O1_I1(r, r) +C_O1_I2(r, 0, r) +C_O1_I2(r, ri, ri) +C_O1_I2(r, r, r) +C_O1_I2(r, r, ri) +C_O1_I4(r, r, r, ri, ri) +C_O2_I1(r, r, r) +C_O2_I2(r, r, r, r) +C_O2_I4(r, r, r, r, r, r) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index bb784e018e..1efd8c4fb0 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -207,4 +207,6 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, uintptr_t jmp_rx, /* no need to flush icache explicitly */ } =20 +#define TCG_TARGET_CON_SET_H + #endif /* TCG_TARGET_H */ diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 493bbf1e39..62bedaca28 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -37,154 +37,143 @@ /* Bitfield n...m (in 32 bit value). */ #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) =20 -/* Macros used in tcg_target_op_defs. */ -#define R "r" -#define RI "ri" -#if TCG_TARGET_REG_BITS =3D=3D 32 -# define R64 "r", "r" -#else -# define R64 "r" -#endif -#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS -# define L "r", "r" -# define S "r", "r" -#else -# define L "r" -# define S "r" -#endif - -/* TODO: documentation. */ -static const TCGTargetOpDef tcg_target_op_defs[] =3D { - { INDEX_op_exit_tb, { NULL } }, - { INDEX_op_goto_tb, { NULL } }, - { INDEX_op_br, { NULL } }, - - { INDEX_op_ld8u_i32, { R, R } }, - { INDEX_op_ld8s_i32, { R, R } }, - { INDEX_op_ld16u_i32, { R, R } }, - { INDEX_op_ld16s_i32, { R, R } }, - { INDEX_op_ld_i32, { R, R } }, - { INDEX_op_st8_i32, { R, R } }, - { INDEX_op_st16_i32, { R, R } }, - { INDEX_op_st_i32, { R, R } }, - - { INDEX_op_add_i32, { R, RI, RI } }, - { INDEX_op_sub_i32, { R, RI, RI } }, - { INDEX_op_mul_i32, { R, RI, RI } }, - { INDEX_op_div_i32, { R, R, R } }, - { INDEX_op_divu_i32, { R, R, R } }, - { INDEX_op_rem_i32, { R, R, R } }, - { INDEX_op_remu_i32, { R, R, R } }, - /* TODO: Does R, RI, RI result in faster code than R, R, RI? - If both operands are constants, we can optimize. */ - { INDEX_op_and_i32, { R, RI, RI } }, - { INDEX_op_andc_i32, { R, RI, RI } }, - { INDEX_op_eqv_i32, { R, RI, RI } }, - { INDEX_op_nand_i32, { R, RI, RI } }, - { INDEX_op_nor_i32, { R, RI, RI } }, - { INDEX_op_or_i32, { R, RI, RI } }, - { INDEX_op_orc_i32, { R, RI, RI } }, - { INDEX_op_xor_i32, { R, RI, RI } }, - { INDEX_op_shl_i32, { R, RI, RI } }, - { INDEX_op_shr_i32, { R, RI, RI } }, - { INDEX_op_sar_i32, { R, RI, RI } }, - { INDEX_op_rotl_i32, { R, RI, RI } }, - { INDEX_op_rotr_i32, { R, RI, RI } }, - { INDEX_op_deposit_i32, { R, "0", R } }, - - { INDEX_op_brcond_i32, { R, RI } }, - - { INDEX_op_setcond_i32, { R, R, RI } }, - { INDEX_op_setcond_i64, { R, R, RI } }, - - /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */ - { INDEX_op_add2_i32, { R, R, R, R, R, R } }, - { INDEX_op_sub2_i32, { R, R, R, R, R, R } }, - { INDEX_op_brcond2_i32, { R, R, RI, RI } }, - { INDEX_op_mulu2_i32, { R, R, R, R } }, - { INDEX_op_setcond2_i32, { R, R, R, RI, RI } }, - - { INDEX_op_not_i32, { R, R } }, - { INDEX_op_neg_i32, { R, R } }, - - { INDEX_op_ld8u_i64, { R, R } }, - { INDEX_op_ld8s_i64, { R, R } }, - { INDEX_op_ld16u_i64, { R, R } }, - { INDEX_op_ld16s_i64, { R, R } }, - { INDEX_op_ld32u_i64, { R, R } }, - { INDEX_op_ld32s_i64, { R, R } }, - { INDEX_op_ld_i64, { R, R } }, - - { INDEX_op_st8_i64, { R, R } }, - { INDEX_op_st16_i64, { R, R } }, - { INDEX_op_st32_i64, { R, R } }, - { INDEX_op_st_i64, { R, R } }, - - { INDEX_op_add_i64, { R, RI, RI } }, - { INDEX_op_sub_i64, { R, RI, RI } }, - { INDEX_op_mul_i64, { R, RI, RI } }, - { INDEX_op_div_i64, { R, R, R } }, - { INDEX_op_divu_i64, { R, R, R } }, - { INDEX_op_rem_i64, { R, R, R } }, - { INDEX_op_remu_i64, { R, R, R } }, - { INDEX_op_and_i64, { R, RI, RI } }, - { INDEX_op_andc_i64, { R, RI, RI } }, - { INDEX_op_eqv_i64, { R, RI, RI } }, - { INDEX_op_nand_i64, { R, RI, RI } }, - { INDEX_op_nor_i64, { R, RI, RI } }, - { INDEX_op_or_i64, { R, RI, RI } }, - { INDEX_op_orc_i64, { R, RI, RI } }, - { INDEX_op_xor_i64, { R, RI, RI } }, - { INDEX_op_shl_i64, { R, RI, RI } }, - { INDEX_op_shr_i64, { R, RI, RI } }, - { INDEX_op_sar_i64, { R, RI, RI } }, - { INDEX_op_rotl_i64, { R, RI, RI } }, - { INDEX_op_rotr_i64, { R, RI, RI } }, - { INDEX_op_deposit_i64, { R, "0", R } }, - { INDEX_op_brcond_i64, { R, RI } }, - - { INDEX_op_ext8s_i64, { R, R } }, - { INDEX_op_ext16s_i64, { R, R } }, - { INDEX_op_ext32s_i64, { R, R } }, - { INDEX_op_ext8u_i64, { R, R } }, - { INDEX_op_ext16u_i64, { R, R } }, - { INDEX_op_ext32u_i64, { R, R } }, - { INDEX_op_ext_i32_i64, { R, R } }, - { INDEX_op_extu_i32_i64, { R, R } }, - { INDEX_op_bswap16_i64, { R, R } }, - { INDEX_op_bswap32_i64, { R, R } }, - { INDEX_op_bswap64_i64, { R, R } }, - { INDEX_op_not_i64, { R, R } }, - { INDEX_op_neg_i64, { R, R } }, - - { INDEX_op_qemu_ld_i32, { R, L } }, - { INDEX_op_qemu_ld_i64, { R64, L } }, - - { INDEX_op_qemu_st_i32, { R, S } }, - { INDEX_op_qemu_st_i64, { R64, S } }, - - { INDEX_op_ext8s_i32, { R, R } }, - { INDEX_op_ext16s_i32, { R, R } }, - { INDEX_op_ext8u_i32, { R, R } }, - { INDEX_op_ext16u_i32, { R, R } }, - - { INDEX_op_bswap16_i32, { R, R } }, - { INDEX_op_bswap32_i32, { R, R } }, - - { INDEX_op_mb, { } }, - { -1 }, -}; - -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { - int i, n =3D ARRAY_SIZE(tcg_target_op_defs); + switch (op) { + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_not_i32: + case INDEX_op_not_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + return C_O1_I1(r, r); =20 - for (i =3D 0; i < n; ++i) { - if (tcg_target_op_defs[i].op =3D=3D op) { - return &tcg_target_op_defs[i]; - } + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return C_O0_I2(r, r); + + case INDEX_op_div_i32: + case INDEX_op_div_i64: + case INDEX_op_divu_i32: + case INDEX_op_divu_i64: + case INDEX_op_rem_i32: + case INDEX_op_rem_i64: + case INDEX_op_remu_i32: + case INDEX_op_remu_i64: + return C_O1_I2(r, r, r); + + case INDEX_op_add_i32: + case INDEX_op_add_i64: + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + case INDEX_op_and_i32: + case INDEX_op_and_i64: + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + case INDEX_op_eqv_i32: + case INDEX_op_eqv_i64: + case INDEX_op_nand_i32: + case INDEX_op_nand_i64: + case INDEX_op_nor_i32: + case INDEX_op_nor_i64: + case INDEX_op_or_i32: + case INDEX_op_or_i64: + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + case INDEX_op_shl_i32: + case INDEX_op_shl_i64: + case INDEX_op_shr_i32: + case INDEX_op_shr_i64: + case INDEX_op_sar_i32: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + /* TODO: Does R, RI, RI result in faster code than R, R, RI? */ + return C_O1_I2(r, ri, ri); + + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + return C_O1_I2(r, 0, r); + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + return C_O0_I2(r, ri); + + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + return C_O1_I2(r, r, ri); + +#if TCG_TARGET_REG_BITS =3D=3D 32 + /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */ + case INDEX_op_add2_i32: + case INDEX_op_sub2_i32: + return C_O2_I4(r, r, r, r, r, r); + case INDEX_op_brcond2_i32: + return C_O0_I4(r, r, ri, ri); + case INDEX_op_mulu2_i32: + return C_O2_I2(r, r, r, r); + case INDEX_op_setcond2_i32 + return C_O1_I4(r, r, r, ri, ri); +#endif + + case INDEX_op_qemu_ld_i32: + return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS + ? C_O1_I1(r, r) + : C_O1_I2(r, r, r)); + case INDEX_op_qemu_ld_i64: + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) + : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O2_I1(r, r= , r) + : C_O2_I2(r, r, r, r)); + case INDEX_op_qemu_st_i32: + return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS + ? C_O0_I2(r, r) + : C_O0_I3(r, r, r)); + case INDEX_op_qemu_st_i64: + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(r, r) + : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O0_I3(r, r= , r) + : C_O0_I4(r, r, r, r)); + + default: + g_assert_not_reached(); } - return NULL; } =20 static const int tcg_target_reg_alloc_order[] =3D { --=20 2.25.1 From nobody Thu Nov 14 06:52:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1611952425; cv=none; d=zohomail.com; s=zohoarc; b=K3WiZEnluujDHYj2UT8VM/gEqaukmCeLj+ihdFEP0ZUxNW0D3m05iavyYvad9zijkaEzlbZUfJt+BtSzlWtAAcRmfikz8Cg40vFX6kYQDLvCrbuW3KvXNp753zOud1+pJ+dHEhIAS37G49vjKvnT1qHnkJEmCAWkALYlXU7REfI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611952425; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Y1lw80f1qkFn4X3t7T1lgV932l1h1eTxnNcDp/G7l10=; b=bjLBoinvikl6T9se/v7fsmDplAob4OUSbSK5P+6zP+gotzQ7tNpoiNVHNVQA5qDEqrD41ypC5NoL8R/FHl9deK0Z9ERigkLu1fJbgL2RNlfTQAuhQPC4EfWD1/x8zQ7P0r2YhDRWHFVp1zDZjF9HPlGhVo9Tu86BblmWlKDdQck= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161195242515468.80373356365487; Fri, 29 Jan 2021 12:33:45 -0800 (PST) Received: from localhost ([::1]:42444 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l5aSd-0007Fc-4P for importer@patchew.org; Fri, 29 Jan 2021 15:33:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49366) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5a6s-0007ER-A6 for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:11:14 -0500 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:42976) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5a6q-0008En-9L for qemu-devel@nongnu.org; Fri, 29 Jan 2021 15:11:14 -0500 Received: by mail-pg1-x531.google.com with SMTP id g15so7404405pgu.9 for ; Fri, 29 Jan 2021 12:11:11 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id d133sm9247265pfd.6.2021.01.29.12.11.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 12:11:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y1lw80f1qkFn4X3t7T1lgV932l1h1eTxnNcDp/G7l10=; b=nJmSouER6cNH4iHcoTCn+ZZjMCNUV191PmKleFP8GpEqQ4g0mA8WYWI//Mc1YGA4gX KGZfrPgToycN8k4pGK2mXzIs4cr0DrTMmd1xwDmNckLSfVfpdtw6UAjiw9CYLspeRWcY nRUsVcWoomv0Qy3SMUx13rHAVRhw2xKq+svLFu0/qKfV6dB/erUtiI5FG5/yU+fyR1Un e8xG25ioutlNY2II75iq3vvESnBRWc1tgE/lDTKkxJPr8YfnQy7aHg7HyBPssoCzD3rR GORPNkPhOepzKkeGP7Az7rZu4VXWUVU2BYvbqT5c0ajF2YVYpqJUkEcfMOtu+FJJlmPv lHIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y1lw80f1qkFn4X3t7T1lgV932l1h1eTxnNcDp/G7l10=; b=XGFi3VhHbS/u4VLitxbjaGVjQXe9BwqCwkD/HW2neoeefQ6k+qvUoOYni2Ma7wuCKL FQTYKyxtECKHnodeGhIuzwRwrbsBY2F6SKhRhi9yjusl8rv/g0snKje+laAfJ7kWtF4f DbbyCMKnyB6rt8C4pIR4UMkk9twSY6zUikXmREvqiQxL7t+FeRfiOr+ePCcdGXD1X6Fr Y6ctsTNL3ECX6OmIGnjU0Wp/FPfoeBYSrEXqTnQnS+uoDdsQvnkKFMaUOJlZEZ3SYEKD Aolrenx9OoqqD497RbXV/INTG62HG2MBT1tktrCHg3X8slX2MrWBtuQT5QsNijlMvMFu skUA== X-Gm-Message-State: AOAM531T7LvVgOt4Qk4crW5flBUvNDF2OSjeh/k8wz6pMDl7yDuVEmvA pOb/CKNg2dTHYjBR0rAzodnLBGaytF/8CJv5 X-Google-Smtp-Source: ABdhPJyC4C7Zq/1on4LBKr6cXqaRK6T0lWrSJL9vowteBwz8Z/fPlIyn6u8R8T9kzEc4uNifXVjdkA== X-Received: by 2002:a62:ae0c:0:b029:1bc:a0b9:f0aa with SMTP id q12-20020a62ae0c0000b02901bca0b9f0aamr5799665pff.78.1611951070892; Fri, 29 Jan 2021 12:11:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 24/24] tcg: Remove TCG_TARGET_CON_SET_H Date: Fri, 29 Jan 2021 10:10:28 -1000 Message-Id: <20210129201028.787853-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129201028.787853-1-richard.henderson@linaro.org> References: <20210129201028.787853-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" All backends have now been converted to tcg-target-con-set.h, so we can remove the fallback code. Reviewed-by: Peter Maydell Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 - tcg/arm/tcg-target.h | 1 - tcg/i386/tcg-target.h | 1 - tcg/mips/tcg-target.h | 1 - tcg/ppc/tcg-target.h | 1 - tcg/riscv/tcg-target.h | 1 - tcg/s390/tcg-target.h | 1 - tcg/sparc/tcg-target.h | 1 - tcg/tci/tcg-target.h | 2 -- tcg/tcg.c | 12 ------------ 10 files changed, 22 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 200e9b5e0e..5ec30dba25 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -155,6 +155,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CON_SET_H =20 #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 4d201b1216..8d1fee6327 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -142,6 +142,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CON_SET_H =20 #endif diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 48a6f2a336..b693d3692d 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -235,6 +235,5 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CON_SET_H =20 #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index e520a9d6e3..c2c32fb38f 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -207,6 +207,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif -#define TCG_TARGET_CON_SET_H =20 #endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 551f8d0fc9..d1339afc66 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -185,6 +185,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CON_SET_H =20 #endif diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index a998b951e4..727c8df418 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -171,6 +171,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 0 -#define TCG_TARGET_CON_SET_H =20 #endif diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 7aafd25a46..641464eea4 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -159,6 +159,5 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CON_SET_H =20 #endif diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index f50e8d50ee..f66f5d07dc 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -168,6 +168,5 @@ extern bool use_vis3_instructions; void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CON_SET_H =20 #endif diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 1efd8c4fb0..bb784e018e 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -207,6 +207,4 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, uintptr_t jmp_rx, /* no need to flush icache explicitly */ } =20 -#define TCG_TARGET_CON_SET_H - #endif /* TCG_TARGET_H */ diff --git a/tcg/tcg.c b/tcg/tcg.c index df9f32763e..63a12b197b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -69,9 +69,6 @@ /* Forward declarations for functions declared in tcg-target.c.inc and used here. */ static void tcg_target_init(TCGContext *s); -#ifndef TCG_TARGET_CON_SET_H -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode); -#endif static void tcg_target_qemu_prologue(TCGContext *s); static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend); @@ -349,7 +346,6 @@ static void set_jmp_reset_offset(TCGContext *s, int whi= ch) s->tb_jmp_reset_offset[which] =3D tcg_current_code_size(s); } =20 -#ifdef TCG_TARGET_CON_SET_H #define C_PFX1(P, A) P##A #define C_PFX2(P, A, B) P##A##_##B #define C_PFX3(P, A, B, C) P##A##_##B##_##C @@ -453,8 +449,6 @@ static const TCGTargetOpDef constraint_sets[] =3D { #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I= 3) #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I= 3, I4) =20 -#endif /* TCG_TARGET_CON_SET_H */ - #include "tcg-target.c.inc" =20 /* compare a pointer @ptr and a tb_tc @s */ @@ -2532,7 +2526,6 @@ static void process_op_defs(TCGContext *s) continue; } =20 -#ifdef TCG_TARGET_CON_SET_H /* * Macro magic should make it impossible, but double-check that * the array index is in range. Since the signness of an enum @@ -2541,11 +2534,6 @@ static void process_op_defs(TCGContext *s) unsigned con_set =3D tcg_target_op_def(op); tcg_debug_assert(con_set < ARRAY_SIZE(constraint_sets)); tdefs =3D &constraint_sets[con_set]; -#else - tdefs =3D tcg_target_op_def(op); - /* Missing TCGTargetOpDef entry. */ - tcg_debug_assert(tdefs !=3D NULL); -#endif =20 for (i =3D 0; i < nb_args; i++) { const char *ct_str =3D tdefs->args_ct_str[i]; --=20 2.25.1